| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
| 96.03 | 95.47 | 93.71 | 95.35 | 94.54 | 97.53 | 99.57 |
| T2762 | /workspace/coverage/cover_reg_top/97.xbar_stress_all_with_error.126443420 | Aug 12 06:59:18 PM PDT 24 | Aug 12 07:00:59 PM PDT 24 | 2715763418 ps | ||
| T2763 | /workspace/coverage/cover_reg_top/65.xbar_random_slow_rsp.873585120 | Aug 12 06:55:13 PM PDT 24 | Aug 12 07:11:14 PM PDT 24 | 52267346490 ps | ||
| T2764 | /workspace/coverage/cover_reg_top/20.xbar_unmapped_addr.410777849 | Aug 12 06:48:54 PM PDT 24 | Aug 12 06:49:21 PM PDT 24 | 202059888 ps | ||
| T2765 | /workspace/coverage/cover_reg_top/31.xbar_smoke_slow_rsp.974995192 | Aug 12 06:50:26 PM PDT 24 | Aug 12 06:51:44 PM PDT 24 | 4510001416 ps | ||
| T2766 | /workspace/coverage/cover_reg_top/76.xbar_access_same_device.2032324629 | Aug 12 06:56:39 PM PDT 24 | Aug 12 06:58:13 PM PDT 24 | 2204355038 ps | ||
| T2767 | /workspace/coverage/cover_reg_top/1.chip_csr_rw.2502851806 | Aug 12 06:47:06 PM PDT 24 | Aug 12 06:52:29 PM PDT 24 | 4122555470 ps | ||
| T2768 | /workspace/coverage/cover_reg_top/13.xbar_smoke.243857282 | Aug 12 06:47:46 PM PDT 24 | Aug 12 06:47:56 PM PDT 24 | 254193116 ps | ||
| T2769 | /workspace/coverage/cover_reg_top/42.xbar_stress_all_with_rand_reset.2563791826 | Aug 12 06:52:05 PM PDT 24 | Aug 12 06:59:28 PM PDT 24 | 2358006869 ps | ||
| T2770 | /workspace/coverage/cover_reg_top/75.xbar_random_large_delays.1308603037 | Aug 12 06:56:29 PM PDT 24 | Aug 12 06:57:55 PM PDT 24 | 8137159925 ps | ||
| T2771 | /workspace/coverage/cover_reg_top/17.xbar_random_slow_rsp.2471672839 | Aug 12 06:48:29 PM PDT 24 | Aug 12 06:55:59 PM PDT 24 | 26072196718 ps | ||
| T2772 | /workspace/coverage/cover_reg_top/75.xbar_unmapped_addr.1049836755 | Aug 12 06:56:28 PM PDT 24 | Aug 12 06:57:06 PM PDT 24 | 810203749 ps | ||
| T2773 | /workspace/coverage/cover_reg_top/1.xbar_error_and_unmapped_addr.4199260794 | Aug 12 06:47:13 PM PDT 24 | Aug 12 06:47:50 PM PDT 24 | 972617059 ps | ||
| T2774 | /workspace/coverage/cover_reg_top/70.xbar_stress_all.441507658 | Aug 12 06:55:54 PM PDT 24 | Aug 12 06:56:49 PM PDT 24 | 1509241490 ps | ||
| T2775 | /workspace/coverage/cover_reg_top/70.xbar_stress_all_with_rand_reset.2467916990 | Aug 12 06:55:51 PM PDT 24 | Aug 12 06:57:44 PM PDT 24 | 273399675 ps | ||
| T2776 | /workspace/coverage/cover_reg_top/8.xbar_random.3453276571 | Aug 12 06:47:35 PM PDT 24 | Aug 12 06:47:48 PM PDT 24 | 229361668 ps | ||
| T2777 | /workspace/coverage/cover_reg_top/22.xbar_smoke.3405931094 | Aug 12 06:49:05 PM PDT 24 | Aug 12 06:49:15 PM PDT 24 | 259213827 ps | ||
| T2778 | /workspace/coverage/cover_reg_top/95.xbar_access_same_device_slow_rsp.3000282021 | Aug 12 06:59:04 PM PDT 24 | Aug 12 07:32:50 PM PDT 24 | 115932731993 ps | ||
| T2779 | /workspace/coverage/cover_reg_top/95.xbar_random.2207775735 | Aug 12 06:59:00 PM PDT 24 | Aug 12 07:00:04 PM PDT 24 | 1919583127 ps | ||
| T2780 | /workspace/coverage/cover_reg_top/76.xbar_error_and_unmapped_addr.2075003232 | Aug 12 06:56:46 PM PDT 24 | Aug 12 06:57:32 PM PDT 24 | 1038351363 ps | ||
| T2781 | /workspace/coverage/cover_reg_top/6.chip_csr_rw.3671750004 | Aug 12 06:47:41 PM PDT 24 | Aug 12 06:52:03 PM PDT 24 | 3570966446 ps | ||
| T2782 | /workspace/coverage/cover_reg_top/82.xbar_access_same_device_slow_rsp.1376517821 | Aug 12 06:57:22 PM PDT 24 | Aug 12 07:37:31 PM PDT 24 | 128348443759 ps | ||
| T2783 | /workspace/coverage/cover_reg_top/7.xbar_stress_all.1160560302 | Aug 12 06:47:42 PM PDT 24 | Aug 12 06:56:30 PM PDT 24 | 15343272385 ps | ||
| T2784 | /workspace/coverage/cover_reg_top/19.xbar_access_same_device.2722552142 | Aug 12 06:48:48 PM PDT 24 | Aug 12 06:49:36 PM PDT 24 | 671823909 ps | ||
| T2785 | /workspace/coverage/cover_reg_top/61.xbar_stress_all_with_reset_error.1447347555 | Aug 12 06:54:48 PM PDT 24 | Aug 12 06:57:24 PM PDT 24 | 360473762 ps | ||
| T2786 | /workspace/coverage/cover_reg_top/10.xbar_smoke.1532330106 | Aug 12 06:47:40 PM PDT 24 | Aug 12 06:47:46 PM PDT 24 | 42569511 ps | ||
| T2787 | /workspace/coverage/cover_reg_top/56.xbar_same_source.2031870624 | Aug 12 06:54:10 PM PDT 24 | Aug 12 06:54:47 PM PDT 24 | 535012922 ps | ||
| T2788 | /workspace/coverage/cover_reg_top/51.xbar_stress_all_with_rand_reset.3714298256 | Aug 12 06:53:21 PM PDT 24 | Aug 12 06:54:50 PM PDT 24 | 235039552 ps | ||
| T2789 | /workspace/coverage/cover_reg_top/47.xbar_stress_all_with_rand_reset.713387230 | Aug 12 06:52:58 PM PDT 24 | Aug 12 06:57:54 PM PDT 24 | 4383554930 ps | ||
| T2790 | /workspace/coverage/cover_reg_top/92.xbar_smoke_large_delays.3657856785 | Aug 12 06:58:27 PM PDT 24 | Aug 12 06:59:55 PM PDT 24 | 8606060319 ps | ||
| T2791 | /workspace/coverage/cover_reg_top/90.xbar_random.3378675874 | Aug 12 06:58:18 PM PDT 24 | Aug 12 06:58:47 PM PDT 24 | 349934026 ps | ||
| T2792 | /workspace/coverage/cover_reg_top/18.xbar_smoke_slow_rsp.3058083897 | Aug 12 06:48:40 PM PDT 24 | Aug 12 06:50:12 PM PDT 24 | 6198738918 ps | ||
| T2793 | /workspace/coverage/cover_reg_top/14.xbar_random_large_delays.3464834577 | Aug 12 06:48:05 PM PDT 24 | Aug 12 06:59:31 PM PDT 24 | 70703907626 ps | ||
| T2794 | /workspace/coverage/cover_reg_top/17.xbar_random.1866518130 | Aug 12 06:48:28 PM PDT 24 | Aug 12 06:48:36 PM PDT 24 | 131411124 ps | ||
| T2795 | /workspace/coverage/cover_reg_top/86.xbar_access_same_device_slow_rsp.1184658826 | Aug 12 06:57:52 PM PDT 24 | Aug 12 07:06:20 PM PDT 24 | 30407422634 ps | ||
| T2796 | /workspace/coverage/cover_reg_top/4.chip_tl_errors.472443995 | Aug 12 06:47:17 PM PDT 24 | Aug 12 06:54:05 PM PDT 24 | 3785360100 ps | ||
| T2797 | /workspace/coverage/cover_reg_top/79.xbar_smoke.426212051 | Aug 12 06:56:49 PM PDT 24 | Aug 12 06:56:58 PM PDT 24 | 200727019 ps | ||
| T2798 | /workspace/coverage/cover_reg_top/40.xbar_random_slow_rsp.1750396710 | Aug 12 06:51:59 PM PDT 24 | Aug 12 06:58:51 PM PDT 24 | 24493899219 ps | ||
| T2799 | /workspace/coverage/cover_reg_top/97.xbar_random_zero_delays.1003876105 | Aug 12 06:59:11 PM PDT 24 | Aug 12 07:00:00 PM PDT 24 | 559231585 ps | ||
| T2800 | /workspace/coverage/cover_reg_top/55.xbar_smoke.2955229364 | Aug 12 06:53:58 PM PDT 24 | Aug 12 06:54:08 PM PDT 24 | 235115932 ps | ||
| T2801 | /workspace/coverage/cover_reg_top/26.xbar_stress_all_with_error.2286169363 | Aug 12 06:49:55 PM PDT 24 | Aug 12 06:50:45 PM PDT 24 | 1717130554 ps | ||
| T2802 | /workspace/coverage/cover_reg_top/70.xbar_access_same_device.4260652401 | Aug 12 06:55:49 PM PDT 24 | Aug 12 06:56:46 PM PDT 24 | 1567301881 ps | ||
| T2803 | /workspace/coverage/cover_reg_top/9.xbar_stress_all_with_rand_reset.3375405871 | Aug 12 06:47:39 PM PDT 24 | Aug 12 06:50:44 PM PDT 24 | 462010128 ps | ||
| T2804 | /workspace/coverage/cover_reg_top/38.xbar_smoke_slow_rsp.1078383764 | Aug 12 06:51:42 PM PDT 24 | Aug 12 06:53:10 PM PDT 24 | 5556464360 ps | ||
| T2805 | /workspace/coverage/cover_reg_top/93.xbar_same_source.4279219644 | Aug 12 06:58:56 PM PDT 24 | Aug 12 06:59:54 PM PDT 24 | 2016221502 ps | ||
| T2806 | /workspace/coverage/cover_reg_top/60.xbar_same_source.479427843 | Aug 12 06:54:35 PM PDT 24 | Aug 12 06:55:42 PM PDT 24 | 2330134603 ps | ||
| T2807 | /workspace/coverage/cover_reg_top/21.xbar_stress_all.2160436208 | Aug 12 06:49:01 PM PDT 24 | Aug 12 06:50:36 PM PDT 24 | 3266693958 ps | ||
| T2808 | /workspace/coverage/cover_reg_top/67.xbar_random_zero_delays.4192521233 | Aug 12 06:55:29 PM PDT 24 | Aug 12 06:55:43 PM PDT 24 | 135826906 ps | ||
| T2809 | /workspace/coverage/cover_reg_top/55.xbar_smoke_slow_rsp.958381494 | Aug 12 06:53:59 PM PDT 24 | Aug 12 06:55:31 PM PDT 24 | 5587378158 ps | ||
| T2810 | /workspace/coverage/cover_reg_top/55.xbar_stress_all_with_reset_error.84178249 | Aug 12 06:54:10 PM PDT 24 | Aug 12 06:56:11 PM PDT 24 | 516628999 ps | ||
| T2811 | /workspace/coverage/cover_reg_top/6.xbar_error_and_unmapped_addr.3856874173 | Aug 12 06:47:41 PM PDT 24 | Aug 12 06:47:51 PM PDT 24 | 92054626 ps | ||
| T2812 | /workspace/coverage/cover_reg_top/37.xbar_random_zero_delays.1812673255 | Aug 12 06:51:37 PM PDT 24 | Aug 12 06:52:17 PM PDT 24 | 473684279 ps | ||
| T2813 | /workspace/coverage/cover_reg_top/61.xbar_random_slow_rsp.1393180507 | Aug 12 06:54:44 PM PDT 24 | Aug 12 07:01:35 PM PDT 24 | 24477582028 ps | ||
| T2814 | /workspace/coverage/cover_reg_top/13.xbar_stress_all_with_rand_reset.3505681939 | Aug 12 06:48:12 PM PDT 24 | Aug 12 06:48:27 PM PDT 24 | 24946174 ps | ||
| T2815 | /workspace/coverage/cover_reg_top/88.xbar_access_same_device_slow_rsp.293303318 | Aug 12 06:58:01 PM PDT 24 | Aug 12 07:35:34 PM PDT 24 | 137267021810 ps | ||
| T2816 | /workspace/coverage/cover_reg_top/63.xbar_access_same_device_slow_rsp.550122465 | Aug 12 06:55:04 PM PDT 24 | Aug 12 07:32:51 PM PDT 24 | 117997210069 ps | ||
| T2817 | /workspace/coverage/cover_reg_top/74.xbar_random_large_delays.329570101 | Aug 12 06:56:19 PM PDT 24 | Aug 12 07:14:22 PM PDT 24 | 101931125498 ps | ||
| T2818 | /workspace/coverage/cover_reg_top/99.xbar_stress_all.3623104949 | Aug 12 06:59:27 PM PDT 24 | Aug 12 07:02:27 PM PDT 24 | 1995944218 ps | ||
| T2819 | /workspace/coverage/cover_reg_top/67.xbar_unmapped_addr.751510825 | Aug 12 06:55:31 PM PDT 24 | Aug 12 06:56:16 PM PDT 24 | 1099672733 ps | ||
| T2820 | /workspace/coverage/cover_reg_top/45.xbar_access_same_device_slow_rsp.3054858200 | Aug 12 06:52:40 PM PDT 24 | Aug 12 07:26:31 PM PDT 24 | 115069032381 ps | ||
| T2821 | /workspace/coverage/cover_reg_top/90.xbar_error_random.1503814674 | Aug 12 06:58:18 PM PDT 24 | Aug 12 06:58:40 PM PDT 24 | 643719431 ps | ||
| T2822 | /workspace/coverage/cover_reg_top/42.xbar_stress_all_with_error.2098004543 | Aug 12 06:52:03 PM PDT 24 | Aug 12 06:55:26 PM PDT 24 | 6154272370 ps | ||
| T2823 | /workspace/coverage/cover_reg_top/78.xbar_random.1817786879 | Aug 12 06:56:49 PM PDT 24 | Aug 12 06:57:09 PM PDT 24 | 461711285 ps | ||
| T2824 | /workspace/coverage/cover_reg_top/52.xbar_error_random.851518845 | Aug 12 06:53:29 PM PDT 24 | Aug 12 06:53:54 PM PDT 24 | 724381590 ps | ||
| T2825 | /workspace/coverage/cover_reg_top/44.xbar_access_same_device_slow_rsp.979555274 | Aug 12 06:52:31 PM PDT 24 | Aug 12 07:11:45 PM PDT 24 | 64959612453 ps | ||
| T2826 | /workspace/coverage/cover_reg_top/81.xbar_stress_all_with_rand_reset.3973314936 | Aug 12 06:57:12 PM PDT 24 | Aug 12 07:09:52 PM PDT 24 | 6041265958 ps | ||
| T2827 | /workspace/coverage/cover_reg_top/1.xbar_random_slow_rsp.98629034 | Aug 12 06:47:16 PM PDT 24 | Aug 12 06:55:39 PM PDT 24 | 31319670745 ps | ||
| T2828 | /workspace/coverage/cover_reg_top/62.xbar_smoke.738880242 | Aug 12 06:54:52 PM PDT 24 | Aug 12 06:54:58 PM PDT 24 | 36240550 ps | ||
| T2829 | /workspace/coverage/cover_reg_top/37.xbar_error_and_unmapped_addr.66396873 | Aug 12 06:51:42 PM PDT 24 | Aug 12 06:52:05 PM PDT 24 | 209504427 ps | ||
| T2830 | /workspace/coverage/cover_reg_top/0.xbar_stress_all_with_error.2597837580 | Aug 12 06:47:07 PM PDT 24 | Aug 12 06:53:18 PM PDT 24 | 11198565015 ps | ||
| T2831 | /workspace/coverage/cover_reg_top/80.xbar_smoke_large_delays.1095388215 | Aug 12 06:57:00 PM PDT 24 | Aug 12 06:58:23 PM PDT 24 | 8727953490 ps | ||
| T2832 | /workspace/coverage/cover_reg_top/23.xbar_access_same_device_slow_rsp.1160647879 | Aug 12 06:49:19 PM PDT 24 | Aug 12 07:31:23 PM PDT 24 | 133052255776 ps | ||
| T2833 | /workspace/coverage/cover_reg_top/27.xbar_stress_all_with_rand_reset.3269333242 | Aug 12 06:50:02 PM PDT 24 | Aug 12 06:53:28 PM PDT 24 | 758813468 ps | ||
| T2834 | /workspace/coverage/cover_reg_top/73.xbar_smoke_zero_delays.1356924673 | Aug 12 06:56:06 PM PDT 24 | Aug 12 06:56:12 PM PDT 24 | 40350149 ps | ||
| T2835 | /workspace/coverage/cover_reg_top/99.xbar_stress_all_with_rand_reset.4032645744 | Aug 12 06:59:27 PM PDT 24 | Aug 12 07:02:16 PM PDT 24 | 316112211 ps | ||
| T2836 | /workspace/coverage/cover_reg_top/2.xbar_stress_all_with_rand_reset.2779518932 | Aug 12 06:47:20 PM PDT 24 | Aug 12 06:48:35 PM PDT 24 | 119133511 ps | ||
| T2837 | /workspace/coverage/cover_reg_top/26.xbar_random.4242788936 | Aug 12 06:49:44 PM PDT 24 | Aug 12 06:50:24 PM PDT 24 | 471837106 ps | ||
| T2838 | /workspace/coverage/cover_reg_top/64.xbar_stress_all_with_reset_error.1737828739 | Aug 12 06:55:12 PM PDT 24 | Aug 12 07:00:17 PM PDT 24 | 3189209055 ps | ||
| T2839 | /workspace/coverage/cover_reg_top/83.xbar_stress_all_with_reset_error.283200408 | Aug 12 06:57:33 PM PDT 24 | Aug 12 07:03:31 PM PDT 24 | 2069738894 ps | ||
| T2840 | /workspace/coverage/cover_reg_top/13.xbar_unmapped_addr.4091908114 | Aug 12 06:48:00 PM PDT 24 | Aug 12 06:48:23 PM PDT 24 | 541847521 ps | ||
| T2841 | /workspace/coverage/cover_reg_top/93.xbar_stress_all_with_rand_reset.1591455185 | Aug 12 06:58:56 PM PDT 24 | Aug 12 07:06:57 PM PDT 24 | 4018801516 ps | ||
| T2842 | /workspace/coverage/cover_reg_top/67.xbar_access_same_device.2636946486 | Aug 12 06:55:29 PM PDT 24 | Aug 12 06:55:36 PM PDT 24 | 61085424 ps | ||
| T2843 | /workspace/coverage/cover_reg_top/49.xbar_stress_all_with_rand_reset.2497087517 | Aug 12 06:53:14 PM PDT 24 | Aug 12 06:55:04 PM PDT 24 | 350891977 ps | ||
| T2844 | /workspace/coverage/cover_reg_top/22.xbar_random_slow_rsp.1776310442 | Aug 12 06:49:12 PM PDT 24 | Aug 12 06:50:40 PM PDT 24 | 5266639943 ps | ||
| T2845 | /workspace/coverage/cover_reg_top/6.xbar_stress_all_with_error.3720779633 | Aug 12 06:47:30 PM PDT 24 | Aug 12 06:52:14 PM PDT 24 | 7476506807 ps | ||
| T2846 | /workspace/coverage/cover_reg_top/48.xbar_random.2459357225 | Aug 12 06:52:59 PM PDT 24 | Aug 12 06:54:07 PM PDT 24 | 1883928627 ps | ||
| T2847 | /workspace/coverage/cover_reg_top/29.xbar_random.4202197514 | Aug 12 06:50:14 PM PDT 24 | Aug 12 06:50:28 PM PDT 24 | 156330768 ps | ||
| T2848 | /workspace/coverage/cover_reg_top/58.xbar_access_same_device.902876942 | Aug 12 06:54:25 PM PDT 24 | Aug 12 06:55:30 PM PDT 24 | 747946933 ps | ||
| T2849 | /workspace/coverage/cover_reg_top/24.xbar_stress_all.456252596 | Aug 12 06:49:28 PM PDT 24 | Aug 12 07:02:47 PM PDT 24 | 19540186848 ps | ||
| T2850 | /workspace/coverage/cover_reg_top/97.xbar_smoke.2125744239 | Aug 12 06:59:18 PM PDT 24 | Aug 12 06:59:29 PM PDT 24 | 239846119 ps | ||
| T2851 | /workspace/coverage/cover_reg_top/18.chip_same_csr_outstanding.1997713592 | Aug 12 06:48:38 PM PDT 24 | Aug 12 07:50:29 PM PDT 24 | 32136356739 ps | ||
| T2852 | /workspace/coverage/cover_reg_top/79.xbar_random_slow_rsp.1879764353 | Aug 12 06:57:06 PM PDT 24 | Aug 12 06:58:08 PM PDT 24 | 3828847333 ps | ||
| T2853 | /workspace/coverage/cover_reg_top/94.xbar_smoke.3388223642 | Aug 12 06:58:57 PM PDT 24 | Aug 12 06:59:06 PM PDT 24 | 176079279 ps | ||
| T2854 | /workspace/coverage/cover_reg_top/68.xbar_access_same_device_slow_rsp.3015361185 | Aug 12 06:55:39 PM PDT 24 | Aug 12 07:37:09 PM PDT 24 | 133113660430 ps | ||
| T2855 | /workspace/coverage/cover_reg_top/80.xbar_access_same_device_slow_rsp.3277394667 | Aug 12 06:56:59 PM PDT 24 | Aug 12 07:18:07 PM PDT 24 | 67719441751 ps | ||
| T2856 | /workspace/coverage/cover_reg_top/30.xbar_smoke_zero_delays.1380000539 | Aug 12 06:50:26 PM PDT 24 | Aug 12 06:50:32 PM PDT 24 | 33622986 ps | ||
| T2857 | /workspace/coverage/cover_reg_top/10.xbar_smoke_zero_delays.1177595374 | Aug 12 06:47:44 PM PDT 24 | Aug 12 06:47:50 PM PDT 24 | 42488428 ps | ||
| T2858 | /workspace/coverage/cover_reg_top/43.xbar_smoke_zero_delays.2323056943 | Aug 12 06:52:13 PM PDT 24 | Aug 12 06:52:19 PM PDT 24 | 42200744 ps | ||
| T2859 | /workspace/coverage/cover_reg_top/9.xbar_smoke_large_delays.4157585736 | Aug 12 06:47:36 PM PDT 24 | Aug 12 06:48:49 PM PDT 24 | 7233914417 ps | ||
| T2860 | /workspace/coverage/cover_reg_top/26.xbar_unmapped_addr.4098754708 | Aug 12 06:49:49 PM PDT 24 | Aug 12 06:50:08 PM PDT 24 | 138095767 ps | ||
| T2861 | /workspace/coverage/cover_reg_top/72.xbar_error_and_unmapped_addr.1406238936 | Aug 12 06:56:08 PM PDT 24 | Aug 12 06:56:30 PM PDT 24 | 472567126 ps | ||
| T2862 | /workspace/coverage/cover_reg_top/40.xbar_access_same_device_slow_rsp.2301352206 | Aug 12 06:51:58 PM PDT 24 | Aug 12 07:32:05 PM PDT 24 | 137585464561 ps | ||
| T2863 | /workspace/coverage/cover_reg_top/88.xbar_smoke_zero_delays.1315552843 | Aug 12 06:57:59 PM PDT 24 | Aug 12 06:58:06 PM PDT 24 | 51039083 ps | ||
| T2864 | /workspace/coverage/cover_reg_top/86.xbar_stress_all_with_error.783945766 | Aug 12 06:57:41 PM PDT 24 | Aug 12 06:58:09 PM PDT 24 | 409934570 ps | ||
| T2865 | /workspace/coverage/cover_reg_top/29.xbar_error_random.4118581196 | Aug 12 06:50:14 PM PDT 24 | Aug 12 06:50:52 PM PDT 24 | 486290992 ps | ||
| T2866 | /workspace/coverage/cover_reg_top/81.xbar_stress_all.3268576564 | Aug 12 06:57:13 PM PDT 24 | Aug 12 07:03:23 PM PDT 24 | 10441358440 ps | ||
| T2867 | /workspace/coverage/cover_reg_top/33.xbar_error_random.612833891 | Aug 12 06:51:32 PM PDT 24 | Aug 12 06:52:39 PM PDT 24 | 2204949469 ps | ||
| T2868 | /workspace/coverage/cover_reg_top/8.xbar_random_large_delays.3317123297 | Aug 12 06:47:34 PM PDT 24 | Aug 12 06:48:40 PM PDT 24 | 6109830478 ps | ||
| T2869 | /workspace/coverage/cover_reg_top/14.xbar_random_slow_rsp.2573030658 | Aug 12 06:48:08 PM PDT 24 | Aug 12 06:53:13 PM PDT 24 | 17895328071 ps | ||
| T2870 | /workspace/coverage/cover_reg_top/83.xbar_unmapped_addr.763080692 | Aug 12 06:57:21 PM PDT 24 | Aug 12 06:57:26 PM PDT 24 | 24969482 ps | ||
| T2871 | /workspace/coverage/cover_reg_top/70.xbar_unmapped_addr.581992854 | Aug 12 06:55:50 PM PDT 24 | Aug 12 06:56:27 PM PDT 24 | 858882079 ps | ||
| T2872 | /workspace/coverage/cover_reg_top/35.xbar_random_zero_delays.2961546209 | Aug 12 06:51:35 PM PDT 24 | Aug 12 06:51:50 PM PDT 24 | 126824342 ps | ||
| T2873 | /workspace/coverage/cover_reg_top/43.xbar_stress_all_with_rand_reset.2839958063 | Aug 12 06:52:24 PM PDT 24 | Aug 12 06:57:23 PM PDT 24 | 2382734837 ps | ||
| T2874 | /workspace/coverage/cover_reg_top/6.chip_csr_mem_rw_with_rand_reset.951521795 | Aug 12 06:47:40 PM PDT 24 | Aug 12 07:01:49 PM PDT 24 | 10956049655 ps | ||
| T2875 | /workspace/coverage/cover_reg_top/18.chip_csr_rw.112856184 | Aug 12 06:48:47 PM PDT 24 | Aug 12 06:53:59 PM PDT 24 | 4874450716 ps | ||
| T2876 | /workspace/coverage/cover_reg_top/64.xbar_smoke_large_delays.2842979198 | Aug 12 06:55:00 PM PDT 24 | Aug 12 06:56:38 PM PDT 24 | 9451893651 ps | ||
| T2877 | /workspace/coverage/cover_reg_top/3.xbar_error_and_unmapped_addr.2192182796 | Aug 12 06:47:16 PM PDT 24 | Aug 12 06:48:07 PM PDT 24 | 1344465698 ps | ||
| T2878 | /workspace/coverage/cover_reg_top/15.chip_csr_mem_rw_with_rand_reset.3763949162 | Aug 12 06:48:15 PM PDT 24 | Aug 12 06:55:45 PM PDT 24 | 6957279510 ps | ||
| T2879 | /workspace/coverage/cover_reg_top/34.xbar_smoke_large_delays.3138258924 | Aug 12 06:51:34 PM PDT 24 | Aug 12 06:53:08 PM PDT 24 | 8964312126 ps | ||
| T2880 | /workspace/coverage/cover_reg_top/3.xbar_stress_all_with_reset_error.3244916449 | Aug 12 06:47:17 PM PDT 24 | Aug 12 06:50:18 PM PDT 24 | 1614147743 ps | ||
| T2881 | /workspace/coverage/cover_reg_top/8.xbar_random_zero_delays.3222204572 | Aug 12 06:47:49 PM PDT 24 | Aug 12 06:48:31 PM PDT 24 | 600408231 ps | ||
| T2882 | /workspace/coverage/cover_reg_top/36.xbar_smoke_large_delays.3984750168 | Aug 12 06:51:33 PM PDT 24 | Aug 12 06:52:46 PM PDT 24 | 7120353222 ps | ||
| T2883 | /workspace/coverage/cover_reg_top/21.xbar_unmapped_addr.1195263000 | Aug 12 06:49:03 PM PDT 24 | Aug 12 06:49:23 PM PDT 24 | 431496204 ps | ||
| T2884 | /workspace/coverage/cover_reg_top/47.xbar_error_and_unmapped_addr.2676247210 | Aug 12 06:52:59 PM PDT 24 | Aug 12 06:53:11 PM PDT 24 | 105161000 ps | ||
| T2885 | /workspace/coverage/cover_reg_top/28.chip_tl_errors.3717650373 | Aug 12 06:49:56 PM PDT 24 | Aug 12 06:53:59 PM PDT 24 | 3752088490 ps | ||
| T2886 | /workspace/coverage/cover_reg_top/46.xbar_error_and_unmapped_addr.1724179657 | Aug 12 06:52:50 PM PDT 24 | Aug 12 06:52:57 PM PDT 24 | 39868582 ps | ||
| T2887 | /workspace/coverage/cover_reg_top/29.xbar_access_same_device.1037164537 | Aug 12 06:50:19 PM PDT 24 | Aug 12 06:52:11 PM PDT 24 | 2806417737 ps | ||
| T2888 | /workspace/coverage/cover_reg_top/46.xbar_smoke_slow_rsp.612271439 | Aug 12 06:52:49 PM PDT 24 | Aug 12 06:54:16 PM PDT 24 | 4982076299 ps | ||
| T2889 | /workspace/coverage/cover_reg_top/0.chip_prim_tl_access.4259977524 | Aug 12 06:47:09 PM PDT 24 | Aug 12 06:50:29 PM PDT 24 | 6672800904 ps | ||
| T2890 | /workspace/coverage/cover_reg_top/22.chip_tl_errors.1673663774 | Aug 12 06:49:01 PM PDT 24 | Aug 12 06:51:57 PM PDT 24 | 3754588688 ps | ||
| T2891 | /workspace/coverage/cover_reg_top/53.xbar_error_random.4280479907 | Aug 12 06:53:37 PM PDT 24 | Aug 12 06:53:51 PM PDT 24 | 312831263 ps | ||
| T2892 | /workspace/coverage/cover_reg_top/46.xbar_smoke_zero_delays.3551466417 | Aug 12 06:52:52 PM PDT 24 | Aug 12 06:52:58 PM PDT 24 | 48339456 ps | ||
| T2893 | /workspace/coverage/cover_reg_top/6.xbar_smoke.3285009566 | Aug 12 06:47:27 PM PDT 24 | Aug 12 06:47:32 PM PDT 24 | 42409086 ps | ||
| T2894 | /workspace/coverage/cover_reg_top/39.xbar_random.2125843393 | Aug 12 06:51:44 PM PDT 24 | Aug 12 06:52:36 PM PDT 24 | 1707477384 ps | ||
| T2895 | /workspace/coverage/cover_reg_top/91.xbar_stress_all_with_rand_reset.705407709 | Aug 12 06:58:25 PM PDT 24 | Aug 12 06:59:49 PM PDT 24 | 115893702 ps | ||
| T2896 | /workspace/coverage/cover_reg_top/99.xbar_error_and_unmapped_addr.1206082807 | Aug 12 06:59:27 PM PDT 24 | Aug 12 06:59:42 PM PDT 24 | 134477862 ps | ||
| T2897 | /workspace/coverage/cover_reg_top/41.xbar_random_zero_delays.478925503 | Aug 12 06:51:46 PM PDT 24 | Aug 12 06:52:28 PM PDT 24 | 456000871 ps | ||
| T2898 | /workspace/coverage/cover_reg_top/51.xbar_smoke_slow_rsp.3374718705 | Aug 12 06:53:18 PM PDT 24 | Aug 12 06:54:33 PM PDT 24 | 4620799835 ps | ||
| T2899 | /workspace/coverage/cover_reg_top/66.xbar_stress_all_with_rand_reset.1696502244 | Aug 12 06:55:22 PM PDT 24 | Aug 12 07:07:54 PM PDT 24 | 14795671198 ps | ||
| T2900 | /workspace/coverage/cover_reg_top/28.xbar_smoke.2638984417 | Aug 12 06:49:59 PM PDT 24 | Aug 12 06:50:09 PM PDT 24 | 211576553 ps | ||
| T2901 | /workspace/coverage/cover_reg_top/72.xbar_stress_all_with_rand_reset.1009101748 | Aug 12 06:56:09 PM PDT 24 | Aug 12 07:09:24 PM PDT 24 | 6630850282 ps | ||
| T2902 | /workspace/coverage/cover_reg_top/46.xbar_access_same_device.3491841685 | Aug 12 06:52:48 PM PDT 24 | Aug 12 06:53:10 PM PDT 24 | 239957522 ps | ||
| T2903 | /workspace/coverage/cover_reg_top/13.xbar_smoke_slow_rsp.879023943 | Aug 12 06:48:02 PM PDT 24 | Aug 12 06:49:32 PM PDT 24 | 5502748801 ps | ||
| T2904 | /workspace/coverage/cover_reg_top/69.xbar_smoke_zero_delays.250918281 | Aug 12 06:55:39 PM PDT 24 | Aug 12 06:55:46 PM PDT 24 | 48833941 ps | ||
| T2905 | /workspace/coverage/cover_reg_top/95.xbar_error_random.3388309489 | Aug 12 06:59:04 PM PDT 24 | Aug 12 06:59:30 PM PDT 24 | 836425213 ps | ||
| T766 | /workspace/coverage/cover_reg_top/99.xbar_stress_all_with_error.3174063106 | Aug 12 06:59:27 PM PDT 24 | Aug 12 07:06:01 PM PDT 24 | 4685568935 ps | ||
| T2906 | /workspace/coverage/cover_reg_top/2.chip_rv_dm_lc_disabled.2964456874 | Aug 12 06:47:15 PM PDT 24 | Aug 12 06:58:45 PM PDT 24 | 21807655582 ps | ||
| T2907 | /workspace/coverage/cover_reg_top/48.xbar_random_large_delays.3224385457 | Aug 12 06:52:58 PM PDT 24 | Aug 12 07:01:12 PM PDT 24 | 43445216775 ps | ||
| T2908 | /workspace/coverage/cover_reg_top/49.xbar_access_same_device.2094226066 | Aug 12 06:53:07 PM PDT 24 | Aug 12 06:53:33 PM PDT 24 | 272345286 ps | ||
| T2909 | /workspace/coverage/cover_reg_top/91.xbar_smoke_slow_rsp.1470271870 | Aug 12 06:58:27 PM PDT 24 | Aug 12 06:59:23 PM PDT 24 | 3422706446 ps | ||
| T2910 | /workspace/coverage/cover_reg_top/68.xbar_stress_all_with_reset_error.3444883605 | Aug 12 06:55:39 PM PDT 24 | Aug 12 07:00:33 PM PDT 24 | 2807428248 ps | ||
| T2911 | /workspace/coverage/cover_reg_top/67.xbar_same_source.2194588297 | Aug 12 06:55:30 PM PDT 24 | Aug 12 06:56:01 PM PDT 24 | 1064897590 ps | ||
| T2912 | /workspace/coverage/cover_reg_top/36.xbar_stress_all_with_reset_error.792974926 | Aug 12 06:51:37 PM PDT 24 | Aug 12 06:56:48 PM PDT 24 | 2752968365 ps | ||
| T2913 | /workspace/coverage/cover_reg_top/40.xbar_random_large_delays.390832961 | Aug 12 06:51:46 PM PDT 24 | Aug 12 07:00:46 PM PDT 24 | 52859871143 ps | ||
| T2914 | /workspace/coverage/cover_reg_top/31.xbar_random_zero_delays.719024232 | Aug 12 06:50:34 PM PDT 24 | Aug 12 06:51:13 PM PDT 24 | 415800704 ps | ||
| T2915 | /workspace/coverage/cover_reg_top/30.xbar_random_large_delays.1515757242 | Aug 12 06:50:26 PM PDT 24 | Aug 12 06:52:37 PM PDT 24 | 12546082715 ps | ||
| T2916 | /workspace/coverage/cover_reg_top/48.xbar_smoke_slow_rsp.2442162835 | Aug 12 06:53:01 PM PDT 24 | Aug 12 06:54:30 PM PDT 24 | 5238459207 ps | ||
| T2917 | /workspace/coverage/cover_reg_top/44.xbar_same_source.1064884960 | Aug 12 06:52:33 PM PDT 24 | Aug 12 06:52:44 PM PDT 24 | 299609533 ps | ||
| T2918 | /workspace/coverage/cover_reg_top/40.xbar_same_source.3084857571 | Aug 12 06:51:44 PM PDT 24 | Aug 12 06:52:08 PM PDT 24 | 279665099 ps | ||
| T2919 | /workspace/coverage/cover_reg_top/97.xbar_smoke_large_delays.2356986521 | Aug 12 06:59:11 PM PDT 24 | Aug 12 07:00:42 PM PDT 24 | 8525344027 ps | ||
| T2920 | /workspace/coverage/cover_reg_top/3.xbar_stress_all.662834405 | Aug 12 06:47:19 PM PDT 24 | Aug 12 06:51:41 PM PDT 24 | 2959158609 ps | ||
| T2921 | /workspace/coverage/cover_reg_top/3.xbar_error_random.2115025402 | Aug 12 06:47:19 PM PDT 24 | Aug 12 06:47:30 PM PDT 24 | 106406071 ps | ||
| T2922 | /workspace/coverage/cover_reg_top/40.xbar_random_zero_delays.3590988960 | Aug 12 06:51:47 PM PDT 24 | Aug 12 06:52:12 PM PDT 24 | 295256196 ps | ||
| T2923 | /workspace/coverage/cover_reg_top/39.xbar_access_same_device_slow_rsp.338721397 | Aug 12 06:51:46 PM PDT 24 | Aug 12 06:57:30 PM PDT 24 | 22085100140 ps | ||
| T2924 | /workspace/coverage/cover_reg_top/65.xbar_stress_all_with_reset_error.2959628510 | Aug 12 06:55:12 PM PDT 24 | Aug 12 06:59:18 PM PDT 24 | 2667249471 ps | ||
| T2925 | /workspace/coverage/cover_reg_top/69.xbar_stress_all_with_reset_error.2106892832 | Aug 12 06:55:55 PM PDT 24 | Aug 12 06:56:28 PM PDT 24 | 175554643 ps | ||
| T2926 | /workspace/coverage/cover_reg_top/58.xbar_error_random.2715491165 | Aug 12 06:54:24 PM PDT 24 | Aug 12 06:54:34 PM PDT 24 | 188371407 ps | ||
| T2927 | /workspace/coverage/cover_reg_top/32.xbar_stress_all_with_reset_error.1211519756 | Aug 12 06:51:33 PM PDT 24 | Aug 12 06:54:19 PM PDT 24 | 1347720049 ps | ||
| T2928 | /workspace/coverage/cover_reg_top/93.xbar_random.2942562814 | Aug 12 06:58:38 PM PDT 24 | Aug 12 06:59:05 PM PDT 24 | 632546027 ps | ||
| T2929 | /workspace/coverage/cover_reg_top/80.xbar_stress_all.1525329031 | Aug 12 06:57:16 PM PDT 24 | Aug 12 06:57:46 PM PDT 24 | 844083704 ps | ||
| T2930 | /workspace/coverage/cover_reg_top/39.xbar_random_large_delays.4119197361 | Aug 12 06:51:36 PM PDT 24 | Aug 12 07:06:44 PM PDT 24 | 84752696905 ps | ||
| T2931 | /workspace/coverage/cover_reg_top/9.chip_tl_errors.2351625456 | Aug 12 06:47:36 PM PDT 24 | Aug 12 06:51:22 PM PDT 24 | 3756587514 ps | ||
| T2932 | /workspace/coverage/cover_reg_top/27.xbar_stress_all_with_error.3643180163 | Aug 12 06:50:01 PM PDT 24 | Aug 12 06:52:01 PM PDT 24 | 1562552376 ps | ||
| T2933 | /workspace/coverage/cover_reg_top/21.xbar_stress_all_with_error.3785991648 | Aug 12 06:49:02 PM PDT 24 | Aug 12 06:51:56 PM PDT 24 | 5353450976 ps | ||
| T2934 | /workspace/coverage/cover_reg_top/14.xbar_smoke_large_delays.3361196691 | Aug 12 06:48:05 PM PDT 24 | Aug 12 06:49:28 PM PDT 24 | 8430347861 ps | ||
| T2935 | /workspace/coverage/cover_reg_top/55.xbar_stress_all_with_error.4009727003 | Aug 12 06:54:12 PM PDT 24 | Aug 12 06:55:39 PM PDT 24 | 2395695877 ps | ||
| T2936 | /workspace/coverage/cover_reg_top/58.xbar_stress_all_with_error.1079688167 | Aug 12 06:54:35 PM PDT 24 | Aug 12 06:59:21 PM PDT 24 | 8414270003 ps | ||
| T2937 | /workspace/coverage/cover_reg_top/71.xbar_smoke_zero_delays.3314516259 | Aug 12 06:55:57 PM PDT 24 | Aug 12 06:56:03 PM PDT 24 | 52619149 ps | ||
| T2938 | /workspace/coverage/cover_reg_top/20.xbar_stress_all.3003743827 | Aug 12 06:48:54 PM PDT 24 | Aug 12 06:52:47 PM PDT 24 | 6752936157 ps | ||
| T2939 | /workspace/coverage/cover_reg_top/76.xbar_same_source.3424105947 | Aug 12 06:56:38 PM PDT 24 | Aug 12 06:57:13 PM PDT 24 | 1069813639 ps | ||
| T2940 | /workspace/coverage/cover_reg_top/50.xbar_smoke.1810395079 | Aug 12 06:53:17 PM PDT 24 | Aug 12 06:53:25 PM PDT 24 | 162155201 ps | ||
| T2941 | /workspace/coverage/cover_reg_top/24.xbar_same_source.3578209112 | Aug 12 06:49:28 PM PDT 24 | Aug 12 06:50:35 PM PDT 24 | 2501971138 ps | ||
| T2942 | /workspace/coverage/cover_reg_top/26.xbar_error_random.3112549067 | Aug 12 06:49:44 PM PDT 24 | Aug 12 06:50:02 PM PDT 24 | 217946281 ps | ||
| T2943 | /workspace/coverage/cover_reg_top/13.xbar_random_large_delays.2157040393 | Aug 12 06:47:48 PM PDT 24 | Aug 12 07:05:19 PM PDT 24 | 102537107665 ps | ||
| T31 | /workspace/coverage/pad_ctrl_test_mode/8.chip_padctrl_attributes.411000603 | Aug 12 07:35:19 PM PDT 24 | Aug 12 07:41:12 PM PDT 24 | 4443347439 ps | ||
| T32 | /workspace/coverage/pad_ctrl_test_mode/4.chip_padctrl_attributes.2828813347 | Aug 12 07:35:14 PM PDT 24 | Aug 12 07:39:33 PM PDT 24 | 5058078686 ps | ||
| T33 | /workspace/coverage/pad_ctrl_test_mode/7.chip_padctrl_attributes.68185628 | Aug 12 07:35:17 PM PDT 24 | Aug 12 07:39:29 PM PDT 24 | 3903315240 ps | ||
| T34 | /workspace/coverage/pad_ctrl_test_mode/6.chip_padctrl_attributes.4212134968 | Aug 12 07:35:26 PM PDT 24 | Aug 12 07:40:37 PM PDT 24 | 5282492644 ps | ||
| T42 | /workspace/coverage/pad_ctrl_test_mode/0.chip_padctrl_attributes.1635198973 | Aug 12 07:34:59 PM PDT 24 | Aug 12 07:40:04 PM PDT 24 | 5606872948 ps | ||
| T199 | /workspace/coverage/pad_ctrl_test_mode/5.chip_padctrl_attributes.1817662295 | Aug 12 07:35:23 PM PDT 24 | Aug 12 07:39:44 PM PDT 24 | 4887336288 ps | ||
| T200 | /workspace/coverage/pad_ctrl_test_mode/3.chip_padctrl_attributes.2746960665 | Aug 12 07:35:22 PM PDT 24 | Aug 12 07:41:02 PM PDT 24 | 5487576795 ps | ||
| T201 | /workspace/coverage/pad_ctrl_test_mode/9.chip_padctrl_attributes.3468217769 | Aug 12 07:35:15 PM PDT 24 | Aug 12 07:39:10 PM PDT 24 | 3859695675 ps | ||
| T202 | /workspace/coverage/pad_ctrl_test_mode/1.chip_padctrl_attributes.1013253395 | Aug 12 07:34:59 PM PDT 24 | Aug 12 07:39:09 PM PDT 24 | 4909373269 ps | ||
| T204 | /workspace/coverage/pad_ctrl_test_mode/2.chip_padctrl_attributes.4134806719 | Aug 12 07:35:14 PM PDT 24 | Aug 12 07:40:37 PM PDT 24 | 5051701810 ps |
| Test location | /workspace/coverage/default/56.chip_sw_all_escalation_resets.3048952077 |
| Short name | T6 |
| Test name | |
| Test status | |
| Simulation time | 5624586738 ps |
| CPU time | 681.82 seconds |
| Started | Aug 12 07:38:48 PM PDT 24 |
| Finished | Aug 12 07:50:10 PM PDT 24 |
| Peak memory | 650520 kb |
| Host | smart-425f6759-e971-4036-beb3-ccfe853e3c7d |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 3048952077 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 56.chip_sw_all_escalation_resets.3048952077 |
| Directory | /workspace/56.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/cover_reg_top/16.chip_csr_mem_rw_with_rand_reset.272406096 |
| Short name | T156 |
| Test name | |
| Test status | |
| Simulation time | 10567681072 ps |
| CPU time | 666.95 seconds |
| Started | Aug 12 06:48:26 PM PDT 24 |
| Finished | Aug 12 06:59:33 PM PDT 24 |
| Peak memory | 644392 kb |
| Host | smart-b3a1a4ca-3398-43e8-b8ea-f400d5965bf1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=272406096 -assert nopostproc +U VM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top. vdb -cm_log /dev/null -cm_name 16.chip_csr_mem_rw_with_rand_reset.272406096 |
| Directory | /workspace/16.chip_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/90.xbar_stress_all_with_error.3781919921 |
| Short name | T137 |
| Test name | |
| Test status | |
| Simulation time | 5086473232 ps |
| CPU time | 391.53 seconds |
| Started | Aug 12 06:58:24 PM PDT 24 |
| Finished | Aug 12 07:04:56 PM PDT 24 |
| Peak memory | 576644 kb |
| Host | smart-6017d8ae-22c1-452b-983d-6dbd58b49b38 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3781919921 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 90.xbar_stress_all_with_error.3781919921 |
| Directory | /workspace/90.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/default/0.chip_plic_all_irqs_0.1100387318 |
| Short name | T331 |
| Test name | |
| Test status | |
| Simulation time | 6220479760 ps |
| CPU time | 1353.66 seconds |
| Started | Aug 12 07:10:53 PM PDT 24 |
| Finished | Aug 12 07:33:27 PM PDT 24 |
| Peak memory | 610616 kb |
| Host | smart-bb69550a-e54f-4bb1-98d9-5270448df502 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=plic_all_irqs_test_0:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1100387318 -assert nopostproc +UVM_TESTNA ME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 0.chip_plic_all_irqs_0.1100387318 |
| Directory | /workspace/0.chip_plic_all_irqs_0/latest |
| Test location | /workspace/coverage/cover_reg_top/10.xbar_access_same_device_slow_rsp.1364371976 |
| Short name | T496 |
| Test name | |
| Test status | |
| Simulation time | 93328216251 ps |
| CPU time | 1782.7 seconds |
| Started | Aug 12 06:47:44 PM PDT 24 |
| Finished | Aug 12 07:17:27 PM PDT 24 |
| Peak memory | 576000 kb |
| Host | smart-fd3a74fa-60fc-468a-9ca4-4adfe00b4e9d |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1364371976 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.xbar_access_same_ device_slow_rsp.1364371976 |
| Directory | /workspace/10.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/default/0.chip_sw_power_virus.648383791 |
| Short name | T12 |
| Test name | |
| Test status | |
| Simulation time | 5577220692 ps |
| CPU time | 1478.56 seconds |
| Started | Aug 12 07:15:58 PM PDT 24 |
| Finished | Aug 12 07:40:37 PM PDT 24 |
| Peak memory | 625444 kb |
| Host | smart-d17ed1fe-29bd-4faa-bdaa-f41114ccba82 |
| User | root |
| Command | /workspace/default/simv +rng_srate_value_min=15 +rng_srate_value_max=20 +sw_test_timeout_ns=400_000_000 +use_otp_image=OtpTypeCustom +sw_build_device= sim_dv +sw_images=power_virus_systemtest:1:new_rules,power_virus_systemtest_otp_img_rma:4,test_rom:0 +accelerate_cold_power_up_time=3 +accelerate_ regulators_power_up_time=2 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d v/tools/sim.tcl +ntb_random_seed=648383791 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_power_virus_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_power_virus.648383791 |
| Directory | /workspace/0.chip_sw_power_virus/latest |
| Test location | /workspace/coverage/pad_ctrl_test_mode/8.chip_padctrl_attributes.411000603 |
| Short name | T31 |
| Test name | |
| Test status | |
| Simulation time | 4443347439 ps |
| CPU time | 352.55 seconds |
| Started | Aug 12 07:35:19 PM PDT 24 |
| Finished | Aug 12 07:41:12 PM PDT 24 |
| Peak memory | 641280 kb |
| Host | smart-3cf412e9-80fe-42c1-99a0-9d82a0dd306f |
| User | root |
| Command | /workspace/pad_ctrl_test_mode/simv +use_otp_image=OtpTypeLcStProd +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=411000603 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TES T_SEQ=chip_padctrl_attributes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/pad_ctrl_test_mode.vdb -cm_log /dev/n ull -cm_name 8.chip_padctrl_attributes.411000603 |
| Directory | /workspace/8.chip_padctrl_attributes/latest |
| Test location | /workspace/coverage/default/1.chip_sw_keymgr_key_derivation_jitter_en_reduced_freq.1361308886 |
| Short name | T122 |
| Test name | |
| Test status | |
| Simulation time | 10148874774 ps |
| CPU time | 1625.45 seconds |
| Started | Aug 12 07:19:53 PM PDT 24 |
| Finished | Aug 12 07:46:59 PM PDT 24 |
| Peak memory | 617408 kb |
| Host | smart-51885279-6ad7-4668-a18e-4bcab49e1445 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=20_000_000 +en_jitter=1 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=keymgr_key_derivation_test :1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=1361308886 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_keymgr_key_derivation_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_keymgr_key_derivation_jitter_en _reduced_freq.1361308886 |
| Directory | /workspace/1.chip_sw_keymgr_key_derivation_jitter_en_reduced_freq/latest |
| Test location | /workspace/coverage/cover_reg_top/14.xbar_access_same_device_slow_rsp.1440019027 |
| Short name | T760 |
| Test name | |
| Test status | |
| Simulation time | 85011597683 ps |
| CPU time | 1466.48 seconds |
| Started | Aug 12 06:47:58 PM PDT 24 |
| Finished | Aug 12 07:12:25 PM PDT 24 |
| Peak memory | 575656 kb |
| Host | smart-bd083244-ee55-49e1-85fe-1dc8f583c55b |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1440019027 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.xbar_access_same_ device_slow_rsp.1440019027 |
| Directory | /workspace/14.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/default/2.chip_sw_lc_walkthrough_dev.2347032120 |
| Short name | T52 |
| Test name | |
| Test status | |
| Simulation time | 50107357311 ps |
| CPU time | 5313.63 seconds |
| Started | Aug 12 07:24:25 PM PDT 24 |
| Finished | Aug 12 08:53:00 PM PDT 24 |
| Peak memory | 621328 kb |
| Host | smart-dcecc002-a5f8-4721-a85d-87f1cbbe72e9 |
| User | root |
| Command | /workspace/default/simv +flash_program_latency=5 +use_otp_image=OtpTypeLcStRaw +dest_dec_state=DecLcStDev +sw_test_timeout_ns=200_000_000 +sw_build_de vice=sim_dv +sw_images=lc_walkthrough_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2347032120 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=c hip_sw_lc_walkthrough_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip _sw_lc_walkthrough_dev.2347032120 |
| Directory | /workspace/2.chip_sw_lc_walkthrough_dev/latest |
| Test location | /workspace/coverage/default/0.chip_sw_alert_test.817986919 |
| Short name | T57 |
| Test name | |
| Test status | |
| Simulation time | 2474408648 ps |
| CPU time | 259.84 seconds |
| Started | Aug 12 07:11:00 PM PDT 24 |
| Finished | Aug 12 07:15:20 PM PDT 24 |
| Peak memory | 610368 kb |
| Host | smart-05361664-cf74-4b1e-92b4-0164fbc53dc8 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=alert_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=817986919 -assert nopostproc +UVM_TESTNAME=chip_bas e_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm _name 0.chip_sw_alert_test.817986919 |
| Directory | /workspace/0.chip_sw_alert_test/latest |
| Test location | /workspace/coverage/cover_reg_top/46.xbar_access_same_device_slow_rsp.569705881 |
| Short name | T477 |
| Test name | |
| Test status | |
| Simulation time | 130025896030 ps |
| CPU time | 2473.1 seconds |
| Started | Aug 12 06:52:52 PM PDT 24 |
| Finished | Aug 12 07:34:05 PM PDT 24 |
| Peak memory | 575868 kb |
| Host | smart-a1b61bfb-3b31-4b24-b4b7-fe6082af8389 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=569705881 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.xbar_access_same_d evice_slow_rsp.569705881 |
| Directory | /workspace/46.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/default/2.chip_sw_sleep_pin_retention.2434055836 |
| Short name | T17 |
| Test name | |
| Test status | |
| Simulation time | 4198609960 ps |
| CPU time | 478.8 seconds |
| Started | Aug 12 07:22:49 PM PDT 24 |
| Finished | Aug 12 07:30:48 PM PDT 24 |
| Peak memory | 609288 kb |
| Host | smart-33485078-5fe1-45e6-8231-e4582619dafa |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=sleep_pin_retention_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2434055836 -assert nopostproc +UVM_TE STNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sleep_pin_retention_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def ault.vdb -cm_log /dev/null -cm_name 2.chip_sw_sleep_pin_retention.2434055836 |
| Directory | /workspace/2.chip_sw_sleep_pin_retention/latest |
| Test location | /workspace/coverage/cover_reg_top/77.xbar_access_same_device_slow_rsp.3921499833 |
| Short name | T503 |
| Test name | |
| Test status | |
| Simulation time | 108100144288 ps |
| CPU time | 2034.44 seconds |
| Started | Aug 12 06:56:40 PM PDT 24 |
| Finished | Aug 12 07:30:34 PM PDT 24 |
| Peak memory | 575700 kb |
| Host | smart-ea4e0af6-7e98-4cd7-aa94-3a92306240e0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3921499833 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 77.xbar_access_same_ device_slow_rsp.3921499833 |
| Directory | /workspace/77.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_sigverify_always_a_nothing_b_bad_prod_end.1086933448 |
| Short name | T7 |
| Test name | |
| Test status | |
| Simulation time | 14041283570 ps |
| CPU time | 4772.52 seconds |
| Started | Aug 12 07:18:27 PM PDT 24 |
| Finished | Aug 12 08:38:00 PM PDT 24 |
| Peak memory | 610672 kb |
| Host | smart-597e274e-6f90-4a39-8e26-84d8053ff23f |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=100_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_b_corrupted:1: ot_flash_binary:signed:fake_ecdsa_prod_key_0,otp_img_sigverify_always_prod_end:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1086933448 -assert nopostproc +UVM_TESTNAME=chip _base_test +UVM_TEST_SEQ=chip_sw_rom_e2e_sigverify_always_a_bad_b_bad_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera ge/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_sigverify_always_a_nothing_b_bad_prod_end.1086933448 |
| Directory | /workspace/0.rom_e2e_sigverify_always_a_nothing_b_bad_prod_end/latest |
| Test location | /workspace/coverage/cover_reg_top/12.xbar_stress_all_with_reset_error.4216856424 |
| Short name | T556 |
| Test name | |
| Test status | |
| Simulation time | 7589174884 ps |
| CPU time | 395.7 seconds |
| Started | Aug 12 06:48:05 PM PDT 24 |
| Finished | Aug 12 06:54:40 PM PDT 24 |
| Peak memory | 576628 kb |
| Host | smart-3b522d46-a992-4676-afe2-38af4d7e4fc1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4216856424 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.xbar_stress_al l_with_reset_error.4216856424 |
| Directory | /workspace/12.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/default/0.chip_sw_rv_core_ibex_address_translation.1143902151 |
| Short name | T304 |
| Test name | |
| Test status | |
| Simulation time | 2809892336 ps |
| CPU time | 275.88 seconds |
| Started | Aug 12 07:08:40 PM PDT 24 |
| Finished | Aug 12 07:13:16 PM PDT 24 |
| Peak memory | 609000 kb |
| Host | smart-a1cf6e8e-da02-499a-a54e-d03ffab7f212 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=7_000_000 +sw_build_device=sim_dv +sw_images=rv_core_ibex_address_translation_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random _seed=1143902151 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_rv_core_ibex_address_translation.1143902151 |
| Directory | /workspace/0.chip_sw_rv_core_ibex_address_translation/latest |
| Test location | /workspace/coverage/cover_reg_top/9.xbar_access_same_device_slow_rsp.1648094554 |
| Short name | T1584 |
| Test name | |
| Test status | |
| Simulation time | 134854124544 ps |
| CPU time | 2298.38 seconds |
| Started | Aug 12 06:47:55 PM PDT 24 |
| Finished | Aug 12 07:26:14 PM PDT 24 |
| Peak memory | 575756 kb |
| Host | smart-8e606517-4b78-4938-99e8-ff026051f3f4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1648094554 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.xbar_access_same_d evice_slow_rsp.1648094554 |
| Directory | /workspace/9.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/default/0.chip_sw_sleep_pin_mio_dio_val.3900741618 |
| Short name | T9 |
| Test name | |
| Test status | |
| Simulation time | 3183029974 ps |
| CPU time | 355.8 seconds |
| Started | Aug 12 07:07:10 PM PDT 24 |
| Finished | Aug 12 07:13:06 PM PDT 24 |
| Peak memory | 610392 kb |
| Host | smart-f5c53ad7-eb6f-427e-ae6c-175ac325c84b |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStProd +sw_build_device=sim_dv +sw_images=sleep_pin_mio_dio_val_test:1:new_rules,test_rom:0 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3900 741618 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sleep_pin_mio_dio_val_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_sleep_pin_mio_dio_val.3900741618 |
| Directory | /workspace/0.chip_sw_sleep_pin_mio_dio_val/latest |
| Test location | /workspace/coverage/default/0.chip_plic_all_irqs_20.149321458 |
| Short name | T316 |
| Test name | |
| Test status | |
| Simulation time | 4658522264 ps |
| CPU time | 873.92 seconds |
| Started | Aug 12 07:11:28 PM PDT 24 |
| Finished | Aug 12 07:26:02 PM PDT 24 |
| Peak memory | 610508 kb |
| Host | smart-c9508fb9-acb8-4556-a5ed-81bd7b6489af |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=plic_all_irqs_test_20:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=149321458 -assert nopostproc +UVM_TESTNA ME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 0.chip_plic_all_irqs_20.149321458 |
| Directory | /workspace/0.chip_plic_all_irqs_20/latest |
| Test location | /workspace/coverage/cover_reg_top/59.xbar_access_same_device_slow_rsp.1275000939 |
| Short name | T921 |
| Test name | |
| Test status | |
| Simulation time | 45252549904 ps |
| CPU time | 687.68 seconds |
| Started | Aug 12 06:54:38 PM PDT 24 |
| Finished | Aug 12 07:06:06 PM PDT 24 |
| Peak memory | 575812 kb |
| Host | smart-cd215abb-b126-485f-9c1d-8b52357758a6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1275000939 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 59.xbar_access_same_ device_slow_rsp.1275000939 |
| Directory | /workspace/59.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/default/2.chip_sw_keymgr_sideload_otbn.235925421 |
| Short name | T227 |
| Test name | |
| Test status | |
| Simulation time | 15070314444 ps |
| CPU time | 3934.72 seconds |
| Started | Aug 12 07:27:06 PM PDT 24 |
| Finished | Aug 12 08:32:41 PM PDT 24 |
| Peak memory | 611328 kb |
| Host | smart-417ffc2d-5bbb-4d79-a4e1-c645cdc75777 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=20_000_000 +sw_build_device=sim_dv +sw_images=keymgr_sideload_otbn_test:1:new_rules,test_rom:0 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23592 5421 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_keymgr_sideload_otbn.235925421 |
| Directory | /workspace/2.chip_sw_keymgr_sideload_otbn/latest |
| Test location | /workspace/coverage/cover_reg_top/93.xbar_access_same_device_slow_rsp.1509575297 |
| Short name | T486 |
| Test name | |
| Test status | |
| Simulation time | 81756153588 ps |
| CPU time | 1451.15 seconds |
| Started | Aug 12 06:58:57 PM PDT 24 |
| Finished | Aug 12 07:23:09 PM PDT 24 |
| Peak memory | 575816 kb |
| Host | smart-f167a3bb-88b3-4f99-961d-fd36b9e860b3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1509575297 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 93.xbar_access_same_ device_slow_rsp.1509575297 |
| Directory | /workspace/93.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/96.xbar_access_same_device_slow_rsp.3917742669 |
| Short name | T536 |
| Test name | |
| Test status | |
| Simulation time | 136798977977 ps |
| CPU time | 2495.34 seconds |
| Started | Aug 12 06:59:10 PM PDT 24 |
| Finished | Aug 12 07:40:45 PM PDT 24 |
| Peak memory | 575820 kb |
| Host | smart-1e433244-e0d0-44c7-ba32-4f87381dc22b |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3917742669 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 96.xbar_access_same_ device_slow_rsp.3917742669 |
| Directory | /workspace/96.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/default/3.chip_sw_uart_tx_rx_idx2.230923510 |
| Short name | T4 |
| Test name | |
| Test status | |
| Simulation time | 3867568244 ps |
| CPU time | 621.78 seconds |
| Started | Aug 12 07:30:49 PM PDT 24 |
| Finished | Aug 12 07:41:12 PM PDT 24 |
| Peak memory | 623980 kb |
| Host | smart-7dca3f96-37ee-4b9c-8665-e3fb59f57801 |
| User | root |
| Command | /workspace/default/simv +uart_idx=2 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=230923510 -as sert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac e/coverage/default.vdb -cm_log /dev/null -cm_name 3.chip_sw_uart_tx_rx_idx2.230923510 |
| Directory | /workspace/3.chip_sw_uart_tx_rx_idx2/latest |
| Test location | /workspace/coverage/default/0.chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup.2436710733 |
| Short name | T142 |
| Test name | |
| Test status | |
| Simulation time | 5673261660 ps |
| CPU time | 506.91 seconds |
| Started | Aug 12 07:12:02 PM PDT 24 |
| Finished | Aug 12 07:20:29 PM PDT 24 |
| Peak memory | 609144 kb |
| Host | smart-39d67c2a-86ea-4240-bed9-b929bb6a9ee1 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=8_000_000 +sw_build_device=sim_dv +sw_images=sensor_ctrl_wakeup_test:1:new_rules,test_rom:0 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24367107 33 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac e/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup.2436710733 |
| Directory | /workspace/0.chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup/latest |
| Test location | /workspace/coverage/default/0.chip_plic_all_irqs_10.3462509024 |
| Short name | T167 |
| Test name | |
| Test status | |
| Simulation time | 4726833592 ps |
| CPU time | 621.89 seconds |
| Started | Aug 12 07:09:07 PM PDT 24 |
| Finished | Aug 12 07:19:29 PM PDT 24 |
| Peak memory | 609756 kb |
| Host | smart-0ef60fc9-65a1-4354-917d-637daa925f79 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=plic_all_irqs_test_10:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3462509024 -assert nopostproc +UVM_TESTN AME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log / dev/null -cm_name 0.chip_plic_all_irqs_10.3462509024 |
| Directory | /workspace/0.chip_plic_all_irqs_10/latest |
| Test location | /workspace/coverage/default/76.chip_sw_alert_handler_lpg_sleep_mode_alerts.4133447245 |
| Short name | T302 |
| Test name | |
| Test status | |
| Simulation time | 3330669918 ps |
| CPU time | 415.69 seconds |
| Started | Aug 12 07:40:36 PM PDT 24 |
| Finished | Aug 12 07:47:32 PM PDT 24 |
| Peak memory | 649424 kb |
| Host | smart-ad5d8757-eabe-4e9b-aad0-4d1141cb097a |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4133447245 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 76.chip_ sw_alert_handler_lpg_sleep_mode_alerts.4133447245 |
| Directory | /workspace/76.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/cover_reg_top/80.xbar_stress_all_with_error.1975454725 |
| Short name | T907 |
| Test name | |
| Test status | |
| Simulation time | 4237567182 ps |
| CPU time | 347.4 seconds |
| Started | Aug 12 06:57:12 PM PDT 24 |
| Finished | Aug 12 07:03:00 PM PDT 24 |
| Peak memory | 576572 kb |
| Host | smart-b7675ce2-1d3f-4590-a745-388f2f8eacf5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1975454725 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 80.xbar_stress_all_with_error.1975454725 |
| Directory | /workspace/80.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/25.chip_tl_errors.1212622487 |
| Short name | T581 |
| Test name | |
| Test status | |
| Simulation time | 4771507851 ps |
| CPU time | 401.57 seconds |
| Started | Aug 12 06:49:27 PM PDT 24 |
| Finished | Aug 12 06:56:08 PM PDT 24 |
| Peak memory | 603240 kb |
| Host | smart-336787ce-b409-43c0-8759-26c45b06ab7b |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1212622487 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.chip_tl_errors.1212622487 |
| Directory | /workspace/25.chip_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/24.xbar_stress_all_with_rand_reset.3440255885 |
| Short name | T80 |
| Test name | |
| Test status | |
| Simulation time | 2502281754 ps |
| CPU time | 116.79 seconds |
| Started | Aug 12 06:49:28 PM PDT 24 |
| Finished | Aug 12 06:51:25 PM PDT 24 |
| Peak memory | 575744 kb |
| Host | smart-13561200-3844-4694-b798-fe9daafe299b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3440255885 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.xbar_stress_all _with_rand_reset.3440255885 |
| Directory | /workspace/24.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/2.chip_same_csr_outstanding.2111468357 |
| Short name | T393 |
| Test name | |
| Test status | |
| Simulation time | 30218701153 ps |
| CPU time | 3734.06 seconds |
| Started | Aug 12 06:47:15 PM PDT 24 |
| Finished | Aug 12 07:49:30 PM PDT 24 |
| Peak memory | 593032 kb |
| Host | smart-37c26346-7c5c-46f5-8fdd-a0b3b0587850 |
| User | root |
| Command | /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +run_same_csr_outstanding +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2111468357 -assert nopostproc +UVM_TE STNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb - cm_log /dev/null -cm_name 2.chip_same_csr_outstanding.2111468357 |
| Directory | /workspace/2.chip_same_csr_outstanding/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_jtag_debug_rma.930340520 |
| Short name | T55 |
| Test name | |
| Test status | |
| Simulation time | 11774372862 ps |
| CPU time | 2007.48 seconds |
| Started | Aug 12 07:10:38 PM PDT 24 |
| Finished | Aug 12 07:44:06 PM PDT 24 |
| Peak memory | 624752 kb |
| Host | smart-a6af435e-4143-4ede-9b29-0656dad7d46d |
| User | root |
| Command | /workspace/default/simv +use_jtag_dmi=1 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=img_rma_exec_disabled:4,mask_rom:0 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=93034 0520 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rom_e2e_jtag_debug_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_jtag_debug_rma.930340520 |
| Directory | /workspace/0.rom_e2e_jtag_debug_rma/latest |
| Test location | /workspace/coverage/default/0.chip_sw_gpio_smoketest.2221955034 |
| Short name | T26 |
| Test name | |
| Test status | |
| Simulation time | 3507796944 ps |
| CPU time | 349.91 seconds |
| Started | Aug 12 07:11:44 PM PDT 24 |
| Finished | Aug 12 07:17:34 PM PDT 24 |
| Peak memory | 610304 kb |
| Host | smart-6ea7e464-ec75-46ea-9007-d9caa6fc435d |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=gpio_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2221955034 -assert nopostproc +UVM_TESTNAME=chi p_base_test +UVM_TEST_SEQ=chip_sw_gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 0.chip_sw_gpio_smoketest.2221955034 |
| Directory | /workspace/0.chip_sw_gpio_smoketest/latest |
| Test location | /workspace/coverage/default/1.chip_sw_sysrst_ctrl_reset.2697831925 |
| Short name | T22 |
| Test name | |
| Test status | |
| Simulation time | 23021540480 ps |
| CPU time | 1617.72 seconds |
| Started | Aug 12 07:15:57 PM PDT 24 |
| Finished | Aug 12 07:42:55 PM PDT 24 |
| Peak memory | 615376 kb |
| Host | smart-2cd4a65b-7962-46de-a2de-3f792f054c32 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=36_000_000 +sw_build_device=sim_dv +sw_images=sysrst_ctrl_reset_test:1:new_rules,test_rom:0 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26978319 25 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sysrst_ctrl_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_sysrst_ctrl_reset.2697831925 |
| Directory | /workspace/1.chip_sw_sysrst_ctrl_reset/latest |
| Test location | /workspace/coverage/default/2.chip_sw_sleep_pin_mio_dio_val.4000630215 |
| Short name | T11 |
| Test name | |
| Test status | |
| Simulation time | 2634793289 ps |
| CPU time | 318.18 seconds |
| Started | Aug 12 07:23:21 PM PDT 24 |
| Finished | Aug 12 07:28:40 PM PDT 24 |
| Peak memory | 610592 kb |
| Host | smart-7ea5ccc6-cd9a-401f-bcef-293a974ae7cb |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStProd +sw_build_device=sim_dv +sw_images=sleep_pin_mio_dio_val_test:1:new_rules,test_rom:0 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4000 630215 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sleep_pin_mio_dio_val_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_sleep_pin_mio_dio_val.4000630215 |
| Directory | /workspace/2.chip_sw_sleep_pin_mio_dio_val/latest |
| Test location | /workspace/coverage/default/0.chip_sw_flash_init_reduced_freq.34977123 |
| Short name | T241 |
| Test name | |
| Test status | |
| Simulation time | 19688524611 ps |
| CPU time | 1985.73 seconds |
| Started | Aug 12 07:08:15 PM PDT 24 |
| Finished | Aug 12 07:41:21 PM PDT 24 |
| Peak memory | 614996 kb |
| Host | smart-432ff9fb-9cb7-4722-a405-43ef9a8b3383 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=25_000_000 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=flash_init_test:0:test_in_rom:new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=34977123 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_flash_init_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_flash_init_reduced_freq.34977123 |
| Directory | /workspace/0.chip_sw_flash_init_reduced_freq/latest |
| Test location | /workspace/coverage/default/5.chip_sw_all_escalation_resets.371539482 |
| Short name | T248 |
| Test name | |
| Test status | |
| Simulation time | 5091010040 ps |
| CPU time | 678.72 seconds |
| Started | Aug 12 07:32:50 PM PDT 24 |
| Finished | Aug 12 07:44:10 PM PDT 24 |
| Peak memory | 650448 kb |
| Host | smart-f8f3d671-ce9f-4418-8909-1155ccedf648 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 371539482 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.chip_sw_all_escalation_resets.371539482 |
| Directory | /workspace/5.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/cover_reg_top/60.xbar_stress_all_with_error.611692123 |
| Short name | T920 |
| Test name | |
| Test status | |
| Simulation time | 14591695315 ps |
| CPU time | 495.59 seconds |
| Started | Aug 12 06:54:50 PM PDT 24 |
| Finished | Aug 12 07:03:06 PM PDT 24 |
| Peak memory | 575804 kb |
| Host | smart-f07aaf36-d945-4953-af70-6f228f35716d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=611692123 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 60.xbar_stress_all_with_error.611692123 |
| Directory | /workspace/60.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/0.xbar_random_large_delays.89703228 |
| Short name | T453 |
| Test name | |
| Test status | |
| Simulation time | 79698379539 ps |
| CPU time | 839.85 seconds |
| Started | Aug 12 06:47:06 PM PDT 24 |
| Finished | Aug 12 07:01:06 PM PDT 24 |
| Peak memory | 575688 kb |
| Host | smart-16501154-eee3-4539-a009-59259a94661e |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=89703228 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.xbar_random_large_delays.89703228 |
| Directory | /workspace/0.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/default/0.chip_sw_alert_handler_lpg_sleep_mode_pings.3703738840 |
| Short name | T83 |
| Test name | |
| Test status | |
| Simulation time | 11120730712 ps |
| CPU time | 1536 seconds |
| Started | Aug 12 07:09:40 PM PDT 24 |
| Finished | Aug 12 07:35:17 PM PDT 24 |
| Peak memory | 611428 kb |
| Host | smart-c5ebd679-9c85-480f-afa9-661f34c81f2b |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=alert_handler _lpg_sleep_mode_pings_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3703738840 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_alert_han dler_shorten_ping_wait_cycle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_alert_handler_lpg_sleep_mode_pings.3703738840 |
| Directory | /workspace/0.chip_sw_alert_handler_lpg_sleep_mode_pings/latest |
| Test location | /workspace/coverage/default/1.chip_sw_csrng_edn_concurrency_reduced_freq.3288012626 |
| Short name | T119 |
| Test name | |
| Test status | |
| Simulation time | 83832861238 ps |
| CPU time | 12174.2 seconds |
| Started | Aug 12 07:23:11 PM PDT 24 |
| Finished | Aug 12 10:46:06 PM PDT 24 |
| Peak memory | 610616 kb |
| Host | smart-3dedb274-d79e-4d21-bf3b-a40083281f52 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=360_000_000 +rng_srate_value_min=15 +rng_srate_value_max=20 +cal_sys_clk_70mhz=1 +en_jitter=1 +sw_build_de vice=sim_dv +sw_images=csrng_edn_concurrency_test:1:new_rules,test_rom:0 +accelerate_cold_power_up_time=3 +accelerate_regulators_power_up_time=2 + cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_ seed=3288012626 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_csrng_edn_concurrency_reduced_freq.3288012626 |
| Directory | /workspace/1.chip_sw_csrng_edn_concurrency_reduced_freq/latest |
| Test location | /workspace/coverage/default/49.chip_sw_all_escalation_resets.925708580 |
| Short name | T177 |
| Test name | |
| Test status | |
| Simulation time | 4532524352 ps |
| CPU time | 694.38 seconds |
| Started | Aug 12 07:38:04 PM PDT 24 |
| Finished | Aug 12 07:49:39 PM PDT 24 |
| Peak memory | 620412 kb |
| Host | smart-1e8fc079-dea4-4aba-92ba-88f82dd17af0 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 925708580 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.chip_sw_all_escalation_resets.925708580 |
| Directory | /workspace/49.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/1.chip_sw_pwrmgr_deep_sleep_all_wake_ups.768881432 |
| Short name | T19 |
| Test name | |
| Test status | |
| Simulation time | 21869449876 ps |
| CPU time | 1557.43 seconds |
| Started | Aug 12 07:23:57 PM PDT 24 |
| Finished | Aug 12 07:49:55 PM PDT 24 |
| Peak memory | 611484 kb |
| Host | smart-0e495602-c9b0-4f4d-9ed0-3cceb562a686 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=pwrmgr_deep_sleep_all_wake_ups:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 768881432 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_pwrmgr_deep_sleep_all_wake_ups_vseq +en_cov=1 -cm line+cond+fsm+tg l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_pwrmgr_deep_sleep_all_wake_ups.768881432 |
| Directory | /workspace/1.chip_sw_pwrmgr_deep_sleep_all_wake_ups/latest |
| Test location | /workspace/coverage/cover_reg_top/0.chip_tl_errors.34518311 |
| Short name | T579 |
| Test name | |
| Test status | |
| Simulation time | 4694530700 ps |
| CPU time | 327.28 seconds |
| Started | Aug 12 06:47:05 PM PDT 24 |
| Finished | Aug 12 06:52:32 PM PDT 24 |
| Peak memory | 603384 kb |
| Host | smart-140a7b76-774a-40bf-bfad-1a24fe8b7ae0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34518311 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.chip_tl_errors.34518311 |
| Directory | /workspace/0.chip_tl_errors/latest |
| Test location | /workspace/coverage/default/0.chip_sw_lc_walkthrough_prod.3819247359 |
| Short name | T176 |
| Test name | |
| Test status | |
| Simulation time | 51250152220 ps |
| CPU time | 6155.33 seconds |
| Started | Aug 12 07:07:06 PM PDT 24 |
| Finished | Aug 12 08:49:43 PM PDT 24 |
| Peak memory | 621048 kb |
| Host | smart-3aab25a1-f60c-49c7-8387-efba04de1784 |
| User | root |
| Command | /workspace/default/simv +flash_program_latency=5 +use_otp_image=OtpTypeLcStRaw +dest_dec_state=DecLcStProd +sw_test_timeout_ns=200_000_000 +sw_build_d evice=sim_dv +sw_images=lc_walkthrough_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3819247359 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ= chip_sw_lc_walkthrough_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chi p_sw_lc_walkthrough_prod.3819247359 |
| Directory | /workspace/0.chip_sw_lc_walkthrough_prod/latest |
| Test location | /workspace/coverage/default/1.chip_sw_sleep_pin_mio_dio_val.2396307412 |
| Short name | T10 |
| Test name | |
| Test status | |
| Simulation time | 3520166271 ps |
| CPU time | 170.74 seconds |
| Started | Aug 12 07:09:10 PM PDT 24 |
| Finished | Aug 12 07:12:01 PM PDT 24 |
| Peak memory | 610404 kb |
| Host | smart-1a827ce7-44b3-4c7f-9862-9f391499fc42 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStProd +sw_build_device=sim_dv +sw_images=sleep_pin_mio_dio_val_test:1:new_rules,test_rom:0 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2396 307412 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sleep_pin_mio_dio_val_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_sleep_pin_mio_dio_val.2396307412 |
| Directory | /workspace/1.chip_sw_sleep_pin_mio_dio_val/latest |
| Test location | /workspace/coverage/cover_reg_top/6.xbar_stress_all_with_reset_error.3492353001 |
| Short name | T696 |
| Test name | |
| Test status | |
| Simulation time | 12265828809 ps |
| CPU time | 614.21 seconds |
| Started | Aug 12 06:47:29 PM PDT 24 |
| Finished | Aug 12 06:57:43 PM PDT 24 |
| Peak memory | 577016 kb |
| Host | smart-de5c0c54-5e0f-4447-b444-910dba23b4e6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3492353001 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.xbar_stress_all _with_reset_error.3492353001 |
| Directory | /workspace/6.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/default/2.chip_sw_sram_ctrl_scrambled_access.3595531224 |
| Short name | T109 |
| Test name | |
| Test status | |
| Simulation time | 4982894888 ps |
| CPU time | 728.99 seconds |
| Started | Aug 12 07:28:07 PM PDT 24 |
| Finished | Aug 12 07:40:16 PM PDT 24 |
| Peak memory | 611328 kb |
| Host | smart-23e346fa-32de-4d91-a679-5f50450ebefc |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=12_000_000 +en_scb_tl_err_chk=0 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=sram _ctrl_scrambled_access_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3595531224 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sram_ctr l_scrambled_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw _sram_ctrl_scrambled_access.3595531224 |
| Directory | /workspace/2.chip_sw_sram_ctrl_scrambled_access/latest |
| Test location | /workspace/coverage/default/0.chip_jtag_csr_rw.2142854021 |
| Short name | T208 |
| Test name | |
| Test status | |
| Simulation time | 11893247711 ps |
| CPU time | 1311.03 seconds |
| Started | Aug 12 07:01:12 PM PDT 24 |
| Finished | Aug 12 07:23:03 PM PDT 24 |
| Peak memory | 608376 kb |
| Host | smart-eed8bf21-4add-4339-9011-a1d14d995059 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +csr_rw +create_jtag_riscv_map=1 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2142854021 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_T EST_SEQ=chip_jtag_csr_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.c hip_jtag_csr_rw.2142854021 |
| Directory | /workspace/0.chip_jtag_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/21.chip_tl_errors.307479263 |
| Short name | T408 |
| Test name | |
| Test status | |
| Simulation time | 5190006088 ps |
| CPU time | 416.65 seconds |
| Started | Aug 12 06:49:04 PM PDT 24 |
| Finished | Aug 12 06:56:01 PM PDT 24 |
| Peak memory | 603332 kb |
| Host | smart-d5cb9e82-7e8d-4028-9f57-1a138b2835a6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=307479263 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.chip_tl_errors.307479263 |
| Directory | /workspace/21.chip_tl_errors/latest |
| Test location | /workspace/coverage/default/0.chip_sw_flash_rma_unlocked.260983231 |
| Short name | T195 |
| Test name | |
| Test status | |
| Simulation time | 42717496352 ps |
| CPU time | 5324.08 seconds |
| Started | Aug 12 07:07:44 PM PDT 24 |
| Finished | Aug 12 08:36:29 PM PDT 24 |
| Peak memory | 622172 kb |
| Host | smart-c53b707b-da98-480c-b3c7-a3a6421454b8 |
| User | root |
| Command | /workspace/default/simv +flash_program_latency=5 +sw_test_timeout_ns=150_000_000 +sw_build_device=sim_dv +sw_images=flash_rma_unlocked_test:0:test_in_ rom:new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t cl +ntb_random_seed=260983231 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_flash_rma_unlocked_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_flash_rma_unlocked.260983231 |
| Directory | /workspace/0.chip_sw_flash_rma_unlocked/latest |
| Test location | /workspace/coverage/cover_reg_top/97.xbar_error_random.2084009528 |
| Short name | T79 |
| Test name | |
| Test status | |
| Simulation time | 278645336 ps |
| CPU time | 23.11 seconds |
| Started | Aug 12 06:59:19 PM PDT 24 |
| Finished | Aug 12 06:59:42 PM PDT 24 |
| Peak memory | 575668 kb |
| Host | smart-5d7f4fe5-65aa-4448-b50d-85cf0181da04 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2084009528 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 97.xbar_error_random.2084009528 |
| Directory | /workspace/97.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/2.chip_csr_hw_reset.3561818070 |
| Short name | T145 |
| Test name | |
| Test status | |
| Simulation time | 7585578131 ps |
| CPU time | 330.15 seconds |
| Started | Aug 12 06:47:18 PM PDT 24 |
| Finished | Aug 12 06:52:48 PM PDT 24 |
| Peak memory | 663752 kb |
| Host | smart-0d3be44b-dd5a-451f-ac74-bcbd00c5acb0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3561818070 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.chip_csr_hw_r eset.3561818070 |
| Directory | /workspace/2.chip_csr_hw_reset/latest |
| Test location | /workspace/coverage/default/2.chip_sw_data_integrity_escalation.3709700437 |
| Short name | T244 |
| Test name | |
| Test status | |
| Simulation time | 5687484132 ps |
| CPU time | 988.35 seconds |
| Started | Aug 12 07:21:57 PM PDT 24 |
| Finished | Aug 12 07:38:26 PM PDT 24 |
| Peak memory | 611552 kb |
| Host | smart-22eaf0b7-51a6-4ef6-b6b0-76105a654cf0 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=data_integrity_escalation_reset_test:1:new_rules,test_ro m:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=3709700437 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_data_integrity_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_data_integrity_escalation.3709700437 |
| Directory | /workspace/2.chip_sw_data_integrity_escalation/latest |
| Test location | /workspace/coverage/default/70.chip_sw_all_escalation_resets.2430176476 |
| Short name | T246 |
| Test name | |
| Test status | |
| Simulation time | 5460579368 ps |
| CPU time | 698.14 seconds |
| Started | Aug 12 07:40:35 PM PDT 24 |
| Finished | Aug 12 07:52:13 PM PDT 24 |
| Peak memory | 650396 kb |
| Host | smart-b7eb5c5e-97f4-4789-8db6-3be8c5fffc55 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 2430176476 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 70.chip_sw_all_escalation_resets.2430176476 |
| Directory | /workspace/70.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/0.chip_sw_lc_ctrl_rand_to_scrap.928275648 |
| Short name | T185 |
| Test name | |
| Test status | |
| Simulation time | 2279631562 ps |
| CPU time | 137.01 seconds |
| Started | Aug 12 07:07:45 PM PDT 24 |
| Finished | Aug 12 07:10:02 PM PDT 24 |
| Peak memory | 620372 kb |
| Host | smart-8b931e33-1354-49de-86ba-6a5302fde7e9 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=lc_ctrl_scrap_test:1:new_rules,test_rom:0 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=92827564 8 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_scrap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_lc_ctrl_rand_to_scrap.928275648 |
| Directory | /workspace/0.chip_sw_lc_ctrl_rand_to_scrap/latest |
| Test location | /workspace/coverage/default/81.chip_sw_all_escalation_resets.3407019566 |
| Short name | T317 |
| Test name | |
| Test status | |
| Simulation time | 4542659766 ps |
| CPU time | 555.97 seconds |
| Started | Aug 12 07:42:22 PM PDT 24 |
| Finished | Aug 12 07:51:38 PM PDT 24 |
| Peak memory | 650788 kb |
| Host | smart-b4bb2d71-4ee1-4054-aacd-e095002c80fe |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 3407019566 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 81.chip_sw_all_escalation_resets.3407019566 |
| Directory | /workspace/81.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/cover_reg_top/78.xbar_stress_all_with_rand_reset.2269842072 |
| Short name | T480 |
| Test name | |
| Test status | |
| Simulation time | 24961065023 ps |
| CPU time | 1408.59 seconds |
| Started | Aug 12 06:56:52 PM PDT 24 |
| Finished | Aug 12 07:20:21 PM PDT 24 |
| Peak memory | 575756 kb |
| Host | smart-aa5f9ba3-44eb-4d9e-bbbf-c309d9a91150 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2269842072 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 78.xbar_stress_all _with_rand_reset.2269842072 |
| Directory | /workspace/78.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/15.chip_sw_all_escalation_resets.1403818054 |
| Short name | T92 |
| Test name | |
| Test status | |
| Simulation time | 5414658896 ps |
| CPU time | 627.56 seconds |
| Started | Aug 12 07:34:26 PM PDT 24 |
| Finished | Aug 12 07:44:54 PM PDT 24 |
| Peak memory | 651188 kb |
| Host | smart-97e28965-2ff3-4705-a9e6-5731ca194a7c |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 1403818054 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.chip_sw_all_escalation_resets.1403818054 |
| Directory | /workspace/15.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/1.chip_sw_power_sleep_load.2402310674 |
| Short name | T117 |
| Test name | |
| Test status | |
| Simulation time | 5039243024 ps |
| CPU time | 426.11 seconds |
| Started | Aug 12 07:21:48 PM PDT 24 |
| Finished | Aug 12 07:28:55 PM PDT 24 |
| Peak memory | 609928 kb |
| Host | smart-7cbd93dc-43eb-41ed-ab5a-6abe44293773 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=chip_power_sleep_load:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2402310674 -assert nopostproc +UVM_TESTN AME=chip_base_test +UVM_TEST_SEQ=chip_sw_power_sleep_load_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v db -cm_log /dev/null -cm_name 1.chip_sw_power_sleep_load.2402310674 |
| Directory | /workspace/1.chip_sw_power_sleep_load/latest |
| Test location | /workspace/coverage/default/3.chip_sw_uart_tx_rx_alt_clk_freq.1590110399 |
| Short name | T127 |
| Test name | |
| Test status | |
| Simulation time | 13068707673 ps |
| CPU time | 2163.58 seconds |
| Started | Aug 12 07:33:19 PM PDT 24 |
| Finished | Aug 12 08:09:23 PM PDT 24 |
| Peak memory | 623868 kb |
| Host | smart-dd5cb959-8adc-4846-8688-49dbc7b8c125 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=80_000_000 +chip_clock_source=ChipClockSourceExternal96Mhz +calibrate_usb_clk=1 +sw_build_device=sim_dv +s w_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1590110399 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_b audrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.chip_sw_uart_tx_rx _alt_clk_freq.1590110399 |
| Directory | /workspace/3.chip_sw_uart_tx_rx_alt_clk_freq/latest |
| Test location | /workspace/coverage/default/1.chip_plic_all_irqs_0.1052720482 |
| Short name | T336 |
| Test name | |
| Test status | |
| Simulation time | 6022512628 ps |
| CPU time | 1561.6 seconds |
| Started | Aug 12 07:19:20 PM PDT 24 |
| Finished | Aug 12 07:45:22 PM PDT 24 |
| Peak memory | 610368 kb |
| Host | smart-f450dc35-ae80-41c5-a08c-519bcc48d363 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=plic_all_irqs_test_0:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1052720482 -assert nopostproc +UVM_TESTNA ME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 1.chip_plic_all_irqs_0.1052720482 |
| Directory | /workspace/1.chip_plic_all_irqs_0/latest |
| Test location | /workspace/coverage/default/0.chip_sw_spi_device_pinmux_sleep_retention.2094100465 |
| Short name | T64 |
| Test name | |
| Test status | |
| Simulation time | 3684975818 ps |
| CPU time | 308.9 seconds |
| Started | Aug 12 07:06:48 PM PDT 24 |
| Finished | Aug 12 07:11:58 PM PDT 24 |
| Peak memory | 619456 kb |
| Host | smart-35a677f6-ea44-465a-94e1-6232c6bfd680 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=spi_device_sleep_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2094100465 -assert nopostproc +UVM_TESTN AME=chip_base_test +UVM_TEST_SEQ=chip_sw_spi_device_pinmux_sleep_retention_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/c overage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_spi_device_pinmux_sleep_retention.2094100465 |
| Directory | /workspace/0.chip_sw_spi_device_pinmux_sleep_retention/latest |
| Test location | /workspace/coverage/default/2.chip_sw_sensor_ctrl_alert.1694923820 |
| Short name | T146 |
| Test name | |
| Test status | |
| Simulation time | 7186471032 ps |
| CPU time | 1016.21 seconds |
| Started | Aug 12 07:26:59 PM PDT 24 |
| Finished | Aug 12 07:43:55 PM PDT 24 |
| Peak memory | 609724 kb |
| Host | smart-159a3a17-706d-499a-9aba-c56bac15808a |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=40_000_000 +sw_build_device=sim_dv +sw_images=sensor_ctrl_alert_test:1:new_rules,test_rom:0 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16949238 20 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac e/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_sensor_ctrl_alert.1694923820 |
| Directory | /workspace/2.chip_sw_sensor_ctrl_alert/latest |
| Test location | /workspace/coverage/default/2.chip_sw_exit_test_unlocked_bootstrap.2009272961 |
| Short name | T71 |
| Test name | |
| Test status | |
| Simulation time | 59656232162 ps |
| CPU time | 10596.4 seconds |
| Started | Aug 12 07:22:44 PM PDT 24 |
| Finished | Aug 12 10:19:22 PM PDT 24 |
| Peak memory | 625200 kb |
| Host | smart-1b408d29-039d-4b4e-a8fb-518ab611d965 |
| User | root |
| Command | /workspace/default/simv +flash_program_latency=5 +sw_test_timeout_ns=150_000_000 +sw_build_device=sim_dv +sw_images=exit_test_unlocked_bootstrap:1:new _rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/s im.tcl +ntb_random_seed=2009272961 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_exit_test_unlocked_bootstrap_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_exit_test_unlocked_bootstrap.2009272961 |
| Directory | /workspace/2.chip_sw_exit_test_unlocked_bootstrap/latest |
| Test location | /workspace/coverage/default/0.chip_sw_usbdev_aon_pullup.3287732479 |
| Short name | T77 |
| Test name | |
| Test status | |
| Simulation time | 4017651996 ps |
| CPU time | 539.73 seconds |
| Started | Aug 12 07:07:29 PM PDT 24 |
| Finished | Aug 12 07:16:30 PM PDT 24 |
| Peak memory | 610180 kb |
| Host | smart-1a2e98e1-aa74-4a8d-aa83-821050b83997 |
| User | root |
| Command | /workspace/default/simv +uart_idx=0 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=usbdev_aon_pullup_test:1:new_rules,test_rom:0 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=328773 2479 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_usbdev_dpi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_usbdev_aon_pullup.3287732479 |
| Directory | /workspace/0.chip_sw_usbdev_aon_pullup/latest |
| Test location | /workspace/coverage/cover_reg_top/6.xbar_stress_all_with_rand_reset.3447266348 |
| Short name | T514 |
| Test name | |
| Test status | |
| Simulation time | 1647249665 ps |
| CPU time | 371.76 seconds |
| Started | Aug 12 06:47:30 PM PDT 24 |
| Finished | Aug 12 06:53:41 PM PDT 24 |
| Peak memory | 576524 kb |
| Host | smart-2c1d4c6e-e212-47cb-8ed0-929ab71543c6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3447266348 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.xbar_stress_all_ with_rand_reset.3447266348 |
| Directory | /workspace/6.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/2.chip_tap_straps_testunlock0.2423142823 |
| Short name | T67 |
| Test name | |
| Test status | |
| Simulation time | 5129647990 ps |
| CPU time | 404.42 seconds |
| Started | Aug 12 07:28:15 PM PDT 24 |
| Finished | Aug 12 07:35:00 PM PDT 24 |
| Peak memory | 625376 kb |
| Host | smart-9b5c3ee7-093f-4afc-b7e7-054c37b75a58 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStTestUnlocked0 +create_jtag_riscv_map=1 +sw_build_device=sim_dv +sw_images=example_test_from_rom:0:te st_in_rom:new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2423142823 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_tap_straps_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_tap_straps_testunlock0.2423142823 |
| Directory | /workspace/2.chip_tap_straps_testunlock0/latest |
| Test location | /workspace/coverage/default/0.chip_sw_sleep_pin_wake.603300908 |
| Short name | T116 |
| Test name | |
| Test status | |
| Simulation time | 4779724792 ps |
| CPU time | 446.1 seconds |
| Started | Aug 12 07:11:33 PM PDT 24 |
| Finished | Aug 12 07:19:00 PM PDT 24 |
| Peak memory | 611312 kb |
| Host | smart-e593c33a-e055-4785-8058-0600c0583422 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStProd +sw_build_device=sim_dv +sw_images=sleep_pin_wake_test:1:new_rules,test_rom:0 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=603300908 - assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sleep_pin_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_sleep_pin_wake.603300908 |
| Directory | /workspace/0.chip_sw_sleep_pin_wake/latest |
| Test location | /workspace/coverage/default/2.chip_sw_sleep_pin_wake.94415958 |
| Short name | T103 |
| Test name | |
| Test status | |
| Simulation time | 3438000920 ps |
| CPU time | 322 seconds |
| Started | Aug 12 07:23:13 PM PDT 24 |
| Finished | Aug 12 07:28:36 PM PDT 24 |
| Peak memory | 610388 kb |
| Host | smart-00409bd7-111a-4bd0-9c0b-00b8b53480fc |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStProd +sw_build_device=sim_dv +sw_images=sleep_pin_wake_test:1:new_rules,test_rom:0 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=94415958 -a ssert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sleep_pin_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_sleep_pin_wake.94415958 |
| Directory | /workspace/2.chip_sw_sleep_pin_wake/latest |
| Test location | /workspace/coverage/default/1.chip_sw_flash_ctrl_lc_rw_en.2006898987 |
| Short name | T182 |
| Test name | |
| Test status | |
| Simulation time | 5609609372 ps |
| CPU time | 557.31 seconds |
| Started | Aug 12 07:12:48 PM PDT 24 |
| Finished | Aug 12 07:22:05 PM PDT 24 |
| Peak memory | 610384 kb |
| Host | smart-c4cb9eaa-4e3d-495d-975d-83ff0fbc25ed |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=flash_ctrl_lc_rw_en_test:1:new_rules,test_rom:0 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20 06898987 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_flash_ctrl_lc_rw_en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_flash_ctrl_lc_rw_en.2006898987 |
| Directory | /workspace/1.chip_sw_flash_ctrl_lc_rw_en/latest |
| Test location | /workspace/coverage/pad_ctrl_test_mode/0.chip_padctrl_attributes.1635198973 |
| Short name | T42 |
| Test name | |
| Test status | |
| Simulation time | 5606872948 ps |
| CPU time | 305.46 seconds |
| Started | Aug 12 07:34:59 PM PDT 24 |
| Finished | Aug 12 07:40:04 PM PDT 24 |
| Peak memory | 657624 kb |
| Host | smart-c784b68c-2402-462e-b9d7-dde16d05e895 |
| User | root |
| Command | /workspace/pad_ctrl_test_mode/simv +use_otp_image=OtpTypeLcStProd +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1635198973 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TE ST_SEQ=chip_padctrl_attributes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/pad_ctrl_test_mode.vdb -cm_log /dev/ null -cm_name 0.chip_padctrl_attributes.1635198973 |
| Directory | /workspace/0.chip_padctrl_attributes/latest |
| Test location | /workspace/coverage/cover_reg_top/48.xbar_access_same_device.1371276171 |
| Short name | T922 |
| Test name | |
| Test status | |
| Simulation time | 657672030 ps |
| CPU time | 46.9 seconds |
| Started | Aug 12 06:52:59 PM PDT 24 |
| Finished | Aug 12 06:53:46 PM PDT 24 |
| Peak memory | 575560 kb |
| Host | smart-69f65d06-e61f-4e08-abf0-d0d63007d86e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1371276171 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.xbar_access_same_device .1371276171 |
| Directory | /workspace/48.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/38.xbar_stress_all_with_rand_reset.3995613207 |
| Short name | T481 |
| Test name | |
| Test status | |
| Simulation time | 3387300246 ps |
| CPU time | 394.46 seconds |
| Started | Aug 12 06:51:44 PM PDT 24 |
| Finished | Aug 12 06:58:18 PM PDT 24 |
| Peak memory | 576568 kb |
| Host | smart-0cac9825-c0c1-4306-a8db-2f5b94217e11 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3995613207 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.xbar_stress_all _with_rand_reset.3995613207 |
| Directory | /workspace/38.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/2.chip_sw_csrng_lc_hw_debug_en_test.1794724277 |
| Short name | T133 |
| Test name | |
| Test status | |
| Simulation time | 5304194824 ps |
| CPU time | 738.07 seconds |
| Started | Aug 12 07:27:24 PM PDT 24 |
| Finished | Aug 12 07:39:43 PM PDT 24 |
| Peak memory | 611736 kb |
| Host | smart-6fd20ba6-e154-4d75-a121-02c3167e283b |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=15_000_000 +rng_srate_value_min=15 +use_otp_image=OtpTypeLcStTestUnlocked0 +sw_build_device=sim_dv +sw_ima ges=csrng_lc_hw_debug_en_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1794724277 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_csrng_ lc_hw_debug_en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_csr ng_lc_hw_debug_en_test.1794724277 |
| Directory | /workspace/2.chip_sw_csrng_lc_hw_debug_en_test/latest |
| Test location | /workspace/coverage/default/1.chip_sw_flash_ctrl_ops_jitter_en_reduced_freq.4076752151 |
| Short name | T330 |
| Test name | |
| Test status | |
| Simulation time | 4769487608 ps |
| CPU time | 883.44 seconds |
| Started | Aug 12 07:20:29 PM PDT 24 |
| Finished | Aug 12 07:35:13 PM PDT 24 |
| Peak memory | 610400 kb |
| Host | smart-9c12a70e-ff48-4a62-a237-f4ac6d10e815 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=50_000_000 +en_jitter=1 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=flash_ctrl_ops_test:1:new_ rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si m.tcl +ntb_random_seed=4076752151 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_flash_ctrl_ops_jitter_en_reduced_freq.4076752151 |
| Directory | /workspace/1.chip_sw_flash_ctrl_ops_jitter_en_reduced_freq/latest |
| Test location | /workspace/coverage/cover_reg_top/24.chip_tl_errors.1558100847 |
| Short name | T774 |
| Test name | |
| Test status | |
| Simulation time | 4843027193 ps |
| CPU time | 463.05 seconds |
| Started | Aug 12 06:49:19 PM PDT 24 |
| Finished | Aug 12 06:57:02 PM PDT 24 |
| Peak memory | 603340 kb |
| Host | smart-5d954fc0-a54e-4929-801d-d29e448d4474 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1558100847 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.chip_tl_errors.1558100847 |
| Directory | /workspace/24.chip_tl_errors/latest |
| Test location | /workspace/coverage/default/2.chip_plic_all_irqs_0.2659487159 |
| Short name | T332 |
| Test name | |
| Test status | |
| Simulation time | 6025805950 ps |
| CPU time | 1405.2 seconds |
| Started | Aug 12 07:27:34 PM PDT 24 |
| Finished | Aug 12 07:51:00 PM PDT 24 |
| Peak memory | 609344 kb |
| Host | smart-3ecb94ec-c9bd-4b64-aee6-7659b51a7952 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=plic_all_irqs_test_0:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2659487159 -assert nopostproc +UVM_TESTNA ME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 2.chip_plic_all_irqs_0.2659487159 |
| Directory | /workspace/2.chip_plic_all_irqs_0/latest |
| Test location | /workspace/coverage/default/2.chip_plic_all_irqs_20.1778274820 |
| Short name | T99 |
| Test name | |
| Test status | |
| Simulation time | 4204107652 ps |
| CPU time | 823.75 seconds |
| Started | Aug 12 07:28:28 PM PDT 24 |
| Finished | Aug 12 07:42:12 PM PDT 24 |
| Peak memory | 610236 kb |
| Host | smart-3fc557ac-5f78-49ab-a8c7-cc20e9bac8bc |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=plic_all_irqs_test_20:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1778274820 -assert nopostproc +UVM_TESTN AME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log / dev/null -cm_name 2.chip_plic_all_irqs_20.1778274820 |
| Directory | /workspace/2.chip_plic_all_irqs_20/latest |
| Test location | /workspace/coverage/cover_reg_top/71.xbar_stress_all_with_rand_reset.3545355728 |
| Short name | T464 |
| Test name | |
| Test status | |
| Simulation time | 5452959041 ps |
| CPU time | 445.26 seconds |
| Started | Aug 12 06:55:59 PM PDT 24 |
| Finished | Aug 12 07:03:25 PM PDT 24 |
| Peak memory | 575772 kb |
| Host | smart-f8abab80-b4e6-4491-8191-07e857b7854a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3545355728 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 71.xbar_stress_all _with_rand_reset.3545355728 |
| Directory | /workspace/71.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/76.xbar_stress_all_with_rand_reset.3165557239 |
| Short name | T590 |
| Test name | |
| Test status | |
| Simulation time | 1087115477 ps |
| CPU time | 294.23 seconds |
| Started | Aug 12 06:56:42 PM PDT 24 |
| Finished | Aug 12 07:01:37 PM PDT 24 |
| Peak memory | 576548 kb |
| Host | smart-144dc2d6-72b3-459b-aeb6-8187b0088d24 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3165557239 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 76.xbar_stress_all _with_rand_reset.3165557239 |
| Directory | /workspace/76.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/1.chip_sw_flash_rma_unlocked.417541845 |
| Short name | T194 |
| Test name | |
| Test status | |
| Simulation time | 43303271693 ps |
| CPU time | 4486.53 seconds |
| Started | Aug 12 07:11:41 PM PDT 24 |
| Finished | Aug 12 08:26:29 PM PDT 24 |
| Peak memory | 621572 kb |
| Host | smart-d50b85cb-cfa7-435e-9948-b9d51ac947ef |
| User | root |
| Command | /workspace/default/simv +flash_program_latency=5 +sw_test_timeout_ns=150_000_000 +sw_build_device=sim_dv +sw_images=flash_rma_unlocked_test:0:test_in_ rom:new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t cl +ntb_random_seed=417541845 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_flash_rma_unlocked_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_flash_rma_unlocked.417541845 |
| Directory | /workspace/1.chip_sw_flash_rma_unlocked/latest |
| Test location | /workspace/coverage/default/1.chip_plic_all_irqs_20.4042733154 |
| Short name | T333 |
| Test name | |
| Test status | |
| Simulation time | 5042246612 ps |
| CPU time | 781.51 seconds |
| Started | Aug 12 07:19:13 PM PDT 24 |
| Finished | Aug 12 07:32:15 PM PDT 24 |
| Peak memory | 609736 kb |
| Host | smart-65038628-7e91-4cb4-bda0-a9b3e46fa0e1 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=plic_all_irqs_test_20:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4042733154 -assert nopostproc +UVM_TESTN AME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log / dev/null -cm_name 1.chip_plic_all_irqs_20.4042733154 |
| Directory | /workspace/1.chip_plic_all_irqs_20/latest |
| Test location | /workspace/coverage/default/0.chip_rv_dm_ndm_reset_req.1248138942 |
| Short name | T114 |
| Test name | |
| Test status | |
| Simulation time | 3912540856 ps |
| CPU time | 355.38 seconds |
| Started | Aug 12 07:09:47 PM PDT 24 |
| Finished | Aug 12 07:15:42 PM PDT 24 |
| Peak memory | 621156 kb |
| Host | smart-9d9f91cb-46e3-44e8-b637-f3118dbe3a70 |
| User | root |
| Command | /workspace/default/simv +en_scb_tl_err_chk=0 +use_jtag_dmi=1 +sw_build_device=sim_dv +sw_images=rv_dm_ndm_reset_req_rma:1:new_rules,test_rom:0 +cdc_in strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1 248138942 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_rv_dm_ndm_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_rv_dm_ndm_reset_req.1248138942 |
| Directory | /workspace/0.chip_rv_dm_ndm_reset_req/latest |
| Test location | /workspace/coverage/default/0.chip_sw_sensor_ctrl_alert.3779340327 |
| Short name | T143 |
| Test name | |
| Test status | |
| Simulation time | 6549167500 ps |
| CPU time | 777.02 seconds |
| Started | Aug 12 07:08:28 PM PDT 24 |
| Finished | Aug 12 07:21:26 PM PDT 24 |
| Peak memory | 609624 kb |
| Host | smart-78e75684-d9e6-42c0-b1d5-7be9db7ff964 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=40_000_000 +sw_build_device=sim_dv +sw_images=sensor_ctrl_alert_test:1:new_rules,test_rom:0 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37793403 27 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac e/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_sensor_ctrl_alert.3779340327 |
| Directory | /workspace/0.chip_sw_sensor_ctrl_alert/latest |
| Test location | /workspace/coverage/cover_reg_top/7.chip_same_csr_outstanding.2603425545 |
| Short name | T394 |
| Test name | |
| Test status | |
| Simulation time | 28988958250 ps |
| CPU time | 4077.99 seconds |
| Started | Aug 12 06:47:33 PM PDT 24 |
| Finished | Aug 12 07:55:31 PM PDT 24 |
| Peak memory | 592836 kb |
| Host | smart-be23e2ad-4c81-4b8c-9740-e264b5f66537 |
| User | root |
| Command | /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +run_same_csr_outstanding +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2603425545 -assert nopostproc +UVM_TE STNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb - cm_log /dev/null -cm_name 7.chip_same_csr_outstanding.2603425545 |
| Directory | /workspace/7.chip_same_csr_outstanding/latest |
| Test location | /workspace/coverage/default/22.chip_sw_all_escalation_resets.2922496536 |
| Short name | T66 |
| Test name | |
| Test status | |
| Simulation time | 5048858888 ps |
| CPU time | 631.86 seconds |
| Started | Aug 12 07:35:15 PM PDT 24 |
| Finished | Aug 12 07:45:47 PM PDT 24 |
| Peak memory | 650224 kb |
| Host | smart-edc8706d-da68-4b1c-8bd9-7759d73ac2e3 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 2922496536 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.chip_sw_all_escalation_resets.2922496536 |
| Directory | /workspace/22.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/cover_reg_top/29.xbar_stress_all.3857654086 |
| Short name | T450 |
| Test name | |
| Test status | |
| Simulation time | 1665111352 ps |
| CPU time | 126.21 seconds |
| Started | Aug 12 06:50:13 PM PDT 24 |
| Finished | Aug 12 06:52:19 PM PDT 24 |
| Peak memory | 575764 kb |
| Host | smart-a68f75b1-9eaf-4e3c-833b-ededb00ce7b6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3857654086 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.xbar_stress_all.3857654086 |
| Directory | /workspace/29.xbar_stress_all/latest |
| Test location | /workspace/coverage/default/2.chip_sw_otp_ctrl_vendor_test_csr_access.3718660824 |
| Short name | T173 |
| Test name | |
| Test status | |
| Simulation time | 2376038998 ps |
| CPU time | 206.39 seconds |
| Started | Aug 12 07:24:13 PM PDT 24 |
| Finished | Aug 12 07:27:40 PM PDT 24 |
| Peak memory | 623364 kb |
| Host | smart-17d34c07-9891-4ac3-af89-a5e6c3954484 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=otp_ctrl_vendor_test_csr_access_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3718660824 -assert nopost proc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_otp_ctrl_vendor_test_csr_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_otp_ctrl_vendor_test_csr_access.3718660824 |
| Directory | /workspace/2.chip_sw_otp_ctrl_vendor_test_csr_access/latest |
| Test location | /workspace/coverage/cover_reg_top/16.chip_tl_errors.200656012 |
| Short name | T630 |
| Test name | |
| Test status | |
| Simulation time | 3895103368 ps |
| CPU time | 300.48 seconds |
| Started | Aug 12 06:48:13 PM PDT 24 |
| Finished | Aug 12 06:53:14 PM PDT 24 |
| Peak memory | 603276 kb |
| Host | smart-9208a1fa-a6f3-48a3-83ef-8b17c310f218 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=200656012 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.chip_tl_errors.200656012 |
| Directory | /workspace/16.chip_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/62.xbar_stress_all_with_rand_reset.2765525986 |
| Short name | T1822 |
| Test name | |
| Test status | |
| Simulation time | 6875242336 ps |
| CPU time | 852.84 seconds |
| Started | Aug 12 06:54:59 PM PDT 24 |
| Finished | Aug 12 07:09:12 PM PDT 24 |
| Peak memory | 576588 kb |
| Host | smart-10fb9371-1fbf-43c6-84a5-971880ac4d3a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2765525986 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 62.xbar_stress_all _with_rand_reset.2765525986 |
| Directory | /workspace/62.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/35.xbar_stress_all_with_reset_error.3959959227 |
| Short name | T669 |
| Test name | |
| Test status | |
| Simulation time | 8572365385 ps |
| CPU time | 396.87 seconds |
| Started | Aug 12 06:51:35 PM PDT 24 |
| Finished | Aug 12 06:58:12 PM PDT 24 |
| Peak memory | 575776 kb |
| Host | smart-eb2636c9-586b-40cd-961d-2276b7d97d8d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3959959227 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.xbar_stress_al l_with_reset_error.3959959227 |
| Directory | /workspace/35.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/84.xbar_stress_all.950651003 |
| Short name | T251 |
| Test name | |
| Test status | |
| Simulation time | 4923083862 ps |
| CPU time | 165.86 seconds |
| Started | Aug 12 06:57:36 PM PDT 24 |
| Finished | Aug 12 07:00:22 PM PDT 24 |
| Peak memory | 576580 kb |
| Host | smart-a92ca5b2-8600-4462-83f0-a62a4ae4c381 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=950651003 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 84.xbar_stress_all.950651003 |
| Directory | /workspace/84.xbar_stress_all/latest |
| Test location | /workspace/coverage/default/2.chip_sw_flash_rma_unlocked.2053106821 |
| Short name | T196 |
| Test name | |
| Test status | |
| Simulation time | 42913878789 ps |
| CPU time | 5274.28 seconds |
| Started | Aug 12 07:23:16 PM PDT 24 |
| Finished | Aug 12 08:51:11 PM PDT 24 |
| Peak memory | 621364 kb |
| Host | smart-f877f7c9-dfd9-4bd3-9ead-8d91a188f54c |
| User | root |
| Command | /workspace/default/simv +flash_program_latency=5 +sw_test_timeout_ns=150_000_000 +sw_build_device=sim_dv +sw_images=flash_rma_unlocked_test:0:test_in_ rom:new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t cl +ntb_random_seed=2053106821 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_flash_rma_unlocked_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_flash_rma_unlocked.2053106821 |
| Directory | /workspace/2.chip_sw_flash_rma_unlocked/latest |
| Test location | /workspace/coverage/default/0.chip_sw_gpio.1539317068 |
| Short name | T29 |
| Test name | |
| Test status | |
| Simulation time | 4456735704 ps |
| CPU time | 464.99 seconds |
| Started | Aug 12 07:08:08 PM PDT 24 |
| Finished | Aug 12 07:15:53 PM PDT 24 |
| Peak memory | 609704 kb |
| Host | smart-8734950e-e950-4c38-98d2-dd791b2ed23b |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=gpio_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1539317068 -assert nopostproc +UVM_TESTNAME=chip_bas e_test +UVM_TEST_SEQ=chip_sw_gpio_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm _name 0.chip_sw_gpio.1539317068 |
| Directory | /workspace/0.chip_sw_gpio/latest |
| Test location | /workspace/coverage/cover_reg_top/3.chip_csr_hw_reset.138228602 |
| Short name | T152 |
| Test name | |
| Test status | |
| Simulation time | 6781650351 ps |
| CPU time | 328.95 seconds |
| Started | Aug 12 06:47:19 PM PDT 24 |
| Finished | Aug 12 06:52:48 PM PDT 24 |
| Peak memory | 661740 kb |
| Host | smart-ca2905f3-7fe6-4a03-86a7-8de692df36ef |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=138228602 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_c ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.chip_csr_hw_re set.138228602 |
| Directory | /workspace/3.chip_csr_hw_reset/latest |
| Test location | /workspace/coverage/default/0.chip_sw_adc_ctrl_sleep_debug_cable_wakeup.234286053 |
| Short name | T373 |
| Test name | |
| Test status | |
| Simulation time | 19339638072 ps |
| CPU time | 622.68 seconds |
| Started | Aug 12 07:12:04 PM PDT 24 |
| Finished | Aug 12 07:22:28 PM PDT 24 |
| Peak memory | 619864 kb |
| Host | smart-24b5e47c-aa65-45b0-b011-47fd43951b7d |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=adc_ctrl_sleep_debug_cable_wakeup_test:1:new_rules,test_rom: 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand om_seed=234286053 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_adc_ctrl_sleep_debug_cable_wakeup_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_adc_ctrl_sleep_debug_cable_wakeup.234286053 |
| Directory | /workspace/0.chip_sw_adc_ctrl_sleep_debug_cable_wakeup/latest |
| Test location | /workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_fast_dev.1239300172 |
| Short name | T1136 |
| Test name | |
| Test status | |
| Simulation time | 3891569390 ps |
| CPU time | 628.73 seconds |
| Started | Aug 12 07:11:59 PM PDT 24 |
| Finished | Aug 12 07:22:28 PM PDT 24 |
| Peak memory | 612508 kb |
| Host | smart-527022f5-d1eb-4215-b7ad-4173a4f8682f |
| User | root |
| Command | /workspace/default/simv +chip_clock_source=ChipClockSourceExternal96Mhz +calibrate_usb_clk=1 +src_dec_state=DecLcStDev +sw_build_device=sim_dv +sw_ima ges=clkmgr_external_clk_src_for_sw_fast_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1239300172 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ =chip_sw_lc_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_c lkmgr_external_clk_src_for_sw_fast_dev.1239300172 |
| Directory | /workspace/0.chip_sw_clkmgr_external_clk_src_for_sw_fast_dev/latest |
| Test location | /workspace/coverage/cover_reg_top/14.chip_tl_errors.4226339660 |
| Short name | T748 |
| Test name | |
| Test status | |
| Simulation time | 4720213308 ps |
| CPU time | 432.2 seconds |
| Started | Aug 12 06:48:02 PM PDT 24 |
| Finished | Aug 12 06:55:14 PM PDT 24 |
| Peak memory | 603332 kb |
| Host | smart-2c8a5334-e09c-4bca-86a8-86cdb0bb44ea |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4226339660 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.chip_tl_errors.4226339660 |
| Directory | /workspace/14.chip_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/13.xbar_stress_all_with_reset_error.3392518909 |
| Short name | T2394 |
| Test name | |
| Test status | |
| Simulation time | 4658853153 ps |
| CPU time | 222.38 seconds |
| Started | Aug 12 06:48:01 PM PDT 24 |
| Finished | Aug 12 06:51:44 PM PDT 24 |
| Peak memory | 576616 kb |
| Host | smart-869a15e4-b8a0-4994-aad7-e8ba38b6213c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3392518909 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.xbar_stress_al l_with_reset_error.3392518909 |
| Directory | /workspace/13.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/33.xbar_stress_all_with_reset_error.1654874010 |
| Short name | T943 |
| Test name | |
| Test status | |
| Simulation time | 301909690 ps |
| CPU time | 90.65 seconds |
| Started | Aug 12 06:51:34 PM PDT 24 |
| Finished | Aug 12 06:53:05 PM PDT 24 |
| Peak memory | 576508 kb |
| Host | smart-a897cf67-d980-4609-b33a-0ea8f5e5a04f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1654874010 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.xbar_stress_al l_with_reset_error.1654874010 |
| Directory | /workspace/33.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/54.xbar_stress_all_with_reset_error.3772438966 |
| Short name | T946 |
| Test name | |
| Test status | |
| Simulation time | 1858387042 ps |
| CPU time | 169.81 seconds |
| Started | Aug 12 06:53:48 PM PDT 24 |
| Finished | Aug 12 06:56:38 PM PDT 24 |
| Peak memory | 575696 kb |
| Host | smart-5383a374-c4a0-4599-991a-dd18970c3be3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3772438966 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 54.xbar_stress_al l_with_reset_error.3772438966 |
| Directory | /workspace/54.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/default/0.chip_sw_uart_tx_rx_idx3.1121457281 |
| Short name | T1204 |
| Test name | |
| Test status | |
| Simulation time | 4044142024 ps |
| CPU time | 693.21 seconds |
| Started | Aug 12 07:08:15 PM PDT 24 |
| Finished | Aug 12 07:19:50 PM PDT 24 |
| Peak memory | 624284 kb |
| Host | smart-04374437-c22a-44f6-9f32-8a8e128a624d |
| User | root |
| Command | /workspace/default/simv +uart_idx=3 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1121457281 -a ssert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ce/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_uart_tx_rx_idx3.1121457281 |
| Directory | /workspace/0.chip_sw_uart_tx_rx_idx3/latest |
| Test location | /workspace/coverage/default/0.chip_sw_uart_tx_rx.3216361274 |
| Short name | T1077 |
| Test name | |
| Test status | |
| Simulation time | 3913731496 ps |
| CPU time | 640.55 seconds |
| Started | Aug 12 07:07:08 PM PDT 24 |
| Finished | Aug 12 07:17:49 PM PDT 24 |
| Peak memory | 624304 kb |
| Host | smart-7a7f40df-a620-4a3b-9bf2-3261ecf50bde |
| User | root |
| Command | /workspace/default/simv +uart_idx=0 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3216361274 -a ssert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ce/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_uart_tx_rx.3216361274 |
| Directory | /workspace/0.chip_sw_uart_tx_rx/latest |
| Test location | /workspace/coverage/default/84.chip_sw_alert_handler_lpg_sleep_mode_alerts.308435949 |
| Short name | T318 |
| Test name | |
| Test status | |
| Simulation time | 3509396280 ps |
| CPU time | 372.81 seconds |
| Started | Aug 12 07:41:29 PM PDT 24 |
| Finished | Aug 12 07:47:42 PM PDT 24 |
| Peak memory | 649272 kb |
| Host | smart-15501775-4e9a-4317-ba3c-a77cc9e29072 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=308435949 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all _escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 84.chip_s w_alert_handler_lpg_sleep_mode_alerts.308435949 |
| Directory | /workspace/84.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/0.chip_sw_pwrmgr_random_sleep_all_reset_reqs.1685716668 |
| Short name | T259 |
| Test name | |
| Test status | |
| Simulation time | 27103198609 ps |
| CPU time | 2405.45 seconds |
| Started | Aug 12 07:09:04 PM PDT 24 |
| Finished | Aug 12 07:49:11 PM PDT 24 |
| Peak memory | 611992 kb |
| Host | smart-161acbe4-1dbb-4ff2-857c-ba42fdd4bfd8 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=50_000_000 +sw_build_device=sim_dv +sw_images=pwrmgr_random_sleep_all_reset_reqs_test:1:new_rules,test_rom :0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=1685716668 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_deep_sleep_all_reset_vseq +en_cov=1 -cm line+cond+fsm+tg l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_pwrmgr_random_sleep_all_reset_reqs.1685716668 |
| Directory | /workspace/0.chip_sw_pwrmgr_random_sleep_all_reset_reqs/latest |
| Test location | /workspace/coverage/default/1.chip_sw_sysrst_ctrl_ulp_z3_wakeup.1176161601 |
| Short name | T39 |
| Test name | |
| Test status | |
| Simulation time | 6025685138 ps |
| CPU time | 444.45 seconds |
| Started | Aug 12 07:16:35 PM PDT 24 |
| Finished | Aug 12 07:24:01 PM PDT 24 |
| Peak memory | 610296 kb |
| Host | smart-77e5cd38-fe04-4faa-9dcb-db78047f5677 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=sysrst_ctrl_ulp_z3_wakeup_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1176161601 -assert nopostproc + UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sysrst_ctrl_ulp_z3_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/ coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_sysrst_ctrl_ulp_z3_wakeup.1176161601 |
| Directory | /workspace/1.chip_sw_sysrst_ctrl_ulp_z3_wakeup/latest |
| Test location | /workspace/coverage/default/0.chip_sw_otp_ctrl_vendor_test_csr_access.1558890160 |
| Short name | T172 |
| Test name | |
| Test status | |
| Simulation time | 3156364704 ps |
| CPU time | 279.4 seconds |
| Started | Aug 12 07:07:46 PM PDT 24 |
| Finished | Aug 12 07:12:26 PM PDT 24 |
| Peak memory | 623332 kb |
| Host | smart-4688a053-9a6e-4205-a8ac-24bac63c46a9 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=otp_ctrl_vendor_test_csr_access_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1558890160 -assert nopost proc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_otp_ctrl_vendor_test_csr_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_otp_ctrl_vendor_test_csr_access.1558890160 |
| Directory | /workspace/0.chip_sw_otp_ctrl_vendor_test_csr_access/latest |
| Test location | /workspace/coverage/default/0.chip_sw_spi_device_pass_through_collision.831231071 |
| Short name | T205 |
| Test name | |
| Test status | |
| Simulation time | 4790191807 ps |
| CPU time | 574.84 seconds |
| Started | Aug 12 07:08:15 PM PDT 24 |
| Finished | Aug 12 07:17:50 PM PDT 24 |
| Peak memory | 625184 kb |
| Host | smart-8fa9946e-013b-4d23-95f1-e257ac19cc22 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=spi_passthrough_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=831231071 -assert nopostproc +UVM_TESTNAM E=chip_base_test +UVM_TEST_SEQ=chip_sw_spi_passthrough_collision_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de fault.vdb -cm_log /dev/null -cm_name 0.chip_sw_spi_device_pass_through_collision.831231071 |
| Directory | /workspace/0.chip_sw_spi_device_pass_through_collision/latest |
| Test location | /workspace/coverage/default/11.chip_sw_alert_handler_lpg_sleep_mode_alerts.2161768624 |
| Short name | T319 |
| Test name | |
| Test status | |
| Simulation time | 4183672236 ps |
| CPU time | 405.72 seconds |
| Started | Aug 12 07:34:56 PM PDT 24 |
| Finished | Aug 12 07:41:42 PM PDT 24 |
| Peak memory | 649444 kb |
| Host | smart-090b9154-c865-4454-848c-2b0e4cdd8956 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2161768624 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.chip_ sw_alert_handler_lpg_sleep_mode_alerts.2161768624 |
| Directory | /workspace/11.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/13.chip_sw_all_escalation_resets.777605001 |
| Short name | T203 |
| Test name | |
| Test status | |
| Simulation time | 4746030114 ps |
| CPU time | 622.72 seconds |
| Started | Aug 12 07:34:38 PM PDT 24 |
| Finished | Aug 12 07:45:01 PM PDT 24 |
| Peak memory | 650392 kb |
| Host | smart-541738e0-a7be-4785-89d8-cca968443411 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 777605001 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.chip_sw_all_escalation_resets.777605001 |
| Directory | /workspace/13.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/41.chip_sw_all_escalation_resets.3255361994 |
| Short name | T815 |
| Test name | |
| Test status | |
| Simulation time | 5620520586 ps |
| CPU time | 649.99 seconds |
| Started | Aug 12 07:37:45 PM PDT 24 |
| Finished | Aug 12 07:48:36 PM PDT 24 |
| Peak memory | 650184 kb |
| Host | smart-2fc6b5dd-6524-4876-b17c-c45e1f054008 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 3255361994 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.chip_sw_all_escalation_resets.3255361994 |
| Directory | /workspace/41.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/cover_reg_top/10.xbar_stress_all_with_rand_reset.2562064343 |
| Short name | T2231 |
| Test name | |
| Test status | |
| Simulation time | 947155831 ps |
| CPU time | 311.9 seconds |
| Started | Aug 12 06:47:44 PM PDT 24 |
| Finished | Aug 12 06:52:56 PM PDT 24 |
| Peak memory | 575704 kb |
| Host | smart-74216179-037a-4680-96d6-83174f1bb3b2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2562064343 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.xbar_stress_all _with_rand_reset.2562064343 |
| Directory | /workspace/10.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/78.xbar_stress_all.3585048841 |
| Short name | T2412 |
| Test name | |
| Test status | |
| Simulation time | 12021840602 ps |
| CPU time | 408.39 seconds |
| Started | Aug 12 06:56:50 PM PDT 24 |
| Finished | Aug 12 07:03:39 PM PDT 24 |
| Peak memory | 576592 kb |
| Host | smart-d1af0217-0f38-4fb2-8330-438183e7f933 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3585048841 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 78.xbar_stress_all.3585048841 |
| Directory | /workspace/78.xbar_stress_all/latest |
| Test location | /workspace/coverage/default/1.chip_plic_all_irqs_10.153131605 |
| Short name | T168 |
| Test name | |
| Test status | |
| Simulation time | 4165424072 ps |
| CPU time | 661.02 seconds |
| Started | Aug 12 07:17:25 PM PDT 24 |
| Finished | Aug 12 07:28:27 PM PDT 24 |
| Peak memory | 609704 kb |
| Host | smart-5fdef606-f499-4358-b984-88c65968fa94 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=plic_all_irqs_test_10:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=153131605 -assert nopostproc +UVM_TESTNA ME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 1.chip_plic_all_irqs_10.153131605 |
| Directory | /workspace/1.chip_plic_all_irqs_10/latest |
| Test location | /workspace/coverage/default/38.chip_sw_all_escalation_resets.1238408252 |
| Short name | T362 |
| Test name | |
| Test status | |
| Simulation time | 4849935196 ps |
| CPU time | 746 seconds |
| Started | Aug 12 07:36:41 PM PDT 24 |
| Finished | Aug 12 07:49:07 PM PDT 24 |
| Peak memory | 650580 kb |
| Host | smart-a51c24fb-a7da-4134-9d3a-801898b18a8b |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 1238408252 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.chip_sw_all_escalation_resets.1238408252 |
| Directory | /workspace/38.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/0.chip_sw_usbdev_config_host.1371217808 |
| Short name | T20 |
| Test name | |
| Test status | |
| Simulation time | 7973885996 ps |
| CPU time | 2032.15 seconds |
| Started | Aug 12 07:07:28 PM PDT 24 |
| Finished | Aug 12 07:41:21 PM PDT 24 |
| Peak memory | 610636 kb |
| Host | smart-38c606dc-2b5e-4592-9766-7b1711685a1b |
| User | root |
| Command | /workspace/default/simv +uart_idx=0 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=usbdev_config_host_test:1:new_rules,test_rom:0 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13712 17808 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_usbdev_dpi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_usbdev_config_host.1371217808 |
| Directory | /workspace/0.chip_sw_usbdev_config_host/latest |
| Test location | /workspace/coverage/cover_reg_top/0.xbar_stress_all_with_rand_reset.4154437531 |
| Short name | T2071 |
| Test name | |
| Test status | |
| Simulation time | 352372101 ps |
| CPU time | 110.53 seconds |
| Started | Aug 12 06:47:16 PM PDT 24 |
| Finished | Aug 12 06:49:06 PM PDT 24 |
| Peak memory | 575680 kb |
| Host | smart-d9e22bac-473c-4069-8218-49b834eb913c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4154437531 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.xbar_stress_all_ with_rand_reset.4154437531 |
| Directory | /workspace/0.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/20.xbar_stress_all_with_rand_reset.4126375090 |
| Short name | T1850 |
| Test name | |
| Test status | |
| Simulation time | 3031355359 ps |
| CPU time | 335.97 seconds |
| Started | Aug 12 06:49:01 PM PDT 24 |
| Finished | Aug 12 06:54:37 PM PDT 24 |
| Peak memory | 575764 kb |
| Host | smart-4bac8894-7de9-4890-b097-b45900de858d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4126375090 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.xbar_stress_all _with_rand_reset.4126375090 |
| Directory | /workspace/20.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/7.chip_csr_mem_rw_with_rand_reset.1185680758 |
| Short name | T806 |
| Test name | |
| Test status | |
| Simulation time | 6381863336 ps |
| CPU time | 475.81 seconds |
| Started | Aug 12 06:47:30 PM PDT 24 |
| Finished | Aug 12 06:55:26 PM PDT 24 |
| Peak memory | 637040 kb |
| Host | smart-a56f7277-3a9c-4e0c-9f40-5dc42dc183cb |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1185680758 -assert nopostproc + UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top .vdb -cm_log /dev/null -cm_name 7.chip_csr_mem_rw_with_rand_reset.1185680758 |
| Directory | /workspace/7.chip_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/default/0.chip_sw_alert_handler_lpg_sleep_mode_alerts.2551566899 |
| Short name | T322 |
| Test name | |
| Test status | |
| Simulation time | 3672952692 ps |
| CPU time | 443.8 seconds |
| Started | Aug 12 07:10:11 PM PDT 24 |
| Finished | Aug 12 07:17:35 PM PDT 24 |
| Peak memory | 649192 kb |
| Host | smart-4d0f4911-7dad-4f0a-bd85-c10d190e5e84 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2551566899 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_s w_alert_handler_lpg_sleep_mode_alerts.2551566899 |
| Directory | /workspace/0.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/1.chip_sw_alert_handler_lpg_sleep_mode_alerts.1836200016 |
| Short name | T1336 |
| Test name | |
| Test status | |
| Simulation time | 3733705098 ps |
| CPU time | 467.87 seconds |
| Started | Aug 12 07:15:21 PM PDT 24 |
| Finished | Aug 12 07:23:09 PM PDT 24 |
| Peak memory | 649320 kb |
| Host | smart-fcb5ab40-7f99-45dc-9e83-ba8d1c3537f0 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1836200016 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_s w_alert_handler_lpg_sleep_mode_alerts.1836200016 |
| Directory | /workspace/1.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/1.chip_sw_all_escalation_resets.3919412107 |
| Short name | T880 |
| Test name | |
| Test status | |
| Simulation time | 6105933464 ps |
| CPU time | 664.48 seconds |
| Started | Aug 12 07:11:46 PM PDT 24 |
| Finished | Aug 12 07:22:51 PM PDT 24 |
| Peak memory | 650508 kb |
| Host | smart-ebde0899-81b4-4cab-b4b2-da0e65543508 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 3919412107 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_all_escalation_resets.3919412107 |
| Directory | /workspace/1.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/10.chip_sw_alert_handler_lpg_sleep_mode_alerts.3702617695 |
| Short name | T94 |
| Test name | |
| Test status | |
| Simulation time | 3649861840 ps |
| CPU time | 411.16 seconds |
| Started | Aug 12 07:33:54 PM PDT 24 |
| Finished | Aug 12 07:40:45 PM PDT 24 |
| Peak memory | 649836 kb |
| Host | smart-b9754dd8-07bd-4b1d-82e1-aeff027a4162 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3702617695 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.chip_ sw_alert_handler_lpg_sleep_mode_alerts.3702617695 |
| Directory | /workspace/10.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/12.chip_sw_alert_handler_lpg_sleep_mode_alerts.2654781414 |
| Short name | T836 |
| Test name | |
| Test status | |
| Simulation time | 4490682400 ps |
| CPU time | 325.33 seconds |
| Started | Aug 12 07:35:02 PM PDT 24 |
| Finished | Aug 12 07:40:28 PM PDT 24 |
| Peak memory | 649992 kb |
| Host | smart-19d20060-13b0-4766-ab5f-ee4514ef7ea6 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2654781414 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.chip_ sw_alert_handler_lpg_sleep_mode_alerts.2654781414 |
| Directory | /workspace/12.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/12.chip_sw_all_escalation_resets.1873385429 |
| Short name | T1144 |
| Test name | |
| Test status | |
| Simulation time | 6035114500 ps |
| CPU time | 653.45 seconds |
| Started | Aug 12 07:34:19 PM PDT 24 |
| Finished | Aug 12 07:45:13 PM PDT 24 |
| Peak memory | 650492 kb |
| Host | smart-4a3f4bed-e041-49a2-96f6-bc76bc7de590 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 1873385429 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.chip_sw_all_escalation_resets.1873385429 |
| Directory | /workspace/12.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/13.chip_sw_alert_handler_lpg_sleep_mode_alerts.4196804087 |
| Short name | T810 |
| Test name | |
| Test status | |
| Simulation time | 4158645544 ps |
| CPU time | 365.07 seconds |
| Started | Aug 12 07:34:12 PM PDT 24 |
| Finished | Aug 12 07:40:18 PM PDT 24 |
| Peak memory | 649532 kb |
| Host | smart-1f6a9bd3-8692-4da2-9d8d-d6e8cd86376f |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4196804087 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.chip_ sw_alert_handler_lpg_sleep_mode_alerts.4196804087 |
| Directory | /workspace/13.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/14.chip_sw_alert_handler_lpg_sleep_mode_alerts.3864259607 |
| Short name | T848 |
| Test name | |
| Test status | |
| Simulation time | 4040822640 ps |
| CPU time | 445.25 seconds |
| Started | Aug 12 07:35:26 PM PDT 24 |
| Finished | Aug 12 07:42:52 PM PDT 24 |
| Peak memory | 649348 kb |
| Host | smart-c49f7e40-2313-4f42-a1bb-3c4899e5f0c8 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3864259607 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.chip_ sw_alert_handler_lpg_sleep_mode_alerts.3864259607 |
| Directory | /workspace/14.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/14.chip_sw_all_escalation_resets.989262839 |
| Short name | T862 |
| Test name | |
| Test status | |
| Simulation time | 4866162668 ps |
| CPU time | 641.92 seconds |
| Started | Aug 12 07:34:44 PM PDT 24 |
| Finished | Aug 12 07:45:26 PM PDT 24 |
| Peak memory | 650628 kb |
| Host | smart-7fc131eb-52ce-4e8a-a478-3cbc5ea6b84e |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 989262839 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.chip_sw_all_escalation_resets.989262839 |
| Directory | /workspace/14.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/15.chip_sw_alert_handler_lpg_sleep_mode_alerts.2968199804 |
| Short name | T387 |
| Test name | |
| Test status | |
| Simulation time | 3492731934 ps |
| CPU time | 350.52 seconds |
| Started | Aug 12 07:34:40 PM PDT 24 |
| Finished | Aug 12 07:40:30 PM PDT 24 |
| Peak memory | 649056 kb |
| Host | smart-a4319bc3-f0bf-41ec-b410-73704d254400 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2968199804 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.chip_ sw_alert_handler_lpg_sleep_mode_alerts.2968199804 |
| Directory | /workspace/15.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/16.chip_sw_alert_handler_lpg_sleep_mode_alerts.3142047968 |
| Short name | T828 |
| Test name | |
| Test status | |
| Simulation time | 4047504756 ps |
| CPU time | 415.54 seconds |
| Started | Aug 12 07:35:50 PM PDT 24 |
| Finished | Aug 12 07:42:46 PM PDT 24 |
| Peak memory | 649384 kb |
| Host | smart-6f9d37b9-850f-4518-9772-4c3ccdda8051 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3142047968 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.chip_ sw_alert_handler_lpg_sleep_mode_alerts.3142047968 |
| Directory | /workspace/16.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/17.chip_sw_alert_handler_lpg_sleep_mode_alerts.1005902276 |
| Short name | T796 |
| Test name | |
| Test status | |
| Simulation time | 3411514928 ps |
| CPU time | 341.45 seconds |
| Started | Aug 12 07:35:01 PM PDT 24 |
| Finished | Aug 12 07:40:43 PM PDT 24 |
| Peak memory | 649328 kb |
| Host | smart-8000ffea-22c8-4ec6-81e2-c1a4838f9af2 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1005902276 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.chip_ sw_alert_handler_lpg_sleep_mode_alerts.1005902276 |
| Directory | /workspace/17.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/18.chip_sw_all_escalation_resets.2533544962 |
| Short name | T845 |
| Test name | |
| Test status | |
| Simulation time | 4982593268 ps |
| CPU time | 726.76 seconds |
| Started | Aug 12 07:35:16 PM PDT 24 |
| Finished | Aug 12 07:47:24 PM PDT 24 |
| Peak memory | 650536 kb |
| Host | smart-2a94070d-a81e-44cd-8910-02b140008033 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 2533544962 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.chip_sw_all_escalation_resets.2533544962 |
| Directory | /workspace/18.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/19.chip_sw_all_escalation_resets.515255893 |
| Short name | T865 |
| Test name | |
| Test status | |
| Simulation time | 4682462720 ps |
| CPU time | 579.59 seconds |
| Started | Aug 12 07:36:42 PM PDT 24 |
| Finished | Aug 12 07:46:22 PM PDT 24 |
| Peak memory | 650292 kb |
| Host | smart-636ad2d6-14c6-45e0-a492-17d5ada66ada |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 515255893 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.chip_sw_all_escalation_resets.515255893 |
| Directory | /workspace/19.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/2.chip_sw_alert_handler_lpg_sleep_mode_alerts.3585752486 |
| Short name | T442 |
| Test name | |
| Test status | |
| Simulation time | 3652744040 ps |
| CPU time | 372.08 seconds |
| Started | Aug 12 07:28:52 PM PDT 24 |
| Finished | Aug 12 07:35:04 PM PDT 24 |
| Peak memory | 649640 kb |
| Host | smart-bf3efaca-208c-4aa1-86b9-4108f44b09f0 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3585752486 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_s w_alert_handler_lpg_sleep_mode_alerts.3585752486 |
| Directory | /workspace/2.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/2.chip_sw_all_escalation_resets.32525141 |
| Short name | T831 |
| Test name | |
| Test status | |
| Simulation time | 5702299160 ps |
| CPU time | 676.23 seconds |
| Started | Aug 12 07:22:02 PM PDT 24 |
| Finished | Aug 12 07:33:18 PM PDT 24 |
| Peak memory | 650788 kb |
| Host | smart-96e5b73e-fc29-413c-8fff-e16df9e2c3cd |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 32525141 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_all_escalation_resets.32525141 |
| Directory | /workspace/2.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/20.chip_sw_alert_handler_lpg_sleep_mode_alerts.2122907687 |
| Short name | T834 |
| Test name | |
| Test status | |
| Simulation time | 4227680130 ps |
| CPU time | 405.44 seconds |
| Started | Aug 12 07:35:17 PM PDT 24 |
| Finished | Aug 12 07:42:03 PM PDT 24 |
| Peak memory | 649628 kb |
| Host | smart-6576bdda-a2c6-4d89-b149-580efd10b25a |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2122907687 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.chip_ sw_alert_handler_lpg_sleep_mode_alerts.2122907687 |
| Directory | /workspace/20.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/20.chip_sw_all_escalation_resets.4177882647 |
| Short name | T864 |
| Test name | |
| Test status | |
| Simulation time | 5879052856 ps |
| CPU time | 689.21 seconds |
| Started | Aug 12 07:35:09 PM PDT 24 |
| Finished | Aug 12 07:46:39 PM PDT 24 |
| Peak memory | 650348 kb |
| Host | smart-1fa245c4-c9d2-4cd0-b6a5-e699d02e7729 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 4177882647 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.chip_sw_all_escalation_resets.4177882647 |
| Directory | /workspace/20.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/21.chip_sw_all_escalation_resets.135166798 |
| Short name | T888 |
| Test name | |
| Test status | |
| Simulation time | 5522691080 ps |
| CPU time | 588.4 seconds |
| Started | Aug 12 07:35:20 PM PDT 24 |
| Finished | Aug 12 07:45:08 PM PDT 24 |
| Peak memory | 650468 kb |
| Host | smart-29e9e542-72d0-4ecb-9aa7-9190c500f36b |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 135166798 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.chip_sw_all_escalation_resets.135166798 |
| Directory | /workspace/21.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/23.chip_sw_alert_handler_lpg_sleep_mode_alerts.3504371874 |
| Short name | T872 |
| Test name | |
| Test status | |
| Simulation time | 3717871430 ps |
| CPU time | 370.32 seconds |
| Started | Aug 12 07:35:51 PM PDT 24 |
| Finished | Aug 12 07:42:01 PM PDT 24 |
| Peak memory | 649048 kb |
| Host | smart-2bf5572f-1c95-4354-8a78-913125a4a392 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3504371874 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.chip_ sw_alert_handler_lpg_sleep_mode_alerts.3504371874 |
| Directory | /workspace/23.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/23.chip_sw_all_escalation_resets.2171993644 |
| Short name | T270 |
| Test name | |
| Test status | |
| Simulation time | 4880042188 ps |
| CPU time | 586.5 seconds |
| Started | Aug 12 07:35:08 PM PDT 24 |
| Finished | Aug 12 07:44:54 PM PDT 24 |
| Peak memory | 650732 kb |
| Host | smart-9f6a2566-6f72-4063-a8f5-d166f8e53aed |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 2171993644 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.chip_sw_all_escalation_resets.2171993644 |
| Directory | /workspace/23.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/24.chip_sw_alert_handler_lpg_sleep_mode_alerts.1120945283 |
| Short name | T879 |
| Test name | |
| Test status | |
| Simulation time | 3649909736 ps |
| CPU time | 315.79 seconds |
| Started | Aug 12 07:35:24 PM PDT 24 |
| Finished | Aug 12 07:40:40 PM PDT 24 |
| Peak memory | 649364 kb |
| Host | smart-a164c077-6c7b-4e70-bb0e-81f25d8da3c3 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1120945283 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.chip_ sw_alert_handler_lpg_sleep_mode_alerts.1120945283 |
| Directory | /workspace/24.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/25.chip_sw_all_escalation_resets.442927021 |
| Short name | T101 |
| Test name | |
| Test status | |
| Simulation time | 5508191202 ps |
| CPU time | 588.12 seconds |
| Started | Aug 12 07:36:27 PM PDT 24 |
| Finished | Aug 12 07:46:15 PM PDT 24 |
| Peak memory | 650848 kb |
| Host | smart-c4d74710-0237-45d3-b8fd-970247c704ee |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 442927021 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.chip_sw_all_escalation_resets.442927021 |
| Directory | /workspace/25.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/26.chip_sw_alert_handler_lpg_sleep_mode_alerts.3483109965 |
| Short name | T797 |
| Test name | |
| Test status | |
| Simulation time | 4186217416 ps |
| CPU time | 381.83 seconds |
| Started | Aug 12 07:35:43 PM PDT 24 |
| Finished | Aug 12 07:42:06 PM PDT 24 |
| Peak memory | 649276 kb |
| Host | smart-351117f5-df7e-423b-bb3e-15e32ca4144f |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3483109965 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.chip_ sw_alert_handler_lpg_sleep_mode_alerts.3483109965 |
| Directory | /workspace/26.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/26.chip_sw_all_escalation_resets.3702520546 |
| Short name | T843 |
| Test name | |
| Test status | |
| Simulation time | 5443862018 ps |
| CPU time | 627.37 seconds |
| Started | Aug 12 07:35:07 PM PDT 24 |
| Finished | Aug 12 07:45:35 PM PDT 24 |
| Peak memory | 650520 kb |
| Host | smart-b007ac04-40fc-4ba2-84fb-6fd042be884e |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 3702520546 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.chip_sw_all_escalation_resets.3702520546 |
| Directory | /workspace/26.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/27.chip_sw_alert_handler_lpg_sleep_mode_alerts.2621965159 |
| Short name | T826 |
| Test name | |
| Test status | |
| Simulation time | 4264325382 ps |
| CPU time | 466.96 seconds |
| Started | Aug 12 07:37:11 PM PDT 24 |
| Finished | Aug 12 07:44:58 PM PDT 24 |
| Peak memory | 649208 kb |
| Host | smart-bb420288-f91c-4725-8e53-7d1d3e25fb1b |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2621965159 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.chip_ sw_alert_handler_lpg_sleep_mode_alerts.2621965159 |
| Directory | /workspace/27.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/29.chip_sw_alert_handler_lpg_sleep_mode_alerts.811831372 |
| Short name | T1116 |
| Test name | |
| Test status | |
| Simulation time | 4287350150 ps |
| CPU time | 439.37 seconds |
| Started | Aug 12 07:36:00 PM PDT 24 |
| Finished | Aug 12 07:43:20 PM PDT 24 |
| Peak memory | 649400 kb |
| Host | smart-fb419dc5-ce09-46a7-89cf-b2fd577ccecc |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=811831372 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all _escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.chip_s w_alert_handler_lpg_sleep_mode_alerts.811831372 |
| Directory | /workspace/29.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/29.chip_sw_all_escalation_resets.3356117173 |
| Short name | T873 |
| Test name | |
| Test status | |
| Simulation time | 5577614782 ps |
| CPU time | 661.2 seconds |
| Started | Aug 12 07:36:54 PM PDT 24 |
| Finished | Aug 12 07:47:55 PM PDT 24 |
| Peak memory | 650548 kb |
| Host | smart-484aa118-4792-4a84-8ed2-8b655060754a |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 3356117173 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.chip_sw_all_escalation_resets.3356117173 |
| Directory | /workspace/29.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/3.chip_sw_alert_handler_lpg_sleep_mode_alerts.2277940008 |
| Short name | T854 |
| Test name | |
| Test status | |
| Simulation time | 4229526672 ps |
| CPU time | 482.55 seconds |
| Started | Aug 12 07:33:20 PM PDT 24 |
| Finished | Aug 12 07:41:22 PM PDT 24 |
| Peak memory | 649324 kb |
| Host | smart-2a6c4c36-2f4a-42df-b37c-8f6fa73c3032 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2277940008 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.chip_s w_alert_handler_lpg_sleep_mode_alerts.2277940008 |
| Directory | /workspace/3.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/3.chip_sw_all_escalation_resets.880900866 |
| Short name | T782 |
| Test name | |
| Test status | |
| Simulation time | 4828100316 ps |
| CPU time | 525.8 seconds |
| Started | Aug 12 07:30:57 PM PDT 24 |
| Finished | Aug 12 07:39:43 PM PDT 24 |
| Peak memory | 650528 kb |
| Host | smart-b641e166-c589-4550-9c73-6921fc18f172 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 880900866 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.chip_sw_all_escalation_resets.880900866 |
| Directory | /workspace/3.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/31.chip_sw_all_escalation_resets.3726609492 |
| Short name | T884 |
| Test name | |
| Test status | |
| Simulation time | 4302936728 ps |
| CPU time | 447.2 seconds |
| Started | Aug 12 07:37:01 PM PDT 24 |
| Finished | Aug 12 07:44:29 PM PDT 24 |
| Peak memory | 648892 kb |
| Host | smart-8c69635a-4bd0-45b3-a0d1-e1b80b0ff5a4 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 3726609492 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.chip_sw_all_escalation_resets.3726609492 |
| Directory | /workspace/31.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/32.chip_sw_all_escalation_resets.3832388930 |
| Short name | T858 |
| Test name | |
| Test status | |
| Simulation time | 4245140312 ps |
| CPU time | 548.42 seconds |
| Started | Aug 12 07:35:41 PM PDT 24 |
| Finished | Aug 12 07:44:50 PM PDT 24 |
| Peak memory | 650280 kb |
| Host | smart-2ce4d92d-e67e-4d17-a562-602dbb796a88 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 3832388930 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.chip_sw_all_escalation_resets.3832388930 |
| Directory | /workspace/32.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/33.chip_sw_all_escalation_resets.1337480728 |
| Short name | T795 |
| Test name | |
| Test status | |
| Simulation time | 4810022412 ps |
| CPU time | 577.76 seconds |
| Started | Aug 12 07:36:27 PM PDT 24 |
| Finished | Aug 12 07:46:05 PM PDT 24 |
| Peak memory | 650380 kb |
| Host | smart-1d9e3914-1a5d-409a-b679-e485539c5e2b |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 1337480728 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.chip_sw_all_escalation_resets.1337480728 |
| Directory | /workspace/33.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/35.chip_sw_alert_handler_lpg_sleep_mode_alerts.2621372852 |
| Short name | T852 |
| Test name | |
| Test status | |
| Simulation time | 4407717320 ps |
| CPU time | 560.42 seconds |
| Started | Aug 12 07:38:04 PM PDT 24 |
| Finished | Aug 12 07:47:25 PM PDT 24 |
| Peak memory | 649392 kb |
| Host | smart-54f9cb52-a9d1-4e4e-a78d-4c2c9a2bfe4b |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2621372852 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.chip_ sw_alert_handler_lpg_sleep_mode_alerts.2621372852 |
| Directory | /workspace/35.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/38.chip_sw_alert_handler_lpg_sleep_mode_alerts.2189940270 |
| Short name | T881 |
| Test name | |
| Test status | |
| Simulation time | 4007352036 ps |
| CPU time | 362.09 seconds |
| Started | Aug 12 07:36:51 PM PDT 24 |
| Finished | Aug 12 07:42:53 PM PDT 24 |
| Peak memory | 649084 kb |
| Host | smart-e4ebae8d-7817-4b73-a8ad-5be890d11924 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2189940270 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.chip_ sw_alert_handler_lpg_sleep_mode_alerts.2189940270 |
| Directory | /workspace/38.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/4.chip_sw_all_escalation_resets.2593107897 |
| Short name | T800 |
| Test name | |
| Test status | |
| Simulation time | 4597211640 ps |
| CPU time | 758.81 seconds |
| Started | Aug 12 07:33:51 PM PDT 24 |
| Finished | Aug 12 07:46:30 PM PDT 24 |
| Peak memory | 650360 kb |
| Host | smart-bf8a6fcf-a3e0-400b-acfa-4eb20bbb3cc7 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 2593107897 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.chip_sw_all_escalation_resets.2593107897 |
| Directory | /workspace/4.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/40.chip_sw_alert_handler_lpg_sleep_mode_alerts.617270327 |
| Short name | T818 |
| Test name | |
| Test status | |
| Simulation time | 4438201362 ps |
| CPU time | 417.15 seconds |
| Started | Aug 12 07:37:09 PM PDT 24 |
| Finished | Aug 12 07:44:06 PM PDT 24 |
| Peak memory | 649660 kb |
| Host | smart-63a6d511-601d-4ac8-9633-526647c996ce |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=617270327 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all _escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.chip_s w_alert_handler_lpg_sleep_mode_alerts.617270327 |
| Directory | /workspace/40.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/43.chip_sw_alert_handler_lpg_sleep_mode_alerts.1852525247 |
| Short name | T869 |
| Test name | |
| Test status | |
| Simulation time | 3943667664 ps |
| CPU time | 476.29 seconds |
| Started | Aug 12 07:37:37 PM PDT 24 |
| Finished | Aug 12 07:45:33 PM PDT 24 |
| Peak memory | 649444 kb |
| Host | smart-b80ca37d-2373-4016-904a-c2a115d6811f |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1852525247 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.chip_ sw_alert_handler_lpg_sleep_mode_alerts.1852525247 |
| Directory | /workspace/43.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/44.chip_sw_all_escalation_resets.247171187 |
| Short name | T1419 |
| Test name | |
| Test status | |
| Simulation time | 5616109728 ps |
| CPU time | 594.13 seconds |
| Started | Aug 12 07:36:42 PM PDT 24 |
| Finished | Aug 12 07:46:37 PM PDT 24 |
| Peak memory | 650440 kb |
| Host | smart-73e43ca0-493b-4286-810f-791a83544326 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 247171187 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.chip_sw_all_escalation_resets.247171187 |
| Directory | /workspace/44.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/46.chip_sw_alert_handler_lpg_sleep_mode_alerts.426845132 |
| Short name | T812 |
| Test name | |
| Test status | |
| Simulation time | 4386208914 ps |
| CPU time | 387.67 seconds |
| Started | Aug 12 07:38:01 PM PDT 24 |
| Finished | Aug 12 07:44:29 PM PDT 24 |
| Peak memory | 649472 kb |
| Host | smart-350f71d6-1d61-41d8-a765-49f702a8c287 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=426845132 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all _escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.chip_s w_alert_handler_lpg_sleep_mode_alerts.426845132 |
| Directory | /workspace/46.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/47.chip_sw_alert_handler_lpg_sleep_mode_alerts.2109348949 |
| Short name | T825 |
| Test name | |
| Test status | |
| Simulation time | 3632689770 ps |
| CPU time | 417.6 seconds |
| Started | Aug 12 07:38:45 PM PDT 24 |
| Finished | Aug 12 07:45:43 PM PDT 24 |
| Peak memory | 649364 kb |
| Host | smart-e8ad7423-4f74-4e77-a419-a1794a604440 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2109348949 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.chip_ sw_alert_handler_lpg_sleep_mode_alerts.2109348949 |
| Directory | /workspace/47.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/48.chip_sw_all_escalation_resets.4164451415 |
| Short name | T821 |
| Test name | |
| Test status | |
| Simulation time | 5055942528 ps |
| CPU time | 661.26 seconds |
| Started | Aug 12 07:38:07 PM PDT 24 |
| Finished | Aug 12 07:49:08 PM PDT 24 |
| Peak memory | 650456 kb |
| Host | smart-b691213a-ef7f-4926-b21e-548d5915b2fc |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 4164451415 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.chip_sw_all_escalation_resets.4164451415 |
| Directory | /workspace/48.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/50.chip_sw_alert_handler_lpg_sleep_mode_alerts.1031144356 |
| Short name | T822 |
| Test name | |
| Test status | |
| Simulation time | 4218865516 ps |
| CPU time | 431.6 seconds |
| Started | Aug 12 07:39:06 PM PDT 24 |
| Finished | Aug 12 07:46:18 PM PDT 24 |
| Peak memory | 649316 kb |
| Host | smart-281e38fb-07da-4f55-a08b-1fa9a7f4ec1b |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1031144356 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 50.chip_ sw_alert_handler_lpg_sleep_mode_alerts.1031144356 |
| Directory | /workspace/50.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/50.chip_sw_all_escalation_resets.4039793404 |
| Short name | T298 |
| Test name | |
| Test status | |
| Simulation time | 4310603144 ps |
| CPU time | 477.13 seconds |
| Started | Aug 12 07:38:45 PM PDT 24 |
| Finished | Aug 12 07:46:42 PM PDT 24 |
| Peak memory | 650200 kb |
| Host | smart-942b48d0-bf10-49af-8650-dd377a0fea73 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 4039793404 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 50.chip_sw_all_escalation_resets.4039793404 |
| Directory | /workspace/50.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/52.chip_sw_alert_handler_lpg_sleep_mode_alerts.790591048 |
| Short name | T892 |
| Test name | |
| Test status | |
| Simulation time | 3950124960 ps |
| CPU time | 437.01 seconds |
| Started | Aug 12 07:39:16 PM PDT 24 |
| Finished | Aug 12 07:46:33 PM PDT 24 |
| Peak memory | 649212 kb |
| Host | smart-c3095bf9-8925-4970-89db-0545b2e08527 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=790591048 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all _escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 52.chip_s w_alert_handler_lpg_sleep_mode_alerts.790591048 |
| Directory | /workspace/52.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/52.chip_sw_all_escalation_resets.2343681360 |
| Short name | T803 |
| Test name | |
| Test status | |
| Simulation time | 6182075080 ps |
| CPU time | 596.11 seconds |
| Started | Aug 12 07:38:04 PM PDT 24 |
| Finished | Aug 12 07:48:00 PM PDT 24 |
| Peak memory | 650128 kb |
| Host | smart-3bbfc8d3-1ade-4ec6-8470-ad9a131188f9 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 2343681360 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 52.chip_sw_all_escalation_resets.2343681360 |
| Directory | /workspace/52.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/54.chip_sw_alert_handler_lpg_sleep_mode_alerts.3211318572 |
| Short name | T807 |
| Test name | |
| Test status | |
| Simulation time | 3433095358 ps |
| CPU time | 364.5 seconds |
| Started | Aug 12 07:38:32 PM PDT 24 |
| Finished | Aug 12 07:44:36 PM PDT 24 |
| Peak memory | 649392 kb |
| Host | smart-2277bd43-00cb-4c27-825a-75de9ba0f4a9 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3211318572 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 54.chip_ sw_alert_handler_lpg_sleep_mode_alerts.3211318572 |
| Directory | /workspace/54.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/55.chip_sw_alert_handler_lpg_sleep_mode_alerts.1365295415 |
| Short name | T833 |
| Test name | |
| Test status | |
| Simulation time | 3942330680 ps |
| CPU time | 497.14 seconds |
| Started | Aug 12 07:42:34 PM PDT 24 |
| Finished | Aug 12 07:50:52 PM PDT 24 |
| Peak memory | 649600 kb |
| Host | smart-87368d67-4f67-4117-898f-64daa2741b93 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1365295415 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 55.chip_ sw_alert_handler_lpg_sleep_mode_alerts.1365295415 |
| Directory | /workspace/55.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/57.chip_sw_all_escalation_resets.3956761437 |
| Short name | T886 |
| Test name | |
| Test status | |
| Simulation time | 5470746000 ps |
| CPU time | 730.99 seconds |
| Started | Aug 12 07:39:07 PM PDT 24 |
| Finished | Aug 12 07:51:19 PM PDT 24 |
| Peak memory | 650256 kb |
| Host | smart-da5235e9-96e5-436e-ba48-d41419a57273 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 3956761437 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 57.chip_sw_all_escalation_resets.3956761437 |
| Directory | /workspace/57.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/60.chip_sw_all_escalation_resets.3799736104 |
| Short name | T875 |
| Test name | |
| Test status | |
| Simulation time | 5012937160 ps |
| CPU time | 498.28 seconds |
| Started | Aug 12 07:38:54 PM PDT 24 |
| Finished | Aug 12 07:47:13 PM PDT 24 |
| Peak memory | 650280 kb |
| Host | smart-c9c3fc19-b057-4364-84ff-6fe6b964d1a0 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 3799736104 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 60.chip_sw_all_escalation_resets.3799736104 |
| Directory | /workspace/60.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/63.chip_sw_all_escalation_resets.511706914 |
| Short name | T847 |
| Test name | |
| Test status | |
| Simulation time | 5621211832 ps |
| CPU time | 779.15 seconds |
| Started | Aug 12 07:40:19 PM PDT 24 |
| Finished | Aug 12 07:53:18 PM PDT 24 |
| Peak memory | 650476 kb |
| Host | smart-91ffb8b2-fec7-48ad-b02a-fd63720aac0d |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 511706914 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 63.chip_sw_all_escalation_resets.511706914 |
| Directory | /workspace/63.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/66.chip_sw_alert_handler_lpg_sleep_mode_alerts.4117349826 |
| Short name | T835 |
| Test name | |
| Test status | |
| Simulation time | 3294505604 ps |
| CPU time | 429.97 seconds |
| Started | Aug 12 07:39:50 PM PDT 24 |
| Finished | Aug 12 07:47:00 PM PDT 24 |
| Peak memory | 649660 kb |
| Host | smart-3ba10a88-8f64-4575-bb02-651e06dbadbb |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4117349826 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 66.chip_ sw_alert_handler_lpg_sleep_mode_alerts.4117349826 |
| Directory | /workspace/66.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/7.chip_sw_all_escalation_resets.2689390212 |
| Short name | T412 |
| Test name | |
| Test status | |
| Simulation time | 5829951892 ps |
| CPU time | 643.46 seconds |
| Started | Aug 12 07:32:38 PM PDT 24 |
| Finished | Aug 12 07:43:22 PM PDT 24 |
| Peak memory | 650824 kb |
| Host | smart-d085b844-54b4-4026-b583-476ee6e6050b |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 2689390212 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.chip_sw_all_escalation_resets.2689390212 |
| Directory | /workspace/7.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/73.chip_sw_alert_handler_lpg_sleep_mode_alerts.3798296635 |
| Short name | T274 |
| Test name | |
| Test status | |
| Simulation time | 3606018324 ps |
| CPU time | 312.12 seconds |
| Started | Aug 12 07:41:27 PM PDT 24 |
| Finished | Aug 12 07:46:39 PM PDT 24 |
| Peak memory | 649400 kb |
| Host | smart-a074d677-516d-4de5-a011-510b7e54f178 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3798296635 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 73.chip_ sw_alert_handler_lpg_sleep_mode_alerts.3798296635 |
| Directory | /workspace/73.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/74.chip_sw_alert_handler_lpg_sleep_mode_alerts.4015136667 |
| Short name | T804 |
| Test name | |
| Test status | |
| Simulation time | 3548167252 ps |
| CPU time | 364.2 seconds |
| Started | Aug 12 07:41:07 PM PDT 24 |
| Finished | Aug 12 07:47:11 PM PDT 24 |
| Peak memory | 649456 kb |
| Host | smart-6567e992-0ed2-43b4-869e-1c8b23c741f3 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4015136667 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 74.chip_ sw_alert_handler_lpg_sleep_mode_alerts.4015136667 |
| Directory | /workspace/74.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/75.chip_sw_alert_handler_lpg_sleep_mode_alerts.1495654525 |
| Short name | T791 |
| Test name | |
| Test status | |
| Simulation time | 3193855560 ps |
| CPU time | 351.15 seconds |
| Started | Aug 12 07:40:23 PM PDT 24 |
| Finished | Aug 12 07:46:15 PM PDT 24 |
| Peak memory | 649296 kb |
| Host | smart-b812c952-ad29-415f-aa12-b0820a8f0d05 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1495654525 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 75.chip_ sw_alert_handler_lpg_sleep_mode_alerts.1495654525 |
| Directory | /workspace/75.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/77.chip_sw_alert_handler_lpg_sleep_mode_alerts.448550249 |
| Short name | T859 |
| Test name | |
| Test status | |
| Simulation time | 3420132304 ps |
| CPU time | 430 seconds |
| Started | Aug 12 07:41:12 PM PDT 24 |
| Finished | Aug 12 07:48:22 PM PDT 24 |
| Peak memory | 649424 kb |
| Host | smart-8f6bba8f-8b17-444b-aeb8-30be2eb3f872 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=448550249 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all _escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 77.chip_s w_alert_handler_lpg_sleep_mode_alerts.448550249 |
| Directory | /workspace/77.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/79.chip_sw_alert_handler_lpg_sleep_mode_alerts.1753938398 |
| Short name | T780 |
| Test name | |
| Test status | |
| Simulation time | 3537028664 ps |
| CPU time | 361.95 seconds |
| Started | Aug 12 07:39:59 PM PDT 24 |
| Finished | Aug 12 07:46:01 PM PDT 24 |
| Peak memory | 649348 kb |
| Host | smart-bd6c16ff-8787-429c-b472-9db7a3a259d5 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1753938398 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 79.chip_ sw_alert_handler_lpg_sleep_mode_alerts.1753938398 |
| Directory | /workspace/79.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/94.chip_sw_all_escalation_resets.2606893093 |
| Short name | T893 |
| Test name | |
| Test status | |
| Simulation time | 5165048004 ps |
| CPU time | 565 seconds |
| Started | Aug 12 07:43:11 PM PDT 24 |
| Finished | Aug 12 07:52:36 PM PDT 24 |
| Peak memory | 650492 kb |
| Host | smart-f2d048fb-a859-4e3c-96fd-48a35558c9fb |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 2606893093 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 94.chip_sw_all_escalation_resets.2606893093 |
| Directory | /workspace/94.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/97.chip_sw_all_escalation_resets.2858990519 |
| Short name | T793 |
| Test name | |
| Test status | |
| Simulation time | 4810919480 ps |
| CPU time | 578.23 seconds |
| Started | Aug 12 07:41:37 PM PDT 24 |
| Finished | Aug 12 07:51:16 PM PDT 24 |
| Peak memory | 650468 kb |
| Host | smart-e07db966-4966-4cb6-ae1b-a9f3d6d7518d |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 2858990519 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 97.chip_sw_all_escalation_resets.2858990519 |
| Directory | /workspace/97.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/0.chip_sw_sram_ctrl_execution_main.2937206047 |
| Short name | T314 |
| Test name | |
| Test status | |
| Simulation time | 6644681171 ps |
| CPU time | 596.66 seconds |
| Started | Aug 12 07:12:11 PM PDT 24 |
| Finished | Aug 12 07:22:07 PM PDT 24 |
| Peak memory | 610100 kb |
| Host | smart-fc425f28-abe8-45c6-9365-b60c14f8080b |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=sram_ctrl_execution_main_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2937206047 -assert nopostproc +U VM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sram_ctrl_execution_main_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co verage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_sram_ctrl_execution_main.2937206047 |
| Directory | /workspace/0.chip_sw_sram_ctrl_execution_main/latest |
| Test location | /workspace/coverage/default/0.chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up.476747321 |
| Short name | T385 |
| Test name | |
| Test status | |
| Simulation time | 6403813336 ps |
| CPU time | 497.18 seconds |
| Started | Aug 12 07:12:28 PM PDT 24 |
| Finished | Aug 12 07:20:46 PM PDT 24 |
| Peak memory | 611500 kb |
| Host | smart-86a80ca2-ef4e-44cb-a0ad-40c9fd0c9ec2 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +do_random=1 +sw_build_device=sim_dv +sw_images=pwrmgr_sensor_ctrl_deep_sleep_wake_up:1:new_rul es,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t cl +ntb_random_seed=476747321 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_pwrmgr_sensor_ctrl_deep_sl eep_wake_up.476747321 |
| Directory | /workspace/0.chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up/latest |
| Test location | /workspace/coverage/default/1.chip_sw_entropy_src_csrng.1510656853 |
| Short name | T342 |
| Test name | |
| Test status | |
| Simulation time | 6549480792 ps |
| CPU time | 1236.83 seconds |
| Started | Aug 12 07:16:31 PM PDT 24 |
| Finished | Aug 12 07:37:08 PM PDT 24 |
| Peak memory | 610372 kb |
| Host | smart-7684f439-7cde-406a-9b50-369ab0f57856 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=50_000_000 +rng_srate_value_min=15 +rng_srate_value_max=30 +sw_build_device=sim_dv +sw_images=entropy_src_ csrng_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1510656853 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_entropy_src_csrng.1510656853 |
| Directory | /workspace/1.chip_sw_entropy_src_csrng/latest |
| Test location | /workspace/coverage/default/2.chip_sw_gpio.248991510 |
| Short name | T28 |
| Test name | |
| Test status | |
| Simulation time | 4130666880 ps |
| CPU time | 511.44 seconds |
| Started | Aug 12 07:24:15 PM PDT 24 |
| Finished | Aug 12 07:32:47 PM PDT 24 |
| Peak memory | 609716 kb |
| Host | smart-63e2fc9e-c96c-4bc4-a4c0-958e6d10f747 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=gpio_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=248991510 -assert nopostproc +UVM_TESTNAME=chip_base _test +UVM_TEST_SEQ=chip_sw_gpio_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 2.chip_sw_gpio.248991510 |
| Directory | /workspace/2.chip_sw_gpio/latest |
| Test location | /workspace/coverage/default/2.chip_sw_i2c_host_tx_rx_idx1.1379436445 |
| Short name | T222 |
| Test name | |
| Test status | |
| Simulation time | 4848437076 ps |
| CPU time | 684.61 seconds |
| Started | Aug 12 07:24:26 PM PDT 24 |
| Finished | Aug 12 07:35:51 PM PDT 24 |
| Peak memory | 609876 kb |
| Host | smart-d8e2817f-0764-4936-9628-bf0b7351b5a8 |
| User | root |
| Command | /workspace/default/simv +i2c_idx=1 +sw_build_device=sim_dv +sw_images=i2c_host_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1379436445 -assert nopostproc + UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_i2c_host_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de fault.vdb -cm_log /dev/null -cm_name 2.chip_sw_i2c_host_tx_rx_idx1.1379436445 |
| Directory | /workspace/2.chip_sw_i2c_host_tx_rx_idx1/latest |
| Test location | /workspace/coverage/default/69.chip_sw_all_escalation_resets.2082742005 |
| Short name | T264 |
| Test name | |
| Test status | |
| Simulation time | 5226845884 ps |
| CPU time | 563.41 seconds |
| Started | Aug 12 07:39:39 PM PDT 24 |
| Finished | Aug 12 07:49:03 PM PDT 24 |
| Peak memory | 611372 kb |
| Host | smart-7bd371e2-6c65-454e-888f-6b48257184ca |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 2082742005 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 69.chip_sw_all_escalation_resets.2082742005 |
| Directory | /workspace/69.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/0.chip_sw_pwrmgr_full_aon_reset.2241487549 |
| Short name | T98 |
| Test name | |
| Test status | |
| Simulation time | 9167951052 ps |
| CPU time | 536.95 seconds |
| Started | Aug 12 07:07:41 PM PDT 24 |
| Finished | Aug 12 07:16:39 PM PDT 24 |
| Peak memory | 611176 kb |
| Host | smart-de6f3d85-88c3-455f-bc7e-40e64e74c95a |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=rstmgr_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2241487549 -assert nopostproc +UVM_TESTNAME=c hip_base_test +UVM_TEST_SEQ=chip_sw_full_aon_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_ log /dev/null -cm_name 0.chip_sw_pwrmgr_full_aon_reset.2241487549 |
| Directory | /workspace/0.chip_sw_pwrmgr_full_aon_reset/latest |
| Test location | /workspace/coverage/default/1.chip_sw_otp_ctrl_vendor_test_csr_access.1255233022 |
| Short name | T174 |
| Test name | |
| Test status | |
| Simulation time | 1864195243 ps |
| CPU time | 87.12 seconds |
| Started | Aug 12 07:12:22 PM PDT 24 |
| Finished | Aug 12 07:13:49 PM PDT 24 |
| Peak memory | 623252 kb |
| Host | smart-7ac9225b-818a-4d34-affd-aeaaaad59b44 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=otp_ctrl_vendor_test_csr_access_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1255233022 -assert nopost proc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_otp_ctrl_vendor_test_csr_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_otp_ctrl_vendor_test_csr_access.1255233022 |
| Directory | /workspace/1.chip_sw_otp_ctrl_vendor_test_csr_access/latest |
| Test location | /workspace/coverage/default/0.chip_sw_pwrmgr_random_sleep_all_wake_ups.1939954335 |
| Short name | T106 |
| Test name | |
| Test status | |
| Simulation time | 24590211160 ps |
| CPU time | 1508.14 seconds |
| Started | Aug 12 07:12:32 PM PDT 24 |
| Finished | Aug 12 07:37:41 PM PDT 24 |
| Peak memory | 611108 kb |
| Host | smart-7e5c5c7b-dd86-4927-a57a-ea71e9623a66 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +do_random=1 +sw_build_device=sim_dv +sw_images=pwrmgr_random_sleep_all_wake_ups:1:new_rules,te st_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n tb_random_seed=1939954335 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_pwrmgr_deep_sleep_all_wake_ups_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_pwrmgr_random_sleep_all_wake_ups.1939954335 |
| Directory | /workspace/0.chip_sw_pwrmgr_random_sleep_all_wake_ups/latest |
| Test location | /workspace/coverage/default/0.chip_sw_rv_dm_access_after_escalation_reset.2116726828 |
| Short name | T749 |
| Test name | |
| Test status | |
| Simulation time | 5442376998 ps |
| CPU time | 586.47 seconds |
| Started | Aug 12 07:09:59 PM PDT 24 |
| Finished | Aug 12 07:19:46 PM PDT 24 |
| Peak memory | 624948 kb |
| Host | smart-46cc352d-155b-49ce-b78f-97caec8b10f9 |
| User | root |
| Command | /workspace/default/simv +use_jtag_dmi=1 +sw_build_device=sim_dv +sw_images=alert_handler_escalation_test:1:new_rules,test_rom:0 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2116726828 -asse rt nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rv_dm_access_after_escalation_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_rv_dm_access_after_escalation_reset.2116726828 |
| Directory | /workspace/0.chip_sw_rv_dm_access_after_escalation_reset/latest |
| Test location | /workspace/coverage/default/0.chip_tap_straps_dev.3630241644 |
| Short name | T75 |
| Test name | |
| Test status | |
| Simulation time | 9663103826 ps |
| CPU time | 1181.9 seconds |
| Started | Aug 12 07:09:10 PM PDT 24 |
| Finished | Aug 12 07:28:52 PM PDT 24 |
| Peak memory | 621400 kb |
| Host | smart-2c07c8ee-f8c6-420b-8c6c-d7a72a1bb8b0 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStDev +create_jtag_riscv_map=1 +sw_build_device=sim_dv +sw_images=example_test_from_rom:0:test_in_rom: new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=3630241644 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_tap_straps_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_tap_straps_dev.3630241644 |
| Directory | /workspace/0.chip_tap_straps_dev/latest |
| Test location | /workspace/coverage/cover_reg_top/20.chip_tl_errors.2651411594 |
| Short name | T2582 |
| Test name | |
| Test status | |
| Simulation time | 2691825745 ps |
| CPU time | 108.38 seconds |
| Started | Aug 12 06:48:56 PM PDT 24 |
| Finished | Aug 12 06:50:44 PM PDT 24 |
| Peak memory | 598248 kb |
| Host | smart-8e76a254-a1ff-45f0-9331-7a8ea9f705cc |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2651411594 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.chip_tl_errors.2651411594 |
| Directory | /workspace/20.chip_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/31.xbar_stress_all.220061936 |
| Short name | T1818 |
| Test name | |
| Test status | |
| Simulation time | 135726304 ps |
| CPU time | 17.16 seconds |
| Started | Aug 12 06:50:39 PM PDT 24 |
| Finished | Aug 12 06:50:56 PM PDT 24 |
| Peak memory | 575692 kb |
| Host | smart-f3c13e0a-2001-4f6c-a559-e06b1d900c22 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=220061936 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.xbar_stress_all.220061936 |
| Directory | /workspace/31.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/36.xbar_stress_all_with_error.338264386 |
| Short name | T680 |
| Test name | |
| Test status | |
| Simulation time | 25251689905 ps |
| CPU time | 834.9 seconds |
| Started | Aug 12 06:51:38 PM PDT 24 |
| Finished | Aug 12 07:05:33 PM PDT 24 |
| Peak memory | 576604 kb |
| Host | smart-5778db0c-51ab-4cab-a7a8-212f698086c8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=338264386 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.xbar_stress_all_with_error.338264386 |
| Directory | /workspace/36.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/default/0.chip_sw_flash_ctrl_ops_jitter_en_reduced_freq.3502339360 |
| Short name | T375 |
| Test name | |
| Test status | |
| Simulation time | 4696486073 ps |
| CPU time | 658.95 seconds |
| Started | Aug 12 07:10:31 PM PDT 24 |
| Finished | Aug 12 07:21:30 PM PDT 24 |
| Peak memory | 609612 kb |
| Host | smart-8f9d4cba-4d3e-4d8c-91f8-69043c5670b8 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=50_000_000 +en_jitter=1 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=flash_ctrl_ops_test:1:new_ rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si m.tcl +ntb_random_seed=3502339360 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_flash_ctrl_ops_jitter_en_reduced_freq.3502339360 |
| Directory | /workspace/0.chip_sw_flash_ctrl_ops_jitter_en_reduced_freq/latest |
| Test location | /workspace/coverage/default/0.chip_sw_pwrmgr_lowpower_cancel.2675949168 |
| Short name | T352 |
| Test name | |
| Test status | |
| Simulation time | 3496518848 ps |
| CPU time | 401.68 seconds |
| Started | Aug 12 07:08:55 PM PDT 24 |
| Finished | Aug 12 07:15:37 PM PDT 24 |
| Peak memory | 610280 kb |
| Host | smart-14a59c20-737e-446b-81c3-cb684990ca4e |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_lowpower_cancel_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2675949168 -assert nopostproc +UVM _TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm _log /dev/null -cm_name 0.chip_sw_pwrmgr_lowpower_cancel.2675949168 |
| Directory | /workspace/0.chip_sw_pwrmgr_lowpower_cancel/latest |
| Test location | /workspace/coverage/default/0.chip_sw_rstmgr_alert_info.113056957 |
| Short name | T338 |
| Test name | |
| Test status | |
| Simulation time | 12918998358 ps |
| CPU time | 2190.33 seconds |
| Started | Aug 12 07:09:06 PM PDT 24 |
| Finished | Aug 12 07:45:37 PM PDT 24 |
| Peak memory | 611108 kb |
| Host | smart-d6cca0a8-5435-4072-a6ff-70e8646cd265 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=30_000_000 +en_scb_tl_err_chk=0 +sw_build_device=sim_dv +sw_images=rstmgr_alert_info_test:1:new_rules,test _rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb _random_seed=113056957 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_rstmgr_alert_info.113056957 |
| Directory | /workspace/0.chip_sw_rstmgr_alert_info/latest |
| Test location | /workspace/coverage/default/2.chip_plic_all_irqs_10.1800568370 |
| Short name | T169 |
| Test name | |
| Test status | |
| Simulation time | 3708427384 ps |
| CPU time | 547.57 seconds |
| Started | Aug 12 07:32:21 PM PDT 24 |
| Finished | Aug 12 07:41:29 PM PDT 24 |
| Peak memory | 610304 kb |
| Host | smart-983fa3d9-9c46-4c92-931d-0ef852fe9da5 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=plic_all_irqs_test_10:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1800568370 -assert nopostproc +UVM_TESTN AME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log / dev/null -cm_name 2.chip_plic_all_irqs_10.1800568370 |
| Directory | /workspace/2.chip_plic_all_irqs_10/latest |
| Test location | /workspace/coverage/default/4.chip_sw_uart_tx_rx_alt_clk_freq_low_speed.2613839305 |
| Short name | T16 |
| Test name | |
| Test status | |
| Simulation time | 4687862474 ps |
| CPU time | 587 seconds |
| Started | Aug 12 07:31:57 PM PDT 24 |
| Finished | Aug 12 07:41:44 PM PDT 24 |
| Peak memory | 619436 kb |
| Host | smart-e7a19045-ec3f-4ff3-8769-f0c2ec4cff52 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +chip_clock_source=ChipClockSourceExternal48Mhz +sw_build_device=sim_dv +s w_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2613839305 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_b audrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.chip_sw_uart_tx_rx _alt_clk_freq_low_speed.2613839305 |
| Directory | /workspace/4.chip_sw_uart_tx_rx_alt_clk_freq_low_speed/latest |
| Test location | /workspace/coverage/cover_reg_top/0.chip_csr_hw_reset.3987871097 |
| Short name | T151 |
| Test name | |
| Test status | |
| Simulation time | 5839254984 ps |
| CPU time | 317.49 seconds |
| Started | Aug 12 06:47:15 PM PDT 24 |
| Finished | Aug 12 06:52:33 PM PDT 24 |
| Peak memory | 660064 kb |
| Host | smart-b0def379-ead1-4ce0-b687-9d5418358fe8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3987871097 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.chip_csr_hw_r eset.3987871097 |
| Directory | /workspace/0.chip_csr_hw_reset/latest |
| Test location | /workspace/coverage/default/0.chip_sw_ast_clk_rst_inputs.3591641829 |
| Short name | T121 |
| Test name | |
| Test status | |
| Simulation time | 15481718245 ps |
| CPU time | 2226.37 seconds |
| Started | Aug 12 07:10:27 PM PDT 24 |
| Finished | Aug 12 07:47:34 PM PDT 24 |
| Peak memory | 611516 kb |
| Host | smart-09d4219e-f4e5-46a5-a69f-22239d2da8bd |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=200_000_000 +sw_build_device=sim_dv +sw_images=ast_clk_rst_inputs:1:new_rules,test_rom:0 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3591641829 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_ast_clk_rst_inputs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_ast_clk_rst_inputs.3591641829 |
| Directory | /workspace/0.chip_sw_ast_clk_rst_inputs/latest |
| Test location | /workspace/coverage/default/0.chip_sw_lc_ctrl_program_error.2960740308 |
| Short name | T35 |
| Test name | |
| Test status | |
| Simulation time | 5825634264 ps |
| CPU time | 479.41 seconds |
| Started | Aug 12 07:09:15 PM PDT 24 |
| Finished | Aug 12 07:17:15 PM PDT 24 |
| Peak memory | 611460 kb |
| Host | smart-dc993d84-18db-473a-83c9-fd2e28fe67b6 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=lc_ctrl_program_error:1:new_rules,test_rom:0 + cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_ seed=2960740308 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_program_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_lc_ctrl_program_error.2960740308 |
| Directory | /workspace/0.chip_sw_lc_ctrl_program_error/latest |
| Test location | /workspace/coverage/default/0.chip_sw_ast_clk_outputs.1155177692 |
| Short name | T809 |
| Test name | |
| Test status | |
| Simulation time | 7999676956 ps |
| CPU time | 996.12 seconds |
| Started | Aug 12 07:12:07 PM PDT 24 |
| Finished | Aug 12 07:28:43 PM PDT 24 |
| Peak memory | 616784 kb |
| Host | smart-16807151-6cf3-4428-bd32-37c265d0cd9c |
| User | root |
| Command | /workspace/default/simv +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=ast_clk_outs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled= 1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1155177692 -assert nopo stproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_ast_clk_outputs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co verage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_ast_clk_outputs.1155177692 |
| Directory | /workspace/0.chip_sw_ast_clk_outputs/latest |
| Test location | /workspace/coverage/default/0.chip_sw_lc_ctrl_volatile_raw_unlock.3970378740 |
| Short name | T278 |
| Test name | |
| Test status | |
| Simulation time | 2321782403 ps |
| CPU time | 142.66 seconds |
| Started | Aug 12 07:08:44 PM PDT 24 |
| Finished | Aug 12 07:11:07 PM PDT 24 |
| Peak memory | 618212 kb |
| Host | smart-6e4edd0c-7cb3-416f-a9fb-2e6887392db0 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStRaw +exp_volatile_raw_unlock_en=0 +sw_build_device=sim_dv +sw_images=lc_ctrl_volatile_raw_unlock_tes t:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/ tools/sim.tcl +ntb_random_seed=3970378740 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_volatile_raw_unlock_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_lc_ctrl_volatile_raw_unlock.3970378740 |
| Directory | /workspace/0.chip_sw_lc_ctrl_volatile_raw_unlock/latest |
| Test location | /workspace/coverage/default/0.chip_sw_lc_walkthrough_dev.691697036 |
| Short name | T236 |
| Test name | |
| Test status | |
| Simulation time | 47251115000 ps |
| CPU time | 5636.86 seconds |
| Started | Aug 12 07:09:45 PM PDT 24 |
| Finished | Aug 12 08:43:42 PM PDT 24 |
| Peak memory | 621008 kb |
| Host | smart-702b856c-a22c-4fca-91d6-1c3493c97d8d |
| User | root |
| Command | /workspace/default/simv +flash_program_latency=5 +use_otp_image=OtpTypeLcStRaw +dest_dec_state=DecLcStDev +sw_test_timeout_ns=200_000_000 +sw_build_de vice=sim_dv +sw_images=lc_walkthrough_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=691697036 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=ch ip_sw_lc_walkthrough_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_ sw_lc_walkthrough_dev.691697036 |
| Directory | /workspace/0.chip_sw_lc_walkthrough_dev/latest |
| Test location | /workspace/coverage/default/0.chip_sw_pwrmgr_deep_sleep_power_glitch_reset.3624023200 |
| Short name | T1156 |
| Test name | |
| Test status | |
| Simulation time | 6890736250 ps |
| CPU time | 385.62 seconds |
| Started | Aug 12 07:09:43 PM PDT 24 |
| Finished | Aug 12 07:16:08 PM PDT 24 |
| Peak memory | 616800 kb |
| Host | smart-b2e465a8-84b9-4fbf-9739-459b6bc0b339 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=pwrmgr_deep_sleep_power_glitch_test:1:new_rules,test_rom :0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=3624023200 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_deep_power_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_pwrmgr_deep_sleep_power_glitch_reset.3624023200 |
| Directory | /workspace/0.chip_sw_pwrmgr_deep_sleep_power_glitch_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/16.xbar_stress_all_with_error.1889482017 |
| Short name | T678 |
| Test name | |
| Test status | |
| Simulation time | 9647637045 ps |
| CPU time | 332.38 seconds |
| Started | Aug 12 06:48:21 PM PDT 24 |
| Finished | Aug 12 06:53:54 PM PDT 24 |
| Peak memory | 576448 kb |
| Host | smart-8cafac64-ae19-4b84-9b27-dd8b6644a5bf |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1889482017 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.xbar_stress_all_with_error.1889482017 |
| Directory | /workspace/16.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/29.xbar_stress_all_with_error.3213630186 |
| Short name | T691 |
| Test name | |
| Test status | |
| Simulation time | 1304678604 ps |
| CPU time | 92.15 seconds |
| Started | Aug 12 06:50:17 PM PDT 24 |
| Finished | Aug 12 06:51:49 PM PDT 24 |
| Peak memory | 575732 kb |
| Host | smart-3c10592a-300c-42b2-9796-e6c8eeb5c9a0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3213630186 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.xbar_stress_all_with_error.3213630186 |
| Directory | /workspace/29.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/34.xbar_stress_all_with_error.1916886570 |
| Short name | T701 |
| Test name | |
| Test status | |
| Simulation time | 9734966284 ps |
| CPU time | 283.92 seconds |
| Started | Aug 12 06:51:36 PM PDT 24 |
| Finished | Aug 12 06:56:20 PM PDT 24 |
| Peak memory | 575736 kb |
| Host | smart-e447609e-39cc-4e85-be56-75d807b165d1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1916886570 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.xbar_stress_all_with_error.1916886570 |
| Directory | /workspace/34.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/39.xbar_stress_all_with_error.2309857366 |
| Short name | T747 |
| Test name | |
| Test status | |
| Simulation time | 10959607543 ps |
| CPU time | 424.73 seconds |
| Started | Aug 12 06:51:44 PM PDT 24 |
| Finished | Aug 12 06:58:48 PM PDT 24 |
| Peak memory | 576576 kb |
| Host | smart-1a914239-fed9-460c-ba3a-1c69516f036d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2309857366 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.xbar_stress_all_with_error.2309857366 |
| Directory | /workspace/39.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/44.xbar_stress_all_with_error.1645850932 |
| Short name | T765 |
| Test name | |
| Test status | |
| Simulation time | 2981855298 ps |
| CPU time | 247.71 seconds |
| Started | Aug 12 06:52:34 PM PDT 24 |
| Finished | Aug 12 06:56:42 PM PDT 24 |
| Peak memory | 575876 kb |
| Host | smart-37d7fb29-4da8-4cc6-b3cc-db3d2067cff5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1645850932 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.xbar_stress_all_with_error.1645850932 |
| Directory | /workspace/44.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/82.xbar_stress_all_with_error.3774668704 |
| Short name | T700 |
| Test name | |
| Test status | |
| Simulation time | 3078925922 ps |
| CPU time | 118.52 seconds |
| Started | Aug 12 06:57:21 PM PDT 24 |
| Finished | Aug 12 06:59:19 PM PDT 24 |
| Peak memory | 575736 kb |
| Host | smart-a859d1c0-065e-492b-840f-bd7d97d06454 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3774668704 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 82.xbar_stress_all_with_error.3774668704 |
| Directory | /workspace/82.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/default/0.chip_sw_hmac_enc_jitter_en.3975955660 |
| Short name | T378 |
| Test name | |
| Test status | |
| Simulation time | 3194279548 ps |
| CPU time | 258.99 seconds |
| Started | Aug 12 07:08:28 PM PDT 24 |
| Finished | Aug 12 07:12:47 PM PDT 24 |
| Peak memory | 609940 kb |
| Host | smart-cf1b2a4f-bc43-4c1b-8b42-064a2499bf74 |
| User | root |
| Command | /workspace/default/simv +en_jitter=1 +sw_build_device=sim_dv +sw_images=hmac_enc_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3975955660 -assert nopostproc +UVM_ TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_ log /dev/null -cm_name 0.chip_sw_hmac_enc_jitter_en.3975955660 |
| Directory | /workspace/0.chip_sw_hmac_enc_jitter_en/latest |
| Test location | /workspace/coverage/default/0.chip_sw_i2c_host_tx_rx_idx2.9738947 |
| Short name | T347 |
| Test name | |
| Test status | |
| Simulation time | 4565537430 ps |
| CPU time | 818.95 seconds |
| Started | Aug 12 07:08:28 PM PDT 24 |
| Finished | Aug 12 07:22:09 PM PDT 24 |
| Peak memory | 609884 kb |
| Host | smart-e9c5deef-249c-4460-aa14-20d1a60e61ac |
| User | root |
| Command | /workspace/default/simv +i2c_idx=2 +sw_build_device=sim_dv +sw_images=i2c_host_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=9738947 -assert nopostproc +UVM _TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_i2c_host_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau lt.vdb -cm_log /dev/null -cm_name 0.chip_sw_i2c_host_tx_rx_idx2.9738947 |
| Directory | /workspace/0.chip_sw_i2c_host_tx_rx_idx2/latest |
| Test location | /workspace/coverage/default/0.chip_sw_rv_core_ibex_nmi_irq.1403456902 |
| Short name | T547 |
| Test name | |
| Test status | |
| Simulation time | 4384952432 ps |
| CPU time | 767.25 seconds |
| Started | Aug 12 07:09:11 PM PDT 24 |
| Finished | Aug 12 07:21:58 PM PDT 24 |
| Peak memory | 609344 kb |
| Host | smart-1464c2a5-6a17-4924-8b35-82e59b3fa6d5 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=10_000_000 +sw_build_device=sim_dv +sw_images=rv_core_ibex_nmi_irq_test:1:new_rules,test_rom:0 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14034 56902 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_rv_core_ibex_nmi_irq.1403456902 |
| Directory | /workspace/0.chip_sw_rv_core_ibex_nmi_irq/latest |
| Test location | /workspace/coverage/default/1.chip_jtag_csr_rw.2410091547 |
| Short name | T56 |
| Test name | |
| Test status | |
| Simulation time | 9283595196 ps |
| CPU time | 971.58 seconds |
| Started | Aug 12 07:11:39 PM PDT 24 |
| Finished | Aug 12 07:27:50 PM PDT 24 |
| Peak memory | 604212 kb |
| Host | smart-da0eda2e-43bd-434f-bf6d-09921d3a8a38 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +csr_rw +create_jtag_riscv_map=1 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2410091547 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_T EST_SEQ=chip_jtag_csr_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.c hip_jtag_csr_rw.2410091547 |
| Directory | /workspace/1.chip_jtag_csr_rw/latest |
| Test location | /workspace/coverage/default/0.chip_sw_aes_enc.2871129485 |
| Short name | T1063 |
| Test name | |
| Test status | |
| Simulation time | 2623835532 ps |
| CPU time | 243.52 seconds |
| Started | Aug 12 07:08:33 PM PDT 24 |
| Finished | Aug 12 07:12:36 PM PDT 24 |
| Peak memory | 609692 kb |
| Host | smart-d6f7fc9a-26d0-44cd-8770-01d82d47fe28 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=22_000_000 +sw_build_device=sim_dv +sw_images=aes_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2871129485 -asser t nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag e/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_aes_enc.2871129485 |
| Directory | /workspace/0.chip_sw_aes_enc/latest |
| Test location | /workspace/coverage/default/0.chip_sw_edn_boot_mode.2540244259 |
| Short name | T744 |
| Test name | |
| Test status | |
| Simulation time | 2833339138 ps |
| CPU time | 651.78 seconds |
| Started | Aug 12 07:09:07 PM PDT 24 |
| Finished | Aug 12 07:20:00 PM PDT 24 |
| Peak memory | 610436 kb |
| Host | smart-65498c89-a7e4-42c5-9aff-914cbdcc0a52 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +rng_srate_value=5 +sw_build_device=sim_dv +sw_images=edn_boot_mode:1:new_rules,test_rom:0 +acc elerate_cold_power_up_time=3 +accelerate_regulators_power_up_time=2 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2540244259 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ =chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_edn_ boot_mode.2540244259 |
| Directory | /workspace/0.chip_sw_edn_boot_mode/latest |
| Test location | /workspace/coverage/default/0.chip_sw_keymgr_sideload_aes.3086000044 |
| Short name | T230 |
| Test name | |
| Test status | |
| Simulation time | 11393019634 ps |
| CPU time | 2525.02 seconds |
| Started | Aug 12 07:09:07 PM PDT 24 |
| Finished | Aug 12 07:51:13 PM PDT 24 |
| Peak memory | 611624 kb |
| Host | smart-83911073-fe88-4aad-aa77-b68ddda5629f |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=20_000_000 +sw_build_device=sim_dv +sw_images=keymgr_sideload_aes_test:1:new_rules,test_rom:0 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=308600 0044 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_keymgr_sideload_aes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_keymgr_sideload_aes.3086000044 |
| Directory | /workspace/0.chip_sw_keymgr_sideload_aes/latest |
| Test location | /workspace/coverage/default/0.chip_sw_otbn_ecdsa_op_irq.1336616618 |
| Short name | T164 |
| Test name | |
| Test status | |
| Simulation time | 16881504228 ps |
| CPU time | 3309.05 seconds |
| Started | Aug 12 07:12:46 PM PDT 24 |
| Finished | Aug 12 08:07:56 PM PDT 24 |
| Peak memory | 610660 kb |
| Host | smart-673526d9-cf40-4a8b-9602-9432a22a5e0e |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=28_000_000 +rng_srate_value=30 +sw_build_device=sim_dv +sw_images=otbn_ecdsa_op_irq_test:1:new_rules,test_ rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ random_seed=1336616618 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_otbn_ecdsa_op_irq.1336616618 |
| Directory | /workspace/0.chip_sw_otbn_ecdsa_op_irq/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_bad_b_good_dev.4148341712 |
| Short name | T1173 |
| Test name | |
| Test status | |
| Simulation time | 24581666590 ps |
| CPU time | 5540.97 seconds |
| Started | Aug 12 07:18:14 PM PDT 24 |
| Finished | Aug 12 08:50:36 PM PDT 24 |
| Peak memory | 610456 kb |
| Host | smart-27925553-64f3-41df-b7db-50e07c8e5b92 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=100_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_corrupted:1: ot_flash_binary:signed:fake_ecdsa_prod_key_0,empty_test_slot_b_fake_ecdsa_prod_key_0:2:ot_flash_binary,otp_img_boot_policy_valid_dev:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random _seed=4148341712 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_boot_policy_valid_a_bad_b_good_dev.4148341712 |
| Directory | /workspace/0.rom_e2e_boot_policy_valid_a_bad_b_good_dev/latest |
| Test location | /workspace/coverage/cover_reg_top/0.chip_csr_bit_bash.1097396250 |
| Short name | T746 |
| Test name | |
| Test status | |
| Simulation time | 7452056864 ps |
| CPU time | 557.88 seconds |
| Started | Aug 12 06:47:07 PM PDT 24 |
| Finished | Aug 12 06:56:25 PM PDT 24 |
| Peak memory | 592612 kb |
| Host | smart-6eefe4a8-f3df-4fa3-815d-7ccbb7eeccf5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +num_test_csrs=200 +csr_bit_bash +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1097396250 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to p.vdb -cm_log /dev/null -cm_name 0.chip_csr_bit_bash.1097396250 |
| Directory | /workspace/0.chip_csr_bit_bash/latest |
| Test location | /workspace/coverage/cover_reg_top/0.chip_csr_mem_rw_with_rand_reset.1833842151 |
| Short name | T2541 |
| Test name | |
| Test status | |
| Simulation time | 6317593225 ps |
| CPU time | 361.15 seconds |
| Started | Aug 12 06:47:07 PM PDT 24 |
| Finished | Aug 12 06:53:08 PM PDT 24 |
| Peak memory | 644636 kb |
| Host | smart-1d045ff0-6b73-4dfc-92ab-dcb1ccf8a776 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1833842151 -assert nopostproc + UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top .vdb -cm_log /dev/null -cm_name 0.chip_csr_mem_rw_with_rand_reset.1833842151 |
| Directory | /workspace/0.chip_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/0.chip_csr_rw.368902999 |
| Short name | T420 |
| Test name | |
| Test status | |
| Simulation time | 5903625601 ps |
| CPU time | 558.11 seconds |
| Started | Aug 12 06:47:07 PM PDT 24 |
| Finished | Aug 12 06:56:25 PM PDT 24 |
| Peak memory | 598480 kb |
| Host | smart-d7d4a7df-72d2-4bfc-b118-4367b6bc1a66 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=368902999 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.chip_csr_rw.368902999 |
| Directory | /workspace/0.chip_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/0.chip_prim_tl_access.4259977524 |
| Short name | T2889 |
| Test name | |
| Test status | |
| Simulation time | 6672800904 ps |
| CPU time | 200.1 seconds |
| Started | Aug 12 06:47:09 PM PDT 24 |
| Finished | Aug 12 06:50:29 PM PDT 24 |
| Peak memory | 590160 kb |
| Host | smart-c6ac4180-54b2-48ae-affa-620214b29ac5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +en_scb=0 +en_scb_tl_err_chk=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4259977524 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SE Q=chip_prim_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.chip_prim_tl_access.4259977524 |
| Directory | /workspace/0.chip_prim_tl_access/latest |
| Test location | /workspace/coverage/cover_reg_top/0.chip_rv_dm_lc_disabled.714873135 |
| Short name | T2158 |
| Test name | |
| Test status | |
| Simulation time | 17705374104 ps |
| CPU time | 805.13 seconds |
| Started | Aug 12 06:47:05 PM PDT 24 |
| Finished | Aug 12 07:00:30 PM PDT 24 |
| Peak memory | 590948 kb |
| Host | smart-5c34b956-f653-4637-ba55-8e900c9ab206 |
| User | root |
| Command | /workspace/cover_reg_top/simv +en_scb=0 +en_scb_tl_err_chk=0 +use_jtag_dmi=1 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=714873135 -assert nopostproc +UVM_TESTNAME=chip_base_te st +UVM_TEST_SEQ=chip_rv_dm_lc_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log / dev/null -cm_name 0.chip_rv_dm_lc_disabled.714873135 |
| Directory | /workspace/0.chip_rv_dm_lc_disabled/latest |
| Test location | /workspace/coverage/cover_reg_top/0.chip_same_csr_outstanding.1525479194 |
| Short name | T2390 |
| Test name | |
| Test status | |
| Simulation time | 26993372560 ps |
| CPU time | 4175.57 seconds |
| Started | Aug 12 06:47:09 PM PDT 24 |
| Finished | Aug 12 07:56:45 PM PDT 24 |
| Peak memory | 592968 kb |
| Host | smart-dd329014-6b30-4509-997b-775cb4034ced |
| User | root |
| Command | /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +run_same_csr_outstanding +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1525479194 -assert nopostproc +UVM_TE STNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb - cm_log /dev/null -cm_name 0.chip_same_csr_outstanding.1525479194 |
| Directory | /workspace/0.chip_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/0.xbar_access_same_device.3012920891 |
| Short name | T1964 |
| Test name | |
| Test status | |
| Simulation time | 693278763 ps |
| CPU time | 28.52 seconds |
| Started | Aug 12 06:47:06 PM PDT 24 |
| Finished | Aug 12 06:47:34 PM PDT 24 |
| Peak memory | 575608 kb |
| Host | smart-65c1e5da-b313-4af6-b278-9ab53c81011c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3012920891 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.xbar_access_same_device. 3012920891 |
| Directory | /workspace/0.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/0.xbar_access_same_device_slow_rsp.4244034559 |
| Short name | T1746 |
| Test name | |
| Test status | |
| Simulation time | 120605453395 ps |
| CPU time | 2196.68 seconds |
| Started | Aug 12 06:47:07 PM PDT 24 |
| Finished | Aug 12 07:23:44 PM PDT 24 |
| Peak memory | 575768 kb |
| Host | smart-dda7da34-c1f2-4ac6-baea-a47823346db8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4244034559 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.xbar_access_same_d evice_slow_rsp.4244034559 |
| Directory | /workspace/0.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/0.xbar_error_and_unmapped_addr.3103967342 |
| Short name | T2243 |
| Test name | |
| Test status | |
| Simulation time | 289998128 ps |
| CPU time | 29.01 seconds |
| Started | Aug 12 06:47:15 PM PDT 24 |
| Finished | Aug 12 06:47:44 PM PDT 24 |
| Peak memory | 575496 kb |
| Host | smart-1c2af0f8-eb48-4f38-a930-8f40986298f2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3103967342 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.xbar_error_and_unmapped_addr .3103967342 |
| Directory | /workspace/0.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/0.xbar_error_random.3218386126 |
| Short name | T1695 |
| Test name | |
| Test status | |
| Simulation time | 1068913565 ps |
| CPU time | 37 seconds |
| Started | Aug 12 06:47:08 PM PDT 24 |
| Finished | Aug 12 06:47:45 PM PDT 24 |
| Peak memory | 575680 kb |
| Host | smart-2bac8f08-e494-4aee-b33f-0cbd54c17ba2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3218386126 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.xbar_error_random.3218386126 |
| Directory | /workspace/0.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/0.xbar_random.3400508601 |
| Short name | T2151 |
| Test name | |
| Test status | |
| Simulation time | 252276651 ps |
| CPU time | 21.74 seconds |
| Started | Aug 12 06:47:10 PM PDT 24 |
| Finished | Aug 12 06:47:31 PM PDT 24 |
| Peak memory | 575656 kb |
| Host | smart-2a8a61a3-6918-4400-9845-d99455aa8d89 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3400508601 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.xbar_random.3400508601 |
| Directory | /workspace/0.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/0.xbar_random_slow_rsp.3392241573 |
| Short name | T500 |
| Test name | |
| Test status | |
| Simulation time | 10932287317 ps |
| CPU time | 189.84 seconds |
| Started | Aug 12 06:47:13 PM PDT 24 |
| Finished | Aug 12 06:50:23 PM PDT 24 |
| Peak memory | 575776 kb |
| Host | smart-faa69df2-b65f-44ab-8e20-cb86e3bea33b |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3392241573 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.xbar_random_slow_rsp.3392241573 |
| Directory | /workspace/0.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/0.xbar_random_zero_delays.2089204670 |
| Short name | T2672 |
| Test name | |
| Test status | |
| Simulation time | 266745379 ps |
| CPU time | 24.14 seconds |
| Started | Aug 12 06:47:09 PM PDT 24 |
| Finished | Aug 12 06:47:33 PM PDT 24 |
| Peak memory | 575604 kb |
| Host | smart-d60df040-e1bc-4231-8ca6-65f77aa2e6ee |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2089204670 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.xbar_random_zero_dela ys.2089204670 |
| Directory | /workspace/0.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/0.xbar_same_source.673341883 |
| Short name | T612 |
| Test name | |
| Test status | |
| Simulation time | 700932333 ps |
| CPU time | 20.58 seconds |
| Started | Aug 12 06:47:05 PM PDT 24 |
| Finished | Aug 12 06:47:25 PM PDT 24 |
| Peak memory | 575612 kb |
| Host | smart-812ecfd1-f45b-44a5-88cf-68ff14622d09 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=673341883 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.xbar_same_source.673341883 |
| Directory | /workspace/0.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/0.xbar_smoke.2128166061 |
| Short name | T1657 |
| Test name | |
| Test status | |
| Simulation time | 179167355 ps |
| CPU time | 7.68 seconds |
| Started | Aug 12 06:47:15 PM PDT 24 |
| Finished | Aug 12 06:47:23 PM PDT 24 |
| Peak memory | 573572 kb |
| Host | smart-ed21ec79-cd18-4b80-a5b4-326545b67b4b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2128166061 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.xbar_smoke.2128166061 |
| Directory | /workspace/0.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/0.xbar_smoke_large_delays.2743698319 |
| Short name | T2256 |
| Test name | |
| Test status | |
| Simulation time | 8106852297 ps |
| CPU time | 81.51 seconds |
| Started | Aug 12 06:47:10 PM PDT 24 |
| Finished | Aug 12 06:48:31 PM PDT 24 |
| Peak memory | 573600 kb |
| Host | smart-f33d85a9-2268-4d9c-94ea-08127c756952 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2743698319 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.xbar_smoke_large_delays.2743698319 |
| Directory | /workspace/0.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/0.xbar_smoke_slow_rsp.3869880112 |
| Short name | T2607 |
| Test name | |
| Test status | |
| Simulation time | 4380790856 ps |
| CPU time | 71.49 seconds |
| Started | Aug 12 06:47:15 PM PDT 24 |
| Finished | Aug 12 06:48:26 PM PDT 24 |
| Peak memory | 573668 kb |
| Host | smart-6ed2a774-557f-43cb-9d70-75a8576a2498 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3869880112 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.xbar_smoke_slow_rsp.3869880112 |
| Directory | /workspace/0.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/0.xbar_smoke_zero_delays.1095699956 |
| Short name | T2536 |
| Test name | |
| Test status | |
| Simulation time | 44124480 ps |
| CPU time | 6.33 seconds |
| Started | Aug 12 06:47:10 PM PDT 24 |
| Finished | Aug 12 06:47:16 PM PDT 24 |
| Peak memory | 574316 kb |
| Host | smart-2283b5bb-33fd-4073-a446-288ae349ec9f |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1095699956 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.xbar_smoke_zero_delays .1095699956 |
| Directory | /workspace/0.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/0.xbar_stress_all.2934031870 |
| Short name | T1800 |
| Test name | |
| Test status | |
| Simulation time | 4304929383 ps |
| CPU time | 158.29 seconds |
| Started | Aug 12 06:47:11 PM PDT 24 |
| Finished | Aug 12 06:49:50 PM PDT 24 |
| Peak memory | 575756 kb |
| Host | smart-9f8619e2-eebe-471d-8096-336b0a6569ce |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2934031870 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.xbar_stress_all.2934031870 |
| Directory | /workspace/0.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/0.xbar_stress_all_with_error.2597837580 |
| Short name | T2830 |
| Test name | |
| Test status | |
| Simulation time | 11198565015 ps |
| CPU time | 371.47 seconds |
| Started | Aug 12 06:47:07 PM PDT 24 |
| Finished | Aug 12 06:53:18 PM PDT 24 |
| Peak memory | 575792 kb |
| Host | smart-73ae43f3-0fc4-40d4-9f74-87793eec3183 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2597837580 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.xbar_stress_all_with_error.2597837580 |
| Directory | /workspace/0.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/0.xbar_stress_all_with_reset_error.3217459473 |
| Short name | T948 |
| Test name | |
| Test status | |
| Simulation time | 264851374 ps |
| CPU time | 129.42 seconds |
| Started | Aug 12 06:47:16 PM PDT 24 |
| Finished | Aug 12 06:49:25 PM PDT 24 |
| Peak memory | 576524 kb |
| Host | smart-e376c1d8-e806-46d8-ab8f-073c20ab7726 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3217459473 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.xbar_stress_all _with_reset_error.3217459473 |
| Directory | /workspace/0.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/0.xbar_unmapped_addr.2675971258 |
| Short name | T739 |
| Test name | |
| Test status | |
| Simulation time | 112426725 ps |
| CPU time | 7.7 seconds |
| Started | Aug 12 06:47:09 PM PDT 24 |
| Finished | Aug 12 06:47:17 PM PDT 24 |
| Peak memory | 573604 kb |
| Host | smart-e0228551-a6a6-40ca-9a1d-6db03a01ac0e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2675971258 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.xbar_unmapped_addr.2675971258 |
| Directory | /workspace/0.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/1.chip_csr_aliasing.2472027517 |
| Short name | T2334 |
| Test name | |
| Test status | |
| Simulation time | 28843332440 ps |
| CPU time | 5099.44 seconds |
| Started | Aug 12 06:47:07 PM PDT 24 |
| Finished | Aug 12 08:12:07 PM PDT 24 |
| Peak memory | 593972 kb |
| Host | smart-90377730-f33f-43d4-aaa8-d5223bfdf39f |
| User | root |
| Command | /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +csr_aliasing +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2472027517 -assert nopostproc +UVM_TESTNAME=chip_ base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/ null -cm_name 1.chip_csr_aliasing.2472027517 |
| Directory | /workspace/1.chip_csr_aliasing/latest |
| Test location | /workspace/coverage/cover_reg_top/1.chip_csr_bit_bash.1371946297 |
| Short name | T1588 |
| Test name | |
| Test status | |
| Simulation time | 5453119528 ps |
| CPU time | 521.16 seconds |
| Started | Aug 12 06:47:14 PM PDT 24 |
| Finished | Aug 12 06:55:55 PM PDT 24 |
| Peak memory | 592492 kb |
| Host | smart-8df8a478-b3c8-4931-b9d5-a220d14b58d2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +num_test_csrs=200 +csr_bit_bash +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1371946297 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to p.vdb -cm_log /dev/null -cm_name 1.chip_csr_bit_bash.1371946297 |
| Directory | /workspace/1.chip_csr_bit_bash/latest |
| Test location | /workspace/coverage/cover_reg_top/1.chip_csr_hw_reset.730960496 |
| Short name | T149 |
| Test name | |
| Test status | |
| Simulation time | 6029481166 ps |
| CPU time | 350.42 seconds |
| Started | Aug 12 06:47:12 PM PDT 24 |
| Finished | Aug 12 06:53:02 PM PDT 24 |
| Peak memory | 663480 kb |
| Host | smart-9bee7313-3c59-4477-9374-d1d1f2a34c05 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=730960496 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_c ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.chip_csr_hw_re set.730960496 |
| Directory | /workspace/1.chip_csr_hw_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/1.chip_csr_mem_rw_with_rand_reset.3003544370 |
| Short name | T543 |
| Test name | |
| Test status | |
| Simulation time | 7497186639 ps |
| CPU time | 523.77 seconds |
| Started | Aug 12 06:47:10 PM PDT 24 |
| Finished | Aug 12 06:55:54 PM PDT 24 |
| Peak memory | 636728 kb |
| Host | smart-640f5aab-e591-49e7-b8cf-b37379196be5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3003544370 -assert nopostproc + UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top .vdb -cm_log /dev/null -cm_name 1.chip_csr_mem_rw_with_rand_reset.3003544370 |
| Directory | /workspace/1.chip_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/1.chip_csr_rw.2502851806 |
| Short name | T2767 |
| Test name | |
| Test status | |
| Simulation time | 4122555470 ps |
| CPU time | 323.25 seconds |
| Started | Aug 12 06:47:06 PM PDT 24 |
| Finished | Aug 12 06:52:29 PM PDT 24 |
| Peak memory | 596848 kb |
| Host | smart-bc747638-8da9-4347-bacb-19fa3c146108 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2502851806 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.chip_csr_rw.2502851806 |
| Directory | /workspace/1.chip_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/1.chip_prim_tl_access.339868495 |
| Short name | T1718 |
| Test name | |
| Test status | |
| Simulation time | 10335827224 ps |
| CPU time | 392.26 seconds |
| Started | Aug 12 06:47:08 PM PDT 24 |
| Finished | Aug 12 06:53:40 PM PDT 24 |
| Peak memory | 591080 kb |
| Host | smart-251d04b7-09f9-4a46-9855-44b04d5c75b1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +en_scb=0 +en_scb_tl_err_chk=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=339868495 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ =chip_prim_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1 .chip_prim_tl_access.339868495 |
| Directory | /workspace/1.chip_prim_tl_access/latest |
| Test location | /workspace/coverage/cover_reg_top/1.chip_rv_dm_lc_disabled.195489942 |
| Short name | T1608 |
| Test name | |
| Test status | |
| Simulation time | 6910748692 ps |
| CPU time | 358.22 seconds |
| Started | Aug 12 06:47:10 PM PDT 24 |
| Finished | Aug 12 06:53:09 PM PDT 24 |
| Peak memory | 591896 kb |
| Host | smart-f26ec954-f756-4ad7-8620-8c53eb0d043e |
| User | root |
| Command | /workspace/cover_reg_top/simv +en_scb=0 +en_scb_tl_err_chk=0 +use_jtag_dmi=1 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=195489942 -assert nopostproc +UVM_TESTNAME=chip_base_te st +UVM_TEST_SEQ=chip_rv_dm_lc_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log / dev/null -cm_name 1.chip_rv_dm_lc_disabled.195489942 |
| Directory | /workspace/1.chip_rv_dm_lc_disabled/latest |
| Test location | /workspace/coverage/cover_reg_top/1.chip_same_csr_outstanding.1625910311 |
| Short name | T395 |
| Test name | |
| Test status | |
| Simulation time | 17368101206 ps |
| CPU time | 1778.14 seconds |
| Started | Aug 12 06:47:07 PM PDT 24 |
| Finished | Aug 12 07:16:46 PM PDT 24 |
| Peak memory | 592944 kb |
| Host | smart-3b55d1e2-62e7-451a-84cb-d6d1fc2d5944 |
| User | root |
| Command | /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +run_same_csr_outstanding +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1625910311 -assert nopostproc +UVM_TE STNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb - cm_log /dev/null -cm_name 1.chip_same_csr_outstanding.1625910311 |
| Directory | /workspace/1.chip_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/1.chip_tl_errors.943516352 |
| Short name | T775 |
| Test name | |
| Test status | |
| Simulation time | 3849247396 ps |
| CPU time | 206.39 seconds |
| Started | Aug 12 06:47:15 PM PDT 24 |
| Finished | Aug 12 06:50:42 PM PDT 24 |
| Peak memory | 598184 kb |
| Host | smart-d04d5e71-5ae1-413a-a8e8-b23f39f56732 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=943516352 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.chip_tl_errors.943516352 |
| Directory | /workspace/1.chip_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/1.xbar_access_same_device.4147300742 |
| Short name | T899 |
| Test name | |
| Test status | |
| Simulation time | 1715419004 ps |
| CPU time | 68.93 seconds |
| Started | Aug 12 06:47:12 PM PDT 24 |
| Finished | Aug 12 06:48:21 PM PDT 24 |
| Peak memory | 575696 kb |
| Host | smart-4256bc53-95b9-4a90-a718-81a39f61fd21 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4147300742 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.xbar_access_same_device. 4147300742 |
| Directory | /workspace/1.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/1.xbar_access_same_device_slow_rsp.2757760918 |
| Short name | T1792 |
| Test name | |
| Test status | |
| Simulation time | 74668085348 ps |
| CPU time | 1198.58 seconds |
| Started | Aug 12 06:47:15 PM PDT 24 |
| Finished | Aug 12 07:07:14 PM PDT 24 |
| Peak memory | 575956 kb |
| Host | smart-a1f60a54-e017-4b63-ac32-1a73a10bd20e |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2757760918 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.xbar_access_same_d evice_slow_rsp.2757760918 |
| Directory | /workspace/1.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/1.xbar_error_and_unmapped_addr.4199260794 |
| Short name | T2773 |
| Test name | |
| Test status | |
| Simulation time | 972617059 ps |
| CPU time | 36.65 seconds |
| Started | Aug 12 06:47:13 PM PDT 24 |
| Finished | Aug 12 06:47:50 PM PDT 24 |
| Peak memory | 575628 kb |
| Host | smart-196ca63f-2315-48f9-955d-953ebba320fd |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4199260794 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.xbar_error_and_unmapped_addr .4199260794 |
| Directory | /workspace/1.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/1.xbar_error_random.149510998 |
| Short name | T463 |
| Test name | |
| Test status | |
| Simulation time | 322360885 ps |
| CPU time | 24.21 seconds |
| Started | Aug 12 06:47:09 PM PDT 24 |
| Finished | Aug 12 06:47:33 PM PDT 24 |
| Peak memory | 575724 kb |
| Host | smart-505f224a-6b71-4f9b-a432-17473fb98a27 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=149510998 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.xbar_error_random.149510998 |
| Directory | /workspace/1.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/1.xbar_random.1653964415 |
| Short name | T2000 |
| Test name | |
| Test status | |
| Simulation time | 2146835164 ps |
| CPU time | 72.94 seconds |
| Started | Aug 12 06:47:14 PM PDT 24 |
| Finished | Aug 12 06:48:27 PM PDT 24 |
| Peak memory | 575624 kb |
| Host | smart-773e4f75-c654-447b-aaf0-3249eacb1722 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1653964415 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.xbar_random.1653964415 |
| Directory | /workspace/1.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/1.xbar_random_large_delays.2024006898 |
| Short name | T2601 |
| Test name | |
| Test status | |
| Simulation time | 25676302240 ps |
| CPU time | 247.52 seconds |
| Started | Aug 12 06:47:06 PM PDT 24 |
| Finished | Aug 12 06:51:14 PM PDT 24 |
| Peak memory | 575620 kb |
| Host | smart-3c8905b5-47ba-48a5-b0a6-e93ee0187306 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2024006898 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.xbar_random_large_delays.2024006898 |
| Directory | /workspace/1.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/1.xbar_random_slow_rsp.98629034 |
| Short name | T2827 |
| Test name | |
| Test status | |
| Simulation time | 31319670745 ps |
| CPU time | 503.46 seconds |
| Started | Aug 12 06:47:16 PM PDT 24 |
| Finished | Aug 12 06:55:39 PM PDT 24 |
| Peak memory | 575672 kb |
| Host | smart-cc0d5bb5-c53a-41bb-87c1-a412821e2a61 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=98629034 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.xbar_random_slow_rsp.98629034 |
| Directory | /workspace/1.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/1.xbar_random_zero_delays.2170888912 |
| Short name | T501 |
| Test name | |
| Test status | |
| Simulation time | 392708267 ps |
| CPU time | 34.07 seconds |
| Started | Aug 12 06:47:10 PM PDT 24 |
| Finished | Aug 12 06:47:44 PM PDT 24 |
| Peak memory | 575576 kb |
| Host | smart-e268cd20-0b8e-4215-88f0-fe640b6c246c |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2170888912 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.xbar_random_zero_dela ys.2170888912 |
| Directory | /workspace/1.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/1.xbar_same_source.762672361 |
| Short name | T2134 |
| Test name | |
| Test status | |
| Simulation time | 2723576092 ps |
| CPU time | 81.17 seconds |
| Started | Aug 12 06:47:08 PM PDT 24 |
| Finished | Aug 12 06:48:30 PM PDT 24 |
| Peak memory | 575692 kb |
| Host | smart-df4c9c41-00d4-4ff9-95b9-5f565b124b71 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=762672361 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.xbar_same_source.762672361 |
| Directory | /workspace/1.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/1.xbar_smoke.1901009952 |
| Short name | T2197 |
| Test name | |
| Test status | |
| Simulation time | 242709912 ps |
| CPU time | 8.96 seconds |
| Started | Aug 12 06:47:12 PM PDT 24 |
| Finished | Aug 12 06:47:21 PM PDT 24 |
| Peak memory | 574260 kb |
| Host | smart-db75e2a9-b7a0-4258-bfb6-f30a49bb5d82 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1901009952 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.xbar_smoke.1901009952 |
| Directory | /workspace/1.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/1.xbar_smoke_large_delays.3493551946 |
| Short name | T1477 |
| Test name | |
| Test status | |
| Simulation time | 8786183365 ps |
| CPU time | 84.31 seconds |
| Started | Aug 12 06:47:14 PM PDT 24 |
| Finished | Aug 12 06:48:39 PM PDT 24 |
| Peak memory | 573764 kb |
| Host | smart-4cb68f36-4d50-4e4c-bb4d-d7bbf53de6cc |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3493551946 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.xbar_smoke_large_delays.3493551946 |
| Directory | /workspace/1.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/1.xbar_smoke_slow_rsp.112619770 |
| Short name | T2091 |
| Test name | |
| Test status | |
| Simulation time | 6494491994 ps |
| CPU time | 110.05 seconds |
| Started | Aug 12 06:47:11 PM PDT 24 |
| Finished | Aug 12 06:49:01 PM PDT 24 |
| Peak memory | 574384 kb |
| Host | smart-d286a742-cbab-4bbf-88f9-d5d04649de11 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=112619770 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.xbar_smoke_slow_rsp.112619770 |
| Directory | /workspace/1.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/1.xbar_smoke_zero_delays.403751168 |
| Short name | T2434 |
| Test name | |
| Test status | |
| Simulation time | 52657171 ps |
| CPU time | 6.38 seconds |
| Started | Aug 12 06:47:05 PM PDT 24 |
| Finished | Aug 12 06:47:11 PM PDT 24 |
| Peak memory | 573004 kb |
| Host | smart-454ab8e1-e83c-4d94-941e-d12794e48907 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=403751168 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.xbar_smoke_zero_delays. 403751168 |
| Directory | /workspace/1.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/1.xbar_stress_all.4038669837 |
| Short name | T712 |
| Test name | |
| Test status | |
| Simulation time | 4986332928 ps |
| CPU time | 186.58 seconds |
| Started | Aug 12 06:47:05 PM PDT 24 |
| Finished | Aug 12 06:50:12 PM PDT 24 |
| Peak memory | 575760 kb |
| Host | smart-e791ec3d-9ad7-4eea-a3e5-1ab7b3325666 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4038669837 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.xbar_stress_all.4038669837 |
| Directory | /workspace/1.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/1.xbar_stress_all_with_error.1614373751 |
| Short name | T1500 |
| Test name | |
| Test status | |
| Simulation time | 14616246754 ps |
| CPU time | 551.74 seconds |
| Started | Aug 12 06:47:08 PM PDT 24 |
| Finished | Aug 12 06:56:20 PM PDT 24 |
| Peak memory | 576604 kb |
| Host | smart-20823cae-b757-4d6c-98b5-6eb0a287532c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1614373751 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.xbar_stress_all_with_error.1614373751 |
| Directory | /workspace/1.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/1.xbar_stress_all_with_rand_reset.3181767116 |
| Short name | T2025 |
| Test name | |
| Test status | |
| Simulation time | 4121153227 ps |
| CPU time | 469.57 seconds |
| Started | Aug 12 06:47:09 PM PDT 24 |
| Finished | Aug 12 06:54:58 PM PDT 24 |
| Peak memory | 576572 kb |
| Host | smart-d4d2eba6-62e8-4278-9d85-aed671a3655e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3181767116 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.xbar_stress_all_ with_rand_reset.3181767116 |
| Directory | /workspace/1.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/1.xbar_stress_all_with_reset_error.2866393430 |
| Short name | T956 |
| Test name | |
| Test status | |
| Simulation time | 5450209612 ps |
| CPU time | 345.22 seconds |
| Started | Aug 12 06:47:14 PM PDT 24 |
| Finished | Aug 12 06:52:59 PM PDT 24 |
| Peak memory | 575716 kb |
| Host | smart-673aab74-2c4f-44e2-a985-a6071c8ef2ad |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2866393430 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.xbar_stress_all _with_reset_error.2866393430 |
| Directory | /workspace/1.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/1.xbar_unmapped_addr.289850954 |
| Short name | T1705 |
| Test name | |
| Test status | |
| Simulation time | 197341598 ps |
| CPU time | 11.19 seconds |
| Started | Aug 12 06:47:13 PM PDT 24 |
| Finished | Aug 12 06:47:25 PM PDT 24 |
| Peak memory | 575568 kb |
| Host | smart-f71d32c4-1ff9-4161-b881-7484b7076f6e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=289850954 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.xbar_unmapped_addr.289850954 |
| Directory | /workspace/1.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/10.chip_csr_mem_rw_with_rand_reset.3816824592 |
| Short name | T1838 |
| Test name | |
| Test status | |
| Simulation time | 12928734650 ps |
| CPU time | 905.5 seconds |
| Started | Aug 12 06:47:55 PM PDT 24 |
| Finished | Aug 12 07:03:01 PM PDT 24 |
| Peak memory | 652560 kb |
| Host | smart-fdb33ced-c454-4498-ae31-1c1a5e236f7d |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3816824592 -assert nopostproc + UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top .vdb -cm_log /dev/null -cm_name 10.chip_csr_mem_rw_with_rand_reset.3816824592 |
| Directory | /workspace/10.chip_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/10.chip_csr_rw.3889975188 |
| Short name | T396 |
| Test name | |
| Test status | |
| Simulation time | 4452282185 ps |
| CPU time | 319.81 seconds |
| Started | Aug 12 06:47:40 PM PDT 24 |
| Finished | Aug 12 06:53:00 PM PDT 24 |
| Peak memory | 597344 kb |
| Host | smart-a8223460-2d69-40d0-ab00-4f95c039d78e |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3889975188 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.chip_csr_rw.3889975188 |
| Directory | /workspace/10.chip_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/10.chip_same_csr_outstanding.1379903023 |
| Short name | T2016 |
| Test name | |
| Test status | |
| Simulation time | 30374807190 ps |
| CPU time | 3845.51 seconds |
| Started | Aug 12 06:47:41 PM PDT 24 |
| Finished | Aug 12 07:51:46 PM PDT 24 |
| Peak memory | 593308 kb |
| Host | smart-08dc1caf-d7f7-44fa-a448-9d611df0a4f0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +run_same_csr_outstanding +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1379903023 -assert nopostproc +UVM_TE STNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb - cm_log /dev/null -cm_name 10.chip_same_csr_outstanding.1379903023 |
| Directory | /workspace/10.chip_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/10.chip_tl_errors.2508305289 |
| Short name | T2294 |
| Test name | |
| Test status | |
| Simulation time | 3942475825 ps |
| CPU time | 391.34 seconds |
| Started | Aug 12 06:47:40 PM PDT 24 |
| Finished | Aug 12 06:54:11 PM PDT 24 |
| Peak memory | 603280 kb |
| Host | smart-957aae03-e35c-4416-806c-696d1b1d6685 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2508305289 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.chip_tl_errors.2508305289 |
| Directory | /workspace/10.chip_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/10.xbar_access_same_device.2675367389 |
| Short name | T1554 |
| Test name | |
| Test status | |
| Simulation time | 1155233584 ps |
| CPU time | 78.83 seconds |
| Started | Aug 12 06:47:51 PM PDT 24 |
| Finished | Aug 12 06:49:10 PM PDT 24 |
| Peak memory | 575724 kb |
| Host | smart-10b4e93f-5a47-42d7-8133-41cdfc2f177a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2675367389 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.xbar_access_same_device .2675367389 |
| Directory | /workspace/10.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/10.xbar_error_and_unmapped_addr.2808061577 |
| Short name | T2549 |
| Test name | |
| Test status | |
| Simulation time | 1117969684 ps |
| CPU time | 38.36 seconds |
| Started | Aug 12 06:47:42 PM PDT 24 |
| Finished | Aug 12 06:48:21 PM PDT 24 |
| Peak memory | 575588 kb |
| Host | smart-8afea334-bb46-4685-91c2-e3dbd4975d74 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2808061577 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.xbar_error_and_unmapped_add r.2808061577 |
| Directory | /workspace/10.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/10.xbar_error_random.2052277932 |
| Short name | T2487 |
| Test name | |
| Test status | |
| Simulation time | 322074211 ps |
| CPU time | 12.92 seconds |
| Started | Aug 12 06:47:43 PM PDT 24 |
| Finished | Aug 12 06:47:56 PM PDT 24 |
| Peak memory | 575748 kb |
| Host | smart-8056d444-4b86-4790-b364-90f0a7b4d7e7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2052277932 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.xbar_error_random.2052277932 |
| Directory | /workspace/10.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/10.xbar_random.2939179866 |
| Short name | T2175 |
| Test name | |
| Test status | |
| Simulation time | 410503541 ps |
| CPU time | 38.33 seconds |
| Started | Aug 12 06:47:41 PM PDT 24 |
| Finished | Aug 12 06:48:19 PM PDT 24 |
| Peak memory | 575676 kb |
| Host | smart-b58ad533-5b21-43cf-9198-97c1b9fd1af2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2939179866 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.xbar_random.2939179866 |
| Directory | /workspace/10.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/10.xbar_random_large_delays.3669915918 |
| Short name | T620 |
| Test name | |
| Test status | |
| Simulation time | 86052979570 ps |
| CPU time | 899.09 seconds |
| Started | Aug 12 06:47:43 PM PDT 24 |
| Finished | Aug 12 07:02:42 PM PDT 24 |
| Peak memory | 576496 kb |
| Host | smart-68cf374d-f0aa-40a9-9412-fd7fd5f0ffa9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3669915918 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.xbar_random_large_delays.3669915918 |
| Directory | /workspace/10.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/10.xbar_random_slow_rsp.752659909 |
| Short name | T2117 |
| Test name | |
| Test status | |
| Simulation time | 15016537300 ps |
| CPU time | 241.86 seconds |
| Started | Aug 12 06:47:40 PM PDT 24 |
| Finished | Aug 12 06:51:42 PM PDT 24 |
| Peak memory | 575748 kb |
| Host | smart-2b1abb0f-0981-460b-849c-3f72fec8f88f |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=752659909 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.xbar_random_slow_rsp.752659909 |
| Directory | /workspace/10.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/10.xbar_random_zero_delays.633210435 |
| Short name | T1690 |
| Test name | |
| Test status | |
| Simulation time | 153765588 ps |
| CPU time | 14.33 seconds |
| Started | Aug 12 06:47:43 PM PDT 24 |
| Finished | Aug 12 06:47:57 PM PDT 24 |
| Peak memory | 575664 kb |
| Host | smart-03961153-dd5d-443e-8aa9-dc2a210567f6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=633210435 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.xbar_random_zero_dela ys.633210435 |
| Directory | /workspace/10.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/10.xbar_same_source.2963863443 |
| Short name | T2416 |
| Test name | |
| Test status | |
| Simulation time | 2315750888 ps |
| CPU time | 65.92 seconds |
| Started | Aug 12 06:47:40 PM PDT 24 |
| Finished | Aug 12 06:48:46 PM PDT 24 |
| Peak memory | 575676 kb |
| Host | smart-bcec3773-a265-4374-b2bc-5d8870749106 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2963863443 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.xbar_same_source.2963863443 |
| Directory | /workspace/10.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/10.xbar_smoke.1532330106 |
| Short name | T2786 |
| Test name | |
| Test status | |
| Simulation time | 42569511 ps |
| CPU time | 5.79 seconds |
| Started | Aug 12 06:47:40 PM PDT 24 |
| Finished | Aug 12 06:47:46 PM PDT 24 |
| Peak memory | 573660 kb |
| Host | smart-4ed066bc-b7e4-4e1e-8525-6e9443be434c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1532330106 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.xbar_smoke.1532330106 |
| Directory | /workspace/10.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/10.xbar_smoke_large_delays.3765187644 |
| Short name | T2698 |
| Test name | |
| Test status | |
| Simulation time | 7911115732 ps |
| CPU time | 86.07 seconds |
| Started | Aug 12 06:47:42 PM PDT 24 |
| Finished | Aug 12 06:49:08 PM PDT 24 |
| Peak memory | 573628 kb |
| Host | smart-0220846b-960f-435f-b61e-6cbcdfe22a36 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3765187644 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.xbar_smoke_large_delays.3765187644 |
| Directory | /workspace/10.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/10.xbar_smoke_slow_rsp.3428622456 |
| Short name | T1617 |
| Test name | |
| Test status | |
| Simulation time | 5364077983 ps |
| CPU time | 91.95 seconds |
| Started | Aug 12 06:47:46 PM PDT 24 |
| Finished | Aug 12 06:49:18 PM PDT 24 |
| Peak memory | 574308 kb |
| Host | smart-a868b671-ba49-4664-ab5b-3f8ca4dea185 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3428622456 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.xbar_smoke_slow_rsp.3428622456 |
| Directory | /workspace/10.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/10.xbar_smoke_zero_delays.1177595374 |
| Short name | T2857 |
| Test name | |
| Test status | |
| Simulation time | 42488428 ps |
| CPU time | 6.54 seconds |
| Started | Aug 12 06:47:44 PM PDT 24 |
| Finished | Aug 12 06:47:50 PM PDT 24 |
| Peak memory | 573640 kb |
| Host | smart-26884ba2-f48f-4aa0-bd16-ae7f2d232c5a |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1177595374 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.xbar_smoke_zero_delay s.1177595374 |
| Directory | /workspace/10.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/10.xbar_stress_all.1526389720 |
| Short name | T2624 |
| Test name | |
| Test status | |
| Simulation time | 11667449228 ps |
| CPU time | 395.9 seconds |
| Started | Aug 12 06:47:44 PM PDT 24 |
| Finished | Aug 12 06:54:20 PM PDT 24 |
| Peak memory | 576020 kb |
| Host | smart-313ee75b-5848-45cd-98df-a9d75617ed70 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1526389720 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.xbar_stress_all.1526389720 |
| Directory | /workspace/10.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/10.xbar_stress_all_with_error.3940929365 |
| Short name | T1796 |
| Test name | |
| Test status | |
| Simulation time | 2257405935 ps |
| CPU time | 167.71 seconds |
| Started | Aug 12 06:47:46 PM PDT 24 |
| Finished | Aug 12 06:50:34 PM PDT 24 |
| Peak memory | 576096 kb |
| Host | smart-4a2bc004-a89a-4a59-8bc8-88ddf3f45f05 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3940929365 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.xbar_stress_all_with_error.3940929365 |
| Directory | /workspace/10.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/10.xbar_stress_all_with_reset_error.88136936 |
| Short name | T2217 |
| Test name | |
| Test status | |
| Simulation time | 3829962976 ps |
| CPU time | 471.97 seconds |
| Started | Aug 12 06:47:38 PM PDT 24 |
| Finished | Aug 12 06:55:30 PM PDT 24 |
| Peak memory | 576604 kb |
| Host | smart-e746351f-374c-4adf-a9aa-49709be1aa56 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=88136936 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_res et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.xbar_stress_all_ with_reset_error.88136936 |
| Directory | /workspace/10.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/10.xbar_unmapped_addr.1751423779 |
| Short name | T2420 |
| Test name | |
| Test status | |
| Simulation time | 1170587226 ps |
| CPU time | 46.84 seconds |
| Started | Aug 12 06:47:39 PM PDT 24 |
| Finished | Aug 12 06:48:26 PM PDT 24 |
| Peak memory | 575748 kb |
| Host | smart-a73044d2-6bb8-41df-9390-136c05817af6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1751423779 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.xbar_unmapped_addr.1751423779 |
| Directory | /workspace/10.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/11.chip_csr_mem_rw_with_rand_reset.499144850 |
| Short name | T1799 |
| Test name | |
| Test status | |
| Simulation time | 5910881008 ps |
| CPU time | 558.27 seconds |
| Started | Aug 12 06:47:48 PM PDT 24 |
| Finished | Aug 12 06:57:06 PM PDT 24 |
| Peak memory | 643404 kb |
| Host | smart-feb089f2-46ed-41d9-9f27-0e52c7e5740b |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=499144850 -assert nopostproc +U VM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top. vdb -cm_log /dev/null -cm_name 11.chip_csr_mem_rw_with_rand_reset.499144850 |
| Directory | /workspace/11.chip_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/11.chip_csr_rw.1956604329 |
| Short name | T1888 |
| Test name | |
| Test status | |
| Simulation time | 6208503064 ps |
| CPU time | 576.88 seconds |
| Started | Aug 12 06:48:02 PM PDT 24 |
| Finished | Aug 12 06:57:39 PM PDT 24 |
| Peak memory | 598392 kb |
| Host | smart-a62376ff-25bc-4b3f-957a-49aaaaad9e86 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1956604329 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.chip_csr_rw.1956604329 |
| Directory | /workspace/11.chip_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/11.chip_same_csr_outstanding.256832967 |
| Short name | T1953 |
| Test name | |
| Test status | |
| Simulation time | 29028202522 ps |
| CPU time | 3356.06 seconds |
| Started | Aug 12 06:47:41 PM PDT 24 |
| Finished | Aug 12 07:43:37 PM PDT 24 |
| Peak memory | 592928 kb |
| Host | smart-1c4cee50-3e07-4553-bf36-19fc68268c00 |
| User | root |
| Command | /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +run_same_csr_outstanding +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=256832967 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c m_log /dev/null -cm_name 11.chip_same_csr_outstanding.256832967 |
| Directory | /workspace/11.chip_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/11.chip_tl_errors.903288801 |
| Short name | T2739 |
| Test name | |
| Test status | |
| Simulation time | 3053096110 ps |
| CPU time | 141.67 seconds |
| Started | Aug 12 06:47:43 PM PDT 24 |
| Finished | Aug 12 06:50:05 PM PDT 24 |
| Peak memory | 601292 kb |
| Host | smart-9d645283-1dec-47ac-99bf-27bd334b30b5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=903288801 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.chip_tl_errors.903288801 |
| Directory | /workspace/11.chip_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/11.xbar_access_same_device.3049039991 |
| Short name | T1704 |
| Test name | |
| Test status | |
| Simulation time | 343538616 ps |
| CPU time | 20.59 seconds |
| Started | Aug 12 06:47:44 PM PDT 24 |
| Finished | Aug 12 06:48:05 PM PDT 24 |
| Peak memory | 575600 kb |
| Host | smart-54e6b528-c1e1-47d3-83ab-d06f3f69eee0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3049039991 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.xbar_access_same_device .3049039991 |
| Directory | /workspace/11.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/11.xbar_access_same_device_slow_rsp.3513463566 |
| Short name | T919 |
| Test name | |
| Test status | |
| Simulation time | 61659619697 ps |
| CPU time | 932.24 seconds |
| Started | Aug 12 06:47:44 PM PDT 24 |
| Finished | Aug 12 07:03:17 PM PDT 24 |
| Peak memory | 575644 kb |
| Host | smart-f25a5e0a-4806-4f79-ac56-8afd798760cc |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3513463566 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.xbar_access_same_ device_slow_rsp.3513463566 |
| Directory | /workspace/11.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/11.xbar_error_and_unmapped_addr.577355229 |
| Short name | T2183 |
| Test name | |
| Test status | |
| Simulation time | 862312505 ps |
| CPU time | 38.05 seconds |
| Started | Aug 12 06:47:48 PM PDT 24 |
| Finished | Aug 12 06:48:26 PM PDT 24 |
| Peak memory | 575668 kb |
| Host | smart-f3124581-fe42-4f7f-8503-894407aea02f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=577355229 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.xbar_error_and_unmapped_addr .577355229 |
| Directory | /workspace/11.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/11.xbar_error_random.4001144790 |
| Short name | T1958 |
| Test name | |
| Test status | |
| Simulation time | 1838290928 ps |
| CPU time | 60.56 seconds |
| Started | Aug 12 06:47:49 PM PDT 24 |
| Finished | Aug 12 06:48:50 PM PDT 24 |
| Peak memory | 575544 kb |
| Host | smart-41252633-b547-4539-8596-f733275ccbb3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4001144790 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.xbar_error_random.4001144790 |
| Directory | /workspace/11.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/11.xbar_random.1135617427 |
| Short name | T440 |
| Test name | |
| Test status | |
| Simulation time | 580950800 ps |
| CPU time | 54.17 seconds |
| Started | Aug 12 06:47:55 PM PDT 24 |
| Finished | Aug 12 06:48:49 PM PDT 24 |
| Peak memory | 575708 kb |
| Host | smart-9f0d1c0d-b161-4922-b8c7-1a0e49886f3a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1135617427 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.xbar_random.1135617427 |
| Directory | /workspace/11.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/11.xbar_random_large_delays.1967682424 |
| Short name | T2345 |
| Test name | |
| Test status | |
| Simulation time | 7612543693 ps |
| CPU time | 82.13 seconds |
| Started | Aug 12 06:47:44 PM PDT 24 |
| Finished | Aug 12 06:49:07 PM PDT 24 |
| Peak memory | 575576 kb |
| Host | smart-b0db2a91-2b5c-4595-8e30-aac2f53e91b5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1967682424 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.xbar_random_large_delays.1967682424 |
| Directory | /workspace/11.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/11.xbar_random_slow_rsp.1367588335 |
| Short name | T485 |
| Test name | |
| Test status | |
| Simulation time | 43335606050 ps |
| CPU time | 677.43 seconds |
| Started | Aug 12 06:47:38 PM PDT 24 |
| Finished | Aug 12 06:58:56 PM PDT 24 |
| Peak memory | 575828 kb |
| Host | smart-8536c44c-856c-4f3d-bb68-7cd2584f57de |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1367588335 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.xbar_random_slow_rsp.1367588335 |
| Directory | /workspace/11.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/11.xbar_random_zero_delays.395419956 |
| Short name | T517 |
| Test name | |
| Test status | |
| Simulation time | 195703663 ps |
| CPU time | 19.73 seconds |
| Started | Aug 12 06:47:40 PM PDT 24 |
| Finished | Aug 12 06:48:00 PM PDT 24 |
| Peak memory | 575684 kb |
| Host | smart-cdbe3009-982d-458d-98d4-49b47aa8512d |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=395419956 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.xbar_random_zero_dela ys.395419956 |
| Directory | /workspace/11.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/11.xbar_same_source.1448754201 |
| Short name | T1946 |
| Test name | |
| Test status | |
| Simulation time | 2468683806 ps |
| CPU time | 67.21 seconds |
| Started | Aug 12 06:48:08 PM PDT 24 |
| Finished | Aug 12 06:49:15 PM PDT 24 |
| Peak memory | 575660 kb |
| Host | smart-dfd7c588-1837-4c2d-9ad1-c1fbf88de3c0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1448754201 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.xbar_same_source.1448754201 |
| Directory | /workspace/11.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/11.xbar_smoke.139535498 |
| Short name | T2264 |
| Test name | |
| Test status | |
| Simulation time | 43355574 ps |
| CPU time | 5.47 seconds |
| Started | Aug 12 06:47:46 PM PDT 24 |
| Finished | Aug 12 06:47:52 PM PDT 24 |
| Peak memory | 574232 kb |
| Host | smart-0c75481f-fbdc-4599-942f-26fee3590d17 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=139535498 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.xbar_smoke.139535498 |
| Directory | /workspace/11.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/11.xbar_smoke_large_delays.809997675 |
| Short name | T599 |
| Test name | |
| Test status | |
| Simulation time | 7969831373 ps |
| CPU time | 84.44 seconds |
| Started | Aug 12 06:47:44 PM PDT 24 |
| Finished | Aug 12 06:49:09 PM PDT 24 |
| Peak memory | 573656 kb |
| Host | smart-6d21460b-30b9-4040-90cb-b05f1651f694 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=809997675 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.xbar_smoke_large_delays.809997675 |
| Directory | /workspace/11.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/11.xbar_smoke_slow_rsp.49099737 |
| Short name | T1789 |
| Test name | |
| Test status | |
| Simulation time | 6328978622 ps |
| CPU time | 106.84 seconds |
| Started | Aug 12 06:47:41 PM PDT 24 |
| Finished | Aug 12 06:49:28 PM PDT 24 |
| Peak memory | 573668 kb |
| Host | smart-dd9d62dd-91e7-406d-ad3f-fb034d7e4e28 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49099737 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.xbar_smoke_slow_rsp.49099737 |
| Directory | /workspace/11.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/11.xbar_smoke_zero_delays.3627506125 |
| Short name | T2637 |
| Test name | |
| Test status | |
| Simulation time | 47714910 ps |
| CPU time | 6.14 seconds |
| Started | Aug 12 06:47:40 PM PDT 24 |
| Finished | Aug 12 06:47:46 PM PDT 24 |
| Peak memory | 573556 kb |
| Host | smart-e4630cb9-810e-4395-879e-405ead07adf1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3627506125 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.xbar_smoke_zero_delay s.3627506125 |
| Directory | /workspace/11.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/11.xbar_stress_all.146609726 |
| Short name | T731 |
| Test name | |
| Test status | |
| Simulation time | 5958045559 ps |
| CPU time | 238.68 seconds |
| Started | Aug 12 06:47:59 PM PDT 24 |
| Finished | Aug 12 06:51:58 PM PDT 24 |
| Peak memory | 575780 kb |
| Host | smart-bae29612-69b3-4f2a-85c7-a2e5ad15f8e4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=146609726 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.xbar_stress_all.146609726 |
| Directory | /workspace/11.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/11.xbar_stress_all_with_error.3451102619 |
| Short name | T2451 |
| Test name | |
| Test status | |
| Simulation time | 455524476 ps |
| CPU time | 19.29 seconds |
| Started | Aug 12 06:47:49 PM PDT 24 |
| Finished | Aug 12 06:48:08 PM PDT 24 |
| Peak memory | 575692 kb |
| Host | smart-fcb00802-9d41-4ea2-983d-c61988986fa4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3451102619 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.xbar_stress_all_with_error.3451102619 |
| Directory | /workspace/11.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/11.xbar_stress_all_with_rand_reset.2844487931 |
| Short name | T592 |
| Test name | |
| Test status | |
| Simulation time | 3109779884 ps |
| CPU time | 433.16 seconds |
| Started | Aug 12 06:48:03 PM PDT 24 |
| Finished | Aug 12 06:55:16 PM PDT 24 |
| Peak memory | 576552 kb |
| Host | smart-1c61acba-59a9-47f6-be5b-92b121c6e5bb |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2844487931 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.xbar_stress_all _with_rand_reset.2844487931 |
| Directory | /workspace/11.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/11.xbar_stress_all_with_reset_error.2404294566 |
| Short name | T1591 |
| Test name | |
| Test status | |
| Simulation time | 2918071463 ps |
| CPU time | 195.28 seconds |
| Started | Aug 12 06:47:59 PM PDT 24 |
| Finished | Aug 12 06:51:15 PM PDT 24 |
| Peak memory | 576544 kb |
| Host | smart-4babf508-729d-4110-8940-aa71a1f95eac |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2404294566 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.xbar_stress_al l_with_reset_error.2404294566 |
| Directory | /workspace/11.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/11.xbar_unmapped_addr.1417339776 |
| Short name | T2427 |
| Test name | |
| Test status | |
| Simulation time | 435841924 ps |
| CPU time | 17.81 seconds |
| Started | Aug 12 06:47:51 PM PDT 24 |
| Finished | Aug 12 06:48:09 PM PDT 24 |
| Peak memory | 575592 kb |
| Host | smart-4d93369e-bba4-4c6b-8334-a8d81b1900d7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1417339776 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.xbar_unmapped_addr.1417339776 |
| Directory | /workspace/11.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/12.chip_csr_mem_rw_with_rand_reset.340908496 |
| Short name | T2708 |
| Test name | |
| Test status | |
| Simulation time | 5976896250 ps |
| CPU time | 430.45 seconds |
| Started | Aug 12 06:47:51 PM PDT 24 |
| Finished | Aug 12 06:55:01 PM PDT 24 |
| Peak memory | 636200 kb |
| Host | smart-59710805-dff8-4a72-ac1d-c47ce47308c9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=340908496 -assert nopostproc +U VM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top. vdb -cm_log /dev/null -cm_name 12.chip_csr_mem_rw_with_rand_reset.340908496 |
| Directory | /workspace/12.chip_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/12.chip_csr_rw.459446538 |
| Short name | T1872 |
| Test name | |
| Test status | |
| Simulation time | 6073767984 ps |
| CPU time | 701.2 seconds |
| Started | Aug 12 06:48:05 PM PDT 24 |
| Finished | Aug 12 06:59:46 PM PDT 24 |
| Peak memory | 598016 kb |
| Host | smart-19da7b84-9c88-42e8-a9ff-e840cef1d927 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=459446538 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.chip_csr_rw.459446538 |
| Directory | /workspace/12.chip_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/12.chip_same_csr_outstanding.569050366 |
| Short name | T2471 |
| Test name | |
| Test status | |
| Simulation time | 15267363997 ps |
| CPU time | 1703.4 seconds |
| Started | Aug 12 06:47:51 PM PDT 24 |
| Finished | Aug 12 07:16:15 PM PDT 24 |
| Peak memory | 592928 kb |
| Host | smart-8b6bac16-7c15-48d6-b8dd-d7d6443f5997 |
| User | root |
| Command | /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +run_same_csr_outstanding +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=569050366 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c m_log /dev/null -cm_name 12.chip_same_csr_outstanding.569050366 |
| Directory | /workspace/12.chip_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/12.chip_tl_errors.1352635862 |
| Short name | T805 |
| Test name | |
| Test status | |
| Simulation time | 2576166800 ps |
| CPU time | 109.97 seconds |
| Started | Aug 12 06:48:08 PM PDT 24 |
| Finished | Aug 12 06:49:58 PM PDT 24 |
| Peak memory | 598152 kb |
| Host | smart-334c8ad8-6a88-4e78-b49b-89f55f014b54 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1352635862 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.chip_tl_errors.1352635862 |
| Directory | /workspace/12.chip_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/12.xbar_access_same_device.2300597192 |
| Short name | T1919 |
| Test name | |
| Test status | |
| Simulation time | 484522429 ps |
| CPU time | 36.58 seconds |
| Started | Aug 12 06:47:58 PM PDT 24 |
| Finished | Aug 12 06:48:35 PM PDT 24 |
| Peak memory | 575676 kb |
| Host | smart-fb6e898e-e94a-49ca-9def-1a62fbf9d0ba |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2300597192 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.xbar_access_same_device .2300597192 |
| Directory | /workspace/12.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/12.xbar_access_same_device_slow_rsp.3523788437 |
| Short name | T1996 |
| Test name | |
| Test status | |
| Simulation time | 118454994747 ps |
| CPU time | 2121.08 seconds |
| Started | Aug 12 06:47:52 PM PDT 24 |
| Finished | Aug 12 07:23:13 PM PDT 24 |
| Peak memory | 575812 kb |
| Host | smart-709b5588-3c0e-438f-a432-e85950b811dc |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3523788437 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.xbar_access_same_ device_slow_rsp.3523788437 |
| Directory | /workspace/12.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/12.xbar_error_and_unmapped_addr.2296611409 |
| Short name | T1795 |
| Test name | |
| Test status | |
| Simulation time | 171345075 ps |
| CPU time | 16.31 seconds |
| Started | Aug 12 06:48:00 PM PDT 24 |
| Finished | Aug 12 06:48:16 PM PDT 24 |
| Peak memory | 575764 kb |
| Host | smart-4885bb74-cce3-4555-a1fa-e22cba4d1c0a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2296611409 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.xbar_error_and_unmapped_add r.2296611409 |
| Directory | /workspace/12.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/12.xbar_error_random.1328602922 |
| Short name | T1633 |
| Test name | |
| Test status | |
| Simulation time | 264669662 ps |
| CPU time | 21.4 seconds |
| Started | Aug 12 06:47:50 PM PDT 24 |
| Finished | Aug 12 06:48:12 PM PDT 24 |
| Peak memory | 575732 kb |
| Host | smart-fad86a51-9f06-4cc0-9862-a5b28abe2961 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1328602922 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.xbar_error_random.1328602922 |
| Directory | /workspace/12.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/12.xbar_random.1986207279 |
| Short name | T1995 |
| Test name | |
| Test status | |
| Simulation time | 520619674 ps |
| CPU time | 40.2 seconds |
| Started | Aug 12 06:47:51 PM PDT 24 |
| Finished | Aug 12 06:48:31 PM PDT 24 |
| Peak memory | 575500 kb |
| Host | smart-936bfa86-22f1-41c9-8878-bec4cd5f808f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1986207279 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.xbar_random.1986207279 |
| Directory | /workspace/12.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/12.xbar_random_large_delays.1888059680 |
| Short name | T2061 |
| Test name | |
| Test status | |
| Simulation time | 57128914700 ps |
| CPU time | 580.36 seconds |
| Started | Aug 12 06:47:58 PM PDT 24 |
| Finished | Aug 12 06:57:38 PM PDT 24 |
| Peak memory | 575756 kb |
| Host | smart-8b9ff364-2284-4160-bb59-379e79313f2c |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1888059680 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.xbar_random_large_delays.1888059680 |
| Directory | /workspace/12.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/12.xbar_random_slow_rsp.2707192773 |
| Short name | T2376 |
| Test name | |
| Test status | |
| Simulation time | 47827322085 ps |
| CPU time | 854.23 seconds |
| Started | Aug 12 06:47:58 PM PDT 24 |
| Finished | Aug 12 07:02:12 PM PDT 24 |
| Peak memory | 575800 kb |
| Host | smart-701ce650-a834-4c43-af63-b1194b6ac4a2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2707192773 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.xbar_random_slow_rsp.2707192773 |
| Directory | /workspace/12.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/12.xbar_random_zero_delays.699764995 |
| Short name | T675 |
| Test name | |
| Test status | |
| Simulation time | 187240124 ps |
| CPU time | 18.99 seconds |
| Started | Aug 12 06:47:57 PM PDT 24 |
| Finished | Aug 12 06:48:16 PM PDT 24 |
| Peak memory | 575564 kb |
| Host | smart-b9cc9e81-e57f-4d93-aeb5-77ee2bc3a4a4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=699764995 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.xbar_random_zero_dela ys.699764995 |
| Directory | /workspace/12.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/12.xbar_same_source.1106997097 |
| Short name | T2165 |
| Test name | |
| Test status | |
| Simulation time | 2590184742 ps |
| CPU time | 77.62 seconds |
| Started | Aug 12 06:48:05 PM PDT 24 |
| Finished | Aug 12 06:49:23 PM PDT 24 |
| Peak memory | 575616 kb |
| Host | smart-828f4494-774b-4f46-af79-38f6585441fe |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1106997097 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.xbar_same_source.1106997097 |
| Directory | /workspace/12.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/12.xbar_smoke.3725481665 |
| Short name | T2726 |
| Test name | |
| Test status | |
| Simulation time | 151112402 ps |
| CPU time | 7.78 seconds |
| Started | Aug 12 06:47:52 PM PDT 24 |
| Finished | Aug 12 06:48:00 PM PDT 24 |
| Peak memory | 574220 kb |
| Host | smart-688e2d1b-76d6-4258-a3bb-63773a9bf149 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3725481665 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.xbar_smoke.3725481665 |
| Directory | /workspace/12.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/12.xbar_smoke_large_delays.1266979325 |
| Short name | T1623 |
| Test name | |
| Test status | |
| Simulation time | 9617234357 ps |
| CPU time | 93.54 seconds |
| Started | Aug 12 06:47:52 PM PDT 24 |
| Finished | Aug 12 06:49:25 PM PDT 24 |
| Peak memory | 573608 kb |
| Host | smart-7dc95a09-ebbf-401f-a176-da91f07a697c |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1266979325 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.xbar_smoke_large_delays.1266979325 |
| Directory | /workspace/12.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/12.xbar_smoke_slow_rsp.1164026098 |
| Short name | T1542 |
| Test name | |
| Test status | |
| Simulation time | 3742332906 ps |
| CPU time | 59.59 seconds |
| Started | Aug 12 06:47:49 PM PDT 24 |
| Finished | Aug 12 06:48:49 PM PDT 24 |
| Peak memory | 573640 kb |
| Host | smart-e2bd6e94-ac04-46fd-9f8d-ecde42e5e058 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1164026098 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.xbar_smoke_slow_rsp.1164026098 |
| Directory | /workspace/12.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/12.xbar_smoke_zero_delays.4234940088 |
| Short name | T1975 |
| Test name | |
| Test status | |
| Simulation time | 45091740 ps |
| CPU time | 6.14 seconds |
| Started | Aug 12 06:47:50 PM PDT 24 |
| Finished | Aug 12 06:47:57 PM PDT 24 |
| Peak memory | 573616 kb |
| Host | smart-67e3b588-76f4-432f-9e5e-295bf97d238c |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4234940088 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.xbar_smoke_zero_delay s.4234940088 |
| Directory | /workspace/12.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/12.xbar_stress_all.1739704476 |
| Short name | T1784 |
| Test name | |
| Test status | |
| Simulation time | 462229070 ps |
| CPU time | 18.58 seconds |
| Started | Aug 12 06:47:48 PM PDT 24 |
| Finished | Aug 12 06:48:07 PM PDT 24 |
| Peak memory | 575780 kb |
| Host | smart-f3873d70-aa30-4ce7-b525-413df7602596 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1739704476 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.xbar_stress_all.1739704476 |
| Directory | /workspace/12.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/12.xbar_stress_all_with_error.2876264626 |
| Short name | T896 |
| Test name | |
| Test status | |
| Simulation time | 16371086537 ps |
| CPU time | 597.27 seconds |
| Started | Aug 12 06:48:02 PM PDT 24 |
| Finished | Aug 12 06:57:59 PM PDT 24 |
| Peak memory | 576568 kb |
| Host | smart-725929c6-b5e9-4307-84ea-d0d334c1c8ad |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2876264626 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.xbar_stress_all_with_error.2876264626 |
| Directory | /workspace/12.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/12.xbar_stress_all_with_rand_reset.2806241413 |
| Short name | T2721 |
| Test name | |
| Test status | |
| Simulation time | 6304829672 ps |
| CPU time | 519.43 seconds |
| Started | Aug 12 06:47:58 PM PDT 24 |
| Finished | Aug 12 06:56:37 PM PDT 24 |
| Peak memory | 575784 kb |
| Host | smart-3934cfe7-abcb-4852-a110-536a68770c47 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2806241413 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.xbar_stress_all _with_rand_reset.2806241413 |
| Directory | /workspace/12.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/12.xbar_unmapped_addr.3043110172 |
| Short name | T1569 |
| Test name | |
| Test status | |
| Simulation time | 1305971117 ps |
| CPU time | 53.37 seconds |
| Started | Aug 12 06:47:48 PM PDT 24 |
| Finished | Aug 12 06:48:42 PM PDT 24 |
| Peak memory | 575560 kb |
| Host | smart-c3269daf-c691-450c-9767-361ea888eb2d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3043110172 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.xbar_unmapped_addr.3043110172 |
| Directory | /workspace/12.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/13.chip_csr_mem_rw_with_rand_reset.603594421 |
| Short name | T544 |
| Test name | |
| Test status | |
| Simulation time | 7809888892 ps |
| CPU time | 418.68 seconds |
| Started | Aug 12 06:47:59 PM PDT 24 |
| Finished | Aug 12 06:54:57 PM PDT 24 |
| Peak memory | 644980 kb |
| Host | smart-0076048a-5f10-423c-9260-be8175b0d4af |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=603594421 -assert nopostproc +U VM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top. vdb -cm_log /dev/null -cm_name 13.chip_csr_mem_rw_with_rand_reset.603594421 |
| Directory | /workspace/13.chip_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/13.chip_csr_rw.3389791313 |
| Short name | T457 |
| Test name | |
| Test status | |
| Simulation time | 6236188524 ps |
| CPU time | 628.6 seconds |
| Started | Aug 12 06:48:07 PM PDT 24 |
| Finished | Aug 12 06:58:36 PM PDT 24 |
| Peak memory | 598584 kb |
| Host | smart-6f55cbb2-b67f-4b5f-b173-71ba0993b248 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3389791313 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.chip_csr_rw.3389791313 |
| Directory | /workspace/13.chip_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/13.chip_same_csr_outstanding.3035247511 |
| Short name | T403 |
| Test name | |
| Test status | |
| Simulation time | 16875359033 ps |
| CPU time | 2847.8 seconds |
| Started | Aug 12 06:48:12 PM PDT 24 |
| Finished | Aug 12 07:35:41 PM PDT 24 |
| Peak memory | 592908 kb |
| Host | smart-d5d0e8d2-84c3-4d1b-918a-b675fc7dddaa |
| User | root |
| Command | /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +run_same_csr_outstanding +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3035247511 -assert nopostproc +UVM_TE STNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb - cm_log /dev/null -cm_name 13.chip_same_csr_outstanding.3035247511 |
| Directory | /workspace/13.chip_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/13.chip_tl_errors.1277049791 |
| Short name | T574 |
| Test name | |
| Test status | |
| Simulation time | 4077698281 ps |
| CPU time | 285.38 seconds |
| Started | Aug 12 06:47:57 PM PDT 24 |
| Finished | Aug 12 06:52:43 PM PDT 24 |
| Peak memory | 598228 kb |
| Host | smart-4e4ece11-284e-4ec2-b0d0-91d0d164b253 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1277049791 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.chip_tl_errors.1277049791 |
| Directory | /workspace/13.chip_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/13.xbar_access_same_device.3898018633 |
| Short name | T2366 |
| Test name | |
| Test status | |
| Simulation time | 1610366750 ps |
| CPU time | 75.47 seconds |
| Started | Aug 12 06:48:05 PM PDT 24 |
| Finished | Aug 12 06:49:21 PM PDT 24 |
| Peak memory | 575524 kb |
| Host | smart-a03974ca-c02c-45ae-a870-440106ed01e3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3898018633 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.xbar_access_same_device .3898018633 |
| Directory | /workspace/13.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/13.xbar_access_same_device_slow_rsp.4014546451 |
| Short name | T2147 |
| Test name | |
| Test status | |
| Simulation time | 151380000554 ps |
| CPU time | 2687.08 seconds |
| Started | Aug 12 06:47:59 PM PDT 24 |
| Finished | Aug 12 07:32:47 PM PDT 24 |
| Peak memory | 575880 kb |
| Host | smart-7397ff3a-1605-457c-ab19-ba0fb775e9a4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4014546451 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.xbar_access_same_ device_slow_rsp.4014546451 |
| Directory | /workspace/13.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/13.xbar_error_and_unmapped_addr.1054923652 |
| Short name | T2421 |
| Test name | |
| Test status | |
| Simulation time | 179074800 ps |
| CPU time | 19.39 seconds |
| Started | Aug 12 06:47:59 PM PDT 24 |
| Finished | Aug 12 06:48:18 PM PDT 24 |
| Peak memory | 575724 kb |
| Host | smart-93bfb76e-13b5-48d6-bd85-aa3e49e7422f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1054923652 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.xbar_error_and_unmapped_add r.1054923652 |
| Directory | /workspace/13.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/13.xbar_error_random.37340868 |
| Short name | T1812 |
| Test name | |
| Test status | |
| Simulation time | 2296541197 ps |
| CPU time | 68.57 seconds |
| Started | Aug 12 06:48:01 PM PDT 24 |
| Finished | Aug 12 06:49:10 PM PDT 24 |
| Peak memory | 575572 kb |
| Host | smart-a98abed9-c9cc-484a-bd4f-79f2714eac62 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37340868 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.xbar_error_random.37340868 |
| Directory | /workspace/13.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/13.xbar_random.3999296735 |
| Short name | T646 |
| Test name | |
| Test status | |
| Simulation time | 398916254 ps |
| CPU time | 16.57 seconds |
| Started | Aug 12 06:48:01 PM PDT 24 |
| Finished | Aug 12 06:48:18 PM PDT 24 |
| Peak memory | 575528 kb |
| Host | smart-5a0041fa-87d3-4c63-904b-2130ed698c4d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3999296735 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.xbar_random.3999296735 |
| Directory | /workspace/13.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/13.xbar_random_large_delays.2157040393 |
| Short name | T2943 |
| Test name | |
| Test status | |
| Simulation time | 102537107665 ps |
| CPU time | 1050.45 seconds |
| Started | Aug 12 06:47:48 PM PDT 24 |
| Finished | Aug 12 07:05:19 PM PDT 24 |
| Peak memory | 575864 kb |
| Host | smart-90356769-1fda-4301-be90-50f4bb0d6ea9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2157040393 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.xbar_random_large_delays.2157040393 |
| Directory | /workspace/13.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/13.xbar_random_slow_rsp.422004697 |
| Short name | T603 |
| Test name | |
| Test status | |
| Simulation time | 15217003285 ps |
| CPU time | 259.71 seconds |
| Started | Aug 12 06:47:51 PM PDT 24 |
| Finished | Aug 12 06:52:11 PM PDT 24 |
| Peak memory | 575852 kb |
| Host | smart-55e91f31-a745-4ac0-9ec6-1c45da51ed4f |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=422004697 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.xbar_random_slow_rsp.422004697 |
| Directory | /workspace/13.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/13.xbar_random_zero_delays.1594585495 |
| Short name | T638 |
| Test name | |
| Test status | |
| Simulation time | 533007167 ps |
| CPU time | 44.39 seconds |
| Started | Aug 12 06:48:04 PM PDT 24 |
| Finished | Aug 12 06:48:49 PM PDT 24 |
| Peak memory | 575620 kb |
| Host | smart-6916f826-57a9-4348-a983-ff218e2e906b |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1594585495 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.xbar_random_zero_del ays.1594585495 |
| Directory | /workspace/13.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/13.xbar_same_source.3567794892 |
| Short name | T2430 |
| Test name | |
| Test status | |
| Simulation time | 471290113 ps |
| CPU time | 36.62 seconds |
| Started | Aug 12 06:48:02 PM PDT 24 |
| Finished | Aug 12 06:48:39 PM PDT 24 |
| Peak memory | 575636 kb |
| Host | smart-8dfc71fa-0c80-44bd-9afa-75a318f5562c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3567794892 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.xbar_same_source.3567794892 |
| Directory | /workspace/13.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/13.xbar_smoke.243857282 |
| Short name | T2768 |
| Test name | |
| Test status | |
| Simulation time | 254193116 ps |
| CPU time | 9.9 seconds |
| Started | Aug 12 06:47:46 PM PDT 24 |
| Finished | Aug 12 06:47:56 PM PDT 24 |
| Peak memory | 573624 kb |
| Host | smart-6b8d2669-b6f0-405c-aaaa-6829577b1877 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=243857282 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.xbar_smoke.243857282 |
| Directory | /workspace/13.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/13.xbar_smoke_large_delays.881355589 |
| Short name | T1985 |
| Test name | |
| Test status | |
| Simulation time | 7514086894 ps |
| CPU time | 76.61 seconds |
| Started | Aug 12 06:48:02 PM PDT 24 |
| Finished | Aug 12 06:49:18 PM PDT 24 |
| Peak memory | 574344 kb |
| Host | smart-e7438bc7-5843-4b50-908c-1fe94c8711dc |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=881355589 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.xbar_smoke_large_delays.881355589 |
| Directory | /workspace/13.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/13.xbar_smoke_slow_rsp.879023943 |
| Short name | T2903 |
| Test name | |
| Test status | |
| Simulation time | 5502748801 ps |
| CPU time | 89.14 seconds |
| Started | Aug 12 06:48:02 PM PDT 24 |
| Finished | Aug 12 06:49:32 PM PDT 24 |
| Peak memory | 573616 kb |
| Host | smart-2570b729-66e3-48d9-935a-345c1dc189c7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=879023943 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.xbar_smoke_slow_rsp.879023943 |
| Directory | /workspace/13.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/13.xbar_smoke_zero_delays.2145384054 |
| Short name | T1989 |
| Test name | |
| Test status | |
| Simulation time | 42307435 ps |
| CPU time | 5.85 seconds |
| Started | Aug 12 06:47:51 PM PDT 24 |
| Finished | Aug 12 06:47:57 PM PDT 24 |
| Peak memory | 573528 kb |
| Host | smart-4fed7c46-d655-4688-9804-0a892c8e3c84 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2145384054 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.xbar_smoke_zero_delay s.2145384054 |
| Directory | /workspace/13.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/13.xbar_stress_all.1792497385 |
| Short name | T2200 |
| Test name | |
| Test status | |
| Simulation time | 1683439642 ps |
| CPU time | 135.53 seconds |
| Started | Aug 12 06:47:58 PM PDT 24 |
| Finished | Aug 12 06:50:13 PM PDT 24 |
| Peak memory | 575688 kb |
| Host | smart-150089df-5d41-4c78-b6a3-2c2d1d07f906 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1792497385 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.xbar_stress_all.1792497385 |
| Directory | /workspace/13.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/13.xbar_stress_all_with_error.696195586 |
| Short name | T1921 |
| Test name | |
| Test status | |
| Simulation time | 4823837292 ps |
| CPU time | 342.52 seconds |
| Started | Aug 12 06:48:05 PM PDT 24 |
| Finished | Aug 12 06:53:47 PM PDT 24 |
| Peak memory | 576540 kb |
| Host | smart-5bf47a4a-cf5b-4a01-a2f3-d5dbe6c31eb6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=696195586 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.xbar_stress_all_with_error.696195586 |
| Directory | /workspace/13.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/13.xbar_stress_all_with_rand_reset.3505681939 |
| Short name | T2814 |
| Test name | |
| Test status | |
| Simulation time | 24946174 ps |
| CPU time | 14.74 seconds |
| Started | Aug 12 06:48:12 PM PDT 24 |
| Finished | Aug 12 06:48:27 PM PDT 24 |
| Peak memory | 574332 kb |
| Host | smart-ffe669cb-2dff-40ee-8af9-acce63728028 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3505681939 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.xbar_stress_all _with_rand_reset.3505681939 |
| Directory | /workspace/13.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/13.xbar_unmapped_addr.4091908114 |
| Short name | T2840 |
| Test name | |
| Test status | |
| Simulation time | 541847521 ps |
| CPU time | 23.01 seconds |
| Started | Aug 12 06:48:00 PM PDT 24 |
| Finished | Aug 12 06:48:23 PM PDT 24 |
| Peak memory | 575560 kb |
| Host | smart-f50b9a13-5bf4-4937-be6b-7f4e4eb9f815 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4091908114 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.xbar_unmapped_addr.4091908114 |
| Directory | /workspace/13.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/14.chip_csr_mem_rw_with_rand_reset.2456255350 |
| Short name | T2587 |
| Test name | |
| Test status | |
| Simulation time | 7477662392 ps |
| CPU time | 464.45 seconds |
| Started | Aug 12 06:48:05 PM PDT 24 |
| Finished | Aug 12 06:55:50 PM PDT 24 |
| Peak memory | 638296 kb |
| Host | smart-b05aa998-eddc-41ec-9ea1-96c8c0204820 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2456255350 -assert nopostproc + UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top .vdb -cm_log /dev/null -cm_name 14.chip_csr_mem_rw_with_rand_reset.2456255350 |
| Directory | /workspace/14.chip_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/14.chip_csr_rw.921819616 |
| Short name | T2481 |
| Test name | |
| Test status | |
| Simulation time | 6613575929 ps |
| CPU time | 533.79 seconds |
| Started | Aug 12 06:48:06 PM PDT 24 |
| Finished | Aug 12 06:56:59 PM PDT 24 |
| Peak memory | 598628 kb |
| Host | smart-e8ac2259-77fa-4ea2-954e-2170b58ef54a |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=921819616 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.chip_csr_rw.921819616 |
| Directory | /workspace/14.chip_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/14.chip_same_csr_outstanding.2441990428 |
| Short name | T406 |
| Test name | |
| Test status | |
| Simulation time | 31625518455 ps |
| CPU time | 4675.57 seconds |
| Started | Aug 12 06:47:59 PM PDT 24 |
| Finished | Aug 12 08:05:55 PM PDT 24 |
| Peak memory | 592992 kb |
| Host | smart-7278dda7-3147-4e5c-b88d-b4a90df50771 |
| User | root |
| Command | /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +run_same_csr_outstanding +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2441990428 -assert nopostproc +UVM_TE STNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb - cm_log /dev/null -cm_name 14.chip_same_csr_outstanding.2441990428 |
| Directory | /workspace/14.chip_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/14.xbar_access_same_device.3846482835 |
| Short name | T895 |
| Test name | |
| Test status | |
| Simulation time | 1961037738 ps |
| CPU time | 71.37 seconds |
| Started | Aug 12 06:48:01 PM PDT 24 |
| Finished | Aug 12 06:49:12 PM PDT 24 |
| Peak memory | 575700 kb |
| Host | smart-089e4f08-72c0-4c87-a902-34cd414b9a15 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3846482835 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.xbar_access_same_device .3846482835 |
| Directory | /workspace/14.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/14.xbar_error_and_unmapped_addr.807011914 |
| Short name | T1703 |
| Test name | |
| Test status | |
| Simulation time | 313591404 ps |
| CPU time | 13.15 seconds |
| Started | Aug 12 06:48:05 PM PDT 24 |
| Finished | Aug 12 06:48:19 PM PDT 24 |
| Peak memory | 575688 kb |
| Host | smart-7e0d6efc-738e-4582-894b-a8ee5cf13d1b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=807011914 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.xbar_error_and_unmapped_addr .807011914 |
| Directory | /workspace/14.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/14.xbar_error_random.3633895716 |
| Short name | T1648 |
| Test name | |
| Test status | |
| Simulation time | 499102429 ps |
| CPU time | 19.26 seconds |
| Started | Aug 12 06:48:12 PM PDT 24 |
| Finished | Aug 12 06:48:32 PM PDT 24 |
| Peak memory | 575628 kb |
| Host | smart-0d7ac566-8611-49fa-9901-606fd6cb6695 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3633895716 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.xbar_error_random.3633895716 |
| Directory | /workspace/14.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/14.xbar_random.2634386701 |
| Short name | T504 |
| Test name | |
| Test status | |
| Simulation time | 1697604038 ps |
| CPU time | 52.85 seconds |
| Started | Aug 12 06:48:07 PM PDT 24 |
| Finished | Aug 12 06:49:00 PM PDT 24 |
| Peak memory | 575548 kb |
| Host | smart-d31efc4b-b9ee-4935-9987-4ba8c7fb0a01 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2634386701 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.xbar_random.2634386701 |
| Directory | /workspace/14.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/14.xbar_random_large_delays.3464834577 |
| Short name | T2793 |
| Test name | |
| Test status | |
| Simulation time | 70703907626 ps |
| CPU time | 685.79 seconds |
| Started | Aug 12 06:48:05 PM PDT 24 |
| Finished | Aug 12 06:59:31 PM PDT 24 |
| Peak memory | 575704 kb |
| Host | smart-4164c886-80ef-4c48-a449-c9e1b1146bb5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3464834577 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.xbar_random_large_delays.3464834577 |
| Directory | /workspace/14.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/14.xbar_random_slow_rsp.2573030658 |
| Short name | T2869 |
| Test name | |
| Test status | |
| Simulation time | 17895328071 ps |
| CPU time | 304.44 seconds |
| Started | Aug 12 06:48:08 PM PDT 24 |
| Finished | Aug 12 06:53:13 PM PDT 24 |
| Peak memory | 575628 kb |
| Host | smart-f15d51f0-3b21-4acd-a58e-85751f912e78 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2573030658 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.xbar_random_slow_rsp.2573030658 |
| Directory | /workspace/14.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/14.xbar_random_zero_delays.427693642 |
| Short name | T2756 |
| Test name | |
| Test status | |
| Simulation time | 395758977 ps |
| CPU time | 33.29 seconds |
| Started | Aug 12 06:48:05 PM PDT 24 |
| Finished | Aug 12 06:48:38 PM PDT 24 |
| Peak memory | 575504 kb |
| Host | smart-48a15485-cfb2-4bb7-b8a8-fad26768c872 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=427693642 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.xbar_random_zero_dela ys.427693642 |
| Directory | /workspace/14.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/14.xbar_same_source.1497619583 |
| Short name | T1987 |
| Test name | |
| Test status | |
| Simulation time | 256537680 ps |
| CPU time | 10.75 seconds |
| Started | Aug 12 06:47:58 PM PDT 24 |
| Finished | Aug 12 06:48:09 PM PDT 24 |
| Peak memory | 573600 kb |
| Host | smart-dd39f642-0467-43a0-ab9a-c875c5e011b1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1497619583 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.xbar_same_source.1497619583 |
| Directory | /workspace/14.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/14.xbar_smoke.3500430050 |
| Short name | T2324 |
| Test name | |
| Test status | |
| Simulation time | 217043338 ps |
| CPU time | 9.32 seconds |
| Started | Aug 12 06:48:12 PM PDT 24 |
| Finished | Aug 12 06:48:22 PM PDT 24 |
| Peak memory | 574236 kb |
| Host | smart-c4380ab0-7e3b-4537-9cb8-164676427c03 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3500430050 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.xbar_smoke.3500430050 |
| Directory | /workspace/14.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/14.xbar_smoke_large_delays.3361196691 |
| Short name | T2934 |
| Test name | |
| Test status | |
| Simulation time | 8430347861 ps |
| CPU time | 83.42 seconds |
| Started | Aug 12 06:48:05 PM PDT 24 |
| Finished | Aug 12 06:49:28 PM PDT 24 |
| Peak memory | 573668 kb |
| Host | smart-ab974bc5-a8fa-46cf-8843-ce4ad6943a34 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3361196691 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.xbar_smoke_large_delays.3361196691 |
| Directory | /workspace/14.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/14.xbar_smoke_slow_rsp.2055882671 |
| Short name | T2245 |
| Test name | |
| Test status | |
| Simulation time | 5529892954 ps |
| CPU time | 89.59 seconds |
| Started | Aug 12 06:48:07 PM PDT 24 |
| Finished | Aug 12 06:49:36 PM PDT 24 |
| Peak memory | 573716 kb |
| Host | smart-39ddf5c5-e93c-4e4e-a172-be7522a672bc |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2055882671 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.xbar_smoke_slow_rsp.2055882671 |
| Directory | /workspace/14.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/14.xbar_smoke_zero_delays.3918512590 |
| Short name | T2403 |
| Test name | |
| Test status | |
| Simulation time | 55933560 ps |
| CPU time | 6.77 seconds |
| Started | Aug 12 06:47:59 PM PDT 24 |
| Finished | Aug 12 06:48:06 PM PDT 24 |
| Peak memory | 574264 kb |
| Host | smart-5ae0e3f2-3e81-4cea-b022-7aa1eb60096d |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3918512590 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.xbar_smoke_zero_delay s.3918512590 |
| Directory | /workspace/14.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/14.xbar_stress_all.1269666728 |
| Short name | T466 |
| Test name | |
| Test status | |
| Simulation time | 8455360030 ps |
| CPU time | 278.59 seconds |
| Started | Aug 12 06:48:01 PM PDT 24 |
| Finished | Aug 12 06:52:40 PM PDT 24 |
| Peak memory | 576576 kb |
| Host | smart-5b6a628d-3ded-4060-857d-c8c11b59db21 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1269666728 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.xbar_stress_all.1269666728 |
| Directory | /workspace/14.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/14.xbar_stress_all_with_error.814886545 |
| Short name | T2055 |
| Test name | |
| Test status | |
| Simulation time | 2088866262 ps |
| CPU time | 124.1 seconds |
| Started | Aug 12 06:48:07 PM PDT 24 |
| Finished | Aug 12 06:50:11 PM PDT 24 |
| Peak memory | 575900 kb |
| Host | smart-7ff64868-4bee-43bc-8d6f-65e94ae77107 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=814886545 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.xbar_stress_all_with_error.814886545 |
| Directory | /workspace/14.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/14.xbar_stress_all_with_rand_reset.2322551766 |
| Short name | T2388 |
| Test name | |
| Test status | |
| Simulation time | 46082112 ps |
| CPU time | 8.99 seconds |
| Started | Aug 12 06:48:08 PM PDT 24 |
| Finished | Aug 12 06:48:17 PM PDT 24 |
| Peak memory | 574456 kb |
| Host | smart-74f72d26-537e-4156-a287-72e3e2058acc |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2322551766 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.xbar_stress_all _with_rand_reset.2322551766 |
| Directory | /workspace/14.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/14.xbar_stress_all_with_reset_error.4136472080 |
| Short name | T1938 |
| Test name | |
| Test status | |
| Simulation time | 3417935993 ps |
| CPU time | 351.16 seconds |
| Started | Aug 12 06:48:04 PM PDT 24 |
| Finished | Aug 12 06:53:55 PM PDT 24 |
| Peak memory | 576624 kb |
| Host | smart-9ca01c3c-dc10-4238-9e6a-aaa4c9cf84ac |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4136472080 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.xbar_stress_al l_with_reset_error.4136472080 |
| Directory | /workspace/14.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/14.xbar_unmapped_addr.4142524382 |
| Short name | T2731 |
| Test name | |
| Test status | |
| Simulation time | 121700767 ps |
| CPU time | 15.08 seconds |
| Started | Aug 12 06:47:59 PM PDT 24 |
| Finished | Aug 12 06:48:15 PM PDT 24 |
| Peak memory | 575740 kb |
| Host | smart-a9dbed15-caf0-4b92-83e5-db0807cf2189 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4142524382 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.xbar_unmapped_addr.4142524382 |
| Directory | /workspace/14.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/15.chip_csr_mem_rw_with_rand_reset.3763949162 |
| Short name | T2878 |
| Test name | |
| Test status | |
| Simulation time | 6957279510 ps |
| CPU time | 449.78 seconds |
| Started | Aug 12 06:48:15 PM PDT 24 |
| Finished | Aug 12 06:55:45 PM PDT 24 |
| Peak memory | 638756 kb |
| Host | smart-f2ee209c-d513-4409-9e2e-ebe072cb82a3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3763949162 -assert nopostproc + UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top .vdb -cm_log /dev/null -cm_name 15.chip_csr_mem_rw_with_rand_reset.3763949162 |
| Directory | /workspace/15.chip_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/15.chip_csr_rw.1701592014 |
| Short name | T2382 |
| Test name | |
| Test status | |
| Simulation time | 4129787965 ps |
| CPU time | 301.4 seconds |
| Started | Aug 12 06:48:16 PM PDT 24 |
| Finished | Aug 12 06:53:18 PM PDT 24 |
| Peak memory | 598204 kb |
| Host | smart-4e1d0ac9-94a8-49d9-9482-525ebbd0668b |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1701592014 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.chip_csr_rw.1701592014 |
| Directory | /workspace/15.chip_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/15.chip_same_csr_outstanding.3534091349 |
| Short name | T404 |
| Test name | |
| Test status | |
| Simulation time | 15504188145 ps |
| CPU time | 1660.83 seconds |
| Started | Aug 12 06:48:05 PM PDT 24 |
| Finished | Aug 12 07:15:46 PM PDT 24 |
| Peak memory | 592684 kb |
| Host | smart-e8ab2ba0-32b6-4f5a-abf0-eca7544f8f6c |
| User | root |
| Command | /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +run_same_csr_outstanding +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3534091349 -assert nopostproc +UVM_TE STNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb - cm_log /dev/null -cm_name 15.chip_same_csr_outstanding.3534091349 |
| Directory | /workspace/15.chip_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/15.chip_tl_errors.4101688651 |
| Short name | T776 |
| Test name | |
| Test status | |
| Simulation time | 4080398652 ps |
| CPU time | 216.03 seconds |
| Started | Aug 12 06:48:13 PM PDT 24 |
| Finished | Aug 12 06:51:50 PM PDT 24 |
| Peak memory | 603212 kb |
| Host | smart-47b68f2c-51ca-4bf0-ba32-a9518f9e684a |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4101688651 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.chip_tl_errors.4101688651 |
| Directory | /workspace/15.chip_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/15.xbar_access_same_device.4261929590 |
| Short name | T2648 |
| Test name | |
| Test status | |
| Simulation time | 2511806612 ps |
| CPU time | 97.99 seconds |
| Started | Aug 12 06:48:06 PM PDT 24 |
| Finished | Aug 12 06:49:44 PM PDT 24 |
| Peak memory | 575792 kb |
| Host | smart-ef929272-0d0c-4637-8bfd-c22ef4c84047 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4261929590 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.xbar_access_same_device .4261929590 |
| Directory | /workspace/15.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/15.xbar_access_same_device_slow_rsp.4053592766 |
| Short name | T1902 |
| Test name | |
| Test status | |
| Simulation time | 112357388213 ps |
| CPU time | 1954.12 seconds |
| Started | Aug 12 06:48:13 PM PDT 24 |
| Finished | Aug 12 07:20:48 PM PDT 24 |
| Peak memory | 575736 kb |
| Host | smart-5b2b1597-8390-4413-9fda-c5b1aafe2071 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4053592766 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.xbar_access_same_ device_slow_rsp.4053592766 |
| Directory | /workspace/15.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/15.xbar_error_and_unmapped_addr.661090095 |
| Short name | T1528 |
| Test name | |
| Test status | |
| Simulation time | 272827804 ps |
| CPU time | 32.5 seconds |
| Started | Aug 12 06:48:17 PM PDT 24 |
| Finished | Aug 12 06:48:50 PM PDT 24 |
| Peak memory | 575672 kb |
| Host | smart-a29d4b45-e9b9-4002-8033-164c6a004880 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=661090095 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.xbar_error_and_unmapped_addr .661090095 |
| Directory | /workspace/15.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/15.xbar_error_random.3661807337 |
| Short name | T1451 |
| Test name | |
| Test status | |
| Simulation time | 108381753 ps |
| CPU time | 7.23 seconds |
| Started | Aug 12 06:48:05 PM PDT 24 |
| Finished | Aug 12 06:48:13 PM PDT 24 |
| Peak memory | 573584 kb |
| Host | smart-7bcb0346-98f5-4ff9-b49f-0eb5073426f2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3661807337 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.xbar_error_random.3661807337 |
| Directory | /workspace/15.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/15.xbar_random.1825108192 |
| Short name | T2218 |
| Test name | |
| Test status | |
| Simulation time | 2297401772 ps |
| CPU time | 80.21 seconds |
| Started | Aug 12 06:48:14 PM PDT 24 |
| Finished | Aug 12 06:49:34 PM PDT 24 |
| Peak memory | 575672 kb |
| Host | smart-fbe42300-6b7f-44c9-ba7e-bbb71638b6cd |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1825108192 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.xbar_random.1825108192 |
| Directory | /workspace/15.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/15.xbar_random_large_delays.2747651527 |
| Short name | T2550 |
| Test name | |
| Test status | |
| Simulation time | 34966755111 ps |
| CPU time | 349.82 seconds |
| Started | Aug 12 06:48:04 PM PDT 24 |
| Finished | Aug 12 06:53:54 PM PDT 24 |
| Peak memory | 575780 kb |
| Host | smart-628829e6-5a19-42f5-81c9-348970853cf2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2747651527 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.xbar_random_large_delays.2747651527 |
| Directory | /workspace/15.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/15.xbar_random_slow_rsp.277594535 |
| Short name | T2033 |
| Test name | |
| Test status | |
| Simulation time | 37541975691 ps |
| CPU time | 647.58 seconds |
| Started | Aug 12 06:48:08 PM PDT 24 |
| Finished | Aug 12 06:58:56 PM PDT 24 |
| Peak memory | 575716 kb |
| Host | smart-c8c38df2-4709-4c90-b533-0cf8163c70ee |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=277594535 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.xbar_random_slow_rsp.277594535 |
| Directory | /workspace/15.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/15.xbar_random_zero_delays.876615485 |
| Short name | T1973 |
| Test name | |
| Test status | |
| Simulation time | 415655988 ps |
| CPU time | 36.91 seconds |
| Started | Aug 12 06:48:05 PM PDT 24 |
| Finished | Aug 12 06:48:42 PM PDT 24 |
| Peak memory | 575720 kb |
| Host | smart-263b9428-736d-48d7-9c4f-9785d6117696 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=876615485 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.xbar_random_zero_dela ys.876615485 |
| Directory | /workspace/15.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/15.xbar_same_source.2897124914 |
| Short name | T1653 |
| Test name | |
| Test status | |
| Simulation time | 2521183757 ps |
| CPU time | 74.56 seconds |
| Started | Aug 12 06:48:05 PM PDT 24 |
| Finished | Aug 12 06:49:20 PM PDT 24 |
| Peak memory | 575732 kb |
| Host | smart-5745e154-22e2-4600-be22-865c17ea0518 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2897124914 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.xbar_same_source.2897124914 |
| Directory | /workspace/15.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/15.xbar_smoke.1772590072 |
| Short name | T1563 |
| Test name | |
| Test status | |
| Simulation time | 222370578 ps |
| CPU time | 9.11 seconds |
| Started | Aug 12 06:48:06 PM PDT 24 |
| Finished | Aug 12 06:48:16 PM PDT 24 |
| Peak memory | 573524 kb |
| Host | smart-b6867949-c076-45de-b71c-5ee36b6dc1c0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1772590072 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.xbar_smoke.1772590072 |
| Directory | /workspace/15.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/15.xbar_smoke_large_delays.974874919 |
| Short name | T2523 |
| Test name | |
| Test status | |
| Simulation time | 6396219157 ps |
| CPU time | 69.34 seconds |
| Started | Aug 12 06:48:08 PM PDT 24 |
| Finished | Aug 12 06:49:18 PM PDT 24 |
| Peak memory | 573680 kb |
| Host | smart-5e223e82-b7fb-43e4-aef1-1dee1bc3b7fe |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=974874919 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.xbar_smoke_large_delays.974874919 |
| Directory | /workspace/15.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/15.xbar_smoke_slow_rsp.735832552 |
| Short name | T1671 |
| Test name | |
| Test status | |
| Simulation time | 5069005648 ps |
| CPU time | 84.66 seconds |
| Started | Aug 12 06:48:06 PM PDT 24 |
| Finished | Aug 12 06:49:31 PM PDT 24 |
| Peak memory | 573688 kb |
| Host | smart-8a82963b-0a1d-43c1-9ee1-4e04d7125791 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=735832552 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.xbar_smoke_slow_rsp.735832552 |
| Directory | /workspace/15.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/15.xbar_smoke_zero_delays.2989642134 |
| Short name | T1814 |
| Test name | |
| Test status | |
| Simulation time | 49936499 ps |
| CPU time | 6.19 seconds |
| Started | Aug 12 06:48:05 PM PDT 24 |
| Finished | Aug 12 06:48:11 PM PDT 24 |
| Peak memory | 573600 kb |
| Host | smart-5efce16f-8f6f-4bd9-8427-6fcbb7ba1888 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2989642134 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.xbar_smoke_zero_delay s.2989642134 |
| Directory | /workspace/15.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/15.xbar_stress_all.1296112910 |
| Short name | T498 |
| Test name | |
| Test status | |
| Simulation time | 8332337966 ps |
| CPU time | 318 seconds |
| Started | Aug 12 06:48:17 PM PDT 24 |
| Finished | Aug 12 06:53:35 PM PDT 24 |
| Peak memory | 575788 kb |
| Host | smart-3537519c-a843-4d5c-aca9-b9921fc08e1b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1296112910 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.xbar_stress_all.1296112910 |
| Directory | /workspace/15.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/15.xbar_stress_all_with_error.1043872397 |
| Short name | T2368 |
| Test name | |
| Test status | |
| Simulation time | 2732522414 ps |
| CPU time | 87.46 seconds |
| Started | Aug 12 06:48:17 PM PDT 24 |
| Finished | Aug 12 06:49:45 PM PDT 24 |
| Peak memory | 575612 kb |
| Host | smart-bf998852-845f-4160-9c75-9c2afb42c091 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1043872397 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.xbar_stress_all_with_error.1043872397 |
| Directory | /workspace/15.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/15.xbar_stress_all_with_rand_reset.2423175254 |
| Short name | T507 |
| Test name | |
| Test status | |
| Simulation time | 7151308094 ps |
| CPU time | 455.56 seconds |
| Started | Aug 12 06:48:08 PM PDT 24 |
| Finished | Aug 12 06:55:43 PM PDT 24 |
| Peak memory | 575752 kb |
| Host | smart-3c12bac5-d583-4a4f-a15f-2ac7eff8e429 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2423175254 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.xbar_stress_all _with_rand_reset.2423175254 |
| Directory | /workspace/15.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/15.xbar_stress_all_with_reset_error.2285197839 |
| Short name | T947 |
| Test name | |
| Test status | |
| Simulation time | 10668232983 ps |
| CPU time | 440.48 seconds |
| Started | Aug 12 06:48:17 PM PDT 24 |
| Finished | Aug 12 06:55:37 PM PDT 24 |
| Peak memory | 576580 kb |
| Host | smart-5856e5a1-74e7-4e0e-b190-3b296e757af7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2285197839 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.xbar_stress_al l_with_reset_error.2285197839 |
| Directory | /workspace/15.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/15.xbar_unmapped_addr.3758408857 |
| Short name | T558 |
| Test name | |
| Test status | |
| Simulation time | 531428632 ps |
| CPU time | 23.67 seconds |
| Started | Aug 12 06:48:06 PM PDT 24 |
| Finished | Aug 12 06:48:30 PM PDT 24 |
| Peak memory | 575708 kb |
| Host | smart-fabd773e-22de-4002-a745-256b50ca8a2a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3758408857 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.xbar_unmapped_addr.3758408857 |
| Directory | /workspace/15.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/16.chip_csr_rw.3551676415 |
| Short name | T1741 |
| Test name | |
| Test status | |
| Simulation time | 3727287232 ps |
| CPU time | 289.91 seconds |
| Started | Aug 12 06:48:22 PM PDT 24 |
| Finished | Aug 12 06:53:12 PM PDT 24 |
| Peak memory | 598600 kb |
| Host | smart-c81ae070-5565-48e5-9bb2-2057a7771c1a |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3551676415 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.chip_csr_rw.3551676415 |
| Directory | /workspace/16.chip_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/16.chip_same_csr_outstanding.4239626953 |
| Short name | T1754 |
| Test name | |
| Test status | |
| Simulation time | 14442140327 ps |
| CPU time | 1644.65 seconds |
| Started | Aug 12 06:48:25 PM PDT 24 |
| Finished | Aug 12 07:15:50 PM PDT 24 |
| Peak memory | 593024 kb |
| Host | smart-4879a9e0-ba44-4b75-bafb-d96df473c894 |
| User | root |
| Command | /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +run_same_csr_outstanding +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4239626953 -assert nopostproc +UVM_TE STNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb - cm_log /dev/null -cm_name 16.chip_same_csr_outstanding.4239626953 |
| Directory | /workspace/16.chip_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/16.xbar_access_same_device.1729139276 |
| Short name | T2056 |
| Test name | |
| Test status | |
| Simulation time | 948693101 ps |
| CPU time | 30.69 seconds |
| Started | Aug 12 06:48:18 PM PDT 24 |
| Finished | Aug 12 06:48:48 PM PDT 24 |
| Peak memory | 575548 kb |
| Host | smart-d1976353-ca22-4578-891d-aa4a4f2d4ae2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1729139276 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.xbar_access_same_device .1729139276 |
| Directory | /workspace/16.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/16.xbar_access_same_device_slow_rsp.4110957153 |
| Short name | T937 |
| Test name | |
| Test status | |
| Simulation time | 45445255633 ps |
| CPU time | 714.12 seconds |
| Started | Aug 12 06:48:16 PM PDT 24 |
| Finished | Aug 12 07:00:11 PM PDT 24 |
| Peak memory | 575688 kb |
| Host | smart-7286e50b-3718-458b-af06-0ea4eead12d7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4110957153 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.xbar_access_same_ device_slow_rsp.4110957153 |
| Directory | /workspace/16.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/16.xbar_error_and_unmapped_addr.572660920 |
| Short name | T1735 |
| Test name | |
| Test status | |
| Simulation time | 1005541000 ps |
| CPU time | 43.19 seconds |
| Started | Aug 12 06:48:23 PM PDT 24 |
| Finished | Aug 12 06:49:06 PM PDT 24 |
| Peak memory | 575708 kb |
| Host | smart-9842dd73-1c9f-485d-b408-9241c7657afe |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=572660920 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.xbar_error_and_unmapped_addr .572660920 |
| Directory | /workspace/16.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/16.xbar_error_random.3974083566 |
| Short name | T1723 |
| Test name | |
| Test status | |
| Simulation time | 614360133 ps |
| CPU time | 43.88 seconds |
| Started | Aug 12 06:48:21 PM PDT 24 |
| Finished | Aug 12 06:49:05 PM PDT 24 |
| Peak memory | 575752 kb |
| Host | smart-ca740fc9-e3a6-4914-9704-20c2d36165d8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3974083566 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.xbar_error_random.3974083566 |
| Directory | /workspace/16.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/16.xbar_random.533438274 |
| Short name | T693 |
| Test name | |
| Test status | |
| Simulation time | 301272067 ps |
| CPU time | 13.21 seconds |
| Started | Aug 12 06:48:25 PM PDT 24 |
| Finished | Aug 12 06:48:39 PM PDT 24 |
| Peak memory | 575544 kb |
| Host | smart-7bcf5339-b5c9-4627-9b41-cb918515178a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=533438274 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.xbar_random.533438274 |
| Directory | /workspace/16.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/16.xbar_random_large_delays.2445141925 |
| Short name | T2450 |
| Test name | |
| Test status | |
| Simulation time | 70248481558 ps |
| CPU time | 731.92 seconds |
| Started | Aug 12 06:48:16 PM PDT 24 |
| Finished | Aug 12 07:00:28 PM PDT 24 |
| Peak memory | 575712 kb |
| Host | smart-b5383726-37ac-4902-b60f-f2d6d9c51844 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2445141925 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.xbar_random_large_delays.2445141925 |
| Directory | /workspace/16.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/16.xbar_random_slow_rsp.1987460073 |
| Short name | T571 |
| Test name | |
| Test status | |
| Simulation time | 17406884029 ps |
| CPU time | 292.16 seconds |
| Started | Aug 12 06:48:17 PM PDT 24 |
| Finished | Aug 12 06:53:10 PM PDT 24 |
| Peak memory | 576428 kb |
| Host | smart-297161d4-4c85-4d6a-8571-fb625b61e662 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1987460073 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.xbar_random_slow_rsp.1987460073 |
| Directory | /workspace/16.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/16.xbar_random_zero_delays.2831064828 |
| Short name | T2008 |
| Test name | |
| Test status | |
| Simulation time | 343702395 ps |
| CPU time | 33.78 seconds |
| Started | Aug 12 06:48:15 PM PDT 24 |
| Finished | Aug 12 06:48:49 PM PDT 24 |
| Peak memory | 575656 kb |
| Host | smart-bdfeb13e-a357-45ef-ac1f-62d41df9a9a8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2831064828 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.xbar_random_zero_del ays.2831064828 |
| Directory | /workspace/16.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/16.xbar_same_source.1194908816 |
| Short name | T1904 |
| Test name | |
| Test status | |
| Simulation time | 2258632784 ps |
| CPU time | 70.73 seconds |
| Started | Aug 12 06:48:24 PM PDT 24 |
| Finished | Aug 12 06:49:35 PM PDT 24 |
| Peak memory | 575712 kb |
| Host | smart-52b9f13f-4df8-4d96-aa34-dcb77e3189de |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1194908816 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.xbar_same_source.1194908816 |
| Directory | /workspace/16.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/16.xbar_smoke.1014047440 |
| Short name | T1558 |
| Test name | |
| Test status | |
| Simulation time | 45473264 ps |
| CPU time | 6.34 seconds |
| Started | Aug 12 06:48:15 PM PDT 24 |
| Finished | Aug 12 06:48:21 PM PDT 24 |
| Peak memory | 573544 kb |
| Host | smart-208ad0bb-daaa-484f-944a-d6944a11c167 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1014047440 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.xbar_smoke.1014047440 |
| Directory | /workspace/16.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/16.xbar_smoke_large_delays.1312401721 |
| Short name | T2137 |
| Test name | |
| Test status | |
| Simulation time | 9274732333 ps |
| CPU time | 97.65 seconds |
| Started | Aug 12 06:48:17 PM PDT 24 |
| Finished | Aug 12 06:49:55 PM PDT 24 |
| Peak memory | 573644 kb |
| Host | smart-3e08d713-94b8-4532-b779-43d976af1886 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1312401721 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.xbar_smoke_large_delays.1312401721 |
| Directory | /workspace/16.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/16.xbar_smoke_slow_rsp.1448564466 |
| Short name | T2613 |
| Test name | |
| Test status | |
| Simulation time | 5762220859 ps |
| CPU time | 96.73 seconds |
| Started | Aug 12 06:48:17 PM PDT 24 |
| Finished | Aug 12 06:49:54 PM PDT 24 |
| Peak memory | 573716 kb |
| Host | smart-a6fc6744-58c9-42e2-97c9-c47e835e60b6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1448564466 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.xbar_smoke_slow_rsp.1448564466 |
| Directory | /workspace/16.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/16.xbar_smoke_zero_delays.3104861789 |
| Short name | T2703 |
| Test name | |
| Test status | |
| Simulation time | 49081414 ps |
| CPU time | 6.95 seconds |
| Started | Aug 12 06:48:18 PM PDT 24 |
| Finished | Aug 12 06:48:25 PM PDT 24 |
| Peak memory | 573528 kb |
| Host | smart-969dadfc-d3da-49eb-9641-457938a3b5db |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3104861789 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.xbar_smoke_zero_delay s.3104861789 |
| Directory | /workspace/16.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/16.xbar_stress_all.4128238949 |
| Short name | T674 |
| Test name | |
| Test status | |
| Simulation time | 271239969 ps |
| CPU time | 21.51 seconds |
| Started | Aug 12 06:48:21 PM PDT 24 |
| Finished | Aug 12 06:48:43 PM PDT 24 |
| Peak memory | 575692 kb |
| Host | smart-5a686813-6314-4828-b33f-724a1c2cd182 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4128238949 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.xbar_stress_all.4128238949 |
| Directory | /workspace/16.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/16.xbar_stress_all_with_rand_reset.3379285476 |
| Short name | T2495 |
| Test name | |
| Test status | |
| Simulation time | 8227048637 ps |
| CPU time | 896.41 seconds |
| Started | Aug 12 06:48:21 PM PDT 24 |
| Finished | Aug 12 07:03:18 PM PDT 24 |
| Peak memory | 575756 kb |
| Host | smart-34e3c92f-c563-4577-94b6-b081868be7c1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3379285476 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.xbar_stress_all _with_rand_reset.3379285476 |
| Directory | /workspace/16.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/16.xbar_stress_all_with_reset_error.3352161096 |
| Short name | T900 |
| Test name | |
| Test status | |
| Simulation time | 5290700031 ps |
| CPU time | 321.64 seconds |
| Started | Aug 12 06:48:27 PM PDT 24 |
| Finished | Aug 12 06:53:49 PM PDT 24 |
| Peak memory | 576556 kb |
| Host | smart-2497ec4d-8d2e-4d1c-8da0-1a2f46862b9f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3352161096 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.xbar_stress_al l_with_reset_error.3352161096 |
| Directory | /workspace/16.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/16.xbar_unmapped_addr.1309301425 |
| Short name | T2344 |
| Test name | |
| Test status | |
| Simulation time | 186068597 ps |
| CPU time | 20.53 seconds |
| Started | Aug 12 06:48:25 PM PDT 24 |
| Finished | Aug 12 06:48:45 PM PDT 24 |
| Peak memory | 575608 kb |
| Host | smart-0ce34b81-29bc-4886-8ac5-d470832e0e1d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1309301425 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.xbar_unmapped_addr.1309301425 |
| Directory | /workspace/16.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/17.chip_csr_mem_rw_with_rand_reset.932969778 |
| Short name | T2154 |
| Test name | |
| Test status | |
| Simulation time | 6617467267 ps |
| CPU time | 439.51 seconds |
| Started | Aug 12 06:48:42 PM PDT 24 |
| Finished | Aug 12 06:56:01 PM PDT 24 |
| Peak memory | 638804 kb |
| Host | smart-bce09562-13d6-4c8b-b3c4-2ea3e43759b8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=932969778 -assert nopostproc +U VM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top. vdb -cm_log /dev/null -cm_name 17.chip_csr_mem_rw_with_rand_reset.932969778 |
| Directory | /workspace/17.chip_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/17.chip_csr_rw.2718187360 |
| Short name | T2673 |
| Test name | |
| Test status | |
| Simulation time | 4450869020 ps |
| CPU time | 394.78 seconds |
| Started | Aug 12 06:48:38 PM PDT 24 |
| Finished | Aug 12 06:55:13 PM PDT 24 |
| Peak memory | 598896 kb |
| Host | smart-52079281-f7f1-4fef-b70a-6a192a00dc49 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2718187360 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.chip_csr_rw.2718187360 |
| Directory | /workspace/17.chip_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/17.chip_same_csr_outstanding.1935489613 |
| Short name | T1911 |
| Test name | |
| Test status | |
| Simulation time | 32101376009 ps |
| CPU time | 4268.14 seconds |
| Started | Aug 12 06:48:27 PM PDT 24 |
| Finished | Aug 12 07:59:36 PM PDT 24 |
| Peak memory | 593428 kb |
| Host | smart-6674e003-4584-44e5-bc10-c6dcc19257a1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +run_same_csr_outstanding +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1935489613 -assert nopostproc +UVM_TE STNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb - cm_log /dev/null -cm_name 17.chip_same_csr_outstanding.1935489613 |
| Directory | /workspace/17.chip_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/17.chip_tl_errors.1143831878 |
| Short name | T567 |
| Test name | |
| Test status | |
| Simulation time | 2796884343 ps |
| CPU time | 141.32 seconds |
| Started | Aug 12 06:48:21 PM PDT 24 |
| Finished | Aug 12 06:50:42 PM PDT 24 |
| Peak memory | 603244 kb |
| Host | smart-e85d6a8d-e818-41ec-bb8f-b81f7b93c281 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1143831878 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.chip_tl_errors.1143831878 |
| Directory | /workspace/17.chip_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/17.xbar_access_same_device.1799754698 |
| Short name | T1914 |
| Test name | |
| Test status | |
| Simulation time | 2233454557 ps |
| CPU time | 101.13 seconds |
| Started | Aug 12 06:48:28 PM PDT 24 |
| Finished | Aug 12 06:50:10 PM PDT 24 |
| Peak memory | 575600 kb |
| Host | smart-266a0dbd-d940-4803-b448-4baf62d8e106 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1799754698 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.xbar_access_same_device .1799754698 |
| Directory | /workspace/17.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/17.xbar_access_same_device_slow_rsp.1545948447 |
| Short name | T928 |
| Test name | |
| Test status | |
| Simulation time | 17857298535 ps |
| CPU time | 291.51 seconds |
| Started | Aug 12 06:48:29 PM PDT 24 |
| Finished | Aug 12 06:53:21 PM PDT 24 |
| Peak memory | 575784 kb |
| Host | smart-50e90c3a-3a33-4f69-bbaf-7f9e89fb99d7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1545948447 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.xbar_access_same_ device_slow_rsp.1545948447 |
| Directory | /workspace/17.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/17.xbar_error_and_unmapped_addr.3298831913 |
| Short name | T2462 |
| Test name | |
| Test status | |
| Simulation time | 1044506165 ps |
| CPU time | 39.87 seconds |
| Started | Aug 12 06:48:31 PM PDT 24 |
| Finished | Aug 12 06:49:11 PM PDT 24 |
| Peak memory | 575728 kb |
| Host | smart-9875a7e5-d7e6-48be-88bc-136d5f415cc2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3298831913 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.xbar_error_and_unmapped_add r.3298831913 |
| Directory | /workspace/17.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/17.xbar_error_random.2001974201 |
| Short name | T2028 |
| Test name | |
| Test status | |
| Simulation time | 963108111 ps |
| CPU time | 31.03 seconds |
| Started | Aug 12 06:48:50 PM PDT 24 |
| Finished | Aug 12 06:49:22 PM PDT 24 |
| Peak memory | 575780 kb |
| Host | smart-14a2ef2b-cb23-43fb-954d-d9620e068adc |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2001974201 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.xbar_error_random.2001974201 |
| Directory | /workspace/17.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/17.xbar_random.1866518130 |
| Short name | T2794 |
| Test name | |
| Test status | |
| Simulation time | 131411124 ps |
| CPU time | 8.67 seconds |
| Started | Aug 12 06:48:28 PM PDT 24 |
| Finished | Aug 12 06:48:36 PM PDT 24 |
| Peak memory | 573556 kb |
| Host | smart-1d719b2e-d515-43c8-ae66-b84190c8dd8b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1866518130 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.xbar_random.1866518130 |
| Directory | /workspace/17.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/17.xbar_random_large_delays.3455777068 |
| Short name | T2239 |
| Test name | |
| Test status | |
| Simulation time | 63419571739 ps |
| CPU time | 613.32 seconds |
| Started | Aug 12 06:48:29 PM PDT 24 |
| Finished | Aug 12 06:58:43 PM PDT 24 |
| Peak memory | 575728 kb |
| Host | smart-6b9513ea-4c60-43fb-b800-7bbe0fc6f86e |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3455777068 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.xbar_random_large_delays.3455777068 |
| Directory | /workspace/17.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/17.xbar_random_slow_rsp.2471672839 |
| Short name | T2771 |
| Test name | |
| Test status | |
| Simulation time | 26072196718 ps |
| CPU time | 450.03 seconds |
| Started | Aug 12 06:48:29 PM PDT 24 |
| Finished | Aug 12 06:55:59 PM PDT 24 |
| Peak memory | 575736 kb |
| Host | smart-8d3811b5-3d82-4b08-9153-68fbfc3aa5fc |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2471672839 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.xbar_random_slow_rsp.2471672839 |
| Directory | /workspace/17.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/17.xbar_random_zero_delays.457798593 |
| Short name | T2667 |
| Test name | |
| Test status | |
| Simulation time | 143253999 ps |
| CPU time | 12.88 seconds |
| Started | Aug 12 06:48:30 PM PDT 24 |
| Finished | Aug 12 06:48:43 PM PDT 24 |
| Peak memory | 575672 kb |
| Host | smart-d3506298-ee83-4b31-bf7d-6b17fc9eeedb |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=457798593 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.xbar_random_zero_dela ys.457798593 |
| Directory | /workspace/17.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/17.xbar_same_source.211016938 |
| Short name | T660 |
| Test name | |
| Test status | |
| Simulation time | 560514091 ps |
| CPU time | 34.35 seconds |
| Started | Aug 12 06:48:29 PM PDT 24 |
| Finished | Aug 12 06:49:04 PM PDT 24 |
| Peak memory | 575652 kb |
| Host | smart-0241ce4d-cb4a-4c99-92dc-8bb26112aa09 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=211016938 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.xbar_same_source.211016938 |
| Directory | /workspace/17.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/17.xbar_smoke.1378967489 |
| Short name | T2225 |
| Test name | |
| Test status | |
| Simulation time | 48187342 ps |
| CPU time | 6.54 seconds |
| Started | Aug 12 06:48:30 PM PDT 24 |
| Finished | Aug 12 06:48:36 PM PDT 24 |
| Peak memory | 573564 kb |
| Host | smart-01153600-ea36-4180-a080-9738bf685af5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1378967489 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.xbar_smoke.1378967489 |
| Directory | /workspace/17.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/17.xbar_smoke_large_delays.2365602737 |
| Short name | T2701 |
| Test name | |
| Test status | |
| Simulation time | 7658992622 ps |
| CPU time | 82.44 seconds |
| Started | Aug 12 06:48:28 PM PDT 24 |
| Finished | Aug 12 06:49:51 PM PDT 24 |
| Peak memory | 574340 kb |
| Host | smart-df1ce614-ce0c-46ce-a053-b437d3e3f7a8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2365602737 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.xbar_smoke_large_delays.2365602737 |
| Directory | /workspace/17.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/17.xbar_smoke_slow_rsp.2090867401 |
| Short name | T2249 |
| Test name | |
| Test status | |
| Simulation time | 5979763310 ps |
| CPU time | 98.9 seconds |
| Started | Aug 12 06:48:29 PM PDT 24 |
| Finished | Aug 12 06:50:09 PM PDT 24 |
| Peak memory | 573596 kb |
| Host | smart-f206de17-97d7-47c3-b320-419272ffd9b6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2090867401 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.xbar_smoke_slow_rsp.2090867401 |
| Directory | /workspace/17.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/17.xbar_smoke_zero_delays.2589321386 |
| Short name | T2494 |
| Test name | |
| Test status | |
| Simulation time | 42852631 ps |
| CPU time | 5.65 seconds |
| Started | Aug 12 06:48:29 PM PDT 24 |
| Finished | Aug 12 06:48:35 PM PDT 24 |
| Peak memory | 574292 kb |
| Host | smart-8c1791b8-b436-49e8-9098-42f08a79f010 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2589321386 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.xbar_smoke_zero_delay s.2589321386 |
| Directory | /workspace/17.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/17.xbar_stress_all.4224606833 |
| Short name | T722 |
| Test name | |
| Test status | |
| Simulation time | 3154233123 ps |
| CPU time | 254.24 seconds |
| Started | Aug 12 06:48:31 PM PDT 24 |
| Finished | Aug 12 06:52:46 PM PDT 24 |
| Peak memory | 576720 kb |
| Host | smart-22019a49-11d9-4923-ad1f-4f5c7ab4ac92 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4224606833 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.xbar_stress_all.4224606833 |
| Directory | /workspace/17.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/17.xbar_stress_all_with_error.1485990458 |
| Short name | T2206 |
| Test name | |
| Test status | |
| Simulation time | 565298680 ps |
| CPU time | 44.79 seconds |
| Started | Aug 12 06:48:34 PM PDT 24 |
| Finished | Aug 12 06:49:19 PM PDT 24 |
| Peak memory | 575776 kb |
| Host | smart-120f3d71-53f6-43e5-9002-599ddb12c806 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1485990458 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.xbar_stress_all_with_error.1485990458 |
| Directory | /workspace/17.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/17.xbar_stress_all_with_rand_reset.3605941619 |
| Short name | T961 |
| Test name | |
| Test status | |
| Simulation time | 189209325 ps |
| CPU time | 51.02 seconds |
| Started | Aug 12 06:48:33 PM PDT 24 |
| Finished | Aug 12 06:49:24 PM PDT 24 |
| Peak memory | 575716 kb |
| Host | smart-3026eb15-1b4b-401f-a56b-e26d2717e841 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3605941619 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.xbar_stress_all _with_rand_reset.3605941619 |
| Directory | /workspace/17.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/17.xbar_stress_all_with_reset_error.194689036 |
| Short name | T2075 |
| Test name | |
| Test status | |
| Simulation time | 163386124 ps |
| CPU time | 58.95 seconds |
| Started | Aug 12 06:48:29 PM PDT 24 |
| Finished | Aug 12 06:49:28 PM PDT 24 |
| Peak memory | 576248 kb |
| Host | smart-5db50b07-a1b4-453a-95e5-e8f2202d8e70 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=194689036 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.xbar_stress_all _with_reset_error.194689036 |
| Directory | /workspace/17.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/17.xbar_unmapped_addr.3389040729 |
| Short name | T1467 |
| Test name | |
| Test status | |
| Simulation time | 858362739 ps |
| CPU time | 32.83 seconds |
| Started | Aug 12 06:48:34 PM PDT 24 |
| Finished | Aug 12 06:49:07 PM PDT 24 |
| Peak memory | 575752 kb |
| Host | smart-b9f826f4-8f21-4669-9522-f740dfa6a1a2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3389040729 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.xbar_unmapped_addr.3389040729 |
| Directory | /workspace/17.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/18.chip_csr_mem_rw_with_rand_reset.1646379181 |
| Short name | T418 |
| Test name | |
| Test status | |
| Simulation time | 6828350280 ps |
| CPU time | 443.99 seconds |
| Started | Aug 12 06:48:47 PM PDT 24 |
| Finished | Aug 12 06:56:12 PM PDT 24 |
| Peak memory | 639456 kb |
| Host | smart-f351e125-f0fb-4fe9-a474-4f5c6d137bb8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1646379181 -assert nopostproc + UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top .vdb -cm_log /dev/null -cm_name 18.chip_csr_mem_rw_with_rand_reset.1646379181 |
| Directory | /workspace/18.chip_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/18.chip_csr_rw.112856184 |
| Short name | T2875 |
| Test name | |
| Test status | |
| Simulation time | 4874450716 ps |
| CPU time | 312.17 seconds |
| Started | Aug 12 06:48:47 PM PDT 24 |
| Finished | Aug 12 06:53:59 PM PDT 24 |
| Peak memory | 597136 kb |
| Host | smart-1db63644-e9cd-4841-9a7f-d7afdceff35c |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=112856184 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.chip_csr_rw.112856184 |
| Directory | /workspace/18.chip_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/18.chip_same_csr_outstanding.1997713592 |
| Short name | T2851 |
| Test name | |
| Test status | |
| Simulation time | 32136356739 ps |
| CPU time | 3710.17 seconds |
| Started | Aug 12 06:48:38 PM PDT 24 |
| Finished | Aug 12 07:50:29 PM PDT 24 |
| Peak memory | 592980 kb |
| Host | smart-c39f77a6-bff0-4ddf-94ee-fb6e7d331e8e |
| User | root |
| Command | /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +run_same_csr_outstanding +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1997713592 -assert nopostproc +UVM_TE STNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb - cm_log /dev/null -cm_name 18.chip_same_csr_outstanding.1997713592 |
| Directory | /workspace/18.chip_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/18.chip_tl_errors.3312194421 |
| Short name | T570 |
| Test name | |
| Test status | |
| Simulation time | 3027688951 ps |
| CPU time | 141.81 seconds |
| Started | Aug 12 06:48:38 PM PDT 24 |
| Finished | Aug 12 06:51:00 PM PDT 24 |
| Peak memory | 598156 kb |
| Host | smart-5d9dd1de-812e-426a-bc7b-db5caabb3656 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3312194421 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.chip_tl_errors.3312194421 |
| Directory | /workspace/18.chip_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/18.xbar_access_same_device.4085646695 |
| Short name | T2566 |
| Test name | |
| Test status | |
| Simulation time | 824507946 ps |
| CPU time | 29.76 seconds |
| Started | Aug 12 06:48:42 PM PDT 24 |
| Finished | Aug 12 06:49:11 PM PDT 24 |
| Peak memory | 575532 kb |
| Host | smart-1b947e6b-222f-4bbb-b7f9-2be08e3971ef |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4085646695 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.xbar_access_same_device .4085646695 |
| Directory | /workspace/18.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/18.xbar_access_same_device_slow_rsp.2610059610 |
| Short name | T1709 |
| Test name | |
| Test status | |
| Simulation time | 74895556901 ps |
| CPU time | 1292.3 seconds |
| Started | Aug 12 06:48:38 PM PDT 24 |
| Finished | Aug 12 07:10:11 PM PDT 24 |
| Peak memory | 575856 kb |
| Host | smart-d7f18f6c-8183-43e9-a3af-e02b58a8d262 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2610059610 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.xbar_access_same_ device_slow_rsp.2610059610 |
| Directory | /workspace/18.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/18.xbar_error_and_unmapped_addr.203762623 |
| Short name | T2512 |
| Test name | |
| Test status | |
| Simulation time | 817684161 ps |
| CPU time | 32.66 seconds |
| Started | Aug 12 06:48:39 PM PDT 24 |
| Finished | Aug 12 06:49:12 PM PDT 24 |
| Peak memory | 575492 kb |
| Host | smart-d4fe3709-fe23-4671-9aaa-71c1f0c8f9b5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=203762623 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.xbar_error_and_unmapped_addr .203762623 |
| Directory | /workspace/18.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/18.xbar_error_random.4260511491 |
| Short name | T2432 |
| Test name | |
| Test status | |
| Simulation time | 1448131689 ps |
| CPU time | 51.63 seconds |
| Started | Aug 12 06:48:37 PM PDT 24 |
| Finished | Aug 12 06:49:29 PM PDT 24 |
| Peak memory | 575568 kb |
| Host | smart-9e75bc11-b1f4-4028-8d8c-1c503832896f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4260511491 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.xbar_error_random.4260511491 |
| Directory | /workspace/18.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/18.xbar_random.3654300813 |
| Short name | T2718 |
| Test name | |
| Test status | |
| Simulation time | 940473223 ps |
| CPU time | 29.12 seconds |
| Started | Aug 12 06:48:39 PM PDT 24 |
| Finished | Aug 12 06:49:08 PM PDT 24 |
| Peak memory | 575652 kb |
| Host | smart-13515fe7-1920-4584-be68-afc71eda10a2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3654300813 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.xbar_random.3654300813 |
| Directory | /workspace/18.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/18.xbar_random_large_delays.1327483418 |
| Short name | T707 |
| Test name | |
| Test status | |
| Simulation time | 41312915306 ps |
| CPU time | 427.73 seconds |
| Started | Aug 12 06:48:38 PM PDT 24 |
| Finished | Aug 12 06:55:46 PM PDT 24 |
| Peak memory | 575732 kb |
| Host | smart-7cbc1a78-45f0-4876-8cb2-713e71d28a54 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1327483418 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.xbar_random_large_delays.1327483418 |
| Directory | /workspace/18.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/18.xbar_random_slow_rsp.1699004054 |
| Short name | T2565 |
| Test name | |
| Test status | |
| Simulation time | 7866264066 ps |
| CPU time | 123.12 seconds |
| Started | Aug 12 06:48:38 PM PDT 24 |
| Finished | Aug 12 06:50:41 PM PDT 24 |
| Peak memory | 575584 kb |
| Host | smart-3cba004f-6a69-4816-bca1-f1f2e9d3738b |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1699004054 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.xbar_random_slow_rsp.1699004054 |
| Directory | /workspace/18.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/18.xbar_random_zero_delays.3638542904 |
| Short name | T1672 |
| Test name | |
| Test status | |
| Simulation time | 395036367 ps |
| CPU time | 29.71 seconds |
| Started | Aug 12 06:48:38 PM PDT 24 |
| Finished | Aug 12 06:49:08 PM PDT 24 |
| Peak memory | 575564 kb |
| Host | smart-483a6e98-7586-4fcb-8c40-ee9defe09c0b |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3638542904 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.xbar_random_zero_del ays.3638542904 |
| Directory | /workspace/18.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/18.xbar_same_source.3845986767 |
| Short name | T2228 |
| Test name | |
| Test status | |
| Simulation time | 1447174316 ps |
| CPU time | 48.52 seconds |
| Started | Aug 12 06:48:40 PM PDT 24 |
| Finished | Aug 12 06:49:28 PM PDT 24 |
| Peak memory | 575608 kb |
| Host | smart-334862bd-f40c-44fc-b26f-e835fa8198ba |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3845986767 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.xbar_same_source.3845986767 |
| Directory | /workspace/18.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/18.xbar_smoke.1402115369 |
| Short name | T1845 |
| Test name | |
| Test status | |
| Simulation time | 187078352 ps |
| CPU time | 8.63 seconds |
| Started | Aug 12 06:48:42 PM PDT 24 |
| Finished | Aug 12 06:48:51 PM PDT 24 |
| Peak memory | 573580 kb |
| Host | smart-f66f60f6-e372-476e-b351-39caa9e43ef2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1402115369 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.xbar_smoke.1402115369 |
| Directory | /workspace/18.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/18.xbar_smoke_large_delays.2136484092 |
| Short name | T1522 |
| Test name | |
| Test status | |
| Simulation time | 6893656413 ps |
| CPU time | 64.99 seconds |
| Started | Aug 12 06:48:40 PM PDT 24 |
| Finished | Aug 12 06:49:45 PM PDT 24 |
| Peak memory | 573628 kb |
| Host | smart-99eedfa1-f2ea-43e8-b09b-432cb22f9c2a |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2136484092 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.xbar_smoke_large_delays.2136484092 |
| Directory | /workspace/18.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/18.xbar_smoke_slow_rsp.3058083897 |
| Short name | T2792 |
| Test name | |
| Test status | |
| Simulation time | 6198738918 ps |
| CPU time | 92.2 seconds |
| Started | Aug 12 06:48:40 PM PDT 24 |
| Finished | Aug 12 06:50:12 PM PDT 24 |
| Peak memory | 573700 kb |
| Host | smart-9b0e2658-6980-4d6e-8d2e-0485d4484458 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3058083897 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.xbar_smoke_slow_rsp.3058083897 |
| Directory | /workspace/18.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/18.xbar_smoke_zero_delays.126917672 |
| Short name | T1632 |
| Test name | |
| Test status | |
| Simulation time | 35978969 ps |
| CPU time | 5.82 seconds |
| Started | Aug 12 06:48:39 PM PDT 24 |
| Finished | Aug 12 06:48:45 PM PDT 24 |
| Peak memory | 574236 kb |
| Host | smart-e0d1a170-9314-462c-8168-f3a20ea603ef |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=126917672 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.xbar_smoke_zero_delays .126917672 |
| Directory | /workspace/18.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/18.xbar_stress_all.1934573257 |
| Short name | T2276 |
| Test name | |
| Test status | |
| Simulation time | 1992075773 ps |
| CPU time | 184.42 seconds |
| Started | Aug 12 06:48:42 PM PDT 24 |
| Finished | Aug 12 06:51:46 PM PDT 24 |
| Peak memory | 575788 kb |
| Host | smart-d2d2296b-f4a9-4134-81b9-b0a56284b1c2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1934573257 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.xbar_stress_all.1934573257 |
| Directory | /workspace/18.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/18.xbar_stress_all_with_error.3676356750 |
| Short name | T1751 |
| Test name | |
| Test status | |
| Simulation time | 11044887483 ps |
| CPU time | 410.92 seconds |
| Started | Aug 12 06:48:39 PM PDT 24 |
| Finished | Aug 12 06:55:30 PM PDT 24 |
| Peak memory | 576556 kb |
| Host | smart-ebf291ae-9d60-464c-9bb0-1029624dab77 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3676356750 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.xbar_stress_all_with_error.3676356750 |
| Directory | /workspace/18.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/18.xbar_stress_all_with_rand_reset.2554722877 |
| Short name | T2603 |
| Test name | |
| Test status | |
| Simulation time | 441534761 ps |
| CPU time | 152.74 seconds |
| Started | Aug 12 06:48:38 PM PDT 24 |
| Finished | Aug 12 06:51:11 PM PDT 24 |
| Peak memory | 575688 kb |
| Host | smart-f76f876d-f39c-42fd-8c5a-496dcfa3db0c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2554722877 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.xbar_stress_all _with_rand_reset.2554722877 |
| Directory | /workspace/18.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/18.xbar_stress_all_with_reset_error.4119621349 |
| Short name | T962 |
| Test name | |
| Test status | |
| Simulation time | 802801619 ps |
| CPU time | 166.4 seconds |
| Started | Aug 12 06:48:38 PM PDT 24 |
| Finished | Aug 12 06:51:24 PM PDT 24 |
| Peak memory | 575684 kb |
| Host | smart-dec4d420-8c28-4b2d-ab27-05b3a3d57097 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4119621349 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.xbar_stress_al l_with_reset_error.4119621349 |
| Directory | /workspace/18.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/18.xbar_unmapped_addr.3265040829 |
| Short name | T2525 |
| Test name | |
| Test status | |
| Simulation time | 284190610 ps |
| CPU time | 33.1 seconds |
| Started | Aug 12 06:48:38 PM PDT 24 |
| Finished | Aug 12 06:49:11 PM PDT 24 |
| Peak memory | 575664 kb |
| Host | smart-3a3d2877-01df-4992-8902-e7d9277fbff6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3265040829 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.xbar_unmapped_addr.3265040829 |
| Directory | /workspace/18.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/19.chip_csr_mem_rw_with_rand_reset.420460930 |
| Short name | T2346 |
| Test name | |
| Test status | |
| Simulation time | 8033588972 ps |
| CPU time | 929.57 seconds |
| Started | Aug 12 06:48:54 PM PDT 24 |
| Finished | Aug 12 07:04:24 PM PDT 24 |
| Peak memory | 652616 kb |
| Host | smart-81c13fa7-3966-4c27-9d25-12698ccc685e |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=420460930 -assert nopostproc +U VM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top. vdb -cm_log /dev/null -cm_name 19.chip_csr_mem_rw_with_rand_reset.420460930 |
| Directory | /workspace/19.chip_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/19.chip_csr_rw.2718403470 |
| Short name | T2268 |
| Test name | |
| Test status | |
| Simulation time | 4358035360 ps |
| CPU time | 320.43 seconds |
| Started | Aug 12 06:48:53 PM PDT 24 |
| Finished | Aug 12 06:54:14 PM PDT 24 |
| Peak memory | 596620 kb |
| Host | smart-68cf97af-a804-4a31-9811-19a92f16c5d3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2718403470 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.chip_csr_rw.2718403470 |
| Directory | /workspace/19.chip_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/19.chip_same_csr_outstanding.4261964270 |
| Short name | T2240 |
| Test name | |
| Test status | |
| Simulation time | 16116317844 ps |
| CPU time | 2777.93 seconds |
| Started | Aug 12 06:48:49 PM PDT 24 |
| Finished | Aug 12 07:35:07 PM PDT 24 |
| Peak memory | 593004 kb |
| Host | smart-54400dd9-6e5b-4fea-b834-e028bd704fd3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +run_same_csr_outstanding +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4261964270 -assert nopostproc +UVM_TE STNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb - cm_log /dev/null -cm_name 19.chip_same_csr_outstanding.4261964270 |
| Directory | /workspace/19.chip_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/19.chip_tl_errors.3355212907 |
| Short name | T2235 |
| Test name | |
| Test status | |
| Simulation time | 3375913668 ps |
| CPU time | 177.85 seconds |
| Started | Aug 12 06:48:55 PM PDT 24 |
| Finished | Aug 12 06:51:53 PM PDT 24 |
| Peak memory | 603352 kb |
| Host | smart-7013d75a-3e26-497f-8093-ea84de7847cf |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3355212907 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.chip_tl_errors.3355212907 |
| Directory | /workspace/19.chip_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/19.xbar_access_same_device.2722552142 |
| Short name | T2784 |
| Test name | |
| Test status | |
| Simulation time | 671823909 ps |
| CPU time | 47.78 seconds |
| Started | Aug 12 06:48:48 PM PDT 24 |
| Finished | Aug 12 06:49:36 PM PDT 24 |
| Peak memory | 575712 kb |
| Host | smart-157cc92c-06bf-4f76-bfba-ff1dba1b2c0c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2722552142 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.xbar_access_same_device .2722552142 |
| Directory | /workspace/19.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/19.xbar_access_same_device_slow_rsp.2765152637 |
| Short name | T939 |
| Test name | |
| Test status | |
| Simulation time | 15300739039 ps |
| CPU time | 266.03 seconds |
| Started | Aug 12 06:48:47 PM PDT 24 |
| Finished | Aug 12 06:53:13 PM PDT 24 |
| Peak memory | 575740 kb |
| Host | smart-797d0e88-5dcc-4d01-bf0f-8bd4c1b7774d |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2765152637 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.xbar_access_same_ device_slow_rsp.2765152637 |
| Directory | /workspace/19.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/19.xbar_error_and_unmapped_addr.2698582843 |
| Short name | T1646 |
| Test name | |
| Test status | |
| Simulation time | 946407222 ps |
| CPU time | 36.7 seconds |
| Started | Aug 12 06:48:54 PM PDT 24 |
| Finished | Aug 12 06:49:31 PM PDT 24 |
| Peak memory | 575696 kb |
| Host | smart-24c134a7-1259-4443-a714-da10040cf87a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2698582843 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.xbar_error_and_unmapped_add r.2698582843 |
| Directory | /workspace/19.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/19.xbar_error_random.794747626 |
| Short name | T1449 |
| Test name | |
| Test status | |
| Simulation time | 1042761246 ps |
| CPU time | 34.42 seconds |
| Started | Aug 12 06:48:52 PM PDT 24 |
| Finished | Aug 12 06:49:27 PM PDT 24 |
| Peak memory | 575664 kb |
| Host | smart-4722c0b7-b485-47c1-b928-36d9f0343c2c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=794747626 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.xbar_error_random.794747626 |
| Directory | /workspace/19.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/19.xbar_random.1343592881 |
| Short name | T728 |
| Test name | |
| Test status | |
| Simulation time | 61366869 ps |
| CPU time | 8.57 seconds |
| Started | Aug 12 06:48:54 PM PDT 24 |
| Finished | Aug 12 06:49:03 PM PDT 24 |
| Peak memory | 575564 kb |
| Host | smart-9e4921f5-893d-4031-ae0e-4cd1f0a82afc |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1343592881 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.xbar_random.1343592881 |
| Directory | /workspace/19.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/19.xbar_random_large_delays.2916945677 |
| Short name | T1767 |
| Test name | |
| Test status | |
| Simulation time | 59211603299 ps |
| CPU time | 617.67 seconds |
| Started | Aug 12 06:48:46 PM PDT 24 |
| Finished | Aug 12 06:59:04 PM PDT 24 |
| Peak memory | 575776 kb |
| Host | smart-6fbcbb4b-b5aa-4420-9480-a6b5327b9d19 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2916945677 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.xbar_random_large_delays.2916945677 |
| Directory | /workspace/19.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/19.xbar_random_slow_rsp.1384747873 |
| Short name | T670 |
| Test name | |
| Test status | |
| Simulation time | 17708547955 ps |
| CPU time | 310.55 seconds |
| Started | Aug 12 06:48:45 PM PDT 24 |
| Finished | Aug 12 06:53:56 PM PDT 24 |
| Peak memory | 575616 kb |
| Host | smart-c57d5d0e-411c-43c6-8955-82cd7e545f6b |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1384747873 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.xbar_random_slow_rsp.1384747873 |
| Directory | /workspace/19.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/19.xbar_random_zero_delays.1753958130 |
| Short name | T478 |
| Test name | |
| Test status | |
| Simulation time | 503220359 ps |
| CPU time | 45.57 seconds |
| Started | Aug 12 06:48:46 PM PDT 24 |
| Finished | Aug 12 06:49:32 PM PDT 24 |
| Peak memory | 575548 kb |
| Host | smart-5f2b055e-f163-4ecb-8678-7927bc3d18cb |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1753958130 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.xbar_random_zero_del ays.1753958130 |
| Directory | /workspace/19.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/19.xbar_same_source.2849298416 |
| Short name | T2259 |
| Test name | |
| Test status | |
| Simulation time | 427490813 ps |
| CPU time | 30.33 seconds |
| Started | Aug 12 06:48:48 PM PDT 24 |
| Finished | Aug 12 06:49:18 PM PDT 24 |
| Peak memory | 575708 kb |
| Host | smart-9ac320b7-e211-42d4-ae8d-cfa5aac1af76 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2849298416 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.xbar_same_source.2849298416 |
| Directory | /workspace/19.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/19.xbar_smoke.1316537625 |
| Short name | T1886 |
| Test name | |
| Test status | |
| Simulation time | 50413732 ps |
| CPU time | 6.37 seconds |
| Started | Aug 12 06:48:50 PM PDT 24 |
| Finished | Aug 12 06:48:57 PM PDT 24 |
| Peak memory | 574308 kb |
| Host | smart-504826af-d9e6-4c83-b305-a6bebace803e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1316537625 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.xbar_smoke.1316537625 |
| Directory | /workspace/19.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/19.xbar_smoke_large_delays.738065298 |
| Short name | T1720 |
| Test name | |
| Test status | |
| Simulation time | 9121317529 ps |
| CPU time | 94.99 seconds |
| Started | Aug 12 06:48:46 PM PDT 24 |
| Finished | Aug 12 06:50:21 PM PDT 24 |
| Peak memory | 573652 kb |
| Host | smart-cf8e596b-c4cb-44aa-a98d-bcecf07f687d |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=738065298 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.xbar_smoke_large_delays.738065298 |
| Directory | /workspace/19.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/19.xbar_smoke_slow_rsp.1374337669 |
| Short name | T1474 |
| Test name | |
| Test status | |
| Simulation time | 4177045063 ps |
| CPU time | 68.97 seconds |
| Started | Aug 12 06:48:48 PM PDT 24 |
| Finished | Aug 12 06:49:57 PM PDT 24 |
| Peak memory | 573636 kb |
| Host | smart-d406c6d4-13c1-4b92-9396-a9403c457aa9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1374337669 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.xbar_smoke_slow_rsp.1374337669 |
| Directory | /workspace/19.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/19.xbar_smoke_zero_delays.1428840411 |
| Short name | T2520 |
| Test name | |
| Test status | |
| Simulation time | 37862087 ps |
| CPU time | 5.53 seconds |
| Started | Aug 12 06:48:45 PM PDT 24 |
| Finished | Aug 12 06:48:51 PM PDT 24 |
| Peak memory | 573612 kb |
| Host | smart-0b34e80a-f602-4737-be54-2b9f0770b9b4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1428840411 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.xbar_smoke_zero_delay s.1428840411 |
| Directory | /workspace/19.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/19.xbar_stress_all.2802344683 |
| Short name | T2020 |
| Test name | |
| Test status | |
| Simulation time | 679961169 ps |
| CPU time | 66.58 seconds |
| Started | Aug 12 06:48:46 PM PDT 24 |
| Finished | Aug 12 06:49:53 PM PDT 24 |
| Peak memory | 575800 kb |
| Host | smart-a66d0018-063e-40de-bdce-c18009aa4de8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2802344683 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.xbar_stress_all.2802344683 |
| Directory | /workspace/19.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/19.xbar_stress_all_with_error.3835628899 |
| Short name | T2422 |
| Test name | |
| Test status | |
| Simulation time | 2324445342 ps |
| CPU time | 148.14 seconds |
| Started | Aug 12 06:48:55 PM PDT 24 |
| Finished | Aug 12 06:51:23 PM PDT 24 |
| Peak memory | 575552 kb |
| Host | smart-4f9db966-715e-42cc-b78a-d0e2dcb03bc0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3835628899 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.xbar_stress_all_with_error.3835628899 |
| Directory | /workspace/19.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/19.xbar_stress_all_with_rand_reset.1919980654 |
| Short name | T2671 |
| Test name | |
| Test status | |
| Simulation time | 13274046233 ps |
| CPU time | 625.29 seconds |
| Started | Aug 12 06:48:55 PM PDT 24 |
| Finished | Aug 12 06:59:20 PM PDT 24 |
| Peak memory | 575840 kb |
| Host | smart-5b63bf8a-ed11-42b2-a326-951318aad6fb |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1919980654 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.xbar_stress_all _with_rand_reset.1919980654 |
| Directory | /workspace/19.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/19.xbar_stress_all_with_reset_error.1972408891 |
| Short name | T2716 |
| Test name | |
| Test status | |
| Simulation time | 308708498 ps |
| CPU time | 80.84 seconds |
| Started | Aug 12 06:48:54 PM PDT 24 |
| Finished | Aug 12 06:50:14 PM PDT 24 |
| Peak memory | 575696 kb |
| Host | smart-5c905980-ebb4-4665-b33d-bf49d3fd19b6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1972408891 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.xbar_stress_al l_with_reset_error.1972408891 |
| Directory | /workspace/19.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/19.xbar_unmapped_addr.1410698897 |
| Short name | T2402 |
| Test name | |
| Test status | |
| Simulation time | 716250425 ps |
| CPU time | 31.69 seconds |
| Started | Aug 12 06:48:46 PM PDT 24 |
| Finished | Aug 12 06:49:18 PM PDT 24 |
| Peak memory | 575720 kb |
| Host | smart-0c254294-68b6-4089-959b-51a648eac4b3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1410698897 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.xbar_unmapped_addr.1410698897 |
| Directory | /workspace/19.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/2.chip_csr_bit_bash.282216099 |
| Short name | T1877 |
| Test name | |
| Test status | |
| Simulation time | 42634978230 ps |
| CPU time | 4590 seconds |
| Started | Aug 12 06:47:06 PM PDT 24 |
| Finished | Aug 12 08:03:37 PM PDT 24 |
| Peak memory | 592420 kb |
| Host | smart-ad34f478-879c-45d8-93e5-f04e3af90d84 |
| User | root |
| Command | /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +num_test_csrs=200 +csr_bit_bash +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=282216099 -assert nopostproc + UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top .vdb -cm_log /dev/null -cm_name 2.chip_csr_bit_bash.282216099 |
| Directory | /workspace/2.chip_csr_bit_bash/latest |
| Test location | /workspace/coverage/cover_reg_top/2.chip_csr_mem_rw_with_rand_reset.641687205 |
| Short name | T158 |
| Test name | |
| Test status | |
| Simulation time | 6175282674 ps |
| CPU time | 394.64 seconds |
| Started | Aug 12 06:47:21 PM PDT 24 |
| Finished | Aug 12 06:53:56 PM PDT 24 |
| Peak memory | 647664 kb |
| Host | smart-004edc77-95e3-4e93-8dc3-60e218f6bf59 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=641687205 -assert nopostproc +U VM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top. vdb -cm_log /dev/null -cm_name 2.chip_csr_mem_rw_with_rand_reset.641687205 |
| Directory | /workspace/2.chip_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/2.chip_csr_rw.1013224730 |
| Short name | T2112 |
| Test name | |
| Test status | |
| Simulation time | 4137422824 ps |
| CPU time | 270.44 seconds |
| Started | Aug 12 06:47:20 PM PDT 24 |
| Finished | Aug 12 06:51:51 PM PDT 24 |
| Peak memory | 598512 kb |
| Host | smart-83c36f62-3e48-4de3-b08b-5953f0e8de5e |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1013224730 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.chip_csr_rw.1013224730 |
| Directory | /workspace/2.chip_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/2.chip_prim_tl_access.3223314124 |
| Short name | T2556 |
| Test name | |
| Test status | |
| Simulation time | 5043752413 ps |
| CPU time | 178.65 seconds |
| Started | Aug 12 06:47:13 PM PDT 24 |
| Finished | Aug 12 06:50:12 PM PDT 24 |
| Peak memory | 591048 kb |
| Host | smart-46cba46d-bd3e-4fa1-b509-7c96f793ece9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +en_scb=0 +en_scb_tl_err_chk=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3223314124 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SE Q=chip_prim_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.chip_prim_tl_access.3223314124 |
| Directory | /workspace/2.chip_prim_tl_access/latest |
| Test location | /workspace/coverage/cover_reg_top/2.chip_rv_dm_lc_disabled.2964456874 |
| Short name | T2906 |
| Test name | |
| Test status | |
| Simulation time | 21807655582 ps |
| CPU time | 689.68 seconds |
| Started | Aug 12 06:47:15 PM PDT 24 |
| Finished | Aug 12 06:58:45 PM PDT 24 |
| Peak memory | 591020 kb |
| Host | smart-9a061856-868a-44bf-b0ff-1622fa897a2c |
| User | root |
| Command | /workspace/cover_reg_top/simv +en_scb=0 +en_scb_tl_err_chk=0 +use_jtag_dmi=1 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2964456874 -assert nopostproc +UVM_TESTNAME=chip_base_t est +UVM_TEST_SEQ=chip_rv_dm_lc_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.chip_rv_dm_lc_disabled.2964456874 |
| Directory | /workspace/2.chip_rv_dm_lc_disabled/latest |
| Test location | /workspace/coverage/cover_reg_top/2.chip_tl_errors.3733921446 |
| Short name | T568 |
| Test name | |
| Test status | |
| Simulation time | 3202701593 ps |
| CPU time | 167.57 seconds |
| Started | Aug 12 06:47:12 PM PDT 24 |
| Finished | Aug 12 06:50:00 PM PDT 24 |
| Peak memory | 598464 kb |
| Host | smart-1f96a0a4-0f06-49ef-a4c8-418c559f2d2f |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3733921446 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.chip_tl_errors.3733921446 |
| Directory | /workspace/2.chip_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/2.xbar_access_same_device.4134916122 |
| Short name | T2436 |
| Test name | |
| Test status | |
| Simulation time | 1325381359 ps |
| CPU time | 91.37 seconds |
| Started | Aug 12 06:47:19 PM PDT 24 |
| Finished | Aug 12 06:48:50 PM PDT 24 |
| Peak memory | 575536 kb |
| Host | smart-47b0e4f0-f06c-4154-bb83-c29b690b7c36 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4134916122 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.xbar_access_same_device. 4134916122 |
| Directory | /workspace/2.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/2.xbar_access_same_device_slow_rsp.1452964792 |
| Short name | T902 |
| Test name | |
| Test status | |
| Simulation time | 13803899189 ps |
| CPU time | 230.69 seconds |
| Started | Aug 12 06:47:18 PM PDT 24 |
| Finished | Aug 12 06:51:09 PM PDT 24 |
| Peak memory | 575772 kb |
| Host | smart-dff22586-2ae7-47df-ae53-98693430da3b |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1452964792 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.xbar_access_same_d evice_slow_rsp.1452964792 |
| Directory | /workspace/2.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/2.xbar_error_and_unmapped_addr.4270298150 |
| Short name | T2695 |
| Test name | |
| Test status | |
| Simulation time | 1074501308 ps |
| CPU time | 40.15 seconds |
| Started | Aug 12 06:47:18 PM PDT 24 |
| Finished | Aug 12 06:47:59 PM PDT 24 |
| Peak memory | 575496 kb |
| Host | smart-2c6bd837-67d7-4d51-8938-a3ec7393676d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4270298150 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.xbar_error_and_unmapped_addr .4270298150 |
| Directory | /workspace/2.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/2.xbar_error_random.1894122479 |
| Short name | T1580 |
| Test name | |
| Test status | |
| Simulation time | 406324324 ps |
| CPU time | 36.71 seconds |
| Started | Aug 12 06:47:17 PM PDT 24 |
| Finished | Aug 12 06:47:54 PM PDT 24 |
| Peak memory | 575716 kb |
| Host | smart-b61fef0f-f5a4-4e54-876c-79af19688ded |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1894122479 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.xbar_error_random.1894122479 |
| Directory | /workspace/2.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/2.xbar_random.1163213538 |
| Short name | T465 |
| Test name | |
| Test status | |
| Simulation time | 589183826 ps |
| CPU time | 45.05 seconds |
| Started | Aug 12 06:47:17 PM PDT 24 |
| Finished | Aug 12 06:48:03 PM PDT 24 |
| Peak memory | 575548 kb |
| Host | smart-13c6f9e4-2293-4e0e-8478-ff6576c63109 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1163213538 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.xbar_random.1163213538 |
| Directory | /workspace/2.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/2.xbar_random_large_delays.862624394 |
| Short name | T1659 |
| Test name | |
| Test status | |
| Simulation time | 72983943070 ps |
| CPU time | 735.56 seconds |
| Started | Aug 12 06:47:16 PM PDT 24 |
| Finished | Aug 12 06:59:32 PM PDT 24 |
| Peak memory | 575732 kb |
| Host | smart-dba83797-93a8-4ea3-bceb-919adb622811 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=862624394 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.xbar_random_large_delays.862624394 |
| Directory | /workspace/2.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/2.xbar_random_slow_rsp.1146971483 |
| Short name | T2185 |
| Test name | |
| Test status | |
| Simulation time | 62931595273 ps |
| CPU time | 1124.58 seconds |
| Started | Aug 12 06:47:19 PM PDT 24 |
| Finished | Aug 12 07:06:04 PM PDT 24 |
| Peak memory | 575720 kb |
| Host | smart-3bda98b7-1c1a-4587-87d4-a8b21fe4b5f1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1146971483 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.xbar_random_slow_rsp.1146971483 |
| Directory | /workspace/2.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/2.xbar_random_zero_delays.2819612894 |
| Short name | T1820 |
| Test name | |
| Test status | |
| Simulation time | 136139977 ps |
| CPU time | 12.3 seconds |
| Started | Aug 12 06:47:14 PM PDT 24 |
| Finished | Aug 12 06:47:27 PM PDT 24 |
| Peak memory | 575708 kb |
| Host | smart-6a09fa31-3837-41a4-9734-d3e3f66a0878 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2819612894 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.xbar_random_zero_dela ys.2819612894 |
| Directory | /workspace/2.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/2.xbar_same_source.1895864561 |
| Short name | T2107 |
| Test name | |
| Test status | |
| Simulation time | 622104275 ps |
| CPU time | 18.27 seconds |
| Started | Aug 12 06:47:15 PM PDT 24 |
| Finished | Aug 12 06:47:34 PM PDT 24 |
| Peak memory | 575612 kb |
| Host | smart-0b46aa69-05d5-4931-9375-81307cc01993 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1895864561 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.xbar_same_source.1895864561 |
| Directory | /workspace/2.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/2.xbar_smoke.3410959726 |
| Short name | T1541 |
| Test name | |
| Test status | |
| Simulation time | 45337367 ps |
| CPU time | 6.35 seconds |
| Started | Aug 12 06:47:20 PM PDT 24 |
| Finished | Aug 12 06:47:27 PM PDT 24 |
| Peak memory | 573624 kb |
| Host | smart-dcb23b40-5263-4cd7-87a4-3eab8e0f80f0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3410959726 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.xbar_smoke.3410959726 |
| Directory | /workspace/2.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/2.xbar_smoke_large_delays.3667700928 |
| Short name | T2561 |
| Test name | |
| Test status | |
| Simulation time | 8967503969 ps |
| CPU time | 87.68 seconds |
| Started | Aug 12 06:47:18 PM PDT 24 |
| Finished | Aug 12 06:48:45 PM PDT 24 |
| Peak memory | 573588 kb |
| Host | smart-ce871a0a-7360-40ac-b9d5-5582a1407357 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3667700928 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.xbar_smoke_large_delays.3667700928 |
| Directory | /workspace/2.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/2.xbar_smoke_slow_rsp.785568402 |
| Short name | T1738 |
| Test name | |
| Test status | |
| Simulation time | 2890766432 ps |
| CPU time | 44.95 seconds |
| Started | Aug 12 06:47:15 PM PDT 24 |
| Finished | Aug 12 06:48:00 PM PDT 24 |
| Peak memory | 573640 kb |
| Host | smart-1fa6cfcd-6783-483b-9961-21c2027c34df |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=785568402 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.xbar_smoke_slow_rsp.785568402 |
| Directory | /workspace/2.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/2.xbar_smoke_zero_delays.2942055320 |
| Short name | T2424 |
| Test name | |
| Test status | |
| Simulation time | 39813972 ps |
| CPU time | 5.64 seconds |
| Started | Aug 12 06:47:17 PM PDT 24 |
| Finished | Aug 12 06:47:23 PM PDT 24 |
| Peak memory | 574396 kb |
| Host | smart-b4813144-0c51-4f64-9c26-11e723ede5a5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2942055320 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.xbar_smoke_zero_delays .2942055320 |
| Directory | /workspace/2.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/2.xbar_stress_all.1337743034 |
| Short name | T2323 |
| Test name | |
| Test status | |
| Simulation time | 7076748089 ps |
| CPU time | 242.77 seconds |
| Started | Aug 12 06:47:17 PM PDT 24 |
| Finished | Aug 12 06:51:20 PM PDT 24 |
| Peak memory | 576572 kb |
| Host | smart-815980a4-d946-41c1-b64b-ac1eff7cba69 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1337743034 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.xbar_stress_all.1337743034 |
| Directory | /workspace/2.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/2.xbar_stress_all_with_error.2655791830 |
| Short name | T1629 |
| Test name | |
| Test status | |
| Simulation time | 3066432419 ps |
| CPU time | 226.01 seconds |
| Started | Aug 12 06:47:18 PM PDT 24 |
| Finished | Aug 12 06:51:05 PM PDT 24 |
| Peak memory | 576540 kb |
| Host | smart-a58f10f0-d7d9-48d6-b3a3-068d41848b06 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2655791830 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.xbar_stress_all_with_error.2655791830 |
| Directory | /workspace/2.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/2.xbar_stress_all_with_rand_reset.2779518932 |
| Short name | T2836 |
| Test name | |
| Test status | |
| Simulation time | 119133511 ps |
| CPU time | 74.73 seconds |
| Started | Aug 12 06:47:20 PM PDT 24 |
| Finished | Aug 12 06:48:35 PM PDT 24 |
| Peak memory | 575688 kb |
| Host | smart-679a18ec-b4f1-4a8d-9a3d-6e5e2c33e67f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2779518932 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.xbar_stress_all_ with_rand_reset.2779518932 |
| Directory | /workspace/2.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/2.xbar_stress_all_with_reset_error.2239439276 |
| Short name | T940 |
| Test name | |
| Test status | |
| Simulation time | 890329006 ps |
| CPU time | 171.7 seconds |
| Started | Aug 12 06:47:18 PM PDT 24 |
| Finished | Aug 12 06:50:10 PM PDT 24 |
| Peak memory | 576512 kb |
| Host | smart-e0a07f46-d109-4de3-bd2b-b572c0761248 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2239439276 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.xbar_stress_all _with_reset_error.2239439276 |
| Directory | /workspace/2.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/2.xbar_unmapped_addr.4178655896 |
| Short name | T1523 |
| Test name | |
| Test status | |
| Simulation time | 816688313 ps |
| CPU time | 33.55 seconds |
| Started | Aug 12 06:47:14 PM PDT 24 |
| Finished | Aug 12 06:47:48 PM PDT 24 |
| Peak memory | 575744 kb |
| Host | smart-bcef107c-dddd-497f-9821-f8a10be1c5d5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4178655896 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.xbar_unmapped_addr.4178655896 |
| Directory | /workspace/2.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/20.xbar_access_same_device.3249403049 |
| Short name | T2544 |
| Test name | |
| Test status | |
| Simulation time | 2366246888 ps |
| CPU time | 93.84 seconds |
| Started | Aug 12 06:48:54 PM PDT 24 |
| Finished | Aug 12 06:50:28 PM PDT 24 |
| Peak memory | 575724 kb |
| Host | smart-5b5a2eb7-27c3-442f-a33f-7fc0a4640a19 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3249403049 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.xbar_access_same_device .3249403049 |
| Directory | /workspace/20.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/20.xbar_access_same_device_slow_rsp.609921816 |
| Short name | T2425 |
| Test name | |
| Test status | |
| Simulation time | 40131898254 ps |
| CPU time | 681.09 seconds |
| Started | Aug 12 06:48:53 PM PDT 24 |
| Finished | Aug 12 07:00:15 PM PDT 24 |
| Peak memory | 575812 kb |
| Host | smart-8b8214da-3aa2-466a-a005-236844773c6c |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=609921816 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.xbar_access_same_d evice_slow_rsp.609921816 |
| Directory | /workspace/20.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/20.xbar_error_and_unmapped_addr.2261799152 |
| Short name | T2440 |
| Test name | |
| Test status | |
| Simulation time | 273921585 ps |
| CPU time | 30.21 seconds |
| Started | Aug 12 06:48:54 PM PDT 24 |
| Finished | Aug 12 06:49:24 PM PDT 24 |
| Peak memory | 575784 kb |
| Host | smart-d2f99e6d-e74d-4a2d-9398-125f7f33a7e8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2261799152 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.xbar_error_and_unmapped_add r.2261799152 |
| Directory | /workspace/20.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/20.xbar_error_random.3356228749 |
| Short name | T1517 |
| Test name | |
| Test status | |
| Simulation time | 313060799 ps |
| CPU time | 13.05 seconds |
| Started | Aug 12 06:48:55 PM PDT 24 |
| Finished | Aug 12 06:49:08 PM PDT 24 |
| Peak memory | 575484 kb |
| Host | smart-6594b629-1415-4033-83ed-f61ce009f615 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3356228749 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.xbar_error_random.3356228749 |
| Directory | /workspace/20.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/20.xbar_random.2767173542 |
| Short name | T2597 |
| Test name | |
| Test status | |
| Simulation time | 1980330169 ps |
| CPU time | 73.12 seconds |
| Started | Aug 12 06:48:55 PM PDT 24 |
| Finished | Aug 12 06:50:08 PM PDT 24 |
| Peak memory | 575720 kb |
| Host | smart-bd9badec-fa06-469f-9d98-94809dcbc9c0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2767173542 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.xbar_random.2767173542 |
| Directory | /workspace/20.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/20.xbar_random_large_delays.547408292 |
| Short name | T1768 |
| Test name | |
| Test status | |
| Simulation time | 5967522109 ps |
| CPU time | 64.1 seconds |
| Started | Aug 12 06:48:54 PM PDT 24 |
| Finished | Aug 12 06:49:58 PM PDT 24 |
| Peak memory | 574372 kb |
| Host | smart-2b8e5749-a5d5-41a5-a290-2fbbcf9216f5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=547408292 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.xbar_random_large_delays.547408292 |
| Directory | /workspace/20.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/20.xbar_random_slow_rsp.3927472926 |
| Short name | T2659 |
| Test name | |
| Test status | |
| Simulation time | 32674313183 ps |
| CPU time | 536.37 seconds |
| Started | Aug 12 06:48:56 PM PDT 24 |
| Finished | Aug 12 06:57:53 PM PDT 24 |
| Peak memory | 575728 kb |
| Host | smart-3770f243-9fe9-4e46-afff-91ef944a6332 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3927472926 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.xbar_random_slow_rsp.3927472926 |
| Directory | /workspace/20.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/20.xbar_random_zero_delays.402786267 |
| Short name | T2679 |
| Test name | |
| Test status | |
| Simulation time | 234140910 ps |
| CPU time | 21.73 seconds |
| Started | Aug 12 06:48:57 PM PDT 24 |
| Finished | Aug 12 06:49:19 PM PDT 24 |
| Peak memory | 575568 kb |
| Host | smart-8fbdd48a-83e1-40b0-b908-1ad8225bd0fc |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=402786267 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.xbar_random_zero_dela ys.402786267 |
| Directory | /workspace/20.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/20.xbar_same_source.3139317076 |
| Short name | T2035 |
| Test name | |
| Test status | |
| Simulation time | 622236433 ps |
| CPU time | 20.28 seconds |
| Started | Aug 12 06:48:54 PM PDT 24 |
| Finished | Aug 12 06:49:14 PM PDT 24 |
| Peak memory | 575528 kb |
| Host | smart-489181e5-44e8-4677-a6ee-a70d9be18cff |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3139317076 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.xbar_same_source.3139317076 |
| Directory | /workspace/20.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/20.xbar_smoke.1639669063 |
| Short name | T1487 |
| Test name | |
| Test status | |
| Simulation time | 135559115 ps |
| CPU time | 7.12 seconds |
| Started | Aug 12 06:48:54 PM PDT 24 |
| Finished | Aug 12 06:49:01 PM PDT 24 |
| Peak memory | 573560 kb |
| Host | smart-88a4fcc2-6a30-4b58-b8b6-9c464dc3c825 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1639669063 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.xbar_smoke.1639669063 |
| Directory | /workspace/20.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/20.xbar_smoke_large_delays.2770642198 |
| Short name | T1613 |
| Test name | |
| Test status | |
| Simulation time | 7458201960 ps |
| CPU time | 76.43 seconds |
| Started | Aug 12 06:48:55 PM PDT 24 |
| Finished | Aug 12 06:50:11 PM PDT 24 |
| Peak memory | 573676 kb |
| Host | smart-38dd395a-83c7-4a05-9638-d0181e07a297 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2770642198 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.xbar_smoke_large_delays.2770642198 |
| Directory | /workspace/20.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/20.xbar_smoke_slow_rsp.94390342 |
| Short name | T2001 |
| Test name | |
| Test status | |
| Simulation time | 5877849073 ps |
| CPU time | 94.29 seconds |
| Started | Aug 12 06:48:55 PM PDT 24 |
| Finished | Aug 12 06:50:30 PM PDT 24 |
| Peak memory | 573664 kb |
| Host | smart-d93c094f-5955-4bc0-a2fb-0ab017a024eb |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=94390342 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.xbar_smoke_slow_rsp.94390342 |
| Directory | /workspace/20.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/20.xbar_smoke_zero_delays.2289356293 |
| Short name | T1928 |
| Test name | |
| Test status | |
| Simulation time | 50178065 ps |
| CPU time | 6.78 seconds |
| Started | Aug 12 06:48:53 PM PDT 24 |
| Finished | Aug 12 06:49:00 PM PDT 24 |
| Peak memory | 573564 kb |
| Host | smart-6b2db1a8-8baa-4fd3-9057-b8861065d271 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2289356293 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.xbar_smoke_zero_delay s.2289356293 |
| Directory | /workspace/20.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/20.xbar_stress_all.3003743827 |
| Short name | T2938 |
| Test name | |
| Test status | |
| Simulation time | 6752936157 ps |
| CPU time | 232.51 seconds |
| Started | Aug 12 06:48:54 PM PDT 24 |
| Finished | Aug 12 06:52:47 PM PDT 24 |
| Peak memory | 575792 kb |
| Host | smart-db211de4-e6c5-40e3-9b7d-0456396900cd |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3003743827 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.xbar_stress_all.3003743827 |
| Directory | /workspace/20.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/20.xbar_stress_all_with_error.3389737809 |
| Short name | T1991 |
| Test name | |
| Test status | |
| Simulation time | 1802122324 ps |
| CPU time | 139.37 seconds |
| Started | Aug 12 06:49:04 PM PDT 24 |
| Finished | Aug 12 06:51:24 PM PDT 24 |
| Peak memory | 575692 kb |
| Host | smart-7cb42cf6-ab63-4f5d-892f-8711d3f9089a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3389737809 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.xbar_stress_all_with_error.3389737809 |
| Directory | /workspace/20.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/20.xbar_stress_all_with_reset_error.58829202 |
| Short name | T2284 |
| Test name | |
| Test status | |
| Simulation time | 1381771033 ps |
| CPU time | 123.24 seconds |
| Started | Aug 12 06:49:06 PM PDT 24 |
| Finished | Aug 12 06:51:09 PM PDT 24 |
| Peak memory | 575688 kb |
| Host | smart-35b3b404-8a2a-40f6-8897-1ccb815171bb |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58829202 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_res et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.xbar_stress_all_ with_reset_error.58829202 |
| Directory | /workspace/20.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/20.xbar_unmapped_addr.410777849 |
| Short name | T2764 |
| Test name | |
| Test status | |
| Simulation time | 202059888 ps |
| CPU time | 26.32 seconds |
| Started | Aug 12 06:48:54 PM PDT 24 |
| Finished | Aug 12 06:49:21 PM PDT 24 |
| Peak memory | 575724 kb |
| Host | smart-c0898f71-e4b1-4a6a-9526-6a81f772258b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=410777849 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.xbar_unmapped_addr.410777849 |
| Directory | /workspace/20.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/21.xbar_access_same_device.2257786797 |
| Short name | T2578 |
| Test name | |
| Test status | |
| Simulation time | 1841958817 ps |
| CPU time | 68.79 seconds |
| Started | Aug 12 06:49:03 PM PDT 24 |
| Finished | Aug 12 06:50:11 PM PDT 24 |
| Peak memory | 575584 kb |
| Host | smart-1bff5ebd-7869-40a4-a21e-4458621e9e91 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2257786797 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.xbar_access_same_device .2257786797 |
| Directory | /workspace/21.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/21.xbar_access_same_device_slow_rsp.1068238352 |
| Short name | T2595 |
| Test name | |
| Test status | |
| Simulation time | 94995029579 ps |
| CPU time | 1710.48 seconds |
| Started | Aug 12 06:49:04 PM PDT 24 |
| Finished | Aug 12 07:17:35 PM PDT 24 |
| Peak memory | 575680 kb |
| Host | smart-fd2b9e50-b15a-4b1b-8773-b4883a6c29f8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1068238352 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.xbar_access_same_ device_slow_rsp.1068238352 |
| Directory | /workspace/21.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/21.xbar_error_and_unmapped_addr.2248447826 |
| Short name | T1979 |
| Test name | |
| Test status | |
| Simulation time | 1125846530 ps |
| CPU time | 47.66 seconds |
| Started | Aug 12 06:49:03 PM PDT 24 |
| Finished | Aug 12 06:49:51 PM PDT 24 |
| Peak memory | 575708 kb |
| Host | smart-02a52d62-97f1-4064-9b2d-47904c7276cd |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2248447826 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.xbar_error_and_unmapped_add r.2248447826 |
| Directory | /workspace/21.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/21.xbar_error_random.2973574702 |
| Short name | T1549 |
| Test name | |
| Test status | |
| Simulation time | 535613467 ps |
| CPU time | 35.92 seconds |
| Started | Aug 12 06:49:04 PM PDT 24 |
| Finished | Aug 12 06:49:40 PM PDT 24 |
| Peak memory | 575500 kb |
| Host | smart-04379579-1e7c-410f-968e-cdb1bc867dca |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2973574702 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.xbar_error_random.2973574702 |
| Directory | /workspace/21.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/21.xbar_random.3342096122 |
| Short name | T2690 |
| Test name | |
| Test status | |
| Simulation time | 2020357807 ps |
| CPU time | 74.04 seconds |
| Started | Aug 12 06:49:03 PM PDT 24 |
| Finished | Aug 12 06:50:17 PM PDT 24 |
| Peak memory | 575664 kb |
| Host | smart-66cb9a74-ac26-481c-8ec6-f17b4eab04e4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3342096122 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.xbar_random.3342096122 |
| Directory | /workspace/21.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/21.xbar_random_large_delays.2629926078 |
| Short name | T1484 |
| Test name | |
| Test status | |
| Simulation time | 12455359436 ps |
| CPU time | 134.68 seconds |
| Started | Aug 12 06:49:05 PM PDT 24 |
| Finished | Aug 12 06:51:20 PM PDT 24 |
| Peak memory | 575776 kb |
| Host | smart-bdcc018e-8a2f-4078-8799-efe78f4edd40 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2629926078 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.xbar_random_large_delays.2629926078 |
| Directory | /workspace/21.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/21.xbar_random_slow_rsp.2261024843 |
| Short name | T1899 |
| Test name | |
| Test status | |
| Simulation time | 8068450209 ps |
| CPU time | 137.43 seconds |
| Started | Aug 12 06:49:04 PM PDT 24 |
| Finished | Aug 12 06:51:22 PM PDT 24 |
| Peak memory | 575688 kb |
| Host | smart-fe88ec3a-1d68-4339-b9a5-99a8fc413fe7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2261024843 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.xbar_random_slow_rsp.2261024843 |
| Directory | /workspace/21.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/21.xbar_random_zero_delays.2986166582 |
| Short name | T526 |
| Test name | |
| Test status | |
| Simulation time | 574159242 ps |
| CPU time | 42.6 seconds |
| Started | Aug 12 06:49:02 PM PDT 24 |
| Finished | Aug 12 06:49:45 PM PDT 24 |
| Peak memory | 575588 kb |
| Host | smart-cfd3a906-c3ad-48ec-ba8a-7e87d23e7220 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2986166582 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.xbar_random_zero_del ays.2986166582 |
| Directory | /workspace/21.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/21.xbar_same_source.832077170 |
| Short name | T1980 |
| Test name | |
| Test status | |
| Simulation time | 850403301 ps |
| CPU time | 24.33 seconds |
| Started | Aug 12 06:49:02 PM PDT 24 |
| Finished | Aug 12 06:49:27 PM PDT 24 |
| Peak memory | 575568 kb |
| Host | smart-40fac383-450f-49b3-b2c2-53a8aca3e644 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=832077170 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.xbar_same_source.832077170 |
| Directory | /workspace/21.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/21.xbar_smoke.3311135732 |
| Short name | T2097 |
| Test name | |
| Test status | |
| Simulation time | 192651145 ps |
| CPU time | 8.63 seconds |
| Started | Aug 12 06:49:03 PM PDT 24 |
| Finished | Aug 12 06:49:12 PM PDT 24 |
| Peak memory | 573596 kb |
| Host | smart-4d820f0c-6abc-4d4d-8b12-7228945844a9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3311135732 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.xbar_smoke.3311135732 |
| Directory | /workspace/21.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/21.xbar_smoke_large_delays.2774732484 |
| Short name | T2054 |
| Test name | |
| Test status | |
| Simulation time | 9911035926 ps |
| CPU time | 98 seconds |
| Started | Aug 12 06:49:04 PM PDT 24 |
| Finished | Aug 12 06:50:42 PM PDT 24 |
| Peak memory | 573628 kb |
| Host | smart-1688569b-7688-4af6-afdb-dacfbab8b10e |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2774732484 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.xbar_smoke_large_delays.2774732484 |
| Directory | /workspace/21.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/21.xbar_smoke_slow_rsp.1203726326 |
| Short name | T1630 |
| Test name | |
| Test status | |
| Simulation time | 5226064982 ps |
| CPU time | 88.17 seconds |
| Started | Aug 12 06:49:04 PM PDT 24 |
| Finished | Aug 12 06:50:32 PM PDT 24 |
| Peak memory | 574352 kb |
| Host | smart-6ccb785e-8d44-4899-b5fb-631f4c1842ce |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1203726326 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.xbar_smoke_slow_rsp.1203726326 |
| Directory | /workspace/21.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/21.xbar_smoke_zero_delays.3437012127 |
| Short name | T1752 |
| Test name | |
| Test status | |
| Simulation time | 41534316 ps |
| CPU time | 6.12 seconds |
| Started | Aug 12 06:49:03 PM PDT 24 |
| Finished | Aug 12 06:49:09 PM PDT 24 |
| Peak memory | 573580 kb |
| Host | smart-2ab9173c-a42e-4bc6-b391-82e9ab490b6a |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3437012127 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.xbar_smoke_zero_delay s.3437012127 |
| Directory | /workspace/21.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/21.xbar_stress_all.2160436208 |
| Short name | T2807 |
| Test name | |
| Test status | |
| Simulation time | 3266693958 ps |
| CPU time | 94.44 seconds |
| Started | Aug 12 06:49:01 PM PDT 24 |
| Finished | Aug 12 06:50:36 PM PDT 24 |
| Peak memory | 575792 kb |
| Host | smart-d1a7dc74-334e-4246-8a89-68a722ec70a8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2160436208 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.xbar_stress_all.2160436208 |
| Directory | /workspace/21.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/21.xbar_stress_all_with_error.3785991648 |
| Short name | T2933 |
| Test name | |
| Test status | |
| Simulation time | 5353450976 ps |
| CPU time | 173.8 seconds |
| Started | Aug 12 06:49:02 PM PDT 24 |
| Finished | Aug 12 06:51:56 PM PDT 24 |
| Peak memory | 576040 kb |
| Host | smart-b73f3fb2-6ca2-4915-9dcc-cbaa0974af1a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3785991648 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.xbar_stress_all_with_error.3785991648 |
| Directory | /workspace/21.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/21.xbar_stress_all_with_rand_reset.926957743 |
| Short name | T2483 |
| Test name | |
| Test status | |
| Simulation time | 471546422 ps |
| CPU time | 235.31 seconds |
| Started | Aug 12 06:49:05 PM PDT 24 |
| Finished | Aug 12 06:53:00 PM PDT 24 |
| Peak memory | 576524 kb |
| Host | smart-ad35798a-3a4a-4341-9963-67a864b4abe3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=926957743 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_res et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.xbar_stress_all_ with_rand_reset.926957743 |
| Directory | /workspace/21.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/21.xbar_stress_all_with_reset_error.2177526341 |
| Short name | T1981 |
| Test name | |
| Test status | |
| Simulation time | 3700578341 ps |
| CPU time | 427.41 seconds |
| Started | Aug 12 06:49:04 PM PDT 24 |
| Finished | Aug 12 06:56:11 PM PDT 24 |
| Peak memory | 576600 kb |
| Host | smart-0c7db975-1e18-4d29-b47e-13083f4d6e92 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2177526341 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.xbar_stress_al l_with_reset_error.2177526341 |
| Directory | /workspace/21.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/21.xbar_unmapped_addr.1195263000 |
| Short name | T2883 |
| Test name | |
| Test status | |
| Simulation time | 431496204 ps |
| CPU time | 20.08 seconds |
| Started | Aug 12 06:49:03 PM PDT 24 |
| Finished | Aug 12 06:49:23 PM PDT 24 |
| Peak memory | 575608 kb |
| Host | smart-0dcd64e7-a9b9-41e2-910a-56b2c166d9df |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1195263000 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.xbar_unmapped_addr.1195263000 |
| Directory | /workspace/21.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/22.chip_tl_errors.1673663774 |
| Short name | T2890 |
| Test name | |
| Test status | |
| Simulation time | 3754588688 ps |
| CPU time | 176.12 seconds |
| Started | Aug 12 06:49:01 PM PDT 24 |
| Finished | Aug 12 06:51:57 PM PDT 24 |
| Peak memory | 598144 kb |
| Host | smart-1e2f1e14-727f-484f-964e-ed46f14d1d26 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1673663774 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.chip_tl_errors.1673663774 |
| Directory | /workspace/22.chip_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/22.xbar_access_same_device.1188933206 |
| Short name | T1534 |
| Test name | |
| Test status | |
| Simulation time | 2282589808 ps |
| CPU time | 84.31 seconds |
| Started | Aug 12 06:49:11 PM PDT 24 |
| Finished | Aug 12 06:50:36 PM PDT 24 |
| Peak memory | 575616 kb |
| Host | smart-b5ddc09f-c2a5-4836-9343-059411adb011 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1188933206 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.xbar_access_same_device .1188933206 |
| Directory | /workspace/22.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/22.xbar_access_same_device_slow_rsp.2369259222 |
| Short name | T2297 |
| Test name | |
| Test status | |
| Simulation time | 25657136852 ps |
| CPU time | 421.78 seconds |
| Started | Aug 12 06:49:10 PM PDT 24 |
| Finished | Aug 12 06:56:11 PM PDT 24 |
| Peak memory | 575628 kb |
| Host | smart-ef4164b9-7308-492e-ad12-0c94ca3af20d |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2369259222 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.xbar_access_same_ device_slow_rsp.2369259222 |
| Directory | /workspace/22.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/22.xbar_error_and_unmapped_addr.1951948024 |
| Short name | T1459 |
| Test name | |
| Test status | |
| Simulation time | 1122256815 ps |
| CPU time | 40.1 seconds |
| Started | Aug 12 06:49:10 PM PDT 24 |
| Finished | Aug 12 06:49:50 PM PDT 24 |
| Peak memory | 575752 kb |
| Host | smart-24a029fc-51bd-4db2-bed4-797c5b7f382a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1951948024 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.xbar_error_and_unmapped_add r.1951948024 |
| Directory | /workspace/22.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/22.xbar_error_random.474293038 |
| Short name | T2407 |
| Test name | |
| Test status | |
| Simulation time | 2287664346 ps |
| CPU time | 71.39 seconds |
| Started | Aug 12 06:49:15 PM PDT 24 |
| Finished | Aug 12 06:50:26 PM PDT 24 |
| Peak memory | 575600 kb |
| Host | smart-54dd3e24-3d65-4c21-acf8-fc66c90ad425 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=474293038 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.xbar_error_random.474293038 |
| Directory | /workspace/22.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/22.xbar_random.2108095828 |
| Short name | T467 |
| Test name | |
| Test status | |
| Simulation time | 508329481 ps |
| CPU time | 38.86 seconds |
| Started | Aug 12 06:49:09 PM PDT 24 |
| Finished | Aug 12 06:49:47 PM PDT 24 |
| Peak memory | 575516 kb |
| Host | smart-fcc3a5cf-a47a-4fda-9632-6bffeca90380 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2108095828 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.xbar_random.2108095828 |
| Directory | /workspace/22.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/22.xbar_random_large_delays.1582037192 |
| Short name | T2076 |
| Test name | |
| Test status | |
| Simulation time | 26525812259 ps |
| CPU time | 288.92 seconds |
| Started | Aug 12 06:49:11 PM PDT 24 |
| Finished | Aug 12 06:54:00 PM PDT 24 |
| Peak memory | 575740 kb |
| Host | smart-2d37784a-03e2-443e-ae0e-39eeb1c64c7a |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1582037192 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.xbar_random_large_delays.1582037192 |
| Directory | /workspace/22.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/22.xbar_random_slow_rsp.1776310442 |
| Short name | T2844 |
| Test name | |
| Test status | |
| Simulation time | 5266639943 ps |
| CPU time | 87.88 seconds |
| Started | Aug 12 06:49:12 PM PDT 24 |
| Finished | Aug 12 06:50:40 PM PDT 24 |
| Peak memory | 573700 kb |
| Host | smart-1bf55370-a510-45fa-b217-eea994f9392a |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1776310442 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.xbar_random_slow_rsp.1776310442 |
| Directory | /workspace/22.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/22.xbar_random_zero_delays.1307145489 |
| Short name | T2439 |
| Test name | |
| Test status | |
| Simulation time | 568524880 ps |
| CPU time | 51.2 seconds |
| Started | Aug 12 06:49:14 PM PDT 24 |
| Finished | Aug 12 06:50:05 PM PDT 24 |
| Peak memory | 575552 kb |
| Host | smart-fc465633-585a-4575-bd37-5f012daf8c1f |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1307145489 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.xbar_random_zero_del ays.1307145489 |
| Directory | /workspace/22.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/22.xbar_same_source.4289877380 |
| Short name | T1841 |
| Test name | |
| Test status | |
| Simulation time | 473243227 ps |
| CPU time | 35.84 seconds |
| Started | Aug 12 06:49:14 PM PDT 24 |
| Finished | Aug 12 06:49:50 PM PDT 24 |
| Peak memory | 575684 kb |
| Host | smart-6431d7ee-4940-4658-8de7-244727016d22 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4289877380 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.xbar_same_source.4289877380 |
| Directory | /workspace/22.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/22.xbar_smoke.3405931094 |
| Short name | T2777 |
| Test name | |
| Test status | |
| Simulation time | 259213827 ps |
| CPU time | 9.35 seconds |
| Started | Aug 12 06:49:05 PM PDT 24 |
| Finished | Aug 12 06:49:15 PM PDT 24 |
| Peak memory | 574260 kb |
| Host | smart-88fbfbd1-0fbd-4bf0-b13c-ba1cfeb3fcdf |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3405931094 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.xbar_smoke.3405931094 |
| Directory | /workspace/22.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/22.xbar_smoke_large_delays.1344661635 |
| Short name | T2709 |
| Test name | |
| Test status | |
| Simulation time | 8858690699 ps |
| CPU time | 92.75 seconds |
| Started | Aug 12 06:49:09 PM PDT 24 |
| Finished | Aug 12 06:50:42 PM PDT 24 |
| Peak memory | 574348 kb |
| Host | smart-fce0ddc9-c3af-4063-b94e-d07b62c079c2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1344661635 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.xbar_smoke_large_delays.1344661635 |
| Directory | /workspace/22.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/22.xbar_smoke_slow_rsp.2477634353 |
| Short name | T1628 |
| Test name | |
| Test status | |
| Simulation time | 5345337586 ps |
| CPU time | 89.35 seconds |
| Started | Aug 12 06:49:09 PM PDT 24 |
| Finished | Aug 12 06:50:38 PM PDT 24 |
| Peak memory | 573664 kb |
| Host | smart-94686628-bc67-40a9-9e26-c86fcf037cee |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2477634353 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.xbar_smoke_slow_rsp.2477634353 |
| Directory | /workspace/22.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/22.xbar_smoke_zero_delays.3095246717 |
| Short name | T81 |
| Test name | |
| Test status | |
| Simulation time | 36374544 ps |
| CPU time | 6.15 seconds |
| Started | Aug 12 06:49:10 PM PDT 24 |
| Finished | Aug 12 06:49:16 PM PDT 24 |
| Peak memory | 573628 kb |
| Host | smart-50188826-bba0-46ff-9bbc-004e87d2ad29 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3095246717 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.xbar_smoke_zero_delay s.3095246717 |
| Directory | /workspace/22.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/22.xbar_stress_all.755708148 |
| Short name | T2106 |
| Test name | |
| Test status | |
| Simulation time | 6299590865 ps |
| CPU time | 245.68 seconds |
| Started | Aug 12 06:49:14 PM PDT 24 |
| Finished | Aug 12 06:53:20 PM PDT 24 |
| Peak memory | 575828 kb |
| Host | smart-8bd92615-20fc-4854-8bb3-5ca863a1e916 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=755708148 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.xbar_stress_all.755708148 |
| Directory | /workspace/22.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/22.xbar_stress_all_with_error.3979257119 |
| Short name | T923 |
| Test name | |
| Test status | |
| Simulation time | 11487741615 ps |
| CPU time | 362.9 seconds |
| Started | Aug 12 06:49:11 PM PDT 24 |
| Finished | Aug 12 06:55:14 PM PDT 24 |
| Peak memory | 576576 kb |
| Host | smart-3e7992e6-08f6-4bb2-9c47-65c3b94fe442 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3979257119 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.xbar_stress_all_with_error.3979257119 |
| Directory | /workspace/22.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/22.xbar_stress_all_with_rand_reset.1676835591 |
| Short name | T1778 |
| Test name | |
| Test status | |
| Simulation time | 141833618 ps |
| CPU time | 40.68 seconds |
| Started | Aug 12 06:49:14 PM PDT 24 |
| Finished | Aug 12 06:49:54 PM PDT 24 |
| Peak memory | 575708 kb |
| Host | smart-1a53fed2-5190-4fb3-b4e6-890815c8c95a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1676835591 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.xbar_stress_all _with_rand_reset.1676835591 |
| Directory | /workspace/22.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/22.xbar_stress_all_with_reset_error.1596635034 |
| Short name | T2605 |
| Test name | |
| Test status | |
| Simulation time | 85891119 ps |
| CPU time | 11.44 seconds |
| Started | Aug 12 06:49:10 PM PDT 24 |
| Finished | Aug 12 06:49:22 PM PDT 24 |
| Peak memory | 573628 kb |
| Host | smart-8901cbfe-17d1-47cb-adaa-aa54c9c1aca0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1596635034 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.xbar_stress_al l_with_reset_error.1596635034 |
| Directory | /workspace/22.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/22.xbar_unmapped_addr.158615196 |
| Short name | T2306 |
| Test name | |
| Test status | |
| Simulation time | 926132965 ps |
| CPU time | 40.9 seconds |
| Started | Aug 12 06:49:13 PM PDT 24 |
| Finished | Aug 12 06:49:54 PM PDT 24 |
| Peak memory | 575696 kb |
| Host | smart-324b93e5-6b17-445e-82cd-4ffd070faac6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=158615196 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.xbar_unmapped_addr.158615196 |
| Directory | /workspace/22.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/23.chip_tl_errors.1254080467 |
| Short name | T771 |
| Test name | |
| Test status | |
| Simulation time | 3875748340 ps |
| CPU time | 214.75 seconds |
| Started | Aug 12 06:49:21 PM PDT 24 |
| Finished | Aug 12 06:52:56 PM PDT 24 |
| Peak memory | 599388 kb |
| Host | smart-8499ea0e-1891-4b03-ba20-28c371de6f75 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1254080467 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.chip_tl_errors.1254080467 |
| Directory | /workspace/23.chip_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/23.xbar_access_same_device.1506725269 |
| Short name | T1825 |
| Test name | |
| Test status | |
| Simulation time | 525879821 ps |
| CPU time | 37.75 seconds |
| Started | Aug 12 06:49:20 PM PDT 24 |
| Finished | Aug 12 06:49:57 PM PDT 24 |
| Peak memory | 575732 kb |
| Host | smart-9b5c542a-d97f-47aa-a64c-7cd4f6300c35 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1506725269 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.xbar_access_same_device .1506725269 |
| Directory | /workspace/23.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/23.xbar_access_same_device_slow_rsp.1160647879 |
| Short name | T2832 |
| Test name | |
| Test status | |
| Simulation time | 133052255776 ps |
| CPU time | 2523.08 seconds |
| Started | Aug 12 06:49:19 PM PDT 24 |
| Finished | Aug 12 07:31:23 PM PDT 24 |
| Peak memory | 575852 kb |
| Host | smart-b7f5a531-008b-4a8e-9218-2a4432b51f3e |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1160647879 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.xbar_access_same_ device_slow_rsp.1160647879 |
| Directory | /workspace/23.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/23.xbar_error_and_unmapped_addr.1825181069 |
| Short name | T2062 |
| Test name | |
| Test status | |
| Simulation time | 1048023008 ps |
| CPU time | 47.77 seconds |
| Started | Aug 12 06:49:18 PM PDT 24 |
| Finished | Aug 12 06:50:06 PM PDT 24 |
| Peak memory | 575860 kb |
| Host | smart-a3941840-363f-4b0c-9400-26267b339783 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1825181069 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.xbar_error_and_unmapped_add r.1825181069 |
| Directory | /workspace/23.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/23.xbar_error_random.1693640086 |
| Short name | T1854 |
| Test name | |
| Test status | |
| Simulation time | 1528922054 ps |
| CPU time | 55.01 seconds |
| Started | Aug 12 06:49:21 PM PDT 24 |
| Finished | Aug 12 06:50:16 PM PDT 24 |
| Peak memory | 575740 kb |
| Host | smart-f6b5895d-1a90-47b8-a4d1-884c996c7dd3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1693640086 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.xbar_error_random.1693640086 |
| Directory | /workspace/23.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/23.xbar_random.1978576782 |
| Short name | T636 |
| Test name | |
| Test status | |
| Simulation time | 324931408 ps |
| CPU time | 30.89 seconds |
| Started | Aug 12 06:49:22 PM PDT 24 |
| Finished | Aug 12 06:49:53 PM PDT 24 |
| Peak memory | 575696 kb |
| Host | smart-11cec7b3-48ab-4946-8527-39194f6fe15c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1978576782 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.xbar_random.1978576782 |
| Directory | /workspace/23.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/23.xbar_random_large_delays.1156240457 |
| Short name | T2438 |
| Test name | |
| Test status | |
| Simulation time | 30669982935 ps |
| CPU time | 312.19 seconds |
| Started | Aug 12 06:49:20 PM PDT 24 |
| Finished | Aug 12 06:54:32 PM PDT 24 |
| Peak memory | 575728 kb |
| Host | smart-3404123d-ee7d-48ce-888f-2a2957f20a64 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1156240457 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.xbar_random_large_delays.1156240457 |
| Directory | /workspace/23.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/23.xbar_random_slow_rsp.3446654259 |
| Short name | T655 |
| Test name | |
| Test status | |
| Simulation time | 54528703907 ps |
| CPU time | 917.66 seconds |
| Started | Aug 12 06:49:20 PM PDT 24 |
| Finished | Aug 12 07:04:38 PM PDT 24 |
| Peak memory | 575696 kb |
| Host | smart-b023feef-cc09-4a03-8763-5765c5a37050 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3446654259 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.xbar_random_slow_rsp.3446654259 |
| Directory | /workspace/23.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/23.xbar_random_zero_delays.865002298 |
| Short name | T2581 |
| Test name | |
| Test status | |
| Simulation time | 375405169 ps |
| CPU time | 31.53 seconds |
| Started | Aug 12 06:49:19 PM PDT 24 |
| Finished | Aug 12 06:49:50 PM PDT 24 |
| Peak memory | 575648 kb |
| Host | smart-6bc48bfc-6d87-4c53-a941-612b4457d2ff |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=865002298 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.xbar_random_zero_dela ys.865002298 |
| Directory | /workspace/23.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/23.xbar_same_source.3023934361 |
| Short name | T546 |
| Test name | |
| Test status | |
| Simulation time | 481957524 ps |
| CPU time | 36.49 seconds |
| Started | Aug 12 06:49:20 PM PDT 24 |
| Finished | Aug 12 06:49:57 PM PDT 24 |
| Peak memory | 575512 kb |
| Host | smart-3cf25684-0951-4984-bfbe-1a197dce43b4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3023934361 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.xbar_same_source.3023934361 |
| Directory | /workspace/23.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/23.xbar_smoke.1751535615 |
| Short name | T2189 |
| Test name | |
| Test status | |
| Simulation time | 43106832 ps |
| CPU time | 6.21 seconds |
| Started | Aug 12 06:49:18 PM PDT 24 |
| Finished | Aug 12 06:49:25 PM PDT 24 |
| Peak memory | 574296 kb |
| Host | smart-d7e46731-38d7-4363-af39-d0c617de6b79 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1751535615 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.xbar_smoke.1751535615 |
| Directory | /workspace/23.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/23.xbar_smoke_large_delays.224133396 |
| Short name | T2174 |
| Test name | |
| Test status | |
| Simulation time | 8145436370 ps |
| CPU time | 82.99 seconds |
| Started | Aug 12 06:49:21 PM PDT 24 |
| Finished | Aug 12 06:50:44 PM PDT 24 |
| Peak memory | 574328 kb |
| Host | smart-c4e6be95-9c6b-44fe-89a2-f0abf1c08f5e |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=224133396 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.xbar_smoke_large_delays.224133396 |
| Directory | /workspace/23.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/23.xbar_smoke_slow_rsp.3758272464 |
| Short name | T639 |
| Test name | |
| Test status | |
| Simulation time | 4236568843 ps |
| CPU time | 71.72 seconds |
| Started | Aug 12 06:49:19 PM PDT 24 |
| Finished | Aug 12 06:50:31 PM PDT 24 |
| Peak memory | 573684 kb |
| Host | smart-f17ee6ab-650a-4094-97d7-d14de523383e |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3758272464 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.xbar_smoke_slow_rsp.3758272464 |
| Directory | /workspace/23.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/23.xbar_smoke_zero_delays.881829529 |
| Short name | T2682 |
| Test name | |
| Test status | |
| Simulation time | 54001800 ps |
| CPU time | 6.19 seconds |
| Started | Aug 12 06:49:18 PM PDT 24 |
| Finished | Aug 12 06:49:25 PM PDT 24 |
| Peak memory | 573604 kb |
| Host | smart-e566e3aa-2e04-423b-880a-1e270cdd63aa |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=881829529 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.xbar_smoke_zero_delays .881829529 |
| Directory | /workspace/23.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/23.xbar_stress_all.864660219 |
| Short name | T487 |
| Test name | |
| Test status | |
| Simulation time | 6538811497 ps |
| CPU time | 241.06 seconds |
| Started | Aug 12 06:49:19 PM PDT 24 |
| Finished | Aug 12 06:53:20 PM PDT 24 |
| Peak memory | 576540 kb |
| Host | smart-57c6acdd-e141-4904-8827-76d1c49aad70 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=864660219 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.xbar_stress_all.864660219 |
| Directory | /workspace/23.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/23.xbar_stress_all_with_error.1209196958 |
| Short name | T2632 |
| Test name | |
| Test status | |
| Simulation time | 229624286 ps |
| CPU time | 22.77 seconds |
| Started | Aug 12 06:49:18 PM PDT 24 |
| Finished | Aug 12 06:49:41 PM PDT 24 |
| Peak memory | 575528 kb |
| Host | smart-bd4ace8c-a910-4ddf-880c-9ac589a61302 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1209196958 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.xbar_stress_all_with_error.1209196958 |
| Directory | /workspace/23.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/23.xbar_stress_all_with_rand_reset.2779282297 |
| Short name | T2176 |
| Test name | |
| Test status | |
| Simulation time | 4767629560 ps |
| CPU time | 309.58 seconds |
| Started | Aug 12 06:49:19 PM PDT 24 |
| Finished | Aug 12 06:54:28 PM PDT 24 |
| Peak memory | 576604 kb |
| Host | smart-8e9733c2-fd9f-410b-b5a2-e0c423152e8e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2779282297 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.xbar_stress_all _with_rand_reset.2779282297 |
| Directory | /workspace/23.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/23.xbar_stress_all_with_reset_error.2289208061 |
| Short name | T942 |
| Test name | |
| Test status | |
| Simulation time | 631018579 ps |
| CPU time | 181.83 seconds |
| Started | Aug 12 06:49:21 PM PDT 24 |
| Finished | Aug 12 06:52:22 PM PDT 24 |
| Peak memory | 576544 kb |
| Host | smart-28026084-d450-45f2-9e27-4effcba0c096 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2289208061 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.xbar_stress_al l_with_reset_error.2289208061 |
| Directory | /workspace/23.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/23.xbar_unmapped_addr.419555642 |
| Short name | T2270 |
| Test name | |
| Test status | |
| Simulation time | 1104526572 ps |
| CPU time | 46.24 seconds |
| Started | Aug 12 06:49:19 PM PDT 24 |
| Finished | Aug 12 06:50:05 PM PDT 24 |
| Peak memory | 575676 kb |
| Host | smart-3f21a43b-8041-4b76-8f2f-1ed7a9e395a3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=419555642 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.xbar_unmapped_addr.419555642 |
| Directory | /workspace/23.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/24.xbar_access_same_device.2989451817 |
| Short name | T1745 |
| Test name | |
| Test status | |
| Simulation time | 405684972 ps |
| CPU time | 36.06 seconds |
| Started | Aug 12 06:49:26 PM PDT 24 |
| Finished | Aug 12 06:50:02 PM PDT 24 |
| Peak memory | 575592 kb |
| Host | smart-4ebf7533-233e-445c-aa46-c3c37d9a79c0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2989451817 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.xbar_access_same_device .2989451817 |
| Directory | /workspace/24.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/24.xbar_access_same_device_slow_rsp.2245192965 |
| Short name | T1788 |
| Test name | |
| Test status | |
| Simulation time | 150702386759 ps |
| CPU time | 2740.71 seconds |
| Started | Aug 12 06:49:28 PM PDT 24 |
| Finished | Aug 12 07:35:09 PM PDT 24 |
| Peak memory | 575624 kb |
| Host | smart-3e5d7763-6902-41b0-b85c-403fc80a8b71 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2245192965 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.xbar_access_same_ device_slow_rsp.2245192965 |
| Directory | /workspace/24.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/24.xbar_error_and_unmapped_addr.4006150220 |
| Short name | T2381 |
| Test name | |
| Test status | |
| Simulation time | 780470884 ps |
| CPU time | 28.63 seconds |
| Started | Aug 12 06:49:28 PM PDT 24 |
| Finished | Aug 12 06:49:56 PM PDT 24 |
| Peak memory | 575528 kb |
| Host | smart-7feec460-5753-4d50-8b9e-cfecfdcda9fa |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4006150220 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.xbar_error_and_unmapped_add r.4006150220 |
| Directory | /workspace/24.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/24.xbar_error_random.2124726210 |
| Short name | T1471 |
| Test name | |
| Test status | |
| Simulation time | 180333760 ps |
| CPU time | 17.24 seconds |
| Started | Aug 12 06:49:26 PM PDT 24 |
| Finished | Aug 12 06:49:43 PM PDT 24 |
| Peak memory | 575624 kb |
| Host | smart-38db5181-31e6-4e93-84ba-9087ab8f3abb |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2124726210 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.xbar_error_random.2124726210 |
| Directory | /workspace/24.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/24.xbar_random.139336034 |
| Short name | T2216 |
| Test name | |
| Test status | |
| Simulation time | 1241165197 ps |
| CPU time | 46.82 seconds |
| Started | Aug 12 06:49:28 PM PDT 24 |
| Finished | Aug 12 06:50:15 PM PDT 24 |
| Peak memory | 575680 kb |
| Host | smart-2ded3010-8413-46c4-8106-2eaddf0354d0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=139336034 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.xbar_random.139336034 |
| Directory | /workspace/24.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/24.xbar_random_large_delays.1052950213 |
| Short name | T1772 |
| Test name | |
| Test status | |
| Simulation time | 95495898147 ps |
| CPU time | 1009.17 seconds |
| Started | Aug 12 06:49:27 PM PDT 24 |
| Finished | Aug 12 07:06:16 PM PDT 24 |
| Peak memory | 575852 kb |
| Host | smart-b39c6e3a-0f78-4945-b20e-2fd1db5fa60f |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1052950213 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.xbar_random_large_delays.1052950213 |
| Directory | /workspace/24.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/24.xbar_random_slow_rsp.51571057 |
| Short name | T2467 |
| Test name | |
| Test status | |
| Simulation time | 63262965867 ps |
| CPU time | 1100.97 seconds |
| Started | Aug 12 06:49:26 PM PDT 24 |
| Finished | Aug 12 07:07:48 PM PDT 24 |
| Peak memory | 575788 kb |
| Host | smart-df4d4aba-2c0c-4868-9005-57e975d16c4b |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=51571057 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.xbar_random_slow_rsp.51571057 |
| Directory | /workspace/24.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/24.xbar_random_zero_delays.2163492819 |
| Short name | T2156 |
| Test name | |
| Test status | |
| Simulation time | 397919163 ps |
| CPU time | 38.11 seconds |
| Started | Aug 12 06:49:28 PM PDT 24 |
| Finished | Aug 12 06:50:06 PM PDT 24 |
| Peak memory | 575556 kb |
| Host | smart-8d6d5065-5ac4-4816-a400-98a422a7ae18 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2163492819 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.xbar_random_zero_del ays.2163492819 |
| Directory | /workspace/24.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/24.xbar_same_source.3578209112 |
| Short name | T2941 |
| Test name | |
| Test status | |
| Simulation time | 2501971138 ps |
| CPU time | 67.16 seconds |
| Started | Aug 12 06:49:28 PM PDT 24 |
| Finished | Aug 12 06:50:35 PM PDT 24 |
| Peak memory | 575676 kb |
| Host | smart-273964f4-85e8-4181-9e90-27faf3724672 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3578209112 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.xbar_same_source.3578209112 |
| Directory | /workspace/24.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/24.xbar_smoke.3286221513 |
| Short name | T1446 |
| Test name | |
| Test status | |
| Simulation time | 223357537 ps |
| CPU time | 8.68 seconds |
| Started | Aug 12 06:49:18 PM PDT 24 |
| Finished | Aug 12 06:49:27 PM PDT 24 |
| Peak memory | 573620 kb |
| Host | smart-7d128f73-bce7-4b89-9d16-77874ceee9f0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3286221513 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.xbar_smoke.3286221513 |
| Directory | /workspace/24.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/24.xbar_smoke_large_delays.2685631430 |
| Short name | T628 |
| Test name | |
| Test status | |
| Simulation time | 9478419035 ps |
| CPU time | 102.69 seconds |
| Started | Aug 12 06:49:31 PM PDT 24 |
| Finished | Aug 12 06:51:13 PM PDT 24 |
| Peak memory | 574328 kb |
| Host | smart-d1e64b7d-5d2d-4f62-bbe3-f6dadbd41835 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2685631430 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.xbar_smoke_large_delays.2685631430 |
| Directory | /workspace/24.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/24.xbar_smoke_slow_rsp.811722769 |
| Short name | T2429 |
| Test name | |
| Test status | |
| Simulation time | 5911173641 ps |
| CPU time | 100.74 seconds |
| Started | Aug 12 06:49:29 PM PDT 24 |
| Finished | Aug 12 06:51:10 PM PDT 24 |
| Peak memory | 574332 kb |
| Host | smart-fe2d59a3-aae3-4805-a8aa-81421daca852 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=811722769 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.xbar_smoke_slow_rsp.811722769 |
| Directory | /workspace/24.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/24.xbar_smoke_zero_delays.2116536896 |
| Short name | T1445 |
| Test name | |
| Test status | |
| Simulation time | 51157685 ps |
| CPU time | 6.22 seconds |
| Started | Aug 12 06:49:21 PM PDT 24 |
| Finished | Aug 12 06:49:27 PM PDT 24 |
| Peak memory | 574284 kb |
| Host | smart-6514b38c-95fb-4a89-b845-461e03d617cc |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2116536896 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.xbar_smoke_zero_delay s.2116536896 |
| Directory | /workspace/24.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/24.xbar_stress_all.456252596 |
| Short name | T2849 |
| Test name | |
| Test status | |
| Simulation time | 19540186848 ps |
| CPU time | 798.79 seconds |
| Started | Aug 12 06:49:28 PM PDT 24 |
| Finished | Aug 12 07:02:47 PM PDT 24 |
| Peak memory | 575784 kb |
| Host | smart-b4a9b747-b229-4b6b-88d1-361471ba6e6a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=456252596 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.xbar_stress_all.456252596 |
| Directory | /workspace/24.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/24.xbar_stress_all_with_error.2365759716 |
| Short name | T1468 |
| Test name | |
| Test status | |
| Simulation time | 8142564101 ps |
| CPU time | 306.17 seconds |
| Started | Aug 12 06:49:30 PM PDT 24 |
| Finished | Aug 12 06:54:36 PM PDT 24 |
| Peak memory | 576544 kb |
| Host | smart-40f7790d-1539-4ec1-b7a2-47a70e8d539c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2365759716 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.xbar_stress_all_with_error.2365759716 |
| Directory | /workspace/24.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/24.xbar_stress_all_with_reset_error.3602959553 |
| Short name | T1717 |
| Test name | |
| Test status | |
| Simulation time | 14495424 ps |
| CPU time | 7.48 seconds |
| Started | Aug 12 06:49:26 PM PDT 24 |
| Finished | Aug 12 06:49:34 PM PDT 24 |
| Peak memory | 573604 kb |
| Host | smart-b47fe087-4a7c-4b07-aebd-47569bccc3d6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3602959553 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.xbar_stress_al l_with_reset_error.3602959553 |
| Directory | /workspace/24.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/24.xbar_unmapped_addr.4281099913 |
| Short name | T618 |
| Test name | |
| Test status | |
| Simulation time | 706220530 ps |
| CPU time | 33.99 seconds |
| Started | Aug 12 06:49:26 PM PDT 24 |
| Finished | Aug 12 06:50:00 PM PDT 24 |
| Peak memory | 575532 kb |
| Host | smart-a36907a6-c868-469d-a6db-6fb07c103051 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4281099913 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.xbar_unmapped_addr.4281099913 |
| Directory | /workspace/24.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/25.xbar_access_same_device.2054533332 |
| Short name | T2592 |
| Test name | |
| Test status | |
| Simulation time | 2247743707 ps |
| CPU time | 88.93 seconds |
| Started | Aug 12 06:49:36 PM PDT 24 |
| Finished | Aug 12 06:51:05 PM PDT 24 |
| Peak memory | 575608 kb |
| Host | smart-0682c5ac-722c-43e8-b160-a8134332f2ae |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2054533332 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.xbar_access_same_device .2054533332 |
| Directory | /workspace/25.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/25.xbar_access_same_device_slow_rsp.149970900 |
| Short name | T2408 |
| Test name | |
| Test status | |
| Simulation time | 97130615050 ps |
| CPU time | 1799.39 seconds |
| Started | Aug 12 06:49:35 PM PDT 24 |
| Finished | Aug 12 07:19:34 PM PDT 24 |
| Peak memory | 575828 kb |
| Host | smart-79d94500-53e7-47f1-8ae6-e62b9cfaf848 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=149970900 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.xbar_access_same_d evice_slow_rsp.149970900 |
| Directory | /workspace/25.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/25.xbar_error_and_unmapped_addr.4159771926 |
| Short name | T1493 |
| Test name | |
| Test status | |
| Simulation time | 225916746 ps |
| CPU time | 26.62 seconds |
| Started | Aug 12 06:49:34 PM PDT 24 |
| Finished | Aug 12 06:50:01 PM PDT 24 |
| Peak memory | 575708 kb |
| Host | smart-625b3544-f7e3-40aa-916b-ff86163c79b9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4159771926 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.xbar_error_and_unmapped_add r.4159771926 |
| Directory | /workspace/25.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/25.xbar_error_random.1804986609 |
| Short name | T1470 |
| Test name | |
| Test status | |
| Simulation time | 280301111 ps |
| CPU time | 26.99 seconds |
| Started | Aug 12 06:49:34 PM PDT 24 |
| Finished | Aug 12 06:50:01 PM PDT 24 |
| Peak memory | 575644 kb |
| Host | smart-8787df01-879c-480a-9e77-e0a2841624d4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1804986609 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.xbar_error_random.1804986609 |
| Directory | /workspace/25.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/25.xbar_random.4230938057 |
| Short name | T1486 |
| Test name | |
| Test status | |
| Simulation time | 62122977 ps |
| CPU time | 9.23 seconds |
| Started | Aug 12 06:49:35 PM PDT 24 |
| Finished | Aug 12 06:49:44 PM PDT 24 |
| Peak memory | 575684 kb |
| Host | smart-e22128eb-d52e-4701-beb5-1e143da49035 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4230938057 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.xbar_random.4230938057 |
| Directory | /workspace/25.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/25.xbar_random_large_delays.1137291160 |
| Short name | T511 |
| Test name | |
| Test status | |
| Simulation time | 68293422504 ps |
| CPU time | 746.42 seconds |
| Started | Aug 12 06:49:34 PM PDT 24 |
| Finished | Aug 12 07:02:01 PM PDT 24 |
| Peak memory | 575804 kb |
| Host | smart-6413193f-20c6-4bdb-8176-2c64ac4fead5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1137291160 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.xbar_random_large_delays.1137291160 |
| Directory | /workspace/25.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/25.xbar_random_slow_rsp.3843671981 |
| Short name | T706 |
| Test name | |
| Test status | |
| Simulation time | 36683959606 ps |
| CPU time | 581.55 seconds |
| Started | Aug 12 06:49:34 PM PDT 24 |
| Finished | Aug 12 06:59:16 PM PDT 24 |
| Peak memory | 575672 kb |
| Host | smart-adbb97bc-e6f9-490e-a530-ebc16d725bd1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3843671981 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.xbar_random_slow_rsp.3843671981 |
| Directory | /workspace/25.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/25.xbar_random_zero_delays.1116577679 |
| Short name | T1644 |
| Test name | |
| Test status | |
| Simulation time | 398908260 ps |
| CPU time | 34.46 seconds |
| Started | Aug 12 06:49:35 PM PDT 24 |
| Finished | Aug 12 06:50:09 PM PDT 24 |
| Peak memory | 575560 kb |
| Host | smart-dfb67fb3-0ca7-4c83-a334-6ddd26b5b2b3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1116577679 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.xbar_random_zero_del ays.1116577679 |
| Directory | /workspace/25.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/25.xbar_same_source.1631671686 |
| Short name | T1794 |
| Test name | |
| Test status | |
| Simulation time | 573510810 ps |
| CPU time | 42.1 seconds |
| Started | Aug 12 06:49:35 PM PDT 24 |
| Finished | Aug 12 06:50:17 PM PDT 24 |
| Peak memory | 575620 kb |
| Host | smart-aa047829-ae04-42f1-8000-45128487bdb9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1631671686 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.xbar_same_source.1631671686 |
| Directory | /workspace/25.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/25.xbar_smoke.539492132 |
| Short name | T735 |
| Test name | |
| Test status | |
| Simulation time | 44455864 ps |
| CPU time | 6.48 seconds |
| Started | Aug 12 06:49:34 PM PDT 24 |
| Finished | Aug 12 06:49:41 PM PDT 24 |
| Peak memory | 573536 kb |
| Host | smart-08dda6af-b1f9-4ac4-8c7e-b7c32060d5f8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=539492132 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.xbar_smoke.539492132 |
| Directory | /workspace/25.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/25.xbar_smoke_large_delays.1953147376 |
| Short name | T686 |
| Test name | |
| Test status | |
| Simulation time | 8080478693 ps |
| CPU time | 83.08 seconds |
| Started | Aug 12 06:49:34 PM PDT 24 |
| Finished | Aug 12 06:50:57 PM PDT 24 |
| Peak memory | 573644 kb |
| Host | smart-9a2a31f0-36f9-4b00-8b2d-039697af14eb |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1953147376 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.xbar_smoke_large_delays.1953147376 |
| Directory | /workspace/25.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/25.xbar_smoke_slow_rsp.926653807 |
| Short name | T1506 |
| Test name | |
| Test status | |
| Simulation time | 4374954429 ps |
| CPU time | 75.18 seconds |
| Started | Aug 12 06:49:35 PM PDT 24 |
| Finished | Aug 12 06:50:51 PM PDT 24 |
| Peak memory | 573684 kb |
| Host | smart-04bc336c-64ef-4db6-8b73-5edea54c53cf |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=926653807 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.xbar_smoke_slow_rsp.926653807 |
| Directory | /workspace/25.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/25.xbar_smoke_zero_delays.705344679 |
| Short name | T1501 |
| Test name | |
| Test status | |
| Simulation time | 50978951 ps |
| CPU time | 6.86 seconds |
| Started | Aug 12 06:49:35 PM PDT 24 |
| Finished | Aug 12 06:49:42 PM PDT 24 |
| Peak memory | 574324 kb |
| Host | smart-4c492602-af25-43c2-9aa3-e889b1a9e79f |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=705344679 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.xbar_smoke_zero_delays .705344679 |
| Directory | /workspace/25.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/25.xbar_stress_all.2272586357 |
| Short name | T610 |
| Test name | |
| Test status | |
| Simulation time | 3333799661 ps |
| CPU time | 118.16 seconds |
| Started | Aug 12 06:49:55 PM PDT 24 |
| Finished | Aug 12 06:51:53 PM PDT 24 |
| Peak memory | 575804 kb |
| Host | smart-bda235df-cf4b-4707-84be-7c736b493ab5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2272586357 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.xbar_stress_all.2272586357 |
| Directory | /workspace/25.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/25.xbar_stress_all_with_error.25958381 |
| Short name | T1747 |
| Test name | |
| Test status | |
| Simulation time | 2681483355 ps |
| CPU time | 197.69 seconds |
| Started | Aug 12 06:49:45 PM PDT 24 |
| Finished | Aug 12 06:53:03 PM PDT 24 |
| Peak memory | 576196 kb |
| Host | smart-663be2e8-ec02-4521-a556-f790fc77bc10 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25958381 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.xbar_stress_all_with_error.25958381 |
| Directory | /workspace/25.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/25.xbar_stress_all_with_rand_reset.1464949956 |
| Short name | T2275 |
| Test name | |
| Test status | |
| Simulation time | 61676393 ps |
| CPU time | 16.8 seconds |
| Started | Aug 12 06:49:49 PM PDT 24 |
| Finished | Aug 12 06:50:05 PM PDT 24 |
| Peak memory | 574056 kb |
| Host | smart-c7583b47-4954-4443-956c-a42be5477bb0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1464949956 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.xbar_stress_all _with_rand_reset.1464949956 |
| Directory | /workspace/25.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/25.xbar_stress_all_with_reset_error.813518332 |
| Short name | T2120 |
| Test name | |
| Test status | |
| Simulation time | 1579222320 ps |
| CPU time | 136.12 seconds |
| Started | Aug 12 06:49:47 PM PDT 24 |
| Finished | Aug 12 06:52:03 PM PDT 24 |
| Peak memory | 575684 kb |
| Host | smart-ac8b2a4f-1249-4fec-9444-916aff367c1d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=813518332 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.xbar_stress_all _with_reset_error.813518332 |
| Directory | /workspace/25.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/25.xbar_unmapped_addr.214462844 |
| Short name | T1856 |
| Test name | |
| Test status | |
| Simulation time | 973540591 ps |
| CPU time | 49.83 seconds |
| Started | Aug 12 06:49:34 PM PDT 24 |
| Finished | Aug 12 06:50:24 PM PDT 24 |
| Peak memory | 575720 kb |
| Host | smart-8e21269f-4b44-4380-b7a2-97830737f6be |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=214462844 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.xbar_unmapped_addr.214462844 |
| Directory | /workspace/25.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/26.chip_tl_errors.2858048081 |
| Short name | T777 |
| Test name | |
| Test status | |
| Simulation time | 4228795826 ps |
| CPU time | 291.17 seconds |
| Started | Aug 12 06:49:49 PM PDT 24 |
| Finished | Aug 12 06:54:41 PM PDT 24 |
| Peak memory | 603356 kb |
| Host | smart-dca3d6cf-4bc3-4118-bb56-d3815febdefb |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2858048081 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.chip_tl_errors.2858048081 |
| Directory | /workspace/26.chip_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/26.xbar_access_same_device.2305534768 |
| Short name | T1857 |
| Test name | |
| Test status | |
| Simulation time | 2767335257 ps |
| CPU time | 101.66 seconds |
| Started | Aug 12 06:49:47 PM PDT 24 |
| Finished | Aug 12 06:51:29 PM PDT 24 |
| Peak memory | 575732 kb |
| Host | smart-10f2bf81-054e-4832-b720-550505f4c1a3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2305534768 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.xbar_access_same_device .2305534768 |
| Directory | /workspace/26.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/26.xbar_access_same_device_slow_rsp.775322182 |
| Short name | T929 |
| Test name | |
| Test status | |
| Simulation time | 91809036219 ps |
| CPU time | 1525.15 seconds |
| Started | Aug 12 06:49:48 PM PDT 24 |
| Finished | Aug 12 07:15:14 PM PDT 24 |
| Peak memory | 575772 kb |
| Host | smart-6e35181d-e2d8-41b4-8962-744246b35726 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=775322182 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.xbar_access_same_d evice_slow_rsp.775322182 |
| Directory | /workspace/26.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/26.xbar_error_and_unmapped_addr.2645143239 |
| Short name | T2519 |
| Test name | |
| Test status | |
| Simulation time | 20015852 ps |
| CPU time | 5.14 seconds |
| Started | Aug 12 06:49:55 PM PDT 24 |
| Finished | Aug 12 06:50:00 PM PDT 24 |
| Peak memory | 573632 kb |
| Host | smart-9213a0fb-6cef-49a3-b23f-623ea032daa4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2645143239 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.xbar_error_and_unmapped_add r.2645143239 |
| Directory | /workspace/26.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/26.xbar_error_random.3112549067 |
| Short name | T2942 |
| Test name | |
| Test status | |
| Simulation time | 217946281 ps |
| CPU time | 18.02 seconds |
| Started | Aug 12 06:49:44 PM PDT 24 |
| Finished | Aug 12 06:50:02 PM PDT 24 |
| Peak memory | 575784 kb |
| Host | smart-9185f797-a0cf-41b9-8462-697bfbc3b2c9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3112549067 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.xbar_error_random.3112549067 |
| Directory | /workspace/26.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/26.xbar_random.4242788936 |
| Short name | T2837 |
| Test name | |
| Test status | |
| Simulation time | 471837106 ps |
| CPU time | 39.4 seconds |
| Started | Aug 12 06:49:44 PM PDT 24 |
| Finished | Aug 12 06:50:24 PM PDT 24 |
| Peak memory | 575536 kb |
| Host | smart-34c902d8-5698-4c15-90dd-db353bc51d54 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4242788936 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.xbar_random.4242788936 |
| Directory | /workspace/26.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/26.xbar_random_large_delays.479314558 |
| Short name | T651 |
| Test name | |
| Test status | |
| Simulation time | 17443456587 ps |
| CPU time | 168.31 seconds |
| Started | Aug 12 06:49:49 PM PDT 24 |
| Finished | Aug 12 06:52:38 PM PDT 24 |
| Peak memory | 575744 kb |
| Host | smart-9659c447-6d20-445d-99a4-10e012ead048 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=479314558 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.xbar_random_large_delays.479314558 |
| Directory | /workspace/26.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/26.xbar_random_slow_rsp.3655636570 |
| Short name | T2042 |
| Test name | |
| Test status | |
| Simulation time | 21626142436 ps |
| CPU time | 380.26 seconds |
| Started | Aug 12 06:49:55 PM PDT 24 |
| Finished | Aug 12 06:56:16 PM PDT 24 |
| Peak memory | 575748 kb |
| Host | smart-025beb4d-9139-4efe-be3b-eda623504db1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3655636570 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.xbar_random_slow_rsp.3655636570 |
| Directory | /workspace/26.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/26.xbar_random_zero_delays.3335160326 |
| Short name | T2372 |
| Test name | |
| Test status | |
| Simulation time | 382262032 ps |
| CPU time | 28.52 seconds |
| Started | Aug 12 06:49:46 PM PDT 24 |
| Finished | Aug 12 06:50:15 PM PDT 24 |
| Peak memory | 575696 kb |
| Host | smart-c81ff963-bf98-458b-9051-7152ad3d16bf |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3335160326 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.xbar_random_zero_del ays.3335160326 |
| Directory | /workspace/26.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/26.xbar_same_source.178924894 |
| Short name | T2140 |
| Test name | |
| Test status | |
| Simulation time | 43527843 ps |
| CPU time | 6.08 seconds |
| Started | Aug 12 06:49:45 PM PDT 24 |
| Finished | Aug 12 06:49:51 PM PDT 24 |
| Peak memory | 573624 kb |
| Host | smart-f227690c-125a-464f-9e69-c783b03c5998 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=178924894 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.xbar_same_source.178924894 |
| Directory | /workspace/26.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/26.xbar_smoke.349490100 |
| Short name | T1495 |
| Test name | |
| Test status | |
| Simulation time | 40974702 ps |
| CPU time | 5.74 seconds |
| Started | Aug 12 06:49:44 PM PDT 24 |
| Finished | Aug 12 06:49:50 PM PDT 24 |
| Peak memory | 573500 kb |
| Host | smart-c87a6e9d-16a8-4b6d-b26e-062d69c3a224 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=349490100 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.xbar_smoke.349490100 |
| Directory | /workspace/26.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/26.xbar_smoke_large_delays.1954550699 |
| Short name | T1894 |
| Test name | |
| Test status | |
| Simulation time | 5715875110 ps |
| CPU time | 56.49 seconds |
| Started | Aug 12 06:49:48 PM PDT 24 |
| Finished | Aug 12 06:50:45 PM PDT 24 |
| Peak memory | 574332 kb |
| Host | smart-c76b13b9-50b9-48d9-8db7-b19aabbd9878 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1954550699 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.xbar_smoke_large_delays.1954550699 |
| Directory | /workspace/26.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/26.xbar_smoke_slow_rsp.1078580957 |
| Short name | T2281 |
| Test name | |
| Test status | |
| Simulation time | 4247948553 ps |
| CPU time | 70.13 seconds |
| Started | Aug 12 06:49:48 PM PDT 24 |
| Finished | Aug 12 06:50:58 PM PDT 24 |
| Peak memory | 574336 kb |
| Host | smart-407ccee6-2e5d-411a-b8ee-9f6450b6e69d |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1078580957 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.xbar_smoke_slow_rsp.1078580957 |
| Directory | /workspace/26.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/26.xbar_smoke_zero_delays.658130386 |
| Short name | T1999 |
| Test name | |
| Test status | |
| Simulation time | 52217537 ps |
| CPU time | 6.87 seconds |
| Started | Aug 12 06:49:47 PM PDT 24 |
| Finished | Aug 12 06:49:54 PM PDT 24 |
| Peak memory | 573640 kb |
| Host | smart-63ecbd9f-f6dd-4599-816e-beeff9a41a6b |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=658130386 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.xbar_smoke_zero_delays .658130386 |
| Directory | /workspace/26.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/26.xbar_stress_all.2691678485 |
| Short name | T716 |
| Test name | |
| Test status | |
| Simulation time | 1075072768 ps |
| CPU time | 85.73 seconds |
| Started | Aug 12 06:49:59 PM PDT 24 |
| Finished | Aug 12 06:51:25 PM PDT 24 |
| Peak memory | 575804 kb |
| Host | smart-ae311c34-da31-4dab-9cd7-23f2d6ceb4ae |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2691678485 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.xbar_stress_all.2691678485 |
| Directory | /workspace/26.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/26.xbar_stress_all_with_error.2286169363 |
| Short name | T2801 |
| Test name | |
| Test status | |
| Simulation time | 1717130554 ps |
| CPU time | 49.81 seconds |
| Started | Aug 12 06:49:55 PM PDT 24 |
| Finished | Aug 12 06:50:45 PM PDT 24 |
| Peak memory | 575720 kb |
| Host | smart-091f6c0b-e118-4b22-9a66-b88ee7dc9236 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2286169363 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.xbar_stress_all_with_error.2286169363 |
| Directory | /workspace/26.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/26.xbar_stress_all_with_rand_reset.2429654188 |
| Short name | T1571 |
| Test name | |
| Test status | |
| Simulation time | 7886150 ps |
| CPU time | 7.18 seconds |
| Started | Aug 12 06:49:55 PM PDT 24 |
| Finished | Aug 12 06:50:03 PM PDT 24 |
| Peak memory | 573632 kb |
| Host | smart-17e76fbd-69b9-4768-b3f6-362a4dc1cc55 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2429654188 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.xbar_stress_all _with_rand_reset.2429654188 |
| Directory | /workspace/26.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/26.xbar_stress_all_with_reset_error.480355662 |
| Short name | T2740 |
| Test name | |
| Test status | |
| Simulation time | 1191150012 ps |
| CPU time | 260.7 seconds |
| Started | Aug 12 06:49:59 PM PDT 24 |
| Finished | Aug 12 06:54:20 PM PDT 24 |
| Peak memory | 576588 kb |
| Host | smart-7b9e3199-0f8a-4d42-bf0b-eb42818a4464 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=480355662 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.xbar_stress_all _with_reset_error.480355662 |
| Directory | /workspace/26.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/26.xbar_unmapped_addr.4098754708 |
| Short name | T2860 |
| Test name | |
| Test status | |
| Simulation time | 138095767 ps |
| CPU time | 18.33 seconds |
| Started | Aug 12 06:49:49 PM PDT 24 |
| Finished | Aug 12 06:50:08 PM PDT 24 |
| Peak memory | 575588 kb |
| Host | smart-af89bfe9-890b-4527-95f7-d480ebf048a9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4098754708 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.xbar_unmapped_addr.4098754708 |
| Directory | /workspace/26.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/27.chip_tl_errors.1183087490 |
| Short name | T770 |
| Test name | |
| Test status | |
| Simulation time | 3769882948 ps |
| CPU time | 242.19 seconds |
| Started | Aug 12 06:49:55 PM PDT 24 |
| Finished | Aug 12 06:53:58 PM PDT 24 |
| Peak memory | 603304 kb |
| Host | smart-bffab5a4-dd8b-469e-80a4-608d35044104 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1183087490 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.chip_tl_errors.1183087490 |
| Directory | /workspace/27.chip_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/27.xbar_access_same_device.3827229331 |
| Short name | T2066 |
| Test name | |
| Test status | |
| Simulation time | 756594876 ps |
| CPU time | 50.73 seconds |
| Started | Aug 12 06:49:57 PM PDT 24 |
| Finished | Aug 12 06:50:48 PM PDT 24 |
| Peak memory | 575736 kb |
| Host | smart-7cbbdd9e-7ee8-4660-85ef-f9ee946c3173 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3827229331 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.xbar_access_same_device .3827229331 |
| Directory | /workspace/27.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/27.xbar_access_same_device_slow_rsp.1399468247 |
| Short name | T2103 |
| Test name | |
| Test status | |
| Simulation time | 92387322163 ps |
| CPU time | 1674.05 seconds |
| Started | Aug 12 06:49:56 PM PDT 24 |
| Finished | Aug 12 07:17:51 PM PDT 24 |
| Peak memory | 575784 kb |
| Host | smart-ee58de4f-153e-48ca-b28b-f6f79c654bc1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1399468247 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.xbar_access_same_ device_slow_rsp.1399468247 |
| Directory | /workspace/27.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/27.xbar_error_and_unmapped_addr.1346049878 |
| Short name | T1512 |
| Test name | |
| Test status | |
| Simulation time | 1349874457 ps |
| CPU time | 46.23 seconds |
| Started | Aug 12 06:49:59 PM PDT 24 |
| Finished | Aug 12 06:50:45 PM PDT 24 |
| Peak memory | 575780 kb |
| Host | smart-ec69fafe-6bfd-4a60-8fca-4933aecfc6af |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1346049878 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.xbar_error_and_unmapped_add r.1346049878 |
| Directory | /workspace/27.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/27.xbar_error_random.3237522938 |
| Short name | T2012 |
| Test name | |
| Test status | |
| Simulation time | 259368508 ps |
| CPU time | 11.49 seconds |
| Started | Aug 12 06:49:57 PM PDT 24 |
| Finished | Aug 12 06:50:08 PM PDT 24 |
| Peak memory | 575552 kb |
| Host | smart-ecdb7bdf-d74f-41f9-8cfb-13d649fe392c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3237522938 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.xbar_error_random.3237522938 |
| Directory | /workspace/27.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/27.xbar_random.3497973115 |
| Short name | T698 |
| Test name | |
| Test status | |
| Simulation time | 158640872 ps |
| CPU time | 17.43 seconds |
| Started | Aug 12 06:49:57 PM PDT 24 |
| Finished | Aug 12 06:50:15 PM PDT 24 |
| Peak memory | 575712 kb |
| Host | smart-d70f7c3f-0764-4f86-9460-cadc477156bc |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3497973115 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.xbar_random.3497973115 |
| Directory | /workspace/27.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/27.xbar_random_large_delays.271700117 |
| Short name | T1884 |
| Test name | |
| Test status | |
| Simulation time | 55568846303 ps |
| CPU time | 560.09 seconds |
| Started | Aug 12 06:50:01 PM PDT 24 |
| Finished | Aug 12 06:59:22 PM PDT 24 |
| Peak memory | 575596 kb |
| Host | smart-646e29bc-ac00-437d-973a-b48ebeb32451 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=271700117 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.xbar_random_large_delays.271700117 |
| Directory | /workspace/27.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/27.xbar_random_slow_rsp.1819298823 |
| Short name | T1974 |
| Test name | |
| Test status | |
| Simulation time | 20514785016 ps |
| CPU time | 349.68 seconds |
| Started | Aug 12 06:49:58 PM PDT 24 |
| Finished | Aug 12 06:55:47 PM PDT 24 |
| Peak memory | 575608 kb |
| Host | smart-0062b912-28c0-44b2-b042-1e282f5cfc47 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1819298823 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.xbar_random_slow_rsp.1819298823 |
| Directory | /workspace/27.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/27.xbar_random_zero_delays.1768681855 |
| Short name | T659 |
| Test name | |
| Test status | |
| Simulation time | 273521766 ps |
| CPU time | 29.07 seconds |
| Started | Aug 12 06:49:57 PM PDT 24 |
| Finished | Aug 12 06:50:26 PM PDT 24 |
| Peak memory | 575552 kb |
| Host | smart-f5f91d57-ca53-40d6-945d-af3159dc9a04 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1768681855 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.xbar_random_zero_del ays.1768681855 |
| Directory | /workspace/27.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/27.xbar_same_source.131392363 |
| Short name | T2478 |
| Test name | |
| Test status | |
| Simulation time | 83789824 ps |
| CPU time | 9.21 seconds |
| Started | Aug 12 06:50:01 PM PDT 24 |
| Finished | Aug 12 06:50:10 PM PDT 24 |
| Peak memory | 575472 kb |
| Host | smart-9c05ce78-7426-4042-8ac7-92ac70ba0069 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=131392363 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.xbar_same_source.131392363 |
| Directory | /workspace/27.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/27.xbar_smoke.3531872609 |
| Short name | T2473 |
| Test name | |
| Test status | |
| Simulation time | 200633340 ps |
| CPU time | 9.55 seconds |
| Started | Aug 12 06:49:57 PM PDT 24 |
| Finished | Aug 12 06:50:06 PM PDT 24 |
| Peak memory | 573452 kb |
| Host | smart-f099e5e1-66de-457c-8129-dea4dfba5a6d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3531872609 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.xbar_smoke.3531872609 |
| Directory | /workspace/27.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/27.xbar_smoke_large_delays.470960038 |
| Short name | T658 |
| Test name | |
| Test status | |
| Simulation time | 9935763212 ps |
| CPU time | 96.07 seconds |
| Started | Aug 12 06:49:55 PM PDT 24 |
| Finished | Aug 12 06:51:32 PM PDT 24 |
| Peak memory | 573740 kb |
| Host | smart-ebff9c08-1263-4da0-a8f0-c3f977b9d1aa |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=470960038 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.xbar_smoke_large_delays.470960038 |
| Directory | /workspace/27.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/27.xbar_smoke_slow_rsp.4198931824 |
| Short name | T643 |
| Test name | |
| Test status | |
| Simulation time | 4842225505 ps |
| CPU time | 81.97 seconds |
| Started | Aug 12 06:49:57 PM PDT 24 |
| Finished | Aug 12 06:51:19 PM PDT 24 |
| Peak memory | 574376 kb |
| Host | smart-84d3c07e-9dfb-4ff9-89bb-b674ba99083d |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4198931824 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.xbar_smoke_slow_rsp.4198931824 |
| Directory | /workspace/27.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/27.xbar_smoke_zero_delays.1254143446 |
| Short name | T2663 |
| Test name | |
| Test status | |
| Simulation time | 51764905 ps |
| CPU time | 6.87 seconds |
| Started | Aug 12 06:49:57 PM PDT 24 |
| Finished | Aug 12 06:50:04 PM PDT 24 |
| Peak memory | 573600 kb |
| Host | smart-c20445d0-8afc-40a8-bb43-db663164cf2b |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1254143446 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.xbar_smoke_zero_delay s.1254143446 |
| Directory | /workspace/27.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/27.xbar_stress_all.706321609 |
| Short name | T2623 |
| Test name | |
| Test status | |
| Simulation time | 2346683485 ps |
| CPU time | 190.1 seconds |
| Started | Aug 12 06:50:01 PM PDT 24 |
| Finished | Aug 12 06:53:12 PM PDT 24 |
| Peak memory | 575712 kb |
| Host | smart-c23bcf5b-87c4-42b3-ad5c-af8a4b38b513 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=706321609 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.xbar_stress_all.706321609 |
| Directory | /workspace/27.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/27.xbar_stress_all_with_error.3643180163 |
| Short name | T2932 |
| Test name | |
| Test status | |
| Simulation time | 1562552376 ps |
| CPU time | 119.21 seconds |
| Started | Aug 12 06:50:01 PM PDT 24 |
| Finished | Aug 12 06:52:01 PM PDT 24 |
| Peak memory | 575896 kb |
| Host | smart-be94bde2-7106-467f-acf1-e2e685a05f4e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3643180163 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.xbar_stress_all_with_error.3643180163 |
| Directory | /workspace/27.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/27.xbar_stress_all_with_rand_reset.3269333242 |
| Short name | T2833 |
| Test name | |
| Test status | |
| Simulation time | 758813468 ps |
| CPU time | 206.28 seconds |
| Started | Aug 12 06:50:02 PM PDT 24 |
| Finished | Aug 12 06:53:28 PM PDT 24 |
| Peak memory | 575760 kb |
| Host | smart-7c9646f9-2947-4ba8-bf89-064e911e5028 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3269333242 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.xbar_stress_all _with_rand_reset.3269333242 |
| Directory | /workspace/27.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/27.xbar_stress_all_with_reset_error.3708242052 |
| Short name | T901 |
| Test name | |
| Test status | |
| Simulation time | 6779683590 ps |
| CPU time | 435.07 seconds |
| Started | Aug 12 06:50:00 PM PDT 24 |
| Finished | Aug 12 06:57:15 PM PDT 24 |
| Peak memory | 576564 kb |
| Host | smart-088ccbf6-7f80-4ffc-9204-d9a0e1ee40d6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3708242052 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.xbar_stress_al l_with_reset_error.3708242052 |
| Directory | /workspace/27.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/27.xbar_unmapped_addr.4265476189 |
| Short name | T725 |
| Test name | |
| Test status | |
| Simulation time | 299443991 ps |
| CPU time | 31.72 seconds |
| Started | Aug 12 06:50:01 PM PDT 24 |
| Finished | Aug 12 06:50:33 PM PDT 24 |
| Peak memory | 575560 kb |
| Host | smart-de9b844c-92f9-478a-9b0a-eed449c80144 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4265476189 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.xbar_unmapped_addr.4265476189 |
| Directory | /workspace/27.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/28.chip_tl_errors.3717650373 |
| Short name | T2885 |
| Test name | |
| Test status | |
| Simulation time | 3752088490 ps |
| CPU time | 243.32 seconds |
| Started | Aug 12 06:49:56 PM PDT 24 |
| Finished | Aug 12 06:53:59 PM PDT 24 |
| Peak memory | 598484 kb |
| Host | smart-a53ca3a4-cb41-47be-aa0d-0f45cd14b169 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3717650373 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.chip_tl_errors.3717650373 |
| Directory | /workspace/28.chip_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/28.xbar_access_same_device.4111341795 |
| Short name | T1867 |
| Test name | |
| Test status | |
| Simulation time | 709710453 ps |
| CPU time | 72.34 seconds |
| Started | Aug 12 06:50:04 PM PDT 24 |
| Finished | Aug 12 06:51:17 PM PDT 24 |
| Peak memory | 575636 kb |
| Host | smart-759f53e5-7cc0-49ca-9cb9-3f9655d50107 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4111341795 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.xbar_access_same_device .4111341795 |
| Directory | /workspace/28.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/28.xbar_access_same_device_slow_rsp.1984809288 |
| Short name | T936 |
| Test name | |
| Test status | |
| Simulation time | 51963073610 ps |
| CPU time | 959.92 seconds |
| Started | Aug 12 06:50:09 PM PDT 24 |
| Finished | Aug 12 07:06:09 PM PDT 24 |
| Peak memory | 575688 kb |
| Host | smart-b83bbdbe-0b28-4531-bf19-2fe65ee9307e |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1984809288 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.xbar_access_same_ device_slow_rsp.1984809288 |
| Directory | /workspace/28.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/28.xbar_error_and_unmapped_addr.2776690682 |
| Short name | T2318 |
| Test name | |
| Test status | |
| Simulation time | 776038529 ps |
| CPU time | 35.82 seconds |
| Started | Aug 12 06:50:14 PM PDT 24 |
| Finished | Aug 12 06:50:50 PM PDT 24 |
| Peak memory | 575664 kb |
| Host | smart-c964a69b-91b3-4257-bebf-00ad6ecf8df7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2776690682 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.xbar_error_and_unmapped_add r.2776690682 |
| Directory | /workspace/28.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/28.xbar_error_random.3473260255 |
| Short name | T2504 |
| Test name | |
| Test status | |
| Simulation time | 347110063 ps |
| CPU time | 26.43 seconds |
| Started | Aug 12 06:50:05 PM PDT 24 |
| Finished | Aug 12 06:50:32 PM PDT 24 |
| Peak memory | 575752 kb |
| Host | smart-1739891b-1fc3-4ba6-8f95-d98e2ec7031a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3473260255 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.xbar_error_random.3473260255 |
| Directory | /workspace/28.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/28.xbar_random.2674716838 |
| Short name | T2622 |
| Test name | |
| Test status | |
| Simulation time | 1881699183 ps |
| CPU time | 64.96 seconds |
| Started | Aug 12 06:50:07 PM PDT 24 |
| Finished | Aug 12 06:51:12 PM PDT 24 |
| Peak memory | 575764 kb |
| Host | smart-7e310fd2-20b7-4e4e-a53f-b08798c66225 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2674716838 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.xbar_random.2674716838 |
| Directory | /workspace/28.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/28.xbar_random_large_delays.3417251354 |
| Short name | T714 |
| Test name | |
| Test status | |
| Simulation time | 25282964144 ps |
| CPU time | 268.27 seconds |
| Started | Aug 12 06:50:06 PM PDT 24 |
| Finished | Aug 12 06:54:35 PM PDT 24 |
| Peak memory | 575820 kb |
| Host | smart-8281edc0-13d8-4e19-a4d9-74863c199438 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3417251354 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.xbar_random_large_delays.3417251354 |
| Directory | /workspace/28.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/28.xbar_random_slow_rsp.2131418957 |
| Short name | T1715 |
| Test name | |
| Test status | |
| Simulation time | 3346367786 ps |
| CPU time | 51.05 seconds |
| Started | Aug 12 06:50:07 PM PDT 24 |
| Finished | Aug 12 06:50:58 PM PDT 24 |
| Peak memory | 574364 kb |
| Host | smart-b82e5f0c-20e7-4ea1-8d7d-101c1da1133f |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2131418957 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.xbar_random_slow_rsp.2131418957 |
| Directory | /workspace/28.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/28.xbar_random_zero_delays.1203180973 |
| Short name | T2538 |
| Test name | |
| Test status | |
| Simulation time | 189848987 ps |
| CPU time | 16.67 seconds |
| Started | Aug 12 06:50:10 PM PDT 24 |
| Finished | Aug 12 06:50:27 PM PDT 24 |
| Peak memory | 575656 kb |
| Host | smart-a4473e70-1f75-4079-8074-c0406ed5916d |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1203180973 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.xbar_random_zero_del ays.1203180973 |
| Directory | /workspace/28.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/28.xbar_same_source.4196464087 |
| Short name | T2313 |
| Test name | |
| Test status | |
| Simulation time | 349091992 ps |
| CPU time | 11.6 seconds |
| Started | Aug 12 06:50:09 PM PDT 24 |
| Finished | Aug 12 06:50:20 PM PDT 24 |
| Peak memory | 575484 kb |
| Host | smart-bcf14fc1-197b-41ae-b596-41c88207ae3e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4196464087 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.xbar_same_source.4196464087 |
| Directory | /workspace/28.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/28.xbar_smoke.2638984417 |
| Short name | T2900 |
| Test name | |
| Test status | |
| Simulation time | 211576553 ps |
| CPU time | 9.48 seconds |
| Started | Aug 12 06:49:59 PM PDT 24 |
| Finished | Aug 12 06:50:09 PM PDT 24 |
| Peak memory | 573500 kb |
| Host | smart-c0c38022-d3b5-455b-9eb9-21db759127c3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2638984417 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.xbar_smoke.2638984417 |
| Directory | /workspace/28.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/28.xbar_smoke_large_delays.2098822248 |
| Short name | T2257 |
| Test name | |
| Test status | |
| Simulation time | 7374696874 ps |
| CPU time | 75.93 seconds |
| Started | Aug 12 06:50:04 PM PDT 24 |
| Finished | Aug 12 06:51:21 PM PDT 24 |
| Peak memory | 574352 kb |
| Host | smart-4eb9596f-a2bf-4342-83a5-49604f1432b6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2098822248 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.xbar_smoke_large_delays.2098822248 |
| Directory | /workspace/28.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/28.xbar_smoke_slow_rsp.652675339 |
| Short name | T1937 |
| Test name | |
| Test status | |
| Simulation time | 5253378995 ps |
| CPU time | 87.89 seconds |
| Started | Aug 12 06:50:06 PM PDT 24 |
| Finished | Aug 12 06:51:34 PM PDT 24 |
| Peak memory | 573640 kb |
| Host | smart-79d4d2ea-2860-4f68-9980-da3199494807 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=652675339 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.xbar_smoke_slow_rsp.652675339 |
| Directory | /workspace/28.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/28.xbar_smoke_zero_delays.2128295715 |
| Short name | T2159 |
| Test name | |
| Test status | |
| Simulation time | 50880696 ps |
| CPU time | 6.32 seconds |
| Started | Aug 12 06:50:06 PM PDT 24 |
| Finished | Aug 12 06:50:13 PM PDT 24 |
| Peak memory | 573580 kb |
| Host | smart-e46c975f-cbc0-4737-b128-801bf674c523 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2128295715 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.xbar_smoke_zero_delay s.2128295715 |
| Directory | /workspace/28.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/28.xbar_stress_all.4138398119 |
| Short name | T702 |
| Test name | |
| Test status | |
| Simulation time | 7468560364 ps |
| CPU time | 281.17 seconds |
| Started | Aug 12 06:50:16 PM PDT 24 |
| Finished | Aug 12 06:54:57 PM PDT 24 |
| Peak memory | 576452 kb |
| Host | smart-40d410b0-6451-4d6f-9bac-89cc48d7745e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4138398119 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.xbar_stress_all.4138398119 |
| Directory | /workspace/28.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/28.xbar_stress_all_with_error.2926568841 |
| Short name | T1508 |
| Test name | |
| Test status | |
| Simulation time | 17345437041 ps |
| CPU time | 560.05 seconds |
| Started | Aug 12 06:50:17 PM PDT 24 |
| Finished | Aug 12 06:59:37 PM PDT 24 |
| Peak memory | 576572 kb |
| Host | smart-e30a5d6c-a89b-4ab2-bcaf-8d9b7e476f2a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2926568841 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.xbar_stress_all_with_error.2926568841 |
| Directory | /workspace/28.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/28.xbar_stress_all_with_rand_reset.3780667580 |
| Short name | T2428 |
| Test name | |
| Test status | |
| Simulation time | 217934967 ps |
| CPU time | 34.08 seconds |
| Started | Aug 12 06:50:16 PM PDT 24 |
| Finished | Aug 12 06:50:51 PM PDT 24 |
| Peak memory | 575664 kb |
| Host | smart-bc4ac8b7-b3a9-4ef9-9661-2d0b1bdbff89 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3780667580 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.xbar_stress_all _with_rand_reset.3780667580 |
| Directory | /workspace/28.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/28.xbar_stress_all_with_reset_error.4081800673 |
| Short name | T2079 |
| Test name | |
| Test status | |
| Simulation time | 1752105850 ps |
| CPU time | 293.48 seconds |
| Started | Aug 12 06:50:17 PM PDT 24 |
| Finished | Aug 12 06:55:10 PM PDT 24 |
| Peak memory | 576532 kb |
| Host | smart-eecd24bf-1bd4-4889-bf10-7c862b288121 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4081800673 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.xbar_stress_al l_with_reset_error.4081800673 |
| Directory | /workspace/28.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/28.xbar_unmapped_addr.505449621 |
| Short name | T2209 |
| Test name | |
| Test status | |
| Simulation time | 412228045 ps |
| CPU time | 17.64 seconds |
| Started | Aug 12 06:50:06 PM PDT 24 |
| Finished | Aug 12 06:50:24 PM PDT 24 |
| Peak memory | 575728 kb |
| Host | smart-4301fed0-06b5-4e91-b91f-e365038f6962 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=505449621 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.xbar_unmapped_addr.505449621 |
| Directory | /workspace/28.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/29.chip_tl_errors.2670569820 |
| Short name | T708 |
| Test name | |
| Test status | |
| Simulation time | 2565920400 ps |
| CPU time | 131.02 seconds |
| Started | Aug 12 06:50:16 PM PDT 24 |
| Finished | Aug 12 06:52:27 PM PDT 24 |
| Peak memory | 598168 kb |
| Host | smart-1f05bcfc-9f41-4948-8181-7f4fb939a9df |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2670569820 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.chip_tl_errors.2670569820 |
| Directory | /workspace/29.chip_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/29.xbar_access_same_device.1037164537 |
| Short name | T2887 |
| Test name | |
| Test status | |
| Simulation time | 2806417737 ps |
| CPU time | 111.91 seconds |
| Started | Aug 12 06:50:19 PM PDT 24 |
| Finished | Aug 12 06:52:11 PM PDT 24 |
| Peak memory | 575612 kb |
| Host | smart-90eb4484-c6f7-4749-9438-1a117af0948b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1037164537 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.xbar_access_same_device .1037164537 |
| Directory | /workspace/29.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/29.xbar_access_same_device_slow_rsp.965297551 |
| Short name | T1805 |
| Test name | |
| Test status | |
| Simulation time | 36208785755 ps |
| CPU time | 606.69 seconds |
| Started | Aug 12 06:50:15 PM PDT 24 |
| Finished | Aug 12 07:00:22 PM PDT 24 |
| Peak memory | 575620 kb |
| Host | smart-3a082f63-241d-404f-8f0f-fe9b82492b54 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=965297551 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.xbar_access_same_d evice_slow_rsp.965297551 |
| Directory | /workspace/29.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/29.xbar_error_and_unmapped_addr.3254246606 |
| Short name | T2707 |
| Test name | |
| Test status | |
| Simulation time | 349561709 ps |
| CPU time | 14.91 seconds |
| Started | Aug 12 06:50:15 PM PDT 24 |
| Finished | Aug 12 06:50:30 PM PDT 24 |
| Peak memory | 575548 kb |
| Host | smart-a8a7c6d0-6a54-493b-a9bf-bdf8acd035c1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3254246606 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.xbar_error_and_unmapped_add r.3254246606 |
| Directory | /workspace/29.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/29.xbar_error_random.4118581196 |
| Short name | T2865 |
| Test name | |
| Test status | |
| Simulation time | 486290992 ps |
| CPU time | 37.78 seconds |
| Started | Aug 12 06:50:14 PM PDT 24 |
| Finished | Aug 12 06:50:52 PM PDT 24 |
| Peak memory | 575792 kb |
| Host | smart-7268f464-3916-4282-a16a-22e96983676e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4118581196 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.xbar_error_random.4118581196 |
| Directory | /workspace/29.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/29.xbar_random.4202197514 |
| Short name | T2847 |
| Test name | |
| Test status | |
| Simulation time | 156330768 ps |
| CPU time | 13.78 seconds |
| Started | Aug 12 06:50:14 PM PDT 24 |
| Finished | Aug 12 06:50:28 PM PDT 24 |
| Peak memory | 575488 kb |
| Host | smart-69cfe32b-3da2-4584-bfa3-a25917de1bae |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4202197514 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.xbar_random.4202197514 |
| Directory | /workspace/29.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/29.xbar_random_large_delays.2497692506 |
| Short name | T2445 |
| Test name | |
| Test status | |
| Simulation time | 102575026613 ps |
| CPU time | 1132.34 seconds |
| Started | Aug 12 06:50:16 PM PDT 24 |
| Finished | Aug 12 07:09:08 PM PDT 24 |
| Peak memory | 575780 kb |
| Host | smart-3a7a100a-1206-45e0-8d89-7b11f724fd4c |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2497692506 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.xbar_random_large_delays.2497692506 |
| Directory | /workspace/29.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/29.xbar_random_slow_rsp.357269164 |
| Short name | T740 |
| Test name | |
| Test status | |
| Simulation time | 20810753501 ps |
| CPU time | 366.76 seconds |
| Started | Aug 12 06:50:13 PM PDT 24 |
| Finished | Aug 12 06:56:20 PM PDT 24 |
| Peak memory | 575580 kb |
| Host | smart-b0b96e99-dbc5-413c-b684-82e29b7d1e13 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=357269164 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.xbar_random_slow_rsp.357269164 |
| Directory | /workspace/29.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/29.xbar_random_zero_delays.3436829322 |
| Short name | T2351 |
| Test name | |
| Test status | |
| Simulation time | 360638559 ps |
| CPU time | 31 seconds |
| Started | Aug 12 06:50:16 PM PDT 24 |
| Finished | Aug 12 06:50:47 PM PDT 24 |
| Peak memory | 575496 kb |
| Host | smart-f967a2ee-2834-4bdb-977a-79a7089ae178 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3436829322 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.xbar_random_zero_del ays.3436829322 |
| Directory | /workspace/29.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/29.xbar_same_source.4031222062 |
| Short name | T2302 |
| Test name | |
| Test status | |
| Simulation time | 1297804788 ps |
| CPU time | 36.36 seconds |
| Started | Aug 12 06:50:15 PM PDT 24 |
| Finished | Aug 12 06:50:51 PM PDT 24 |
| Peak memory | 575604 kb |
| Host | smart-8277b050-7321-4ffb-a09f-cbc67d2cf2b0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4031222062 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.xbar_same_source.4031222062 |
| Directory | /workspace/29.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/29.xbar_smoke.1903030835 |
| Short name | T1721 |
| Test name | |
| Test status | |
| Simulation time | 211599028 ps |
| CPU time | 9.15 seconds |
| Started | Aug 12 06:50:16 PM PDT 24 |
| Finished | Aug 12 06:50:25 PM PDT 24 |
| Peak memory | 573560 kb |
| Host | smart-e8dacf44-0d9d-481f-83b7-f3f8893890b0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1903030835 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.xbar_smoke.1903030835 |
| Directory | /workspace/29.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/29.xbar_smoke_large_delays.3749810223 |
| Short name | T2278 |
| Test name | |
| Test status | |
| Simulation time | 7972110156 ps |
| CPU time | 82.1 seconds |
| Started | Aug 12 06:50:17 PM PDT 24 |
| Finished | Aug 12 06:51:40 PM PDT 24 |
| Peak memory | 573592 kb |
| Host | smart-e3d549f4-776d-4364-b109-91d856afaffd |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3749810223 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.xbar_smoke_large_delays.3749810223 |
| Directory | /workspace/29.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/29.xbar_smoke_slow_rsp.2329201108 |
| Short name | T2513 |
| Test name | |
| Test status | |
| Simulation time | 4102101577 ps |
| CPU time | 70.92 seconds |
| Started | Aug 12 06:50:14 PM PDT 24 |
| Finished | Aug 12 06:51:25 PM PDT 24 |
| Peak memory | 573616 kb |
| Host | smart-57dceaba-ef45-4ac4-8a23-df3a19c80716 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2329201108 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.xbar_smoke_slow_rsp.2329201108 |
| Directory | /workspace/29.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/29.xbar_smoke_zero_delays.945702661 |
| Short name | T1698 |
| Test name | |
| Test status | |
| Simulation time | 52409804 ps |
| CPU time | 6.48 seconds |
| Started | Aug 12 06:50:17 PM PDT 24 |
| Finished | Aug 12 06:50:24 PM PDT 24 |
| Peak memory | 573512 kb |
| Host | smart-c352ed12-50b2-49ec-84a3-790d024d7729 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=945702661 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.xbar_smoke_zero_delays .945702661 |
| Directory | /workspace/29.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/29.xbar_stress_all_with_rand_reset.1682351714 |
| Short name | T609 |
| Test name | |
| Test status | |
| Simulation time | 6907016978 ps |
| CPU time | 380.93 seconds |
| Started | Aug 12 06:50:15 PM PDT 24 |
| Finished | Aug 12 06:56:37 PM PDT 24 |
| Peak memory | 575816 kb |
| Host | smart-ceee6e9b-6b3d-4dca-94a0-ea5be9cef63e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1682351714 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.xbar_stress_all _with_rand_reset.1682351714 |
| Directory | /workspace/29.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/29.xbar_stress_all_with_reset_error.2031647825 |
| Short name | T2461 |
| Test name | |
| Test status | |
| Simulation time | 4710982915 ps |
| CPU time | 245.49 seconds |
| Started | Aug 12 06:50:27 PM PDT 24 |
| Finished | Aug 12 06:54:33 PM PDT 24 |
| Peak memory | 576596 kb |
| Host | smart-a6701b7d-96cc-4847-95b1-04bbcac75e18 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2031647825 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.xbar_stress_al l_with_reset_error.2031647825 |
| Directory | /workspace/29.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/29.xbar_unmapped_addr.1212206509 |
| Short name | T2236 |
| Test name | |
| Test status | |
| Simulation time | 272828605 ps |
| CPU time | 15.31 seconds |
| Started | Aug 12 06:50:13 PM PDT 24 |
| Finished | Aug 12 06:50:29 PM PDT 24 |
| Peak memory | 575728 kb |
| Host | smart-d3d2106f-20c8-41b9-8d06-b57114aa9c19 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1212206509 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.xbar_unmapped_addr.1212206509 |
| Directory | /workspace/29.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/3.chip_csr_aliasing.133940071 |
| Short name | T419 |
| Test name | |
| Test status | |
| Simulation time | 33594314258 ps |
| CPU time | 5156.88 seconds |
| Started | Aug 12 06:47:17 PM PDT 24 |
| Finished | Aug 12 08:13:15 PM PDT 24 |
| Peak memory | 593768 kb |
| Host | smart-3c7a5c7f-18aa-4e03-99f1-ab0289744608 |
| User | root |
| Command | /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +csr_aliasing +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=133940071 -assert nopostproc +UVM_TESTNAME=chip_b ase_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/n ull -cm_name 3.chip_csr_aliasing.133940071 |
| Directory | /workspace/3.chip_csr_aliasing/latest |
| Test location | /workspace/coverage/cover_reg_top/3.chip_csr_bit_bash.1582959706 |
| Short name | T2585 |
| Test name | |
| Test status | |
| Simulation time | 61484981263 ps |
| CPU time | 6005.08 seconds |
| Started | Aug 12 06:47:16 PM PDT 24 |
| Finished | Aug 12 08:27:21 PM PDT 24 |
| Peak memory | 592404 kb |
| Host | smart-39edd589-c6e2-49dc-a761-41c6ff690248 |
| User | root |
| Command | /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +num_test_csrs=200 +csr_bit_bash +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1582959706 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to p.vdb -cm_log /dev/null -cm_name 3.chip_csr_bit_bash.1582959706 |
| Directory | /workspace/3.chip_csr_bit_bash/latest |
| Test location | /workspace/coverage/cover_reg_top/3.chip_csr_mem_rw_with_rand_reset.1004454083 |
| Short name | T1906 |
| Test name | |
| Test status | |
| Simulation time | 7669334964 ps |
| CPU time | 464.85 seconds |
| Started | Aug 12 06:47:16 PM PDT 24 |
| Finished | Aug 12 06:55:01 PM PDT 24 |
| Peak memory | 637240 kb |
| Host | smart-66c9f9bb-265f-4b4e-8930-cb2f6994869d |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1004454083 -assert nopostproc + UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top .vdb -cm_log /dev/null -cm_name 3.chip_csr_mem_rw_with_rand_reset.1004454083 |
| Directory | /workspace/3.chip_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/3.chip_csr_rw.3169136806 |
| Short name | T1734 |
| Test name | |
| Test status | |
| Simulation time | 5486494208 ps |
| CPU time | 530.56 seconds |
| Started | Aug 12 06:47:18 PM PDT 24 |
| Finished | Aug 12 06:56:09 PM PDT 24 |
| Peak memory | 598516 kb |
| Host | smart-cab90394-8c00-4dab-9a88-3a849e337710 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3169136806 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.chip_csr_rw.3169136806 |
| Directory | /workspace/3.chip_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/3.chip_same_csr_outstanding.1856132117 |
| Short name | T2400 |
| Test name | |
| Test status | |
| Simulation time | 30526951424 ps |
| CPU time | 4515.98 seconds |
| Started | Aug 12 06:47:17 PM PDT 24 |
| Finished | Aug 12 08:02:33 PM PDT 24 |
| Peak memory | 592680 kb |
| Host | smart-0af9cdf6-b16a-415b-9f44-6f185e261f33 |
| User | root |
| Command | /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +run_same_csr_outstanding +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1856132117 -assert nopostproc +UVM_TE STNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb - cm_log /dev/null -cm_name 3.chip_same_csr_outstanding.1856132117 |
| Directory | /workspace/3.chip_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/3.chip_tl_errors.913834141 |
| Short name | T584 |
| Test name | |
| Test status | |
| Simulation time | 4074573854 ps |
| CPU time | 348.69 seconds |
| Started | Aug 12 06:47:17 PM PDT 24 |
| Finished | Aug 12 06:53:06 PM PDT 24 |
| Peak memory | 603328 kb |
| Host | smart-1cb19448-968b-4588-bb19-9bfb19e331e2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=913834141 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.chip_tl_errors.913834141 |
| Directory | /workspace/3.chip_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/3.xbar_access_same_device.778517644 |
| Short name | T2661 |
| Test name | |
| Test status | |
| Simulation time | 885649429 ps |
| CPU time | 33.5 seconds |
| Started | Aug 12 06:47:14 PM PDT 24 |
| Finished | Aug 12 06:47:48 PM PDT 24 |
| Peak memory | 575608 kb |
| Host | smart-a764c985-b83c-477f-bd60-81bf190bcea6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=778517644 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.xbar_access_same_device.778517644 |
| Directory | /workspace/3.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/3.xbar_access_same_device_slow_rsp.270010935 |
| Short name | T2712 |
| Test name | |
| Test status | |
| Simulation time | 74821517113 ps |
| CPU time | 1320.79 seconds |
| Started | Aug 12 06:47:14 PM PDT 24 |
| Finished | Aug 12 07:09:15 PM PDT 24 |
| Peak memory | 575844 kb |
| Host | smart-e984a466-d7de-4cce-820c-24af334a9eff |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=270010935 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.xbar_access_same_de vice_slow_rsp.270010935 |
| Directory | /workspace/3.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/3.xbar_error_and_unmapped_addr.2192182796 |
| Short name | T2877 |
| Test name | |
| Test status | |
| Simulation time | 1344465698 ps |
| CPU time | 51.15 seconds |
| Started | Aug 12 06:47:16 PM PDT 24 |
| Finished | Aug 12 06:48:07 PM PDT 24 |
| Peak memory | 575528 kb |
| Host | smart-9f259bc5-6852-4d37-9e5f-fd51cb77a756 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2192182796 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.xbar_error_and_unmapped_addr .2192182796 |
| Directory | /workspace/3.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/3.xbar_error_random.2115025402 |
| Short name | T2921 |
| Test name | |
| Test status | |
| Simulation time | 106406071 ps |
| CPU time | 10.72 seconds |
| Started | Aug 12 06:47:19 PM PDT 24 |
| Finished | Aug 12 06:47:30 PM PDT 24 |
| Peak memory | 575712 kb |
| Host | smart-0ccb8069-44b1-48dc-94ed-fef1c738dd1b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2115025402 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.xbar_error_random.2115025402 |
| Directory | /workspace/3.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/3.xbar_random.583369670 |
| Short name | T1891 |
| Test name | |
| Test status | |
| Simulation time | 560340283 ps |
| CPU time | 45.97 seconds |
| Started | Aug 12 06:47:17 PM PDT 24 |
| Finished | Aug 12 06:48:03 PM PDT 24 |
| Peak memory | 575688 kb |
| Host | smart-f3ea4ac1-4085-48fb-8931-d851ac5d8056 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=583369670 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.xbar_random.583369670 |
| Directory | /workspace/3.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/3.xbar_random_large_delays.1527670769 |
| Short name | T1638 |
| Test name | |
| Test status | |
| Simulation time | 57766950936 ps |
| CPU time | 582.79 seconds |
| Started | Aug 12 06:47:20 PM PDT 24 |
| Finished | Aug 12 06:57:03 PM PDT 24 |
| Peak memory | 575616 kb |
| Host | smart-5e86c1a2-55dd-48a7-93d2-74d0bbc025a8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1527670769 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.xbar_random_large_delays.1527670769 |
| Directory | /workspace/3.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/3.xbar_random_slow_rsp.1555391165 |
| Short name | T2505 |
| Test name | |
| Test status | |
| Simulation time | 13449088089 ps |
| CPU time | 229.75 seconds |
| Started | Aug 12 06:47:17 PM PDT 24 |
| Finished | Aug 12 06:51:07 PM PDT 24 |
| Peak memory | 575708 kb |
| Host | smart-69408de2-8163-433e-b2e2-f8bdb2857f83 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1555391165 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.xbar_random_slow_rsp.1555391165 |
| Directory | /workspace/3.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/3.xbar_random_zero_delays.582353919 |
| Short name | T553 |
| Test name | |
| Test status | |
| Simulation time | 70866747 ps |
| CPU time | 8.3 seconds |
| Started | Aug 12 06:47:21 PM PDT 24 |
| Finished | Aug 12 06:47:30 PM PDT 24 |
| Peak memory | 575528 kb |
| Host | smart-a8bbd152-e81a-4ae9-ab55-0cdf0cea4bc9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=582353919 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.xbar_random_zero_delay s.582353919 |
| Directory | /workspace/3.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/3.xbar_same_source.511896661 |
| Short name | T2272 |
| Test name | |
| Test status | |
| Simulation time | 2424381406 ps |
| CPU time | 63.82 seconds |
| Started | Aug 12 06:47:14 PM PDT 24 |
| Finished | Aug 12 06:48:18 PM PDT 24 |
| Peak memory | 575732 kb |
| Host | smart-af64138c-f4a1-4518-988f-b911ccda2a6a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=511896661 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.xbar_same_source.511896661 |
| Directory | /workspace/3.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/3.xbar_smoke.443414914 |
| Short name | T2384 |
| Test name | |
| Test status | |
| Simulation time | 141738713 ps |
| CPU time | 7.35 seconds |
| Started | Aug 12 06:47:19 PM PDT 24 |
| Finished | Aug 12 06:47:26 PM PDT 24 |
| Peak memory | 573600 kb |
| Host | smart-68dd73cb-c99d-4f84-8a57-bbb2d438fcbe |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=443414914 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.xbar_smoke.443414914 |
| Directory | /workspace/3.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/3.xbar_smoke_large_delays.2960366238 |
| Short name | T1631 |
| Test name | |
| Test status | |
| Simulation time | 9132019445 ps |
| CPU time | 93.55 seconds |
| Started | Aug 12 06:47:16 PM PDT 24 |
| Finished | Aug 12 06:48:50 PM PDT 24 |
| Peak memory | 573740 kb |
| Host | smart-fc7b5d4a-6430-4031-99aa-bb8f886262cb |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2960366238 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.xbar_smoke_large_delays.2960366238 |
| Directory | /workspace/3.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/3.xbar_smoke_slow_rsp.552307380 |
| Short name | T1976 |
| Test name | |
| Test status | |
| Simulation time | 5720036276 ps |
| CPU time | 89.28 seconds |
| Started | Aug 12 06:47:22 PM PDT 24 |
| Finished | Aug 12 06:48:52 PM PDT 24 |
| Peak memory | 573668 kb |
| Host | smart-ce0c2d14-578f-4ae0-bd1e-c71bd1bd511a |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=552307380 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.xbar_smoke_slow_rsp.552307380 |
| Directory | /workspace/3.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/3.xbar_smoke_zero_delays.2617909921 |
| Short name | T2195 |
| Test name | |
| Test status | |
| Simulation time | 51709081 ps |
| CPU time | 6.34 seconds |
| Started | Aug 12 06:47:19 PM PDT 24 |
| Finished | Aug 12 06:47:25 PM PDT 24 |
| Peak memory | 573640 kb |
| Host | smart-ec1d6f05-16c9-484b-9fa9-5e9df80397a2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2617909921 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.xbar_smoke_zero_delays .2617909921 |
| Directory | /workspace/3.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/3.xbar_stress_all.662834405 |
| Short name | T2920 |
| Test name | |
| Test status | |
| Simulation time | 2959158609 ps |
| CPU time | 261.53 seconds |
| Started | Aug 12 06:47:19 PM PDT 24 |
| Finished | Aug 12 06:51:41 PM PDT 24 |
| Peak memory | 575780 kb |
| Host | smart-f9ea6a80-d747-42ce-8591-d854c842e511 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=662834405 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.xbar_stress_all.662834405 |
| Directory | /workspace/3.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/3.xbar_stress_all_with_error.53174623 |
| Short name | T2004 |
| Test name | |
| Test status | |
| Simulation time | 2185363862 ps |
| CPU time | 72.63 seconds |
| Started | Aug 12 06:47:17 PM PDT 24 |
| Finished | Aug 12 06:48:30 PM PDT 24 |
| Peak memory | 575888 kb |
| Host | smart-f056ce69-972c-444c-bc31-e57081885b01 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=53174623 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.xbar_stress_all_with_error.53174623 |
| Directory | /workspace/3.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/3.xbar_stress_all_with_rand_reset.4028859463 |
| Short name | T1714 |
| Test name | |
| Test status | |
| Simulation time | 188197684 ps |
| CPU time | 72.28 seconds |
| Started | Aug 12 06:47:17 PM PDT 24 |
| Finished | Aug 12 06:48:29 PM PDT 24 |
| Peak memory | 575696 kb |
| Host | smart-592df7c3-5236-4578-a5db-e1398c219b0d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4028859463 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.xbar_stress_all_ with_rand_reset.4028859463 |
| Directory | /workspace/3.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/3.xbar_stress_all_with_reset_error.3244916449 |
| Short name | T2880 |
| Test name | |
| Test status | |
| Simulation time | 1614147743 ps |
| CPU time | 180.16 seconds |
| Started | Aug 12 06:47:17 PM PDT 24 |
| Finished | Aug 12 06:50:18 PM PDT 24 |
| Peak memory | 575820 kb |
| Host | smart-3735673a-c515-4950-a86b-f03d8d591144 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3244916449 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.xbar_stress_all _with_reset_error.3244916449 |
| Directory | /workspace/3.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/3.xbar_unmapped_addr.3383035304 |
| Short name | T1924 |
| Test name | |
| Test status | |
| Simulation time | 679631443 ps |
| CPU time | 29.18 seconds |
| Started | Aug 12 06:47:18 PM PDT 24 |
| Finished | Aug 12 06:47:48 PM PDT 24 |
| Peak memory | 575532 kb |
| Host | smart-dc227cb7-c8b6-4120-842f-7deec048fa57 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3383035304 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.xbar_unmapped_addr.3383035304 |
| Directory | /workspace/3.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/30.xbar_access_same_device.2754635149 |
| Short name | T1572 |
| Test name | |
| Test status | |
| Simulation time | 260167736 ps |
| CPU time | 12.81 seconds |
| Started | Aug 12 06:50:27 PM PDT 24 |
| Finished | Aug 12 06:50:40 PM PDT 24 |
| Peak memory | 573648 kb |
| Host | smart-6d645930-b59b-40a0-82cd-9b13a2b75e18 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2754635149 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.xbar_access_same_device .2754635149 |
| Directory | /workspace/30.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/30.xbar_access_same_device_slow_rsp.3508999714 |
| Short name | T2700 |
| Test name | |
| Test status | |
| Simulation time | 15122577351 ps |
| CPU time | 257.95 seconds |
| Started | Aug 12 06:50:27 PM PDT 24 |
| Finished | Aug 12 06:54:45 PM PDT 24 |
| Peak memory | 575748 kb |
| Host | smart-bc539b77-e42b-4f2e-b43b-8c0464b4bed0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3508999714 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.xbar_access_same_ device_slow_rsp.3508999714 |
| Directory | /workspace/30.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/30.xbar_error_and_unmapped_addr.2842221347 |
| Short name | T1455 |
| Test name | |
| Test status | |
| Simulation time | 299207543 ps |
| CPU time | 36.25 seconds |
| Started | Aug 12 06:50:26 PM PDT 24 |
| Finished | Aug 12 06:51:03 PM PDT 24 |
| Peak memory | 575760 kb |
| Host | smart-09631d8b-f3e5-4616-ae37-63d09f767ec6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2842221347 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.xbar_error_and_unmapped_add r.2842221347 |
| Directory | /workspace/30.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/30.xbar_error_random.2838335971 |
| Short name | T2350 |
| Test name | |
| Test status | |
| Simulation time | 1155414643 ps |
| CPU time | 39.69 seconds |
| Started | Aug 12 06:50:28 PM PDT 24 |
| Finished | Aug 12 06:51:07 PM PDT 24 |
| Peak memory | 575700 kb |
| Host | smart-c6674885-c49c-4adc-84ee-d8dd11903076 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2838335971 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.xbar_error_random.2838335971 |
| Directory | /workspace/30.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/30.xbar_random.659352912 |
| Short name | T2019 |
| Test name | |
| Test status | |
| Simulation time | 195634479 ps |
| CPU time | 18.79 seconds |
| Started | Aug 12 06:50:27 PM PDT 24 |
| Finished | Aug 12 06:50:45 PM PDT 24 |
| Peak memory | 575648 kb |
| Host | smart-cdee526d-af4e-46d1-b29d-36d9a0ce44af |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=659352912 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.xbar_random.659352912 |
| Directory | /workspace/30.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/30.xbar_random_large_delays.1515757242 |
| Short name | T2915 |
| Test name | |
| Test status | |
| Simulation time | 12546082715 ps |
| CPU time | 131.18 seconds |
| Started | Aug 12 06:50:26 PM PDT 24 |
| Finished | Aug 12 06:52:37 PM PDT 24 |
| Peak memory | 575776 kb |
| Host | smart-4e4c25ec-08d7-4f54-8abe-e06115705b34 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1515757242 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.xbar_random_large_delays.1515757242 |
| Directory | /workspace/30.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/30.xbar_random_slow_rsp.1657355712 |
| Short name | T649 |
| Test name | |
| Test status | |
| Simulation time | 25940280760 ps |
| CPU time | 440.51 seconds |
| Started | Aug 12 06:50:31 PM PDT 24 |
| Finished | Aug 12 06:57:52 PM PDT 24 |
| Peak memory | 575820 kb |
| Host | smart-bfab8e27-818f-4958-bfd0-69fdc1fcb514 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1657355712 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.xbar_random_slow_rsp.1657355712 |
| Directory | /workspace/30.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/30.xbar_random_zero_delays.2070992006 |
| Short name | T2067 |
| Test name | |
| Test status | |
| Simulation time | 106538851 ps |
| CPU time | 12.4 seconds |
| Started | Aug 12 06:50:31 PM PDT 24 |
| Finished | Aug 12 06:50:44 PM PDT 24 |
| Peak memory | 575732 kb |
| Host | smart-fd7928dd-091d-4d6f-839f-3b04b9d80b99 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2070992006 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.xbar_random_zero_del ays.2070992006 |
| Directory | /workspace/30.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/30.xbar_same_source.2620188490 |
| Short name | T637 |
| Test name | |
| Test status | |
| Simulation time | 112109521 ps |
| CPU time | 10.75 seconds |
| Started | Aug 12 06:50:27 PM PDT 24 |
| Finished | Aug 12 06:50:38 PM PDT 24 |
| Peak memory | 575628 kb |
| Host | smart-fe0524dd-8224-4789-bb0a-471ada2ef958 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2620188490 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.xbar_same_source.2620188490 |
| Directory | /workspace/30.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/30.xbar_smoke.307424874 |
| Short name | T1810 |
| Test name | |
| Test status | |
| Simulation time | 36360337 ps |
| CPU time | 6 seconds |
| Started | Aug 12 06:50:26 PM PDT 24 |
| Finished | Aug 12 06:50:32 PM PDT 24 |
| Peak memory | 574280 kb |
| Host | smart-00708f8a-15ad-4d4d-98d6-7210228f2c8f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=307424874 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.xbar_smoke.307424874 |
| Directory | /workspace/30.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/30.xbar_smoke_large_delays.779433671 |
| Short name | T2710 |
| Test name | |
| Test status | |
| Simulation time | 5027815206 ps |
| CPU time | 49.41 seconds |
| Started | Aug 12 06:50:28 PM PDT 24 |
| Finished | Aug 12 06:51:17 PM PDT 24 |
| Peak memory | 573676 kb |
| Host | smart-737329e2-fa5c-4d00-816c-b07cbe5b4fbb |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=779433671 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.xbar_smoke_large_delays.779433671 |
| Directory | /workspace/30.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/30.xbar_smoke_slow_rsp.3328472715 |
| Short name | T2327 |
| Test name | |
| Test status | |
| Simulation time | 5005208227 ps |
| CPU time | 85.49 seconds |
| Started | Aug 12 06:50:28 PM PDT 24 |
| Finished | Aug 12 06:51:54 PM PDT 24 |
| Peak memory | 573704 kb |
| Host | smart-4a974e63-706e-41c5-9168-a1dc9f70de0d |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3328472715 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.xbar_smoke_slow_rsp.3328472715 |
| Directory | /workspace/30.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/30.xbar_smoke_zero_delays.1380000539 |
| Short name | T2856 |
| Test name | |
| Test status | |
| Simulation time | 33622986 ps |
| CPU time | 5.25 seconds |
| Started | Aug 12 06:50:26 PM PDT 24 |
| Finished | Aug 12 06:50:32 PM PDT 24 |
| Peak memory | 574292 kb |
| Host | smart-63ec091e-d1ff-4dd0-b2a2-5f87ef07c0de |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1380000539 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.xbar_smoke_zero_delay s.1380000539 |
| Directory | /workspace/30.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/30.xbar_stress_all.3221450547 |
| Short name | T519 |
| Test name | |
| Test status | |
| Simulation time | 2572189138 ps |
| CPU time | 104.35 seconds |
| Started | Aug 12 06:50:28 PM PDT 24 |
| Finished | Aug 12 06:52:13 PM PDT 24 |
| Peak memory | 574348 kb |
| Host | smart-75fadec6-bad6-4ac0-a506-ee42e3a64b1d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3221450547 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.xbar_stress_all.3221450547 |
| Directory | /workspace/30.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/30.xbar_stress_all_with_error.3441828323 |
| Short name | T2571 |
| Test name | |
| Test status | |
| Simulation time | 6394650 ps |
| CPU time | 3.73 seconds |
| Started | Aug 12 06:50:28 PM PDT 24 |
| Finished | Aug 12 06:50:32 PM PDT 24 |
| Peak memory | 565880 kb |
| Host | smart-bd501042-c31f-4fd3-9b2c-973c7d3a7495 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3441828323 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.xbar_stress_all_with_error.3441828323 |
| Directory | /workspace/30.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/30.xbar_stress_all_with_rand_reset.1312558084 |
| Short name | T2283 |
| Test name | |
| Test status | |
| Simulation time | 3379408732 ps |
| CPU time | 509.72 seconds |
| Started | Aug 12 06:50:26 PM PDT 24 |
| Finished | Aug 12 06:58:56 PM PDT 24 |
| Peak memory | 576560 kb |
| Host | smart-0abd4f0c-204f-44a8-a9de-baa69005035e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1312558084 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.xbar_stress_all _with_rand_reset.1312558084 |
| Directory | /workspace/30.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/30.xbar_stress_all_with_reset_error.1905376394 |
| Short name | T1769 |
| Test name | |
| Test status | |
| Simulation time | 561474487 ps |
| CPU time | 132.73 seconds |
| Started | Aug 12 06:50:27 PM PDT 24 |
| Finished | Aug 12 06:52:40 PM PDT 24 |
| Peak memory | 576532 kb |
| Host | smart-f66dd47d-03da-4e1b-9c8e-f0656bad2af9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1905376394 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.xbar_stress_al l_with_reset_error.1905376394 |
| Directory | /workspace/30.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/30.xbar_unmapped_addr.546049383 |
| Short name | T2335 |
| Test name | |
| Test status | |
| Simulation time | 163800016 ps |
| CPU time | 23.53 seconds |
| Started | Aug 12 06:50:28 PM PDT 24 |
| Finished | Aug 12 06:50:52 PM PDT 24 |
| Peak memory | 574316 kb |
| Host | smart-0a866fe9-e1ef-41b2-a4f4-054b7463a6fb |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=546049383 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.xbar_unmapped_addr.546049383 |
| Directory | /workspace/30.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/31.xbar_access_same_device.1314917353 |
| Short name | T2342 |
| Test name | |
| Test status | |
| Simulation time | 73919925 ps |
| CPU time | 13.23 seconds |
| Started | Aug 12 06:50:34 PM PDT 24 |
| Finished | Aug 12 06:50:47 PM PDT 24 |
| Peak memory | 575520 kb |
| Host | smart-54205bfd-abba-4d4f-b0a3-23c6d3e57f5b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1314917353 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.xbar_access_same_device .1314917353 |
| Directory | /workspace/31.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/31.xbar_access_same_device_slow_rsp.466973389 |
| Short name | T905 |
| Test name | |
| Test status | |
| Simulation time | 107335994695 ps |
| CPU time | 1786.13 seconds |
| Started | Aug 12 06:50:34 PM PDT 24 |
| Finished | Aug 12 07:20:21 PM PDT 24 |
| Peak memory | 575896 kb |
| Host | smart-39452725-dd47-4ff2-a48b-b116e201c55e |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=466973389 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.xbar_access_same_d evice_slow_rsp.466973389 |
| Directory | /workspace/31.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/31.xbar_error_and_unmapped_addr.4275156972 |
| Short name | T2489 |
| Test name | |
| Test status | |
| Simulation time | 238781806 ps |
| CPU time | 28.14 seconds |
| Started | Aug 12 06:50:33 PM PDT 24 |
| Finished | Aug 12 06:51:02 PM PDT 24 |
| Peak memory | 575556 kb |
| Host | smart-0619ee64-4d07-4c29-9949-8caa2be59705 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4275156972 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.xbar_error_and_unmapped_add r.4275156972 |
| Directory | /workspace/31.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/31.xbar_error_random.3459886261 |
| Short name | T2691 |
| Test name | |
| Test status | |
| Simulation time | 1203202499 ps |
| CPU time | 43.04 seconds |
| Started | Aug 12 06:50:34 PM PDT 24 |
| Finished | Aug 12 06:51:17 PM PDT 24 |
| Peak memory | 575632 kb |
| Host | smart-7f53aaa9-c915-44cb-a9f7-35d9999cb809 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3459886261 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.xbar_error_random.3459886261 |
| Directory | /workspace/31.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/31.xbar_random.933405485 |
| Short name | T2686 |
| Test name | |
| Test status | |
| Simulation time | 1004639875 ps |
| CPU time | 35.78 seconds |
| Started | Aug 12 06:50:37 PM PDT 24 |
| Finished | Aug 12 06:51:13 PM PDT 24 |
| Peak memory | 575540 kb |
| Host | smart-03c0d635-4df4-437d-9a25-44f87b198435 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=933405485 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.xbar_random.933405485 |
| Directory | /workspace/31.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/31.xbar_random_large_delays.2071268285 |
| Short name | T2732 |
| Test name | |
| Test status | |
| Simulation time | 97114686681 ps |
| CPU time | 1165.41 seconds |
| Started | Aug 12 06:50:35 PM PDT 24 |
| Finished | Aug 12 07:10:01 PM PDT 24 |
| Peak memory | 575732 kb |
| Host | smart-fe4c2a99-4f5a-4b51-bd59-88d74a4690bf |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2071268285 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.xbar_random_large_delays.2071268285 |
| Directory | /workspace/31.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/31.xbar_random_slow_rsp.2271422958 |
| Short name | T2650 |
| Test name | |
| Test status | |
| Simulation time | 38308302442 ps |
| CPU time | 650.3 seconds |
| Started | Aug 12 06:50:33 PM PDT 24 |
| Finished | Aug 12 07:01:24 PM PDT 24 |
| Peak memory | 575528 kb |
| Host | smart-72e4e8f6-3c13-4b07-b9a0-9c5cbeadfc1f |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2271422958 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.xbar_random_slow_rsp.2271422958 |
| Directory | /workspace/31.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/31.xbar_random_zero_delays.719024232 |
| Short name | T2914 |
| Test name | |
| Test status | |
| Simulation time | 415800704 ps |
| CPU time | 39.69 seconds |
| Started | Aug 12 06:50:34 PM PDT 24 |
| Finished | Aug 12 06:51:13 PM PDT 24 |
| Peak memory | 575528 kb |
| Host | smart-af2f46bd-e64b-458a-a0da-3ab2a21ab461 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=719024232 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.xbar_random_zero_dela ys.719024232 |
| Directory | /workspace/31.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/31.xbar_same_source.3774789155 |
| Short name | T516 |
| Test name | |
| Test status | |
| Simulation time | 2628002566 ps |
| CPU time | 75.41 seconds |
| Started | Aug 12 06:50:32 PM PDT 24 |
| Finished | Aug 12 06:51:47 PM PDT 24 |
| Peak memory | 575728 kb |
| Host | smart-177f91ac-342e-4abf-b18a-4ddc106eeb02 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3774789155 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.xbar_same_source.3774789155 |
| Directory | /workspace/31.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/31.xbar_smoke.3216958776 |
| Short name | T1713 |
| Test name | |
| Test status | |
| Simulation time | 252337843 ps |
| CPU time | 10.88 seconds |
| Started | Aug 12 06:50:27 PM PDT 24 |
| Finished | Aug 12 06:50:38 PM PDT 24 |
| Peak memory | 573604 kb |
| Host | smart-d5aa6786-b325-4c43-a86c-90a28dda31d7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3216958776 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.xbar_smoke.3216958776 |
| Directory | /workspace/31.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/31.xbar_smoke_large_delays.262888709 |
| Short name | T1984 |
| Test name | |
| Test status | |
| Simulation time | 6259791758 ps |
| CPU time | 61.24 seconds |
| Started | Aug 12 06:50:27 PM PDT 24 |
| Finished | Aug 12 06:51:28 PM PDT 24 |
| Peak memory | 573604 kb |
| Host | smart-f9b9c483-e67d-4793-991b-1cefb85817e4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=262888709 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.xbar_smoke_large_delays.262888709 |
| Directory | /workspace/31.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/31.xbar_smoke_slow_rsp.974995192 |
| Short name | T2765 |
| Test name | |
| Test status | |
| Simulation time | 4510001416 ps |
| CPU time | 77.29 seconds |
| Started | Aug 12 06:50:26 PM PDT 24 |
| Finished | Aug 12 06:51:44 PM PDT 24 |
| Peak memory | 573660 kb |
| Host | smart-23f58954-f5aa-4812-b17f-88cce0d62508 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=974995192 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.xbar_smoke_slow_rsp.974995192 |
| Directory | /workspace/31.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/31.xbar_smoke_zero_delays.2857808893 |
| Short name | T2678 |
| Test name | |
| Test status | |
| Simulation time | 49922097 ps |
| CPU time | 6.65 seconds |
| Started | Aug 12 06:50:28 PM PDT 24 |
| Finished | Aug 12 06:50:34 PM PDT 24 |
| Peak memory | 573640 kb |
| Host | smart-1a23b3f6-289c-4b99-be8f-6305a9670ef3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2857808893 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.xbar_smoke_zero_delay s.2857808893 |
| Directory | /workspace/31.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/31.xbar_stress_all_with_error.271454670 |
| Short name | T2141 |
| Test name | |
| Test status | |
| Simulation time | 2093616968 ps |
| CPU time | 161.49 seconds |
| Started | Aug 12 06:50:39 PM PDT 24 |
| Finished | Aug 12 06:53:20 PM PDT 24 |
| Peak memory | 575784 kb |
| Host | smart-5252a192-8bd5-477f-912a-902840e942cd |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=271454670 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.xbar_stress_all_with_error.271454670 |
| Directory | /workspace/31.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/31.xbar_stress_all_with_rand_reset.1328037198 |
| Short name | T1897 |
| Test name | |
| Test status | |
| Simulation time | 7256802 ps |
| CPU time | 23.03 seconds |
| Started | Aug 12 06:50:34 PM PDT 24 |
| Finished | Aug 12 06:50:57 PM PDT 24 |
| Peak memory | 573632 kb |
| Host | smart-07ea630b-1c09-4e4f-915e-61a8465ac4f5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1328037198 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.xbar_stress_all _with_rand_reset.1328037198 |
| Directory | /workspace/31.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/31.xbar_stress_all_with_reset_error.3744600092 |
| Short name | T2005 |
| Test name | |
| Test status | |
| Simulation time | 1810438075 ps |
| CPU time | 334.59 seconds |
| Started | Aug 12 06:50:34 PM PDT 24 |
| Finished | Aug 12 06:56:09 PM PDT 24 |
| Peak memory | 575668 kb |
| Host | smart-837ec589-b201-43f1-82c0-1d9cbbd073f1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3744600092 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.xbar_stress_al l_with_reset_error.3744600092 |
| Directory | /workspace/31.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/31.xbar_unmapped_addr.3893243239 |
| Short name | T2065 |
| Test name | |
| Test status | |
| Simulation time | 365818039 ps |
| CPU time | 19.71 seconds |
| Started | Aug 12 06:50:33 PM PDT 24 |
| Finished | Aug 12 06:50:53 PM PDT 24 |
| Peak memory | 575620 kb |
| Host | smart-4a963cc3-31bf-44b8-8f61-522af5f7fbd3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3893243239 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.xbar_unmapped_addr.3893243239 |
| Directory | /workspace/31.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/32.xbar_access_same_device.3963719548 |
| Short name | T2612 |
| Test name | |
| Test status | |
| Simulation time | 1595509214 ps |
| CPU time | 67.32 seconds |
| Started | Aug 12 06:50:38 PM PDT 24 |
| Finished | Aug 12 06:51:45 PM PDT 24 |
| Peak memory | 575604 kb |
| Host | smart-03851dac-691e-43b1-abc7-ec6797b6f4bf |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3963719548 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.xbar_access_same_device .3963719548 |
| Directory | /workspace/32.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/32.xbar_access_same_device_slow_rsp.2225186709 |
| Short name | T933 |
| Test name | |
| Test status | |
| Simulation time | 13391644698 ps |
| CPU time | 222.3 seconds |
| Started | Aug 12 06:51:17 PM PDT 24 |
| Finished | Aug 12 06:54:59 PM PDT 24 |
| Peak memory | 575596 kb |
| Host | smart-93952618-0303-40a2-bbce-5f1fefa0afee |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2225186709 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.xbar_access_same_ device_slow_rsp.2225186709 |
| Directory | /workspace/32.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/32.xbar_error_and_unmapped_addr.1814096778 |
| Short name | T2029 |
| Test name | |
| Test status | |
| Simulation time | 197323620 ps |
| CPU time | 10.8 seconds |
| Started | Aug 12 06:51:36 PM PDT 24 |
| Finished | Aug 12 06:51:47 PM PDT 24 |
| Peak memory | 575760 kb |
| Host | smart-25313981-8364-488f-bbe6-da58c6d8858d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1814096778 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.xbar_error_and_unmapped_add r.1814096778 |
| Directory | /workspace/32.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/32.xbar_error_random.3942598766 |
| Short name | T1844 |
| Test name | |
| Test status | |
| Simulation time | 62738078 ps |
| CPU time | 5.93 seconds |
| Started | Aug 12 06:51:35 PM PDT 24 |
| Finished | Aug 12 06:51:41 PM PDT 24 |
| Peak memory | 573752 kb |
| Host | smart-bda64511-b29d-4185-b3ec-8bddbe2559a3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3942598766 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.xbar_error_random.3942598766 |
| Directory | /workspace/32.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/32.xbar_random.3433996869 |
| Short name | T2307 |
| Test name | |
| Test status | |
| Simulation time | 700441215 ps |
| CPU time | 25.63 seconds |
| Started | Aug 12 06:50:33 PM PDT 24 |
| Finished | Aug 12 06:50:59 PM PDT 24 |
| Peak memory | 575696 kb |
| Host | smart-80dbcb15-6935-4fa0-b75f-7579f278cc18 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3433996869 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.xbar_random.3433996869 |
| Directory | /workspace/32.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/32.xbar_random_large_delays.1956979256 |
| Short name | T2233 |
| Test name | |
| Test status | |
| Simulation time | 72506828311 ps |
| CPU time | 795.44 seconds |
| Started | Aug 12 06:50:34 PM PDT 24 |
| Finished | Aug 12 07:03:50 PM PDT 24 |
| Peak memory | 575604 kb |
| Host | smart-62f86113-41db-41f2-90d1-d719f157ca19 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1956979256 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.xbar_random_large_delays.1956979256 |
| Directory | /workspace/32.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/32.xbar_random_slow_rsp.3458875892 |
| Short name | T2021 |
| Test name | |
| Test status | |
| Simulation time | 21120781691 ps |
| CPU time | 350.95 seconds |
| Started | Aug 12 06:50:36 PM PDT 24 |
| Finished | Aug 12 06:56:27 PM PDT 24 |
| Peak memory | 575752 kb |
| Host | smart-8cdd8a19-115b-4701-97ef-23f3ea8c3ba0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3458875892 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.xbar_random_slow_rsp.3458875892 |
| Directory | /workspace/32.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/32.xbar_random_zero_delays.1782127057 |
| Short name | T2133 |
| Test name | |
| Test status | |
| Simulation time | 278975418 ps |
| CPU time | 24.76 seconds |
| Started | Aug 12 06:50:48 PM PDT 24 |
| Finished | Aug 12 06:51:13 PM PDT 24 |
| Peak memory | 575668 kb |
| Host | smart-0b4264ca-1cc8-4fd7-a05c-19001b699daa |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1782127057 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.xbar_random_zero_del ays.1782127057 |
| Directory | /workspace/32.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/32.xbar_same_source.441783437 |
| Short name | T688 |
| Test name | |
| Test status | |
| Simulation time | 1121023576 ps |
| CPU time | 32.52 seconds |
| Started | Aug 12 06:51:37 PM PDT 24 |
| Finished | Aug 12 06:52:09 PM PDT 24 |
| Peak memory | 575724 kb |
| Host | smart-268d4ef5-e9f2-4169-b0b1-60b29794e077 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=441783437 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.xbar_same_source.441783437 |
| Directory | /workspace/32.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/32.xbar_smoke.3028673091 |
| Short name | T2463 |
| Test name | |
| Test status | |
| Simulation time | 171308759 ps |
| CPU time | 8.19 seconds |
| Started | Aug 12 06:50:37 PM PDT 24 |
| Finished | Aug 12 06:50:46 PM PDT 24 |
| Peak memory | 573560 kb |
| Host | smart-17d0be60-8902-4bb1-9c6f-0c151dce7e40 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3028673091 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.xbar_smoke.3028673091 |
| Directory | /workspace/32.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/32.xbar_smoke_large_delays.3892670772 |
| Short name | T2046 |
| Test name | |
| Test status | |
| Simulation time | 10035035810 ps |
| CPU time | 100.41 seconds |
| Started | Aug 12 06:50:39 PM PDT 24 |
| Finished | Aug 12 06:52:19 PM PDT 24 |
| Peak memory | 574300 kb |
| Host | smart-6d78c12e-a161-41a2-9aa6-f8a85e8a16c3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3892670772 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.xbar_smoke_large_delays.3892670772 |
| Directory | /workspace/32.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/32.xbar_smoke_slow_rsp.2597788758 |
| Short name | T1815 |
| Test name | |
| Test status | |
| Simulation time | 3627557113 ps |
| CPU time | 63.1 seconds |
| Started | Aug 12 06:50:37 PM PDT 24 |
| Finished | Aug 12 06:51:40 PM PDT 24 |
| Peak memory | 573740 kb |
| Host | smart-d62ea59d-9e78-4473-a2ce-a6107f2493b4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2597788758 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.xbar_smoke_slow_rsp.2597788758 |
| Directory | /workspace/32.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/32.xbar_smoke_zero_delays.618650642 |
| Short name | T2168 |
| Test name | |
| Test status | |
| Simulation time | 39599370 ps |
| CPU time | 6.17 seconds |
| Started | Aug 12 06:50:36 PM PDT 24 |
| Finished | Aug 12 06:50:42 PM PDT 24 |
| Peak memory | 573584 kb |
| Host | smart-5cdbf324-f317-43da-ab77-0c0cad3a1e46 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=618650642 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.xbar_smoke_zero_delays .618650642 |
| Directory | /workspace/32.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/32.xbar_stress_all.3269758168 |
| Short name | T580 |
| Test name | |
| Test status | |
| Simulation time | 3896905779 ps |
| CPU time | 129.44 seconds |
| Started | Aug 12 06:51:36 PM PDT 24 |
| Finished | Aug 12 06:53:46 PM PDT 24 |
| Peak memory | 575888 kb |
| Host | smart-6e27ee68-84c9-4ccd-9b3f-eaf5dc382c2f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3269758168 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.xbar_stress_all.3269758168 |
| Directory | /workspace/32.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/32.xbar_stress_all_with_error.1605178556 |
| Short name | T552 |
| Test name | |
| Test status | |
| Simulation time | 2561605264 ps |
| CPU time | 162.79 seconds |
| Started | Aug 12 06:51:41 PM PDT 24 |
| Finished | Aug 12 06:54:24 PM PDT 24 |
| Peak memory | 576024 kb |
| Host | smart-7d2732d2-c56f-4244-bc04-c699b2c46e7b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1605178556 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.xbar_stress_all_with_error.1605178556 |
| Directory | /workspace/32.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/32.xbar_stress_all_with_rand_reset.3730292245 |
| Short name | T2627 |
| Test name | |
| Test status | |
| Simulation time | 101702652 ps |
| CPU time | 12.45 seconds |
| Started | Aug 12 06:51:32 PM PDT 24 |
| Finished | Aug 12 06:51:44 PM PDT 24 |
| Peak memory | 573656 kb |
| Host | smart-c24dfb21-962c-4050-8609-afed548bb91c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3730292245 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.xbar_stress_all _with_rand_reset.3730292245 |
| Directory | /workspace/32.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/32.xbar_stress_all_with_reset_error.1211519756 |
| Short name | T2927 |
| Test name | |
| Test status | |
| Simulation time | 1347720049 ps |
| CPU time | 166.02 seconds |
| Started | Aug 12 06:51:33 PM PDT 24 |
| Finished | Aug 12 06:54:19 PM PDT 24 |
| Peak memory | 575692 kb |
| Host | smart-72f08b84-d152-48f4-a16e-1356586983c1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1211519756 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.xbar_stress_al l_with_reset_error.1211519756 |
| Directory | /workspace/32.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/32.xbar_unmapped_addr.938514098 |
| Short name | T710 |
| Test name | |
| Test status | |
| Simulation time | 100530968 ps |
| CPU time | 14.93 seconds |
| Started | Aug 12 06:51:35 PM PDT 24 |
| Finished | Aug 12 06:51:50 PM PDT 24 |
| Peak memory | 575716 kb |
| Host | smart-1964bcf1-f9b1-4bc9-a640-565a43adc174 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=938514098 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.xbar_unmapped_addr.938514098 |
| Directory | /workspace/32.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/33.xbar_access_same_device.1145052875 |
| Short name | T1965 |
| Test name | |
| Test status | |
| Simulation time | 28996687 ps |
| CPU time | 8.31 seconds |
| Started | Aug 12 06:51:33 PM PDT 24 |
| Finished | Aug 12 06:51:42 PM PDT 24 |
| Peak memory | 575700 kb |
| Host | smart-68b5afea-25eb-43bf-af9a-e1c0f688cbac |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1145052875 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.xbar_access_same_device .1145052875 |
| Directory | /workspace/33.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/33.xbar_access_same_device_slow_rsp.474103684 |
| Short name | T2123 |
| Test name | |
| Test status | |
| Simulation time | 32742303697 ps |
| CPU time | 584.2 seconds |
| Started | Aug 12 06:51:32 PM PDT 24 |
| Finished | Aug 12 07:01:17 PM PDT 24 |
| Peak memory | 575756 kb |
| Host | smart-b9d569ad-2942-4191-8c68-86dfd3f3d01d |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=474103684 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.xbar_access_same_d evice_slow_rsp.474103684 |
| Directory | /workspace/33.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/33.xbar_error_and_unmapped_addr.697531922 |
| Short name | T2136 |
| Test name | |
| Test status | |
| Simulation time | 76750057 ps |
| CPU time | 10.3 seconds |
| Started | Aug 12 06:51:34 PM PDT 24 |
| Finished | Aug 12 06:51:44 PM PDT 24 |
| Peak memory | 575528 kb |
| Host | smart-71ae9412-7579-4b1c-8071-5f9a247f93e6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=697531922 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.xbar_error_and_unmapped_addr .697531922 |
| Directory | /workspace/33.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/33.xbar_error_random.612833891 |
| Short name | T2867 |
| Test name | |
| Test status | |
| Simulation time | 2204949469 ps |
| CPU time | 66.49 seconds |
| Started | Aug 12 06:51:32 PM PDT 24 |
| Finished | Aug 12 06:52:39 PM PDT 24 |
| Peak memory | 575752 kb |
| Host | smart-01ad5aca-e667-434d-9be4-899ed3a5fe26 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=612833891 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.xbar_error_random.612833891 |
| Directory | /workspace/33.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/33.xbar_random.2029281265 |
| Short name | T705 |
| Test name | |
| Test status | |
| Simulation time | 417273686 ps |
| CPU time | 37.2 seconds |
| Started | Aug 12 06:51:35 PM PDT 24 |
| Finished | Aug 12 06:52:12 PM PDT 24 |
| Peak memory | 575688 kb |
| Host | smart-2f1d6218-cce3-4461-b3be-7dfee6885d5a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2029281265 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.xbar_random.2029281265 |
| Directory | /workspace/33.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/33.xbar_random_large_delays.1195587608 |
| Short name | T657 |
| Test name | |
| Test status | |
| Simulation time | 44618072794 ps |
| CPU time | 485.9 seconds |
| Started | Aug 12 06:51:32 PM PDT 24 |
| Finished | Aug 12 06:59:39 PM PDT 24 |
| Peak memory | 575824 kb |
| Host | smart-2404b3f9-b5a9-4269-885b-7a4370d2d9c7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1195587608 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.xbar_random_large_delays.1195587608 |
| Directory | /workspace/33.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/33.xbar_random_slow_rsp.2509709374 |
| Short name | T1620 |
| Test name | |
| Test status | |
| Simulation time | 3302399134 ps |
| CPU time | 52.18 seconds |
| Started | Aug 12 06:51:34 PM PDT 24 |
| Finished | Aug 12 06:52:26 PM PDT 24 |
| Peak memory | 573720 kb |
| Host | smart-5fff37fb-88e8-48cf-9915-5b669f2b437f |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2509709374 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.xbar_random_slow_rsp.2509709374 |
| Directory | /workspace/33.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/33.xbar_random_zero_delays.3128178104 |
| Short name | T2570 |
| Test name | |
| Test status | |
| Simulation time | 449740466 ps |
| CPU time | 35.92 seconds |
| Started | Aug 12 06:51:35 PM PDT 24 |
| Finished | Aug 12 06:52:11 PM PDT 24 |
| Peak memory | 575724 kb |
| Host | smart-7bf03d24-1ae3-41ca-b77c-ea690ff4ad05 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3128178104 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.xbar_random_zero_del ays.3128178104 |
| Directory | /workspace/33.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/33.xbar_same_source.2174765068 |
| Short name | T2002 |
| Test name | |
| Test status | |
| Simulation time | 267407332 ps |
| CPU time | 20.59 seconds |
| Started | Aug 12 06:51:35 PM PDT 24 |
| Finished | Aug 12 06:51:56 PM PDT 24 |
| Peak memory | 575648 kb |
| Host | smart-926077f1-670b-4218-9976-0a5f7e7ae139 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2174765068 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.xbar_same_source.2174765068 |
| Directory | /workspace/33.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/33.xbar_smoke.959775750 |
| Short name | T1889 |
| Test name | |
| Test status | |
| Simulation time | 163237812 ps |
| CPU time | 7.8 seconds |
| Started | Aug 12 06:51:31 PM PDT 24 |
| Finished | Aug 12 06:51:39 PM PDT 24 |
| Peak memory | 573500 kb |
| Host | smart-364d81cc-2b05-4e8b-a351-3cb9d7cf48b2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=959775750 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.xbar_smoke.959775750 |
| Directory | /workspace/33.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/33.xbar_smoke_large_delays.3722834214 |
| Short name | T1678 |
| Test name | |
| Test status | |
| Simulation time | 7617059865 ps |
| CPU time | 76.38 seconds |
| Started | Aug 12 06:51:32 PM PDT 24 |
| Finished | Aug 12 06:52:48 PM PDT 24 |
| Peak memory | 573556 kb |
| Host | smart-b3a2a8ab-6688-4d70-954a-ec7abf71f42b |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3722834214 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.xbar_smoke_large_delays.3722834214 |
| Directory | /workspace/33.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/33.xbar_smoke_slow_rsp.619548518 |
| Short name | T926 |
| Test name | |
| Test status | |
| Simulation time | 4917321867 ps |
| CPU time | 73.68 seconds |
| Started | Aug 12 06:51:41 PM PDT 24 |
| Finished | Aug 12 06:52:55 PM PDT 24 |
| Peak memory | 574428 kb |
| Host | smart-f8b7725d-8ed8-4c7a-a1b9-ac980c346a36 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=619548518 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.xbar_smoke_slow_rsp.619548518 |
| Directory | /workspace/33.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/33.xbar_smoke_zero_delays.2531794370 |
| Short name | T2152 |
| Test name | |
| Test status | |
| Simulation time | 51772068 ps |
| CPU time | 7.14 seconds |
| Started | Aug 12 06:51:33 PM PDT 24 |
| Finished | Aug 12 06:51:40 PM PDT 24 |
| Peak memory | 573560 kb |
| Host | smart-ae6f2d3b-80fd-4440-a0d0-8fb84de839c1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2531794370 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.xbar_smoke_zero_delay s.2531794370 |
| Directory | /workspace/33.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/33.xbar_stress_all.3446729244 |
| Short name | T2326 |
| Test name | |
| Test status | |
| Simulation time | 1322484356 ps |
| CPU time | 53.11 seconds |
| Started | Aug 12 06:51:37 PM PDT 24 |
| Finished | Aug 12 06:52:30 PM PDT 24 |
| Peak memory | 575752 kb |
| Host | smart-1a475df6-05a2-474a-948f-e5fec600729b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3446729244 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.xbar_stress_all.3446729244 |
| Directory | /workspace/33.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/33.xbar_stress_all_with_error.4174674846 |
| Short name | T2122 |
| Test name | |
| Test status | |
| Simulation time | 266960718 ps |
| CPU time | 21.65 seconds |
| Started | Aug 12 06:51:34 PM PDT 24 |
| Finished | Aug 12 06:51:56 PM PDT 24 |
| Peak memory | 575748 kb |
| Host | smart-983316ea-d4c4-4e10-979f-720721b7cd41 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4174674846 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.xbar_stress_all_with_error.4174674846 |
| Directory | /workspace/33.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/33.xbar_stress_all_with_rand_reset.4104982870 |
| Short name | T2232 |
| Test name | |
| Test status | |
| Simulation time | 384671760 ps |
| CPU time | 146.46 seconds |
| Started | Aug 12 06:51:34 PM PDT 24 |
| Finished | Aug 12 06:54:01 PM PDT 24 |
| Peak memory | 575724 kb |
| Host | smart-47637822-0dc5-483e-8417-f5b80baa575a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4104982870 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.xbar_stress_all _with_rand_reset.4104982870 |
| Directory | /workspace/33.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/33.xbar_unmapped_addr.2022709729 |
| Short name | T2124 |
| Test name | |
| Test status | |
| Simulation time | 205585638 ps |
| CPU time | 12.49 seconds |
| Started | Aug 12 06:51:34 PM PDT 24 |
| Finished | Aug 12 06:51:47 PM PDT 24 |
| Peak memory | 575716 kb |
| Host | smart-edf60309-0236-41cb-83d0-0241578d4bd8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2022709729 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.xbar_unmapped_addr.2022709729 |
| Directory | /workspace/33.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/34.xbar_access_same_device.1472853174 |
| Short name | T2246 |
| Test name | |
| Test status | |
| Simulation time | 282026233 ps |
| CPU time | 23.83 seconds |
| Started | Aug 12 06:51:36 PM PDT 24 |
| Finished | Aug 12 06:52:00 PM PDT 24 |
| Peak memory | 575620 kb |
| Host | smart-f37e8ef3-a54f-4e67-96a1-e9a5121ad94d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1472853174 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.xbar_access_same_device .1472853174 |
| Directory | /workspace/34.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/34.xbar_access_same_device_slow_rsp.487745073 |
| Short name | T2367 |
| Test name | |
| Test status | |
| Simulation time | 112953852639 ps |
| CPU time | 2043.35 seconds |
| Started | Aug 12 06:51:33 PM PDT 24 |
| Finished | Aug 12 07:25:37 PM PDT 24 |
| Peak memory | 575972 kb |
| Host | smart-9cc75bd4-9bc8-4482-9ca5-8bf13a04e240 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=487745073 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.xbar_access_same_d evice_slow_rsp.487745073 |
| Directory | /workspace/34.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/34.xbar_error_and_unmapped_addr.416606619 |
| Short name | T1797 |
| Test name | |
| Test status | |
| Simulation time | 878208158 ps |
| CPU time | 37.21 seconds |
| Started | Aug 12 06:51:36 PM PDT 24 |
| Finished | Aug 12 06:52:13 PM PDT 24 |
| Peak memory | 575764 kb |
| Host | smart-ac5b67c5-b3fd-4dc7-8f61-b8a33cd13624 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=416606619 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.xbar_error_and_unmapped_addr .416606619 |
| Directory | /workspace/34.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/34.xbar_error_random.568724081 |
| Short name | T2267 |
| Test name | |
| Test status | |
| Simulation time | 659478043 ps |
| CPU time | 27.76 seconds |
| Started | Aug 12 06:51:36 PM PDT 24 |
| Finished | Aug 12 06:52:04 PM PDT 24 |
| Peak memory | 575628 kb |
| Host | smart-74bca6ea-8b06-4bbd-8b17-ee03e382afab |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=568724081 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.xbar_error_random.568724081 |
| Directory | /workspace/34.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/34.xbar_random.220136461 |
| Short name | T1624 |
| Test name | |
| Test status | |
| Simulation time | 257889140 ps |
| CPU time | 21.89 seconds |
| Started | Aug 12 06:51:31 PM PDT 24 |
| Finished | Aug 12 06:51:53 PM PDT 24 |
| Peak memory | 575640 kb |
| Host | smart-3b70c32c-f701-433a-856e-33e116a5da92 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=220136461 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.xbar_random.220136461 |
| Directory | /workspace/34.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/34.xbar_random_large_delays.2318816089 |
| Short name | T2574 |
| Test name | |
| Test status | |
| Simulation time | 50800110944 ps |
| CPU time | 568.49 seconds |
| Started | Aug 12 06:51:37 PM PDT 24 |
| Finished | Aug 12 07:01:06 PM PDT 24 |
| Peak memory | 575620 kb |
| Host | smart-077dc73e-900b-4eb5-8dc4-ac74fcdbe086 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2318816089 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.xbar_random_large_delays.2318816089 |
| Directory | /workspace/34.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/34.xbar_random_slow_rsp.2476590541 |
| Short name | T2744 |
| Test name | |
| Test status | |
| Simulation time | 64557634969 ps |
| CPU time | 1126.69 seconds |
| Started | Aug 12 06:51:35 PM PDT 24 |
| Finished | Aug 12 07:10:23 PM PDT 24 |
| Peak memory | 575840 kb |
| Host | smart-308abc3a-2fee-4d5b-8407-42f2145014d7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2476590541 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.xbar_random_slow_rsp.2476590541 |
| Directory | /workspace/34.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/34.xbar_random_zero_delays.546883226 |
| Short name | T2755 |
| Test name | |
| Test status | |
| Simulation time | 465583785 ps |
| CPU time | 39.23 seconds |
| Started | Aug 12 06:51:34 PM PDT 24 |
| Finished | Aug 12 06:52:14 PM PDT 24 |
| Peak memory | 575856 kb |
| Host | smart-f17fb61d-65c0-4a8f-bdd5-d619221b039a |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=546883226 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.xbar_random_zero_dela ys.546883226 |
| Directory | /workspace/34.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/34.xbar_same_source.1940031126 |
| Short name | T2639 |
| Test name | |
| Test status | |
| Simulation time | 1389387399 ps |
| CPU time | 41.38 seconds |
| Started | Aug 12 06:51:37 PM PDT 24 |
| Finished | Aug 12 06:52:19 PM PDT 24 |
| Peak memory | 575668 kb |
| Host | smart-03477dfa-5716-448e-a434-417f6c245a5f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1940031126 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.xbar_same_source.1940031126 |
| Directory | /workspace/34.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/34.xbar_smoke.3279266076 |
| Short name | T1535 |
| Test name | |
| Test status | |
| Simulation time | 185813227 ps |
| CPU time | 8.8 seconds |
| Started | Aug 12 06:51:36 PM PDT 24 |
| Finished | Aug 12 06:51:45 PM PDT 24 |
| Peak memory | 573604 kb |
| Host | smart-e0388e87-462a-4bc5-bf3b-ecc477b26c6d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3279266076 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.xbar_smoke.3279266076 |
| Directory | /workspace/34.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/34.xbar_smoke_large_delays.3138258924 |
| Short name | T2879 |
| Test name | |
| Test status | |
| Simulation time | 8964312126 ps |
| CPU time | 93 seconds |
| Started | Aug 12 06:51:34 PM PDT 24 |
| Finished | Aug 12 06:53:08 PM PDT 24 |
| Peak memory | 573588 kb |
| Host | smart-cef82175-750f-49b6-bf9d-75b786e7db3e |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3138258924 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.xbar_smoke_large_delays.3138258924 |
| Directory | /workspace/34.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/34.xbar_smoke_slow_rsp.1018302709 |
| Short name | T1681 |
| Test name | |
| Test status | |
| Simulation time | 4374048749 ps |
| CPU time | 73.25 seconds |
| Started | Aug 12 06:51:37 PM PDT 24 |
| Finished | Aug 12 06:52:50 PM PDT 24 |
| Peak memory | 574300 kb |
| Host | smart-9cde1a4e-6fd9-4adf-b81c-8919faaf6874 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1018302709 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.xbar_smoke_slow_rsp.1018302709 |
| Directory | /workspace/34.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/34.xbar_smoke_zero_delays.1148512881 |
| Short name | T2496 |
| Test name | |
| Test status | |
| Simulation time | 47760334 ps |
| CPU time | 6.85 seconds |
| Started | Aug 12 06:51:35 PM PDT 24 |
| Finished | Aug 12 06:51:42 PM PDT 24 |
| Peak memory | 573568 kb |
| Host | smart-8e6a5a5e-275a-4126-8c4c-20534247d601 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1148512881 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.xbar_smoke_zero_delay s.1148512881 |
| Directory | /workspace/34.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/34.xbar_stress_all.4199567951 |
| Short name | T2608 |
| Test name | |
| Test status | |
| Simulation time | 14810900825 ps |
| CPU time | 552.73 seconds |
| Started | Aug 12 06:51:35 PM PDT 24 |
| Finished | Aug 12 07:00:48 PM PDT 24 |
| Peak memory | 575748 kb |
| Host | smart-2e4b2007-cc37-40d3-b5eb-ccc50a87d3d2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4199567951 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.xbar_stress_all.4199567951 |
| Directory | /workspace/34.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/34.xbar_stress_all_with_rand_reset.4182107347 |
| Short name | T523 |
| Test name | |
| Test status | |
| Simulation time | 5017246216 ps |
| CPU time | 297.84 seconds |
| Started | Aug 12 06:51:35 PM PDT 24 |
| Finished | Aug 12 06:56:33 PM PDT 24 |
| Peak memory | 576532 kb |
| Host | smart-28e29953-e312-43f7-8e5b-c5eface9f9e6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4182107347 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.xbar_stress_all _with_rand_reset.4182107347 |
| Directory | /workspace/34.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/34.xbar_stress_all_with_reset_error.168689419 |
| Short name | T2417 |
| Test name | |
| Test status | |
| Simulation time | 7367341671 ps |
| CPU time | 401.69 seconds |
| Started | Aug 12 06:51:35 PM PDT 24 |
| Finished | Aug 12 06:58:17 PM PDT 24 |
| Peak memory | 576628 kb |
| Host | smart-38447d5b-da4b-461f-b7be-5a9f8c43e900 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=168689419 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.xbar_stress_all _with_reset_error.168689419 |
| Directory | /workspace/34.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/34.xbar_unmapped_addr.2525884599 |
| Short name | T2524 |
| Test name | |
| Test status | |
| Simulation time | 1066830392 ps |
| CPU time | 45.43 seconds |
| Started | Aug 12 06:51:36 PM PDT 24 |
| Finished | Aug 12 06:52:22 PM PDT 24 |
| Peak memory | 575716 kb |
| Host | smart-45cc11df-6dcc-4f32-9959-447617cfe9a3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2525884599 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.xbar_unmapped_addr.2525884599 |
| Directory | /workspace/34.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/35.xbar_access_same_device.1254885889 |
| Short name | T2729 |
| Test name | |
| Test status | |
| Simulation time | 2501525769 ps |
| CPU time | 114.69 seconds |
| Started | Aug 12 06:51:32 PM PDT 24 |
| Finished | Aug 12 06:53:27 PM PDT 24 |
| Peak memory | 575716 kb |
| Host | smart-788a3ce8-c3d8-4d72-a143-cc5e297d607d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1254885889 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.xbar_access_same_device .1254885889 |
| Directory | /workspace/35.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/35.xbar_access_same_device_slow_rsp.55137261 |
| Short name | T1962 |
| Test name | |
| Test status | |
| Simulation time | 114249273365 ps |
| CPU time | 2123.47 seconds |
| Started | Aug 12 06:51:37 PM PDT 24 |
| Finished | Aug 12 07:27:01 PM PDT 24 |
| Peak memory | 575580 kb |
| Host | smart-546df6f1-5e74-4360-a6ea-668443a219b9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=55137261 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.xbar_access_same_de vice_slow_rsp.55137261 |
| Directory | /workspace/35.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/35.xbar_error_and_unmapped_addr.1911649008 |
| Short name | T2506 |
| Test name | |
| Test status | |
| Simulation time | 185436306 ps |
| CPU time | 21.18 seconds |
| Started | Aug 12 06:51:36 PM PDT 24 |
| Finished | Aug 12 06:51:58 PM PDT 24 |
| Peak memory | 575800 kb |
| Host | smart-2e044f47-8ff8-415a-b1e8-63292ba0ae95 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1911649008 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.xbar_error_and_unmapped_add r.1911649008 |
| Directory | /workspace/35.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/35.xbar_error_random.2591332269 |
| Short name | T1473 |
| Test name | |
| Test status | |
| Simulation time | 365765751 ps |
| CPU time | 30.83 seconds |
| Started | Aug 12 06:51:35 PM PDT 24 |
| Finished | Aug 12 06:52:06 PM PDT 24 |
| Peak memory | 575688 kb |
| Host | smart-075eba01-62a4-428c-92c8-5dbd11e014cc |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2591332269 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.xbar_error_random.2591332269 |
| Directory | /workspace/35.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/35.xbar_random.3589482577 |
| Short name | T2199 |
| Test name | |
| Test status | |
| Simulation time | 1181363099 ps |
| CPU time | 38.55 seconds |
| Started | Aug 12 06:51:34 PM PDT 24 |
| Finished | Aug 12 06:52:13 PM PDT 24 |
| Peak memory | 575516 kb |
| Host | smart-c0bf14f7-d64d-41d7-b2aa-b108217e49ba |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3589482577 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.xbar_random.3589482577 |
| Directory | /workspace/35.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/35.xbar_random_large_delays.863223365 |
| Short name | T2502 |
| Test name | |
| Test status | |
| Simulation time | 11033514354 ps |
| CPU time | 117.99 seconds |
| Started | Aug 12 06:51:34 PM PDT 24 |
| Finished | Aug 12 06:53:32 PM PDT 24 |
| Peak memory | 575632 kb |
| Host | smart-f6596db8-067c-4dfe-8c25-7518a39d0928 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=863223365 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.xbar_random_large_delays.863223365 |
| Directory | /workspace/35.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/35.xbar_random_slow_rsp.4278503803 |
| Short name | T689 |
| Test name | |
| Test status | |
| Simulation time | 62968142853 ps |
| CPU time | 1082.53 seconds |
| Started | Aug 12 06:51:35 PM PDT 24 |
| Finished | Aug 12 07:09:38 PM PDT 24 |
| Peak memory | 575852 kb |
| Host | smart-da4f570a-176a-4b7f-ba74-f3e80ca63627 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4278503803 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.xbar_random_slow_rsp.4278503803 |
| Directory | /workspace/35.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/35.xbar_random_zero_delays.2961546209 |
| Short name | T2872 |
| Test name | |
| Test status | |
| Simulation time | 126824342 ps |
| CPU time | 14.14 seconds |
| Started | Aug 12 06:51:35 PM PDT 24 |
| Finished | Aug 12 06:51:50 PM PDT 24 |
| Peak memory | 575664 kb |
| Host | smart-04726c11-c451-4ea8-8fa2-ff30bb22f37c |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2961546209 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.xbar_random_zero_del ays.2961546209 |
| Directory | /workspace/35.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/35.xbar_same_source.3236979296 |
| Short name | T667 |
| Test name | |
| Test status | |
| Simulation time | 300685495 ps |
| CPU time | 26.08 seconds |
| Started | Aug 12 06:51:36 PM PDT 24 |
| Finished | Aug 12 06:52:02 PM PDT 24 |
| Peak memory | 575708 kb |
| Host | smart-395ad72a-9af0-40ea-8b29-b3386c00567f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3236979296 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.xbar_same_source.3236979296 |
| Directory | /workspace/35.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/35.xbar_smoke.1844379328 |
| Short name | T1940 |
| Test name | |
| Test status | |
| Simulation time | 48052956 ps |
| CPU time | 6.37 seconds |
| Started | Aug 12 06:51:35 PM PDT 24 |
| Finished | Aug 12 06:51:42 PM PDT 24 |
| Peak memory | 573584 kb |
| Host | smart-5cbc5575-bb64-4ef3-8331-9e96dd41bbdf |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1844379328 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.xbar_smoke.1844379328 |
| Directory | /workspace/35.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/35.xbar_smoke_large_delays.3940048560 |
| Short name | T2291 |
| Test name | |
| Test status | |
| Simulation time | 9171984620 ps |
| CPU time | 91.19 seconds |
| Started | Aug 12 06:51:34 PM PDT 24 |
| Finished | Aug 12 06:53:05 PM PDT 24 |
| Peak memory | 573644 kb |
| Host | smart-d66307e3-4762-49ab-91ef-31abe8c1e38b |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3940048560 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.xbar_smoke_large_delays.3940048560 |
| Directory | /workspace/35.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/35.xbar_smoke_slow_rsp.526236691 |
| Short name | T1552 |
| Test name | |
| Test status | |
| Simulation time | 6232945628 ps |
| CPU time | 103.9 seconds |
| Started | Aug 12 06:51:35 PM PDT 24 |
| Finished | Aug 12 06:53:19 PM PDT 24 |
| Peak memory | 573636 kb |
| Host | smart-76c7328e-fe8a-477e-8258-f220305de1e9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=526236691 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.xbar_smoke_slow_rsp.526236691 |
| Directory | /workspace/35.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/35.xbar_smoke_zero_delays.2224894791 |
| Short name | T1775 |
| Test name | |
| Test status | |
| Simulation time | 42775863 ps |
| CPU time | 6.06 seconds |
| Started | Aug 12 06:51:36 PM PDT 24 |
| Finished | Aug 12 06:51:42 PM PDT 24 |
| Peak memory | 573632 kb |
| Host | smart-ec06eb46-d0b5-4256-8e65-fdaa9baf9387 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2224894791 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.xbar_smoke_zero_delay s.2224894791 |
| Directory | /workspace/35.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/35.xbar_stress_all.3981020572 |
| Short name | T1952 |
| Test name | |
| Test status | |
| Simulation time | 3299960193 ps |
| CPU time | 141.65 seconds |
| Started | Aug 12 06:51:35 PM PDT 24 |
| Finished | Aug 12 06:53:57 PM PDT 24 |
| Peak memory | 575788 kb |
| Host | smart-949bad3d-3f01-4a75-b864-6f17753cf29c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3981020572 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.xbar_stress_all.3981020572 |
| Directory | /workspace/35.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/35.xbar_stress_all_with_error.1843784802 |
| Short name | T1556 |
| Test name | |
| Test status | |
| Simulation time | 8075052124 ps |
| CPU time | 249.01 seconds |
| Started | Aug 12 06:51:34 PM PDT 24 |
| Finished | Aug 12 06:55:44 PM PDT 24 |
| Peak memory | 575964 kb |
| Host | smart-4e10badc-c89e-49d7-8ea4-6b33ca16e126 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1843784802 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.xbar_stress_all_with_error.1843784802 |
| Directory | /workspace/35.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/35.xbar_stress_all_with_rand_reset.3804242174 |
| Short name | T2226 |
| Test name | |
| Test status | |
| Simulation time | 99548891 ps |
| CPU time | 43.93 seconds |
| Started | Aug 12 06:51:34 PM PDT 24 |
| Finished | Aug 12 06:52:19 PM PDT 24 |
| Peak memory | 576476 kb |
| Host | smart-6c83c3a0-98ec-4a31-bd14-cf5cd65a905a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3804242174 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.xbar_stress_all _with_rand_reset.3804242174 |
| Directory | /workspace/35.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/35.xbar_unmapped_addr.1975177894 |
| Short name | T559 |
| Test name | |
| Test status | |
| Simulation time | 503017032 ps |
| CPU time | 24.1 seconds |
| Started | Aug 12 06:51:32 PM PDT 24 |
| Finished | Aug 12 06:51:56 PM PDT 24 |
| Peak memory | 575628 kb |
| Host | smart-e8daa952-7961-44d3-a05b-36d31c843c7f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1975177894 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.xbar_unmapped_addr.1975177894 |
| Directory | /workspace/35.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/36.xbar_access_same_device.1382649539 |
| Short name | T2617 |
| Test name | |
| Test status | |
| Simulation time | 346485521 ps |
| CPU time | 31.82 seconds |
| Started | Aug 12 06:51:39 PM PDT 24 |
| Finished | Aug 12 06:52:11 PM PDT 24 |
| Peak memory | 575624 kb |
| Host | smart-2251621c-d3b1-4e1e-98c9-25a684426beb |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1382649539 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.xbar_access_same_device .1382649539 |
| Directory | /workspace/36.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/36.xbar_access_same_device_slow_rsp.3673220069 |
| Short name | T917 |
| Test name | |
| Test status | |
| Simulation time | 47744309451 ps |
| CPU time | 743.72 seconds |
| Started | Aug 12 06:51:41 PM PDT 24 |
| Finished | Aug 12 07:04:05 PM PDT 24 |
| Peak memory | 575720 kb |
| Host | smart-c966b57b-bede-43ad-8355-59c71df5f10f |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3673220069 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.xbar_access_same_ device_slow_rsp.3673220069 |
| Directory | /workspace/36.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/36.xbar_error_and_unmapped_addr.1221935466 |
| Short name | T2465 |
| Test name | |
| Test status | |
| Simulation time | 38581524 ps |
| CPU time | 7.05 seconds |
| Started | Aug 12 06:51:36 PM PDT 24 |
| Finished | Aug 12 06:51:43 PM PDT 24 |
| Peak memory | 574328 kb |
| Host | smart-6b0b21d0-91a9-4d55-9070-74c28f5ad1fa |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1221935466 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.xbar_error_and_unmapped_add r.1221935466 |
| Directory | /workspace/36.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/36.xbar_error_random.1367030245 |
| Short name | T2119 |
| Test name | |
| Test status | |
| Simulation time | 805535099 ps |
| CPU time | 28.48 seconds |
| Started | Aug 12 06:51:37 PM PDT 24 |
| Finished | Aug 12 06:52:06 PM PDT 24 |
| Peak memory | 575644 kb |
| Host | smart-1b74ebfe-6439-4c73-aef3-1d4ef58ad77a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1367030245 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.xbar_error_random.1367030245 |
| Directory | /workspace/36.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/36.xbar_random.3350614014 |
| Short name | T2258 |
| Test name | |
| Test status | |
| Simulation time | 170030114 ps |
| CPU time | 16.2 seconds |
| Started | Aug 12 06:51:41 PM PDT 24 |
| Finished | Aug 12 06:51:58 PM PDT 24 |
| Peak memory | 575668 kb |
| Host | smart-240c2a74-937e-4c45-91b8-b97b3a4acb8e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3350614014 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.xbar_random.3350614014 |
| Directory | /workspace/36.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/36.xbar_random_large_delays.3850253484 |
| Short name | T2321 |
| Test name | |
| Test status | |
| Simulation time | 89389259904 ps |
| CPU time | 1061.14 seconds |
| Started | Aug 12 06:51:37 PM PDT 24 |
| Finished | Aug 12 07:09:19 PM PDT 24 |
| Peak memory | 575780 kb |
| Host | smart-ccb8a35f-9cfd-4e5f-aa49-c7f592058b98 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3850253484 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.xbar_random_large_delays.3850253484 |
| Directory | /workspace/36.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/36.xbar_random_slow_rsp.2975567720 |
| Short name | T594 |
| Test name | |
| Test status | |
| Simulation time | 24576143654 ps |
| CPU time | 426.56 seconds |
| Started | Aug 12 06:51:39 PM PDT 24 |
| Finished | Aug 12 06:58:45 PM PDT 24 |
| Peak memory | 575612 kb |
| Host | smart-92f79a7f-c343-4357-ab0c-9ee23113d12a |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2975567720 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.xbar_random_slow_rsp.2975567720 |
| Directory | /workspace/36.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/36.xbar_random_zero_delays.1882197546 |
| Short name | T2459 |
| Test name | |
| Test status | |
| Simulation time | 623493699 ps |
| CPU time | 50.76 seconds |
| Started | Aug 12 06:51:37 PM PDT 24 |
| Finished | Aug 12 06:52:28 PM PDT 24 |
| Peak memory | 575676 kb |
| Host | smart-dcbc4557-46f1-40f1-a9cd-bf0fe3298ee3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1882197546 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.xbar_random_zero_del ays.1882197546 |
| Directory | /workspace/36.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/36.xbar_same_source.1919563518 |
| Short name | T2498 |
| Test name | |
| Test status | |
| Simulation time | 166417137 ps |
| CPU time | 14.67 seconds |
| Started | Aug 12 06:51:38 PM PDT 24 |
| Finished | Aug 12 06:51:52 PM PDT 24 |
| Peak memory | 575488 kb |
| Host | smart-96b6d3c5-03b7-4c41-8582-c77155f620a4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1919563518 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.xbar_same_source.1919563518 |
| Directory | /workspace/36.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/36.xbar_smoke.2431770604 |
| Short name | T2759 |
| Test name | |
| Test status | |
| Simulation time | 54364162 ps |
| CPU time | 6.28 seconds |
| Started | Aug 12 06:51:32 PM PDT 24 |
| Finished | Aug 12 06:51:39 PM PDT 24 |
| Peak memory | 574216 kb |
| Host | smart-fd9af513-6a1f-4b00-ba3d-c40effa332bc |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2431770604 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.xbar_smoke.2431770604 |
| Directory | /workspace/36.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/36.xbar_smoke_large_delays.3984750168 |
| Short name | T2882 |
| Test name | |
| Test status | |
| Simulation time | 7120353222 ps |
| CPU time | 72.73 seconds |
| Started | Aug 12 06:51:33 PM PDT 24 |
| Finished | Aug 12 06:52:46 PM PDT 24 |
| Peak memory | 573716 kb |
| Host | smart-3e6b570f-4fa3-445c-a8ff-a87a72ef9103 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3984750168 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.xbar_smoke_large_delays.3984750168 |
| Directory | /workspace/36.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/36.xbar_smoke_slow_rsp.1269688906 |
| Short name | T1462 |
| Test name | |
| Test status | |
| Simulation time | 4611334856 ps |
| CPU time | 70.38 seconds |
| Started | Aug 12 06:51:38 PM PDT 24 |
| Finished | Aug 12 06:52:49 PM PDT 24 |
| Peak memory | 573620 kb |
| Host | smart-14987267-e552-48a3-9c51-6aa93c80eabc |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1269688906 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.xbar_smoke_slow_rsp.1269688906 |
| Directory | /workspace/36.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/36.xbar_smoke_zero_delays.1530548012 |
| Short name | T2514 |
| Test name | |
| Test status | |
| Simulation time | 55512328 ps |
| CPU time | 7.15 seconds |
| Started | Aug 12 06:51:36 PM PDT 24 |
| Finished | Aug 12 06:51:44 PM PDT 24 |
| Peak memory | 574264 kb |
| Host | smart-4f530d28-1b3a-4121-9562-7298cc5cb059 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1530548012 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.xbar_smoke_zero_delay s.1530548012 |
| Directory | /workspace/36.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/36.xbar_stress_all.1963650203 |
| Short name | T2266 |
| Test name | |
| Test status | |
| Simulation time | 3539639756 ps |
| CPU time | 112.58 seconds |
| Started | Aug 12 06:51:37 PM PDT 24 |
| Finished | Aug 12 06:53:30 PM PDT 24 |
| Peak memory | 575880 kb |
| Host | smart-4eca1cf6-0bd1-4fd1-bc2e-ff8740625dbe |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1963650203 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.xbar_stress_all.1963650203 |
| Directory | /workspace/36.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/36.xbar_stress_all_with_rand_reset.1474204001 |
| Short name | T944 |
| Test name | |
| Test status | |
| Simulation time | 7810889054 ps |
| CPU time | 579.85 seconds |
| Started | Aug 12 06:51:38 PM PDT 24 |
| Finished | Aug 12 07:01:18 PM PDT 24 |
| Peak memory | 575760 kb |
| Host | smart-7ae195e1-d948-4755-9ff4-e03ce69d0fde |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1474204001 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.xbar_stress_all _with_rand_reset.1474204001 |
| Directory | /workspace/36.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/36.xbar_stress_all_with_reset_error.792974926 |
| Short name | T2912 |
| Test name | |
| Test status | |
| Simulation time | 2752968365 ps |
| CPU time | 310.18 seconds |
| Started | Aug 12 06:51:37 PM PDT 24 |
| Finished | Aug 12 06:56:48 PM PDT 24 |
| Peak memory | 575756 kb |
| Host | smart-08a32f45-06bb-4a58-bffe-9990f1229961 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=792974926 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.xbar_stress_all _with_reset_error.792974926 |
| Directory | /workspace/36.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/36.xbar_unmapped_addr.1004334456 |
| Short name | T635 |
| Test name | |
| Test status | |
| Simulation time | 1217328301 ps |
| CPU time | 49.46 seconds |
| Started | Aug 12 06:51:39 PM PDT 24 |
| Finished | Aug 12 06:52:29 PM PDT 24 |
| Peak memory | 575600 kb |
| Host | smart-f9bd987b-2ef1-40f1-8713-86417abdac06 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1004334456 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.xbar_unmapped_addr.1004334456 |
| Directory | /workspace/36.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/37.xbar_access_same_device.3958229931 |
| Short name | T2724 |
| Test name | |
| Test status | |
| Simulation time | 161197869 ps |
| CPU time | 12.14 seconds |
| Started | Aug 12 06:51:41 PM PDT 24 |
| Finished | Aug 12 06:51:53 PM PDT 24 |
| Peak memory | 575616 kb |
| Host | smart-980ce9d9-3dc6-4ad8-8dc4-e6e6440e7a79 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3958229931 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.xbar_access_same_device .3958229931 |
| Directory | /workspace/37.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/37.xbar_access_same_device_slow_rsp.2754115546 |
| Short name | T2389 |
| Test name | |
| Test status | |
| Simulation time | 25014900046 ps |
| CPU time | 422.37 seconds |
| Started | Aug 12 06:51:42 PM PDT 24 |
| Finished | Aug 12 06:58:45 PM PDT 24 |
| Peak memory | 575784 kb |
| Host | smart-226cb303-662d-489c-aa74-dda298d64fc3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2754115546 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.xbar_access_same_ device_slow_rsp.2754115546 |
| Directory | /workspace/37.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/37.xbar_error_and_unmapped_addr.66396873 |
| Short name | T2829 |
| Test name | |
| Test status | |
| Simulation time | 209504427 ps |
| CPU time | 23.71 seconds |
| Started | Aug 12 06:51:42 PM PDT 24 |
| Finished | Aug 12 06:52:05 PM PDT 24 |
| Peak memory | 575748 kb |
| Host | smart-775e8dee-ac8c-4bdb-adea-8caf24dae524 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=66396873 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.xbar_error_and_unmapped_addr.66396873 |
| Directory | /workspace/37.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/37.xbar_error_random.2035760398 |
| Short name | T2751 |
| Test name | |
| Test status | |
| Simulation time | 320573166 ps |
| CPU time | 28.75 seconds |
| Started | Aug 12 06:51:41 PM PDT 24 |
| Finished | Aug 12 06:52:10 PM PDT 24 |
| Peak memory | 575680 kb |
| Host | smart-7c3a426a-7408-4cf5-9b98-0e7ef1d967ba |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2035760398 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.xbar_error_random.2035760398 |
| Directory | /workspace/37.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/37.xbar_random.3712004292 |
| Short name | T654 |
| Test name | |
| Test status | |
| Simulation time | 1039277351 ps |
| CPU time | 36.29 seconds |
| Started | Aug 12 06:51:37 PM PDT 24 |
| Finished | Aug 12 06:52:14 PM PDT 24 |
| Peak memory | 575560 kb |
| Host | smart-46e96c84-bf19-481b-ba50-4c4c2b1fc48a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3712004292 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.xbar_random.3712004292 |
| Directory | /workspace/37.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/37.xbar_random_large_delays.2117053331 |
| Short name | T1868 |
| Test name | |
| Test status | |
| Simulation time | 44254378562 ps |
| CPU time | 492.57 seconds |
| Started | Aug 12 06:51:38 PM PDT 24 |
| Finished | Aug 12 06:59:51 PM PDT 24 |
| Peak memory | 575728 kb |
| Host | smart-66efb45b-012a-45cb-91be-5e7b0ffc4a26 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2117053331 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.xbar_random_large_delays.2117053331 |
| Directory | /workspace/37.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/37.xbar_random_slow_rsp.659846203 |
| Short name | T1983 |
| Test name | |
| Test status | |
| Simulation time | 12785772654 ps |
| CPU time | 208.16 seconds |
| Started | Aug 12 06:51:41 PM PDT 24 |
| Finished | Aug 12 06:55:10 PM PDT 24 |
| Peak memory | 575804 kb |
| Host | smart-9ed75f27-697a-4a74-9f18-d6c3d249199c |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=659846203 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.xbar_random_slow_rsp.659846203 |
| Directory | /workspace/37.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/37.xbar_random_zero_delays.1812673255 |
| Short name | T2812 |
| Test name | |
| Test status | |
| Simulation time | 473684279 ps |
| CPU time | 40.15 seconds |
| Started | Aug 12 06:51:37 PM PDT 24 |
| Finished | Aug 12 06:52:17 PM PDT 24 |
| Peak memory | 575552 kb |
| Host | smart-059784a4-556f-48de-aa3f-88c062d00218 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1812673255 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.xbar_random_zero_del ays.1812673255 |
| Directory | /workspace/37.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/37.xbar_same_source.2080202955 |
| Short name | T2251 |
| Test name | |
| Test status | |
| Simulation time | 568432686 ps |
| CPU time | 39.54 seconds |
| Started | Aug 12 06:51:35 PM PDT 24 |
| Finished | Aug 12 06:52:15 PM PDT 24 |
| Peak memory | 575612 kb |
| Host | smart-21bf1ed1-8da3-41f4-885c-72586238c0f3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2080202955 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.xbar_same_source.2080202955 |
| Directory | /workspace/37.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/37.xbar_smoke.1881277266 |
| Short name | T1496 |
| Test name | |
| Test status | |
| Simulation time | 217358617 ps |
| CPU time | 8.81 seconds |
| Started | Aug 12 06:51:41 PM PDT 24 |
| Finished | Aug 12 06:51:50 PM PDT 24 |
| Peak memory | 573704 kb |
| Host | smart-1d4b5790-d4b5-4820-a387-7c3a3c1478b6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1881277266 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.xbar_smoke.1881277266 |
| Directory | /workspace/37.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/37.xbar_smoke_large_delays.2998566640 |
| Short name | T1544 |
| Test name | |
| Test status | |
| Simulation time | 10586284585 ps |
| CPU time | 111.68 seconds |
| Started | Aug 12 06:51:38 PM PDT 24 |
| Finished | Aug 12 06:53:30 PM PDT 24 |
| Peak memory | 573684 kb |
| Host | smart-2d8a00ea-a9cd-4731-982e-0b4cdbebc847 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2998566640 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.xbar_smoke_large_delays.2998566640 |
| Directory | /workspace/37.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/37.xbar_smoke_slow_rsp.958130229 |
| Short name | T682 |
| Test name | |
| Test status | |
| Simulation time | 5310404716 ps |
| CPU time | 83.54 seconds |
| Started | Aug 12 06:51:39 PM PDT 24 |
| Finished | Aug 12 06:53:02 PM PDT 24 |
| Peak memory | 573676 kb |
| Host | smart-4a80f4c6-9884-4c7b-922e-644463e00ac7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=958130229 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.xbar_smoke_slow_rsp.958130229 |
| Directory | /workspace/37.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/37.xbar_smoke_zero_delays.2280586701 |
| Short name | T1970 |
| Test name | |
| Test status | |
| Simulation time | 48322326 ps |
| CPU time | 6.73 seconds |
| Started | Aug 12 06:51:37 PM PDT 24 |
| Finished | Aug 12 06:51:44 PM PDT 24 |
| Peak memory | 574232 kb |
| Host | smart-0e7a015a-280b-48b2-b48c-8dc6b8df9b55 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2280586701 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.xbar_smoke_zero_delay s.2280586701 |
| Directory | /workspace/37.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/37.xbar_stress_all.1458669797 |
| Short name | T2509 |
| Test name | |
| Test status | |
| Simulation time | 3435009746 ps |
| CPU time | 115.4 seconds |
| Started | Aug 12 06:51:41 PM PDT 24 |
| Finished | Aug 12 06:53:37 PM PDT 24 |
| Peak memory | 575760 kb |
| Host | smart-9ea418c5-5898-4545-97c0-ba7bc792dd46 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1458669797 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.xbar_stress_all.1458669797 |
| Directory | /workspace/37.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/37.xbar_stress_all_with_error.1225613054 |
| Short name | T1694 |
| Test name | |
| Test status | |
| Simulation time | 3895585463 ps |
| CPU time | 127.4 seconds |
| Started | Aug 12 06:51:42 PM PDT 24 |
| Finished | Aug 12 06:53:50 PM PDT 24 |
| Peak memory | 575760 kb |
| Host | smart-4a813e6d-c32b-47d8-ba3e-f347f809b165 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1225613054 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.xbar_stress_all_with_error.1225613054 |
| Directory | /workspace/37.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/37.xbar_stress_all_with_rand_reset.3716339007 |
| Short name | T2758 |
| Test name | |
| Test status | |
| Simulation time | 125549402 ps |
| CPU time | 42.01 seconds |
| Started | Aug 12 06:51:42 PM PDT 24 |
| Finished | Aug 12 06:52:25 PM PDT 24 |
| Peak memory | 576448 kb |
| Host | smart-3f6f45f0-dca8-4934-9bd8-e38b42355fe3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3716339007 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.xbar_stress_all _with_rand_reset.3716339007 |
| Directory | /workspace/37.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/37.xbar_stress_all_with_reset_error.1830344856 |
| Short name | T931 |
| Test name | |
| Test status | |
| Simulation time | 583051342 ps |
| CPU time | 207.19 seconds |
| Started | Aug 12 06:51:41 PM PDT 24 |
| Finished | Aug 12 06:55:09 PM PDT 24 |
| Peak memory | 576520 kb |
| Host | smart-e9f02ae6-f5ef-4c32-b159-18d5fd4226d7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1830344856 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.xbar_stress_al l_with_reset_error.1830344856 |
| Directory | /workspace/37.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/37.xbar_unmapped_addr.2013643775 |
| Short name | T2379 |
| Test name | |
| Test status | |
| Simulation time | 277690537 ps |
| CPU time | 32.04 seconds |
| Started | Aug 12 06:51:42 PM PDT 24 |
| Finished | Aug 12 06:52:14 PM PDT 24 |
| Peak memory | 575708 kb |
| Host | smart-6d3a3349-5588-4da0-8630-239a65cd8a45 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2013643775 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.xbar_unmapped_addr.2013643775 |
| Directory | /workspace/37.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/38.xbar_access_same_device.295565344 |
| Short name | T1585 |
| Test name | |
| Test status | |
| Simulation time | 884128733 ps |
| CPU time | 39.9 seconds |
| Started | Aug 12 06:51:42 PM PDT 24 |
| Finished | Aug 12 06:52:22 PM PDT 24 |
| Peak memory | 575600 kb |
| Host | smart-982a1847-3506-4b23-a9a7-a1e049526e89 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=295565344 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.xbar_access_same_device. 295565344 |
| Directory | /workspace/38.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/38.xbar_access_same_device_slow_rsp.2378360838 |
| Short name | T2681 |
| Test name | |
| Test status | |
| Simulation time | 45756643031 ps |
| CPU time | 721 seconds |
| Started | Aug 12 06:51:44 PM PDT 24 |
| Finished | Aug 12 07:03:46 PM PDT 24 |
| Peak memory | 575808 kb |
| Host | smart-5f4bbb9e-c617-4ea0-b016-3026cbefb228 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2378360838 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.xbar_access_same_ device_slow_rsp.2378360838 |
| Directory | /workspace/38.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/38.xbar_error_and_unmapped_addr.2342499236 |
| Short name | T1627 |
| Test name | |
| Test status | |
| Simulation time | 261161036 ps |
| CPU time | 13.73 seconds |
| Started | Aug 12 06:51:46 PM PDT 24 |
| Finished | Aug 12 06:52:00 PM PDT 24 |
| Peak memory | 575728 kb |
| Host | smart-25b4b5d5-ccbb-4892-9799-11de75a633e4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2342499236 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.xbar_error_and_unmapped_add r.2342499236 |
| Directory | /workspace/38.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/38.xbar_error_random.2771403243 |
| Short name | T1649 |
| Test name | |
| Test status | |
| Simulation time | 552222691 ps |
| CPU time | 41.63 seconds |
| Started | Aug 12 06:51:43 PM PDT 24 |
| Finished | Aug 12 06:52:25 PM PDT 24 |
| Peak memory | 575752 kb |
| Host | smart-364017ac-31c1-48a9-80ee-29c280dbf7aa |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2771403243 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.xbar_error_random.2771403243 |
| Directory | /workspace/38.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/38.xbar_random.1034175156 |
| Short name | T578 |
| Test name | |
| Test status | |
| Simulation time | 720331719 ps |
| CPU time | 26.8 seconds |
| Started | Aug 12 06:51:44 PM PDT 24 |
| Finished | Aug 12 06:52:11 PM PDT 24 |
| Peak memory | 575508 kb |
| Host | smart-534e74d4-bb4d-4731-9333-66d2796dc9e6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1034175156 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.xbar_random.1034175156 |
| Directory | /workspace/38.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/38.xbar_random_large_delays.1812242293 |
| Short name | T1929 |
| Test name | |
| Test status | |
| Simulation time | 65692765108 ps |
| CPU time | 723.22 seconds |
| Started | Aug 12 06:51:42 PM PDT 24 |
| Finished | Aug 12 07:03:45 PM PDT 24 |
| Peak memory | 575732 kb |
| Host | smart-18c1a01f-5a77-4b0b-bd1c-1fb4fa35a310 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1812242293 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.xbar_random_large_delays.1812242293 |
| Directory | /workspace/38.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/38.xbar_random_slow_rsp.1288165715 |
| Short name | T2688 |
| Test name | |
| Test status | |
| Simulation time | 21966835416 ps |
| CPU time | 342.28 seconds |
| Started | Aug 12 06:51:44 PM PDT 24 |
| Finished | Aug 12 06:57:26 PM PDT 24 |
| Peak memory | 575716 kb |
| Host | smart-306da093-4d2a-4450-94bf-5341254460a0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1288165715 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.xbar_random_slow_rsp.1288165715 |
| Directory | /workspace/38.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/38.xbar_random_zero_delays.334933485 |
| Short name | T611 |
| Test name | |
| Test status | |
| Simulation time | 443033406 ps |
| CPU time | 36.31 seconds |
| Started | Aug 12 06:51:44 PM PDT 24 |
| Finished | Aug 12 06:52:21 PM PDT 24 |
| Peak memory | 575692 kb |
| Host | smart-e4f2daa3-009d-4f74-9d12-aa4ea83463d8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=334933485 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.xbar_random_zero_dela ys.334933485 |
| Directory | /workspace/38.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/38.xbar_same_source.2179759160 |
| Short name | T2720 |
| Test name | |
| Test status | |
| Simulation time | 1868781114 ps |
| CPU time | 53.86 seconds |
| Started | Aug 12 06:51:43 PM PDT 24 |
| Finished | Aug 12 06:52:37 PM PDT 24 |
| Peak memory | 575564 kb |
| Host | smart-f69c9efd-ee98-440f-817e-cf5f3a08acf3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2179759160 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.xbar_same_source.2179759160 |
| Directory | /workspace/38.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/38.xbar_smoke.2092920024 |
| Short name | T1740 |
| Test name | |
| Test status | |
| Simulation time | 222008475 ps |
| CPU time | 9.55 seconds |
| Started | Aug 12 06:51:42 PM PDT 24 |
| Finished | Aug 12 06:51:52 PM PDT 24 |
| Peak memory | 573588 kb |
| Host | smart-fae72800-0ff1-40a3-ae7b-b82b2c12ed14 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2092920024 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.xbar_smoke.2092920024 |
| Directory | /workspace/38.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/38.xbar_smoke_large_delays.1200047268 |
| Short name | T2349 |
| Test name | |
| Test status | |
| Simulation time | 7224626507 ps |
| CPU time | 72.07 seconds |
| Started | Aug 12 06:51:44 PM PDT 24 |
| Finished | Aug 12 06:52:56 PM PDT 24 |
| Peak memory | 573648 kb |
| Host | smart-7ce977b5-7dad-4856-b776-7de231d1a5e6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1200047268 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.xbar_smoke_large_delays.1200047268 |
| Directory | /workspace/38.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/38.xbar_smoke_slow_rsp.1078383764 |
| Short name | T2804 |
| Test name | |
| Test status | |
| Simulation time | 5556464360 ps |
| CPU time | 87.94 seconds |
| Started | Aug 12 06:51:42 PM PDT 24 |
| Finished | Aug 12 06:53:10 PM PDT 24 |
| Peak memory | 573680 kb |
| Host | smart-addd7373-6084-4010-a1d3-1a627577e9dc |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1078383764 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.xbar_smoke_slow_rsp.1078383764 |
| Directory | /workspace/38.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/38.xbar_smoke_zero_delays.3032629747 |
| Short name | T2169 |
| Test name | |
| Test status | |
| Simulation time | 38725839 ps |
| CPU time | 5.46 seconds |
| Started | Aug 12 06:51:44 PM PDT 24 |
| Finished | Aug 12 06:51:50 PM PDT 24 |
| Peak memory | 573580 kb |
| Host | smart-c6b7a952-3fce-4fe4-a92f-b63aadf75b13 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3032629747 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.xbar_smoke_zero_delay s.3032629747 |
| Directory | /workspace/38.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/38.xbar_stress_all.2842884503 |
| Short name | T713 |
| Test name | |
| Test status | |
| Simulation time | 280074804 ps |
| CPU time | 34.38 seconds |
| Started | Aug 12 06:51:47 PM PDT 24 |
| Finished | Aug 12 06:52:22 PM PDT 24 |
| Peak memory | 575816 kb |
| Host | smart-d801418c-a794-4844-956b-7f72b23a0df3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2842884503 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.xbar_stress_all.2842884503 |
| Directory | /workspace/38.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/38.xbar_stress_all_with_error.1205854676 |
| Short name | T2242 |
| Test name | |
| Test status | |
| Simulation time | 2149348491 ps |
| CPU time | 159.12 seconds |
| Started | Aug 12 06:51:47 PM PDT 24 |
| Finished | Aug 12 06:54:26 PM PDT 24 |
| Peak memory | 575744 kb |
| Host | smart-d23e49d2-8246-4c5c-8df6-8cd009773478 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1205854676 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.xbar_stress_all_with_error.1205854676 |
| Directory | /workspace/38.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/38.xbar_stress_all_with_reset_error.875663543 |
| Short name | T2330 |
| Test name | |
| Test status | |
| Simulation time | 506777370 ps |
| CPU time | 188.35 seconds |
| Started | Aug 12 06:51:47 PM PDT 24 |
| Finished | Aug 12 06:54:55 PM PDT 24 |
| Peak memory | 575720 kb |
| Host | smart-bd79dad5-226a-47c3-8a21-a6a0fdeeddf0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=875663543 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.xbar_stress_all _with_reset_error.875663543 |
| Directory | /workspace/38.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/38.xbar_unmapped_addr.3521584737 |
| Short name | T512 |
| Test name | |
| Test status | |
| Simulation time | 1020303911 ps |
| CPU time | 44.47 seconds |
| Started | Aug 12 06:51:43 PM PDT 24 |
| Finished | Aug 12 06:52:28 PM PDT 24 |
| Peak memory | 575632 kb |
| Host | smart-b2ca50c5-be93-4791-b7b6-1df28b43a21a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3521584737 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.xbar_unmapped_addr.3521584737 |
| Directory | /workspace/38.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/39.xbar_access_same_device.3384387317 |
| Short name | T924 |
| Test name | |
| Test status | |
| Simulation time | 290873049 ps |
| CPU time | 22.86 seconds |
| Started | Aug 12 06:51:46 PM PDT 24 |
| Finished | Aug 12 06:52:09 PM PDT 24 |
| Peak memory | 575536 kb |
| Host | smart-417c8540-8aba-4a42-bdb2-19d1f342bcc2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3384387317 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.xbar_access_same_device .3384387317 |
| Directory | /workspace/39.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/39.xbar_access_same_device_slow_rsp.338721397 |
| Short name | T2923 |
| Test name | |
| Test status | |
| Simulation time | 22085100140 ps |
| CPU time | 343.98 seconds |
| Started | Aug 12 06:51:46 PM PDT 24 |
| Finished | Aug 12 06:57:30 PM PDT 24 |
| Peak memory | 575816 kb |
| Host | smart-f64c348f-f349-4fc8-b35c-9fa670e6ced7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=338721397 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.xbar_access_same_d evice_slow_rsp.338721397 |
| Directory | /workspace/39.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/39.xbar_error_and_unmapped_addr.991217251 |
| Short name | T2575 |
| Test name | |
| Test status | |
| Simulation time | 213980398 ps |
| CPU time | 20.86 seconds |
| Started | Aug 12 06:51:47 PM PDT 24 |
| Finished | Aug 12 06:52:08 PM PDT 24 |
| Peak memory | 575724 kb |
| Host | smart-62d854f9-ecb1-436e-aae1-a5fd1e7ff57e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=991217251 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.xbar_error_and_unmapped_addr .991217251 |
| Directory | /workspace/39.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/39.xbar_error_random.1854164636 |
| Short name | T1485 |
| Test name | |
| Test status | |
| Simulation time | 211762252 ps |
| CPU time | 9.75 seconds |
| Started | Aug 12 06:51:44 PM PDT 24 |
| Finished | Aug 12 06:51:54 PM PDT 24 |
| Peak memory | 575684 kb |
| Host | smart-252de4bc-7a32-4a18-bd1d-4ed67f909416 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1854164636 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.xbar_error_random.1854164636 |
| Directory | /workspace/39.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/39.xbar_random.2125843393 |
| Short name | T2894 |
| Test name | |
| Test status | |
| Simulation time | 1707477384 ps |
| CPU time | 51.43 seconds |
| Started | Aug 12 06:51:44 PM PDT 24 |
| Finished | Aug 12 06:52:36 PM PDT 24 |
| Peak memory | 575624 kb |
| Host | smart-c720f89e-2504-4f5f-9eb4-ad30a0b43914 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2125843393 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.xbar_random.2125843393 |
| Directory | /workspace/39.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/39.xbar_random_large_delays.4119197361 |
| Short name | T2930 |
| Test name | |
| Test status | |
| Simulation time | 84752696905 ps |
| CPU time | 907.58 seconds |
| Started | Aug 12 06:51:36 PM PDT 24 |
| Finished | Aug 12 07:06:44 PM PDT 24 |
| Peak memory | 575724 kb |
| Host | smart-1891e239-1b90-459a-9df2-84f5c623faaf |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4119197361 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.xbar_random_large_delays.4119197361 |
| Directory | /workspace/39.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/39.xbar_random_slow_rsp.2762146963 |
| Short name | T2738 |
| Test name | |
| Test status | |
| Simulation time | 3185954242 ps |
| CPU time | 55.4 seconds |
| Started | Aug 12 06:51:43 PM PDT 24 |
| Finished | Aug 12 06:52:38 PM PDT 24 |
| Peak memory | 573720 kb |
| Host | smart-d9eb8ede-3110-4c2e-a888-f3ae20205539 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2762146963 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.xbar_random_slow_rsp.2762146963 |
| Directory | /workspace/39.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/39.xbar_random_zero_delays.3948136878 |
| Short name | T2491 |
| Test name | |
| Test status | |
| Simulation time | 454962713 ps |
| CPU time | 38.97 seconds |
| Started | Aug 12 06:51:43 PM PDT 24 |
| Finished | Aug 12 06:52:22 PM PDT 24 |
| Peak memory | 575548 kb |
| Host | smart-81b0ae57-82a6-4aef-8c9c-98c56d90dd3d |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3948136878 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.xbar_random_zero_del ays.3948136878 |
| Directory | /workspace/39.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/39.xbar_same_source.1828028051 |
| Short name | T734 |
| Test name | |
| Test status | |
| Simulation time | 970945229 ps |
| CPU time | 31.06 seconds |
| Started | Aug 12 06:51:47 PM PDT 24 |
| Finished | Aug 12 06:52:18 PM PDT 24 |
| Peak memory | 575712 kb |
| Host | smart-8a1dab88-f356-4b06-bfcb-948ecc4894e2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1828028051 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.xbar_same_source.1828028051 |
| Directory | /workspace/39.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/39.xbar_smoke.3180936401 |
| Short name | T2472 |
| Test name | |
| Test status | |
| Simulation time | 171302003 ps |
| CPU time | 8.11 seconds |
| Started | Aug 12 06:51:44 PM PDT 24 |
| Finished | Aug 12 06:51:53 PM PDT 24 |
| Peak memory | 574252 kb |
| Host | smart-27b0e55d-4dd6-4162-81d9-37f1a111301d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3180936401 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.xbar_smoke.3180936401 |
| Directory | /workspace/39.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/39.xbar_smoke_large_delays.2335413751 |
| Short name | T1686 |
| Test name | |
| Test status | |
| Simulation time | 7154086313 ps |
| CPU time | 79.39 seconds |
| Started | Aug 12 06:51:46 PM PDT 24 |
| Finished | Aug 12 06:53:06 PM PDT 24 |
| Peak memory | 573640 kb |
| Host | smart-82168b12-4718-49d9-9f8b-f0e131b9aef2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2335413751 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.xbar_smoke_large_delays.2335413751 |
| Directory | /workspace/39.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/39.xbar_smoke_slow_rsp.1208748795 |
| Short name | T2485 |
| Test name | |
| Test status | |
| Simulation time | 4364575513 ps |
| CPU time | 69.17 seconds |
| Started | Aug 12 06:51:43 PM PDT 24 |
| Finished | Aug 12 06:52:53 PM PDT 24 |
| Peak memory | 574344 kb |
| Host | smart-c8fc3b50-00b0-4bd9-95a8-c2a33c0b30e8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1208748795 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.xbar_smoke_slow_rsp.1208748795 |
| Directory | /workspace/39.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/39.xbar_smoke_zero_delays.736269687 |
| Short name | T1787 |
| Test name | |
| Test status | |
| Simulation time | 54178072 ps |
| CPU time | 6.06 seconds |
| Started | Aug 12 06:51:44 PM PDT 24 |
| Finished | Aug 12 06:51:50 PM PDT 24 |
| Peak memory | 573556 kb |
| Host | smart-9fd7c527-bcac-4395-8d79-df278b9c061a |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=736269687 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.xbar_smoke_zero_delays .736269687 |
| Directory | /workspace/39.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/39.xbar_stress_all.4268560581 |
| Short name | T497 |
| Test name | |
| Test status | |
| Simulation time | 2416379487 ps |
| CPU time | 72.33 seconds |
| Started | Aug 12 06:51:44 PM PDT 24 |
| Finished | Aug 12 06:52:57 PM PDT 24 |
| Peak memory | 575728 kb |
| Host | smart-6f7c4992-d44d-496b-b7e7-9428cae28d1b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4268560581 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.xbar_stress_all.4268560581 |
| Directory | /workspace/39.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/39.xbar_stress_all_with_rand_reset.3166864211 |
| Short name | T1961 |
| Test name | |
| Test status | |
| Simulation time | 189171476 ps |
| CPU time | 103.47 seconds |
| Started | Aug 12 06:51:44 PM PDT 24 |
| Finished | Aug 12 06:53:28 PM PDT 24 |
| Peak memory | 576500 kb |
| Host | smart-ca8e2582-f105-4208-b19a-e271e6e74e83 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3166864211 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.xbar_stress_all _with_rand_reset.3166864211 |
| Directory | /workspace/39.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/39.xbar_stress_all_with_reset_error.1490718085 |
| Short name | T1852 |
| Test name | |
| Test status | |
| Simulation time | 3905977084 ps |
| CPU time | 448.94 seconds |
| Started | Aug 12 06:51:47 PM PDT 24 |
| Finished | Aug 12 06:59:16 PM PDT 24 |
| Peak memory | 576660 kb |
| Host | smart-c9dddd09-3d8d-45e4-a293-8f818aefdcd7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1490718085 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.xbar_stress_al l_with_reset_error.1490718085 |
| Directory | /workspace/39.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/39.xbar_unmapped_addr.2669569887 |
| Short name | T2457 |
| Test name | |
| Test status | |
| Simulation time | 925370815 ps |
| CPU time | 37.79 seconds |
| Started | Aug 12 06:51:46 PM PDT 24 |
| Finished | Aug 12 06:52:24 PM PDT 24 |
| Peak memory | 575648 kb |
| Host | smart-03ff16a2-6dcc-4504-ab56-c2d9ebc9e67c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2669569887 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.xbar_unmapped_addr.2669569887 |
| Directory | /workspace/39.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/4.chip_csr_aliasing.3197196718 |
| Short name | T2684 |
| Test name | |
| Test status | |
| Simulation time | 31558741241 ps |
| CPU time | 5830.88 seconds |
| Started | Aug 12 06:47:19 PM PDT 24 |
| Finished | Aug 12 08:24:30 PM PDT 24 |
| Peak memory | 594172 kb |
| Host | smart-3adf2fa0-8b61-4af6-976c-1ed8a89bf0ad |
| User | root |
| Command | /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +csr_aliasing +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3197196718 -assert nopostproc +UVM_TESTNAME=chip_ base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/ null -cm_name 4.chip_csr_aliasing.3197196718 |
| Directory | /workspace/4.chip_csr_aliasing/latest |
| Test location | /workspace/coverage/cover_reg_top/4.chip_csr_bit_bash.1788182954 |
| Short name | T2373 |
| Test name | |
| Test status | |
| Simulation time | 58131825280 ps |
| CPU time | 5672.32 seconds |
| Started | Aug 12 06:47:18 PM PDT 24 |
| Finished | Aug 12 08:21:51 PM PDT 24 |
| Peak memory | 593680 kb |
| Host | smart-7602dd20-6220-4fd9-924d-9c8ee4bc769b |
| User | root |
| Command | /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +num_test_csrs=200 +csr_bit_bash +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1788182954 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to p.vdb -cm_log /dev/null -cm_name 4.chip_csr_bit_bash.1788182954 |
| Directory | /workspace/4.chip_csr_bit_bash/latest |
| Test location | /workspace/coverage/cover_reg_top/4.chip_csr_hw_reset.2093210698 |
| Short name | T150 |
| Test name | |
| Test status | |
| Simulation time | 6691214396 ps |
| CPU time | 389.09 seconds |
| Started | Aug 12 06:47:26 PM PDT 24 |
| Finished | Aug 12 06:53:55 PM PDT 24 |
| Peak memory | 663748 kb |
| Host | smart-54dabac1-5937-46e4-9c32-2cde662a71b7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2093210698 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.chip_csr_hw_r eset.2093210698 |
| Directory | /workspace/4.chip_csr_hw_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/4.chip_csr_mem_rw_with_rand_reset.3084020983 |
| Short name | T2386 |
| Test name | |
| Test status | |
| Simulation time | 10520958480 ps |
| CPU time | 761.61 seconds |
| Started | Aug 12 06:47:23 PM PDT 24 |
| Finished | Aug 12 07:00:05 PM PDT 24 |
| Peak memory | 652244 kb |
| Host | smart-b2e5a1a6-f50a-4be0-b8d7-9e083b9cfcf6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3084020983 -assert nopostproc + UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top .vdb -cm_log /dev/null -cm_name 4.chip_csr_mem_rw_with_rand_reset.3084020983 |
| Directory | /workspace/4.chip_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/4.chip_csr_rw.988072006 |
| Short name | T2411 |
| Test name | |
| Test status | |
| Simulation time | 3770341896 ps |
| CPU time | 322.61 seconds |
| Started | Aug 12 06:47:25 PM PDT 24 |
| Finished | Aug 12 06:52:48 PM PDT 24 |
| Peak memory | 597724 kb |
| Host | smart-6b62403f-2e04-4c14-988d-8dabe03686e7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=988072006 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.chip_csr_rw.988072006 |
| Directory | /workspace/4.chip_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/4.chip_same_csr_outstanding.1835484303 |
| Short name | T2210 |
| Test name | |
| Test status | |
| Simulation time | 26054173254 ps |
| CPU time | 4194.03 seconds |
| Started | Aug 12 06:47:17 PM PDT 24 |
| Finished | Aug 12 07:57:12 PM PDT 24 |
| Peak memory | 592804 kb |
| Host | smart-f53839f6-98ef-4700-96ce-fbc58d38211c |
| User | root |
| Command | /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +run_same_csr_outstanding +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1835484303 -assert nopostproc +UVM_TE STNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb - cm_log /dev/null -cm_name 4.chip_same_csr_outstanding.1835484303 |
| Directory | /workspace/4.chip_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/4.chip_tl_errors.472443995 |
| Short name | T2796 |
| Test name | |
| Test status | |
| Simulation time | 3785360100 ps |
| CPU time | 408.37 seconds |
| Started | Aug 12 06:47:17 PM PDT 24 |
| Finished | Aug 12 06:54:05 PM PDT 24 |
| Peak memory | 598308 kb |
| Host | smart-159d4964-03b7-431b-8418-7c6a566d4e04 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=472443995 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.chip_tl_errors.472443995 |
| Directory | /workspace/4.chip_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/4.xbar_access_same_device.1390858619 |
| Short name | T1621 |
| Test name | |
| Test status | |
| Simulation time | 288383237 ps |
| CPU time | 32.48 seconds |
| Started | Aug 12 06:47:18 PM PDT 24 |
| Finished | Aug 12 06:47:50 PM PDT 24 |
| Peak memory | 575704 kb |
| Host | smart-f8ca726c-2031-487f-90ce-fbfdd25c2aef |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1390858619 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.xbar_access_same_device. 1390858619 |
| Directory | /workspace/4.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/4.xbar_access_same_device_slow_rsp.1394843528 |
| Short name | T2527 |
| Test name | |
| Test status | |
| Simulation time | 59524474697 ps |
| CPU time | 1027.01 seconds |
| Started | Aug 12 06:47:21 PM PDT 24 |
| Finished | Aug 12 07:04:28 PM PDT 24 |
| Peak memory | 575800 kb |
| Host | smart-c88d7fa0-ebef-4f7b-bf80-736750a3a91c |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1394843528 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.xbar_access_same_d evice_slow_rsp.1394843528 |
| Directory | /workspace/4.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/4.xbar_error_and_unmapped_addr.1317582107 |
| Short name | T2162 |
| Test name | |
| Test status | |
| Simulation time | 1064726040 ps |
| CPU time | 39.74 seconds |
| Started | Aug 12 06:47:26 PM PDT 24 |
| Finished | Aug 12 06:48:06 PM PDT 24 |
| Peak memory | 575584 kb |
| Host | smart-36201000-d998-4670-ba75-090a7c753f91 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1317582107 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.xbar_error_and_unmapped_addr .1317582107 |
| Directory | /workspace/4.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/4.xbar_error_random.485965676 |
| Short name | T2458 |
| Test name | |
| Test status | |
| Simulation time | 157199909 ps |
| CPU time | 15.3 seconds |
| Started | Aug 12 06:47:28 PM PDT 24 |
| Finished | Aug 12 06:47:43 PM PDT 24 |
| Peak memory | 575496 kb |
| Host | smart-348c585e-6063-4300-aa2e-4a4cab8c0914 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=485965676 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.xbar_error_random.485965676 |
| Directory | /workspace/4.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/4.xbar_random.776778544 |
| Short name | T495 |
| Test name | |
| Test status | |
| Simulation time | 443026028 ps |
| CPU time | 37.07 seconds |
| Started | Aug 12 06:47:20 PM PDT 24 |
| Finished | Aug 12 06:47:58 PM PDT 24 |
| Peak memory | 575644 kb |
| Host | smart-8264a047-72c9-4dc9-aa6e-7cb303323fde |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=776778544 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.xbar_random.776778544 |
| Directory | /workspace/4.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/4.xbar_random_large_delays.1131020236 |
| Short name | T1829 |
| Test name | |
| Test status | |
| Simulation time | 6527181073 ps |
| CPU time | 64.11 seconds |
| Started | Aug 12 06:47:19 PM PDT 24 |
| Finished | Aug 12 06:48:23 PM PDT 24 |
| Peak memory | 573624 kb |
| Host | smart-66bb8ea2-345b-4f1c-951c-db4336fa80dd |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1131020236 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.xbar_random_large_delays.1131020236 |
| Directory | /workspace/4.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/4.xbar_random_slow_rsp.2535068736 |
| Short name | T596 |
| Test name | |
| Test status | |
| Simulation time | 30438209821 ps |
| CPU time | 499.58 seconds |
| Started | Aug 12 06:47:17 PM PDT 24 |
| Finished | Aug 12 06:55:37 PM PDT 24 |
| Peak memory | 575744 kb |
| Host | smart-1b9b7ac4-893b-446e-86b9-0b99f98cfdbc |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2535068736 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.xbar_random_slow_rsp.2535068736 |
| Directory | /workspace/4.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/4.xbar_random_zero_delays.2196934441 |
| Short name | T1835 |
| Test name | |
| Test status | |
| Simulation time | 47853458 ps |
| CPU time | 7.68 seconds |
| Started | Aug 12 06:47:17 PM PDT 24 |
| Finished | Aug 12 06:47:25 PM PDT 24 |
| Peak memory | 573608 kb |
| Host | smart-c5496795-45b4-442b-bee4-eb96403fe1d9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2196934441 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.xbar_random_zero_dela ys.2196934441 |
| Directory | /workspace/4.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/4.xbar_same_source.1267660726 |
| Short name | T673 |
| Test name | |
| Test status | |
| Simulation time | 286722605 ps |
| CPU time | 20.82 seconds |
| Started | Aug 12 06:47:16 PM PDT 24 |
| Finished | Aug 12 06:47:37 PM PDT 24 |
| Peak memory | 575652 kb |
| Host | smart-92863568-d92e-4a4a-93a4-452f47a18d57 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1267660726 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.xbar_same_source.1267660726 |
| Directory | /workspace/4.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/4.xbar_smoke.2089168338 |
| Short name | T1461 |
| Test name | |
| Test status | |
| Simulation time | 44339532 ps |
| CPU time | 6.2 seconds |
| Started | Aug 12 06:47:17 PM PDT 24 |
| Finished | Aug 12 06:47:24 PM PDT 24 |
| Peak memory | 573572 kb |
| Host | smart-f0248721-20b1-4439-af8f-b64d2b8cebfe |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2089168338 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.xbar_smoke.2089168338 |
| Directory | /workspace/4.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/4.xbar_smoke_large_delays.412501516 |
| Short name | T2633 |
| Test name | |
| Test status | |
| Simulation time | 6308327571 ps |
| CPU time | 62.03 seconds |
| Started | Aug 12 06:47:18 PM PDT 24 |
| Finished | Aug 12 06:48:20 PM PDT 24 |
| Peak memory | 573652 kb |
| Host | smart-6887fa9d-67eb-49ec-86ba-d9dc7b261be7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=412501516 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.xbar_smoke_large_delays.412501516 |
| Directory | /workspace/4.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/4.xbar_smoke_slow_rsp.411334421 |
| Short name | T593 |
| Test name | |
| Test status | |
| Simulation time | 5141209576 ps |
| CPU time | 81.6 seconds |
| Started | Aug 12 06:47:21 PM PDT 24 |
| Finished | Aug 12 06:48:43 PM PDT 24 |
| Peak memory | 573604 kb |
| Host | smart-f762df1d-5cb6-4d84-835e-dc8a102ab994 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=411334421 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.xbar_smoke_slow_rsp.411334421 |
| Directory | /workspace/4.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/4.xbar_smoke_zero_delays.1664688580 |
| Short name | T1675 |
| Test name | |
| Test status | |
| Simulation time | 47381764 ps |
| CPU time | 6.29 seconds |
| Started | Aug 12 06:47:20 PM PDT 24 |
| Finished | Aug 12 06:47:27 PM PDT 24 |
| Peak memory | 573556 kb |
| Host | smart-db5356a4-5bff-4275-a8fe-49afbf4467c1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1664688580 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.xbar_smoke_zero_delays .1664688580 |
| Directory | /workspace/4.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/4.xbar_stress_all.3128593588 |
| Short name | T1821 |
| Test name | |
| Test status | |
| Simulation time | 471640279 ps |
| CPU time | 34.55 seconds |
| Started | Aug 12 06:47:26 PM PDT 24 |
| Finished | Aug 12 06:48:00 PM PDT 24 |
| Peak memory | 575716 kb |
| Host | smart-1eab2e4c-87e3-4eae-9858-bf81c967bbb9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3128593588 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.xbar_stress_all.3128593588 |
| Directory | /workspace/4.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/4.xbar_stress_all_with_error.2046120536 |
| Short name | T2343 |
| Test name | |
| Test status | |
| Simulation time | 560915210 ps |
| CPU time | 47.23 seconds |
| Started | Aug 12 06:47:25 PM PDT 24 |
| Finished | Aug 12 06:48:13 PM PDT 24 |
| Peak memory | 575752 kb |
| Host | smart-b921b4f3-cb13-4be6-aa2d-3b416140bb4b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2046120536 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.xbar_stress_all_with_error.2046120536 |
| Directory | /workspace/4.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/4.xbar_stress_all_with_rand_reset.612092236 |
| Short name | T585 |
| Test name | |
| Test status | |
| Simulation time | 4605235169 ps |
| CPU time | 334.88 seconds |
| Started | Aug 12 06:47:26 PM PDT 24 |
| Finished | Aug 12 06:53:01 PM PDT 24 |
| Peak memory | 575756 kb |
| Host | smart-f3ea1038-d4d3-4ea5-90e0-b467058b7568 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=612092236 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_res et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.xbar_stress_all_w ith_rand_reset.612092236 |
| Directory | /workspace/4.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/4.xbar_stress_all_with_reset_error.1457215640 |
| Short name | T914 |
| Test name | |
| Test status | |
| Simulation time | 8808987429 ps |
| CPU time | 466.17 seconds |
| Started | Aug 12 06:47:24 PM PDT 24 |
| Finished | Aug 12 06:55:10 PM PDT 24 |
| Peak memory | 576616 kb |
| Host | smart-a6e1c212-3fd9-42ea-9de2-6c9dd521842d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1457215640 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.xbar_stress_all _with_reset_error.1457215640 |
| Directory | /workspace/4.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/4.xbar_unmapped_addr.879368433 |
| Short name | T2753 |
| Test name | |
| Test status | |
| Simulation time | 1282385219 ps |
| CPU time | 49.96 seconds |
| Started | Aug 12 06:47:28 PM PDT 24 |
| Finished | Aug 12 06:48:18 PM PDT 24 |
| Peak memory | 575876 kb |
| Host | smart-86ab644e-188c-4f3b-96a8-2ac2f86edbdb |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=879368433 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.xbar_unmapped_addr.879368433 |
| Directory | /workspace/4.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/40.xbar_access_same_device.2331530032 |
| Short name | T2476 |
| Test name | |
| Test status | |
| Simulation time | 97682100 ps |
| CPU time | 8.89 seconds |
| Started | Aug 12 06:51:46 PM PDT 24 |
| Finished | Aug 12 06:51:56 PM PDT 24 |
| Peak memory | 573616 kb |
| Host | smart-3de77eb3-b823-4d46-91ca-c86fb7f19eb6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2331530032 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.xbar_access_same_device .2331530032 |
| Directory | /workspace/40.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/40.xbar_access_same_device_slow_rsp.2301352206 |
| Short name | T2862 |
| Test name | |
| Test status | |
| Simulation time | 137585464561 ps |
| CPU time | 2406.87 seconds |
| Started | Aug 12 06:51:58 PM PDT 24 |
| Finished | Aug 12 07:32:05 PM PDT 24 |
| Peak memory | 575800 kb |
| Host | smart-07dc33b6-9875-40e5-baaa-5ae75f808675 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2301352206 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.xbar_access_same_ device_slow_rsp.2301352206 |
| Directory | /workspace/40.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/40.xbar_error_and_unmapped_addr.4156437116 |
| Short name | T2589 |
| Test name | |
| Test status | |
| Simulation time | 1446581059 ps |
| CPU time | 56.66 seconds |
| Started | Aug 12 06:51:47 PM PDT 24 |
| Finished | Aug 12 06:52:44 PM PDT 24 |
| Peak memory | 575752 kb |
| Host | smart-a5bb992b-a36f-4770-919f-99e9a6aa4505 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4156437116 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.xbar_error_and_unmapped_add r.4156437116 |
| Directory | /workspace/40.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/40.xbar_error_random.1431516112 |
| Short name | T1753 |
| Test name | |
| Test status | |
| Simulation time | 865475721 ps |
| CPU time | 32.79 seconds |
| Started | Aug 12 06:51:46 PM PDT 24 |
| Finished | Aug 12 06:52:19 PM PDT 24 |
| Peak memory | 575716 kb |
| Host | smart-9777e84b-d9be-43f3-accf-41edfeb97499 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1431516112 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.xbar_error_random.1431516112 |
| Directory | /workspace/40.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/40.xbar_random.1817607554 |
| Short name | T2186 |
| Test name | |
| Test status | |
| Simulation time | 2021582977 ps |
| CPU time | 70.02 seconds |
| Started | Aug 12 06:51:44 PM PDT 24 |
| Finished | Aug 12 06:52:55 PM PDT 24 |
| Peak memory | 575676 kb |
| Host | smart-8a1e99b9-16ac-4abb-a5af-329663e061eb |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1817607554 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.xbar_random.1817607554 |
| Directory | /workspace/40.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/40.xbar_random_large_delays.390832961 |
| Short name | T2913 |
| Test name | |
| Test status | |
| Simulation time | 52859871143 ps |
| CPU time | 539.68 seconds |
| Started | Aug 12 06:51:46 PM PDT 24 |
| Finished | Aug 12 07:00:46 PM PDT 24 |
| Peak memory | 575808 kb |
| Host | smart-cc5ba0c5-458a-47fc-a40a-f39d5d784b00 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=390832961 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.xbar_random_large_delays.390832961 |
| Directory | /workspace/40.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/40.xbar_random_slow_rsp.1750396710 |
| Short name | T2798 |
| Test name | |
| Test status | |
| Simulation time | 24493899219 ps |
| CPU time | 412.01 seconds |
| Started | Aug 12 06:51:59 PM PDT 24 |
| Finished | Aug 12 06:58:51 PM PDT 24 |
| Peak memory | 575752 kb |
| Host | smart-947d963e-7de1-4d9a-8bd7-502b93940fda |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1750396710 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.xbar_random_slow_rsp.1750396710 |
| Directory | /workspace/40.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/40.xbar_random_zero_delays.3590988960 |
| Short name | T2922 |
| Test name | |
| Test status | |
| Simulation time | 295256196 ps |
| CPU time | 24.65 seconds |
| Started | Aug 12 06:51:47 PM PDT 24 |
| Finished | Aug 12 06:52:12 PM PDT 24 |
| Peak memory | 575680 kb |
| Host | smart-daabf7c1-4c5d-4bfb-9409-d0e8418879d0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3590988960 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.xbar_random_zero_del ays.3590988960 |
| Directory | /workspace/40.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/40.xbar_same_source.3084857571 |
| Short name | T2918 |
| Test name | |
| Test status | |
| Simulation time | 279665099 ps |
| CPU time | 23.76 seconds |
| Started | Aug 12 06:51:44 PM PDT 24 |
| Finished | Aug 12 06:52:08 PM PDT 24 |
| Peak memory | 575636 kb |
| Host | smart-42a5852b-ee76-4cdf-9ee5-c7092f9a0eb9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3084857571 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.xbar_same_source.3084857571 |
| Directory | /workspace/40.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/40.xbar_smoke.3027910149 |
| Short name | T2423 |
| Test name | |
| Test status | |
| Simulation time | 49929366 ps |
| CPU time | 6.58 seconds |
| Started | Aug 12 06:51:46 PM PDT 24 |
| Finished | Aug 12 06:51:53 PM PDT 24 |
| Peak memory | 574296 kb |
| Host | smart-56b53f33-d3aa-4e32-8062-7c0cb18fa5e7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3027910149 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.xbar_smoke.3027910149 |
| Directory | /workspace/40.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/40.xbar_smoke_large_delays.3035464136 |
| Short name | T2643 |
| Test name | |
| Test status | |
| Simulation time | 7579187539 ps |
| CPU time | 78.29 seconds |
| Started | Aug 12 06:51:44 PM PDT 24 |
| Finished | Aug 12 06:53:03 PM PDT 24 |
| Peak memory | 574340 kb |
| Host | smart-7e3b106c-e1f3-4bce-9ddb-5d31fd6bd324 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3035464136 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.xbar_smoke_large_delays.3035464136 |
| Directory | /workspace/40.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/40.xbar_smoke_slow_rsp.742612178 |
| Short name | T1702 |
| Test name | |
| Test status | |
| Simulation time | 3309109955 ps |
| CPU time | 54.91 seconds |
| Started | Aug 12 06:51:46 PM PDT 24 |
| Finished | Aug 12 06:52:41 PM PDT 24 |
| Peak memory | 573656 kb |
| Host | smart-8cf2cdef-93b9-4cc4-844a-e60e9a30e999 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=742612178 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.xbar_smoke_slow_rsp.742612178 |
| Directory | /workspace/40.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/40.xbar_smoke_zero_delays.2231363541 |
| Short name | T743 |
| Test name | |
| Test status | |
| Simulation time | 43605834 ps |
| CPU time | 5.85 seconds |
| Started | Aug 12 06:51:44 PM PDT 24 |
| Finished | Aug 12 06:51:50 PM PDT 24 |
| Peak memory | 573584 kb |
| Host | smart-67b4c346-692b-4b87-959c-2634075f458e |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2231363541 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.xbar_smoke_zero_delay s.2231363541 |
| Directory | /workspace/40.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/40.xbar_stress_all.2150518743 |
| Short name | T2203 |
| Test name | |
| Test status | |
| Simulation time | 12080593310 ps |
| CPU time | 482.35 seconds |
| Started | Aug 12 06:51:45 PM PDT 24 |
| Finished | Aug 12 06:59:47 PM PDT 24 |
| Peak memory | 576588 kb |
| Host | smart-adb7335f-b106-4201-bbdb-bdd8a228a4c6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2150518743 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.xbar_stress_all.2150518743 |
| Directory | /workspace/40.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/40.xbar_stress_all_with_error.443431027 |
| Short name | T1677 |
| Test name | |
| Test status | |
| Simulation time | 1758148533 ps |
| CPU time | 121.22 seconds |
| Started | Aug 12 06:51:50 PM PDT 24 |
| Finished | Aug 12 06:53:51 PM PDT 24 |
| Peak memory | 575884 kb |
| Host | smart-2b4ca9da-7df7-4027-9ab9-cc6a1d3e0278 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=443431027 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.xbar_stress_all_with_error.443431027 |
| Directory | /workspace/40.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/40.xbar_stress_all_with_rand_reset.1934627288 |
| Short name | T709 |
| Test name | |
| Test status | |
| Simulation time | 1308029170 ps |
| CPU time | 241.37 seconds |
| Started | Aug 12 06:51:57 PM PDT 24 |
| Finished | Aug 12 06:55:59 PM PDT 24 |
| Peak memory | 575692 kb |
| Host | smart-3ad9f8a9-2bf2-4d1b-ae3a-5945e251e373 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1934627288 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.xbar_stress_all _with_rand_reset.1934627288 |
| Directory | /workspace/40.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/40.xbar_stress_all_with_reset_error.677582453 |
| Short name | T2309 |
| Test name | |
| Test status | |
| Simulation time | 77318353 ps |
| CPU time | 12.23 seconds |
| Started | Aug 12 06:51:58 PM PDT 24 |
| Finished | Aug 12 06:52:10 PM PDT 24 |
| Peak memory | 573756 kb |
| Host | smart-0afe3a97-1dd3-40e7-9eb1-c92727d1e0f0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=677582453 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.xbar_stress_all _with_reset_error.677582453 |
| Directory | /workspace/40.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/40.xbar_unmapped_addr.816277497 |
| Short name | T1726 |
| Test name | |
| Test status | |
| Simulation time | 190705218 ps |
| CPU time | 11.07 seconds |
| Started | Aug 12 06:51:47 PM PDT 24 |
| Finished | Aug 12 06:51:58 PM PDT 24 |
| Peak memory | 575728 kb |
| Host | smart-3e4f319a-748b-454a-95c5-05bd1f26b5eb |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=816277497 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.xbar_unmapped_addr.816277497 |
| Directory | /workspace/40.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/41.xbar_access_same_device.3753178340 |
| Short name | T2569 |
| Test name | |
| Test status | |
| Simulation time | 297925455 ps |
| CPU time | 28.33 seconds |
| Started | Aug 12 06:51:52 PM PDT 24 |
| Finished | Aug 12 06:52:20 PM PDT 24 |
| Peak memory | 575596 kb |
| Host | smart-4973216a-196e-4cad-9c1f-f93fc6c1b758 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3753178340 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.xbar_access_same_device .3753178340 |
| Directory | /workspace/41.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/41.xbar_access_same_device_slow_rsp.2849748240 |
| Short name | T2723 |
| Test name | |
| Test status | |
| Simulation time | 100258103204 ps |
| CPU time | 1762.48 seconds |
| Started | Aug 12 06:51:53 PM PDT 24 |
| Finished | Aug 12 07:21:16 PM PDT 24 |
| Peak memory | 575888 kb |
| Host | smart-e6ed6063-aee9-40fc-94d7-6a8efc14f44e |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2849748240 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.xbar_access_same_ device_slow_rsp.2849748240 |
| Directory | /workspace/41.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/41.xbar_error_and_unmapped_addr.4025412971 |
| Short name | T1489 |
| Test name | |
| Test status | |
| Simulation time | 20237797 ps |
| CPU time | 4.9 seconds |
| Started | Aug 12 06:51:55 PM PDT 24 |
| Finished | Aug 12 06:52:00 PM PDT 24 |
| Peak memory | 573740 kb |
| Host | smart-f9264ffe-8ab3-4067-8cc3-6f15e578f544 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4025412971 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.xbar_error_and_unmapped_add r.4025412971 |
| Directory | /workspace/41.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/41.xbar_error_random.3728764770 |
| Short name | T2615 |
| Test name | |
| Test status | |
| Simulation time | 37578839 ps |
| CPU time | 5.77 seconds |
| Started | Aug 12 06:51:53 PM PDT 24 |
| Finished | Aug 12 06:51:59 PM PDT 24 |
| Peak memory | 574224 kb |
| Host | smart-0376d1c6-84ec-4ca1-b430-d20230a7efba |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3728764770 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.xbar_error_random.3728764770 |
| Directory | /workspace/41.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/41.xbar_random.842422807 |
| Short name | T575 |
| Test name | |
| Test status | |
| Simulation time | 242657678 ps |
| CPU time | 24.25 seconds |
| Started | Aug 12 06:51:46 PM PDT 24 |
| Finished | Aug 12 06:52:10 PM PDT 24 |
| Peak memory | 575672 kb |
| Host | smart-55e15d92-23ea-4459-a407-2c4d4c307b10 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=842422807 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.xbar_random.842422807 |
| Directory | /workspace/41.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/41.xbar_random_large_delays.1067743926 |
| Short name | T1809 |
| Test name | |
| Test status | |
| Simulation time | 11518601449 ps |
| CPU time | 114.66 seconds |
| Started | Aug 12 06:51:44 PM PDT 24 |
| Finished | Aug 12 06:53:39 PM PDT 24 |
| Peak memory | 575592 kb |
| Host | smart-51aa69c5-ddfe-4eb4-8cf1-1d6bc689e614 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1067743926 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.xbar_random_large_delays.1067743926 |
| Directory | /workspace/41.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/41.xbar_random_slow_rsp.482493704 |
| Short name | T2157 |
| Test name | |
| Test status | |
| Simulation time | 22153357153 ps |
| CPU time | 400.75 seconds |
| Started | Aug 12 06:51:55 PM PDT 24 |
| Finished | Aug 12 06:58:36 PM PDT 24 |
| Peak memory | 575804 kb |
| Host | smart-bac2b731-761e-4b32-b7f9-2b4731d56c68 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=482493704 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.xbar_random_slow_rsp.482493704 |
| Directory | /workspace/41.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/41.xbar_random_zero_delays.478925503 |
| Short name | T2897 |
| Test name | |
| Test status | |
| Simulation time | 456000871 ps |
| CPU time | 42.01 seconds |
| Started | Aug 12 06:51:46 PM PDT 24 |
| Finished | Aug 12 06:52:28 PM PDT 24 |
| Peak memory | 575556 kb |
| Host | smart-e2a873d0-b875-4d8a-a1a8-a43b9a9dd2c8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=478925503 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.xbar_random_zero_dela ys.478925503 |
| Directory | /workspace/41.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/41.xbar_same_source.535197911 |
| Short name | T472 |
| Test name | |
| Test status | |
| Simulation time | 2603242455 ps |
| CPU time | 77.51 seconds |
| Started | Aug 12 06:51:53 PM PDT 24 |
| Finished | Aug 12 06:53:10 PM PDT 24 |
| Peak memory | 575676 kb |
| Host | smart-5f02fbd0-be20-4a37-b405-929115893c59 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=535197911 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.xbar_same_source.535197911 |
| Directory | /workspace/41.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/41.xbar_smoke.1486140999 |
| Short name | T1497 |
| Test name | |
| Test status | |
| Simulation time | 220264571 ps |
| CPU time | 8.81 seconds |
| Started | Aug 12 06:51:47 PM PDT 24 |
| Finished | Aug 12 06:51:56 PM PDT 24 |
| Peak memory | 573628 kb |
| Host | smart-55331fd7-0406-414b-aeec-fb2b2ed55048 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1486140999 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.xbar_smoke.1486140999 |
| Directory | /workspace/41.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/41.xbar_smoke_large_delays.1160994133 |
| Short name | T645 |
| Test name | |
| Test status | |
| Simulation time | 10002695828 ps |
| CPU time | 109.57 seconds |
| Started | Aug 12 06:51:46 PM PDT 24 |
| Finished | Aug 12 06:53:36 PM PDT 24 |
| Peak memory | 573696 kb |
| Host | smart-01a703de-00db-4cee-a705-9b072326f0ae |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1160994133 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.xbar_smoke_large_delays.1160994133 |
| Directory | /workspace/41.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/41.xbar_smoke_slow_rsp.1343343565 |
| Short name | T2314 |
| Test name | |
| Test status | |
| Simulation time | 3008093681 ps |
| CPU time | 47.58 seconds |
| Started | Aug 12 06:51:57 PM PDT 24 |
| Finished | Aug 12 06:52:45 PM PDT 24 |
| Peak memory | 573608 kb |
| Host | smart-2ea72e73-be01-40de-9f5f-a4a71822a4f9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1343343565 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.xbar_smoke_slow_rsp.1343343565 |
| Directory | /workspace/41.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/41.xbar_smoke_zero_delays.925940435 |
| Short name | T2654 |
| Test name | |
| Test status | |
| Simulation time | 41244515 ps |
| CPU time | 5.99 seconds |
| Started | Aug 12 06:51:46 PM PDT 24 |
| Finished | Aug 12 06:51:52 PM PDT 24 |
| Peak memory | 573648 kb |
| Host | smart-8f952ab0-14f5-4c0a-8f7c-08df7b3e3b6b |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=925940435 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.xbar_smoke_zero_delays .925940435 |
| Directory | /workspace/41.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/41.xbar_stress_all.2046112742 |
| Short name | T1866 |
| Test name | |
| Test status | |
| Simulation time | 11370962996 ps |
| CPU time | 417.4 seconds |
| Started | Aug 12 06:51:52 PM PDT 24 |
| Finished | Aug 12 06:58:50 PM PDT 24 |
| Peak memory | 575824 kb |
| Host | smart-b36b8085-d4c2-4422-8ab1-980c03a53ffd |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2046112742 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.xbar_stress_all.2046112742 |
| Directory | /workspace/41.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/41.xbar_stress_all_with_error.3669104611 |
| Short name | T2320 |
| Test name | |
| Test status | |
| Simulation time | 2205680539 ps |
| CPU time | 64.38 seconds |
| Started | Aug 12 06:51:55 PM PDT 24 |
| Finished | Aug 12 06:52:59 PM PDT 24 |
| Peak memory | 575736 kb |
| Host | smart-f9619b45-3e64-4ec1-829e-a2590c763d65 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3669104611 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.xbar_stress_all_with_error.3669104611 |
| Directory | /workspace/41.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/41.xbar_stress_all_with_rand_reset.1028678841 |
| Short name | T1668 |
| Test name | |
| Test status | |
| Simulation time | 421782649 ps |
| CPU time | 210.78 seconds |
| Started | Aug 12 06:51:55 PM PDT 24 |
| Finished | Aug 12 06:55:26 PM PDT 24 |
| Peak memory | 576500 kb |
| Host | smart-d2d3c8c0-1581-4cd8-acad-69502bcff6c8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1028678841 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.xbar_stress_all _with_rand_reset.1028678841 |
| Directory | /workspace/41.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/41.xbar_stress_all_with_reset_error.557583680 |
| Short name | T953 |
| Test name | |
| Test status | |
| Simulation time | 70026203 ps |
| CPU time | 30.79 seconds |
| Started | Aug 12 06:51:54 PM PDT 24 |
| Finished | Aug 12 06:52:25 PM PDT 24 |
| Peak memory | 576492 kb |
| Host | smart-8aed2b96-885c-4ad2-8c9d-22d685df79f7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=557583680 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.xbar_stress_all _with_reset_error.557583680 |
| Directory | /workspace/41.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/41.xbar_unmapped_addr.3650307889 |
| Short name | T1749 |
| Test name | |
| Test status | |
| Simulation time | 79016505 ps |
| CPU time | 11.89 seconds |
| Started | Aug 12 06:51:53 PM PDT 24 |
| Finished | Aug 12 06:52:05 PM PDT 24 |
| Peak memory | 575692 kb |
| Host | smart-3517e219-c0c8-4694-a128-b6ce0b3ccba8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3650307889 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.xbar_unmapped_addr.3650307889 |
| Directory | /workspace/41.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/42.xbar_access_same_device.2298110557 |
| Short name | T1802 |
| Test name | |
| Test status | |
| Simulation time | 3079890701 ps |
| CPU time | 121.34 seconds |
| Started | Aug 12 06:52:06 PM PDT 24 |
| Finished | Aug 12 06:54:07 PM PDT 24 |
| Peak memory | 575784 kb |
| Host | smart-a98e9b3b-7311-4da1-8df9-197a0229828b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2298110557 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.xbar_access_same_device .2298110557 |
| Directory | /workspace/42.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/42.xbar_access_same_device_slow_rsp.696417197 |
| Short name | T2398 |
| Test name | |
| Test status | |
| Simulation time | 87262889396 ps |
| CPU time | 1660.51 seconds |
| Started | Aug 12 06:52:02 PM PDT 24 |
| Finished | Aug 12 07:19:43 PM PDT 24 |
| Peak memory | 575888 kb |
| Host | smart-c858a606-d33f-4233-aa64-91db4d455d4d |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=696417197 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.xbar_access_same_d evice_slow_rsp.696417197 |
| Directory | /workspace/42.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/42.xbar_error_and_unmapped_addr.2287835501 |
| Short name | T2699 |
| Test name | |
| Test status | |
| Simulation time | 370862982 ps |
| CPU time | 17.6 seconds |
| Started | Aug 12 06:52:05 PM PDT 24 |
| Finished | Aug 12 06:52:23 PM PDT 24 |
| Peak memory | 575660 kb |
| Host | smart-0b513cfe-5e09-4681-8acb-10188d86f8e2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2287835501 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.xbar_error_and_unmapped_add r.2287835501 |
| Directory | /workspace/42.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/42.xbar_error_random.2411689611 |
| Short name | T1567 |
| Test name | |
| Test status | |
| Simulation time | 1901704565 ps |
| CPU time | 60.54 seconds |
| Started | Aug 12 06:52:03 PM PDT 24 |
| Finished | Aug 12 06:53:04 PM PDT 24 |
| Peak memory | 575460 kb |
| Host | smart-774179d7-08a3-4c4c-a349-a065233aac21 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2411689611 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.xbar_error_random.2411689611 |
| Directory | /workspace/42.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/42.xbar_random.3702924490 |
| Short name | T1916 |
| Test name | |
| Test status | |
| Simulation time | 282629965 ps |
| CPU time | 26.55 seconds |
| Started | Aug 12 06:52:05 PM PDT 24 |
| Finished | Aug 12 06:52:31 PM PDT 24 |
| Peak memory | 575708 kb |
| Host | smart-f22c138b-781b-417e-ae36-de2fb2bd09a0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3702924490 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.xbar_random.3702924490 |
| Directory | /workspace/42.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/42.xbar_random_large_delays.3247481511 |
| Short name | T1712 |
| Test name | |
| Test status | |
| Simulation time | 24719275117 ps |
| CPU time | 269.04 seconds |
| Started | Aug 12 06:52:02 PM PDT 24 |
| Finished | Aug 12 06:56:31 PM PDT 24 |
| Peak memory | 575584 kb |
| Host | smart-b2d0590e-4087-42b2-bfa7-8f5821d5fb02 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3247481511 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.xbar_random_large_delays.3247481511 |
| Directory | /workspace/42.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/42.xbar_random_slow_rsp.1852294729 |
| Short name | T1833 |
| Test name | |
| Test status | |
| Simulation time | 63642085556 ps |
| CPU time | 1074.93 seconds |
| Started | Aug 12 06:52:03 PM PDT 24 |
| Finished | Aug 12 07:09:58 PM PDT 24 |
| Peak memory | 575772 kb |
| Host | smart-ab657310-71c4-458d-ba21-61f813d5c04f |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1852294729 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.xbar_random_slow_rsp.1852294729 |
| Directory | /workspace/42.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/42.xbar_random_zero_delays.2713335134 |
| Short name | T2139 |
| Test name | |
| Test status | |
| Simulation time | 292741064 ps |
| CPU time | 25.4 seconds |
| Started | Aug 12 06:52:04 PM PDT 24 |
| Finished | Aug 12 06:52:30 PM PDT 24 |
| Peak memory | 575732 kb |
| Host | smart-ef74eed3-34c0-4484-b8b4-fed5529569bb |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2713335134 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.xbar_random_zero_del ays.2713335134 |
| Directory | /workspace/42.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/42.xbar_same_source.4047509642 |
| Short name | T1619 |
| Test name | |
| Test status | |
| Simulation time | 117952138 ps |
| CPU time | 10.49 seconds |
| Started | Aug 12 06:52:03 PM PDT 24 |
| Finished | Aug 12 06:52:13 PM PDT 24 |
| Peak memory | 575540 kb |
| Host | smart-c8292b44-ace0-4a11-8db8-1f93bc939e52 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4047509642 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.xbar_same_source.4047509642 |
| Directory | /workspace/42.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/42.xbar_smoke.3574643625 |
| Short name | T2051 |
| Test name | |
| Test status | |
| Simulation time | 256863289 ps |
| CPU time | 10.01 seconds |
| Started | Aug 12 06:52:00 PM PDT 24 |
| Finished | Aug 12 06:52:10 PM PDT 24 |
| Peak memory | 574280 kb |
| Host | smart-94aebaf4-f474-49b7-93c9-91b7d4627095 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3574643625 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.xbar_smoke.3574643625 |
| Directory | /workspace/42.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/42.xbar_smoke_large_delays.1668309251 |
| Short name | T2254 |
| Test name | |
| Test status | |
| Simulation time | 8460721760 ps |
| CPU time | 86.69 seconds |
| Started | Aug 12 06:51:54 PM PDT 24 |
| Finished | Aug 12 06:53:21 PM PDT 24 |
| Peak memory | 573636 kb |
| Host | smart-2a297821-50d0-4d77-898e-88004c27af18 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1668309251 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.xbar_smoke_large_delays.1668309251 |
| Directory | /workspace/42.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/42.xbar_smoke_slow_rsp.227400680 |
| Short name | T2743 |
| Test name | |
| Test status | |
| Simulation time | 5939194583 ps |
| CPU time | 103.05 seconds |
| Started | Aug 12 06:51:56 PM PDT 24 |
| Finished | Aug 12 06:53:39 PM PDT 24 |
| Peak memory | 573692 kb |
| Host | smart-cc25c7f4-cf14-488b-85b1-bb1a1ba2a847 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=227400680 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.xbar_smoke_slow_rsp.227400680 |
| Directory | /workspace/42.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/42.xbar_smoke_zero_delays.1141828417 |
| Short name | T2410 |
| Test name | |
| Test status | |
| Simulation time | 52026967 ps |
| CPU time | 7.05 seconds |
| Started | Aug 12 06:51:53 PM PDT 24 |
| Finished | Aug 12 06:52:00 PM PDT 24 |
| Peak memory | 573516 kb |
| Host | smart-4f038fe6-7152-4c6a-bbed-fb570476af70 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1141828417 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.xbar_smoke_zero_delay s.1141828417 |
| Directory | /workspace/42.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/42.xbar_stress_all.3441492703 |
| Short name | T1605 |
| Test name | |
| Test status | |
| Simulation time | 6458825 ps |
| CPU time | 3.79 seconds |
| Started | Aug 12 06:52:04 PM PDT 24 |
| Finished | Aug 12 06:52:08 PM PDT 24 |
| Peak memory | 565892 kb |
| Host | smart-4c57226c-f1cc-4716-9db7-4b43bfd1c7ef |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3441492703 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.xbar_stress_all.3441492703 |
| Directory | /workspace/42.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/42.xbar_stress_all_with_error.2098004543 |
| Short name | T2822 |
| Test name | |
| Test status | |
| Simulation time | 6154272370 ps |
| CPU time | 202.76 seconds |
| Started | Aug 12 06:52:03 PM PDT 24 |
| Finished | Aug 12 06:55:26 PM PDT 24 |
| Peak memory | 575900 kb |
| Host | smart-f8d4a78f-0faa-4ea7-8122-4e5872b741b4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2098004543 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.xbar_stress_all_with_error.2098004543 |
| Directory | /workspace/42.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/42.xbar_stress_all_with_rand_reset.2563791826 |
| Short name | T2769 |
| Test name | |
| Test status | |
| Simulation time | 2358006869 ps |
| CPU time | 443.64 seconds |
| Started | Aug 12 06:52:05 PM PDT 24 |
| Finished | Aug 12 06:59:28 PM PDT 24 |
| Peak memory | 576584 kb |
| Host | smart-eb70e8fa-a6e3-491b-81e0-7ba71abaaa54 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2563791826 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.xbar_stress_all _with_rand_reset.2563791826 |
| Directory | /workspace/42.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/42.xbar_stress_all_with_reset_error.3584045470 |
| Short name | T2558 |
| Test name | |
| Test status | |
| Simulation time | 10479752065 ps |
| CPU time | 484.34 seconds |
| Started | Aug 12 06:52:05 PM PDT 24 |
| Finished | Aug 12 07:00:10 PM PDT 24 |
| Peak memory | 575776 kb |
| Host | smart-07d2743a-aeec-4979-b187-9ebdb5d951c8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3584045470 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.xbar_stress_al l_with_reset_error.3584045470 |
| Directory | /workspace/42.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/42.xbar_unmapped_addr.3428953941 |
| Short name | T1499 |
| Test name | |
| Test status | |
| Simulation time | 115653673 ps |
| CPU time | 15.1 seconds |
| Started | Aug 12 06:52:05 PM PDT 24 |
| Finished | Aug 12 06:52:20 PM PDT 24 |
| Peak memory | 575592 kb |
| Host | smart-6d23b9d4-da9e-4678-8697-3315bf9587e0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3428953941 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.xbar_unmapped_addr.3428953941 |
| Directory | /workspace/42.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/43.xbar_access_same_device.1012860009 |
| Short name | T2018 |
| Test name | |
| Test status | |
| Simulation time | 238570474 ps |
| CPU time | 11.39 seconds |
| Started | Aug 12 06:52:13 PM PDT 24 |
| Finished | Aug 12 06:52:25 PM PDT 24 |
| Peak memory | 573600 kb |
| Host | smart-8c35960e-ae5b-4cdb-9feb-15ec0e9ed234 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1012860009 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.xbar_access_same_device .1012860009 |
| Directory | /workspace/43.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/43.xbar_access_same_device_slow_rsp.1760928317 |
| Short name | T1837 |
| Test name | |
| Test status | |
| Simulation time | 87415506598 ps |
| CPU time | 1657.49 seconds |
| Started | Aug 12 06:52:13 PM PDT 24 |
| Finished | Aug 12 07:19:51 PM PDT 24 |
| Peak memory | 575852 kb |
| Host | smart-61236090-d2e2-4d27-8d15-8c6107a8a4f8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1760928317 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.xbar_access_same_ device_slow_rsp.1760928317 |
| Directory | /workspace/43.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/43.xbar_error_and_unmapped_addr.1398018057 |
| Short name | T1618 |
| Test name | |
| Test status | |
| Simulation time | 235034098 ps |
| CPU time | 20.78 seconds |
| Started | Aug 12 06:52:23 PM PDT 24 |
| Finished | Aug 12 06:52:44 PM PDT 24 |
| Peak memory | 575776 kb |
| Host | smart-5ddd0709-7da8-44b8-9587-cf02a7d99fec |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1398018057 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.xbar_error_and_unmapped_add r.1398018057 |
| Directory | /workspace/43.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/43.xbar_error_random.2463690142 |
| Short name | T2229 |
| Test name | |
| Test status | |
| Simulation time | 168037903 ps |
| CPU time | 17.32 seconds |
| Started | Aug 12 06:52:23 PM PDT 24 |
| Finished | Aug 12 06:52:41 PM PDT 24 |
| Peak memory | 575720 kb |
| Host | smart-f1935096-2198-424d-88c7-55483524c14b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2463690142 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.xbar_error_random.2463690142 |
| Directory | /workspace/43.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/43.xbar_random.3529935764 |
| Short name | T785 |
| Test name | |
| Test status | |
| Simulation time | 1152479363 ps |
| CPU time | 40.93 seconds |
| Started | Aug 12 06:52:13 PM PDT 24 |
| Finished | Aug 12 06:52:54 PM PDT 24 |
| Peak memory | 575732 kb |
| Host | smart-6b200885-a804-4787-81ea-033db46e3225 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3529935764 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.xbar_random.3529935764 |
| Directory | /workspace/43.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/43.xbar_random_large_delays.2203309027 |
| Short name | T2093 |
| Test name | |
| Test status | |
| Simulation time | 91717879962 ps |
| CPU time | 959.98 seconds |
| Started | Aug 12 06:52:12 PM PDT 24 |
| Finished | Aug 12 07:08:12 PM PDT 24 |
| Peak memory | 575756 kb |
| Host | smart-c5f30d52-2f84-488c-8454-f602ad7542c6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2203309027 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.xbar_random_large_delays.2203309027 |
| Directory | /workspace/43.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/43.xbar_random_slow_rsp.2976933531 |
| Short name | T421 |
| Test name | |
| Test status | |
| Simulation time | 73275433920 ps |
| CPU time | 1277.2 seconds |
| Started | Aug 12 06:52:11 PM PDT 24 |
| Finished | Aug 12 07:13:29 PM PDT 24 |
| Peak memory | 575780 kb |
| Host | smart-ded1b1eb-923c-4ed7-b9bc-16f75c2cf56b |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2976933531 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.xbar_random_slow_rsp.2976933531 |
| Directory | /workspace/43.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/43.xbar_random_zero_delays.1863022171 |
| Short name | T1598 |
| Test name | |
| Test status | |
| Simulation time | 216515133 ps |
| CPU time | 20.97 seconds |
| Started | Aug 12 06:52:14 PM PDT 24 |
| Finished | Aug 12 06:52:35 PM PDT 24 |
| Peak memory | 575536 kb |
| Host | smart-3f2d90c2-de79-442f-ae64-2395a1affb00 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1863022171 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.xbar_random_zero_del ays.1863022171 |
| Directory | /workspace/43.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/43.xbar_same_source.2379683528 |
| Short name | T1700 |
| Test name | |
| Test status | |
| Simulation time | 747760084 ps |
| CPU time | 24.54 seconds |
| Started | Aug 12 06:52:12 PM PDT 24 |
| Finished | Aug 12 06:52:37 PM PDT 24 |
| Peak memory | 575588 kb |
| Host | smart-a5a6cc4f-cd59-4b78-8bfe-8c5ae1753a61 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2379683528 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.xbar_same_source.2379683528 |
| Directory | /workspace/43.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/43.xbar_smoke.465072834 |
| Short name | T2635 |
| Test name | |
| Test status | |
| Simulation time | 230252626 ps |
| CPU time | 9.64 seconds |
| Started | Aug 12 06:52:14 PM PDT 24 |
| Finished | Aug 12 06:52:24 PM PDT 24 |
| Peak memory | 573664 kb |
| Host | smart-2a0fe240-6425-4a07-a0d9-1067305f5bef |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=465072834 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.xbar_smoke.465072834 |
| Directory | /workspace/43.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/43.xbar_smoke_large_delays.1790893851 |
| Short name | T1562 |
| Test name | |
| Test status | |
| Simulation time | 7371202412 ps |
| CPU time | 77.22 seconds |
| Started | Aug 12 06:52:18 PM PDT 24 |
| Finished | Aug 12 06:53:35 PM PDT 24 |
| Peak memory | 573592 kb |
| Host | smart-e4a681c9-1066-4729-9885-d7aa14da65e8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1790893851 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.xbar_smoke_large_delays.1790893851 |
| Directory | /workspace/43.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/43.xbar_smoke_slow_rsp.3166475314 |
| Short name | T784 |
| Test name | |
| Test status | |
| Simulation time | 5215453811 ps |
| CPU time | 87.5 seconds |
| Started | Aug 12 06:52:18 PM PDT 24 |
| Finished | Aug 12 06:53:45 PM PDT 24 |
| Peak memory | 573608 kb |
| Host | smart-37dff318-069c-45eb-8336-3c359773bcb5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3166475314 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.xbar_smoke_slow_rsp.3166475314 |
| Directory | /workspace/43.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/43.xbar_smoke_zero_delays.2323056943 |
| Short name | T2858 |
| Test name | |
| Test status | |
| Simulation time | 42200744 ps |
| CPU time | 5.86 seconds |
| Started | Aug 12 06:52:13 PM PDT 24 |
| Finished | Aug 12 06:52:19 PM PDT 24 |
| Peak memory | 573600 kb |
| Host | smart-814c98de-4c78-432b-b43d-b89c56507226 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2323056943 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.xbar_smoke_zero_delay s.2323056943 |
| Directory | /workspace/43.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/43.xbar_stress_all.2226344435 |
| Short name | T525 |
| Test name | |
| Test status | |
| Simulation time | 3015187794 ps |
| CPU time | 232.94 seconds |
| Started | Aug 12 06:52:22 PM PDT 24 |
| Finished | Aug 12 06:56:15 PM PDT 24 |
| Peak memory | 576556 kb |
| Host | smart-2b807a37-6344-490f-ac76-29d25eb8a788 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2226344435 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.xbar_stress_all.2226344435 |
| Directory | /workspace/43.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/43.xbar_stress_all_with_error.2704370206 |
| Short name | T1656 |
| Test name | |
| Test status | |
| Simulation time | 1509039981 ps |
| CPU time | 120.53 seconds |
| Started | Aug 12 06:52:24 PM PDT 24 |
| Finished | Aug 12 06:54:24 PM PDT 24 |
| Peak memory | 575700 kb |
| Host | smart-f7a7c99d-1496-45c6-a358-7d6e180832ac |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2704370206 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.xbar_stress_all_with_error.2704370206 |
| Directory | /workspace/43.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/43.xbar_stress_all_with_rand_reset.2839958063 |
| Short name | T2873 |
| Test name | |
| Test status | |
| Simulation time | 2382734837 ps |
| CPU time | 298.89 seconds |
| Started | Aug 12 06:52:24 PM PDT 24 |
| Finished | Aug 12 06:57:23 PM PDT 24 |
| Peak memory | 576580 kb |
| Host | smart-8a5b20da-5338-4c03-aae0-10086074ac8f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2839958063 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.xbar_stress_all _with_rand_reset.2839958063 |
| Directory | /workspace/43.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/43.xbar_stress_all_with_reset_error.344970335 |
| Short name | T955 |
| Test name | |
| Test status | |
| Simulation time | 163880003 ps |
| CPU time | 92.62 seconds |
| Started | Aug 12 06:52:24 PM PDT 24 |
| Finished | Aug 12 06:53:56 PM PDT 24 |
| Peak memory | 576488 kb |
| Host | smart-5949dd29-b662-493e-b50a-39ab6d9f67fa |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=344970335 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.xbar_stress_all _with_reset_error.344970335 |
| Directory | /workspace/43.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/43.xbar_unmapped_addr.2315583798 |
| Short name | T1847 |
| Test name | |
| Test status | |
| Simulation time | 22906112 ps |
| CPU time | 5.12 seconds |
| Started | Aug 12 06:52:21 PM PDT 24 |
| Finished | Aug 12 06:52:26 PM PDT 24 |
| Peak memory | 573576 kb |
| Host | smart-88086d0b-1ef7-4441-9945-37e9cd015f88 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2315583798 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.xbar_unmapped_addr.2315583798 |
| Directory | /workspace/43.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/44.xbar_access_same_device.776328536 |
| Short name | T1923 |
| Test name | |
| Test status | |
| Simulation time | 1415430685 ps |
| CPU time | 49.35 seconds |
| Started | Aug 12 06:52:33 PM PDT 24 |
| Finished | Aug 12 06:53:22 PM PDT 24 |
| Peak memory | 575528 kb |
| Host | smart-1e6c5545-ae8d-44b5-8f1c-52993399d012 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=776328536 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.xbar_access_same_device. 776328536 |
| Directory | /workspace/44.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/44.xbar_access_same_device_slow_rsp.979555274 |
| Short name | T2825 |
| Test name | |
| Test status | |
| Simulation time | 64959612453 ps |
| CPU time | 1152.93 seconds |
| Started | Aug 12 06:52:31 PM PDT 24 |
| Finished | Aug 12 07:11:45 PM PDT 24 |
| Peak memory | 575744 kb |
| Host | smart-dce18d88-9b05-4147-aeb5-6b010f2ceb74 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=979555274 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.xbar_access_same_d evice_slow_rsp.979555274 |
| Directory | /workspace/44.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/44.xbar_error_and_unmapped_addr.570198927 |
| Short name | T1954 |
| Test name | |
| Test status | |
| Simulation time | 229861022 ps |
| CPU time | 23.46 seconds |
| Started | Aug 12 06:52:36 PM PDT 24 |
| Finished | Aug 12 06:53:00 PM PDT 24 |
| Peak memory | 575528 kb |
| Host | smart-4f3c865e-6d75-4355-9373-6f2c5750dad5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=570198927 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.xbar_error_and_unmapped_addr .570198927 |
| Directory | /workspace/44.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/44.xbar_error_random.1512078608 |
| Short name | T1568 |
| Test name | |
| Test status | |
| Simulation time | 73186075 ps |
| CPU time | 8.59 seconds |
| Started | Aug 12 06:52:33 PM PDT 24 |
| Finished | Aug 12 06:52:42 PM PDT 24 |
| Peak memory | 575608 kb |
| Host | smart-d29948b6-0c40-450a-b54d-955f98f3b6bd |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1512078608 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.xbar_error_random.1512078608 |
| Directory | /workspace/44.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/44.xbar_random.2535906762 |
| Short name | T616 |
| Test name | |
| Test status | |
| Simulation time | 210798445 ps |
| CPU time | 20.49 seconds |
| Started | Aug 12 06:52:23 PM PDT 24 |
| Finished | Aug 12 06:52:44 PM PDT 24 |
| Peak memory | 575524 kb |
| Host | smart-47420d3d-bbb0-4089-bc37-6313e9d32ceb |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2535906762 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.xbar_random.2535906762 |
| Directory | /workspace/44.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/44.xbar_random_large_delays.1048030275 |
| Short name | T621 |
| Test name | |
| Test status | |
| Simulation time | 29838385440 ps |
| CPU time | 303.47 seconds |
| Started | Aug 12 06:52:24 PM PDT 24 |
| Finished | Aug 12 06:57:27 PM PDT 24 |
| Peak memory | 575752 kb |
| Host | smart-7baba022-4fae-422e-859f-9f2651a080f7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1048030275 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.xbar_random_large_delays.1048030275 |
| Directory | /workspace/44.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/44.xbar_random_slow_rsp.779350740 |
| Short name | T898 |
| Test name | |
| Test status | |
| Simulation time | 34976873493 ps |
| CPU time | 570.2 seconds |
| Started | Aug 12 06:52:23 PM PDT 24 |
| Finished | Aug 12 07:01:54 PM PDT 24 |
| Peak memory | 575764 kb |
| Host | smart-9749eeb7-0114-4ec0-8e96-2cbc36811c6f |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=779350740 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.xbar_random_slow_rsp.779350740 |
| Directory | /workspace/44.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/44.xbar_random_zero_delays.1583769312 |
| Short name | T684 |
| Test name | |
| Test status | |
| Simulation time | 123136536 ps |
| CPU time | 12.63 seconds |
| Started | Aug 12 06:52:22 PM PDT 24 |
| Finished | Aug 12 06:52:35 PM PDT 24 |
| Peak memory | 575572 kb |
| Host | smart-eef1d236-b132-44fa-9200-13212301a822 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1583769312 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.xbar_random_zero_del ays.1583769312 |
| Directory | /workspace/44.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/44.xbar_same_source.1064884960 |
| Short name | T2917 |
| Test name | |
| Test status | |
| Simulation time | 299609533 ps |
| CPU time | 10.93 seconds |
| Started | Aug 12 06:52:33 PM PDT 24 |
| Finished | Aug 12 06:52:44 PM PDT 24 |
| Peak memory | 575584 kb |
| Host | smart-ed2b4f2e-e41d-46fd-aa38-730feabfa83c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1064884960 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.xbar_same_source.1064884960 |
| Directory | /workspace/44.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/44.xbar_smoke.3443263447 |
| Short name | T2115 |
| Test name | |
| Test status | |
| Simulation time | 43950085 ps |
| CPU time | 6.58 seconds |
| Started | Aug 12 06:52:23 PM PDT 24 |
| Finished | Aug 12 06:52:30 PM PDT 24 |
| Peak memory | 573532 kb |
| Host | smart-8160509f-4f4f-4f37-8a20-2b0cc1dfe79f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3443263447 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.xbar_smoke.3443263447 |
| Directory | /workspace/44.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/44.xbar_smoke_large_delays.2766202215 |
| Short name | T1807 |
| Test name | |
| Test status | |
| Simulation time | 5967320180 ps |
| CPU time | 66.94 seconds |
| Started | Aug 12 06:52:24 PM PDT 24 |
| Finished | Aug 12 06:53:31 PM PDT 24 |
| Peak memory | 574348 kb |
| Host | smart-cb9a53a5-94b4-4708-b1fe-17746f499c59 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2766202215 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.xbar_smoke_large_delays.2766202215 |
| Directory | /workspace/44.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/44.xbar_smoke_slow_rsp.772700714 |
| Short name | T2214 |
| Test name | |
| Test status | |
| Simulation time | 4192382244 ps |
| CPU time | 72 seconds |
| Started | Aug 12 06:52:24 PM PDT 24 |
| Finished | Aug 12 06:53:36 PM PDT 24 |
| Peak memory | 573652 kb |
| Host | smart-73b323c0-4793-4fb9-ac3d-9d9eea2faa4a |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=772700714 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.xbar_smoke_slow_rsp.772700714 |
| Directory | /workspace/44.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/44.xbar_smoke_zero_delays.3236598312 |
| Short name | T1748 |
| Test name | |
| Test status | |
| Simulation time | 35150408 ps |
| CPU time | 5.91 seconds |
| Started | Aug 12 06:52:24 PM PDT 24 |
| Finished | Aug 12 06:52:30 PM PDT 24 |
| Peak memory | 573632 kb |
| Host | smart-87a6d802-f191-4b99-b96d-d17d000f7601 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3236598312 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.xbar_smoke_zero_delay s.3236598312 |
| Directory | /workspace/44.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/44.xbar_stress_all.3694995488 |
| Short name | T608 |
| Test name | |
| Test status | |
| Simulation time | 1104577383 ps |
| CPU time | 116.14 seconds |
| Started | Aug 12 06:52:34 PM PDT 24 |
| Finished | Aug 12 06:54:30 PM PDT 24 |
| Peak memory | 576428 kb |
| Host | smart-e8065acb-89c1-4712-836a-7f875016ccf2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3694995488 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.xbar_stress_all.3694995488 |
| Directory | /workspace/44.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/44.xbar_stress_all_with_rand_reset.3742987054 |
| Short name | T2447 |
| Test name | |
| Test status | |
| Simulation time | 383249685 ps |
| CPU time | 122.83 seconds |
| Started | Aug 12 06:52:36 PM PDT 24 |
| Finished | Aug 12 06:54:39 PM PDT 24 |
| Peak memory | 576496 kb |
| Host | smart-ed873be4-bc17-413b-aac4-5e7c6c8e1d6b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3742987054 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.xbar_stress_all _with_rand_reset.3742987054 |
| Directory | /workspace/44.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/44.xbar_stress_all_with_reset_error.2031543599 |
| Short name | T2088 |
| Test name | |
| Test status | |
| Simulation time | 251770366 ps |
| CPU time | 74.94 seconds |
| Started | Aug 12 06:52:33 PM PDT 24 |
| Finished | Aug 12 06:53:48 PM PDT 24 |
| Peak memory | 576468 kb |
| Host | smart-c50af39d-8f00-4aea-ad71-878b5b123d9f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2031543599 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.xbar_stress_al l_with_reset_error.2031543599 |
| Directory | /workspace/44.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/44.xbar_unmapped_addr.3166649494 |
| Short name | T2241 |
| Test name | |
| Test status | |
| Simulation time | 572001571 ps |
| CPU time | 24.99 seconds |
| Started | Aug 12 06:52:33 PM PDT 24 |
| Finished | Aug 12 06:52:58 PM PDT 24 |
| Peak memory | 575720 kb |
| Host | smart-88fb61ad-cf82-4082-8998-375b0f8b90f1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3166649494 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.xbar_unmapped_addr.3166649494 |
| Directory | /workspace/44.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/45.xbar_access_same_device.1607476609 |
| Short name | T2172 |
| Test name | |
| Test status | |
| Simulation time | 910710188 ps |
| CPU time | 40.01 seconds |
| Started | Aug 12 06:52:39 PM PDT 24 |
| Finished | Aug 12 06:53:20 PM PDT 24 |
| Peak memory | 575792 kb |
| Host | smart-2cbb646f-b479-43ea-a1ad-dc1f4d31187a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1607476609 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.xbar_access_same_device .1607476609 |
| Directory | /workspace/45.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/45.xbar_access_same_device_slow_rsp.3054858200 |
| Short name | T2820 |
| Test name | |
| Test status | |
| Simulation time | 115069032381 ps |
| CPU time | 2030.85 seconds |
| Started | Aug 12 06:52:40 PM PDT 24 |
| Finished | Aug 12 07:26:31 PM PDT 24 |
| Peak memory | 575840 kb |
| Host | smart-b3f8f159-7307-475c-811a-af9bb7fbe94e |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3054858200 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.xbar_access_same_ device_slow_rsp.3054858200 |
| Directory | /workspace/45.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/45.xbar_error_and_unmapped_addr.379456718 |
| Short name | T1915 |
| Test name | |
| Test status | |
| Simulation time | 522174530 ps |
| CPU time | 20.68 seconds |
| Started | Aug 12 06:52:49 PM PDT 24 |
| Finished | Aug 12 06:53:09 PM PDT 24 |
| Peak memory | 575564 kb |
| Host | smart-f434407b-1a08-4dd7-b1ea-dedfc03f24f1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=379456718 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.xbar_error_and_unmapped_addr .379456718 |
| Directory | /workspace/45.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/45.xbar_error_random.2296117052 |
| Short name | T2479 |
| Test name | |
| Test status | |
| Simulation time | 1046008257 ps |
| CPU time | 33.58 seconds |
| Started | Aug 12 06:52:49 PM PDT 24 |
| Finished | Aug 12 06:53:22 PM PDT 24 |
| Peak memory | 575668 kb |
| Host | smart-9b29db4a-6fc5-4661-9046-e9531d687969 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2296117052 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.xbar_error_random.2296117052 |
| Directory | /workspace/45.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/45.xbar_random.1988748545 |
| Short name | T2530 |
| Test name | |
| Test status | |
| Simulation time | 494620963 ps |
| CPU time | 23.3 seconds |
| Started | Aug 12 06:52:39 PM PDT 24 |
| Finished | Aug 12 06:53:02 PM PDT 24 |
| Peak memory | 575616 kb |
| Host | smart-5b75dbe4-fbd9-4adb-a8ef-16f269d6c81c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1988748545 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.xbar_random.1988748545 |
| Directory | /workspace/45.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/45.xbar_random_large_delays.989498480 |
| Short name | T1573 |
| Test name | |
| Test status | |
| Simulation time | 19770723816 ps |
| CPU time | 206.01 seconds |
| Started | Aug 12 06:52:39 PM PDT 24 |
| Finished | Aug 12 06:56:05 PM PDT 24 |
| Peak memory | 575648 kb |
| Host | smart-7d9e5d77-d504-4a29-ab14-81c4db2a3a24 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=989498480 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.xbar_random_large_delays.989498480 |
| Directory | /workspace/45.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/45.xbar_random_slow_rsp.3462216744 |
| Short name | T2114 |
| Test name | |
| Test status | |
| Simulation time | 59218314907 ps |
| CPU time | 966.12 seconds |
| Started | Aug 12 06:52:39 PM PDT 24 |
| Finished | Aug 12 07:08:46 PM PDT 24 |
| Peak memory | 575752 kb |
| Host | smart-cc779373-6c0b-439f-9033-99c6657f508c |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3462216744 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.xbar_random_slow_rsp.3462216744 |
| Directory | /workspace/45.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/45.xbar_random_zero_delays.3791635798 |
| Short name | T2515 |
| Test name | |
| Test status | |
| Simulation time | 247460416 ps |
| CPU time | 21.65 seconds |
| Started | Aug 12 06:52:39 PM PDT 24 |
| Finished | Aug 12 06:53:01 PM PDT 24 |
| Peak memory | 575728 kb |
| Host | smart-647122bf-9516-4654-bdaf-bb4bce45dd79 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3791635798 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.xbar_random_zero_del ays.3791635798 |
| Directory | /workspace/45.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/45.xbar_same_source.1410730843 |
| Short name | T2265 |
| Test name | |
| Test status | |
| Simulation time | 510680146 ps |
| CPU time | 41.02 seconds |
| Started | Aug 12 06:52:41 PM PDT 24 |
| Finished | Aug 12 06:53:22 PM PDT 24 |
| Peak memory | 575552 kb |
| Host | smart-2eef5b88-7afc-402f-92e2-d8bec66a1d6e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1410730843 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.xbar_same_source.1410730843 |
| Directory | /workspace/45.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/45.xbar_smoke.820067942 |
| Short name | T2362 |
| Test name | |
| Test status | |
| Simulation time | 41128055 ps |
| CPU time | 5.79 seconds |
| Started | Aug 12 06:52:35 PM PDT 24 |
| Finished | Aug 12 06:52:41 PM PDT 24 |
| Peak memory | 573604 kb |
| Host | smart-c70cce2e-c550-48c5-8c1d-686fb42efcea |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=820067942 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.xbar_smoke.820067942 |
| Directory | /workspace/45.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/45.xbar_smoke_large_delays.2140790463 |
| Short name | T1926 |
| Test name | |
| Test status | |
| Simulation time | 8699453414 ps |
| CPU time | 89.42 seconds |
| Started | Aug 12 06:52:32 PM PDT 24 |
| Finished | Aug 12 06:54:02 PM PDT 24 |
| Peak memory | 573680 kb |
| Host | smart-9e242e62-df6e-4a37-9086-8aa277f948a2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2140790463 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.xbar_smoke_large_delays.2140790463 |
| Directory | /workspace/45.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/45.xbar_smoke_slow_rsp.4034616855 |
| Short name | T1968 |
| Test name | |
| Test status | |
| Simulation time | 4951349285 ps |
| CPU time | 82.44 seconds |
| Started | Aug 12 06:52:42 PM PDT 24 |
| Finished | Aug 12 06:54:05 PM PDT 24 |
| Peak memory | 573628 kb |
| Host | smart-85d978f2-7876-4ebd-8ec9-1414b3497b61 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4034616855 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.xbar_smoke_slow_rsp.4034616855 |
| Directory | /workspace/45.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/45.xbar_smoke_zero_delays.560753241 |
| Short name | T2559 |
| Test name | |
| Test status | |
| Simulation time | 45989907 ps |
| CPU time | 5.88 seconds |
| Started | Aug 12 06:52:33 PM PDT 24 |
| Finished | Aug 12 06:52:39 PM PDT 24 |
| Peak memory | 573616 kb |
| Host | smart-47df6a55-e6b8-4b89-8f89-5b544c187d21 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=560753241 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.xbar_smoke_zero_delays .560753241 |
| Directory | /workspace/45.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/45.xbar_stress_all.609011851 |
| Short name | T1849 |
| Test name | |
| Test status | |
| Simulation time | 8997961560 ps |
| CPU time | 332.89 seconds |
| Started | Aug 12 06:52:48 PM PDT 24 |
| Finished | Aug 12 06:58:21 PM PDT 24 |
| Peak memory | 575880 kb |
| Host | smart-9c0259a0-6b28-4d54-9981-7eaa81b9baa4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=609011851 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.xbar_stress_all.609011851 |
| Directory | /workspace/45.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/45.xbar_stress_all_with_error.3943505778 |
| Short name | T1603 |
| Test name | |
| Test status | |
| Simulation time | 2368055067 ps |
| CPU time | 188.2 seconds |
| Started | Aug 12 06:52:48 PM PDT 24 |
| Finished | Aug 12 06:55:57 PM PDT 24 |
| Peak memory | 575780 kb |
| Host | smart-dc8f4119-cdee-4c74-b571-18311bc32cc7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3943505778 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.xbar_stress_all_with_error.3943505778 |
| Directory | /workspace/45.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/45.xbar_stress_all_with_rand_reset.2327252756 |
| Short name | T761 |
| Test name | |
| Test status | |
| Simulation time | 274853933 ps |
| CPU time | 127.35 seconds |
| Started | Aug 12 06:52:49 PM PDT 24 |
| Finished | Aug 12 06:54:57 PM PDT 24 |
| Peak memory | 576560 kb |
| Host | smart-f33ed0a1-ce5a-4d02-aded-141f42af8011 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2327252756 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.xbar_stress_all _with_rand_reset.2327252756 |
| Directory | /workspace/45.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/45.xbar_stress_all_with_reset_error.3866051659 |
| Short name | T2360 |
| Test name | |
| Test status | |
| Simulation time | 2670902509 ps |
| CPU time | 156.29 seconds |
| Started | Aug 12 06:52:48 PM PDT 24 |
| Finished | Aug 12 06:55:24 PM PDT 24 |
| Peak memory | 575680 kb |
| Host | smart-31d27c0e-0fe0-4f32-a422-ff244dd650e8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3866051659 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.xbar_stress_al l_with_reset_error.3866051659 |
| Directory | /workspace/45.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/45.xbar_unmapped_addr.4170290143 |
| Short name | T762 |
| Test name | |
| Test status | |
| Simulation time | 38196962 ps |
| CPU time | 7.23 seconds |
| Started | Aug 12 06:52:50 PM PDT 24 |
| Finished | Aug 12 06:52:57 PM PDT 24 |
| Peak memory | 573668 kb |
| Host | smart-1f1a85b8-67d6-4b3b-9e46-f6d89147fe08 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4170290143 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.xbar_unmapped_addr.4170290143 |
| Directory | /workspace/45.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/46.xbar_access_same_device.3491841685 |
| Short name | T2902 |
| Test name | |
| Test status | |
| Simulation time | 239957522 ps |
| CPU time | 22.12 seconds |
| Started | Aug 12 06:52:48 PM PDT 24 |
| Finished | Aug 12 06:53:10 PM PDT 24 |
| Peak memory | 575596 kb |
| Host | smart-52bb13fd-e692-455c-bf62-36067a8f51f1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3491841685 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.xbar_access_same_device .3491841685 |
| Directory | /workspace/46.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/46.xbar_error_and_unmapped_addr.1724179657 |
| Short name | T2886 |
| Test name | |
| Test status | |
| Simulation time | 39868582 ps |
| CPU time | 7.12 seconds |
| Started | Aug 12 06:52:50 PM PDT 24 |
| Finished | Aug 12 06:52:57 PM PDT 24 |
| Peak memory | 573616 kb |
| Host | smart-9acf8bf3-2051-4c35-99b2-dac5dd6464ca |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1724179657 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.xbar_error_and_unmapped_add r.1724179657 |
| Directory | /workspace/46.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/46.xbar_error_random.2207659534 |
| Short name | T2469 |
| Test name | |
| Test status | |
| Simulation time | 91522475 ps |
| CPU time | 10.51 seconds |
| Started | Aug 12 06:52:52 PM PDT 24 |
| Finished | Aug 12 06:53:03 PM PDT 24 |
| Peak memory | 575604 kb |
| Host | smart-c1782c8e-afca-4575-b817-c0290150f1b2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2207659534 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.xbar_error_random.2207659534 |
| Directory | /workspace/46.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/46.xbar_random.2838755889 |
| Short name | T1785 |
| Test name | |
| Test status | |
| Simulation time | 631044121 ps |
| CPU time | 54.22 seconds |
| Started | Aug 12 06:52:48 PM PDT 24 |
| Finished | Aug 12 06:53:42 PM PDT 24 |
| Peak memory | 575716 kb |
| Host | smart-e5301655-46da-4ff0-987f-0214ed29ec28 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2838755889 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.xbar_random.2838755889 |
| Directory | /workspace/46.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/46.xbar_random_large_delays.1407786344 |
| Short name | T2630 |
| Test name | |
| Test status | |
| Simulation time | 77925333368 ps |
| CPU time | 781.32 seconds |
| Started | Aug 12 06:52:50 PM PDT 24 |
| Finished | Aug 12 07:05:51 PM PDT 24 |
| Peak memory | 575740 kb |
| Host | smart-c045c5fc-4b23-48fe-887b-3c28b6c735b9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1407786344 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.xbar_random_large_delays.1407786344 |
| Directory | /workspace/46.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/46.xbar_random_slow_rsp.3434906102 |
| Short name | T617 |
| Test name | |
| Test status | |
| Simulation time | 69317138170 ps |
| CPU time | 1239.48 seconds |
| Started | Aug 12 06:52:52 PM PDT 24 |
| Finished | Aug 12 07:13:31 PM PDT 24 |
| Peak memory | 575636 kb |
| Host | smart-9e1e17c2-5847-4762-8f7c-dc57f057b24c |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3434906102 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.xbar_random_slow_rsp.3434906102 |
| Directory | /workspace/46.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/46.xbar_random_zero_delays.1910355309 |
| Short name | T1861 |
| Test name | |
| Test status | |
| Simulation time | 492156326 ps |
| CPU time | 47.83 seconds |
| Started | Aug 12 06:52:53 PM PDT 24 |
| Finished | Aug 12 06:53:41 PM PDT 24 |
| Peak memory | 575568 kb |
| Host | smart-49f8a5ad-0017-48fe-abd0-e1ba48ad9b4d |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1910355309 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.xbar_random_zero_del ays.1910355309 |
| Directory | /workspace/46.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/46.xbar_same_source.1910012964 |
| Short name | T1780 |
| Test name | |
| Test status | |
| Simulation time | 112654393 ps |
| CPU time | 10.83 seconds |
| Started | Aug 12 06:52:48 PM PDT 24 |
| Finished | Aug 12 06:52:59 PM PDT 24 |
| Peak memory | 575640 kb |
| Host | smart-31b6b693-47c2-4d82-9bb5-bf55a06986a6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1910012964 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.xbar_same_source.1910012964 |
| Directory | /workspace/46.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/46.xbar_smoke.2623300548 |
| Short name | T711 |
| Test name | |
| Test status | |
| Simulation time | 175021382 ps |
| CPU time | 8.26 seconds |
| Started | Aug 12 06:52:47 PM PDT 24 |
| Finished | Aug 12 06:52:55 PM PDT 24 |
| Peak memory | 574276 kb |
| Host | smart-123bf55d-c27e-49a9-b85f-4e0f757fe534 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2623300548 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.xbar_smoke.2623300548 |
| Directory | /workspace/46.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/46.xbar_smoke_large_delays.1711132027 |
| Short name | T2618 |
| Test name | |
| Test status | |
| Simulation time | 8125376436 ps |
| CPU time | 82.36 seconds |
| Started | Aug 12 06:52:48 PM PDT 24 |
| Finished | Aug 12 06:54:11 PM PDT 24 |
| Peak memory | 573572 kb |
| Host | smart-7887e969-ab8d-492d-9483-06512935cca4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1711132027 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.xbar_smoke_large_delays.1711132027 |
| Directory | /workspace/46.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/46.xbar_smoke_slow_rsp.612271439 |
| Short name | T2888 |
| Test name | |
| Test status | |
| Simulation time | 4982076299 ps |
| CPU time | 86.25 seconds |
| Started | Aug 12 06:52:49 PM PDT 24 |
| Finished | Aug 12 06:54:16 PM PDT 24 |
| Peak memory | 573692 kb |
| Host | smart-d75133d1-e788-4320-8a85-e1dae704e02f |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=612271439 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.xbar_smoke_slow_rsp.612271439 |
| Directory | /workspace/46.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/46.xbar_smoke_zero_delays.3551466417 |
| Short name | T2892 |
| Test name | |
| Test status | |
| Simulation time | 48339456 ps |
| CPU time | 6.62 seconds |
| Started | Aug 12 06:52:52 PM PDT 24 |
| Finished | Aug 12 06:52:58 PM PDT 24 |
| Peak memory | 573568 kb |
| Host | smart-97f79f75-9fc8-4063-8fdf-c8835f654586 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3551466417 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.xbar_smoke_zero_delay s.3551466417 |
| Directory | /workspace/46.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/46.xbar_stress_all.496135094 |
| Short name | T1766 |
| Test name | |
| Test status | |
| Simulation time | 2352003895 ps |
| CPU time | 211.86 seconds |
| Started | Aug 12 06:52:52 PM PDT 24 |
| Finished | Aug 12 06:56:24 PM PDT 24 |
| Peak memory | 575812 kb |
| Host | smart-cd916ca6-cbbb-4eea-ac17-cd12fb3bd621 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=496135094 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.xbar_stress_all.496135094 |
| Directory | /workspace/46.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/46.xbar_stress_all_with_error.546969701 |
| Short name | T2405 |
| Test name | |
| Test status | |
| Simulation time | 3519019374 ps |
| CPU time | 274.9 seconds |
| Started | Aug 12 06:52:52 PM PDT 24 |
| Finished | Aug 12 06:57:27 PM PDT 24 |
| Peak memory | 576456 kb |
| Host | smart-1d857e09-2946-4c9f-a75d-ef774cc12574 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=546969701 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.xbar_stress_all_with_error.546969701 |
| Directory | /workspace/46.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/46.xbar_stress_all_with_rand_reset.666823757 |
| Short name | T2371 |
| Test name | |
| Test status | |
| Simulation time | 7583502066 ps |
| CPU time | 442.29 seconds |
| Started | Aug 12 06:52:52 PM PDT 24 |
| Finished | Aug 12 07:00:14 PM PDT 24 |
| Peak memory | 575776 kb |
| Host | smart-1e1f7283-9448-413e-a92b-a53a87080373 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=666823757 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_res et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.xbar_stress_all_ with_rand_reset.666823757 |
| Directory | /workspace/46.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/46.xbar_stress_all_with_reset_error.1015396847 |
| Short name | T1949 |
| Test name | |
| Test status | |
| Simulation time | 2082234064 ps |
| CPU time | 147.3 seconds |
| Started | Aug 12 06:53:02 PM PDT 24 |
| Finished | Aug 12 06:55:29 PM PDT 24 |
| Peak memory | 575660 kb |
| Host | smart-aa47ba53-949c-4719-9a5f-8687ca5dfee9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1015396847 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.xbar_stress_al l_with_reset_error.1015396847 |
| Directory | /workspace/46.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/46.xbar_unmapped_addr.2121469387 |
| Short name | T2444 |
| Test name | |
| Test status | |
| Simulation time | 1143748060 ps |
| CPU time | 52.3 seconds |
| Started | Aug 12 06:52:52 PM PDT 24 |
| Finished | Aug 12 06:53:44 PM PDT 24 |
| Peak memory | 575748 kb |
| Host | smart-e370b1ca-95d9-4a7b-8f95-2796b6e57eef |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2121469387 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.xbar_unmapped_addr.2121469387 |
| Directory | /workspace/46.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/47.xbar_access_same_device.2186297631 |
| Short name | T469 |
| Test name | |
| Test status | |
| Simulation time | 1640116464 ps |
| CPU time | 65.44 seconds |
| Started | Aug 12 06:53:00 PM PDT 24 |
| Finished | Aug 12 06:54:05 PM PDT 24 |
| Peak memory | 575720 kb |
| Host | smart-afee80cd-876a-4452-88d9-7e90dc772df7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2186297631 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.xbar_access_same_device .2186297631 |
| Directory | /workspace/47.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/47.xbar_access_same_device_slow_rsp.2978763156 |
| Short name | T2201 |
| Test name | |
| Test status | |
| Simulation time | 50263118237 ps |
| CPU time | 846.21 seconds |
| Started | Aug 12 06:52:57 PM PDT 24 |
| Finished | Aug 12 07:07:03 PM PDT 24 |
| Peak memory | 575792 kb |
| Host | smart-ed5a4eed-6bee-4694-8b6d-dc3604d1d638 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2978763156 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.xbar_access_same_ device_slow_rsp.2978763156 |
| Directory | /workspace/47.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/47.xbar_error_and_unmapped_addr.2676247210 |
| Short name | T2884 |
| Test name | |
| Test status | |
| Simulation time | 105161000 ps |
| CPU time | 12.22 seconds |
| Started | Aug 12 06:52:59 PM PDT 24 |
| Finished | Aug 12 06:53:11 PM PDT 24 |
| Peak memory | 575732 kb |
| Host | smart-08e2bf0f-d490-4116-99cf-d1907bf25c9f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2676247210 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.xbar_error_and_unmapped_add r.2676247210 |
| Directory | /workspace/47.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/47.xbar_error_random.558960013 |
| Short name | T1555 |
| Test name | |
| Test status | |
| Simulation time | 1701687670 ps |
| CPU time | 54.45 seconds |
| Started | Aug 12 06:53:00 PM PDT 24 |
| Finished | Aug 12 06:53:55 PM PDT 24 |
| Peak memory | 575780 kb |
| Host | smart-4c9bb6e3-2c26-44ac-8535-31609ee6bbb5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=558960013 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.xbar_error_random.558960013 |
| Directory | /workspace/47.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/47.xbar_random.3052168665 |
| Short name | T2693 |
| Test name | |
| Test status | |
| Simulation time | 359572169 ps |
| CPU time | 16.3 seconds |
| Started | Aug 12 06:53:01 PM PDT 24 |
| Finished | Aug 12 06:53:17 PM PDT 24 |
| Peak memory | 575500 kb |
| Host | smart-1c958b92-a87f-47ea-bd6a-c2c9c51036bd |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3052168665 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.xbar_random.3052168665 |
| Directory | /workspace/47.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/47.xbar_random_large_delays.1295038015 |
| Short name | T1930 |
| Test name | |
| Test status | |
| Simulation time | 17205839369 ps |
| CPU time | 181.03 seconds |
| Started | Aug 12 06:52:57 PM PDT 24 |
| Finished | Aug 12 06:55:58 PM PDT 24 |
| Peak memory | 575716 kb |
| Host | smart-6a86152a-2295-40f0-91b2-f5c586f9a7c1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1295038015 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.xbar_random_large_delays.1295038015 |
| Directory | /workspace/47.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/47.xbar_random_slow_rsp.49511508 |
| Short name | T2619 |
| Test name | |
| Test status | |
| Simulation time | 47730388824 ps |
| CPU time | 784.43 seconds |
| Started | Aug 12 06:53:11 PM PDT 24 |
| Finished | Aug 12 07:06:16 PM PDT 24 |
| Peak memory | 575780 kb |
| Host | smart-cdd3aa51-b5eb-456b-b23a-b3c5abfc03be |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49511508 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.xbar_random_slow_rsp.49511508 |
| Directory | /workspace/47.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/47.xbar_random_zero_delays.1079993656 |
| Short name | T1931 |
| Test name | |
| Test status | |
| Simulation time | 267552191 ps |
| CPU time | 29.23 seconds |
| Started | Aug 12 06:52:57 PM PDT 24 |
| Finished | Aug 12 06:53:26 PM PDT 24 |
| Peak memory | 575664 kb |
| Host | smart-8f6a0b08-6217-4fcc-9403-23938ce5838d |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1079993656 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.xbar_random_zero_del ays.1079993656 |
| Directory | /workspace/47.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/47.xbar_same_source.2186196742 |
| Short name | T1761 |
| Test name | |
| Test status | |
| Simulation time | 278581391 ps |
| CPU time | 21.62 seconds |
| Started | Aug 12 06:53:12 PM PDT 24 |
| Finished | Aug 12 06:53:34 PM PDT 24 |
| Peak memory | 575672 kb |
| Host | smart-e30153c5-05f6-4734-8430-bc0162b1e422 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2186196742 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.xbar_same_source.2186196742 |
| Directory | /workspace/47.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/47.xbar_smoke.1847101651 |
| Short name | T2576 |
| Test name | |
| Test status | |
| Simulation time | 53234717 ps |
| CPU time | 6.55 seconds |
| Started | Aug 12 06:52:59 PM PDT 24 |
| Finished | Aug 12 06:53:06 PM PDT 24 |
| Peak memory | 574248 kb |
| Host | smart-d249156d-0c7e-4f71-ad3a-892289df8189 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1847101651 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.xbar_smoke.1847101651 |
| Directory | /workspace/47.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/47.xbar_smoke_large_delays.2849402139 |
| Short name | T1565 |
| Test name | |
| Test status | |
| Simulation time | 5325482829 ps |
| CPU time | 55.04 seconds |
| Started | Aug 12 06:52:58 PM PDT 24 |
| Finished | Aug 12 06:53:53 PM PDT 24 |
| Peak memory | 573736 kb |
| Host | smart-acb5beb8-954b-4d46-a530-29194170bdc8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2849402139 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.xbar_smoke_large_delays.2849402139 |
| Directory | /workspace/47.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/47.xbar_smoke_slow_rsp.1062001929 |
| Short name | T555 |
| Test name | |
| Test status | |
| Simulation time | 6291206860 ps |
| CPU time | 97.84 seconds |
| Started | Aug 12 06:53:00 PM PDT 24 |
| Finished | Aug 12 06:54:38 PM PDT 24 |
| Peak memory | 573772 kb |
| Host | smart-4a5b6033-ee4c-434d-9a99-3c38f09acf61 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1062001929 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.xbar_smoke_slow_rsp.1062001929 |
| Directory | /workspace/47.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/47.xbar_smoke_zero_delays.592056539 |
| Short name | T1950 |
| Test name | |
| Test status | |
| Simulation time | 43417244 ps |
| CPU time | 6.06 seconds |
| Started | Aug 12 06:53:01 PM PDT 24 |
| Finished | Aug 12 06:53:08 PM PDT 24 |
| Peak memory | 574268 kb |
| Host | smart-710aa908-c8d0-4f6e-85cc-38efbd3538b3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=592056539 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.xbar_smoke_zero_delays .592056539 |
| Directory | /workspace/47.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/47.xbar_stress_all.4197821265 |
| Short name | T510 |
| Test name | |
| Test status | |
| Simulation time | 7509671142 ps |
| CPU time | 243.96 seconds |
| Started | Aug 12 06:52:57 PM PDT 24 |
| Finished | Aug 12 06:57:01 PM PDT 24 |
| Peak memory | 575752 kb |
| Host | smart-358eb301-35f3-4c02-bc48-f33ee06bd77d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4197821265 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.xbar_stress_all.4197821265 |
| Directory | /workspace/47.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/47.xbar_stress_all_with_error.175980175 |
| Short name | T916 |
| Test name | |
| Test status | |
| Simulation time | 9954615895 ps |
| CPU time | 355.02 seconds |
| Started | Aug 12 06:53:00 PM PDT 24 |
| Finished | Aug 12 06:58:55 PM PDT 24 |
| Peak memory | 575908 kb |
| Host | smart-cd7c3fa4-4be0-42f8-803c-aee1fcfe0c6e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=175980175 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.xbar_stress_all_with_error.175980175 |
| Directory | /workspace/47.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/47.xbar_stress_all_with_rand_reset.713387230 |
| Short name | T2789 |
| Test name | |
| Test status | |
| Simulation time | 4383554930 ps |
| CPU time | 295.46 seconds |
| Started | Aug 12 06:52:58 PM PDT 24 |
| Finished | Aug 12 06:57:54 PM PDT 24 |
| Peak memory | 575760 kb |
| Host | smart-645dcc07-ea5c-4073-afb7-4e645e95a0ce |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=713387230 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_res et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.xbar_stress_all_ with_rand_reset.713387230 |
| Directory | /workspace/47.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/47.xbar_stress_all_with_reset_error.1282118748 |
| Short name | T950 |
| Test name | |
| Test status | |
| Simulation time | 400996657 ps |
| CPU time | 116.48 seconds |
| Started | Aug 12 06:52:59 PM PDT 24 |
| Finished | Aug 12 06:54:56 PM PDT 24 |
| Peak memory | 576516 kb |
| Host | smart-ca7d4b90-4ec9-4bf6-b3a7-bac79cecbe36 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1282118748 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.xbar_stress_al l_with_reset_error.1282118748 |
| Directory | /workspace/47.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/47.xbar_unmapped_addr.2567288385 |
| Short name | T699 |
| Test name | |
| Test status | |
| Simulation time | 798844220 ps |
| CPU time | 37.47 seconds |
| Started | Aug 12 06:52:57 PM PDT 24 |
| Finished | Aug 12 06:53:34 PM PDT 24 |
| Peak memory | 575684 kb |
| Host | smart-f170713e-c433-407f-9666-8ba13e5fa6ea |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2567288385 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.xbar_unmapped_addr.2567288385 |
| Directory | /workspace/47.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/48.xbar_access_same_device_slow_rsp.3897709028 |
| Short name | T521 |
| Test name | |
| Test status | |
| Simulation time | 44693363887 ps |
| CPU time | 766.23 seconds |
| Started | Aug 12 06:53:00 PM PDT 24 |
| Finished | Aug 12 07:05:46 PM PDT 24 |
| Peak memory | 575648 kb |
| Host | smart-3a49b742-407f-4d51-b5eb-47cb2e379b72 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3897709028 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.xbar_access_same_ device_slow_rsp.3897709028 |
| Directory | /workspace/48.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/48.xbar_error_and_unmapped_addr.2717974972 |
| Short name | T1658 |
| Test name | |
| Test status | |
| Simulation time | 1382475157 ps |
| CPU time | 55.76 seconds |
| Started | Aug 12 06:53:05 PM PDT 24 |
| Finished | Aug 12 06:54:01 PM PDT 24 |
| Peak memory | 575700 kb |
| Host | smart-52dceb77-782c-48af-a798-8113b062caf1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2717974972 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.xbar_error_and_unmapped_add r.2717974972 |
| Directory | /workspace/48.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/48.xbar_error_random.3791705649 |
| Short name | T2096 |
| Test name | |
| Test status | |
| Simulation time | 377636586 ps |
| CPU time | 32.23 seconds |
| Started | Aug 12 06:53:12 PM PDT 24 |
| Finished | Aug 12 06:53:44 PM PDT 24 |
| Peak memory | 575684 kb |
| Host | smart-ec7827ea-4eea-41d6-b4be-6760e20e880a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3791705649 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.xbar_error_random.3791705649 |
| Directory | /workspace/48.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/48.xbar_random.2459357225 |
| Short name | T2846 |
| Test name | |
| Test status | |
| Simulation time | 1883928627 ps |
| CPU time | 67.77 seconds |
| Started | Aug 12 06:52:59 PM PDT 24 |
| Finished | Aug 12 06:54:07 PM PDT 24 |
| Peak memory | 575588 kb |
| Host | smart-0f64d48d-466f-4584-97d7-5e0577089af6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2459357225 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.xbar_random.2459357225 |
| Directory | /workspace/48.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/48.xbar_random_large_delays.3224385457 |
| Short name | T2907 |
| Test name | |
| Test status | |
| Simulation time | 43445216775 ps |
| CPU time | 493.98 seconds |
| Started | Aug 12 06:52:58 PM PDT 24 |
| Finished | Aug 12 07:01:12 PM PDT 24 |
| Peak memory | 575660 kb |
| Host | smart-c5b0d1bc-3720-4f43-9211-958876560eee |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3224385457 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.xbar_random_large_delays.3224385457 |
| Directory | /workspace/48.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/48.xbar_random_slow_rsp.619260945 |
| Short name | T729 |
| Test name | |
| Test status | |
| Simulation time | 38977112738 ps |
| CPU time | 625.77 seconds |
| Started | Aug 12 06:53:12 PM PDT 24 |
| Finished | Aug 12 07:03:38 PM PDT 24 |
| Peak memory | 575784 kb |
| Host | smart-040c9af4-2dd0-427a-85c8-cf50cd7d0a2d |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=619260945 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.xbar_random_slow_rsp.619260945 |
| Directory | /workspace/48.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/48.xbar_random_zero_delays.2584279833 |
| Short name | T2415 |
| Test name | |
| Test status | |
| Simulation time | 463408846 ps |
| CPU time | 37.97 seconds |
| Started | Aug 12 06:52:58 PM PDT 24 |
| Finished | Aug 12 06:53:36 PM PDT 24 |
| Peak memory | 575680 kb |
| Host | smart-0a7284a5-4e0b-46b2-b337-e5cb582f96bc |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2584279833 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.xbar_random_zero_del ays.2584279833 |
| Directory | /workspace/48.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/48.xbar_same_source.3948829825 |
| Short name | T2244 |
| Test name | |
| Test status | |
| Simulation time | 293604969 ps |
| CPU time | 21.36 seconds |
| Started | Aug 12 06:52:59 PM PDT 24 |
| Finished | Aug 12 06:53:21 PM PDT 24 |
| Peak memory | 575656 kb |
| Host | smart-6edb2fbc-dfd9-42f1-ad1e-40c9c34a9b42 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3948829825 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.xbar_same_source.3948829825 |
| Directory | /workspace/48.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/48.xbar_smoke.3361170673 |
| Short name | T2500 |
| Test name | |
| Test status | |
| Simulation time | 267603669 ps |
| CPU time | 10.51 seconds |
| Started | Aug 12 06:52:57 PM PDT 24 |
| Finished | Aug 12 06:53:08 PM PDT 24 |
| Peak memory | 573492 kb |
| Host | smart-9a4ccf9e-6418-4930-a254-94d063049c95 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3361170673 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.xbar_smoke.3361170673 |
| Directory | /workspace/48.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/48.xbar_smoke_large_delays.4041651618 |
| Short name | T2725 |
| Test name | |
| Test status | |
| Simulation time | 9277896855 ps |
| CPU time | 90.25 seconds |
| Started | Aug 12 06:53:02 PM PDT 24 |
| Finished | Aug 12 06:54:32 PM PDT 24 |
| Peak memory | 574308 kb |
| Host | smart-a3fb13e1-80c2-4470-b53b-a9c8c40aafb7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4041651618 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.xbar_smoke_large_delays.4041651618 |
| Directory | /workspace/48.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/48.xbar_smoke_slow_rsp.2442162835 |
| Short name | T2916 |
| Test name | |
| Test status | |
| Simulation time | 5238459207 ps |
| CPU time | 89.06 seconds |
| Started | Aug 12 06:53:01 PM PDT 24 |
| Finished | Aug 12 06:54:30 PM PDT 24 |
| Peak memory | 573688 kb |
| Host | smart-dbf83825-812d-4319-96ac-783ca765a595 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2442162835 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.xbar_smoke_slow_rsp.2442162835 |
| Directory | /workspace/48.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/48.xbar_smoke_zero_delays.2068079822 |
| Short name | T2757 |
| Test name | |
| Test status | |
| Simulation time | 41399938 ps |
| CPU time | 6.13 seconds |
| Started | Aug 12 06:52:57 PM PDT 24 |
| Finished | Aug 12 06:53:03 PM PDT 24 |
| Peak memory | 574332 kb |
| Host | smart-e41f041c-1a00-4fa3-98f2-a7b3f9e84bcc |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2068079822 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.xbar_smoke_zero_delay s.2068079822 |
| Directory | /workspace/48.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/48.xbar_stress_all.1346468466 |
| Short name | T2547 |
| Test name | |
| Test status | |
| Simulation time | 2285448564 ps |
| CPU time | 93.49 seconds |
| Started | Aug 12 06:53:11 PM PDT 24 |
| Finished | Aug 12 06:54:45 PM PDT 24 |
| Peak memory | 575784 kb |
| Host | smart-4cff2ef2-401f-4444-907e-f7d2da9cfe7d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1346468466 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.xbar_stress_all.1346468466 |
| Directory | /workspace/48.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/48.xbar_stress_all_with_error.295249161 |
| Short name | T1776 |
| Test name | |
| Test status | |
| Simulation time | 1598023841 ps |
| CPU time | 128.43 seconds |
| Started | Aug 12 06:53:06 PM PDT 24 |
| Finished | Aug 12 06:55:15 PM PDT 24 |
| Peak memory | 575684 kb |
| Host | smart-bdd6cc05-a984-40df-9c51-e9195256c1b9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=295249161 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.xbar_stress_all_with_error.295249161 |
| Directory | /workspace/48.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/48.xbar_stress_all_with_rand_reset.3729643138 |
| Short name | T2588 |
| Test name | |
| Test status | |
| Simulation time | 10059360064 ps |
| CPU time | 628.35 seconds |
| Started | Aug 12 06:53:06 PM PDT 24 |
| Finished | Aug 12 07:03:34 PM PDT 24 |
| Peak memory | 575900 kb |
| Host | smart-45685d9d-3b89-41fb-bf6d-35741eb739b4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3729643138 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.xbar_stress_all _with_rand_reset.3729643138 |
| Directory | /workspace/48.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/48.xbar_stress_all_with_reset_error.179307059 |
| Short name | T2089 |
| Test name | |
| Test status | |
| Simulation time | 654776844 ps |
| CPU time | 163.32 seconds |
| Started | Aug 12 06:53:06 PM PDT 24 |
| Finished | Aug 12 06:55:50 PM PDT 24 |
| Peak memory | 575724 kb |
| Host | smart-773e7268-01db-4582-8f9f-5b0ab113877b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=179307059 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.xbar_stress_all _with_reset_error.179307059 |
| Directory | /workspace/48.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/48.xbar_unmapped_addr.1404154900 |
| Short name | T2466 |
| Test name | |
| Test status | |
| Simulation time | 312557109 ps |
| CPU time | 17.27 seconds |
| Started | Aug 12 06:52:59 PM PDT 24 |
| Finished | Aug 12 06:53:17 PM PDT 24 |
| Peak memory | 575736 kb |
| Host | smart-90a52cda-6b9d-4780-9734-87d246c114fc |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1404154900 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.xbar_unmapped_addr.1404154900 |
| Directory | /workspace/48.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/49.xbar_access_same_device.2094226066 |
| Short name | T2908 |
| Test name | |
| Test status | |
| Simulation time | 272345286 ps |
| CPU time | 25.44 seconds |
| Started | Aug 12 06:53:07 PM PDT 24 |
| Finished | Aug 12 06:53:33 PM PDT 24 |
| Peak memory | 575652 kb |
| Host | smart-6182132d-891e-411d-96cb-785ed8ab2001 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2094226066 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.xbar_access_same_device .2094226066 |
| Directory | /workspace/49.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/49.xbar_access_same_device_slow_rsp.631901172 |
| Short name | T2572 |
| Test name | |
| Test status | |
| Simulation time | 151524268487 ps |
| CPU time | 2587.45 seconds |
| Started | Aug 12 06:53:14 PM PDT 24 |
| Finished | Aug 12 07:36:22 PM PDT 24 |
| Peak memory | 575644 kb |
| Host | smart-5e432feb-8127-444c-9fcf-c616a62b950c |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=631901172 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.xbar_access_same_d evice_slow_rsp.631901172 |
| Directory | /workspace/49.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/49.xbar_error_and_unmapped_addr.3307912333 |
| Short name | T2497 |
| Test name | |
| Test status | |
| Simulation time | 468049670 ps |
| CPU time | 19.4 seconds |
| Started | Aug 12 06:53:09 PM PDT 24 |
| Finished | Aug 12 06:53:28 PM PDT 24 |
| Peak memory | 575756 kb |
| Host | smart-38343089-5ff1-494b-b16e-4539c95f008a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3307912333 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.xbar_error_and_unmapped_add r.3307912333 |
| Directory | /workspace/49.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/49.xbar_error_random.2600137777 |
| Short name | T1464 |
| Test name | |
| Test status | |
| Simulation time | 380607655 ps |
| CPU time | 27.03 seconds |
| Started | Aug 12 06:53:04 PM PDT 24 |
| Finished | Aug 12 06:53:32 PM PDT 24 |
| Peak memory | 575540 kb |
| Host | smart-bcbc9aa3-7619-4f7f-8d8e-28c748caf0d5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2600137777 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.xbar_error_random.2600137777 |
| Directory | /workspace/49.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/49.xbar_random.2059162137 |
| Short name | T665 |
| Test name | |
| Test status | |
| Simulation time | 1507328925 ps |
| CPU time | 52.67 seconds |
| Started | Aug 12 06:53:08 PM PDT 24 |
| Finished | Aug 12 06:54:01 PM PDT 24 |
| Peak memory | 575604 kb |
| Host | smart-66a53adf-ef9d-4cb9-b497-6d4c643d1f9c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2059162137 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.xbar_random.2059162137 |
| Directory | /workspace/49.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/49.xbar_random_large_delays.2084279419 |
| Short name | T2552 |
| Test name | |
| Test status | |
| Simulation time | 77210202536 ps |
| CPU time | 796 seconds |
| Started | Aug 12 06:53:09 PM PDT 24 |
| Finished | Aug 12 07:06:25 PM PDT 24 |
| Peak memory | 575644 kb |
| Host | smart-ee7dde53-02ab-4a2d-8db5-cb605fd9d0f3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2084279419 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.xbar_random_large_delays.2084279419 |
| Directory | /workspace/49.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/49.xbar_random_slow_rsp.3394406307 |
| Short name | T1589 |
| Test name | |
| Test status | |
| Simulation time | 11446370318 ps |
| CPU time | 193.77 seconds |
| Started | Aug 12 06:53:06 PM PDT 24 |
| Finished | Aug 12 06:56:20 PM PDT 24 |
| Peak memory | 575612 kb |
| Host | smart-ec56af07-ebf6-475a-8b48-3d1756dd85b3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3394406307 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.xbar_random_slow_rsp.3394406307 |
| Directory | /workspace/49.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/49.xbar_random_zero_delays.1015296538 |
| Short name | T1882 |
| Test name | |
| Test status | |
| Simulation time | 67776906 ps |
| CPU time | 7.91 seconds |
| Started | Aug 12 06:53:08 PM PDT 24 |
| Finished | Aug 12 06:53:16 PM PDT 24 |
| Peak memory | 575512 kb |
| Host | smart-49903477-861d-4bf2-9b12-5fcb930993ae |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1015296538 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.xbar_random_zero_del ays.1015296538 |
| Directory | /workspace/49.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/49.xbar_same_source.1075168032 |
| Short name | T642 |
| Test name | |
| Test status | |
| Simulation time | 2643130265 ps |
| CPU time | 83.5 seconds |
| Started | Aug 12 06:53:11 PM PDT 24 |
| Finished | Aug 12 06:54:35 PM PDT 24 |
| Peak memory | 575592 kb |
| Host | smart-b629ccaf-52a0-4083-a361-1e1450100b70 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1075168032 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.xbar_same_source.1075168032 |
| Directory | /workspace/49.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/49.xbar_smoke.1516908931 |
| Short name | T1826 |
| Test name | |
| Test status | |
| Simulation time | 40007701 ps |
| CPU time | 5.28 seconds |
| Started | Aug 12 06:53:14 PM PDT 24 |
| Finished | Aug 12 06:53:20 PM PDT 24 |
| Peak memory | 573592 kb |
| Host | smart-5f136a8c-46b6-49b7-ba27-13524e0e246c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1516908931 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.xbar_smoke.1516908931 |
| Directory | /workspace/49.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/49.xbar_smoke_large_delays.1918575285 |
| Short name | T2557 |
| Test name | |
| Test status | |
| Simulation time | 8544483486 ps |
| CPU time | 87.87 seconds |
| Started | Aug 12 06:53:08 PM PDT 24 |
| Finished | Aug 12 06:54:36 PM PDT 24 |
| Peak memory | 574340 kb |
| Host | smart-f031b3ec-2f4d-4131-8db1-d5f9819d92d7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1918575285 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.xbar_smoke_large_delays.1918575285 |
| Directory | /workspace/49.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/49.xbar_smoke_slow_rsp.194992511 |
| Short name | T1448 |
| Test name | |
| Test status | |
| Simulation time | 5461468027 ps |
| CPU time | 96.45 seconds |
| Started | Aug 12 06:53:07 PM PDT 24 |
| Finished | Aug 12 06:54:43 PM PDT 24 |
| Peak memory | 573656 kb |
| Host | smart-45b05100-7910-4955-8f61-0b28ded0df46 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=194992511 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.xbar_smoke_slow_rsp.194992511 |
| Directory | /workspace/49.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/49.xbar_smoke_zero_delays.1603646919 |
| Short name | T1637 |
| Test name | |
| Test status | |
| Simulation time | 47033265 ps |
| CPU time | 6.08 seconds |
| Started | Aug 12 06:53:06 PM PDT 24 |
| Finished | Aug 12 06:53:12 PM PDT 24 |
| Peak memory | 573624 kb |
| Host | smart-02ffb372-4323-4143-aaec-5527c512343a |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1603646919 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.xbar_smoke_zero_delay s.1603646919 |
| Directory | /workspace/49.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/49.xbar_stress_all.3776676356 |
| Short name | T602 |
| Test name | |
| Test status | |
| Simulation time | 4603574270 ps |
| CPU time | 154.26 seconds |
| Started | Aug 12 06:53:08 PM PDT 24 |
| Finished | Aug 12 06:55:42 PM PDT 24 |
| Peak memory | 575928 kb |
| Host | smart-2777f390-9263-4b01-a128-725f6c2f510c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3776676356 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.xbar_stress_all.3776676356 |
| Directory | /workspace/49.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/49.xbar_stress_all_with_error.3002041706 |
| Short name | T1719 |
| Test name | |
| Test status | |
| Simulation time | 2276706338 ps |
| CPU time | 182.39 seconds |
| Started | Aug 12 06:53:12 PM PDT 24 |
| Finished | Aug 12 06:56:15 PM PDT 24 |
| Peak memory | 576244 kb |
| Host | smart-e4f6e401-5a7d-44f5-8f90-cb5e429e625f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3002041706 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.xbar_stress_all_with_error.3002041706 |
| Directory | /workspace/49.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/49.xbar_stress_all_with_rand_reset.2497087517 |
| Short name | T2843 |
| Test name | |
| Test status | |
| Simulation time | 350891977 ps |
| CPU time | 109.74 seconds |
| Started | Aug 12 06:53:14 PM PDT 24 |
| Finished | Aug 12 06:55:04 PM PDT 24 |
| Peak memory | 575740 kb |
| Host | smart-50141036-149e-4d7d-a90c-a237a08956cf |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2497087517 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.xbar_stress_all _with_rand_reset.2497087517 |
| Directory | /workspace/49.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/49.xbar_stress_all_with_reset_error.2005274790 |
| Short name | T952 |
| Test name | |
| Test status | |
| Simulation time | 6921543387 ps |
| CPU time | 307.14 seconds |
| Started | Aug 12 06:53:12 PM PDT 24 |
| Finished | Aug 12 06:58:19 PM PDT 24 |
| Peak memory | 575768 kb |
| Host | smart-812ca31e-a17d-4446-ae6e-917fb51292da |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2005274790 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.xbar_stress_al l_with_reset_error.2005274790 |
| Directory | /workspace/49.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/49.xbar_unmapped_addr.2254567396 |
| Short name | T588 |
| Test name | |
| Test status | |
| Simulation time | 296193663 ps |
| CPU time | 33.32 seconds |
| Started | Aug 12 06:53:13 PM PDT 24 |
| Finished | Aug 12 06:53:46 PM PDT 24 |
| Peak memory | 575728 kb |
| Host | smart-fec36abe-fd3b-4ac2-ab75-2f714ecd48dd |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2254567396 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.xbar_unmapped_addr.2254567396 |
| Directory | /workspace/49.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/5.chip_csr_mem_rw_with_rand_reset.586396073 |
| Short name | T456 |
| Test name | |
| Test status | |
| Simulation time | 6153589612 ps |
| CPU time | 472.44 seconds |
| Started | Aug 12 06:47:28 PM PDT 24 |
| Finished | Aug 12 06:55:21 PM PDT 24 |
| Peak memory | 637160 kb |
| Host | smart-a53fbceb-e4a6-404a-a16b-f59fe7848039 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=586396073 -assert nopostproc +U VM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top. vdb -cm_log /dev/null -cm_name 5.chip_csr_mem_rw_with_rand_reset.586396073 |
| Directory | /workspace/5.chip_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/5.chip_csr_rw.1656000410 |
| Short name | T157 |
| Test name | |
| Test status | |
| Simulation time | 5689251400 ps |
| CPU time | 656.39 seconds |
| Started | Aug 12 06:47:28 PM PDT 24 |
| Finished | Aug 12 06:58:24 PM PDT 24 |
| Peak memory | 598256 kb |
| Host | smart-8a088bfb-0fd2-4b77-a622-f8267276005c |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1656000410 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.chip_csr_rw.1656000410 |
| Directory | /workspace/5.chip_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/5.chip_same_csr_outstanding.467893762 |
| Short name | T405 |
| Test name | |
| Test status | |
| Simulation time | 33498700647 ps |
| CPU time | 4194.68 seconds |
| Started | Aug 12 06:47:32 PM PDT 24 |
| Finished | Aug 12 07:57:27 PM PDT 24 |
| Peak memory | 592904 kb |
| Host | smart-8958bc50-8dd4-4d90-be66-c0616352c17a |
| User | root |
| Command | /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +run_same_csr_outstanding +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=467893762 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c m_log /dev/null -cm_name 5.chip_same_csr_outstanding.467893762 |
| Directory | /workspace/5.chip_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/5.chip_tl_errors.76602323 |
| Short name | T2263 |
| Test name | |
| Test status | |
| Simulation time | 4068530984 ps |
| CPU time | 290.16 seconds |
| Started | Aug 12 06:47:29 PM PDT 24 |
| Finished | Aug 12 06:52:19 PM PDT 24 |
| Peak memory | 603284 kb |
| Host | smart-e47b1382-c647-454e-8abf-cea61086a6b2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76602323 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.chip_tl_errors.76602323 |
| Directory | /workspace/5.chip_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/5.xbar_access_same_device.2606278603 |
| Short name | T2470 |
| Test name | |
| Test status | |
| Simulation time | 366834171 ps |
| CPU time | 33.1 seconds |
| Started | Aug 12 06:47:25 PM PDT 24 |
| Finished | Aug 12 06:47:58 PM PDT 24 |
| Peak memory | 575708 kb |
| Host | smart-8b197288-715b-4056-9350-514e22e13329 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2606278603 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.xbar_access_same_device. 2606278603 |
| Directory | /workspace/5.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/5.xbar_access_same_device_slow_rsp.632180080 |
| Short name | T1640 |
| Test name | |
| Test status | |
| Simulation time | 44694389145 ps |
| CPU time | 732.46 seconds |
| Started | Aug 12 06:47:28 PM PDT 24 |
| Finished | Aug 12 06:59:41 PM PDT 24 |
| Peak memory | 576512 kb |
| Host | smart-4fa69928-28b8-49db-a9b7-1a2389859e11 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=632180080 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.xbar_access_same_de vice_slow_rsp.632180080 |
| Directory | /workspace/5.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/5.xbar_error_and_unmapped_addr.2137194288 |
| Short name | T2308 |
| Test name | |
| Test status | |
| Simulation time | 132704981 ps |
| CPU time | 16.37 seconds |
| Started | Aug 12 06:47:26 PM PDT 24 |
| Finished | Aug 12 06:47:42 PM PDT 24 |
| Peak memory | 575768 kb |
| Host | smart-0415a6f2-eb5e-45b7-95c5-2064a26c4dea |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2137194288 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.xbar_error_and_unmapped_addr .2137194288 |
| Directory | /workspace/5.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/5.xbar_error_random.2036210807 |
| Short name | T2662 |
| Test name | |
| Test status | |
| Simulation time | 307736975 ps |
| CPU time | 12.53 seconds |
| Started | Aug 12 06:47:30 PM PDT 24 |
| Finished | Aug 12 06:47:43 PM PDT 24 |
| Peak memory | 575492 kb |
| Host | smart-0cb4f38a-dc5a-46f3-900f-0a88ee468796 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2036210807 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.xbar_error_random.2036210807 |
| Directory | /workspace/5.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/5.xbar_random.2987456656 |
| Short name | T2628 |
| Test name | |
| Test status | |
| Simulation time | 246591550 ps |
| CPU time | 21.97 seconds |
| Started | Aug 12 06:47:28 PM PDT 24 |
| Finished | Aug 12 06:47:50 PM PDT 24 |
| Peak memory | 575548 kb |
| Host | smart-e263a6a6-996f-447f-be19-e319960ed11a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2987456656 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.xbar_random.2987456656 |
| Directory | /workspace/5.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/5.xbar_random_large_delays.2480689068 |
| Short name | T2301 |
| Test name | |
| Test status | |
| Simulation time | 72405172098 ps |
| CPU time | 695.02 seconds |
| Started | Aug 12 06:47:33 PM PDT 24 |
| Finished | Aug 12 06:59:08 PM PDT 24 |
| Peak memory | 575764 kb |
| Host | smart-18e762c8-c83c-4231-a9a6-37f87465b396 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2480689068 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.xbar_random_large_delays.2480689068 |
| Directory | /workspace/5.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/5.xbar_random_slow_rsp.1444091051 |
| Short name | T479 |
| Test name | |
| Test status | |
| Simulation time | 53394940128 ps |
| CPU time | 889.77 seconds |
| Started | Aug 12 06:47:25 PM PDT 24 |
| Finished | Aug 12 07:02:15 PM PDT 24 |
| Peak memory | 575780 kb |
| Host | smart-3b5eea77-9405-4dd2-a8fe-a2b0a687e99e |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1444091051 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.xbar_random_slow_rsp.1444091051 |
| Directory | /workspace/5.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/5.xbar_random_zero_delays.1612705767 |
| Short name | T1550 |
| Test name | |
| Test status | |
| Simulation time | 55342876 ps |
| CPU time | 7.63 seconds |
| Started | Aug 12 06:47:27 PM PDT 24 |
| Finished | Aug 12 06:47:34 PM PDT 24 |
| Peak memory | 574292 kb |
| Host | smart-004a24c6-5a53-421f-b0b8-365f38858f72 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1612705767 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.xbar_random_zero_dela ys.1612705767 |
| Directory | /workspace/5.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/5.xbar_same_source.158397811 |
| Short name | T561 |
| Test name | |
| Test status | |
| Simulation time | 313558530 ps |
| CPU time | 12.66 seconds |
| Started | Aug 12 06:47:32 PM PDT 24 |
| Finished | Aug 12 06:47:45 PM PDT 24 |
| Peak memory | 575660 kb |
| Host | smart-34a64277-274e-41a8-a300-3b68a5470653 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=158397811 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.xbar_same_source.158397811 |
| Directory | /workspace/5.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/5.xbar_smoke.854913036 |
| Short name | T685 |
| Test name | |
| Test status | |
| Simulation time | 220025763 ps |
| CPU time | 9.21 seconds |
| Started | Aug 12 06:47:23 PM PDT 24 |
| Finished | Aug 12 06:47:33 PM PDT 24 |
| Peak memory | 573572 kb |
| Host | smart-963f8638-2ed2-46ee-9579-9017a7444115 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=854913036 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.xbar_smoke.854913036 |
| Directory | /workspace/5.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/5.xbar_smoke_large_delays.2917057373 |
| Short name | T1685 |
| Test name | |
| Test status | |
| Simulation time | 5551955971 ps |
| CPU time | 54.68 seconds |
| Started | Aug 12 06:47:24 PM PDT 24 |
| Finished | Aug 12 06:48:19 PM PDT 24 |
| Peak memory | 573664 kb |
| Host | smart-813e0c91-64ce-483c-bc5e-f3ad30201fd4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2917057373 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.xbar_smoke_large_delays.2917057373 |
| Directory | /workspace/5.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/5.xbar_smoke_slow_rsp.2081892844 |
| Short name | T2609 |
| Test name | |
| Test status | |
| Simulation time | 4813832520 ps |
| CPU time | 83.71 seconds |
| Started | Aug 12 06:47:32 PM PDT 24 |
| Finished | Aug 12 06:48:56 PM PDT 24 |
| Peak memory | 573592 kb |
| Host | smart-439e05b5-1519-47b2-82a5-c9c604205a22 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2081892844 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.xbar_smoke_slow_rsp.2081892844 |
| Directory | /workspace/5.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/5.xbar_smoke_zero_delays.2953615894 |
| Short name | T736 |
| Test name | |
| Test status | |
| Simulation time | 42042770 ps |
| CPU time | 6.04 seconds |
| Started | Aug 12 06:47:27 PM PDT 24 |
| Finished | Aug 12 06:47:33 PM PDT 24 |
| Peak memory | 574292 kb |
| Host | smart-66331f27-2b08-469d-8350-ba792de1c35c |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2953615894 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.xbar_smoke_zero_delays .2953615894 |
| Directory | /workspace/5.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/5.xbar_stress_all.1633066788 |
| Short name | T2511 |
| Test name | |
| Test status | |
| Simulation time | 1541809362 ps |
| CPU time | 131.04 seconds |
| Started | Aug 12 06:47:25 PM PDT 24 |
| Finished | Aug 12 06:49:36 PM PDT 24 |
| Peak memory | 576488 kb |
| Host | smart-1c43971d-e470-42ba-aa41-140ac2de0237 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1633066788 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.xbar_stress_all.1633066788 |
| Directory | /workspace/5.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/5.xbar_stress_all_with_error.1010835979 |
| Short name | T1909 |
| Test name | |
| Test status | |
| Simulation time | 1803138460 ps |
| CPU time | 61.64 seconds |
| Started | Aug 12 06:47:28 PM PDT 24 |
| Finished | Aug 12 06:48:30 PM PDT 24 |
| Peak memory | 575672 kb |
| Host | smart-650205ef-2c0e-48e6-b954-8130294f1b12 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1010835979 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.xbar_stress_all_with_error.1010835979 |
| Directory | /workspace/5.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/5.xbar_stress_all_with_rand_reset.1384597068 |
| Short name | T2361 |
| Test name | |
| Test status | |
| Simulation time | 3823105149 ps |
| CPU time | 263.22 seconds |
| Started | Aug 12 06:47:31 PM PDT 24 |
| Finished | Aug 12 06:51:54 PM PDT 24 |
| Peak memory | 575784 kb |
| Host | smart-2b437728-f321-44da-aadc-dc48ca18935a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1384597068 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.xbar_stress_all_ with_rand_reset.1384597068 |
| Directory | /workspace/5.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/5.xbar_stress_all_with_reset_error.1928565339 |
| Short name | T1917 |
| Test name | |
| Test status | |
| Simulation time | 408358075 ps |
| CPU time | 77.92 seconds |
| Started | Aug 12 06:47:25 PM PDT 24 |
| Finished | Aug 12 06:48:43 PM PDT 24 |
| Peak memory | 576520 kb |
| Host | smart-2ad2f4e1-fbc6-4998-a5f1-6ea7ee9d38b1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1928565339 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.xbar_stress_all _with_reset_error.1928565339 |
| Directory | /workspace/5.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/5.xbar_unmapped_addr.1134874225 |
| Short name | T2127 |
| Test name | |
| Test status | |
| Simulation time | 280832942 ps |
| CPU time | 31.32 seconds |
| Started | Aug 12 06:47:27 PM PDT 24 |
| Finished | Aug 12 06:47:59 PM PDT 24 |
| Peak memory | 575712 kb |
| Host | smart-4a1faf06-af81-4988-b396-0ea7389e1afe |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1134874225 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.xbar_unmapped_addr.1134874225 |
| Directory | /workspace/5.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/50.xbar_access_same_device.1476255768 |
| Short name | T468 |
| Test name | |
| Test status | |
| Simulation time | 718365998 ps |
| CPU time | 60.71 seconds |
| Started | Aug 12 06:53:18 PM PDT 24 |
| Finished | Aug 12 06:54:18 PM PDT 24 |
| Peak memory | 575676 kb |
| Host | smart-a7eee54c-cbbf-4a90-a911-27bb8e294ddf |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1476255768 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 50.xbar_access_same_device .1476255768 |
| Directory | /workspace/50.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/50.xbar_access_same_device_slow_rsp.679379038 |
| Short name | T2406 |
| Test name | |
| Test status | |
| Simulation time | 87472307231 ps |
| CPU time | 1570.71 seconds |
| Started | Aug 12 06:53:16 PM PDT 24 |
| Finished | Aug 12 07:19:27 PM PDT 24 |
| Peak memory | 575828 kb |
| Host | smart-6554255c-428f-4434-a1a5-7cc7a88f1027 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=679379038 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 50.xbar_access_same_d evice_slow_rsp.679379038 |
| Directory | /workspace/50.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/50.xbar_error_and_unmapped_addr.1194648726 |
| Short name | T1593 |
| Test name | |
| Test status | |
| Simulation time | 1263742726 ps |
| CPU time | 48.53 seconds |
| Started | Aug 12 06:53:16 PM PDT 24 |
| Finished | Aug 12 06:54:05 PM PDT 24 |
| Peak memory | 575660 kb |
| Host | smart-584019fb-5f3c-4a2a-9dda-e3e18c4b386f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1194648726 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 50.xbar_error_and_unmapped_add r.1194648726 |
| Directory | /workspace/50.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/50.xbar_error_random.3746628570 |
| Short name | T1663 |
| Test name | |
| Test status | |
| Simulation time | 1296815619 ps |
| CPU time | 40.05 seconds |
| Started | Aug 12 06:53:14 PM PDT 24 |
| Finished | Aug 12 06:53:54 PM PDT 24 |
| Peak memory | 575700 kb |
| Host | smart-b3161583-7a8f-4a3f-bf92-9f5ef92ddc1b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3746628570 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 50.xbar_error_random.3746628570 |
| Directory | /workspace/50.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/50.xbar_random.4095990454 |
| Short name | T2611 |
| Test name | |
| Test status | |
| Simulation time | 1247571495 ps |
| CPU time | 49.01 seconds |
| Started | Aug 12 06:53:16 PM PDT 24 |
| Finished | Aug 12 06:54:05 PM PDT 24 |
| Peak memory | 575540 kb |
| Host | smart-18a62d05-c7d6-4775-bde1-1fed676cd553 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4095990454 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 50.xbar_random.4095990454 |
| Directory | /workspace/50.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/50.xbar_random_large_delays.4173528624 |
| Short name | T1885 |
| Test name | |
| Test status | |
| Simulation time | 90552248743 ps |
| CPU time | 982.09 seconds |
| Started | Aug 12 06:53:15 PM PDT 24 |
| Finished | Aug 12 07:09:37 PM PDT 24 |
| Peak memory | 575804 kb |
| Host | smart-4a8a6705-e5d6-4f52-9b1b-feb9eb536533 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4173528624 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 50.xbar_random_large_delays.4173528624 |
| Directory | /workspace/50.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/50.xbar_random_slow_rsp.1303680257 |
| Short name | T2480 |
| Test name | |
| Test status | |
| Simulation time | 25831696846 ps |
| CPU time | 420.37 seconds |
| Started | Aug 12 06:53:16 PM PDT 24 |
| Finished | Aug 12 07:00:17 PM PDT 24 |
| Peak memory | 575692 kb |
| Host | smart-b56a93b4-2d68-46b1-95c5-1c27a32ce4b7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1303680257 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 50.xbar_random_slow_rsp.1303680257 |
| Directory | /workspace/50.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/50.xbar_random_zero_delays.2304448843 |
| Short name | T2085 |
| Test name | |
| Test status | |
| Simulation time | 533619170 ps |
| CPU time | 41.91 seconds |
| Started | Aug 12 06:53:18 PM PDT 24 |
| Finished | Aug 12 06:54:00 PM PDT 24 |
| Peak memory | 575548 kb |
| Host | smart-f58635c3-4430-4b17-b818-de245781e687 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2304448843 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 50.xbar_random_zero_del ays.2304448843 |
| Directory | /workspace/50.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/50.xbar_same_source.2059103189 |
| Short name | T2531 |
| Test name | |
| Test status | |
| Simulation time | 540824599 ps |
| CPU time | 39.86 seconds |
| Started | Aug 12 06:53:16 PM PDT 24 |
| Finished | Aug 12 06:53:56 PM PDT 24 |
| Peak memory | 575604 kb |
| Host | smart-bbc8f353-116c-444d-8308-572d813afab0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2059103189 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 50.xbar_same_source.2059103189 |
| Directory | /workspace/50.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/50.xbar_smoke.1810395079 |
| Short name | T2940 |
| Test name | |
| Test status | |
| Simulation time | 162155201 ps |
| CPU time | 8.35 seconds |
| Started | Aug 12 06:53:17 PM PDT 24 |
| Finished | Aug 12 06:53:25 PM PDT 24 |
| Peak memory | 573544 kb |
| Host | smart-55a8c6ca-9d93-4fd3-9928-343c60c23d05 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1810395079 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 50.xbar_smoke.1810395079 |
| Directory | /workspace/50.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/50.xbar_smoke_large_delays.2843986030 |
| Short name | T1604 |
| Test name | |
| Test status | |
| Simulation time | 9530006897 ps |
| CPU time | 97.79 seconds |
| Started | Aug 12 06:53:18 PM PDT 24 |
| Finished | Aug 12 06:54:56 PM PDT 24 |
| Peak memory | 574344 kb |
| Host | smart-6f3bc195-5db7-4ad8-8187-13ad90d84342 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2843986030 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 50.xbar_smoke_large_delays.2843986030 |
| Directory | /workspace/50.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/50.xbar_smoke_slow_rsp.1744214274 |
| Short name | T1516 |
| Test name | |
| Test status | |
| Simulation time | 4471516405 ps |
| CPU time | 73.72 seconds |
| Started | Aug 12 06:53:17 PM PDT 24 |
| Finished | Aug 12 06:54:31 PM PDT 24 |
| Peak memory | 574348 kb |
| Host | smart-0635733b-c78f-4ddc-9753-13927d613cae |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1744214274 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 50.xbar_smoke_slow_rsp.1744214274 |
| Directory | /workspace/50.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/50.xbar_smoke_zero_delays.3252421419 |
| Short name | T2129 |
| Test name | |
| Test status | |
| Simulation time | 45697213 ps |
| CPU time | 6.05 seconds |
| Started | Aug 12 06:53:15 PM PDT 24 |
| Finished | Aug 12 06:53:22 PM PDT 24 |
| Peak memory | 574320 kb |
| Host | smart-ff64f7a9-2fc1-4bf7-be99-ce587a14223f |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3252421419 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 50.xbar_smoke_zero_delay s.3252421419 |
| Directory | /workspace/50.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/50.xbar_stress_all.2905773414 |
| Short name | T532 |
| Test name | |
| Test status | |
| Simulation time | 1879699507 ps |
| CPU time | 171.25 seconds |
| Started | Aug 12 06:53:14 PM PDT 24 |
| Finished | Aug 12 06:56:05 PM PDT 24 |
| Peak memory | 575756 kb |
| Host | smart-06bf439b-2c3f-47b6-9d1d-547b0f76144c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2905773414 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 50.xbar_stress_all.2905773414 |
| Directory | /workspace/50.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/50.xbar_stress_all_with_error.283714789 |
| Short name | T930 |
| Test name | |
| Test status | |
| Simulation time | 5417907943 ps |
| CPU time | 191.83 seconds |
| Started | Aug 12 06:53:14 PM PDT 24 |
| Finished | Aug 12 06:56:26 PM PDT 24 |
| Peak memory | 575676 kb |
| Host | smart-a0273c58-2aa7-404c-9a19-bab285824cc6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=283714789 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 50.xbar_stress_all_with_error.283714789 |
| Directory | /workspace/50.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/50.xbar_stress_all_with_rand_reset.1173414741 |
| Short name | T2717 |
| Test name | |
| Test status | |
| Simulation time | 4060968870 ps |
| CPU time | 411.48 seconds |
| Started | Aug 12 06:53:14 PM PDT 24 |
| Finished | Aug 12 07:00:05 PM PDT 24 |
| Peak memory | 576656 kb |
| Host | smart-7cee8db3-7770-4f05-a604-11f528750652 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1173414741 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 50.xbar_stress_all _with_rand_reset.1173414741 |
| Directory | /workspace/50.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/50.xbar_stress_all_with_reset_error.554494095 |
| Short name | T2273 |
| Test name | |
| Test status | |
| Simulation time | 1355514311 ps |
| CPU time | 63.9 seconds |
| Started | Aug 12 06:53:16 PM PDT 24 |
| Finished | Aug 12 06:54:20 PM PDT 24 |
| Peak memory | 576036 kb |
| Host | smart-2481bd5d-65bf-45cf-a0eb-96eaac50a46b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=554494095 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 50.xbar_stress_all _with_reset_error.554494095 |
| Directory | /workspace/50.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/50.xbar_unmapped_addr.1127426783 |
| Short name | T589 |
| Test name | |
| Test status | |
| Simulation time | 1108531806 ps |
| CPU time | 46.9 seconds |
| Started | Aug 12 06:53:15 PM PDT 24 |
| Finished | Aug 12 06:54:02 PM PDT 24 |
| Peak memory | 575716 kb |
| Host | smart-8f41ddea-7c21-4088-9d6c-69a16850716f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1127426783 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 50.xbar_unmapped_addr.1127426783 |
| Directory | /workspace/50.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/51.xbar_access_same_device.956568700 |
| Short name | T2009 |
| Test name | |
| Test status | |
| Simulation time | 727917681 ps |
| CPU time | 54.53 seconds |
| Started | Aug 12 06:53:25 PM PDT 24 |
| Finished | Aug 12 06:54:20 PM PDT 24 |
| Peak memory | 575524 kb |
| Host | smart-8b40cb89-3d0d-40cf-be2b-e9b49fa21c2a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=956568700 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 51.xbar_access_same_device. 956568700 |
| Directory | /workspace/51.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/51.xbar_access_same_device_slow_rsp.3738804206 |
| Short name | T2300 |
| Test name | |
| Test status | |
| Simulation time | 70985074303 ps |
| CPU time | 1258.75 seconds |
| Started | Aug 12 06:53:25 PM PDT 24 |
| Finished | Aug 12 07:14:24 PM PDT 24 |
| Peak memory | 575736 kb |
| Host | smart-0052410b-9050-4d44-9a80-2dac7e5fa8fe |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3738804206 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 51.xbar_access_same_ device_slow_rsp.3738804206 |
| Directory | /workspace/51.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/51.xbar_error_and_unmapped_addr.3474050776 |
| Short name | T2108 |
| Test name | |
| Test status | |
| Simulation time | 235367529 ps |
| CPU time | 26.48 seconds |
| Started | Aug 12 06:53:20 PM PDT 24 |
| Finished | Aug 12 06:53:47 PM PDT 24 |
| Peak memory | 575728 kb |
| Host | smart-37cbdf11-a8bc-4b23-99af-4e82aa5fa79a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3474050776 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 51.xbar_error_and_unmapped_add r.3474050776 |
| Directory | /workspace/51.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/51.xbar_error_random.1406908076 |
| Short name | T2153 |
| Test name | |
| Test status | |
| Simulation time | 285225376 ps |
| CPU time | 23.54 seconds |
| Started | Aug 12 06:53:21 PM PDT 24 |
| Finished | Aug 12 06:53:44 PM PDT 24 |
| Peak memory | 575612 kb |
| Host | smart-5d65d80d-2481-41a8-9066-4b1d30364f5a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1406908076 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 51.xbar_error_random.1406908076 |
| Directory | /workspace/51.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/51.xbar_random.3732066070 |
| Short name | T2719 |
| Test name | |
| Test status | |
| Simulation time | 134973055 ps |
| CPU time | 14.01 seconds |
| Started | Aug 12 06:53:17 PM PDT 24 |
| Finished | Aug 12 06:53:31 PM PDT 24 |
| Peak memory | 575720 kb |
| Host | smart-7e62446d-1938-4228-8b94-c7e2810b33ef |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3732066070 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 51.xbar_random.3732066070 |
| Directory | /workspace/51.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/51.xbar_random_large_delays.1729220004 |
| Short name | T2409 |
| Test name | |
| Test status | |
| Simulation time | 72892770241 ps |
| CPU time | 766 seconds |
| Started | Aug 12 06:53:19 PM PDT 24 |
| Finished | Aug 12 07:06:05 PM PDT 24 |
| Peak memory | 575764 kb |
| Host | smart-6ca6b85b-0cd8-4911-98b9-5a475ae4af66 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1729220004 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 51.xbar_random_large_delays.1729220004 |
| Directory | /workspace/51.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/51.xbar_random_slow_rsp.1402679740 |
| Short name | T1760 |
| Test name | |
| Test status | |
| Simulation time | 63426499411 ps |
| CPU time | 1155.07 seconds |
| Started | Aug 12 06:53:21 PM PDT 24 |
| Finished | Aug 12 07:12:37 PM PDT 24 |
| Peak memory | 575972 kb |
| Host | smart-944f0d08-21ed-41dc-a3fe-0bcf9b122138 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1402679740 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 51.xbar_random_slow_rsp.1402679740 |
| Directory | /workspace/51.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/51.xbar_random_zero_delays.431048698 |
| Short name | T2102 |
| Test name | |
| Test status | |
| Simulation time | 313198757 ps |
| CPU time | 28.28 seconds |
| Started | Aug 12 06:53:12 PM PDT 24 |
| Finished | Aug 12 06:53:41 PM PDT 24 |
| Peak memory | 575616 kb |
| Host | smart-d9aafb11-226f-43a8-849c-8ccc7e9f83f1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=431048698 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 51.xbar_random_zero_dela ys.431048698 |
| Directory | /workspace/51.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/51.xbar_same_source.3844444633 |
| Short name | T1943 |
| Test name | |
| Test status | |
| Simulation time | 257487406 ps |
| CPU time | 20.13 seconds |
| Started | Aug 12 06:53:20 PM PDT 24 |
| Finished | Aug 12 06:53:40 PM PDT 24 |
| Peak memory | 575624 kb |
| Host | smart-7cb30a8c-d781-4ce2-9c11-f75ddfd9d629 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3844444633 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 51.xbar_same_source.3844444633 |
| Directory | /workspace/51.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/51.xbar_smoke.873230386 |
| Short name | T2602 |
| Test name | |
| Test status | |
| Simulation time | 118675880 ps |
| CPU time | 6.63 seconds |
| Started | Aug 12 06:53:15 PM PDT 24 |
| Finished | Aug 12 06:53:22 PM PDT 24 |
| Peak memory | 574380 kb |
| Host | smart-c09e4e95-647b-4f22-90fb-60c6e6208d24 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=873230386 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 51.xbar_smoke.873230386 |
| Directory | /workspace/51.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/51.xbar_smoke_large_delays.2199365114 |
| Short name | T1606 |
| Test name | |
| Test status | |
| Simulation time | 4735366186 ps |
| CPU time | 51.35 seconds |
| Started | Aug 12 06:53:13 PM PDT 24 |
| Finished | Aug 12 06:54:04 PM PDT 24 |
| Peak memory | 573676 kb |
| Host | smart-9ec5a242-0ad5-4394-99fd-aa2724e74558 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2199365114 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 51.xbar_smoke_large_delays.2199365114 |
| Directory | /workspace/51.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/51.xbar_smoke_slow_rsp.3374718705 |
| Short name | T2898 |
| Test name | |
| Test status | |
| Simulation time | 4620799835 ps |
| CPU time | 75.37 seconds |
| Started | Aug 12 06:53:18 PM PDT 24 |
| Finished | Aug 12 06:54:33 PM PDT 24 |
| Peak memory | 573640 kb |
| Host | smart-bd6ee6ac-4382-4338-ab86-b89d74f33175 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3374718705 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 51.xbar_smoke_slow_rsp.3374718705 |
| Directory | /workspace/51.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/51.xbar_smoke_zero_delays.653918596 |
| Short name | T1482 |
| Test name | |
| Test status | |
| Simulation time | 53563294 ps |
| CPU time | 6.67 seconds |
| Started | Aug 12 06:53:18 PM PDT 24 |
| Finished | Aug 12 06:53:25 PM PDT 24 |
| Peak memory | 573616 kb |
| Host | smart-d69641ec-af08-4ed1-9593-a2b72724390d |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=653918596 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 51.xbar_smoke_zero_delays .653918596 |
| Directory | /workspace/51.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/51.xbar_stress_all.3897132302 |
| Short name | T505 |
| Test name | |
| Test status | |
| Simulation time | 1094813081 ps |
| CPU time | 79.73 seconds |
| Started | Aug 12 06:53:23 PM PDT 24 |
| Finished | Aug 12 06:54:42 PM PDT 24 |
| Peak memory | 575748 kb |
| Host | smart-33532b5d-4bba-4a4d-9496-6494fd71aea7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3897132302 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 51.xbar_stress_all.3897132302 |
| Directory | /workspace/51.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/51.xbar_stress_all_with_error.1488827612 |
| Short name | T1590 |
| Test name | |
| Test status | |
| Simulation time | 3206390784 ps |
| CPU time | 247.46 seconds |
| Started | Aug 12 06:53:22 PM PDT 24 |
| Finished | Aug 12 06:57:29 PM PDT 24 |
| Peak memory | 575904 kb |
| Host | smart-7b28943e-56f4-404b-8bdd-6d02bdca4343 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1488827612 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 51.xbar_stress_all_with_error.1488827612 |
| Directory | /workspace/51.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/51.xbar_stress_all_with_rand_reset.3714298256 |
| Short name | T2788 |
| Test name | |
| Test status | |
| Simulation time | 235039552 ps |
| CPU time | 88.8 seconds |
| Started | Aug 12 06:53:21 PM PDT 24 |
| Finished | Aug 12 06:54:50 PM PDT 24 |
| Peak memory | 575684 kb |
| Host | smart-0be9f0de-7571-441b-ac60-4ea8fa131764 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3714298256 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 51.xbar_stress_all _with_rand_reset.3714298256 |
| Directory | /workspace/51.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/51.xbar_stress_all_with_reset_error.1094165723 |
| Short name | T1907 |
| Test name | |
| Test status | |
| Simulation time | 191189216 ps |
| CPU time | 42.39 seconds |
| Started | Aug 12 06:53:20 PM PDT 24 |
| Finished | Aug 12 06:54:03 PM PDT 24 |
| Peak memory | 576116 kb |
| Host | smart-4b67e08e-3e39-4af6-af64-20d783352632 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1094165723 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 51.xbar_stress_al l_with_reset_error.1094165723 |
| Directory | /workspace/51.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/51.xbar_unmapped_addr.4265695628 |
| Short name | T2194 |
| Test name | |
| Test status | |
| Simulation time | 1308377476 ps |
| CPU time | 56.43 seconds |
| Started | Aug 12 06:53:25 PM PDT 24 |
| Finished | Aug 12 06:54:21 PM PDT 24 |
| Peak memory | 575644 kb |
| Host | smart-21621b1c-0e74-4614-83a6-36f8589c61ee |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4265695628 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 51.xbar_unmapped_addr.4265695628 |
| Directory | /workspace/51.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/52.xbar_access_same_device.1313369610 |
| Short name | T913 |
| Test name | |
| Test status | |
| Simulation time | 1385482070 ps |
| CPU time | 59.37 seconds |
| Started | Aug 12 06:53:30 PM PDT 24 |
| Finished | Aug 12 06:54:30 PM PDT 24 |
| Peak memory | 575632 kb |
| Host | smart-36607959-ee29-4e87-99ff-257b85133169 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1313369610 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 52.xbar_access_same_device .1313369610 |
| Directory | /workspace/52.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/52.xbar_access_same_device_slow_rsp.2214578938 |
| Short name | T2014 |
| Test name | |
| Test status | |
| Simulation time | 114081364344 ps |
| CPU time | 2253.08 seconds |
| Started | Aug 12 06:53:28 PM PDT 24 |
| Finished | Aug 12 07:31:02 PM PDT 24 |
| Peak memory | 575712 kb |
| Host | smart-1d899fe0-0ddf-4251-a873-ea33f726a36a |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2214578938 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 52.xbar_access_same_ device_slow_rsp.2214578938 |
| Directory | /workspace/52.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/52.xbar_error_and_unmapped_addr.2023826722 |
| Short name | T2454 |
| Test name | |
| Test status | |
| Simulation time | 119787865 ps |
| CPU time | 15.23 seconds |
| Started | Aug 12 06:53:28 PM PDT 24 |
| Finished | Aug 12 06:53:44 PM PDT 24 |
| Peak memory | 575752 kb |
| Host | smart-e9bbc5c9-c028-458d-9f84-4406ae0853a4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2023826722 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 52.xbar_error_and_unmapped_add r.2023826722 |
| Directory | /workspace/52.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/52.xbar_error_random.851518845 |
| Short name | T2824 |
| Test name | |
| Test status | |
| Simulation time | 724381590 ps |
| CPU time | 24.63 seconds |
| Started | Aug 12 06:53:29 PM PDT 24 |
| Finished | Aug 12 06:53:54 PM PDT 24 |
| Peak memory | 575640 kb |
| Host | smart-7ceaf65a-bf33-4365-9d03-64df2cd68b80 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=851518845 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 52.xbar_error_random.851518845 |
| Directory | /workspace/52.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/52.xbar_random.2314548306 |
| Short name | T2551 |
| Test name | |
| Test status | |
| Simulation time | 1923768820 ps |
| CPU time | 69.42 seconds |
| Started | Aug 12 06:53:26 PM PDT 24 |
| Finished | Aug 12 06:54:35 PM PDT 24 |
| Peak memory | 575728 kb |
| Host | smart-dc587fae-8a6a-436e-bbb9-8c236fada49e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2314548306 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 52.xbar_random.2314548306 |
| Directory | /workspace/52.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/52.xbar_random_large_delays.2947842731 |
| Short name | T1839 |
| Test name | |
| Test status | |
| Simulation time | 32109282094 ps |
| CPU time | 335.87 seconds |
| Started | Aug 12 06:53:29 PM PDT 24 |
| Finished | Aug 12 06:59:05 PM PDT 24 |
| Peak memory | 575704 kb |
| Host | smart-4eea3499-5385-4089-8572-6a231f93c409 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2947842731 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 52.xbar_random_large_delays.2947842731 |
| Directory | /workspace/52.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/52.xbar_random_slow_rsp.1591068417 |
| Short name | T2652 |
| Test name | |
| Test status | |
| Simulation time | 64774582059 ps |
| CPU time | 1215.2 seconds |
| Started | Aug 12 06:53:30 PM PDT 24 |
| Finished | Aug 12 07:13:45 PM PDT 24 |
| Peak memory | 575840 kb |
| Host | smart-1db6a700-f2d2-40d9-8d14-23a61dc6fe16 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1591068417 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 52.xbar_random_slow_rsp.1591068417 |
| Directory | /workspace/52.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/52.xbar_random_zero_delays.2838615159 |
| Short name | T2238 |
| Test name | |
| Test status | |
| Simulation time | 160513916 ps |
| CPU time | 16.84 seconds |
| Started | Aug 12 06:53:29 PM PDT 24 |
| Finished | Aug 12 06:53:46 PM PDT 24 |
| Peak memory | 575684 kb |
| Host | smart-ccd3d542-69e2-45ce-b241-b5c5e366cf0a |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2838615159 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 52.xbar_random_zero_del ays.2838615159 |
| Directory | /workspace/52.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/52.xbar_same_source.2648690134 |
| Short name | T2375 |
| Test name | |
| Test status | |
| Simulation time | 385176955 ps |
| CPU time | 13.4 seconds |
| Started | Aug 12 06:53:30 PM PDT 24 |
| Finished | Aug 12 06:53:43 PM PDT 24 |
| Peak memory | 575668 kb |
| Host | smart-cbb15869-da45-451d-907a-e534d879d928 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2648690134 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 52.xbar_same_source.2648690134 |
| Directory | /workspace/52.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/52.xbar_smoke.3824539744 |
| Short name | T2735 |
| Test name | |
| Test status | |
| Simulation time | 236693164 ps |
| CPU time | 9.36 seconds |
| Started | Aug 12 06:53:23 PM PDT 24 |
| Finished | Aug 12 06:53:32 PM PDT 24 |
| Peak memory | 573648 kb |
| Host | smart-c41dbb4d-18be-466c-895c-6ffcc75fa69d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3824539744 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 52.xbar_smoke.3824539744 |
| Directory | /workspace/52.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/52.xbar_smoke_large_delays.2572804713 |
| Short name | T1733 |
| Test name | |
| Test status | |
| Simulation time | 8644143377 ps |
| CPU time | 93.06 seconds |
| Started | Aug 12 06:53:20 PM PDT 24 |
| Finished | Aug 12 06:54:53 PM PDT 24 |
| Peak memory | 573684 kb |
| Host | smart-64e21443-038a-43a3-88b3-a9821457e192 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2572804713 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 52.xbar_smoke_large_delays.2572804713 |
| Directory | /workspace/52.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/52.xbar_smoke_slow_rsp.3422662372 |
| Short name | T1465 |
| Test name | |
| Test status | |
| Simulation time | 2398087430 ps |
| CPU time | 41.86 seconds |
| Started | Aug 12 06:53:23 PM PDT 24 |
| Finished | Aug 12 06:54:05 PM PDT 24 |
| Peak memory | 573600 kb |
| Host | smart-ec2e6aaf-5dbc-40e4-b298-9f41ef35e3cf |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3422662372 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 52.xbar_smoke_slow_rsp.3422662372 |
| Directory | /workspace/52.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/52.xbar_smoke_zero_delays.3046480077 |
| Short name | T1466 |
| Test name | |
| Test status | |
| Simulation time | 38148830 ps |
| CPU time | 6.08 seconds |
| Started | Aug 12 06:53:23 PM PDT 24 |
| Finished | Aug 12 06:53:29 PM PDT 24 |
| Peak memory | 573536 kb |
| Host | smart-014f31e3-01d1-41b9-ab21-f19e3cb265d2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3046480077 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 52.xbar_smoke_zero_delay s.3046480077 |
| Directory | /workspace/52.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/52.xbar_stress_all.3954141518 |
| Short name | T2180 |
| Test name | |
| Test status | |
| Simulation time | 101019212 ps |
| CPU time | 10.25 seconds |
| Started | Aug 12 06:53:28 PM PDT 24 |
| Finished | Aug 12 06:53:38 PM PDT 24 |
| Peak memory | 575556 kb |
| Host | smart-e87cf828-595d-4cc3-8c97-c237e55306ad |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3954141518 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 52.xbar_stress_all.3954141518 |
| Directory | /workspace/52.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/52.xbar_stress_all_with_error.3694812081 |
| Short name | T2110 |
| Test name | |
| Test status | |
| Simulation time | 1319656025 ps |
| CPU time | 83.53 seconds |
| Started | Aug 12 06:53:28 PM PDT 24 |
| Finished | Aug 12 06:54:52 PM PDT 24 |
| Peak memory | 575844 kb |
| Host | smart-79549b6e-09a9-4298-bc2b-8a4a3b511f73 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3694812081 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 52.xbar_stress_all_with_error.3694812081 |
| Directory | /workspace/52.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/52.xbar_stress_all_with_rand_reset.1880510447 |
| Short name | T954 |
| Test name | |
| Test status | |
| Simulation time | 4781554238 ps |
| CPU time | 303.88 seconds |
| Started | Aug 12 06:53:31 PM PDT 24 |
| Finished | Aug 12 06:58:35 PM PDT 24 |
| Peak memory | 575788 kb |
| Host | smart-9ff4fb1b-ffa9-425e-9fe6-2398ed482b36 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1880510447 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 52.xbar_stress_all _with_rand_reset.1880510447 |
| Directory | /workspace/52.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/52.xbar_stress_all_with_reset_error.4271375581 |
| Short name | T1538 |
| Test name | |
| Test status | |
| Simulation time | 155170704 ps |
| CPU time | 52 seconds |
| Started | Aug 12 06:53:29 PM PDT 24 |
| Finished | Aug 12 06:54:21 PM PDT 24 |
| Peak memory | 576328 kb |
| Host | smart-8f4bec6a-591e-455c-8f9f-03c332df2c15 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4271375581 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 52.xbar_stress_al l_with_reset_error.4271375581 |
| Directory | /workspace/52.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/52.xbar_unmapped_addr.1967577651 |
| Short name | T726 |
| Test name | |
| Test status | |
| Simulation time | 1470072617 ps |
| CPU time | 57.77 seconds |
| Started | Aug 12 06:53:29 PM PDT 24 |
| Finished | Aug 12 06:54:27 PM PDT 24 |
| Peak memory | 575716 kb |
| Host | smart-69387862-3cd1-4254-81b3-593171b40d73 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1967577651 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 52.xbar_unmapped_addr.1967577651 |
| Directory | /workspace/52.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/53.xbar_access_same_device.2369491098 |
| Short name | T489 |
| Test name | |
| Test status | |
| Simulation time | 473202661 ps |
| CPU time | 30.06 seconds |
| Started | Aug 12 06:53:37 PM PDT 24 |
| Finished | Aug 12 06:54:07 PM PDT 24 |
| Peak memory | 575596 kb |
| Host | smart-f9096f81-6e2c-4f77-a11e-a753052dae36 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2369491098 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 53.xbar_access_same_device .2369491098 |
| Directory | /workspace/53.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/53.xbar_access_same_device_slow_rsp.985282045 |
| Short name | T1693 |
| Test name | |
| Test status | |
| Simulation time | 47929630883 ps |
| CPU time | 862.99 seconds |
| Started | Aug 12 06:53:38 PM PDT 24 |
| Finished | Aug 12 07:08:01 PM PDT 24 |
| Peak memory | 575864 kb |
| Host | smart-b9c4d372-3886-47a7-93e1-e908fe8cc578 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=985282045 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 53.xbar_access_same_d evice_slow_rsp.985282045 |
| Directory | /workspace/53.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/53.xbar_error_and_unmapped_addr.3512999803 |
| Short name | T1758 |
| Test name | |
| Test status | |
| Simulation time | 277932107 ps |
| CPU time | 29.09 seconds |
| Started | Aug 12 06:53:41 PM PDT 24 |
| Finished | Aug 12 06:54:10 PM PDT 24 |
| Peak memory | 575540 kb |
| Host | smart-0a87e896-6ebe-4e50-9e14-be076264e986 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3512999803 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 53.xbar_error_and_unmapped_add r.3512999803 |
| Directory | /workspace/53.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/53.xbar_error_random.4280479907 |
| Short name | T2891 |
| Test name | |
| Test status | |
| Simulation time | 312831263 ps |
| CPU time | 13.95 seconds |
| Started | Aug 12 06:53:37 PM PDT 24 |
| Finished | Aug 12 06:53:51 PM PDT 24 |
| Peak memory | 575504 kb |
| Host | smart-4beaed4e-5ee1-4700-a5cd-f7221fc38897 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4280479907 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 53.xbar_error_random.4280479907 |
| Directory | /workspace/53.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/53.xbar_random.52573453 |
| Short name | T2554 |
| Test name | |
| Test status | |
| Simulation time | 2406656565 ps |
| CPU time | 93.72 seconds |
| Started | Aug 12 06:53:41 PM PDT 24 |
| Finished | Aug 12 06:55:15 PM PDT 24 |
| Peak memory | 575696 kb |
| Host | smart-3e32df70-13e7-4232-93dc-1f9f9ec04274 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=52573453 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 53.xbar_random.52573453 |
| Directory | /workspace/53.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/53.xbar_random_large_delays.988961122 |
| Short name | T614 |
| Test name | |
| Test status | |
| Simulation time | 7973876324 ps |
| CPU time | 87.65 seconds |
| Started | Aug 12 06:53:42 PM PDT 24 |
| Finished | Aug 12 06:55:10 PM PDT 24 |
| Peak memory | 574376 kb |
| Host | smart-f0546449-00c1-4cf3-883b-b7a9de90bbc7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=988961122 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 53.xbar_random_large_delays.988961122 |
| Directory | /workspace/53.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/53.xbar_random_slow_rsp.1212182301 |
| Short name | T1710 |
| Test name | |
| Test status | |
| Simulation time | 27171864310 ps |
| CPU time | 467.49 seconds |
| Started | Aug 12 06:53:38 PM PDT 24 |
| Finished | Aug 12 07:01:26 PM PDT 24 |
| Peak memory | 575832 kb |
| Host | smart-9ad69e7f-7b43-4158-8c19-606d15afada0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1212182301 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 53.xbar_random_slow_rsp.1212182301 |
| Directory | /workspace/53.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/53.xbar_random_zero_delays.309102711 |
| Short name | T2646 |
| Test name | |
| Test status | |
| Simulation time | 580932970 ps |
| CPU time | 46.9 seconds |
| Started | Aug 12 06:53:39 PM PDT 24 |
| Finished | Aug 12 06:54:26 PM PDT 24 |
| Peak memory | 575732 kb |
| Host | smart-e329e634-6474-4503-96ab-e4731921acaf |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=309102711 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 53.xbar_random_zero_dela ys.309102711 |
| Directory | /workspace/53.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/53.xbar_same_source.80209333 |
| Short name | T538 |
| Test name | |
| Test status | |
| Simulation time | 1906050614 ps |
| CPU time | 57.17 seconds |
| Started | Aug 12 06:53:41 PM PDT 24 |
| Finished | Aug 12 06:54:39 PM PDT 24 |
| Peak memory | 575676 kb |
| Host | smart-1327445e-4602-4556-94db-cd7c61175b27 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=80209333 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 53.xbar_same_source.80209333 |
| Directory | /workspace/53.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/53.xbar_smoke.3815571068 |
| Short name | T1453 |
| Test name | |
| Test status | |
| Simulation time | 49663153 ps |
| CPU time | 6.75 seconds |
| Started | Aug 12 06:53:30 PM PDT 24 |
| Finished | Aug 12 06:53:37 PM PDT 24 |
| Peak memory | 574232 kb |
| Host | smart-60a5a580-f22f-47d4-9380-5bf1a71fe629 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3815571068 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 53.xbar_smoke.3815571068 |
| Directory | /workspace/53.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/53.xbar_smoke_large_delays.1149453646 |
| Short name | T2205 |
| Test name | |
| Test status | |
| Simulation time | 8971409194 ps |
| CPU time | 94.55 seconds |
| Started | Aug 12 06:53:30 PM PDT 24 |
| Finished | Aug 12 06:55:05 PM PDT 24 |
| Peak memory | 573748 kb |
| Host | smart-9e1be662-2b65-4321-8371-e55d2f0229b8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1149453646 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 53.xbar_smoke_large_delays.1149453646 |
| Directory | /workspace/53.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/53.xbar_smoke_slow_rsp.2213849414 |
| Short name | T2269 |
| Test name | |
| Test status | |
| Simulation time | 4328167887 ps |
| CPU time | 74.34 seconds |
| Started | Aug 12 06:53:28 PM PDT 24 |
| Finished | Aug 12 06:54:43 PM PDT 24 |
| Peak memory | 573640 kb |
| Host | smart-3d949e5d-bea6-4e1b-a456-504c97bd0387 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2213849414 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 53.xbar_smoke_slow_rsp.2213849414 |
| Directory | /workspace/53.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/53.xbar_smoke_zero_delays.996965975 |
| Short name | T1587 |
| Test name | |
| Test status | |
| Simulation time | 39636918 ps |
| CPU time | 5.74 seconds |
| Started | Aug 12 06:53:30 PM PDT 24 |
| Finished | Aug 12 06:53:36 PM PDT 24 |
| Peak memory | 573568 kb |
| Host | smart-aed790e9-9254-4dc3-89d3-4412b9913d4b |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=996965975 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 53.xbar_smoke_zero_delays .996965975 |
| Directory | /workspace/53.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/53.xbar_stress_all.3102475183 |
| Short name | T482 |
| Test name | |
| Test status | |
| Simulation time | 9507753440 ps |
| CPU time | 367.45 seconds |
| Started | Aug 12 06:53:41 PM PDT 24 |
| Finished | Aug 12 06:59:49 PM PDT 24 |
| Peak memory | 575788 kb |
| Host | smart-be8349fe-3e5a-4bc6-a1db-e6a4915edef6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3102475183 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 53.xbar_stress_all.3102475183 |
| Directory | /workspace/53.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/53.xbar_stress_all_with_error.2461201947 |
| Short name | T915 |
| Test name | |
| Test status | |
| Simulation time | 8225010268 ps |
| CPU time | 282.85 seconds |
| Started | Aug 12 06:53:41 PM PDT 24 |
| Finished | Aug 12 06:58:24 PM PDT 24 |
| Peak memory | 575848 kb |
| Host | smart-9ed00e2c-8afa-4c6a-9be4-7bde78645b3b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2461201947 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 53.xbar_stress_all_with_error.2461201947 |
| Directory | /workspace/53.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/53.xbar_stress_all_with_rand_reset.120113342 |
| Short name | T2224 |
| Test name | |
| Test status | |
| Simulation time | 63922786 ps |
| CPU time | 50.3 seconds |
| Started | Aug 12 06:53:37 PM PDT 24 |
| Finished | Aug 12 06:54:27 PM PDT 24 |
| Peak memory | 576144 kb |
| Host | smart-45d7a788-6334-4c3d-8ccf-bc6460b928ac |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=120113342 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_res et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 53.xbar_stress_all_ with_rand_reset.120113342 |
| Directory | /workspace/53.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/53.xbar_stress_all_with_reset_error.352759718 |
| Short name | T1511 |
| Test name | |
| Test status | |
| Simulation time | 99525828 ps |
| CPU time | 23.84 seconds |
| Started | Aug 12 06:53:37 PM PDT 24 |
| Finished | Aug 12 06:54:01 PM PDT 24 |
| Peak memory | 575848 kb |
| Host | smart-eda161ce-341a-4abb-984f-8fe90692f2f6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=352759718 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 53.xbar_stress_all _with_reset_error.352759718 |
| Directory | /workspace/53.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/53.xbar_unmapped_addr.1824566732 |
| Short name | T2631 |
| Test name | |
| Test status | |
| Simulation time | 727968646 ps |
| CPU time | 33.16 seconds |
| Started | Aug 12 06:53:41 PM PDT 24 |
| Finished | Aug 12 06:54:15 PM PDT 24 |
| Peak memory | 575732 kb |
| Host | smart-8008a6da-8051-4214-aec0-7a8dd25f9d79 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1824566732 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 53.xbar_unmapped_addr.1824566732 |
| Directory | /workspace/53.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/54.xbar_access_same_device.3411572538 |
| Short name | T2064 |
| Test name | |
| Test status | |
| Simulation time | 244639548 ps |
| CPU time | 12.61 seconds |
| Started | Aug 12 06:53:47 PM PDT 24 |
| Finished | Aug 12 06:54:00 PM PDT 24 |
| Peak memory | 573560 kb |
| Host | smart-38af6f25-c87d-4d3e-b3ae-9980343bc25d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3411572538 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 54.xbar_access_same_device .3411572538 |
| Directory | /workspace/54.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/54.xbar_access_same_device_slow_rsp.1410866010 |
| Short name | T1811 |
| Test name | |
| Test status | |
| Simulation time | 123208229035 ps |
| CPU time | 2278.49 seconds |
| Started | Aug 12 06:53:47 PM PDT 24 |
| Finished | Aug 12 07:31:46 PM PDT 24 |
| Peak memory | 575820 kb |
| Host | smart-c2423f80-52f2-4b94-bc17-379dca0eb666 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1410866010 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 54.xbar_access_same_ device_slow_rsp.1410866010 |
| Directory | /workspace/54.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/54.xbar_error_and_unmapped_addr.215794856 |
| Short name | T2737 |
| Test name | |
| Test status | |
| Simulation time | 1049843257 ps |
| CPU time | 41.19 seconds |
| Started | Aug 12 06:53:50 PM PDT 24 |
| Finished | Aug 12 06:54:31 PM PDT 24 |
| Peak memory | 575716 kb |
| Host | smart-9b4c4fd7-0cff-44fa-86ba-d36a27fe4da1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=215794856 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 54.xbar_error_and_unmapped_addr .215794856 |
| Directory | /workspace/54.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/54.xbar_error_random.3048776617 |
| Short name | T2010 |
| Test name | |
| Test status | |
| Simulation time | 59013086 ps |
| CPU time | 7.52 seconds |
| Started | Aug 12 06:53:47 PM PDT 24 |
| Finished | Aug 12 06:53:54 PM PDT 24 |
| Peak memory | 575528 kb |
| Host | smart-608f7f6d-197a-4c3a-abc3-8bf27596589e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3048776617 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 54.xbar_error_random.3048776617 |
| Directory | /workspace/54.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/54.xbar_random.3025717616 |
| Short name | T1990 |
| Test name | |
| Test status | |
| Simulation time | 538439658 ps |
| CPU time | 40.52 seconds |
| Started | Aug 12 06:53:47 PM PDT 24 |
| Finished | Aug 12 06:54:28 PM PDT 24 |
| Peak memory | 575588 kb |
| Host | smart-4a742667-bd25-4fc5-bec9-e81a5da3bc7b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3025717616 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 54.xbar_random.3025717616 |
| Directory | /workspace/54.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/54.xbar_random_large_delays.667157124 |
| Short name | T666 |
| Test name | |
| Test status | |
| Simulation time | 104655293300 ps |
| CPU time | 1163.62 seconds |
| Started | Aug 12 06:53:48 PM PDT 24 |
| Finished | Aug 12 07:13:12 PM PDT 24 |
| Peak memory | 575664 kb |
| Host | smart-bdb50f27-4136-400e-a89b-9fbcd4d9725e |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=667157124 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 54.xbar_random_large_delays.667157124 |
| Directory | /workspace/54.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/54.xbar_random_slow_rsp.998871896 |
| Short name | T1853 |
| Test name | |
| Test status | |
| Simulation time | 14088176458 ps |
| CPU time | 238.25 seconds |
| Started | Aug 12 06:53:52 PM PDT 24 |
| Finished | Aug 12 06:57:50 PM PDT 24 |
| Peak memory | 575732 kb |
| Host | smart-4c942805-8851-4267-8db3-a9cbbdfad936 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=998871896 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 54.xbar_random_slow_rsp.998871896 |
| Directory | /workspace/54.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/54.xbar_random_zero_delays.298670096 |
| Short name | T632 |
| Test name | |
| Test status | |
| Simulation time | 447733702 ps |
| CPU time | 40.97 seconds |
| Started | Aug 12 06:53:52 PM PDT 24 |
| Finished | Aug 12 06:54:33 PM PDT 24 |
| Peak memory | 575728 kb |
| Host | smart-1d259a50-c5f5-4d49-bf6c-4c3b48cd104d |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=298670096 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 54.xbar_random_zero_dela ys.298670096 |
| Directory | /workspace/54.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/54.xbar_same_source.365867949 |
| Short name | T1730 |
| Test name | |
| Test status | |
| Simulation time | 529617798 ps |
| CPU time | 37.56 seconds |
| Started | Aug 12 06:53:46 PM PDT 24 |
| Finished | Aug 12 06:54:24 PM PDT 24 |
| Peak memory | 575660 kb |
| Host | smart-acfd38a6-fd7a-4561-8dae-fb4794af6801 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=365867949 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 54.xbar_same_source.365867949 |
| Directory | /workspace/54.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/54.xbar_smoke.463283038 |
| Short name | T1441 |
| Test name | |
| Test status | |
| Simulation time | 152610521 ps |
| CPU time | 7.56 seconds |
| Started | Aug 12 06:53:40 PM PDT 24 |
| Finished | Aug 12 06:53:48 PM PDT 24 |
| Peak memory | 574252 kb |
| Host | smart-8cf66da7-1eb7-445f-b3c8-95c3a12ea103 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=463283038 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 54.xbar_smoke.463283038 |
| Directory | /workspace/54.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/54.xbar_smoke_large_delays.700014038 |
| Short name | T1444 |
| Test name | |
| Test status | |
| Simulation time | 5346910431 ps |
| CPU time | 58.38 seconds |
| Started | Aug 12 06:53:48 PM PDT 24 |
| Finished | Aug 12 06:54:46 PM PDT 24 |
| Peak memory | 574364 kb |
| Host | smart-9d7452ec-8fd7-4fd4-bf64-a26a6ed7a6e5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=700014038 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 54.xbar_smoke_large_delays.700014038 |
| Directory | /workspace/54.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/54.xbar_smoke_slow_rsp.414484970 |
| Short name | T2222 |
| Test name | |
| Test status | |
| Simulation time | 5432752769 ps |
| CPU time | 94.07 seconds |
| Started | Aug 12 06:53:46 PM PDT 24 |
| Finished | Aug 12 06:55:21 PM PDT 24 |
| Peak memory | 573704 kb |
| Host | smart-33b34296-7276-49e3-bc35-0dbf72357b7c |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=414484970 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 54.xbar_smoke_slow_rsp.414484970 |
| Directory | /workspace/54.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/54.xbar_smoke_zero_delays.337101339 |
| Short name | T1586 |
| Test name | |
| Test status | |
| Simulation time | 38907252 ps |
| CPU time | 5.4 seconds |
| Started | Aug 12 06:53:48 PM PDT 24 |
| Finished | Aug 12 06:53:53 PM PDT 24 |
| Peak memory | 574344 kb |
| Host | smart-39792d06-bd4e-4c22-8a96-1e2defa72d11 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=337101339 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 54.xbar_smoke_zero_delays .337101339 |
| Directory | /workspace/54.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/54.xbar_stress_all.1461557293 |
| Short name | T627 |
| Test name | |
| Test status | |
| Simulation time | 11476638771 ps |
| CPU time | 401.54 seconds |
| Started | Aug 12 06:53:51 PM PDT 24 |
| Finished | Aug 12 07:00:32 PM PDT 24 |
| Peak memory | 576036 kb |
| Host | smart-2848c408-cd21-4e74-9e3d-9bf12075244b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1461557293 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 54.xbar_stress_all.1461557293 |
| Directory | /workspace/54.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/54.xbar_stress_all_with_error.998933022 |
| Short name | T1764 |
| Test name | |
| Test status | |
| Simulation time | 11607947789 ps |
| CPU time | 401.51 seconds |
| Started | Aug 12 06:53:47 PM PDT 24 |
| Finished | Aug 12 07:00:29 PM PDT 24 |
| Peak memory | 575896 kb |
| Host | smart-5c272113-57ff-4619-9d3b-5c9e5a921ae9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=998933022 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 54.xbar_stress_all_with_error.998933022 |
| Directory | /workspace/54.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/54.xbar_stress_all_with_rand_reset.3189876260 |
| Short name | T1601 |
| Test name | |
| Test status | |
| Simulation time | 205065409 ps |
| CPU time | 75.71 seconds |
| Started | Aug 12 06:53:49 PM PDT 24 |
| Finished | Aug 12 06:55:05 PM PDT 24 |
| Peak memory | 575820 kb |
| Host | smart-3f53aa70-a513-42fd-9749-ca8b6caa9ec1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3189876260 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 54.xbar_stress_all _with_rand_reset.3189876260 |
| Directory | /workspace/54.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/54.xbar_unmapped_addr.1578120374 |
| Short name | T491 |
| Test name | |
| Test status | |
| Simulation time | 1009860621 ps |
| CPU time | 40.86 seconds |
| Started | Aug 12 06:53:52 PM PDT 24 |
| Finished | Aug 12 06:54:33 PM PDT 24 |
| Peak memory | 575584 kb |
| Host | smart-b4398de7-e15e-4996-a013-0319fec7e4f3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1578120374 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 54.xbar_unmapped_addr.1578120374 |
| Directory | /workspace/54.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/55.xbar_access_same_device.1282450271 |
| Short name | T1724 |
| Test name | |
| Test status | |
| Simulation time | 1518126687 ps |
| CPU time | 59.09 seconds |
| Started | Aug 12 06:53:58 PM PDT 24 |
| Finished | Aug 12 06:54:57 PM PDT 24 |
| Peak memory | 575532 kb |
| Host | smart-b3eef7c1-8af4-4887-a428-76e5a2cd9d2b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1282450271 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 55.xbar_access_same_device .1282450271 |
| Directory | /workspace/55.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/55.xbar_access_same_device_slow_rsp.312978635 |
| Short name | T2280 |
| Test name | |
| Test status | |
| Simulation time | 54976179338 ps |
| CPU time | 975.07 seconds |
| Started | Aug 12 06:53:59 PM PDT 24 |
| Finished | Aug 12 07:10:16 PM PDT 24 |
| Peak memory | 575620 kb |
| Host | smart-4383b84f-4985-4be3-b2ca-df90d14e0d8a |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=312978635 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 55.xbar_access_same_d evice_slow_rsp.312978635 |
| Directory | /workspace/55.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/55.xbar_error_and_unmapped_addr.23494628 |
| Short name | T1504 |
| Test name | |
| Test status | |
| Simulation time | 1099612578 ps |
| CPU time | 46.32 seconds |
| Started | Aug 12 06:53:58 PM PDT 24 |
| Finished | Aug 12 06:54:44 PM PDT 24 |
| Peak memory | 575772 kb |
| Host | smart-1f63fd6d-2de7-461f-a40f-80d7ebebf381 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23494628 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 55.xbar_error_and_unmapped_addr.23494628 |
| Directory | /workspace/55.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/55.xbar_error_random.1762030903 |
| Short name | T2234 |
| Test name | |
| Test status | |
| Simulation time | 521173815 ps |
| CPU time | 39.87 seconds |
| Started | Aug 12 06:53:57 PM PDT 24 |
| Finished | Aug 12 06:54:37 PM PDT 24 |
| Peak memory | 575472 kb |
| Host | smart-83b21b99-d257-4f14-b62c-2aad92030a29 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1762030903 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 55.xbar_error_random.1762030903 |
| Directory | /workspace/55.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/55.xbar_random.1514050513 |
| Short name | T1935 |
| Test name | |
| Test status | |
| Simulation time | 1610461595 ps |
| CPU time | 60.07 seconds |
| Started | Aug 12 06:53:58 PM PDT 24 |
| Finished | Aug 12 06:54:58 PM PDT 24 |
| Peak memory | 575572 kb |
| Host | smart-b6d45bfa-ba29-4808-a7af-d1c845f7d748 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1514050513 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 55.xbar_random.1514050513 |
| Directory | /workspace/55.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/55.xbar_random_large_delays.3942095136 |
| Short name | T1696 |
| Test name | |
| Test status | |
| Simulation time | 16781261494 ps |
| CPU time | 168.46 seconds |
| Started | Aug 12 06:53:59 PM PDT 24 |
| Finished | Aug 12 06:56:47 PM PDT 24 |
| Peak memory | 575612 kb |
| Host | smart-5a2ebfb4-9f1c-4f88-ade2-ba1beb9fbae2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3942095136 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 55.xbar_random_large_delays.3942095136 |
| Directory | /workspace/55.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/55.xbar_random_slow_rsp.756252415 |
| Short name | T2754 |
| Test name | |
| Test status | |
| Simulation time | 7459760913 ps |
| CPU time | 130.55 seconds |
| Started | Aug 12 06:53:58 PM PDT 24 |
| Finished | Aug 12 06:56:09 PM PDT 24 |
| Peak memory | 575768 kb |
| Host | smart-70d35deb-ba5f-4d6e-a4b8-16a173e2d0e2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=756252415 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 55.xbar_random_slow_rsp.756252415 |
| Directory | /workspace/55.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/55.xbar_random_zero_delays.641836534 |
| Short name | T2626 |
| Test name | |
| Test status | |
| Simulation time | 425941241 ps |
| CPU time | 38.61 seconds |
| Started | Aug 12 06:53:59 PM PDT 24 |
| Finished | Aug 12 06:54:37 PM PDT 24 |
| Peak memory | 575576 kb |
| Host | smart-b85d4c20-0af3-4dbd-b8d0-01a652590346 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=641836534 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 55.xbar_random_zero_dela ys.641836534 |
| Directory | /workspace/55.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/55.xbar_same_source.2378248125 |
| Short name | T506 |
| Test name | |
| Test status | |
| Simulation time | 1294745980 ps |
| CPU time | 41.4 seconds |
| Started | Aug 12 06:53:58 PM PDT 24 |
| Finished | Aug 12 06:54:40 PM PDT 24 |
| Peak memory | 575592 kb |
| Host | smart-78104361-805e-4191-9e87-ebd3d4fff1dc |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2378248125 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 55.xbar_same_source.2378248125 |
| Directory | /workspace/55.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/55.xbar_smoke.2955229364 |
| Short name | T2800 |
| Test name | |
| Test status | |
| Simulation time | 235115932 ps |
| CPU time | 9.93 seconds |
| Started | Aug 12 06:53:58 PM PDT 24 |
| Finished | Aug 12 06:54:08 PM PDT 24 |
| Peak memory | 573552 kb |
| Host | smart-9cced254-01e1-4815-b21c-4f8d2603cbc9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2955229364 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 55.xbar_smoke.2955229364 |
| Directory | /workspace/55.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/55.xbar_smoke_large_delays.3554446637 |
| Short name | T1460 |
| Test name | |
| Test status | |
| Simulation time | 7273388629 ps |
| CPU time | 74.81 seconds |
| Started | Aug 12 06:53:58 PM PDT 24 |
| Finished | Aug 12 06:55:13 PM PDT 24 |
| Peak memory | 573684 kb |
| Host | smart-03e29d83-8901-4344-841e-64e7b21ba37e |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3554446637 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 55.xbar_smoke_large_delays.3554446637 |
| Directory | /workspace/55.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/55.xbar_smoke_slow_rsp.958381494 |
| Short name | T2809 |
| Test name | |
| Test status | |
| Simulation time | 5587378158 ps |
| CPU time | 92.19 seconds |
| Started | Aug 12 06:53:59 PM PDT 24 |
| Finished | Aug 12 06:55:31 PM PDT 24 |
| Peak memory | 573680 kb |
| Host | smart-4af8ab63-9b54-4cfb-8132-3bad77db3acd |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=958381494 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 55.xbar_smoke_slow_rsp.958381494 |
| Directory | /workspace/55.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/55.xbar_smoke_zero_delays.1178649983 |
| Short name | T2250 |
| Test name | |
| Test status | |
| Simulation time | 48855435 ps |
| CPU time | 6.22 seconds |
| Started | Aug 12 06:53:58 PM PDT 24 |
| Finished | Aug 12 06:54:04 PM PDT 24 |
| Peak memory | 573516 kb |
| Host | smart-23779d53-b85e-469c-88ed-a93ad7aa6122 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1178649983 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 55.xbar_smoke_zero_delay s.1178649983 |
| Directory | /workspace/55.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/55.xbar_stress_all.3085575511 |
| Short name | T515 |
| Test name | |
| Test status | |
| Simulation time | 4258841936 ps |
| CPU time | 321.3 seconds |
| Started | Aug 12 06:54:00 PM PDT 24 |
| Finished | Aug 12 06:59:22 PM PDT 24 |
| Peak memory | 576596 kb |
| Host | smart-b6c034ec-68b9-4840-be4d-c9a5a1d917c2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3085575511 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 55.xbar_stress_all.3085575511 |
| Directory | /workspace/55.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/55.xbar_stress_all_with_error.4009727003 |
| Short name | T2935 |
| Test name | |
| Test status | |
| Simulation time | 2395695877 ps |
| CPU time | 86.86 seconds |
| Started | Aug 12 06:54:12 PM PDT 24 |
| Finished | Aug 12 06:55:39 PM PDT 24 |
| Peak memory | 575664 kb |
| Host | smart-2ce7f67f-fd19-42b6-92f0-126720dc1ebb |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4009727003 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 55.xbar_stress_all_with_error.4009727003 |
| Directory | /workspace/55.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/55.xbar_stress_all_with_rand_reset.2400401941 |
| Short name | T2317 |
| Test name | |
| Test status | |
| Simulation time | 4885395754 ps |
| CPU time | 187.85 seconds |
| Started | Aug 12 06:54:11 PM PDT 24 |
| Finished | Aug 12 06:57:19 PM PDT 24 |
| Peak memory | 576592 kb |
| Host | smart-ac4f7589-a10c-4f4d-836f-4395a3fc9486 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2400401941 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 55.xbar_stress_all _with_rand_reset.2400401941 |
| Directory | /workspace/55.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/55.xbar_stress_all_with_reset_error.84178249 |
| Short name | T2810 |
| Test name | |
| Test status | |
| Simulation time | 516628999 ps |
| CPU time | 121.07 seconds |
| Started | Aug 12 06:54:10 PM PDT 24 |
| Finished | Aug 12 06:56:11 PM PDT 24 |
| Peak memory | 575652 kb |
| Host | smart-dceecb72-bdc2-46f6-a3b3-5858530dacd5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=84178249 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_res et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 55.xbar_stress_all_ with_reset_error.84178249 |
| Directory | /workspace/55.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/55.xbar_unmapped_addr.3078612434 |
| Short name | T1688 |
| Test name | |
| Test status | |
| Simulation time | 547458194 ps |
| CPU time | 27.09 seconds |
| Started | Aug 12 06:54:00 PM PDT 24 |
| Finished | Aug 12 06:54:28 PM PDT 24 |
| Peak memory | 575652 kb |
| Host | smart-1cae7fa9-64fe-46cc-8601-16d5104fb054 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3078612434 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 55.xbar_unmapped_addr.3078612434 |
| Directory | /workspace/55.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/56.xbar_access_same_device.2668798178 |
| Short name | T2015 |
| Test name | |
| Test status | |
| Simulation time | 268262095 ps |
| CPU time | 11.53 seconds |
| Started | Aug 12 06:54:10 PM PDT 24 |
| Finished | Aug 12 06:54:22 PM PDT 24 |
| Peak memory | 573652 kb |
| Host | smart-f603315f-c351-436f-8fe4-d116402b5cbd |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2668798178 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 56.xbar_access_same_device .2668798178 |
| Directory | /workspace/56.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/56.xbar_access_same_device_slow_rsp.3023867024 |
| Short name | T1777 |
| Test name | |
| Test status | |
| Simulation time | 26015260844 ps |
| CPU time | 443.25 seconds |
| Started | Aug 12 06:54:13 PM PDT 24 |
| Finished | Aug 12 07:01:36 PM PDT 24 |
| Peak memory | 575716 kb |
| Host | smart-956cb0c6-85a7-4041-9320-6c3931e425a1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3023867024 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 56.xbar_access_same_ device_slow_rsp.3023867024 |
| Directory | /workspace/56.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/56.xbar_error_and_unmapped_addr.3302817289 |
| Short name | T1859 |
| Test name | |
| Test status | |
| Simulation time | 1061992704 ps |
| CPU time | 44.03 seconds |
| Started | Aug 12 06:54:14 PM PDT 24 |
| Finished | Aug 12 06:54:58 PM PDT 24 |
| Peak memory | 575520 kb |
| Host | smart-33251ede-45d1-4ffd-894b-4113e5bf1ade |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3302817289 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 56.xbar_error_and_unmapped_add r.3302817289 |
| Directory | /workspace/56.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/56.xbar_error_random.4215543340 |
| Short name | T2641 |
| Test name | |
| Test status | |
| Simulation time | 562723653 ps |
| CPU time | 47.33 seconds |
| Started | Aug 12 06:54:13 PM PDT 24 |
| Finished | Aug 12 06:55:00 PM PDT 24 |
| Peak memory | 575648 kb |
| Host | smart-071c64d4-c6d1-465d-b923-03e7f0ec712b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4215543340 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 56.xbar_error_random.4215543340 |
| Directory | /workspace/56.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/56.xbar_random.2847820 |
| Short name | T441 |
| Test name | |
| Test status | |
| Simulation time | 1616779263 ps |
| CPU time | 55.12 seconds |
| Started | Aug 12 06:54:09 PM PDT 24 |
| Finished | Aug 12 06:55:04 PM PDT 24 |
| Peak memory | 575556 kb |
| Host | smart-97401b4b-297a-42cf-8a17-1e0e4274afd5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2847820 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 56.xbar_random.2847820 |
| Directory | /workspace/56.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/56.xbar_random_large_delays.1029913238 |
| Short name | T2414 |
| Test name | |
| Test status | |
| Simulation time | 93264538814 ps |
| CPU time | 950.74 seconds |
| Started | Aug 12 06:54:10 PM PDT 24 |
| Finished | Aug 12 07:10:01 PM PDT 24 |
| Peak memory | 575828 kb |
| Host | smart-b550517a-3f97-4f6b-8299-a40b7d869aa8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1029913238 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 56.xbar_random_large_delays.1029913238 |
| Directory | /workspace/56.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/56.xbar_random_slow_rsp.388729701 |
| Short name | T488 |
| Test name | |
| Test status | |
| Simulation time | 39029898554 ps |
| CPU time | 680.68 seconds |
| Started | Aug 12 06:54:09 PM PDT 24 |
| Finished | Aug 12 07:05:30 PM PDT 24 |
| Peak memory | 575636 kb |
| Host | smart-dcd656ff-6034-4367-80a6-d040b29f119c |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=388729701 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 56.xbar_random_slow_rsp.388729701 |
| Directory | /workspace/56.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/56.xbar_random_zero_delays.1860920773 |
| Short name | T601 |
| Test name | |
| Test status | |
| Simulation time | 618615477 ps |
| CPU time | 50.43 seconds |
| Started | Aug 12 06:54:10 PM PDT 24 |
| Finished | Aug 12 06:55:01 PM PDT 24 |
| Peak memory | 575588 kb |
| Host | smart-e8a0ab63-eaf5-4bc4-a279-f0ed0955e913 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1860920773 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 56.xbar_random_zero_del ays.1860920773 |
| Directory | /workspace/56.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/56.xbar_same_source.2031870624 |
| Short name | T2787 |
| Test name | |
| Test status | |
| Simulation time | 535012922 ps |
| CPU time | 35.98 seconds |
| Started | Aug 12 06:54:10 PM PDT 24 |
| Finished | Aug 12 06:54:47 PM PDT 24 |
| Peak memory | 575532 kb |
| Host | smart-1dcb751d-314e-4eb1-9d95-74a3c8d3bc16 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2031870624 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 56.xbar_same_source.2031870624 |
| Directory | /workspace/56.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/56.xbar_smoke.4043879786 |
| Short name | T1639 |
| Test name | |
| Test status | |
| Simulation time | 212386278 ps |
| CPU time | 9.13 seconds |
| Started | Aug 12 06:54:12 PM PDT 24 |
| Finished | Aug 12 06:54:22 PM PDT 24 |
| Peak memory | 574244 kb |
| Host | smart-5a89ad1d-7c56-424a-afcb-7c1cd1dabfc4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4043879786 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 56.xbar_smoke.4043879786 |
| Directory | /workspace/56.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/56.xbar_smoke_large_delays.311996063 |
| Short name | T1669 |
| Test name | |
| Test status | |
| Simulation time | 6227743348 ps |
| CPU time | 67.38 seconds |
| Started | Aug 12 06:54:11 PM PDT 24 |
| Finished | Aug 12 06:55:19 PM PDT 24 |
| Peak memory | 573656 kb |
| Host | smart-8fdcc402-1575-4fa6-ab9d-fc282e43ca2e |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=311996063 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 56.xbar_smoke_large_delays.311996063 |
| Directory | /workspace/56.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/56.xbar_smoke_slow_rsp.819163329 |
| Short name | T1521 |
| Test name | |
| Test status | |
| Simulation time | 5115786136 ps |
| CPU time | 86.35 seconds |
| Started | Aug 12 06:54:13 PM PDT 24 |
| Finished | Aug 12 06:55:40 PM PDT 24 |
| Peak memory | 573672 kb |
| Host | smart-f30f197e-f3d8-4f60-a576-a5cf5a57ee88 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=819163329 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 56.xbar_smoke_slow_rsp.819163329 |
| Directory | /workspace/56.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/56.xbar_smoke_zero_delays.3795330295 |
| Short name | T2715 |
| Test name | |
| Test status | |
| Simulation time | 58895389 ps |
| CPU time | 7.16 seconds |
| Started | Aug 12 06:54:09 PM PDT 24 |
| Finished | Aug 12 06:54:16 PM PDT 24 |
| Peak memory | 573556 kb |
| Host | smart-797ec590-f866-4ed2-82a6-225c9268bcce |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3795330295 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 56.xbar_smoke_zero_delay s.3795330295 |
| Directory | /workspace/56.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/56.xbar_stress_all.1789700457 |
| Short name | T2050 |
| Test name | |
| Test status | |
| Simulation time | 1411453804 ps |
| CPU time | 116.84 seconds |
| Started | Aug 12 06:54:10 PM PDT 24 |
| Finished | Aug 12 06:56:07 PM PDT 24 |
| Peak memory | 576420 kb |
| Host | smart-d8878e56-21fb-4b5b-be7b-e95377904c8e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1789700457 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 56.xbar_stress_all.1789700457 |
| Directory | /workspace/56.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/56.xbar_stress_all_with_error.2066295358 |
| Short name | T2130 |
| Test name | |
| Test status | |
| Simulation time | 3463726768 ps |
| CPU time | 135.19 seconds |
| Started | Aug 12 06:54:09 PM PDT 24 |
| Finished | Aug 12 06:56:24 PM PDT 24 |
| Peak memory | 575612 kb |
| Host | smart-8a1fe085-58e6-4ca7-abb4-516b5c6de0fd |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2066295358 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 56.xbar_stress_all_with_error.2066295358 |
| Directory | /workspace/56.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/56.xbar_stress_all_with_rand_reset.2896901318 |
| Short name | T1786 |
| Test name | |
| Test status | |
| Simulation time | 867456876 ps |
| CPU time | 253.69 seconds |
| Started | Aug 12 06:54:12 PM PDT 24 |
| Finished | Aug 12 06:58:26 PM PDT 24 |
| Peak memory | 575704 kb |
| Host | smart-1ba22049-6800-4572-ba40-404a73132251 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2896901318 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 56.xbar_stress_all _with_rand_reset.2896901318 |
| Directory | /workspace/56.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/56.xbar_stress_all_with_reset_error.2164813986 |
| Short name | T2045 |
| Test name | |
| Test status | |
| Simulation time | 566869845 ps |
| CPU time | 187.46 seconds |
| Started | Aug 12 06:54:13 PM PDT 24 |
| Finished | Aug 12 06:57:21 PM PDT 24 |
| Peak memory | 576524 kb |
| Host | smart-2868a7f9-3dee-4110-a43f-cf2a6ba6e853 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2164813986 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 56.xbar_stress_al l_with_reset_error.2164813986 |
| Directory | /workspace/56.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/56.xbar_unmapped_addr.2675037643 |
| Short name | T1934 |
| Test name | |
| Test status | |
| Simulation time | 24479415 ps |
| CPU time | 5.82 seconds |
| Started | Aug 12 06:54:13 PM PDT 24 |
| Finished | Aug 12 06:54:19 PM PDT 24 |
| Peak memory | 573624 kb |
| Host | smart-64fe364c-5eae-44a6-8f59-f0b91593b442 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2675037643 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 56.xbar_unmapped_addr.2675037643 |
| Directory | /workspace/56.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/57.xbar_access_same_device.2740333235 |
| Short name | T1650 |
| Test name | |
| Test status | |
| Simulation time | 1172294166 ps |
| CPU time | 90.35 seconds |
| Started | Aug 12 06:54:14 PM PDT 24 |
| Finished | Aug 12 06:55:44 PM PDT 24 |
| Peak memory | 575736 kb |
| Host | smart-4339eb2f-cff1-44e6-ba10-75e6fbc80571 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2740333235 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 57.xbar_access_same_device .2740333235 |
| Directory | /workspace/57.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/57.xbar_access_same_device_slow_rsp.2788428603 |
| Short name | T2282 |
| Test name | |
| Test status | |
| Simulation time | 109648088349 ps |
| CPU time | 1941.07 seconds |
| Started | Aug 12 06:54:22 PM PDT 24 |
| Finished | Aug 12 07:26:44 PM PDT 24 |
| Peak memory | 575724 kb |
| Host | smart-2e9caa14-b0c7-4856-aac7-cdc214785512 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2788428603 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 57.xbar_access_same_ device_slow_rsp.2788428603 |
| Directory | /workspace/57.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/57.xbar_error_and_unmapped_addr.3724640236 |
| Short name | T1479 |
| Test name | |
| Test status | |
| Simulation time | 1519814568 ps |
| CPU time | 59.16 seconds |
| Started | Aug 12 06:54:26 PM PDT 24 |
| Finished | Aug 12 06:55:25 PM PDT 24 |
| Peak memory | 575660 kb |
| Host | smart-06cff83b-9c0a-47f3-b8fe-2d22e8c80737 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3724640236 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 57.xbar_error_and_unmapped_add r.3724640236 |
| Directory | /workspace/57.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/57.xbar_error_random.293215504 |
| Short name | T1651 |
| Test name | |
| Test status | |
| Simulation time | 274719707 ps |
| CPU time | 24.96 seconds |
| Started | Aug 12 06:54:24 PM PDT 24 |
| Finished | Aug 12 06:54:49 PM PDT 24 |
| Peak memory | 575616 kb |
| Host | smart-295d4d92-998e-45fd-9901-1a20a24337e4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=293215504 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 57.xbar_error_random.293215504 |
| Directory | /workspace/57.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/57.xbar_random.1772235405 |
| Short name | T1533 |
| Test name | |
| Test status | |
| Simulation time | 1403897862 ps |
| CPU time | 57.28 seconds |
| Started | Aug 12 06:54:12 PM PDT 24 |
| Finished | Aug 12 06:55:09 PM PDT 24 |
| Peak memory | 575696 kb |
| Host | smart-2eb1221b-8499-4183-ae7d-99a86bbe487d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1772235405 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 57.xbar_random.1772235405 |
| Directory | /workspace/57.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/57.xbar_random_large_delays.1689335510 |
| Short name | T2347 |
| Test name | |
| Test status | |
| Simulation time | 51281432736 ps |
| CPU time | 547.02 seconds |
| Started | Aug 12 06:54:10 PM PDT 24 |
| Finished | Aug 12 07:03:17 PM PDT 24 |
| Peak memory | 575764 kb |
| Host | smart-f1d8d815-75ad-49b8-ac9b-66f2107daec7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1689335510 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 57.xbar_random_large_delays.1689335510 |
| Directory | /workspace/57.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/57.xbar_random_slow_rsp.2824908658 |
| Short name | T1728 |
| Test name | |
| Test status | |
| Simulation time | 37988220746 ps |
| CPU time | 621.19 seconds |
| Started | Aug 12 06:54:12 PM PDT 24 |
| Finished | Aug 12 07:04:34 PM PDT 24 |
| Peak memory | 575624 kb |
| Host | smart-82796f4d-7980-42c4-85d3-7d7ea9fcc61b |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2824908658 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 57.xbar_random_slow_rsp.2824908658 |
| Directory | /workspace/57.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/57.xbar_random_zero_delays.2600077328 |
| Short name | T629 |
| Test name | |
| Test status | |
| Simulation time | 380665228 ps |
| CPU time | 36.46 seconds |
| Started | Aug 12 06:54:09 PM PDT 24 |
| Finished | Aug 12 06:54:45 PM PDT 24 |
| Peak memory | 575660 kb |
| Host | smart-38e69c0e-3fca-4f99-88af-7b767fa07936 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2600077328 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 57.xbar_random_zero_del ays.2600077328 |
| Directory | /workspace/57.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/57.xbar_same_source.1692919103 |
| Short name | T719 |
| Test name | |
| Test status | |
| Simulation time | 872870908 ps |
| CPU time | 26.24 seconds |
| Started | Aug 12 06:54:23 PM PDT 24 |
| Finished | Aug 12 06:54:49 PM PDT 24 |
| Peak memory | 575664 kb |
| Host | smart-9999c9a7-275f-4226-b0b8-003f5a26e075 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1692919103 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 57.xbar_same_source.1692919103 |
| Directory | /workspace/57.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/57.xbar_smoke.2787013073 |
| Short name | T1873 |
| Test name | |
| Test status | |
| Simulation time | 201473116 ps |
| CPU time | 9.69 seconds |
| Started | Aug 12 06:54:13 PM PDT 24 |
| Finished | Aug 12 06:54:23 PM PDT 24 |
| Peak memory | 573524 kb |
| Host | smart-80c1c39a-cc22-400b-bd8b-80884b5cba3e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2787013073 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 57.xbar_smoke.2787013073 |
| Directory | /workspace/57.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/57.xbar_smoke_large_delays.1331868852 |
| Short name | T2208 |
| Test name | |
| Test status | |
| Simulation time | 7924780591 ps |
| CPU time | 84.22 seconds |
| Started | Aug 12 06:54:11 PM PDT 24 |
| Finished | Aug 12 06:55:35 PM PDT 24 |
| Peak memory | 573664 kb |
| Host | smart-8f7a30db-a25a-4a52-80c9-af7df95d3d5a |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1331868852 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 57.xbar_smoke_large_delays.1331868852 |
| Directory | /workspace/57.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/57.xbar_smoke_slow_rsp.4139069289 |
| Short name | T2464 |
| Test name | |
| Test status | |
| Simulation time | 4380143119 ps |
| CPU time | 74.46 seconds |
| Started | Aug 12 06:54:09 PM PDT 24 |
| Finished | Aug 12 06:55:24 PM PDT 24 |
| Peak memory | 573704 kb |
| Host | smart-afb0af5c-c962-4679-96c0-50b0d42348a4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4139069289 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 57.xbar_smoke_slow_rsp.4139069289 |
| Directory | /workspace/57.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/57.xbar_smoke_zero_delays.1104978454 |
| Short name | T1666 |
| Test name | |
| Test status | |
| Simulation time | 45831648 ps |
| CPU time | 6.34 seconds |
| Started | Aug 12 06:54:12 PM PDT 24 |
| Finished | Aug 12 06:54:19 PM PDT 24 |
| Peak memory | 573560 kb |
| Host | smart-e5fa3545-9ade-4372-b08c-77b842314b26 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1104978454 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 57.xbar_smoke_zero_delay s.1104978454 |
| Directory | /workspace/57.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/57.xbar_stress_all.3307882489 |
| Short name | T1831 |
| Test name | |
| Test status | |
| Simulation time | 3618653262 ps |
| CPU time | 352.33 seconds |
| Started | Aug 12 06:54:23 PM PDT 24 |
| Finished | Aug 12 07:00:16 PM PDT 24 |
| Peak memory | 576568 kb |
| Host | smart-5f09d35d-da76-4236-b5c9-61585fb64f66 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3307882489 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 57.xbar_stress_all.3307882489 |
| Directory | /workspace/57.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/57.xbar_stress_all_with_error.698687467 |
| Short name | T1791 |
| Test name | |
| Test status | |
| Simulation time | 9144852152 ps |
| CPU time | 321.66 seconds |
| Started | Aug 12 06:54:23 PM PDT 24 |
| Finished | Aug 12 06:59:45 PM PDT 24 |
| Peak memory | 576408 kb |
| Host | smart-1d589592-e5c1-47dd-acba-e73ba04cdd1e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=698687467 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 57.xbar_stress_all_with_error.698687467 |
| Directory | /workspace/57.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/57.xbar_stress_all_with_rand_reset.506635785 |
| Short name | T542 |
| Test name | |
| Test status | |
| Simulation time | 5730686977 ps |
| CPU time | 316.39 seconds |
| Started | Aug 12 06:54:23 PM PDT 24 |
| Finished | Aug 12 06:59:40 PM PDT 24 |
| Peak memory | 575760 kb |
| Host | smart-7183ea0a-3962-4938-9d0e-74dfce11d4a0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=506635785 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_res et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 57.xbar_stress_all_ with_rand_reset.506635785 |
| Directory | /workspace/57.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/57.xbar_stress_all_with_reset_error.1741749639 |
| Short name | T1765 |
| Test name | |
| Test status | |
| Simulation time | 165499242 ps |
| CPU time | 59.33 seconds |
| Started | Aug 12 06:54:24 PM PDT 24 |
| Finished | Aug 12 06:55:23 PM PDT 24 |
| Peak memory | 575748 kb |
| Host | smart-0e800bc2-ed26-4017-98cd-3de79efa1b26 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1741749639 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 57.xbar_stress_al l_with_reset_error.1741749639 |
| Directory | /workspace/57.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/57.xbar_unmapped_addr.1116041129 |
| Short name | T2435 |
| Test name | |
| Test status | |
| Simulation time | 742208564 ps |
| CPU time | 36.18 seconds |
| Started | Aug 12 06:54:26 PM PDT 24 |
| Finished | Aug 12 06:55:02 PM PDT 24 |
| Peak memory | 575872 kb |
| Host | smart-a7013052-7dd9-4c1a-8c6e-c6b8523f2698 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1116041129 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 57.xbar_unmapped_addr.1116041129 |
| Directory | /workspace/57.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/58.xbar_access_same_device.902876942 |
| Short name | T2848 |
| Test name | |
| Test status | |
| Simulation time | 747946933 ps |
| CPU time | 65.06 seconds |
| Started | Aug 12 06:54:25 PM PDT 24 |
| Finished | Aug 12 06:55:30 PM PDT 24 |
| Peak memory | 575772 kb |
| Host | smart-eeed1c06-c5b8-4bb8-a4cd-6af7c7b51d4a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=902876942 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 58.xbar_access_same_device. 902876942 |
| Directory | /workspace/58.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/58.xbar_access_same_device_slow_rsp.3929527890 |
| Short name | T2503 |
| Test name | |
| Test status | |
| Simulation time | 132474376586 ps |
| CPU time | 2445.49 seconds |
| Started | Aug 12 06:54:24 PM PDT 24 |
| Finished | Aug 12 07:35:10 PM PDT 24 |
| Peak memory | 575784 kb |
| Host | smart-43fa402f-4c91-412d-8753-6a4417031e8f |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3929527890 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 58.xbar_access_same_ device_slow_rsp.3929527890 |
| Directory | /workspace/58.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/58.xbar_error_and_unmapped_addr.1625763758 |
| Short name | T1816 |
| Test name | |
| Test status | |
| Simulation time | 198435345 ps |
| CPU time | 22.65 seconds |
| Started | Aug 12 06:54:27 PM PDT 24 |
| Finished | Aug 12 06:54:49 PM PDT 24 |
| Peak memory | 575700 kb |
| Host | smart-26c65ddf-f606-47a7-87f5-076c5aee9d5d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1625763758 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 58.xbar_error_and_unmapped_add r.1625763758 |
| Directory | /workspace/58.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/58.xbar_error_random.2715491165 |
| Short name | T2926 |
| Test name | |
| Test status | |
| Simulation time | 188371407 ps |
| CPU time | 9.99 seconds |
| Started | Aug 12 06:54:24 PM PDT 24 |
| Finished | Aug 12 06:54:34 PM PDT 24 |
| Peak memory | 573652 kb |
| Host | smart-920c84ef-ceb7-49df-9945-0b293c7fe114 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2715491165 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 58.xbar_error_random.2715491165 |
| Directory | /workspace/58.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/58.xbar_random.1590087150 |
| Short name | T509 |
| Test name | |
| Test status | |
| Simulation time | 1569647856 ps |
| CPU time | 50.04 seconds |
| Started | Aug 12 06:54:24 PM PDT 24 |
| Finished | Aug 12 06:55:14 PM PDT 24 |
| Peak memory | 575624 kb |
| Host | smart-0a794511-f0e3-4201-97e5-9a587ce01644 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1590087150 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 58.xbar_random.1590087150 |
| Directory | /workspace/58.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/58.xbar_random_large_delays.766441230 |
| Short name | T1808 |
| Test name | |
| Test status | |
| Simulation time | 53055819794 ps |
| CPU time | 525.62 seconds |
| Started | Aug 12 06:54:21 PM PDT 24 |
| Finished | Aug 12 07:03:07 PM PDT 24 |
| Peak memory | 575808 kb |
| Host | smart-46e6f2ac-199c-4e0d-b024-80d8bb01867f |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=766441230 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 58.xbar_random_large_delays.766441230 |
| Directory | /workspace/58.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/58.xbar_random_slow_rsp.3828544166 |
| Short name | T597 |
| Test name | |
| Test status | |
| Simulation time | 64864355587 ps |
| CPU time | 1169.73 seconds |
| Started | Aug 12 06:54:28 PM PDT 24 |
| Finished | Aug 12 07:13:57 PM PDT 24 |
| Peak memory | 575632 kb |
| Host | smart-09d82f04-7631-4d86-8305-a882c0987ce7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3828544166 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 58.xbar_random_slow_rsp.3828544166 |
| Directory | /workspace/58.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/58.xbar_random_zero_delays.1142215704 |
| Short name | T1707 |
| Test name | |
| Test status | |
| Simulation time | 440358196 ps |
| CPU time | 37.72 seconds |
| Started | Aug 12 06:54:22 PM PDT 24 |
| Finished | Aug 12 06:55:00 PM PDT 24 |
| Peak memory | 575528 kb |
| Host | smart-69425816-3b0b-48e0-84bf-9637cca8f261 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1142215704 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 58.xbar_random_zero_del ays.1142215704 |
| Directory | /workspace/58.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/58.xbar_same_source.2933363918 |
| Short name | T2537 |
| Test name | |
| Test status | |
| Simulation time | 767422056 ps |
| CPU time | 23.53 seconds |
| Started | Aug 12 06:54:27 PM PDT 24 |
| Finished | Aug 12 06:54:51 PM PDT 24 |
| Peak memory | 575560 kb |
| Host | smart-61a10922-906f-423a-8e50-8398d4635a18 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2933363918 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 58.xbar_same_source.2933363918 |
| Directory | /workspace/58.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/58.xbar_smoke.986923825 |
| Short name | T1729 |
| Test name | |
| Test status | |
| Simulation time | 197067026 ps |
| CPU time | 9.45 seconds |
| Started | Aug 12 06:54:25 PM PDT 24 |
| Finished | Aug 12 06:54:34 PM PDT 24 |
| Peak memory | 573588 kb |
| Host | smart-01e655a9-be96-4110-a2cf-7420ca2ff3ce |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=986923825 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 58.xbar_smoke.986923825 |
| Directory | /workspace/58.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/58.xbar_smoke_large_delays.3707802579 |
| Short name | T2289 |
| Test name | |
| Test status | |
| Simulation time | 10553993214 ps |
| CPU time | 108.87 seconds |
| Started | Aug 12 06:54:27 PM PDT 24 |
| Finished | Aug 12 06:56:16 PM PDT 24 |
| Peak memory | 574352 kb |
| Host | smart-bf48638f-4538-47c8-8393-b695e397e16f |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3707802579 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 58.xbar_smoke_large_delays.3707802579 |
| Directory | /workspace/58.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/58.xbar_smoke_slow_rsp.1268257143 |
| Short name | T1834 |
| Test name | |
| Test status | |
| Simulation time | 5115741167 ps |
| CPU time | 84.03 seconds |
| Started | Aug 12 06:54:25 PM PDT 24 |
| Finished | Aug 12 06:55:49 PM PDT 24 |
| Peak memory | 573696 kb |
| Host | smart-6454c93f-15e3-463c-99dc-482a70fc9e2e |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1268257143 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 58.xbar_smoke_slow_rsp.1268257143 |
| Directory | /workspace/58.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/58.xbar_smoke_zero_delays.3100899765 |
| Short name | T2078 |
| Test name | |
| Test status | |
| Simulation time | 50854199 ps |
| CPU time | 6.53 seconds |
| Started | Aug 12 06:54:26 PM PDT 24 |
| Finished | Aug 12 06:54:32 PM PDT 24 |
| Peak memory | 574300 kb |
| Host | smart-b089a71c-7945-421a-b9b1-3e9ddd3772d2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3100899765 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 58.xbar_smoke_zero_delay s.3100899765 |
| Directory | /workspace/58.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/58.xbar_stress_all.2232257878 |
| Short name | T2060 |
| Test name | |
| Test status | |
| Simulation time | 1014787761 ps |
| CPU time | 70.68 seconds |
| Started | Aug 12 06:54:27 PM PDT 24 |
| Finished | Aug 12 06:55:38 PM PDT 24 |
| Peak memory | 575692 kb |
| Host | smart-b988e3db-4a93-4e01-b1c6-510688f2b7b4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2232257878 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 58.xbar_stress_all.2232257878 |
| Directory | /workspace/58.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/58.xbar_stress_all_with_error.1079688167 |
| Short name | T2936 |
| Test name | |
| Test status | |
| Simulation time | 8414270003 ps |
| CPU time | 285.71 seconds |
| Started | Aug 12 06:54:35 PM PDT 24 |
| Finished | Aug 12 06:59:21 PM PDT 24 |
| Peak memory | 576568 kb |
| Host | smart-d34e875c-46f5-45eb-a8c5-c281ec34b119 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1079688167 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 58.xbar_stress_all_with_error.1079688167 |
| Directory | /workspace/58.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/58.xbar_stress_all_with_rand_reset.3027287219 |
| Short name | T1708 |
| Test name | |
| Test status | |
| Simulation time | 20579098 ps |
| CPU time | 9.91 seconds |
| Started | Aug 12 06:54:28 PM PDT 24 |
| Finished | Aug 12 06:54:38 PM PDT 24 |
| Peak memory | 573640 kb |
| Host | smart-a673aac5-7234-4736-b624-cd8b15d78f11 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3027287219 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 58.xbar_stress_all _with_rand_reset.3027287219 |
| Directory | /workspace/58.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/58.xbar_stress_all_with_reset_error.3904088951 |
| Short name | T959 |
| Test name | |
| Test status | |
| Simulation time | 242400343 ps |
| CPU time | 72.84 seconds |
| Started | Aug 12 06:54:31 PM PDT 24 |
| Finished | Aug 12 06:55:44 PM PDT 24 |
| Peak memory | 575708 kb |
| Host | smart-d6cd653f-cfec-4f2e-b60b-d87a0a00620a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3904088951 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 58.xbar_stress_al l_with_reset_error.3904088951 |
| Directory | /workspace/58.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/58.xbar_unmapped_addr.3643090067 |
| Short name | T2083 |
| Test name | |
| Test status | |
| Simulation time | 159725995 ps |
| CPU time | 10.46 seconds |
| Started | Aug 12 06:54:27 PM PDT 24 |
| Finished | Aug 12 06:54:37 PM PDT 24 |
| Peak memory | 575584 kb |
| Host | smart-f8f76ca6-5dd4-4f54-b84e-ddf8336c7d70 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3643090067 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 58.xbar_unmapped_addr.3643090067 |
| Directory | /workspace/58.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/59.xbar_access_same_device.2254502773 |
| Short name | T2374 |
| Test name | |
| Test status | |
| Simulation time | 603102931 ps |
| CPU time | 27.49 seconds |
| Started | Aug 12 06:54:35 PM PDT 24 |
| Finished | Aug 12 06:55:02 PM PDT 24 |
| Peak memory | 575624 kb |
| Host | smart-22a7da2f-3524-4a3d-82b9-3d64c6204405 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2254502773 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 59.xbar_access_same_device .2254502773 |
| Directory | /workspace/59.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/59.xbar_error_and_unmapped_addr.1822516434 |
| Short name | T1783 |
| Test name | |
| Test status | |
| Simulation time | 332215381 ps |
| CPU time | 29.74 seconds |
| Started | Aug 12 06:54:32 PM PDT 24 |
| Finished | Aug 12 06:55:02 PM PDT 24 |
| Peak memory | 575740 kb |
| Host | smart-89aa8867-690e-4b4c-bee9-973180d3f3c4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1822516434 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 59.xbar_error_and_unmapped_add r.1822516434 |
| Directory | /workspace/59.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/59.xbar_error_random.2091239796 |
| Short name | T2155 |
| Test name | |
| Test status | |
| Simulation time | 1560369923 ps |
| CPU time | 56.37 seconds |
| Started | Aug 12 06:54:34 PM PDT 24 |
| Finished | Aug 12 06:55:31 PM PDT 24 |
| Peak memory | 575752 kb |
| Host | smart-1055ad28-1bf7-4e1e-966e-3eb2f6302a1e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2091239796 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 59.xbar_error_random.2091239796 |
| Directory | /workspace/59.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/59.xbar_random.894612638 |
| Short name | T582 |
| Test name | |
| Test status | |
| Simulation time | 1054903155 ps |
| CPU time | 38.11 seconds |
| Started | Aug 12 06:54:39 PM PDT 24 |
| Finished | Aug 12 06:55:17 PM PDT 24 |
| Peak memory | 575676 kb |
| Host | smart-8aa0e7e0-6ef9-4396-ad50-553c4d847a79 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=894612638 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 59.xbar_random.894612638 |
| Directory | /workspace/59.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/59.xbar_random_large_delays.2165296868 |
| Short name | T2413 |
| Test name | |
| Test status | |
| Simulation time | 78517203033 ps |
| CPU time | 772.19 seconds |
| Started | Aug 12 06:54:37 PM PDT 24 |
| Finished | Aug 12 07:07:30 PM PDT 24 |
| Peak memory | 575804 kb |
| Host | smart-46f942a8-3d48-462d-a42f-038f8b6c2b7a |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2165296868 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 59.xbar_random_large_delays.2165296868 |
| Directory | /workspace/59.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/59.xbar_random_slow_rsp.998132709 |
| Short name | T569 |
| Test name | |
| Test status | |
| Simulation time | 56167711825 ps |
| CPU time | 1043.5 seconds |
| Started | Aug 12 06:54:35 PM PDT 24 |
| Finished | Aug 12 07:11:59 PM PDT 24 |
| Peak memory | 575776 kb |
| Host | smart-0c8eb02b-a394-4d76-ac5d-ce9607c4d863 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=998132709 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 59.xbar_random_slow_rsp.998132709 |
| Directory | /workspace/59.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/59.xbar_random_zero_delays.192660309 |
| Short name | T1452 |
| Test name | |
| Test status | |
| Simulation time | 44326582 ps |
| CPU time | 6.89 seconds |
| Started | Aug 12 06:54:36 PM PDT 24 |
| Finished | Aug 12 06:54:43 PM PDT 24 |
| Peak memory | 573604 kb |
| Host | smart-f76a8c18-a30a-445b-b724-1b27ef89da6f |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=192660309 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 59.xbar_random_zero_dela ys.192660309 |
| Directory | /workspace/59.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/59.xbar_same_source.1118469112 |
| Short name | T1670 |
| Test name | |
| Test status | |
| Simulation time | 2551281368 ps |
| CPU time | 73.43 seconds |
| Started | Aug 12 06:54:36 PM PDT 24 |
| Finished | Aug 12 06:55:49 PM PDT 24 |
| Peak memory | 575724 kb |
| Host | smart-6c448bea-1142-40eb-a564-909c8b34b446 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1118469112 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 59.xbar_same_source.1118469112 |
| Directory | /workspace/59.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/59.xbar_smoke.3512072616 |
| Short name | T2675 |
| Test name | |
| Test status | |
| Simulation time | 45381227 ps |
| CPU time | 6.19 seconds |
| Started | Aug 12 06:54:39 PM PDT 24 |
| Finished | Aug 12 06:54:45 PM PDT 24 |
| Peak memory | 573536 kb |
| Host | smart-e6083eb9-776f-4e2f-9496-73fa51d3c20c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3512072616 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 59.xbar_smoke.3512072616 |
| Directory | /workspace/59.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/59.xbar_smoke_large_delays.464340737 |
| Short name | T1918 |
| Test name | |
| Test status | |
| Simulation time | 8369820846 ps |
| CPU time | 86.82 seconds |
| Started | Aug 12 06:54:33 PM PDT 24 |
| Finished | Aug 12 06:56:00 PM PDT 24 |
| Peak memory | 573648 kb |
| Host | smart-5f24236a-d3e8-41ea-be70-5df3238eb027 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=464340737 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 59.xbar_smoke_large_delays.464340737 |
| Directory | /workspace/59.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/59.xbar_smoke_slow_rsp.4144286205 |
| Short name | T2443 |
| Test name | |
| Test status | |
| Simulation time | 6659923000 ps |
| CPU time | 112.54 seconds |
| Started | Aug 12 06:54:42 PM PDT 24 |
| Finished | Aug 12 06:56:34 PM PDT 24 |
| Peak memory | 573692 kb |
| Host | smart-258b057b-e22f-41bc-90b4-db595d834b63 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4144286205 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 59.xbar_smoke_slow_rsp.4144286205 |
| Directory | /workspace/59.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/59.xbar_smoke_zero_delays.3625580583 |
| Short name | T2285 |
| Test name | |
| Test status | |
| Simulation time | 51602749 ps |
| CPU time | 6.45 seconds |
| Started | Aug 12 06:54:35 PM PDT 24 |
| Finished | Aug 12 06:54:42 PM PDT 24 |
| Peak memory | 573616 kb |
| Host | smart-353367ec-b480-4f73-a29f-32df8fb79b25 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3625580583 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 59.xbar_smoke_zero_delay s.3625580583 |
| Directory | /workspace/59.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/59.xbar_stress_all.1257985819 |
| Short name | T2604 |
| Test name | |
| Test status | |
| Simulation time | 3868459870 ps |
| CPU time | 124.45 seconds |
| Started | Aug 12 06:54:36 PM PDT 24 |
| Finished | Aug 12 06:56:41 PM PDT 24 |
| Peak memory | 576012 kb |
| Host | smart-e7cc01ca-12fc-48d1-a665-d8d35e7ce8c4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1257985819 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 59.xbar_stress_all.1257985819 |
| Directory | /workspace/59.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/59.xbar_stress_all_with_error.823053533 |
| Short name | T1955 |
| Test name | |
| Test status | |
| Simulation time | 2040944741 ps |
| CPU time | 168.76 seconds |
| Started | Aug 12 06:54:35 PM PDT 24 |
| Finished | Aug 12 06:57:24 PM PDT 24 |
| Peak memory | 576464 kb |
| Host | smart-f8e7fa87-e4fe-46e7-b5b1-cf6089290e75 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=823053533 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 59.xbar_stress_all_with_error.823053533 |
| Directory | /workspace/59.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/59.xbar_stress_all_with_rand_reset.4163444357 |
| Short name | T2182 |
| Test name | |
| Test status | |
| Simulation time | 4846259065 ps |
| CPU time | 196.24 seconds |
| Started | Aug 12 06:54:42 PM PDT 24 |
| Finished | Aug 12 06:57:58 PM PDT 24 |
| Peak memory | 575804 kb |
| Host | smart-a7e99a74-95f5-4f89-9b2f-0c73ce5aa371 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4163444357 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 59.xbar_stress_all _with_rand_reset.4163444357 |
| Directory | /workspace/59.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/59.xbar_stress_all_with_reset_error.1378721051 |
| Short name | T2664 |
| Test name | |
| Test status | |
| Simulation time | 40279528 ps |
| CPU time | 9.82 seconds |
| Started | Aug 12 06:54:39 PM PDT 24 |
| Finished | Aug 12 06:54:49 PM PDT 24 |
| Peak memory | 575812 kb |
| Host | smart-af65c84c-80f8-45f8-961e-665835c9ea98 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1378721051 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 59.xbar_stress_al l_with_reset_error.1378721051 |
| Directory | /workspace/59.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/59.xbar_unmapped_addr.2749369591 |
| Short name | T1483 |
| Test name | |
| Test status | |
| Simulation time | 20626779 ps |
| CPU time | 5.47 seconds |
| Started | Aug 12 06:54:36 PM PDT 24 |
| Finished | Aug 12 06:54:42 PM PDT 24 |
| Peak memory | 573656 kb |
| Host | smart-9cb731c4-e5a5-4aba-b5b2-9ea64b12d71f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2749369591 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 59.xbar_unmapped_addr.2749369591 |
| Directory | /workspace/59.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/6.chip_csr_mem_rw_with_rand_reset.951521795 |
| Short name | T2874 |
| Test name | |
| Test status | |
| Simulation time | 10956049655 ps |
| CPU time | 848.36 seconds |
| Started | Aug 12 06:47:40 PM PDT 24 |
| Finished | Aug 12 07:01:49 PM PDT 24 |
| Peak memory | 646348 kb |
| Host | smart-178ff983-c36b-474a-88fb-bdb033b9c723 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=951521795 -assert nopostproc +U VM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top. vdb -cm_log /dev/null -cm_name 6.chip_csr_mem_rw_with_rand_reset.951521795 |
| Directory | /workspace/6.chip_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/6.chip_csr_rw.3671750004 |
| Short name | T2781 |
| Test name | |
| Test status | |
| Simulation time | 3570966446 ps |
| CPU time | 262.1 seconds |
| Started | Aug 12 06:47:41 PM PDT 24 |
| Finished | Aug 12 06:52:03 PM PDT 24 |
| Peak memory | 596724 kb |
| Host | smart-9fa1b958-d3cd-4dd5-9a97-6906d353996a |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3671750004 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.chip_csr_rw.3671750004 |
| Directory | /workspace/6.chip_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/6.chip_same_csr_outstanding.3975301353 |
| Short name | T1939 |
| Test name | |
| Test status | |
| Simulation time | 14782615710 ps |
| CPU time | 1534.75 seconds |
| Started | Aug 12 06:47:28 PM PDT 24 |
| Finished | Aug 12 07:13:03 PM PDT 24 |
| Peak memory | 592940 kb |
| Host | smart-00c2b414-42b9-4cc9-89d3-8dba5038d5ba |
| User | root |
| Command | /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +run_same_csr_outstanding +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3975301353 -assert nopostproc +UVM_TE STNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb - cm_log /dev/null -cm_name 6.chip_same_csr_outstanding.3975301353 |
| Directory | /workspace/6.chip_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/6.chip_tl_errors.283789879 |
| Short name | T772 |
| Test name | |
| Test status | |
| Simulation time | 4177850064 ps |
| CPU time | 286.91 seconds |
| Started | Aug 12 06:47:27 PM PDT 24 |
| Finished | Aug 12 06:52:14 PM PDT 24 |
| Peak memory | 603300 kb |
| Host | smart-33272a16-55de-4667-be42-88bf8937dbe3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=283789879 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.chip_tl_errors.283789879 |
| Directory | /workspace/6.chip_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/6.xbar_access_same_device.533574302 |
| Short name | T2007 |
| Test name | |
| Test status | |
| Simulation time | 438103243 ps |
| CPU time | 17.71 seconds |
| Started | Aug 12 06:47:35 PM PDT 24 |
| Finished | Aug 12 06:47:52 PM PDT 24 |
| Peak memory | 575708 kb |
| Host | smart-810cab5b-5492-41c9-8c2d-501e665c9505 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=533574302 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.xbar_access_same_device.533574302 |
| Directory | /workspace/6.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/6.xbar_access_same_device_slow_rsp.2685965154 |
| Short name | T2148 |
| Test name | |
| Test status | |
| Simulation time | 40230541122 ps |
| CPU time | 686.2 seconds |
| Started | Aug 12 06:47:32 PM PDT 24 |
| Finished | Aug 12 06:58:59 PM PDT 24 |
| Peak memory | 575704 kb |
| Host | smart-c63c2fb0-bf21-4249-9a5e-444b38503593 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2685965154 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.xbar_access_same_d evice_slow_rsp.2685965154 |
| Directory | /workspace/6.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/6.xbar_error_and_unmapped_addr.3856874173 |
| Short name | T2811 |
| Test name | |
| Test status | |
| Simulation time | 92054626 ps |
| CPU time | 10.59 seconds |
| Started | Aug 12 06:47:41 PM PDT 24 |
| Finished | Aug 12 06:47:51 PM PDT 24 |
| Peak memory | 575728 kb |
| Host | smart-d4c592f2-71ca-40d0-b2f9-83a3205a3fa2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3856874173 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.xbar_error_and_unmapped_addr .3856874173 |
| Directory | /workspace/6.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/6.xbar_error_random.3154139028 |
| Short name | T1557 |
| Test name | |
| Test status | |
| Simulation time | 424335465 ps |
| CPU time | 28.35 seconds |
| Started | Aug 12 06:47:30 PM PDT 24 |
| Finished | Aug 12 06:47:58 PM PDT 24 |
| Peak memory | 575732 kb |
| Host | smart-ec9ead6e-48da-4020-9b45-88b2339e7343 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3154139028 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.xbar_error_random.3154139028 |
| Directory | /workspace/6.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/6.xbar_random.3689434058 |
| Short name | T2041 |
| Test name | |
| Test status | |
| Simulation time | 225855376 ps |
| CPU time | 20.96 seconds |
| Started | Aug 12 06:47:30 PM PDT 24 |
| Finished | Aug 12 06:47:51 PM PDT 24 |
| Peak memory | 575624 kb |
| Host | smart-d2bb8c3c-c825-4f25-94d2-61d6954f9b4e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3689434058 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.xbar_random.3689434058 |
| Directory | /workspace/6.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/6.xbar_random_large_delays.166677390 |
| Short name | T2094 |
| Test name | |
| Test status | |
| Simulation time | 41946589110 ps |
| CPU time | 407.22 seconds |
| Started | Aug 12 06:47:34 PM PDT 24 |
| Finished | Aug 12 06:54:21 PM PDT 24 |
| Peak memory | 575648 kb |
| Host | smart-42fb54bc-ef8c-43c9-a756-dd60de5eb3ba |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=166677390 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.xbar_random_large_delays.166677390 |
| Directory | /workspace/6.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/6.xbar_random_slow_rsp.2785817839 |
| Short name | T1622 |
| Test name | |
| Test status | |
| Simulation time | 6671500068 ps |
| CPU time | 106.42 seconds |
| Started | Aug 12 06:47:34 PM PDT 24 |
| Finished | Aug 12 06:49:20 PM PDT 24 |
| Peak memory | 575808 kb |
| Host | smart-ba774d53-b24c-4a97-9663-b58879a4fba2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2785817839 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.xbar_random_slow_rsp.2785817839 |
| Directory | /workspace/6.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/6.xbar_random_zero_delays.3822047490 |
| Short name | T2190 |
| Test name | |
| Test status | |
| Simulation time | 499171568 ps |
| CPU time | 42.63 seconds |
| Started | Aug 12 06:47:30 PM PDT 24 |
| Finished | Aug 12 06:48:13 PM PDT 24 |
| Peak memory | 575620 kb |
| Host | smart-0283b602-d7ad-48b7-a6a3-b3ff9ef23c5d |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3822047490 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.xbar_random_zero_dela ys.3822047490 |
| Directory | /workspace/6.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/6.xbar_same_source.3177193075 |
| Short name | T1520 |
| Test name | |
| Test status | |
| Simulation time | 85948029 ps |
| CPU time | 9.21 seconds |
| Started | Aug 12 06:47:25 PM PDT 24 |
| Finished | Aug 12 06:47:34 PM PDT 24 |
| Peak memory | 575496 kb |
| Host | smart-32e07610-18ad-41e1-ad88-84c86b9a82f2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3177193075 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.xbar_same_source.3177193075 |
| Directory | /workspace/6.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/6.xbar_smoke.3285009566 |
| Short name | T2893 |
| Test name | |
| Test status | |
| Simulation time | 42409086 ps |
| CPU time | 5.43 seconds |
| Started | Aug 12 06:47:27 PM PDT 24 |
| Finished | Aug 12 06:47:32 PM PDT 24 |
| Peak memory | 573620 kb |
| Host | smart-656c4c95-c74a-44df-888d-fcef0b5fc38c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3285009566 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.xbar_smoke.3285009566 |
| Directory | /workspace/6.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/6.xbar_smoke_large_delays.183422049 |
| Short name | T2419 |
| Test name | |
| Test status | |
| Simulation time | 9962780934 ps |
| CPU time | 103.58 seconds |
| Started | Aug 12 06:47:29 PM PDT 24 |
| Finished | Aug 12 06:49:13 PM PDT 24 |
| Peak memory | 573668 kb |
| Host | smart-01c678d3-370e-499b-b455-eeba05750300 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=183422049 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.xbar_smoke_large_delays.183422049 |
| Directory | /workspace/6.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/6.xbar_smoke_slow_rsp.384606798 |
| Short name | T2534 |
| Test name | |
| Test status | |
| Simulation time | 6454170810 ps |
| CPU time | 103.7 seconds |
| Started | Aug 12 06:47:29 PM PDT 24 |
| Finished | Aug 12 06:49:13 PM PDT 24 |
| Peak memory | 573672 kb |
| Host | smart-423757d2-116d-491f-9d0c-57f1b9941c4f |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=384606798 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.xbar_smoke_slow_rsp.384606798 |
| Directory | /workspace/6.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/6.xbar_smoke_zero_delays.2198423505 |
| Short name | T2164 |
| Test name | |
| Test status | |
| Simulation time | 42930220 ps |
| CPU time | 6.3 seconds |
| Started | Aug 12 06:47:30 PM PDT 24 |
| Finished | Aug 12 06:47:36 PM PDT 24 |
| Peak memory | 574228 kb |
| Host | smart-b772af29-662c-4cff-b073-5dda34f5c90b |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2198423505 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.xbar_smoke_zero_delays .2198423505 |
| Directory | /workspace/6.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/6.xbar_stress_all.1599244175 |
| Short name | T1773 |
| Test name | |
| Test status | |
| Simulation time | 5660886403 ps |
| CPU time | 207.96 seconds |
| Started | Aug 12 06:47:28 PM PDT 24 |
| Finished | Aug 12 06:50:56 PM PDT 24 |
| Peak memory | 576568 kb |
| Host | smart-7e662d7a-d26d-4a4f-bd0f-4e31885741c0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1599244175 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.xbar_stress_all.1599244175 |
| Directory | /workspace/6.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/6.xbar_stress_all_with_error.3720779633 |
| Short name | T2845 |
| Test name | |
| Test status | |
| Simulation time | 7476506807 ps |
| CPU time | 283.28 seconds |
| Started | Aug 12 06:47:30 PM PDT 24 |
| Finished | Aug 12 06:52:14 PM PDT 24 |
| Peak memory | 575860 kb |
| Host | smart-817e1f2d-b248-4540-8608-e8bc90ae1373 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3720779633 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.xbar_stress_all_with_error.3720779633 |
| Directory | /workspace/6.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/6.xbar_unmapped_addr.811869052 |
| Short name | T1956 |
| Test name | |
| Test status | |
| Simulation time | 96254690 ps |
| CPU time | 11.45 seconds |
| Started | Aug 12 06:47:41 PM PDT 24 |
| Finished | Aug 12 06:47:52 PM PDT 24 |
| Peak memory | 575720 kb |
| Host | smart-836283b1-c1d6-40b5-a5b8-42db5a30631e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=811869052 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.xbar_unmapped_addr.811869052 |
| Directory | /workspace/6.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/60.xbar_access_same_device.1814088115 |
| Short name | T918 |
| Test name | |
| Test status | |
| Simulation time | 58614761 ps |
| CPU time | 6.64 seconds |
| Started | Aug 12 06:54:38 PM PDT 24 |
| Finished | Aug 12 06:54:45 PM PDT 24 |
| Peak memory | 574256 kb |
| Host | smart-41da1915-99af-4821-9905-ae183a350f12 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1814088115 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 60.xbar_access_same_device .1814088115 |
| Directory | /workspace/60.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/60.xbar_access_same_device_slow_rsp.1317545358 |
| Short name | T2109 |
| Test name | |
| Test status | |
| Simulation time | 61102877607 ps |
| CPU time | 1151.42 seconds |
| Started | Aug 12 06:54:34 PM PDT 24 |
| Finished | Aug 12 07:13:46 PM PDT 24 |
| Peak memory | 575732 kb |
| Host | smart-9da38597-51d8-44c2-8986-157a4226bcca |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1317545358 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 60.xbar_access_same_ device_slow_rsp.1317545358 |
| Directory | /workspace/60.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/60.xbar_error_and_unmapped_addr.506171600 |
| Short name | T2026 |
| Test name | |
| Test status | |
| Simulation time | 850333458 ps |
| CPU time | 35.17 seconds |
| Started | Aug 12 06:54:43 PM PDT 24 |
| Finished | Aug 12 06:55:19 PM PDT 24 |
| Peak memory | 575520 kb |
| Host | smart-64a4bd1e-50e9-4bcc-8566-c258be5455cd |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=506171600 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 60.xbar_error_and_unmapped_addr .506171600 |
| Directory | /workspace/60.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/60.xbar_error_random.4037379517 |
| Short name | T2670 |
| Test name | |
| Test status | |
| Simulation time | 359019747 ps |
| CPU time | 25.92 seconds |
| Started | Aug 12 06:54:44 PM PDT 24 |
| Finished | Aug 12 06:55:10 PM PDT 24 |
| Peak memory | 575700 kb |
| Host | smart-4c5f8849-91a3-4ef1-80ad-d1f097e8ec21 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4037379517 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 60.xbar_error_random.4037379517 |
| Directory | /workspace/60.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/60.xbar_random.1403691025 |
| Short name | T2143 |
| Test name | |
| Test status | |
| Simulation time | 2219230262 ps |
| CPU time | 83.12 seconds |
| Started | Aug 12 06:54:37 PM PDT 24 |
| Finished | Aug 12 06:56:00 PM PDT 24 |
| Peak memory | 575796 kb |
| Host | smart-f9570e17-5a6f-4e0e-948e-945943c7be60 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1403691025 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 60.xbar_random.1403691025 |
| Directory | /workspace/60.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/60.xbar_random_large_delays.3116702386 |
| Short name | T1898 |
| Test name | |
| Test status | |
| Simulation time | 3996460846 ps |
| CPU time | 40.66 seconds |
| Started | Aug 12 06:54:34 PM PDT 24 |
| Finished | Aug 12 06:55:15 PM PDT 24 |
| Peak memory | 574380 kb |
| Host | smart-11660772-3c5a-4526-8029-42efc18d0d71 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3116702386 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 60.xbar_random_large_delays.3116702386 |
| Directory | /workspace/60.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/60.xbar_random_slow_rsp.372563521 |
| Short name | T737 |
| Test name | |
| Test status | |
| Simulation time | 32181077108 ps |
| CPU time | 552.08 seconds |
| Started | Aug 12 06:54:35 PM PDT 24 |
| Finished | Aug 12 07:03:47 PM PDT 24 |
| Peak memory | 575624 kb |
| Host | smart-4c359ecb-0eaf-4cfa-a107-a9c60808af0c |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=372563521 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 60.xbar_random_slow_rsp.372563521 |
| Directory | /workspace/60.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/60.xbar_random_zero_delays.2353918747 |
| Short name | T622 |
| Test name | |
| Test status | |
| Simulation time | 472684524 ps |
| CPU time | 44.46 seconds |
| Started | Aug 12 06:54:35 PM PDT 24 |
| Finished | Aug 12 06:55:20 PM PDT 24 |
| Peak memory | 575688 kb |
| Host | smart-37cf1c1f-97a2-4cfe-b8b5-78fb56d071d8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2353918747 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 60.xbar_random_zero_del ays.2353918747 |
| Directory | /workspace/60.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/60.xbar_same_source.479427843 |
| Short name | T2806 |
| Test name | |
| Test status | |
| Simulation time | 2330134603 ps |
| CPU time | 67.26 seconds |
| Started | Aug 12 06:54:35 PM PDT 24 |
| Finished | Aug 12 06:55:42 PM PDT 24 |
| Peak memory | 575752 kb |
| Host | smart-4be9530e-2fa5-43ba-8e20-6073fae3f71b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=479427843 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 60.xbar_same_source.479427843 |
| Directory | /workspace/60.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/60.xbar_smoke.3376991538 |
| Short name | T1689 |
| Test name | |
| Test status | |
| Simulation time | 43273635 ps |
| CPU time | 6.05 seconds |
| Started | Aug 12 06:54:38 PM PDT 24 |
| Finished | Aug 12 06:54:44 PM PDT 24 |
| Peak memory | 574264 kb |
| Host | smart-d35a3feb-f4a1-4f7a-bfc8-ae524ef0c219 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3376991538 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 60.xbar_smoke.3376991538 |
| Directory | /workspace/60.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/60.xbar_smoke_large_delays.832943787 |
| Short name | T1564 |
| Test name | |
| Test status | |
| Simulation time | 8241135068 ps |
| CPU time | 86.73 seconds |
| Started | Aug 12 06:54:35 PM PDT 24 |
| Finished | Aug 12 06:56:02 PM PDT 24 |
| Peak memory | 573624 kb |
| Host | smart-d04bda65-f8c8-448b-b8b9-bd982bb7e542 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=832943787 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 60.xbar_smoke_large_delays.832943787 |
| Directory | /workspace/60.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/60.xbar_smoke_slow_rsp.361074625 |
| Short name | T2584 |
| Test name | |
| Test status | |
| Simulation time | 3788547686 ps |
| CPU time | 61.32 seconds |
| Started | Aug 12 06:54:36 PM PDT 24 |
| Finished | Aug 12 06:55:38 PM PDT 24 |
| Peak memory | 573668 kb |
| Host | smart-ba7512ca-15f5-4bb3-beaa-c8332c1c10f2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=361074625 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 60.xbar_smoke_slow_rsp.361074625 |
| Directory | /workspace/60.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/60.xbar_smoke_zero_delays.2782728788 |
| Short name | T2442 |
| Test name | |
| Test status | |
| Simulation time | 45122494 ps |
| CPU time | 5.81 seconds |
| Started | Aug 12 06:54:42 PM PDT 24 |
| Finished | Aug 12 06:54:48 PM PDT 24 |
| Peak memory | 573608 kb |
| Host | smart-b995c253-1ff6-46ae-b73d-bfbecbcd3e0a |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2782728788 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 60.xbar_smoke_zero_delay s.2782728788 |
| Directory | /workspace/60.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/60.xbar_stress_all.3002407163 |
| Short name | T2332 |
| Test name | |
| Test status | |
| Simulation time | 12406818506 ps |
| CPU time | 484.05 seconds |
| Started | Aug 12 06:54:45 PM PDT 24 |
| Finished | Aug 12 07:02:49 PM PDT 24 |
| Peak memory | 576616 kb |
| Host | smart-6ff939c8-d312-4557-ab57-3f237e0cfa3f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3002407163 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 60.xbar_stress_all.3002407163 |
| Directory | /workspace/60.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/60.xbar_stress_all_with_rand_reset.1944037877 |
| Short name | T1762 |
| Test name | |
| Test status | |
| Simulation time | 156515306 ps |
| CPU time | 36.66 seconds |
| Started | Aug 12 06:54:47 PM PDT 24 |
| Finished | Aug 12 06:55:24 PM PDT 24 |
| Peak memory | 575704 kb |
| Host | smart-24783cf6-ddd8-418f-b573-7be661ea8fb6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1944037877 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 60.xbar_stress_all _with_rand_reset.1944037877 |
| Directory | /workspace/60.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/60.xbar_stress_all_with_reset_error.2855160652 |
| Short name | T903 |
| Test name | |
| Test status | |
| Simulation time | 4500278429 ps |
| CPU time | 367.45 seconds |
| Started | Aug 12 06:54:45 PM PDT 24 |
| Finished | Aug 12 07:00:53 PM PDT 24 |
| Peak memory | 576640 kb |
| Host | smart-3f0fdfd6-c9cf-4cae-8a6a-bf6df5332940 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2855160652 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 60.xbar_stress_al l_with_reset_error.2855160652 |
| Directory | /workspace/60.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/60.xbar_unmapped_addr.1053128825 |
| Short name | T2748 |
| Test name | |
| Test status | |
| Simulation time | 193528412 ps |
| CPU time | 22.7 seconds |
| Started | Aug 12 06:54:45 PM PDT 24 |
| Finished | Aug 12 06:55:08 PM PDT 24 |
| Peak memory | 575780 kb |
| Host | smart-7d052adc-113b-40ac-98cc-a39243336ab2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1053128825 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 60.xbar_unmapped_addr.1053128825 |
| Directory | /workspace/60.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/61.xbar_access_same_device.184304792 |
| Short name | T1691 |
| Test name | |
| Test status | |
| Simulation time | 1707092048 ps |
| CPU time | 77.98 seconds |
| Started | Aug 12 06:54:47 PM PDT 24 |
| Finished | Aug 12 06:56:05 PM PDT 24 |
| Peak memory | 575568 kb |
| Host | smart-1db5c30c-e62b-4b4d-9a4e-68b8e2d03efa |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=184304792 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 61.xbar_access_same_device. 184304792 |
| Directory | /workspace/61.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/61.xbar_access_same_device_slow_rsp.3786532596 |
| Short name | T2179 |
| Test name | |
| Test status | |
| Simulation time | 57099488553 ps |
| CPU time | 1026.78 seconds |
| Started | Aug 12 06:54:45 PM PDT 24 |
| Finished | Aug 12 07:11:52 PM PDT 24 |
| Peak memory | 575744 kb |
| Host | smart-ef6801d5-bee4-4c9f-b541-e4a49094553d |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3786532596 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 61.xbar_access_same_ device_slow_rsp.3786532596 |
| Directory | /workspace/61.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/61.xbar_error_and_unmapped_addr.3575334467 |
| Short name | T2426 |
| Test name | |
| Test status | |
| Simulation time | 357753824 ps |
| CPU time | 14.85 seconds |
| Started | Aug 12 06:54:48 PM PDT 24 |
| Finished | Aug 12 06:55:03 PM PDT 24 |
| Peak memory | 575736 kb |
| Host | smart-6d735877-263e-40e7-9b1c-06638decb437 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3575334467 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 61.xbar_error_and_unmapped_add r.3575334467 |
| Directory | /workspace/61.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/61.xbar_error_random.1868690243 |
| Short name | T1548 |
| Test name | |
| Test status | |
| Simulation time | 1157443758 ps |
| CPU time | 39.87 seconds |
| Started | Aug 12 06:54:48 PM PDT 24 |
| Finished | Aug 12 06:55:28 PM PDT 24 |
| Peak memory | 575652 kb |
| Host | smart-57ad8cf9-10f8-4f09-9a6d-aa99744f323a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1868690243 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 61.xbar_error_random.1868690243 |
| Directory | /workspace/61.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/61.xbar_random.1139388938 |
| Short name | T2072 |
| Test name | |
| Test status | |
| Simulation time | 2301785322 ps |
| CPU time | 80.38 seconds |
| Started | Aug 12 06:54:44 PM PDT 24 |
| Finished | Aug 12 06:56:05 PM PDT 24 |
| Peak memory | 575732 kb |
| Host | smart-aa97f999-e97a-4a97-969c-183e1323a3b2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1139388938 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 61.xbar_random.1139388938 |
| Directory | /workspace/61.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/61.xbar_random_large_delays.2932156217 |
| Short name | T2305 |
| Test name | |
| Test status | |
| Simulation time | 83569817206 ps |
| CPU time | 907.16 seconds |
| Started | Aug 12 06:54:54 PM PDT 24 |
| Finished | Aug 12 07:10:02 PM PDT 24 |
| Peak memory | 575780 kb |
| Host | smart-c972dda7-697e-45b4-ad20-56aa80003de9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2932156217 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 61.xbar_random_large_delays.2932156217 |
| Directory | /workspace/61.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/61.xbar_random_slow_rsp.1393180507 |
| Short name | T2813 |
| Test name | |
| Test status | |
| Simulation time | 24477582028 ps |
| CPU time | 410.58 seconds |
| Started | Aug 12 06:54:44 PM PDT 24 |
| Finished | Aug 12 07:01:35 PM PDT 24 |
| Peak memory | 575636 kb |
| Host | smart-b195cb5f-f2bf-4cec-b5c7-c752d80247eb |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1393180507 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 61.xbar_random_slow_rsp.1393180507 |
| Directory | /workspace/61.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/61.xbar_random_zero_delays.2295942690 |
| Short name | T2542 |
| Test name | |
| Test status | |
| Simulation time | 591754357 ps |
| CPU time | 49.21 seconds |
| Started | Aug 12 06:54:46 PM PDT 24 |
| Finished | Aug 12 06:55:35 PM PDT 24 |
| Peak memory | 575616 kb |
| Host | smart-e33f8675-b706-4a68-a91c-b4d0bdade8a4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2295942690 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 61.xbar_random_zero_del ays.2295942690 |
| Directory | /workspace/61.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/61.xbar_same_source.1109465097 |
| Short name | T1722 |
| Test name | |
| Test status | |
| Simulation time | 240243134 ps |
| CPU time | 18.65 seconds |
| Started | Aug 12 06:54:54 PM PDT 24 |
| Finished | Aug 12 06:55:13 PM PDT 24 |
| Peak memory | 575552 kb |
| Host | smart-49092d41-ed6a-4f66-94ba-d3e571c4454f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1109465097 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 61.xbar_same_source.1109465097 |
| Directory | /workspace/61.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/61.xbar_smoke.396207860 |
| Short name | T1782 |
| Test name | |
| Test status | |
| Simulation time | 38052208 ps |
| CPU time | 5.97 seconds |
| Started | Aug 12 06:54:48 PM PDT 24 |
| Finished | Aug 12 06:54:54 PM PDT 24 |
| Peak memory | 574204 kb |
| Host | smart-6dc7d081-7a93-4094-8af0-0e9788c85652 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=396207860 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 61.xbar_smoke.396207860 |
| Directory | /workspace/61.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/61.xbar_smoke_large_delays.1194943449 |
| Short name | T2475 |
| Test name | |
| Test status | |
| Simulation time | 8003175564 ps |
| CPU time | 81.64 seconds |
| Started | Aug 12 06:54:46 PM PDT 24 |
| Finished | Aug 12 06:56:08 PM PDT 24 |
| Peak memory | 573652 kb |
| Host | smart-9651e298-000f-4248-b310-cf90d9e9edf7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1194943449 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 61.xbar_smoke_large_delays.1194943449 |
| Directory | /workspace/61.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/61.xbar_smoke_slow_rsp.2173520863 |
| Short name | T1881 |
| Test name | |
| Test status | |
| Simulation time | 4222426280 ps |
| CPU time | 68.03 seconds |
| Started | Aug 12 06:54:44 PM PDT 24 |
| Finished | Aug 12 06:55:52 PM PDT 24 |
| Peak memory | 574288 kb |
| Host | smart-dcbd9e8c-8305-4512-b760-cd4b2513ff61 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2173520863 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 61.xbar_smoke_slow_rsp.2173520863 |
| Directory | /workspace/61.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/61.xbar_smoke_zero_delays.874988432 |
| Short name | T1547 |
| Test name | |
| Test status | |
| Simulation time | 46895174 ps |
| CPU time | 6.83 seconds |
| Started | Aug 12 06:54:45 PM PDT 24 |
| Finished | Aug 12 06:54:52 PM PDT 24 |
| Peak memory | 573568 kb |
| Host | smart-64ce224b-e593-47ef-85fe-5aeaee029c39 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=874988432 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 61.xbar_smoke_zero_delays .874988432 |
| Directory | /workspace/61.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/61.xbar_stress_all.1386893214 |
| Short name | T2310 |
| Test name | |
| Test status | |
| Simulation time | 15590330105 ps |
| CPU time | 640.11 seconds |
| Started | Aug 12 06:54:49 PM PDT 24 |
| Finished | Aug 12 07:05:29 PM PDT 24 |
| Peak memory | 576600 kb |
| Host | smart-1daf77fe-e7d5-48f4-9e1d-2ae00567aa52 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1386893214 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 61.xbar_stress_all.1386893214 |
| Directory | /workspace/61.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/61.xbar_stress_all_with_error.654356973 |
| Short name | T2322 |
| Test name | |
| Test status | |
| Simulation time | 11929832169 ps |
| CPU time | 410.1 seconds |
| Started | Aug 12 06:54:43 PM PDT 24 |
| Finished | Aug 12 07:01:33 PM PDT 24 |
| Peak memory | 576140 kb |
| Host | smart-14e90b93-833e-4a16-ac73-b1536eea0996 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=654356973 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 61.xbar_stress_all_with_error.654356973 |
| Directory | /workspace/61.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/61.xbar_stress_all_with_rand_reset.12855610 |
| Short name | T2104 |
| Test name | |
| Test status | |
| Simulation time | 110718478 ps |
| CPU time | 15.68 seconds |
| Started | Aug 12 06:54:46 PM PDT 24 |
| Finished | Aug 12 06:55:02 PM PDT 24 |
| Peak memory | 575736 kb |
| Host | smart-be4b82e2-a9a9-41db-9187-d12e1d8c4659 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12855610 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_rese t_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 61.xbar_stress_all_w ith_rand_reset.12855610 |
| Directory | /workspace/61.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/61.xbar_stress_all_with_reset_error.1447347555 |
| Short name | T2785 |
| Test name | |
| Test status | |
| Simulation time | 360473762 ps |
| CPU time | 156.47 seconds |
| Started | Aug 12 06:54:48 PM PDT 24 |
| Finished | Aug 12 06:57:24 PM PDT 24 |
| Peak memory | 576488 kb |
| Host | smart-9150dfd5-d789-4d51-9d12-2d121626d807 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1447347555 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 61.xbar_stress_al l_with_reset_error.1447347555 |
| Directory | /workspace/61.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/61.xbar_unmapped_addr.3576404231 |
| Short name | T1551 |
| Test name | |
| Test status | |
| Simulation time | 251896846 ps |
| CPU time | 13.73 seconds |
| Started | Aug 12 06:54:44 PM PDT 24 |
| Finished | Aug 12 06:54:58 PM PDT 24 |
| Peak memory | 575728 kb |
| Host | smart-46c28a14-a475-4f7c-8f47-16884e682a77 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3576404231 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 61.xbar_unmapped_addr.3576404231 |
| Directory | /workspace/61.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/62.xbar_access_same_device.1878056637 |
| Short name | T2196 |
| Test name | |
| Test status | |
| Simulation time | 262052493 ps |
| CPU time | 13.1 seconds |
| Started | Aug 12 06:54:55 PM PDT 24 |
| Finished | Aug 12 06:55:08 PM PDT 24 |
| Peak memory | 573636 kb |
| Host | smart-8c74f640-452d-4329-9c9f-4bbcf80283c0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1878056637 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 62.xbar_access_same_device .1878056637 |
| Directory | /workspace/62.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/62.xbar_access_same_device_slow_rsp.2985733334 |
| Short name | T1804 |
| Test name | |
| Test status | |
| Simulation time | 128051321352 ps |
| CPU time | 2348.5 seconds |
| Started | Aug 12 06:54:52 PM PDT 24 |
| Finished | Aug 12 07:34:01 PM PDT 24 |
| Peak memory | 575852 kb |
| Host | smart-cbbd6a96-4743-45c1-8e06-ab539de0018b |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2985733334 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 62.xbar_access_same_ device_slow_rsp.2985733334 |
| Directory | /workspace/62.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/62.xbar_error_and_unmapped_addr.3808502400 |
| Short name | T2540 |
| Test name | |
| Test status | |
| Simulation time | 927756088 ps |
| CPU time | 34.32 seconds |
| Started | Aug 12 06:54:59 PM PDT 24 |
| Finished | Aug 12 06:55:33 PM PDT 24 |
| Peak memory | 575512 kb |
| Host | smart-e3ca44bc-c327-4317-865d-5f33629cd582 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3808502400 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 62.xbar_error_and_unmapped_add r.3808502400 |
| Directory | /workspace/62.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/62.xbar_error_random.1878647281 |
| Short name | T2665 |
| Test name | |
| Test status | |
| Simulation time | 1115637718 ps |
| CPU time | 35.1 seconds |
| Started | Aug 12 06:54:55 PM PDT 24 |
| Finished | Aug 12 06:55:30 PM PDT 24 |
| Peak memory | 575500 kb |
| Host | smart-20881818-fcf4-4ccd-9901-01082ecec59a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1878647281 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 62.xbar_error_random.1878647281 |
| Directory | /workspace/62.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/62.xbar_random.951497291 |
| Short name | T1664 |
| Test name | |
| Test status | |
| Simulation time | 162988003 ps |
| CPU time | 14.24 seconds |
| Started | Aug 12 06:54:52 PM PDT 24 |
| Finished | Aug 12 06:55:06 PM PDT 24 |
| Peak memory | 575636 kb |
| Host | smart-10a45c5f-816a-4a69-8360-793d0e32356f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=951497291 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 62.xbar_random.951497291 |
| Directory | /workspace/62.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/62.xbar_random_large_delays.2578377427 |
| Short name | T1476 |
| Test name | |
| Test status | |
| Simulation time | 18271464088 ps |
| CPU time | 188.73 seconds |
| Started | Aug 12 06:54:57 PM PDT 24 |
| Finished | Aug 12 06:58:06 PM PDT 24 |
| Peak memory | 575704 kb |
| Host | smart-27cdf66a-1a9e-4b1a-9c83-c107b80b34ee |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2578377427 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 62.xbar_random_large_delays.2578377427 |
| Directory | /workspace/62.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/62.xbar_random_slow_rsp.2717599679 |
| Short name | T2697 |
| Test name | |
| Test status | |
| Simulation time | 52749060798 ps |
| CPU time | 943.44 seconds |
| Started | Aug 12 06:54:53 PM PDT 24 |
| Finished | Aug 12 07:10:36 PM PDT 24 |
| Peak memory | 575604 kb |
| Host | smart-4310b686-6067-42a9-a706-8019490e7284 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2717599679 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 62.xbar_random_slow_rsp.2717599679 |
| Directory | /workspace/62.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/62.xbar_random_zero_delays.4011880547 |
| Short name | T2456 |
| Test name | |
| Test status | |
| Simulation time | 570894594 ps |
| CPU time | 46.07 seconds |
| Started | Aug 12 06:54:53 PM PDT 24 |
| Finished | Aug 12 06:55:39 PM PDT 24 |
| Peak memory | 575776 kb |
| Host | smart-2ee56422-9722-4a3e-b0f0-6ba2213a40da |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4011880547 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 62.xbar_random_zero_del ays.4011880547 |
| Directory | /workspace/62.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/62.xbar_same_source.1599491742 |
| Short name | T1636 |
| Test name | |
| Test status | |
| Simulation time | 1897199186 ps |
| CPU time | 58.62 seconds |
| Started | Aug 12 06:54:53 PM PDT 24 |
| Finished | Aug 12 06:55:52 PM PDT 24 |
| Peak memory | 575576 kb |
| Host | smart-a4ad1f29-9c85-4233-bacd-c8c6713ced76 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1599491742 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 62.xbar_same_source.1599491742 |
| Directory | /workspace/62.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/62.xbar_smoke.738880242 |
| Short name | T2828 |
| Test name | |
| Test status | |
| Simulation time | 36240550 ps |
| CPU time | 5.46 seconds |
| Started | Aug 12 06:54:52 PM PDT 24 |
| Finished | Aug 12 06:54:58 PM PDT 24 |
| Peak memory | 573628 kb |
| Host | smart-92340f9f-7596-450e-81eb-8dd966de2799 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=738880242 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 62.xbar_smoke.738880242 |
| Directory | /workspace/62.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/62.xbar_smoke_large_delays.2615752880 |
| Short name | T1993 |
| Test name | |
| Test status | |
| Simulation time | 9916793426 ps |
| CPU time | 97.02 seconds |
| Started | Aug 12 06:54:59 PM PDT 24 |
| Finished | Aug 12 06:56:36 PM PDT 24 |
| Peak memory | 573656 kb |
| Host | smart-af68f212-57cb-471d-a926-8c13cd0185be |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2615752880 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 62.xbar_smoke_large_delays.2615752880 |
| Directory | /workspace/62.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/62.xbar_smoke_slow_rsp.2134615213 |
| Short name | T1824 |
| Test name | |
| Test status | |
| Simulation time | 5772181397 ps |
| CPU time | 93.54 seconds |
| Started | Aug 12 06:54:55 PM PDT 24 |
| Finished | Aug 12 06:56:29 PM PDT 24 |
| Peak memory | 573676 kb |
| Host | smart-62633a3e-d9a7-4efa-bdd4-da9e190ce79e |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2134615213 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 62.xbar_smoke_slow_rsp.2134615213 |
| Directory | /workspace/62.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/62.xbar_smoke_zero_delays.2295472139 |
| Short name | T2616 |
| Test name | |
| Test status | |
| Simulation time | 48042416 ps |
| CPU time | 5.95 seconds |
| Started | Aug 12 06:54:59 PM PDT 24 |
| Finished | Aug 12 06:55:05 PM PDT 24 |
| Peak memory | 574300 kb |
| Host | smart-c7daf35a-f029-487f-872b-e19422ac2eb8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2295472139 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 62.xbar_smoke_zero_delay s.2295472139 |
| Directory | /workspace/62.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/62.xbar_stress_all.2692877838 |
| Short name | T483 |
| Test name | |
| Test status | |
| Simulation time | 12440724756 ps |
| CPU time | 529.94 seconds |
| Started | Aug 12 06:54:53 PM PDT 24 |
| Finished | Aug 12 07:03:43 PM PDT 24 |
| Peak memory | 575820 kb |
| Host | smart-ac2b8106-4ba7-4ef9-ac6e-880f31455c73 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2692877838 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 62.xbar_stress_all.2692877838 |
| Directory | /workspace/62.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/62.xbar_stress_all_with_error.99871962 |
| Short name | T927 |
| Test name | |
| Test status | |
| Simulation time | 1591542100 ps |
| CPU time | 123.05 seconds |
| Started | Aug 12 06:54:54 PM PDT 24 |
| Finished | Aug 12 06:56:58 PM PDT 24 |
| Peak memory | 575888 kb |
| Host | smart-25ad6807-f43e-4c59-b818-83a38216f1ad |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=99871962 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 62.xbar_stress_all_with_error.99871962 |
| Directory | /workspace/62.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/62.xbar_stress_all_with_reset_error.1078793865 |
| Short name | T2202 |
| Test name | |
| Test status | |
| Simulation time | 6878740390 ps |
| CPU time | 464.08 seconds |
| Started | Aug 12 06:54:58 PM PDT 24 |
| Finished | Aug 12 07:02:42 PM PDT 24 |
| Peak memory | 575760 kb |
| Host | smart-ef7a4eae-5c10-49a5-bc53-72a904576d33 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1078793865 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 62.xbar_stress_al l_with_reset_error.1078793865 |
| Directory | /workspace/62.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/62.xbar_unmapped_addr.1305604092 |
| Short name | T1647 |
| Test name | |
| Test status | |
| Simulation time | 491765485 ps |
| CPU time | 20.81 seconds |
| Started | Aug 12 06:55:00 PM PDT 24 |
| Finished | Aug 12 06:55:20 PM PDT 24 |
| Peak memory | 575684 kb |
| Host | smart-9fb5bf0d-8991-4572-b1bd-f2980380a389 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1305604092 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 62.xbar_unmapped_addr.1305604092 |
| Directory | /workspace/62.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/63.xbar_access_same_device.216808615 |
| Short name | T2742 |
| Test name | |
| Test status | |
| Simulation time | 2941609851 ps |
| CPU time | 131.85 seconds |
| Started | Aug 12 06:55:03 PM PDT 24 |
| Finished | Aug 12 06:57:15 PM PDT 24 |
| Peak memory | 575768 kb |
| Host | smart-07389d55-1575-4a54-abd2-c4b2c2ab24fd |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=216808615 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 63.xbar_access_same_device. 216808615 |
| Directory | /workspace/63.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/63.xbar_access_same_device_slow_rsp.550122465 |
| Short name | T2816 |
| Test name | |
| Test status | |
| Simulation time | 117997210069 ps |
| CPU time | 2266.94 seconds |
| Started | Aug 12 06:55:04 PM PDT 24 |
| Finished | Aug 12 07:32:51 PM PDT 24 |
| Peak memory | 575760 kb |
| Host | smart-e739fe78-1d3c-4817-b377-22dc8ec0b250 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=550122465 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 63.xbar_access_same_d evice_slow_rsp.550122465 |
| Directory | /workspace/63.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/63.xbar_error_and_unmapped_addr.1611702189 |
| Short name | T2441 |
| Test name | |
| Test status | |
| Simulation time | 137448238 ps |
| CPU time | 8.48 seconds |
| Started | Aug 12 06:55:02 PM PDT 24 |
| Finished | Aug 12 06:55:10 PM PDT 24 |
| Peak memory | 573708 kb |
| Host | smart-26add121-5929-4e5a-87e6-f123bf89f48a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1611702189 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 63.xbar_error_and_unmapped_add r.1611702189 |
| Directory | /workspace/63.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/63.xbar_error_random.3615893006 |
| Short name | T2685 |
| Test name | |
| Test status | |
| Simulation time | 503500858 ps |
| CPU time | 39.37 seconds |
| Started | Aug 12 06:55:02 PM PDT 24 |
| Finished | Aug 12 06:55:41 PM PDT 24 |
| Peak memory | 575524 kb |
| Host | smart-9438b0bd-75fe-4399-ae05-96cd82605d9e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3615893006 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 63.xbar_error_random.3615893006 |
| Directory | /workspace/63.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/63.xbar_random.3614207812 |
| Short name | T1813 |
| Test name | |
| Test status | |
| Simulation time | 214534992 ps |
| CPU time | 19.51 seconds |
| Started | Aug 12 06:55:02 PM PDT 24 |
| Finished | Aug 12 06:55:22 PM PDT 24 |
| Peak memory | 575700 kb |
| Host | smart-c115a745-d659-40ef-94ab-1ce8e55a80ed |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3614207812 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 63.xbar_random.3614207812 |
| Directory | /workspace/63.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/63.xbar_random_large_delays.3721030655 |
| Short name | T2013 |
| Test name | |
| Test status | |
| Simulation time | 100380108622 ps |
| CPU time | 1207.89 seconds |
| Started | Aug 12 06:55:02 PM PDT 24 |
| Finished | Aug 12 07:15:10 PM PDT 24 |
| Peak memory | 575824 kb |
| Host | smart-855d14eb-8b71-4cf2-9de5-fc6a072fe081 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3721030655 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 63.xbar_random_large_delays.3721030655 |
| Directory | /workspace/63.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/63.xbar_random_slow_rsp.1975635711 |
| Short name | T704 |
| Test name | |
| Test status | |
| Simulation time | 5484276347 ps |
| CPU time | 89 seconds |
| Started | Aug 12 06:55:03 PM PDT 24 |
| Finished | Aug 12 06:56:32 PM PDT 24 |
| Peak memory | 573716 kb |
| Host | smart-f5efb2ec-5af4-4121-a827-fae27237304f |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1975635711 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 63.xbar_random_slow_rsp.1975635711 |
| Directory | /workspace/63.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/63.xbar_random_zero_delays.587104167 |
| Short name | T671 |
| Test name | |
| Test status | |
| Simulation time | 471760215 ps |
| CPU time | 38.89 seconds |
| Started | Aug 12 06:55:02 PM PDT 24 |
| Finished | Aug 12 06:55:41 PM PDT 24 |
| Peak memory | 575748 kb |
| Host | smart-80997d43-0f9f-4538-9d94-1de91d754001 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=587104167 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 63.xbar_random_zero_dela ys.587104167 |
| Directory | /workspace/63.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/63.xbar_same_source.1515116376 |
| Short name | T2077 |
| Test name | |
| Test status | |
| Simulation time | 2298595997 ps |
| CPU time | 66.57 seconds |
| Started | Aug 12 06:55:02 PM PDT 24 |
| Finished | Aug 12 06:56:08 PM PDT 24 |
| Peak memory | 575640 kb |
| Host | smart-959b61df-e40f-47f4-9c76-237c8e075818 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1515116376 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 63.xbar_same_source.1515116376 |
| Directory | /workspace/63.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/63.xbar_smoke.1493989155 |
| Short name | T2191 |
| Test name | |
| Test status | |
| Simulation time | 233701700 ps |
| CPU time | 9.43 seconds |
| Started | Aug 12 06:54:54 PM PDT 24 |
| Finished | Aug 12 06:55:04 PM PDT 24 |
| Peak memory | 573588 kb |
| Host | smart-18b2089a-5b39-42b0-8b91-1195c976ff41 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1493989155 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 63.xbar_smoke.1493989155 |
| Directory | /workspace/63.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/63.xbar_smoke_large_delays.4141902645 |
| Short name | T2024 |
| Test name | |
| Test status | |
| Simulation time | 9142999227 ps |
| CPU time | 87.7 seconds |
| Started | Aug 12 06:54:54 PM PDT 24 |
| Finished | Aug 12 06:56:22 PM PDT 24 |
| Peak memory | 573616 kb |
| Host | smart-478da062-46cb-4e62-91f7-cfe40410484f |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4141902645 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 63.xbar_smoke_large_delays.4141902645 |
| Directory | /workspace/63.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/63.xbar_smoke_slow_rsp.1602878680 |
| Short name | T1779 |
| Test name | |
| Test status | |
| Simulation time | 4704666850 ps |
| CPU time | 80.74 seconds |
| Started | Aug 12 06:54:59 PM PDT 24 |
| Finished | Aug 12 06:56:20 PM PDT 24 |
| Peak memory | 573648 kb |
| Host | smart-0bfbc529-387c-4369-997a-0fec8ca6a279 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1602878680 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 63.xbar_smoke_slow_rsp.1602878680 |
| Directory | /workspace/63.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/63.xbar_smoke_zero_delays.2171149304 |
| Short name | T1739 |
| Test name | |
| Test status | |
| Simulation time | 47854860 ps |
| CPU time | 6.38 seconds |
| Started | Aug 12 06:54:54 PM PDT 24 |
| Finished | Aug 12 06:55:00 PM PDT 24 |
| Peak memory | 573576 kb |
| Host | smart-2cbd908b-fefc-4485-b6be-18c3e6c02ca2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2171149304 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 63.xbar_smoke_zero_delay s.2171149304 |
| Directory | /workspace/63.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/63.xbar_stress_all.3431266900 |
| Short name | T508 |
| Test name | |
| Test status | |
| Simulation time | 1575345774 ps |
| CPU time | 114.35 seconds |
| Started | Aug 12 06:54:59 PM PDT 24 |
| Finished | Aug 12 06:56:54 PM PDT 24 |
| Peak memory | 575668 kb |
| Host | smart-7fb823fb-0129-40df-8012-7104befdef55 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3431266900 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 63.xbar_stress_all.3431266900 |
| Directory | /workspace/63.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/63.xbar_stress_all_with_error.757385398 |
| Short name | T2356 |
| Test name | |
| Test status | |
| Simulation time | 6017945974 ps |
| CPU time | 204.49 seconds |
| Started | Aug 12 06:55:03 PM PDT 24 |
| Finished | Aug 12 06:58:27 PM PDT 24 |
| Peak memory | 576280 kb |
| Host | smart-9c95be61-77f6-4b6a-b1f9-d4be81945555 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=757385398 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 63.xbar_stress_all_with_error.757385398 |
| Directory | /workspace/63.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/63.xbar_stress_all_with_rand_reset.318816248 |
| Short name | T738 |
| Test name | |
| Test status | |
| Simulation time | 511893761 ps |
| CPU time | 154.98 seconds |
| Started | Aug 12 06:55:09 PM PDT 24 |
| Finished | Aug 12 06:57:44 PM PDT 24 |
| Peak memory | 575768 kb |
| Host | smart-64dc0817-9735-4e1b-a98e-125253582177 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=318816248 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_res et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 63.xbar_stress_all_ with_rand_reset.318816248 |
| Directory | /workspace/63.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/63.xbar_stress_all_with_reset_error.923700659 |
| Short name | T2358 |
| Test name | |
| Test status | |
| Simulation time | 593954711 ps |
| CPU time | 267.57 seconds |
| Started | Aug 12 06:55:06 PM PDT 24 |
| Finished | Aug 12 06:59:34 PM PDT 24 |
| Peak memory | 576536 kb |
| Host | smart-e9c85cad-1a28-4af8-a26a-350b5a188a67 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=923700659 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 63.xbar_stress_all _with_reset_error.923700659 |
| Directory | /workspace/63.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/63.xbar_unmapped_addr.1568520331 |
| Short name | T1596 |
| Test name | |
| Test status | |
| Simulation time | 84081758 ps |
| CPU time | 7 seconds |
| Started | Aug 12 06:55:03 PM PDT 24 |
| Finished | Aug 12 06:55:10 PM PDT 24 |
| Peak memory | 573660 kb |
| Host | smart-e51376f0-07d2-4442-a935-06d36c444737 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1568520331 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 63.xbar_unmapped_addr.1568520331 |
| Directory | /workspace/63.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/64.xbar_access_same_device.2052321103 |
| Short name | T1875 |
| Test name | |
| Test status | |
| Simulation time | 3514597833 ps |
| CPU time | 147.01 seconds |
| Started | Aug 12 06:55:08 PM PDT 24 |
| Finished | Aug 12 06:57:36 PM PDT 24 |
| Peak memory | 575808 kb |
| Host | smart-fc6292c6-db72-495d-8b7e-65239e77cfb2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2052321103 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 64.xbar_access_same_device .2052321103 |
| Directory | /workspace/64.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/64.xbar_access_same_device_slow_rsp.669037123 |
| Short name | T904 |
| Test name | |
| Test status | |
| Simulation time | 19085358654 ps |
| CPU time | 336.55 seconds |
| Started | Aug 12 06:55:02 PM PDT 24 |
| Finished | Aug 12 07:00:39 PM PDT 24 |
| Peak memory | 575612 kb |
| Host | smart-6f9364c5-b113-47ca-bd54-b0a4fab3fbac |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=669037123 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 64.xbar_access_same_d evice_slow_rsp.669037123 |
| Directory | /workspace/64.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/64.xbar_error_and_unmapped_addr.2243211910 |
| Short name | T1662 |
| Test name | |
| Test status | |
| Simulation time | 1155254009 ps |
| CPU time | 45.16 seconds |
| Started | Aug 12 06:55:02 PM PDT 24 |
| Finished | Aug 12 06:55:48 PM PDT 24 |
| Peak memory | 575652 kb |
| Host | smart-6cb27e0c-7e26-4137-984e-183dbd2ef89f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2243211910 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 64.xbar_error_and_unmapped_add r.2243211910 |
| Directory | /workspace/64.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/64.xbar_error_random.3216869126 |
| Short name | T1498 |
| Test name | |
| Test status | |
| Simulation time | 1394068416 ps |
| CPU time | 50.25 seconds |
| Started | Aug 12 06:55:03 PM PDT 24 |
| Finished | Aug 12 06:55:53 PM PDT 24 |
| Peak memory | 575700 kb |
| Host | smart-90576880-ba27-4184-8b99-d303ceb4bb08 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3216869126 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 64.xbar_error_random.3216869126 |
| Directory | /workspace/64.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/64.xbar_random.306205560 |
| Short name | T2295 |
| Test name | |
| Test status | |
| Simulation time | 742263828 ps |
| CPU time | 27.59 seconds |
| Started | Aug 12 06:55:04 PM PDT 24 |
| Finished | Aug 12 06:55:32 PM PDT 24 |
| Peak memory | 575712 kb |
| Host | smart-e20963bf-e63b-42e5-a9f7-c8a945c92a31 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=306205560 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 64.xbar_random.306205560 |
| Directory | /workspace/64.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/64.xbar_random_large_delays.3708743978 |
| Short name | T694 |
| Test name | |
| Test status | |
| Simulation time | 73729477631 ps |
| CPU time | 773.7 seconds |
| Started | Aug 12 06:55:08 PM PDT 24 |
| Finished | Aug 12 07:08:02 PM PDT 24 |
| Peak memory | 575688 kb |
| Host | smart-7519ac1c-c10a-4c94-aa00-88d2c81e920f |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3708743978 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 64.xbar_random_large_delays.3708743978 |
| Directory | /workspace/64.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/64.xbar_random_slow_rsp.4084459795 |
| Short name | T2600 |
| Test name | |
| Test status | |
| Simulation time | 65357486748 ps |
| CPU time | 1108.16 seconds |
| Started | Aug 12 06:55:03 PM PDT 24 |
| Finished | Aug 12 07:13:32 PM PDT 24 |
| Peak memory | 575712 kb |
| Host | smart-ae32fa6a-f926-4a22-9907-b12ccc94f03f |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4084459795 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 64.xbar_random_slow_rsp.4084459795 |
| Directory | /workspace/64.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/64.xbar_random_zero_delays.608256693 |
| Short name | T493 |
| Test name | |
| Test status | |
| Simulation time | 289008141 ps |
| CPU time | 28.22 seconds |
| Started | Aug 12 06:55:01 PM PDT 24 |
| Finished | Aug 12 06:55:29 PM PDT 24 |
| Peak memory | 575552 kb |
| Host | smart-43fdd9ba-4478-4997-946a-1ab3c63cabc3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=608256693 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 64.xbar_random_zero_dela ys.608256693 |
| Directory | /workspace/64.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/64.xbar_same_source.787317304 |
| Short name | T587 |
| Test name | |
| Test status | |
| Simulation time | 176287837 ps |
| CPU time | 16.11 seconds |
| Started | Aug 12 06:55:02 PM PDT 24 |
| Finished | Aug 12 06:55:18 PM PDT 24 |
| Peak memory | 575568 kb |
| Host | smart-8eace785-5838-4706-b886-e1ed20a18b12 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=787317304 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 64.xbar_same_source.787317304 |
| Directory | /workspace/64.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/64.xbar_smoke.3120273347 |
| Short name | T2304 |
| Test name | |
| Test status | |
| Simulation time | 190648662 ps |
| CPU time | 7.91 seconds |
| Started | Aug 12 06:55:08 PM PDT 24 |
| Finished | Aug 12 06:55:16 PM PDT 24 |
| Peak memory | 573596 kb |
| Host | smart-eda80a1b-c41f-4e00-bd32-4238b2e6f269 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3120273347 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 64.xbar_smoke.3120273347 |
| Directory | /workspace/64.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/64.xbar_smoke_large_delays.2842979198 |
| Short name | T2876 |
| Test name | |
| Test status | |
| Simulation time | 9451893651 ps |
| CPU time | 97.27 seconds |
| Started | Aug 12 06:55:00 PM PDT 24 |
| Finished | Aug 12 06:56:38 PM PDT 24 |
| Peak memory | 573768 kb |
| Host | smart-824711f5-833c-48ee-8ddb-a83f561c1bf3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2842979198 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 64.xbar_smoke_large_delays.2842979198 |
| Directory | /workspace/64.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/64.xbar_smoke_slow_rsp.1049682909 |
| Short name | T2391 |
| Test name | |
| Test status | |
| Simulation time | 5325375123 ps |
| CPU time | 87.1 seconds |
| Started | Aug 12 06:55:09 PM PDT 24 |
| Finished | Aug 12 06:56:36 PM PDT 24 |
| Peak memory | 574356 kb |
| Host | smart-2f33cc4a-c038-40ac-8adf-09fe7d1e0475 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1049682909 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 64.xbar_smoke_slow_rsp.1049682909 |
| Directory | /workspace/64.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/64.xbar_smoke_zero_delays.1384970938 |
| Short name | T2357 |
| Test name | |
| Test status | |
| Simulation time | 45319134 ps |
| CPU time | 5.97 seconds |
| Started | Aug 12 06:55:05 PM PDT 24 |
| Finished | Aug 12 06:55:11 PM PDT 24 |
| Peak memory | 573524 kb |
| Host | smart-f4ed279a-64ce-4c89-ad01-09f7cb839c24 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1384970938 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 64.xbar_smoke_zero_delay s.1384970938 |
| Directory | /workspace/64.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/64.xbar_stress_all.3357252735 |
| Short name | T2482 |
| Test name | |
| Test status | |
| Simulation time | 5129217349 ps |
| CPU time | 197.93 seconds |
| Started | Aug 12 06:55:03 PM PDT 24 |
| Finished | Aug 12 06:58:21 PM PDT 24 |
| Peak memory | 576396 kb |
| Host | smart-4d53ee9b-1036-4b6c-8a19-0fa9a52f65a2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3357252735 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 64.xbar_stress_all.3357252735 |
| Directory | /workspace/64.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/64.xbar_stress_all_with_error.3403762995 |
| Short name | T1697 |
| Test name | |
| Test status | |
| Simulation time | 3907915534 ps |
| CPU time | 264.49 seconds |
| Started | Aug 12 06:55:11 PM PDT 24 |
| Finished | Aug 12 06:59:35 PM PDT 24 |
| Peak memory | 575792 kb |
| Host | smart-b5f85c8d-4906-4d6e-af89-09398c377670 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3403762995 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 64.xbar_stress_all_with_error.3403762995 |
| Directory | /workspace/64.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/64.xbar_stress_all_with_rand_reset.345833689 |
| Short name | T573 |
| Test name | |
| Test status | |
| Simulation time | 2309299452 ps |
| CPU time | 264.38 seconds |
| Started | Aug 12 06:55:10 PM PDT 24 |
| Finished | Aug 12 06:59:35 PM PDT 24 |
| Peak memory | 576600 kb |
| Host | smart-01aff5a8-564f-4fd1-895f-223cd5d55f43 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=345833689 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_res et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 64.xbar_stress_all_ with_rand_reset.345833689 |
| Directory | /workspace/64.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/64.xbar_stress_all_with_reset_error.1737828739 |
| Short name | T2838 |
| Test name | |
| Test status | |
| Simulation time | 3189209055 ps |
| CPU time | 305.29 seconds |
| Started | Aug 12 06:55:12 PM PDT 24 |
| Finished | Aug 12 07:00:17 PM PDT 24 |
| Peak memory | 576600 kb |
| Host | smart-7e9d686f-610d-44e3-9984-deda12f8f81c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1737828739 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 64.xbar_stress_al l_with_reset_error.1737828739 |
| Directory | /workspace/64.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/64.xbar_unmapped_addr.3301804563 |
| Short name | T733 |
| Test name | |
| Test status | |
| Simulation time | 232877060 ps |
| CPU time | 25.81 seconds |
| Started | Aug 12 06:55:03 PM PDT 24 |
| Finished | Aug 12 06:55:29 PM PDT 24 |
| Peak memory | 575584 kb |
| Host | smart-328e0307-a336-4148-8291-20aca2e63425 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3301804563 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 64.xbar_unmapped_addr.3301804563 |
| Directory | /workspace/64.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/65.xbar_access_same_device.3217424148 |
| Short name | T2220 |
| Test name | |
| Test status | |
| Simulation time | 1776448784 ps |
| CPU time | 79.55 seconds |
| Started | Aug 12 06:55:14 PM PDT 24 |
| Finished | Aug 12 06:56:33 PM PDT 24 |
| Peak memory | 575628 kb |
| Host | smart-6f721487-c3b5-4a25-adbe-5a806acc587a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3217424148 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 65.xbar_access_same_device .3217424148 |
| Directory | /workspace/65.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/65.xbar_access_same_device_slow_rsp.3692173912 |
| Short name | T897 |
| Test name | |
| Test status | |
| Simulation time | 44536930257 ps |
| CPU time | 794.1 seconds |
| Started | Aug 12 06:55:11 PM PDT 24 |
| Finished | Aug 12 07:08:25 PM PDT 24 |
| Peak memory | 575664 kb |
| Host | smart-6cf465b0-7026-482a-981d-a2b58c9c75e7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3692173912 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 65.xbar_access_same_ device_slow_rsp.3692173912 |
| Directory | /workspace/65.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/65.xbar_error_and_unmapped_addr.2624417802 |
| Short name | T2676 |
| Test name | |
| Test status | |
| Simulation time | 141074398 ps |
| CPU time | 8.99 seconds |
| Started | Aug 12 06:55:16 PM PDT 24 |
| Finished | Aug 12 06:55:25 PM PDT 24 |
| Peak memory | 573708 kb |
| Host | smart-aeb30712-9e6d-46eb-a24e-332413cdbf5d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2624417802 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 65.xbar_error_and_unmapped_add r.2624417802 |
| Directory | /workspace/65.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/65.xbar_error_random.133883517 |
| Short name | T1770 |
| Test name | |
| Test status | |
| Simulation time | 473181526 ps |
| CPU time | 17.75 seconds |
| Started | Aug 12 06:55:17 PM PDT 24 |
| Finished | Aug 12 06:55:35 PM PDT 24 |
| Peak memory | 575752 kb |
| Host | smart-cc879b27-33ee-4f4c-b3fc-c97a7b1c46fe |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=133883517 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 65.xbar_error_random.133883517 |
| Directory | /workspace/65.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/65.xbar_random.2606200905 |
| Short name | T1828 |
| Test name | |
| Test status | |
| Simulation time | 91475499 ps |
| CPU time | 9.87 seconds |
| Started | Aug 12 06:55:15 PM PDT 24 |
| Finished | Aug 12 06:55:25 PM PDT 24 |
| Peak memory | 575484 kb |
| Host | smart-418a963d-7163-47b2-95e7-1807b6194dc2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2606200905 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 65.xbar_random.2606200905 |
| Directory | /workspace/65.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/65.xbar_random_large_delays.1051533763 |
| Short name | T732 |
| Test name | |
| Test status | |
| Simulation time | 22776624983 ps |
| CPU time | 241.46 seconds |
| Started | Aug 12 06:55:15 PM PDT 24 |
| Finished | Aug 12 06:59:17 PM PDT 24 |
| Peak memory | 575592 kb |
| Host | smart-d0792e32-10c7-4a1f-b668-23b551899f5f |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1051533763 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 65.xbar_random_large_delays.1051533763 |
| Directory | /workspace/65.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/65.xbar_random_slow_rsp.873585120 |
| Short name | T2763 |
| Test name | |
| Test status | |
| Simulation time | 52267346490 ps |
| CPU time | 961.4 seconds |
| Started | Aug 12 06:55:13 PM PDT 24 |
| Finished | Aug 12 07:11:14 PM PDT 24 |
| Peak memory | 575776 kb |
| Host | smart-c91ac90a-4eee-44d4-92ed-857be3a91aa3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=873585120 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 65.xbar_random_slow_rsp.873585120 |
| Directory | /workspace/65.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/65.xbar_random_zero_delays.985388016 |
| Short name | T2399 |
| Test name | |
| Test status | |
| Simulation time | 481472499 ps |
| CPU time | 47.28 seconds |
| Started | Aug 12 06:55:12 PM PDT 24 |
| Finished | Aug 12 06:56:00 PM PDT 24 |
| Peak memory | 575708 kb |
| Host | smart-71fbfccd-a603-4df9-8b52-7d50b1e4b7e3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=985388016 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 65.xbar_random_zero_dela ys.985388016 |
| Directory | /workspace/65.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/65.xbar_same_source.1659300688 |
| Short name | T2287 |
| Test name | |
| Test status | |
| Simulation time | 505371415 ps |
| CPU time | 34.7 seconds |
| Started | Aug 12 06:55:11 PM PDT 24 |
| Finished | Aug 12 06:55:46 PM PDT 24 |
| Peak memory | 575556 kb |
| Host | smart-c59d850a-245f-468b-a98f-6cdfdd3ac796 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1659300688 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 65.xbar_same_source.1659300688 |
| Directory | /workspace/65.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/65.xbar_smoke.845659102 |
| Short name | T1978 |
| Test name | |
| Test status | |
| Simulation time | 43968156 ps |
| CPU time | 6.26 seconds |
| Started | Aug 12 06:55:13 PM PDT 24 |
| Finished | Aug 12 06:55:20 PM PDT 24 |
| Peak memory | 574236 kb |
| Host | smart-7d9c915f-3874-4471-b231-7710356cede8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=845659102 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 65.xbar_smoke.845659102 |
| Directory | /workspace/65.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/65.xbar_smoke_large_delays.2146413053 |
| Short name | T633 |
| Test name | |
| Test status | |
| Simulation time | 9211700179 ps |
| CPU time | 93.07 seconds |
| Started | Aug 12 06:55:13 PM PDT 24 |
| Finished | Aug 12 06:56:46 PM PDT 24 |
| Peak memory | 573672 kb |
| Host | smart-98d16615-6e53-441c-9a8d-1de456b2300d |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2146413053 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 65.xbar_smoke_large_delays.2146413053 |
| Directory | /workspace/65.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/65.xbar_smoke_slow_rsp.4071925860 |
| Short name | T1879 |
| Test name | |
| Test status | |
| Simulation time | 4487000312 ps |
| CPU time | 68.79 seconds |
| Started | Aug 12 06:55:12 PM PDT 24 |
| Finished | Aug 12 06:56:21 PM PDT 24 |
| Peak memory | 574352 kb |
| Host | smart-834dd805-e529-4f97-b9e8-0a7c76a30b9d |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4071925860 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 65.xbar_smoke_slow_rsp.4071925860 |
| Directory | /workspace/65.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/65.xbar_smoke_zero_delays.4016672113 |
| Short name | T1901 |
| Test name | |
| Test status | |
| Simulation time | 49361116 ps |
| CPU time | 6.01 seconds |
| Started | Aug 12 06:55:12 PM PDT 24 |
| Finished | Aug 12 06:55:18 PM PDT 24 |
| Peak memory | 574268 kb |
| Host | smart-88adef5b-9660-41e4-ab51-2328cecbf0b9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4016672113 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 65.xbar_smoke_zero_delay s.4016672113 |
| Directory | /workspace/65.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/65.xbar_stress_all.3070509664 |
| Short name | T644 |
| Test name | |
| Test status | |
| Simulation time | 6179794568 ps |
| CPU time | 229.71 seconds |
| Started | Aug 12 06:55:14 PM PDT 24 |
| Finished | Aug 12 06:59:04 PM PDT 24 |
| Peak memory | 575876 kb |
| Host | smart-6c3d56eb-4f87-4516-bb45-c9055fb56db7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3070509664 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 65.xbar_stress_all.3070509664 |
| Directory | /workspace/65.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/65.xbar_stress_all_with_error.3753222860 |
| Short name | T1706 |
| Test name | |
| Test status | |
| Simulation time | 5436113883 ps |
| CPU time | 210.79 seconds |
| Started | Aug 12 06:55:13 PM PDT 24 |
| Finished | Aug 12 06:58:44 PM PDT 24 |
| Peak memory | 575760 kb |
| Host | smart-b6c4a888-eae0-422d-88be-92fb7ee2c397 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3753222860 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 65.xbar_stress_all_with_error.3753222860 |
| Directory | /workspace/65.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/65.xbar_stress_all_with_rand_reset.3564493753 |
| Short name | T2037 |
| Test name | |
| Test status | |
| Simulation time | 273410630 ps |
| CPU time | 42.52 seconds |
| Started | Aug 12 06:55:16 PM PDT 24 |
| Finished | Aug 12 06:55:59 PM PDT 24 |
| Peak memory | 575712 kb |
| Host | smart-d4be8391-514e-466a-aaab-77e6cb88e8e9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3564493753 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 65.xbar_stress_all _with_rand_reset.3564493753 |
| Directory | /workspace/65.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/65.xbar_stress_all_with_reset_error.2959628510 |
| Short name | T2924 |
| Test name | |
| Test status | |
| Simulation time | 2667249471 ps |
| CPU time | 245.92 seconds |
| Started | Aug 12 06:55:12 PM PDT 24 |
| Finished | Aug 12 06:59:18 PM PDT 24 |
| Peak memory | 576624 kb |
| Host | smart-851c98f2-dbc6-47ed-9430-38013b9359d8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2959628510 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 65.xbar_stress_al l_with_reset_error.2959628510 |
| Directory | /workspace/65.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/65.xbar_unmapped_addr.980076262 |
| Short name | T2553 |
| Test name | |
| Test status | |
| Simulation time | 37474212 ps |
| CPU time | 7.15 seconds |
| Started | Aug 12 06:55:14 PM PDT 24 |
| Finished | Aug 12 06:55:22 PM PDT 24 |
| Peak memory | 574364 kb |
| Host | smart-898557bc-5c5d-4ea8-9e91-2f1c00b00914 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=980076262 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 65.xbar_unmapped_addr.980076262 |
| Directory | /workspace/65.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/66.xbar_access_same_device.1895618513 |
| Short name | T1757 |
| Test name | |
| Test status | |
| Simulation time | 752358909 ps |
| CPU time | 64.11 seconds |
| Started | Aug 12 06:55:24 PM PDT 24 |
| Finished | Aug 12 06:56:28 PM PDT 24 |
| Peak memory | 575488 kb |
| Host | smart-9d719dfc-dcd1-4e26-a882-5efa7e8439c1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1895618513 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 66.xbar_access_same_device .1895618513 |
| Directory | /workspace/66.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/66.xbar_access_same_device_slow_rsp.544300293 |
| Short name | T1743 |
| Test name | |
| Test status | |
| Simulation time | 19213071626 ps |
| CPU time | 331.05 seconds |
| Started | Aug 12 06:55:19 PM PDT 24 |
| Finished | Aug 12 07:00:50 PM PDT 24 |
| Peak memory | 575784 kb |
| Host | smart-15b85da7-a2a7-4f27-97d5-4de5dac4665d |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=544300293 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 66.xbar_access_same_d evice_slow_rsp.544300293 |
| Directory | /workspace/66.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/66.xbar_error_and_unmapped_addr.305590244 |
| Short name | T2705 |
| Test name | |
| Test status | |
| Simulation time | 94923040 ps |
| CPU time | 7.35 seconds |
| Started | Aug 12 06:55:20 PM PDT 24 |
| Finished | Aug 12 06:55:27 PM PDT 24 |
| Peak memory | 574220 kb |
| Host | smart-820bb3b5-023d-4e86-92f0-e0418f94c32c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=305590244 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 66.xbar_error_and_unmapped_addr .305590244 |
| Directory | /workspace/66.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/66.xbar_error_random.3038636741 |
| Short name | T1616 |
| Test name | |
| Test status | |
| Simulation time | 285745874 ps |
| CPU time | 25.45 seconds |
| Started | Aug 12 06:55:24 PM PDT 24 |
| Finished | Aug 12 06:55:50 PM PDT 24 |
| Peak memory | 575508 kb |
| Host | smart-cffb9740-15ae-45d3-8ed1-c9bf9787b1df |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3038636741 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 66.xbar_error_random.3038636741 |
| Directory | /workspace/66.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/66.xbar_random.2551460867 |
| Short name | T572 |
| Test name | |
| Test status | |
| Simulation time | 1972624487 ps |
| CPU time | 70.19 seconds |
| Started | Aug 12 06:55:18 PM PDT 24 |
| Finished | Aug 12 06:56:28 PM PDT 24 |
| Peak memory | 575568 kb |
| Host | smart-3e06ee12-3e83-4894-af6c-dfa9423044a1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2551460867 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 66.xbar_random.2551460867 |
| Directory | /workspace/66.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/66.xbar_random_large_delays.699629993 |
| Short name | T452 |
| Test name | |
| Test status | |
| Simulation time | 87923448750 ps |
| CPU time | 889.23 seconds |
| Started | Aug 12 06:55:22 PM PDT 24 |
| Finished | Aug 12 07:10:11 PM PDT 24 |
| Peak memory | 575784 kb |
| Host | smart-edb53e4b-169b-4f50-b914-a863c1cdbf19 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=699629993 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 66.xbar_random_large_delays.699629993 |
| Directory | /workspace/66.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/66.xbar_random_slow_rsp.82829959 |
| Short name | T2142 |
| Test name | |
| Test status | |
| Simulation time | 27041372162 ps |
| CPU time | 476.45 seconds |
| Started | Aug 12 06:55:19 PM PDT 24 |
| Finished | Aug 12 07:03:16 PM PDT 24 |
| Peak memory | 575652 kb |
| Host | smart-620097de-c56a-45a3-8f4c-77717e3784ec |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82829959 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 66.xbar_random_slow_rsp.82829959 |
| Directory | /workspace/66.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/66.xbar_random_zero_delays.2798041969 |
| Short name | T1836 |
| Test name | |
| Test status | |
| Simulation time | 471573728 ps |
| CPU time | 39.24 seconds |
| Started | Aug 12 06:55:20 PM PDT 24 |
| Finished | Aug 12 06:55:59 PM PDT 24 |
| Peak memory | 575556 kb |
| Host | smart-fe20cc8e-98b3-4dc1-a4f3-23d74fafaa18 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2798041969 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 66.xbar_random_zero_del ays.2798041969 |
| Directory | /workspace/66.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/66.xbar_same_source.3973328949 |
| Short name | T2680 |
| Test name | |
| Test status | |
| Simulation time | 105521232 ps |
| CPU time | 9.7 seconds |
| Started | Aug 12 06:55:24 PM PDT 24 |
| Finished | Aug 12 06:55:34 PM PDT 24 |
| Peak memory | 575652 kb |
| Host | smart-92254cf1-e224-49d9-b257-f9d35f2440f2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3973328949 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 66.xbar_same_source.3973328949 |
| Directory | /workspace/66.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/66.xbar_smoke.1679620577 |
| Short name | T1442 |
| Test name | |
| Test status | |
| Simulation time | 201940905 ps |
| CPU time | 8.68 seconds |
| Started | Aug 12 06:55:11 PM PDT 24 |
| Finished | Aug 12 06:55:19 PM PDT 24 |
| Peak memory | 573532 kb |
| Host | smart-b0dc7c4b-4316-4af4-8b31-5e1d0dc804b4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1679620577 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 66.xbar_smoke.1679620577 |
| Directory | /workspace/66.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/66.xbar_smoke_large_delays.3050922464 |
| Short name | T2312 |
| Test name | |
| Test status | |
| Simulation time | 7084332568 ps |
| CPU time | 72.51 seconds |
| Started | Aug 12 06:55:14 PM PDT 24 |
| Finished | Aug 12 06:56:27 PM PDT 24 |
| Peak memory | 573700 kb |
| Host | smart-3521c6e0-b2db-4ea9-ad50-fa6e9555914a |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3050922464 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 66.xbar_smoke_large_delays.3050922464 |
| Directory | /workspace/66.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/66.xbar_smoke_slow_rsp.3182378208 |
| Short name | T2730 |
| Test name | |
| Test status | |
| Simulation time | 4634156668 ps |
| CPU time | 75.01 seconds |
| Started | Aug 12 06:55:19 PM PDT 24 |
| Finished | Aug 12 06:56:34 PM PDT 24 |
| Peak memory | 574324 kb |
| Host | smart-c084b5d9-7a1b-489f-bc4d-708dd1fbc7c9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3182378208 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 66.xbar_smoke_slow_rsp.3182378208 |
| Directory | /workspace/66.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/66.xbar_smoke_zero_delays.3453246381 |
| Short name | T1457 |
| Test name | |
| Test status | |
| Simulation time | 42686531 ps |
| CPU time | 5.9 seconds |
| Started | Aug 12 06:55:11 PM PDT 24 |
| Finished | Aug 12 06:55:17 PM PDT 24 |
| Peak memory | 573632 kb |
| Host | smart-a51ecd56-3719-4e22-83c2-f96e138bcade |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3453246381 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 66.xbar_smoke_zero_delay s.3453246381 |
| Directory | /workspace/66.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/66.xbar_stress_all.3223559011 |
| Short name | T715 |
| Test name | |
| Test status | |
| Simulation time | 11809815504 ps |
| CPU time | 414.8 seconds |
| Started | Aug 12 06:55:18 PM PDT 24 |
| Finished | Aug 12 07:02:13 PM PDT 24 |
| Peak memory | 575964 kb |
| Host | smart-7336a779-21f9-4d9b-86c8-6784348257ca |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3223559011 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 66.xbar_stress_all.3223559011 |
| Directory | /workspace/66.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/66.xbar_stress_all_with_error.193373848 |
| Short name | T554 |
| Test name | |
| Test status | |
| Simulation time | 12546035912 ps |
| CPU time | 394.21 seconds |
| Started | Aug 12 06:55:19 PM PDT 24 |
| Finished | Aug 12 07:01:53 PM PDT 24 |
| Peak memory | 576600 kb |
| Host | smart-076d968b-272d-426a-b288-3387469131ad |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=193373848 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 66.xbar_stress_all_with_error.193373848 |
| Directory | /workspace/66.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/66.xbar_stress_all_with_rand_reset.1696502244 |
| Short name | T2899 |
| Test name | |
| Test status | |
| Simulation time | 14795671198 ps |
| CPU time | 751.18 seconds |
| Started | Aug 12 06:55:22 PM PDT 24 |
| Finished | Aug 12 07:07:54 PM PDT 24 |
| Peak memory | 576592 kb |
| Host | smart-3788cc81-d0a3-4922-8066-606fb176df6b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1696502244 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 66.xbar_stress_all _with_rand_reset.1696502244 |
| Directory | /workspace/66.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/66.xbar_stress_all_with_reset_error.4043213293 |
| Short name | T560 |
| Test name | |
| Test status | |
| Simulation time | 631560713 ps |
| CPU time | 238.33 seconds |
| Started | Aug 12 06:55:20 PM PDT 24 |
| Finished | Aug 12 06:59:18 PM PDT 24 |
| Peak memory | 575716 kb |
| Host | smart-e0611979-e06f-4baa-b551-df79c2831ba7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4043213293 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 66.xbar_stress_al l_with_reset_error.4043213293 |
| Directory | /workspace/66.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/66.xbar_unmapped_addr.2026074906 |
| Short name | T1546 |
| Test name | |
| Test status | |
| Simulation time | 225580269 ps |
| CPU time | 13.98 seconds |
| Started | Aug 12 06:55:20 PM PDT 24 |
| Finished | Aug 12 06:55:34 PM PDT 24 |
| Peak memory | 575536 kb |
| Host | smart-aed9f33e-4952-4254-aefe-098395e5b1d2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2026074906 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 66.xbar_unmapped_addr.2026074906 |
| Directory | /workspace/66.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/67.xbar_access_same_device.2636946486 |
| Short name | T2842 |
| Test name | |
| Test status | |
| Simulation time | 61085424 ps |
| CPU time | 6.83 seconds |
| Started | Aug 12 06:55:29 PM PDT 24 |
| Finished | Aug 12 06:55:36 PM PDT 24 |
| Peak memory | 573708 kb |
| Host | smart-cae3ffcb-d480-4e3a-af42-6b3bb2ebfade |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2636946486 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 67.xbar_access_same_device .2636946486 |
| Directory | /workspace/67.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/67.xbar_access_same_device_slow_rsp.1784931197 |
| Short name | T1870 |
| Test name | |
| Test status | |
| Simulation time | 160288310287 ps |
| CPU time | 2760.92 seconds |
| Started | Aug 12 06:55:30 PM PDT 24 |
| Finished | Aug 12 07:41:32 PM PDT 24 |
| Peak memory | 575776 kb |
| Host | smart-00a042a0-8e62-46fc-8c6d-2e5a0382f8a5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1784931197 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 67.xbar_access_same_ device_slow_rsp.1784931197 |
| Directory | /workspace/67.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/67.xbar_error_and_unmapped_addr.1491485797 |
| Short name | T2057 |
| Test name | |
| Test status | |
| Simulation time | 843848494 ps |
| CPU time | 35 seconds |
| Started | Aug 12 06:55:29 PM PDT 24 |
| Finished | Aug 12 06:56:04 PM PDT 24 |
| Peak memory | 575756 kb |
| Host | smart-3e196a82-8fe0-4987-b7ea-a3a1e15f6a49 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1491485797 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 67.xbar_error_and_unmapped_add r.1491485797 |
| Directory | /workspace/67.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/67.xbar_error_random.79566680 |
| Short name | T1570 |
| Test name | |
| Test status | |
| Simulation time | 2230881920 ps |
| CPU time | 77.21 seconds |
| Started | Aug 12 06:55:30 PM PDT 24 |
| Finished | Aug 12 06:56:47 PM PDT 24 |
| Peak memory | 575780 kb |
| Host | smart-36f98ffa-afa7-4c09-90a5-aaf43c49912e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=79566680 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 67.xbar_error_random.79566680 |
| Directory | /workspace/67.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/67.xbar_random.10729169 |
| Short name | T470 |
| Test name | |
| Test status | |
| Simulation time | 885987981 ps |
| CPU time | 30.63 seconds |
| Started | Aug 12 06:55:31 PM PDT 24 |
| Finished | Aug 12 06:56:02 PM PDT 24 |
| Peak memory | 575516 kb |
| Host | smart-fe8336fa-cb26-42fa-9445-0e96ea982eff |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10729169 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 67.xbar_random.10729169 |
| Directory | /workspace/67.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/67.xbar_random_large_delays.769133931 |
| Short name | T2086 |
| Test name | |
| Test status | |
| Simulation time | 79045233904 ps |
| CPU time | 947.88 seconds |
| Started | Aug 12 06:55:29 PM PDT 24 |
| Finished | Aug 12 07:11:17 PM PDT 24 |
| Peak memory | 575796 kb |
| Host | smart-5b16f1cb-0ec7-49d5-b8a8-276d11c7c6c6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=769133931 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 67.xbar_random_large_delays.769133931 |
| Directory | /workspace/67.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/67.xbar_random_slow_rsp.1147124814 |
| Short name | T2125 |
| Test name | |
| Test status | |
| Simulation time | 29708512564 ps |
| CPU time | 541.36 seconds |
| Started | Aug 12 06:55:29 PM PDT 24 |
| Finished | Aug 12 07:04:31 PM PDT 24 |
| Peak memory | 575728 kb |
| Host | smart-6f2c3ab6-7e83-4672-abf9-9fc9d29cc3cd |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1147124814 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 67.xbar_random_slow_rsp.1147124814 |
| Directory | /workspace/67.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/67.xbar_random_zero_delays.4192521233 |
| Short name | T2808 |
| Test name | |
| Test status | |
| Simulation time | 135826906 ps |
| CPU time | 14.25 seconds |
| Started | Aug 12 06:55:29 PM PDT 24 |
| Finished | Aug 12 06:55:43 PM PDT 24 |
| Peak memory | 575680 kb |
| Host | smart-5b67d674-4114-4ada-aed2-29eeb6240264 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4192521233 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 67.xbar_random_zero_del ays.4192521233 |
| Directory | /workspace/67.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/67.xbar_same_source.2194588297 |
| Short name | T2911 |
| Test name | |
| Test status | |
| Simulation time | 1064897590 ps |
| CPU time | 30.41 seconds |
| Started | Aug 12 06:55:30 PM PDT 24 |
| Finished | Aug 12 06:56:01 PM PDT 24 |
| Peak memory | 575584 kb |
| Host | smart-c5fae858-db0a-47eb-9a83-1f926eff0716 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2194588297 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 67.xbar_same_source.2194588297 |
| Directory | /workspace/67.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/67.xbar_smoke.3446531944 |
| Short name | T2073 |
| Test name | |
| Test status | |
| Simulation time | 175984869 ps |
| CPU time | 9.08 seconds |
| Started | Aug 12 06:55:30 PM PDT 24 |
| Finished | Aug 12 06:55:39 PM PDT 24 |
| Peak memory | 573572 kb |
| Host | smart-c6331d1f-77ab-4c88-a824-a45f08c01f08 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3446531944 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 67.xbar_smoke.3446531944 |
| Directory | /workspace/67.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/67.xbar_smoke_large_delays.932741668 |
| Short name | T1912 |
| Test name | |
| Test status | |
| Simulation time | 7273952980 ps |
| CPU time | 70.68 seconds |
| Started | Aug 12 06:55:29 PM PDT 24 |
| Finished | Aug 12 06:56:40 PM PDT 24 |
| Peak memory | 574356 kb |
| Host | smart-8dea5bd7-6449-4461-88f9-efc7b5bbcd5f |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=932741668 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 67.xbar_smoke_large_delays.932741668 |
| Directory | /workspace/67.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/67.xbar_smoke_slow_rsp.2435497085 |
| Short name | T2135 |
| Test name | |
| Test status | |
| Simulation time | 4749675462 ps |
| CPU time | 78.86 seconds |
| Started | Aug 12 06:55:29 PM PDT 24 |
| Finished | Aug 12 06:56:48 PM PDT 24 |
| Peak memory | 573632 kb |
| Host | smart-d75dc445-4633-4e1b-a531-a17171954b9a |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2435497085 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 67.xbar_smoke_slow_rsp.2435497085 |
| Directory | /workspace/67.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/67.xbar_smoke_zero_delays.3674251609 |
| Short name | T1611 |
| Test name | |
| Test status | |
| Simulation time | 39334459 ps |
| CPU time | 5.68 seconds |
| Started | Aug 12 06:55:29 PM PDT 24 |
| Finished | Aug 12 06:55:34 PM PDT 24 |
| Peak memory | 573524 kb |
| Host | smart-5ad7eedc-0ea0-4c8b-bce7-f663a2df87b2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3674251609 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 67.xbar_smoke_zero_delay s.3674251609 |
| Directory | /workspace/67.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/67.xbar_stress_all.2013385031 |
| Short name | T2352 |
| Test name | |
| Test status | |
| Simulation time | 1899934532 ps |
| CPU time | 170.37 seconds |
| Started | Aug 12 06:55:29 PM PDT 24 |
| Finished | Aug 12 06:58:20 PM PDT 24 |
| Peak memory | 575784 kb |
| Host | smart-ed2d5e84-85f3-4662-aef0-88bad7df5efc |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2013385031 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 67.xbar_stress_all.2013385031 |
| Directory | /workspace/67.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/67.xbar_stress_all_with_error.2790070615 |
| Short name | T1625 |
| Test name | |
| Test status | |
| Simulation time | 11630970194 ps |
| CPU time | 409.34 seconds |
| Started | Aug 12 06:55:29 PM PDT 24 |
| Finished | Aug 12 07:02:19 PM PDT 24 |
| Peak memory | 576548 kb |
| Host | smart-88475848-8a0d-4f4b-813a-bba8a2f08fff |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2790070615 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 67.xbar_stress_all_with_error.2790070615 |
| Directory | /workspace/67.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/67.xbar_stress_all_with_rand_reset.1607992811 |
| Short name | T1472 |
| Test name | |
| Test status | |
| Simulation time | 97013004 ps |
| CPU time | 20.54 seconds |
| Started | Aug 12 06:55:30 PM PDT 24 |
| Finished | Aug 12 06:55:50 PM PDT 24 |
| Peak memory | 573992 kb |
| Host | smart-58b08e9d-2c84-4a0c-8357-1a4b8705347e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1607992811 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 67.xbar_stress_all _with_rand_reset.1607992811 |
| Directory | /workspace/67.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/67.xbar_stress_all_with_reset_error.1525256335 |
| Short name | T1798 |
| Test name | |
| Test status | |
| Simulation time | 6223025812 ps |
| CPU time | 462.35 seconds |
| Started | Aug 12 06:55:31 PM PDT 24 |
| Finished | Aug 12 07:03:14 PM PDT 24 |
| Peak memory | 575828 kb |
| Host | smart-4996f2d6-0c85-4cc6-9bef-90644529648a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1525256335 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 67.xbar_stress_al l_with_reset_error.1525256335 |
| Directory | /workspace/67.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/67.xbar_unmapped_addr.751510825 |
| Short name | T2819 |
| Test name | |
| Test status | |
| Simulation time | 1099672733 ps |
| CPU time | 44.84 seconds |
| Started | Aug 12 06:55:31 PM PDT 24 |
| Finished | Aug 12 06:56:16 PM PDT 24 |
| Peak memory | 575740 kb |
| Host | smart-6e5a2c62-927c-4f51-b4e0-15e9dd1e60b2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=751510825 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 67.xbar_unmapped_addr.751510825 |
| Directory | /workspace/67.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/68.xbar_access_same_device.3641845402 |
| Short name | T2338 |
| Test name | |
| Test status | |
| Simulation time | 1295471741 ps |
| CPU time | 49.87 seconds |
| Started | Aug 12 06:55:39 PM PDT 24 |
| Finished | Aug 12 06:56:29 PM PDT 24 |
| Peak memory | 575500 kb |
| Host | smart-88156f1d-8383-4e6e-a0ee-005f32f021e8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3641845402 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 68.xbar_access_same_device .3641845402 |
| Directory | /workspace/68.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/68.xbar_access_same_device_slow_rsp.3015361185 |
| Short name | T2854 |
| Test name | |
| Test status | |
| Simulation time | 133113660430 ps |
| CPU time | 2489.32 seconds |
| Started | Aug 12 06:55:39 PM PDT 24 |
| Finished | Aug 12 07:37:09 PM PDT 24 |
| Peak memory | 575908 kb |
| Host | smart-ccca4954-a6fa-43c6-8836-d09bae8bc8a7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3015361185 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 68.xbar_access_same_ device_slow_rsp.3015361185 |
| Directory | /workspace/68.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/68.xbar_error_and_unmapped_addr.2809644462 |
| Short name | T2560 |
| Test name | |
| Test status | |
| Simulation time | 290716272 ps |
| CPU time | 34.21 seconds |
| Started | Aug 12 06:55:38 PM PDT 24 |
| Finished | Aug 12 06:56:13 PM PDT 24 |
| Peak memory | 575744 kb |
| Host | smart-c2321ec0-3049-4bb6-8093-f87c37bfbc32 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2809644462 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 68.xbar_error_and_unmapped_add r.2809644462 |
| Directory | /workspace/68.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/68.xbar_error_random.2515335149 |
| Short name | T2331 |
| Test name | |
| Test status | |
| Simulation time | 128402001 ps |
| CPU time | 12.97 seconds |
| Started | Aug 12 06:55:39 PM PDT 24 |
| Finished | Aug 12 06:55:52 PM PDT 24 |
| Peak memory | 575488 kb |
| Host | smart-97d43b55-c1fc-4714-bfc0-935ad44fbd11 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2515335149 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 68.xbar_error_random.2515335149 |
| Directory | /workspace/68.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/68.xbar_random.2642555678 |
| Short name | T2668 |
| Test name | |
| Test status | |
| Simulation time | 627641121 ps |
| CPU time | 51.19 seconds |
| Started | Aug 12 06:55:36 PM PDT 24 |
| Finished | Aug 12 06:56:28 PM PDT 24 |
| Peak memory | 575720 kb |
| Host | smart-ae99d2b3-13b0-4ee4-a272-881c2c56bea4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2642555678 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 68.xbar_random.2642555678 |
| Directory | /workspace/68.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/68.xbar_random_large_delays.600324217 |
| Short name | T1750 |
| Test name | |
| Test status | |
| Simulation time | 13053186848 ps |
| CPU time | 129.99 seconds |
| Started | Aug 12 06:55:43 PM PDT 24 |
| Finished | Aug 12 06:57:53 PM PDT 24 |
| Peak memory | 575772 kb |
| Host | smart-4d2fa274-4a07-4e7a-9323-d69ea1ff0815 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=600324217 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 68.xbar_random_large_delays.600324217 |
| Directory | /workspace/68.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/68.xbar_random_slow_rsp.3203641206 |
| Short name | T2150 |
| Test name | |
| Test status | |
| Simulation time | 25195539300 ps |
| CPU time | 474.79 seconds |
| Started | Aug 12 06:55:39 PM PDT 24 |
| Finished | Aug 12 07:03:33 PM PDT 24 |
| Peak memory | 575760 kb |
| Host | smart-5f4e0fda-53ec-48fd-ab64-f783f1bf0898 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3203641206 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 68.xbar_random_slow_rsp.3203641206 |
| Directory | /workspace/68.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/68.xbar_random_zero_delays.2413927008 |
| Short name | T2070 |
| Test name | |
| Test status | |
| Simulation time | 537761807 ps |
| CPU time | 41.1 seconds |
| Started | Aug 12 06:55:40 PM PDT 24 |
| Finished | Aug 12 06:56:22 PM PDT 24 |
| Peak memory | 575588 kb |
| Host | smart-4d2a2ac7-b04b-4a3d-bb00-473d73e7bcaa |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2413927008 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 68.xbar_random_zero_del ays.2413927008 |
| Directory | /workspace/68.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/68.xbar_same_source.1590031005 |
| Short name | T1759 |
| Test name | |
| Test status | |
| Simulation time | 158753040 ps |
| CPU time | 12.01 seconds |
| Started | Aug 12 06:55:39 PM PDT 24 |
| Finished | Aug 12 06:55:51 PM PDT 24 |
| Peak memory | 575744 kb |
| Host | smart-e330a5ed-de59-4ec7-93db-9181d2cfc018 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1590031005 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 68.xbar_same_source.1590031005 |
| Directory | /workspace/68.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/68.xbar_smoke.3214274841 |
| Short name | T1905 |
| Test name | |
| Test status | |
| Simulation time | 245613693 ps |
| CPU time | 10.04 seconds |
| Started | Aug 12 06:55:28 PM PDT 24 |
| Finished | Aug 12 06:55:39 PM PDT 24 |
| Peak memory | 573536 kb |
| Host | smart-9ac8d115-6c68-4f0d-b7a5-4b3670f7114d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3214274841 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 68.xbar_smoke.3214274841 |
| Directory | /workspace/68.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/68.xbar_smoke_large_delays.3054245500 |
| Short name | T2271 |
| Test name | |
| Test status | |
| Simulation time | 6652101864 ps |
| CPU time | 67.81 seconds |
| Started | Aug 12 06:55:39 PM PDT 24 |
| Finished | Aug 12 06:56:47 PM PDT 24 |
| Peak memory | 574384 kb |
| Host | smart-10e1fe3c-2397-48a7-a9ac-967b5e5f802f |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3054245500 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 68.xbar_smoke_large_delays.3054245500 |
| Directory | /workspace/68.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/68.xbar_smoke_slow_rsp.1271976101 |
| Short name | T1553 |
| Test name | |
| Test status | |
| Simulation time | 3215639423 ps |
| CPU time | 55.54 seconds |
| Started | Aug 12 06:55:39 PM PDT 24 |
| Finished | Aug 12 06:56:35 PM PDT 24 |
| Peak memory | 573676 kb |
| Host | smart-c2547118-8e3d-4490-ac3f-0a599af158e9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1271976101 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 68.xbar_smoke_slow_rsp.1271976101 |
| Directory | /workspace/68.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/68.xbar_smoke_zero_delays.589199753 |
| Short name | T1880 |
| Test name | |
| Test status | |
| Simulation time | 56999534 ps |
| CPU time | 6.84 seconds |
| Started | Aug 12 06:55:38 PM PDT 24 |
| Finished | Aug 12 06:55:45 PM PDT 24 |
| Peak memory | 573564 kb |
| Host | smart-b9aaf667-7316-43c3-b368-14d194955fcb |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=589199753 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 68.xbar_smoke_zero_delays .589199753 |
| Directory | /workspace/68.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/68.xbar_stress_all.2128826198 |
| Short name | T2090 |
| Test name | |
| Test status | |
| Simulation time | 3214735501 ps |
| CPU time | 261.94 seconds |
| Started | Aug 12 06:55:38 PM PDT 24 |
| Finished | Aug 12 07:00:00 PM PDT 24 |
| Peak memory | 575824 kb |
| Host | smart-3665966b-5ddf-466c-9054-347ba5d35d14 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2128826198 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 68.xbar_stress_all.2128826198 |
| Directory | /workspace/68.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/68.xbar_stress_all_with_error.3098296161 |
| Short name | T1519 |
| Test name | |
| Test status | |
| Simulation time | 8708005002 ps |
| CPU time | 298.01 seconds |
| Started | Aug 12 06:55:38 PM PDT 24 |
| Finished | Aug 12 07:00:36 PM PDT 24 |
| Peak memory | 575876 kb |
| Host | smart-18d743a3-3588-48b2-8114-0765f6cbd6db |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3098296161 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 68.xbar_stress_all_with_error.3098296161 |
| Directory | /workspace/68.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/68.xbar_stress_all_with_rand_reset.3701304901 |
| Short name | T963 |
| Test name | |
| Test status | |
| Simulation time | 106084644 ps |
| CPU time | 56.79 seconds |
| Started | Aug 12 06:55:42 PM PDT 24 |
| Finished | Aug 12 06:56:39 PM PDT 24 |
| Peak memory | 575720 kb |
| Host | smart-44e50786-9318-45af-a9f0-fa798c44692b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3701304901 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 68.xbar_stress_all _with_rand_reset.3701304901 |
| Directory | /workspace/68.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/68.xbar_stress_all_with_reset_error.3444883605 |
| Short name | T2910 |
| Test name | |
| Test status | |
| Simulation time | 2807428248 ps |
| CPU time | 293.55 seconds |
| Started | Aug 12 06:55:39 PM PDT 24 |
| Finished | Aug 12 07:00:33 PM PDT 24 |
| Peak memory | 576628 kb |
| Host | smart-c8df75b6-5373-4e7c-9b03-d8eac69cf3cb |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3444883605 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 68.xbar_stress_al l_with_reset_error.3444883605 |
| Directory | /workspace/68.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/68.xbar_unmapped_addr.2367397440 |
| Short name | T1660 |
| Test name | |
| Test status | |
| Simulation time | 481773429 ps |
| CPU time | 19.14 seconds |
| Started | Aug 12 06:55:43 PM PDT 24 |
| Finished | Aug 12 06:56:03 PM PDT 24 |
| Peak memory | 575716 kb |
| Host | smart-7e7f3741-634d-4a7a-9141-1d92f59f5486 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2367397440 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 68.xbar_unmapped_addr.2367397440 |
| Directory | /workspace/68.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/69.xbar_access_same_device.1284621393 |
| Short name | T1561 |
| Test name | |
| Test status | |
| Simulation time | 653338777 ps |
| CPU time | 54.99 seconds |
| Started | Aug 12 06:55:48 PM PDT 24 |
| Finished | Aug 12 06:56:43 PM PDT 24 |
| Peak memory | 575784 kb |
| Host | smart-b75d78fc-b136-49a9-852e-cdb135bd717f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1284621393 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 69.xbar_access_same_device .1284621393 |
| Directory | /workspace/69.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/69.xbar_access_same_device_slow_rsp.2121638991 |
| Short name | T2535 |
| Test name | |
| Test status | |
| Simulation time | 47568566488 ps |
| CPU time | 834.02 seconds |
| Started | Aug 12 06:55:48 PM PDT 24 |
| Finished | Aug 12 07:09:42 PM PDT 24 |
| Peak memory | 575820 kb |
| Host | smart-8d9a45f2-7493-40e2-a111-d0a1ceb34f47 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2121638991 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 69.xbar_access_same_ device_slow_rsp.2121638991 |
| Directory | /workspace/69.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/69.xbar_error_and_unmapped_addr.3726517677 |
| Short name | T2555 |
| Test name | |
| Test status | |
| Simulation time | 577548693 ps |
| CPU time | 25.33 seconds |
| Started | Aug 12 06:55:48 PM PDT 24 |
| Finished | Aug 12 06:56:13 PM PDT 24 |
| Peak memory | 575748 kb |
| Host | smart-d040f56c-0a98-49cc-adc0-d261b390d6cb |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3726517677 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 69.xbar_error_and_unmapped_add r.3726517677 |
| Directory | /workspace/69.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/69.xbar_error_random.832680832 |
| Short name | T1963 |
| Test name | |
| Test status | |
| Simulation time | 1969973728 ps |
| CPU time | 72.29 seconds |
| Started | Aug 12 06:55:56 PM PDT 24 |
| Finished | Aug 12 06:57:08 PM PDT 24 |
| Peak memory | 575808 kb |
| Host | smart-fa33b3d5-1823-4e79-bd87-98154f76df5b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=832680832 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 69.xbar_error_random.832680832 |
| Directory | /workspace/69.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/69.xbar_random.4282904474 |
| Short name | T2223 |
| Test name | |
| Test status | |
| Simulation time | 915072168 ps |
| CPU time | 37.09 seconds |
| Started | Aug 12 06:55:42 PM PDT 24 |
| Finished | Aug 12 06:56:19 PM PDT 24 |
| Peak memory | 575692 kb |
| Host | smart-9cf85a7d-3a47-4d7d-9ee4-720e7ef5133a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4282904474 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 69.xbar_random.4282904474 |
| Directory | /workspace/69.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/69.xbar_random_large_delays.3268002551 |
| Short name | T1716 |
| Test name | |
| Test status | |
| Simulation time | 6866238285 ps |
| CPU time | 69.01 seconds |
| Started | Aug 12 06:55:40 PM PDT 24 |
| Finished | Aug 12 06:56:49 PM PDT 24 |
| Peak memory | 573624 kb |
| Host | smart-440f45da-a2c8-4ba2-ab42-ff6018466670 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3268002551 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 69.xbar_random_large_delays.3268002551 |
| Directory | /workspace/69.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/69.xbar_random_slow_rsp.527693180 |
| Short name | T2564 |
| Test name | |
| Test status | |
| Simulation time | 59183608730 ps |
| CPU time | 1062.9 seconds |
| Started | Aug 12 06:55:52 PM PDT 24 |
| Finished | Aug 12 07:13:35 PM PDT 24 |
| Peak memory | 575716 kb |
| Host | smart-a03e2a74-005c-4b97-bf5a-f034243d3346 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=527693180 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 69.xbar_random_slow_rsp.527693180 |
| Directory | /workspace/69.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/69.xbar_random_zero_delays.605535103 |
| Short name | T695 |
| Test name | |
| Test status | |
| Simulation time | 96740933 ps |
| CPU time | 10.41 seconds |
| Started | Aug 12 06:55:42 PM PDT 24 |
| Finished | Aug 12 06:55:53 PM PDT 24 |
| Peak memory | 575684 kb |
| Host | smart-eebe938f-7137-4eb1-875e-95bb4b7e32fe |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=605535103 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 69.xbar_random_zero_dela ys.605535103 |
| Directory | /workspace/69.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/69.xbar_same_source.2575902516 |
| Short name | T1559 |
| Test name | |
| Test status | |
| Simulation time | 689894022 ps |
| CPU time | 21.8 seconds |
| Started | Aug 12 06:55:48 PM PDT 24 |
| Finished | Aug 12 06:56:10 PM PDT 24 |
| Peak memory | 575536 kb |
| Host | smart-08c7aee6-e28b-41b6-8408-0713757cdcac |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2575902516 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 69.xbar_same_source.2575902516 |
| Directory | /workspace/69.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/69.xbar_smoke.1421331637 |
| Short name | T2586 |
| Test name | |
| Test status | |
| Simulation time | 53281858 ps |
| CPU time | 7.18 seconds |
| Started | Aug 12 06:55:39 PM PDT 24 |
| Finished | Aug 12 06:55:47 PM PDT 24 |
| Peak memory | 573532 kb |
| Host | smart-f1c360ed-c9d1-4289-a873-943f8837459b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1421331637 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 69.xbar_smoke.1421331637 |
| Directory | /workspace/69.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/69.xbar_smoke_large_delays.320406079 |
| Short name | T2593 |
| Test name | |
| Test status | |
| Simulation time | 8809880098 ps |
| CPU time | 90.81 seconds |
| Started | Aug 12 06:55:38 PM PDT 24 |
| Finished | Aug 12 06:57:09 PM PDT 24 |
| Peak memory | 573684 kb |
| Host | smart-68e77a72-cf64-48dc-afab-0e384cb4d8b2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=320406079 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 69.xbar_smoke_large_delays.320406079 |
| Directory | /workspace/69.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/69.xbar_smoke_slow_rsp.1461446256 |
| Short name | T1687 |
| Test name | |
| Test status | |
| Simulation time | 6225175294 ps |
| CPU time | 98.8 seconds |
| Started | Aug 12 06:55:41 PM PDT 24 |
| Finished | Aug 12 06:57:20 PM PDT 24 |
| Peak memory | 573700 kb |
| Host | smart-805612e9-4a8c-4301-94eb-322652035852 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1461446256 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 69.xbar_smoke_slow_rsp.1461446256 |
| Directory | /workspace/69.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/69.xbar_smoke_zero_delays.250918281 |
| Short name | T2904 |
| Test name | |
| Test status | |
| Simulation time | 48833941 ps |
| CPU time | 6.22 seconds |
| Started | Aug 12 06:55:39 PM PDT 24 |
| Finished | Aug 12 06:55:46 PM PDT 24 |
| Peak memory | 573616 kb |
| Host | smart-2f51c279-c8db-4384-adf5-aa443bed7e48 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=250918281 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 69.xbar_smoke_zero_delays .250918281 |
| Directory | /workspace/69.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/69.xbar_stress_all.925417459 |
| Short name | T2517 |
| Test name | |
| Test status | |
| Simulation time | 5816724063 ps |
| CPU time | 211.75 seconds |
| Started | Aug 12 06:55:50 PM PDT 24 |
| Finished | Aug 12 06:59:21 PM PDT 24 |
| Peak memory | 576220 kb |
| Host | smart-4d0df9f6-dbd8-4199-bf64-1457ce6c6268 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=925417459 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 69.xbar_stress_all.925417459 |
| Directory | /workspace/69.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/69.xbar_stress_all_with_error.2390545270 |
| Short name | T1526 |
| Test name | |
| Test status | |
| Simulation time | 1018796936 ps |
| CPU time | 67.61 seconds |
| Started | Aug 12 06:55:49 PM PDT 24 |
| Finished | Aug 12 06:56:57 PM PDT 24 |
| Peak memory | 575524 kb |
| Host | smart-8b3f9be6-f775-4287-9260-ddda5b7aaba6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2390545270 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 69.xbar_stress_all_with_error.2390545270 |
| Directory | /workspace/69.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/69.xbar_stress_all_with_rand_reset.2552240425 |
| Short name | T613 |
| Test name | |
| Test status | |
| Simulation time | 10675621729 ps |
| CPU time | 549.38 seconds |
| Started | Aug 12 06:55:54 PM PDT 24 |
| Finished | Aug 12 07:05:04 PM PDT 24 |
| Peak memory | 575816 kb |
| Host | smart-30835998-4f1b-4f3d-b93d-cd15b0236eef |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2552240425 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 69.xbar_stress_all _with_rand_reset.2552240425 |
| Directory | /workspace/69.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/69.xbar_stress_all_with_reset_error.2106892832 |
| Short name | T2925 |
| Test name | |
| Test status | |
| Simulation time | 175554643 ps |
| CPU time | 33.44 seconds |
| Started | Aug 12 06:55:55 PM PDT 24 |
| Finished | Aug 12 06:56:28 PM PDT 24 |
| Peak memory | 575920 kb |
| Host | smart-017f8309-6ede-44bb-aabb-8c5728038da2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2106892832 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 69.xbar_stress_al l_with_reset_error.2106892832 |
| Directory | /workspace/69.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/69.xbar_unmapped_addr.658378814 |
| Short name | T2274 |
| Test name | |
| Test status | |
| Simulation time | 267470242 ps |
| CPU time | 32.59 seconds |
| Started | Aug 12 06:55:52 PM PDT 24 |
| Finished | Aug 12 06:56:24 PM PDT 24 |
| Peak memory | 575724 kb |
| Host | smart-bfbfa084-591a-4cad-af99-4c2fa6679f47 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=658378814 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 69.xbar_unmapped_addr.658378814 |
| Directory | /workspace/69.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/7.chip_csr_rw.3760761012 |
| Short name | T2702 |
| Test name | |
| Test status | |
| Simulation time | 5956001740 ps |
| CPU time | 505.43 seconds |
| Started | Aug 12 06:47:29 PM PDT 24 |
| Finished | Aug 12 06:55:55 PM PDT 24 |
| Peak memory | 598192 kb |
| Host | smart-a0b4c776-679f-4d46-b879-9661f7f1dba5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3760761012 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.chip_csr_rw.3760761012 |
| Directory | /workspace/7.chip_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/7.chip_tl_errors.2964995095 |
| Short name | T773 |
| Test name | |
| Test status | |
| Simulation time | 3129740160 ps |
| CPU time | 216.77 seconds |
| Started | Aug 12 06:47:33 PM PDT 24 |
| Finished | Aug 12 06:51:10 PM PDT 24 |
| Peak memory | 599288 kb |
| Host | smart-6d237ca3-ad7f-4556-9263-d96eea363f3a |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2964995095 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.chip_tl_errors.2964995095 |
| Directory | /workspace/7.chip_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/7.xbar_access_same_device.260694434 |
| Short name | T565 |
| Test name | |
| Test status | |
| Simulation time | 1991141967 ps |
| CPU time | 70.37 seconds |
| Started | Aug 12 06:47:31 PM PDT 24 |
| Finished | Aug 12 06:48:41 PM PDT 24 |
| Peak memory | 575656 kb |
| Host | smart-a72951a0-1e6e-420b-9773-60d3abc79472 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=260694434 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.xbar_access_same_device.260694434 |
| Directory | /workspace/7.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/7.xbar_access_same_device_slow_rsp.3705009619 |
| Short name | T1971 |
| Test name | |
| Test status | |
| Simulation time | 72277180688 ps |
| CPU time | 1161.1 seconds |
| Started | Aug 12 06:47:42 PM PDT 24 |
| Finished | Aug 12 07:07:04 PM PDT 24 |
| Peak memory | 575776 kb |
| Host | smart-d83a9d26-60fb-48e4-859b-de592b3f6d2f |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3705009619 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.xbar_access_same_d evice_slow_rsp.3705009619 |
| Directory | /workspace/7.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/7.xbar_error_and_unmapped_addr.861872732 |
| Short name | T2339 |
| Test name | |
| Test status | |
| Simulation time | 630516777 ps |
| CPU time | 21.88 seconds |
| Started | Aug 12 06:47:40 PM PDT 24 |
| Finished | Aug 12 06:48:02 PM PDT 24 |
| Peak memory | 575756 kb |
| Host | smart-275b0202-23f1-4d72-b783-d80c3ce948cd |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=861872732 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.xbar_error_and_unmapped_addr. 861872732 |
| Directory | /workspace/7.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/7.xbar_error_random.4048833368 |
| Short name | T1992 |
| Test name | |
| Test status | |
| Simulation time | 1025734884 ps |
| CPU time | 35.6 seconds |
| Started | Aug 12 06:47:35 PM PDT 24 |
| Finished | Aug 12 06:48:11 PM PDT 24 |
| Peak memory | 575692 kb |
| Host | smart-c9577781-42f8-42c0-9997-6341248f6a60 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4048833368 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.xbar_error_random.4048833368 |
| Directory | /workspace/7.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/7.xbar_random.2462881023 |
| Short name | T2192 |
| Test name | |
| Test status | |
| Simulation time | 1956781003 ps |
| CPU time | 66.79 seconds |
| Started | Aug 12 06:47:35 PM PDT 24 |
| Finished | Aug 12 06:48:42 PM PDT 24 |
| Peak memory | 575552 kb |
| Host | smart-b9c23fde-afe1-4367-b894-8b946d500872 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2462881023 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.xbar_random.2462881023 |
| Directory | /workspace/7.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/7.xbar_random_large_delays.3339476557 |
| Short name | T615 |
| Test name | |
| Test status | |
| Simulation time | 23110075140 ps |
| CPU time | 247.92 seconds |
| Started | Aug 12 06:47:30 PM PDT 24 |
| Finished | Aug 12 06:51:38 PM PDT 24 |
| Peak memory | 575820 kb |
| Host | smart-70da21c5-3515-4080-8667-c5681fc1a66c |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3339476557 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.xbar_random_large_delays.3339476557 |
| Directory | /workspace/7.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/7.xbar_random_slow_rsp.1904493190 |
| Short name | T1540 |
| Test name | |
| Test status | |
| Simulation time | 9938441923 ps |
| CPU time | 166.85 seconds |
| Started | Aug 12 06:47:33 PM PDT 24 |
| Finished | Aug 12 06:50:20 PM PDT 24 |
| Peak memory | 575664 kb |
| Host | smart-c04b70ea-37fe-4a36-b697-1119bff8dff9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1904493190 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.xbar_random_slow_rsp.1904493190 |
| Directory | /workspace/7.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/7.xbar_random_zero_delays.1019508958 |
| Short name | T1997 |
| Test name | |
| Test status | |
| Simulation time | 67269357 ps |
| CPU time | 7.97 seconds |
| Started | Aug 12 06:47:55 PM PDT 24 |
| Finished | Aug 12 06:48:03 PM PDT 24 |
| Peak memory | 575572 kb |
| Host | smart-6142444b-2167-4651-b521-98890c5b8bda |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1019508958 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.xbar_random_zero_dela ys.1019508958 |
| Directory | /workspace/7.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/7.xbar_same_source.2880010533 |
| Short name | T723 |
| Test name | |
| Test status | |
| Simulation time | 562716273 ps |
| CPU time | 40.76 seconds |
| Started | Aug 12 06:47:32 PM PDT 24 |
| Finished | Aug 12 06:48:13 PM PDT 24 |
| Peak memory | 575580 kb |
| Host | smart-1df34f1f-3d2b-423d-9355-0fdf1b0b3868 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2880010533 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.xbar_same_source.2880010533 |
| Directory | /workspace/7.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/7.xbar_smoke.2950066451 |
| Short name | T2184 |
| Test name | |
| Test status | |
| Simulation time | 37349529 ps |
| CPU time | 6.08 seconds |
| Started | Aug 12 06:47:30 PM PDT 24 |
| Finished | Aug 12 06:47:36 PM PDT 24 |
| Peak memory | 573656 kb |
| Host | smart-c3b22e77-1203-4ea5-9c86-04c90e03aa4b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2950066451 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.xbar_smoke.2950066451 |
| Directory | /workspace/7.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/7.xbar_smoke_large_delays.3696978219 |
| Short name | T2669 |
| Test name | |
| Test status | |
| Simulation time | 7151162589 ps |
| CPU time | 73.85 seconds |
| Started | Aug 12 06:47:31 PM PDT 24 |
| Finished | Aug 12 06:48:45 PM PDT 24 |
| Peak memory | 573640 kb |
| Host | smart-ad4faf76-41a6-4791-9a5b-519216ede5f5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3696978219 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.xbar_smoke_large_delays.3696978219 |
| Directory | /workspace/7.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/7.xbar_smoke_slow_rsp.1982022604 |
| Short name | T1545 |
| Test name | |
| Test status | |
| Simulation time | 3881659156 ps |
| CPU time | 62.24 seconds |
| Started | Aug 12 06:47:35 PM PDT 24 |
| Finished | Aug 12 06:48:37 PM PDT 24 |
| Peak memory | 574372 kb |
| Host | smart-c40fb7f8-fb07-4552-b1d6-041ce12e04c6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1982022604 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.xbar_smoke_slow_rsp.1982022604 |
| Directory | /workspace/7.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/7.xbar_smoke_zero_delays.301360542 |
| Short name | T2049 |
| Test name | |
| Test status | |
| Simulation time | 31917507 ps |
| CPU time | 5.39 seconds |
| Started | Aug 12 06:47:36 PM PDT 24 |
| Finished | Aug 12 06:47:41 PM PDT 24 |
| Peak memory | 574156 kb |
| Host | smart-3c32f9eb-4e5c-4b46-851c-da62868962d9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=301360542 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.xbar_smoke_zero_delays. 301360542 |
| Directory | /workspace/7.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/7.xbar_stress_all.1160560302 |
| Short name | T2783 |
| Test name | |
| Test status | |
| Simulation time | 15343272385 ps |
| CPU time | 528.45 seconds |
| Started | Aug 12 06:47:42 PM PDT 24 |
| Finished | Aug 12 06:56:30 PM PDT 24 |
| Peak memory | 576088 kb |
| Host | smart-c6bbcd78-9421-4299-81c6-9df02a9b9325 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1160560302 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.xbar_stress_all.1160560302 |
| Directory | /workspace/7.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/7.xbar_stress_all_with_error.2935091755 |
| Short name | T1560 |
| Test name | |
| Test status | |
| Simulation time | 4563694873 ps |
| CPU time | 134.13 seconds |
| Started | Aug 12 06:47:34 PM PDT 24 |
| Finished | Aug 12 06:49:49 PM PDT 24 |
| Peak memory | 575932 kb |
| Host | smart-e73d78bb-cba4-4f61-a63d-959f9304ad12 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2935091755 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.xbar_stress_all_with_error.2935091755 |
| Directory | /workspace/7.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/7.xbar_stress_all_with_rand_reset.2432887260 |
| Short name | T2279 |
| Test name | |
| Test status | |
| Simulation time | 352314185 ps |
| CPU time | 115.1 seconds |
| Started | Aug 12 06:47:44 PM PDT 24 |
| Finished | Aug 12 06:49:39 PM PDT 24 |
| Peak memory | 576484 kb |
| Host | smart-c75ad8fd-84ba-4a4e-9df3-fab4b19f4061 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2432887260 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.xbar_stress_all_ with_rand_reset.2432887260 |
| Directory | /workspace/7.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/7.xbar_stress_all_with_reset_error.3193396378 |
| Short name | T1736 |
| Test name | |
| Test status | |
| Simulation time | 3212027613 ps |
| CPU time | 210.3 seconds |
| Started | Aug 12 06:47:32 PM PDT 24 |
| Finished | Aug 12 06:51:02 PM PDT 24 |
| Peak memory | 576540 kb |
| Host | smart-905f9259-3b48-4c12-a87b-c22dfd249b53 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3193396378 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.xbar_stress_all _with_reset_error.3193396378 |
| Directory | /workspace/7.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/7.xbar_unmapped_addr.2445070072 |
| Short name | T2642 |
| Test name | |
| Test status | |
| Simulation time | 528375559 ps |
| CPU time | 23.08 seconds |
| Started | Aug 12 06:47:33 PM PDT 24 |
| Finished | Aug 12 06:47:56 PM PDT 24 |
| Peak memory | 575720 kb |
| Host | smart-19c4ecdc-5654-473a-8d51-14fe3a4fceaf |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2445070072 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.xbar_unmapped_addr.2445070072 |
| Directory | /workspace/7.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/70.xbar_access_same_device.4260652401 |
| Short name | T2802 |
| Test name | |
| Test status | |
| Simulation time | 1567301881 ps |
| CPU time | 56.95 seconds |
| Started | Aug 12 06:55:49 PM PDT 24 |
| Finished | Aug 12 06:56:46 PM PDT 24 |
| Peak memory | 575540 kb |
| Host | smart-7f5caa9c-fa17-412b-9c0e-f8d4a306c0c4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4260652401 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 70.xbar_access_same_device .4260652401 |
| Directory | /workspace/70.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/70.xbar_access_same_device_slow_rsp.2589587781 |
| Short name | T2446 |
| Test name | |
| Test status | |
| Simulation time | 175466008476 ps |
| CPU time | 2999.93 seconds |
| Started | Aug 12 06:55:57 PM PDT 24 |
| Finished | Aug 12 07:45:57 PM PDT 24 |
| Peak memory | 575864 kb |
| Host | smart-fabb86b9-cf37-4fcf-8db0-34fea665788c |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2589587781 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 70.xbar_access_same_ device_slow_rsp.2589587781 |
| Directory | /workspace/70.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/70.xbar_error_and_unmapped_addr.2219776336 |
| Short name | T1827 |
| Test name | |
| Test status | |
| Simulation time | 649606328 ps |
| CPU time | 26.57 seconds |
| Started | Aug 12 06:55:52 PM PDT 24 |
| Finished | Aug 12 06:56:19 PM PDT 24 |
| Peak memory | 575524 kb |
| Host | smart-956c1615-7b8f-4317-80de-cacc0e7906dd |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2219776336 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 70.xbar_error_and_unmapped_add r.2219776336 |
| Directory | /workspace/70.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/70.xbar_error_random.3512452926 |
| Short name | T2596 |
| Test name | |
| Test status | |
| Simulation time | 370717535 ps |
| CPU time | 28.9 seconds |
| Started | Aug 12 06:55:49 PM PDT 24 |
| Finished | Aug 12 06:56:18 PM PDT 24 |
| Peak memory | 575672 kb |
| Host | smart-369897bb-e698-4ec1-82de-cbeb197e0e95 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3512452926 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 70.xbar_error_random.3512452926 |
| Directory | /workspace/70.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/70.xbar_random.2148458137 |
| Short name | T2023 |
| Test name | |
| Test status | |
| Simulation time | 1244399410 ps |
| CPU time | 42.52 seconds |
| Started | Aug 12 06:55:49 PM PDT 24 |
| Finished | Aug 12 06:56:31 PM PDT 24 |
| Peak memory | 575640 kb |
| Host | smart-53ef0d84-068e-4314-ae77-7667eb455d6d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2148458137 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 70.xbar_random.2148458137 |
| Directory | /workspace/70.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/70.xbar_random_large_delays.2936627580 |
| Short name | T577 |
| Test name | |
| Test status | |
| Simulation time | 77855608540 ps |
| CPU time | 920.54 seconds |
| Started | Aug 12 06:55:48 PM PDT 24 |
| Finished | Aug 12 07:11:08 PM PDT 24 |
| Peak memory | 575592 kb |
| Host | smart-790a29c8-0d1f-4dfc-b489-2f8f6c6ef6d3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2936627580 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 70.xbar_random_large_delays.2936627580 |
| Directory | /workspace/70.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/70.xbar_random_slow_rsp.2230132614 |
| Short name | T2437 |
| Test name | |
| Test status | |
| Simulation time | 52281110654 ps |
| CPU time | 957.05 seconds |
| Started | Aug 12 06:55:54 PM PDT 24 |
| Finished | Aug 12 07:11:51 PM PDT 24 |
| Peak memory | 575848 kb |
| Host | smart-dccfbd2a-a6f5-4315-9a8e-3592c90b7ec9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2230132614 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 70.xbar_random_slow_rsp.2230132614 |
| Directory | /workspace/70.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/70.xbar_random_zero_delays.2908395056 |
| Short name | T2395 |
| Test name | |
| Test status | |
| Simulation time | 485698808 ps |
| CPU time | 37.11 seconds |
| Started | Aug 12 06:55:57 PM PDT 24 |
| Finished | Aug 12 06:56:34 PM PDT 24 |
| Peak memory | 575688 kb |
| Host | smart-a466743e-4317-4417-9c7a-ca4517807f28 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2908395056 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 70.xbar_random_zero_del ays.2908395056 |
| Directory | /workspace/70.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/70.xbar_same_source.301434838 |
| Short name | T640 |
| Test name | |
| Test status | |
| Simulation time | 1340149740 ps |
| CPU time | 37.47 seconds |
| Started | Aug 12 06:55:50 PM PDT 24 |
| Finished | Aug 12 06:56:28 PM PDT 24 |
| Peak memory | 575552 kb |
| Host | smart-464e152e-3642-44f5-8bc6-d6556969dc2e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=301434838 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 70.xbar_same_source.301434838 |
| Directory | /workspace/70.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/70.xbar_smoke.4026043395 |
| Short name | T2453 |
| Test name | |
| Test status | |
| Simulation time | 154094410 ps |
| CPU time | 7.32 seconds |
| Started | Aug 12 06:55:51 PM PDT 24 |
| Finished | Aug 12 06:55:59 PM PDT 24 |
| Peak memory | 573516 kb |
| Host | smart-bc5c204e-98e3-4f47-96c2-756b12ce2e4a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4026043395 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 70.xbar_smoke.4026043395 |
| Directory | /workspace/70.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/70.xbar_smoke_large_delays.3358887456 |
| Short name | T1711 |
| Test name | |
| Test status | |
| Simulation time | 9014221711 ps |
| CPU time | 93.86 seconds |
| Started | Aug 12 06:55:57 PM PDT 24 |
| Finished | Aug 12 06:57:31 PM PDT 24 |
| Peak memory | 573692 kb |
| Host | smart-6c145ac4-8491-4fa6-8ad5-fb50c80f523e |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3358887456 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 70.xbar_smoke_large_delays.3358887456 |
| Directory | /workspace/70.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/70.xbar_smoke_slow_rsp.3594494561 |
| Short name | T2677 |
| Test name | |
| Test status | |
| Simulation time | 5819905834 ps |
| CPU time | 86.02 seconds |
| Started | Aug 12 06:55:48 PM PDT 24 |
| Finished | Aug 12 06:57:14 PM PDT 24 |
| Peak memory | 573644 kb |
| Host | smart-8112d47d-b2dd-47be-9376-756b94133353 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3594494561 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 70.xbar_smoke_slow_rsp.3594494561 |
| Directory | /workspace/70.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/70.xbar_smoke_zero_delays.3018685188 |
| Short name | T2219 |
| Test name | |
| Test status | |
| Simulation time | 48664446 ps |
| CPU time | 6.02 seconds |
| Started | Aug 12 06:55:49 PM PDT 24 |
| Finished | Aug 12 06:55:55 PM PDT 24 |
| Peak memory | 573564 kb |
| Host | smart-936473fa-4a01-4cf1-afb4-f53e5b09f542 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3018685188 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 70.xbar_smoke_zero_delay s.3018685188 |
| Directory | /workspace/70.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/70.xbar_stress_all.441507658 |
| Short name | T2774 |
| Test name | |
| Test status | |
| Simulation time | 1509241490 ps |
| CPU time | 54.87 seconds |
| Started | Aug 12 06:55:54 PM PDT 24 |
| Finished | Aug 12 06:56:49 PM PDT 24 |
| Peak memory | 575824 kb |
| Host | smart-f56ee182-bec0-4a58-95f8-eaed95b4d1fc |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=441507658 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 70.xbar_stress_all.441507658 |
| Directory | /workspace/70.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/70.xbar_stress_all_with_error.2121298697 |
| Short name | T2121 |
| Test name | |
| Test status | |
| Simulation time | 9847775301 ps |
| CPU time | 318.71 seconds |
| Started | Aug 12 06:55:51 PM PDT 24 |
| Finished | Aug 12 07:01:09 PM PDT 24 |
| Peak memory | 575956 kb |
| Host | smart-e8253083-7eb1-42a8-b0dd-2153079d5e15 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2121298697 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 70.xbar_stress_all_with_error.2121298697 |
| Directory | /workspace/70.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/70.xbar_stress_all_with_rand_reset.2467916990 |
| Short name | T2775 |
| Test name | |
| Test status | |
| Simulation time | 273399675 ps |
| CPU time | 112.26 seconds |
| Started | Aug 12 06:55:51 PM PDT 24 |
| Finished | Aug 12 06:57:44 PM PDT 24 |
| Peak memory | 576472 kb |
| Host | smart-657d0308-e63d-4d1f-8bb8-883bcfdbc0c5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2467916990 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 70.xbar_stress_all _with_rand_reset.2467916990 |
| Directory | /workspace/70.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/70.xbar_stress_all_with_reset_error.1817025688 |
| Short name | T2178 |
| Test name | |
| Test status | |
| Simulation time | 10986062623 ps |
| CPU time | 630.05 seconds |
| Started | Aug 12 06:55:53 PM PDT 24 |
| Finished | Aug 12 07:06:23 PM PDT 24 |
| Peak memory | 578760 kb |
| Host | smart-36f205ea-3066-4a70-aefb-ac2ae0498a39 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1817025688 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 70.xbar_stress_al l_with_reset_error.1817025688 |
| Directory | /workspace/70.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/70.xbar_unmapped_addr.581992854 |
| Short name | T2871 |
| Test name | |
| Test status | |
| Simulation time | 858882079 ps |
| CPU time | 37.43 seconds |
| Started | Aug 12 06:55:50 PM PDT 24 |
| Finished | Aug 12 06:56:27 PM PDT 24 |
| Peak memory | 575584 kb |
| Host | smart-e9733fb8-e314-459b-b570-d907f4d5285e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=581992854 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 70.xbar_unmapped_addr.581992854 |
| Directory | /workspace/70.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/71.xbar_access_same_device.509040151 |
| Short name | T1595 |
| Test name | |
| Test status | |
| Simulation time | 14186421 ps |
| CPU time | 5.86 seconds |
| Started | Aug 12 06:55:57 PM PDT 24 |
| Finished | Aug 12 06:56:03 PM PDT 24 |
| Peak memory | 573504 kb |
| Host | smart-5e59f136-c6f0-4595-921d-1f7daee39964 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=509040151 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 71.xbar_access_same_device. 509040151 |
| Directory | /workspace/71.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/71.xbar_access_same_device_slow_rsp.1408189667 |
| Short name | T2144 |
| Test name | |
| Test status | |
| Simulation time | 128623328931 ps |
| CPU time | 2524.25 seconds |
| Started | Aug 12 06:55:59 PM PDT 24 |
| Finished | Aug 12 07:38:04 PM PDT 24 |
| Peak memory | 575640 kb |
| Host | smart-fde58512-8887-48ec-8075-714e8fd953e6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1408189667 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 71.xbar_access_same_ device_slow_rsp.1408189667 |
| Directory | /workspace/71.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/71.xbar_error_and_unmapped_addr.748052217 |
| Short name | T1731 |
| Test name | |
| Test status | |
| Simulation time | 93476290 ps |
| CPU time | 7.66 seconds |
| Started | Aug 12 06:55:58 PM PDT 24 |
| Finished | Aug 12 06:56:06 PM PDT 24 |
| Peak memory | 573668 kb |
| Host | smart-586ff024-7418-445f-9472-6348f2d1f3da |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=748052217 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 71.xbar_error_and_unmapped_addr .748052217 |
| Directory | /workspace/71.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/71.xbar_error_random.322455751 |
| Short name | T2354 |
| Test name | |
| Test status | |
| Simulation time | 1195459476 ps |
| CPU time | 34.59 seconds |
| Started | Aug 12 06:55:57 PM PDT 24 |
| Finished | Aug 12 06:56:32 PM PDT 24 |
| Peak memory | 575536 kb |
| Host | smart-57ee36bf-4206-4f14-83c7-d12cbfa9d286 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=322455751 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 71.xbar_error_random.322455751 |
| Directory | /workspace/71.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/71.xbar_random.1953544643 |
| Short name | T2038 |
| Test name | |
| Test status | |
| Simulation time | 581099142 ps |
| CPU time | 19.88 seconds |
| Started | Aug 12 06:55:58 PM PDT 24 |
| Finished | Aug 12 06:56:18 PM PDT 24 |
| Peak memory | 575632 kb |
| Host | smart-8aabb933-ec31-44dd-ab21-43a44907be19 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1953544643 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 71.xbar_random.1953544643 |
| Directory | /workspace/71.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/71.xbar_random_large_delays.2733988461 |
| Short name | T539 |
| Test name | |
| Test status | |
| Simulation time | 52168318343 ps |
| CPU time | 568.47 seconds |
| Started | Aug 12 06:56:07 PM PDT 24 |
| Finished | Aug 12 07:05:36 PM PDT 24 |
| Peak memory | 575552 kb |
| Host | smart-46655cea-7696-4b0d-91dd-84b60f20d27b |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2733988461 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 71.xbar_random_large_delays.2733988461 |
| Directory | /workspace/71.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/71.xbar_random_slow_rsp.2369694931 |
| Short name | T454 |
| Test name | |
| Test status | |
| Simulation time | 62302584060 ps |
| CPU time | 1197.21 seconds |
| Started | Aug 12 06:55:58 PM PDT 24 |
| Finished | Aug 12 07:15:56 PM PDT 24 |
| Peak memory | 575708 kb |
| Host | smart-a7ec5f39-c8ed-4a3a-baa7-400ef168f4cd |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2369694931 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 71.xbar_random_slow_rsp.2369694931 |
| Directory | /workspace/71.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/71.xbar_random_zero_delays.287359877 |
| Short name | T662 |
| Test name | |
| Test status | |
| Simulation time | 336161309 ps |
| CPU time | 26.89 seconds |
| Started | Aug 12 06:55:58 PM PDT 24 |
| Finished | Aug 12 06:56:25 PM PDT 24 |
| Peak memory | 575712 kb |
| Host | smart-5fc9b701-2826-44c0-bba0-88a892bdc79c |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=287359877 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 71.xbar_random_zero_dela ys.287359877 |
| Directory | /workspace/71.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/71.xbar_same_source.820100555 |
| Short name | T2580 |
| Test name | |
| Test status | |
| Simulation time | 99076491 ps |
| CPU time | 8.73 seconds |
| Started | Aug 12 06:56:07 PM PDT 24 |
| Finished | Aug 12 06:56:16 PM PDT 24 |
| Peak memory | 575668 kb |
| Host | smart-c74c439e-874f-404e-8ce0-70744a7ff049 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=820100555 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 71.xbar_same_source.820100555 |
| Directory | /workspace/71.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/71.xbar_smoke.404433211 |
| Short name | T2418 |
| Test name | |
| Test status | |
| Simulation time | 183817532 ps |
| CPU time | 8.74 seconds |
| Started | Aug 12 06:55:57 PM PDT 24 |
| Finished | Aug 12 06:56:06 PM PDT 24 |
| Peak memory | 573628 kb |
| Host | smart-55a8a982-a086-43b8-952c-64b32c85df9a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=404433211 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 71.xbar_smoke.404433211 |
| Directory | /workspace/71.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/71.xbar_smoke_large_delays.2755157064 |
| Short name | T1858 |
| Test name | |
| Test status | |
| Simulation time | 6022844546 ps |
| CPU time | 65.42 seconds |
| Started | Aug 12 06:56:02 PM PDT 24 |
| Finished | Aug 12 06:57:07 PM PDT 24 |
| Peak memory | 573660 kb |
| Host | smart-a5937bce-efdb-4681-abaf-28c16b6c2287 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2755157064 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 71.xbar_smoke_large_delays.2755157064 |
| Directory | /workspace/71.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/71.xbar_smoke_slow_rsp.2577527270 |
| Short name | T1692 |
| Test name | |
| Test status | |
| Simulation time | 5109591608 ps |
| CPU time | 87.37 seconds |
| Started | Aug 12 06:55:56 PM PDT 24 |
| Finished | Aug 12 06:57:24 PM PDT 24 |
| Peak memory | 574288 kb |
| Host | smart-743da459-a18d-4a80-bed8-350d09b5387e |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2577527270 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 71.xbar_smoke_slow_rsp.2577527270 |
| Directory | /workspace/71.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/71.xbar_smoke_zero_delays.3314516259 |
| Short name | T2937 |
| Test name | |
| Test status | |
| Simulation time | 52619149 ps |
| CPU time | 6.26 seconds |
| Started | Aug 12 06:55:57 PM PDT 24 |
| Finished | Aug 12 06:56:03 PM PDT 24 |
| Peak memory | 573552 kb |
| Host | smart-cc02ab09-0d7f-4775-9c31-16fad5765d06 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3314516259 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 71.xbar_smoke_zero_delay s.3314516259 |
| Directory | /workspace/71.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/71.xbar_stress_all.2582072181 |
| Short name | T1602 |
| Test name | |
| Test status | |
| Simulation time | 494251634 ps |
| CPU time | 18.84 seconds |
| Started | Aug 12 06:55:56 PM PDT 24 |
| Finished | Aug 12 06:56:15 PM PDT 24 |
| Peak memory | 575692 kb |
| Host | smart-b0d6bc52-87fd-4054-8ff3-de07c1648d92 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2582072181 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 71.xbar_stress_all.2582072181 |
| Directory | /workspace/71.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/71.xbar_stress_all_with_error.17125222 |
| Short name | T2385 |
| Test name | |
| Test status | |
| Simulation time | 9215557380 ps |
| CPU time | 299.23 seconds |
| Started | Aug 12 06:55:56 PM PDT 24 |
| Finished | Aug 12 07:00:56 PM PDT 24 |
| Peak memory | 576548 kb |
| Host | smart-138464a9-97dd-438c-a271-6bdf803d313b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17125222 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 71.xbar_stress_all_with_error.17125222 |
| Directory | /workspace/71.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/71.xbar_stress_all_with_reset_error.2432546174 |
| Short name | T949 |
| Test name | |
| Test status | |
| Simulation time | 6042528119 ps |
| CPU time | 347.09 seconds |
| Started | Aug 12 06:55:58 PM PDT 24 |
| Finished | Aug 12 07:01:45 PM PDT 24 |
| Peak memory | 576600 kb |
| Host | smart-2aede043-40b9-4b2e-a7c9-2b0ed21a33e7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2432546174 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 71.xbar_stress_al l_with_reset_error.2432546174 |
| Directory | /workspace/71.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/71.xbar_unmapped_addr.3738143943 |
| Short name | T2299 |
| Test name | |
| Test status | |
| Simulation time | 318430361 ps |
| CPU time | 36.89 seconds |
| Started | Aug 12 06:56:00 PM PDT 24 |
| Finished | Aug 12 06:56:37 PM PDT 24 |
| Peak memory | 575648 kb |
| Host | smart-71e16fce-dfc3-4f43-b776-0348ec2351d4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3738143943 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 71.xbar_unmapped_addr.3738143943 |
| Directory | /workspace/71.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/72.xbar_access_same_device.101871223 |
| Short name | T475 |
| Test name | |
| Test status | |
| Simulation time | 1031892099 ps |
| CPU time | 77.56 seconds |
| Started | Aug 12 06:56:08 PM PDT 24 |
| Finished | Aug 12 06:57:26 PM PDT 24 |
| Peak memory | 575736 kb |
| Host | smart-8493618f-5e9c-43da-b345-debd884d7d9e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=101871223 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 72.xbar_access_same_device. 101871223 |
| Directory | /workspace/72.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/72.xbar_access_same_device_slow_rsp.3772193379 |
| Short name | T537 |
| Test name | |
| Test status | |
| Simulation time | 99401821665 ps |
| CPU time | 1922.27 seconds |
| Started | Aug 12 06:56:08 PM PDT 24 |
| Finished | Aug 12 07:28:11 PM PDT 24 |
| Peak memory | 575780 kb |
| Host | smart-d3648d49-e03d-42cd-b9b3-a4e3d8525573 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3772193379 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 72.xbar_access_same_ device_slow_rsp.3772193379 |
| Directory | /workspace/72.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/72.xbar_error_and_unmapped_addr.1406238936 |
| Short name | T2861 |
| Test name | |
| Test status | |
| Simulation time | 472567126 ps |
| CPU time | 21.8 seconds |
| Started | Aug 12 06:56:08 PM PDT 24 |
| Finished | Aug 12 06:56:30 PM PDT 24 |
| Peak memory | 575636 kb |
| Host | smart-36cc2976-8223-490a-a503-823c81299199 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1406238936 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 72.xbar_error_and_unmapped_add r.1406238936 |
| Directory | /workspace/72.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/72.xbar_error_random.3367786168 |
| Short name | T2528 |
| Test name | |
| Test status | |
| Simulation time | 376929583 ps |
| CPU time | 27.63 seconds |
| Started | Aug 12 06:56:09 PM PDT 24 |
| Finished | Aug 12 06:56:37 PM PDT 24 |
| Peak memory | 575480 kb |
| Host | smart-a3e357e7-5a98-4e5b-beb0-69388cf88999 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3367786168 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 72.xbar_error_random.3367786168 |
| Directory | /workspace/72.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/72.xbar_random.3626870795 |
| Short name | T624 |
| Test name | |
| Test status | |
| Simulation time | 888070218 ps |
| CPU time | 33.21 seconds |
| Started | Aug 12 06:56:08 PM PDT 24 |
| Finished | Aug 12 06:56:41 PM PDT 24 |
| Peak memory | 575648 kb |
| Host | smart-ee39270d-a5e7-478e-b8d2-b2d8b041676b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3626870795 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 72.xbar_random.3626870795 |
| Directory | /workspace/72.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/72.xbar_random_large_delays.884958059 |
| Short name | T1966 |
| Test name | |
| Test status | |
| Simulation time | 41182714374 ps |
| CPU time | 429.36 seconds |
| Started | Aug 12 06:56:07 PM PDT 24 |
| Finished | Aug 12 07:03:16 PM PDT 24 |
| Peak memory | 575776 kb |
| Host | smart-ecbf2a6f-87ea-4c3f-a78c-6813bf02b384 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=884958059 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 72.xbar_random_large_delays.884958059 |
| Directory | /workspace/72.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/72.xbar_random_slow_rsp.1908308972 |
| Short name | T2711 |
| Test name | |
| Test status | |
| Simulation time | 42312573848 ps |
| CPU time | 784.14 seconds |
| Started | Aug 12 06:56:10 PM PDT 24 |
| Finished | Aug 12 07:09:14 PM PDT 24 |
| Peak memory | 576504 kb |
| Host | smart-e6c44b8d-a0fa-47af-9ebc-d918196524e5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1908308972 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 72.xbar_random_slow_rsp.1908308972 |
| Directory | /workspace/72.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/72.xbar_random_zero_delays.1843407051 |
| Short name | T1936 |
| Test name | |
| Test status | |
| Simulation time | 147518676 ps |
| CPU time | 17.12 seconds |
| Started | Aug 12 06:56:12 PM PDT 24 |
| Finished | Aug 12 06:56:29 PM PDT 24 |
| Peak memory | 575604 kb |
| Host | smart-692e8647-0e96-49ac-aa9a-70f421ed23c0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1843407051 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 72.xbar_random_zero_del ays.1843407051 |
| Directory | /workspace/72.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/72.xbar_same_source.3126992769 |
| Short name | T2656 |
| Test name | |
| Test status | |
| Simulation time | 581500107 ps |
| CPU time | 44.55 seconds |
| Started | Aug 12 06:56:13 PM PDT 24 |
| Finished | Aug 12 06:56:58 PM PDT 24 |
| Peak memory | 575624 kb |
| Host | smart-cf4fa540-5bf5-4821-85c2-c1303e28e71c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3126992769 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 72.xbar_same_source.3126992769 |
| Directory | /workspace/72.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/72.xbar_smoke.4083276923 |
| Short name | T1494 |
| Test name | |
| Test status | |
| Simulation time | 177097178 ps |
| CPU time | 8.37 seconds |
| Started | Aug 12 06:56:02 PM PDT 24 |
| Finished | Aug 12 06:56:10 PM PDT 24 |
| Peak memory | 574252 kb |
| Host | smart-f8ec0f58-7aba-4160-8ee0-28aff942a0df |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4083276923 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 72.xbar_smoke.4083276923 |
| Directory | /workspace/72.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/72.xbar_smoke_large_delays.2926911432 |
| Short name | T2048 |
| Test name | |
| Test status | |
| Simulation time | 7001132519 ps |
| CPU time | 77.77 seconds |
| Started | Aug 12 06:56:09 PM PDT 24 |
| Finished | Aug 12 06:57:26 PM PDT 24 |
| Peak memory | 573704 kb |
| Host | smart-5c454194-5fa0-40eb-9a73-1a29349d952a |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2926911432 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 72.xbar_smoke_large_delays.2926911432 |
| Directory | /workspace/72.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/72.xbar_smoke_slow_rsp.3101503173 |
| Short name | T2138 |
| Test name | |
| Test status | |
| Simulation time | 5337021654 ps |
| CPU time | 87.63 seconds |
| Started | Aug 12 06:56:10 PM PDT 24 |
| Finished | Aug 12 06:57:38 PM PDT 24 |
| Peak memory | 574336 kb |
| Host | smart-6549fae2-008b-4ffb-9264-e5e93209aca9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3101503173 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 72.xbar_smoke_slow_rsp.3101503173 |
| Directory | /workspace/72.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/72.xbar_smoke_zero_delays.2632576413 |
| Short name | T2212 |
| Test name | |
| Test status | |
| Simulation time | 48023797 ps |
| CPU time | 6.41 seconds |
| Started | Aug 12 06:56:07 PM PDT 24 |
| Finished | Aug 12 06:56:14 PM PDT 24 |
| Peak memory | 573404 kb |
| Host | smart-1d3ae6fa-483e-4728-8c38-73d0e2a01f41 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2632576413 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 72.xbar_smoke_zero_delay s.2632576413 |
| Directory | /workspace/72.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/72.xbar_stress_all.738577342 |
| Short name | T1634 |
| Test name | |
| Test status | |
| Simulation time | 311213342 ps |
| CPU time | 27.22 seconds |
| Started | Aug 12 06:56:12 PM PDT 24 |
| Finished | Aug 12 06:56:39 PM PDT 24 |
| Peak memory | 575852 kb |
| Host | smart-96d95b74-ce08-4b6c-adf8-01487aae9638 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=738577342 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 72.xbar_stress_all.738577342 |
| Directory | /workspace/72.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/72.xbar_stress_all_with_error.3876630624 |
| Short name | T1529 |
| Test name | |
| Test status | |
| Simulation time | 87931695 ps |
| CPU time | 10.33 seconds |
| Started | Aug 12 06:56:06 PM PDT 24 |
| Finished | Aug 12 06:56:17 PM PDT 24 |
| Peak memory | 575680 kb |
| Host | smart-0384c92b-d2a0-4e7f-ac92-a953592fb7d5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3876630624 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 72.xbar_stress_all_with_error.3876630624 |
| Directory | /workspace/72.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/72.xbar_stress_all_with_rand_reset.1009101748 |
| Short name | T2901 |
| Test name | |
| Test status | |
| Simulation time | 6630850282 ps |
| CPU time | 795.03 seconds |
| Started | Aug 12 06:56:09 PM PDT 24 |
| Finished | Aug 12 07:09:24 PM PDT 24 |
| Peak memory | 577596 kb |
| Host | smart-c0af8a80-b077-4856-8394-4ab75e8374a6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1009101748 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 72.xbar_stress_all _with_rand_reset.1009101748 |
| Directory | /workspace/72.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/72.xbar_stress_all_with_reset_error.4037922707 |
| Short name | T1503 |
| Test name | |
| Test status | |
| Simulation time | 202097099 ps |
| CPU time | 58.64 seconds |
| Started | Aug 12 06:56:10 PM PDT 24 |
| Finished | Aug 12 06:57:08 PM PDT 24 |
| Peak memory | 576508 kb |
| Host | smart-db868a7e-b183-4058-9235-9c51dd205d2b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4037922707 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 72.xbar_stress_al l_with_reset_error.4037922707 |
| Directory | /workspace/72.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/72.xbar_unmapped_addr.1106240400 |
| Short name | T1903 |
| Test name | |
| Test status | |
| Simulation time | 290383469 ps |
| CPU time | 14.93 seconds |
| Started | Aug 12 06:56:11 PM PDT 24 |
| Finished | Aug 12 06:56:26 PM PDT 24 |
| Peak memory | 575764 kb |
| Host | smart-af402315-7bd2-49bc-8ca6-4e1d75d016e5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1106240400 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 72.xbar_unmapped_addr.1106240400 |
| Directory | /workspace/72.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/73.xbar_access_same_device.2838948884 |
| Short name | T925 |
| Test name | |
| Test status | |
| Simulation time | 1702478438 ps |
| CPU time | 65.29 seconds |
| Started | Aug 12 06:56:10 PM PDT 24 |
| Finished | Aug 12 06:57:16 PM PDT 24 |
| Peak memory | 575684 kb |
| Host | smart-7696438d-7fef-476a-a521-512a3185bcda |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2838948884 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 73.xbar_access_same_device .2838948884 |
| Directory | /workspace/73.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/73.xbar_access_same_device_slow_rsp.1450469915 |
| Short name | T1927 |
| Test name | |
| Test status | |
| Simulation time | 42597764640 ps |
| CPU time | 749.47 seconds |
| Started | Aug 12 06:56:10 PM PDT 24 |
| Finished | Aug 12 07:08:40 PM PDT 24 |
| Peak memory | 575588 kb |
| Host | smart-de0da5d8-be07-476b-a8e7-4c76812c6e8e |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1450469915 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 73.xbar_access_same_ device_slow_rsp.1450469915 |
| Directory | /workspace/73.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/73.xbar_error_and_unmapped_addr.3835315885 |
| Short name | T1458 |
| Test name | |
| Test status | |
| Simulation time | 648182603 ps |
| CPU time | 26.64 seconds |
| Started | Aug 12 06:56:17 PM PDT 24 |
| Finished | Aug 12 06:56:44 PM PDT 24 |
| Peak memory | 575748 kb |
| Host | smart-9418c815-0db7-49ed-99a6-12083fa95533 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3835315885 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 73.xbar_error_and_unmapped_add r.3835315885 |
| Directory | /workspace/73.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/73.xbar_error_random.2624656993 |
| Short name | T2567 |
| Test name | |
| Test status | |
| Simulation time | 1509602591 ps |
| CPU time | 49.73 seconds |
| Started | Aug 12 06:56:16 PM PDT 24 |
| Finished | Aug 12 06:57:06 PM PDT 24 |
| Peak memory | 575472 kb |
| Host | smart-b4022e44-3bdb-4718-bd86-c47e7908ee52 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2624656993 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 73.xbar_error_random.2624656993 |
| Directory | /workspace/73.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/73.xbar_random.1637011565 |
| Short name | T540 |
| Test name | |
| Test status | |
| Simulation time | 605024140 ps |
| CPU time | 51.63 seconds |
| Started | Aug 12 06:56:08 PM PDT 24 |
| Finished | Aug 12 06:57:00 PM PDT 24 |
| Peak memory | 575552 kb |
| Host | smart-251b7d82-be05-4a30-a2e8-459baf0cb85a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1637011565 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 73.xbar_random.1637011565 |
| Directory | /workspace/73.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/73.xbar_random_large_delays.3319769242 |
| Short name | T2706 |
| Test name | |
| Test status | |
| Simulation time | 98641373192 ps |
| CPU time | 1070.2 seconds |
| Started | Aug 12 06:56:07 PM PDT 24 |
| Finished | Aug 12 07:13:58 PM PDT 24 |
| Peak memory | 575784 kb |
| Host | smart-c967ab24-aa2b-4d9d-bfa8-48220c819146 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3319769242 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 73.xbar_random_large_delays.3319769242 |
| Directory | /workspace/73.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/73.xbar_random_slow_rsp.2730012029 |
| Short name | T2149 |
| Test name | |
| Test status | |
| Simulation time | 61990291003 ps |
| CPU time | 1011.01 seconds |
| Started | Aug 12 06:56:07 PM PDT 24 |
| Finished | Aug 12 07:12:59 PM PDT 24 |
| Peak memory | 575864 kb |
| Host | smart-f0f01b3f-04b6-40fb-b0d4-58148dc67940 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2730012029 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 73.xbar_random_slow_rsp.2730012029 |
| Directory | /workspace/73.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/73.xbar_random_zero_delays.1993677399 |
| Short name | T1774 |
| Test name | |
| Test status | |
| Simulation time | 387258728 ps |
| CPU time | 32.61 seconds |
| Started | Aug 12 06:56:08 PM PDT 24 |
| Finished | Aug 12 06:56:40 PM PDT 24 |
| Peak memory | 575732 kb |
| Host | smart-1d9547d1-4cc2-415e-bd87-99bf37f5d14b |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1993677399 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 73.xbar_random_zero_del ays.1993677399 |
| Directory | /workspace/73.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/73.xbar_same_source.724918899 |
| Short name | T2187 |
| Test name | |
| Test status | |
| Simulation time | 205441583 ps |
| CPU time | 16.58 seconds |
| Started | Aug 12 06:56:07 PM PDT 24 |
| Finished | Aug 12 06:56:23 PM PDT 24 |
| Peak memory | 575592 kb |
| Host | smart-f69d7c76-c4c1-4352-84b4-817e3fd8d14f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=724918899 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 73.xbar_same_source.724918899 |
| Directory | /workspace/73.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/73.xbar_smoke.136172776 |
| Short name | T2518 |
| Test name | |
| Test status | |
| Simulation time | 243822764 ps |
| CPU time | 9.82 seconds |
| Started | Aug 12 06:56:12 PM PDT 24 |
| Finished | Aug 12 06:56:22 PM PDT 24 |
| Peak memory | 573732 kb |
| Host | smart-98315505-5a92-4f8a-9f38-45cdac222768 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=136172776 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 73.xbar_smoke.136172776 |
| Directory | /workspace/73.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/73.xbar_smoke_large_delays.392667909 |
| Short name | T2449 |
| Test name | |
| Test status | |
| Simulation time | 9995739653 ps |
| CPU time | 109.06 seconds |
| Started | Aug 12 06:56:09 PM PDT 24 |
| Finished | Aug 12 06:57:58 PM PDT 24 |
| Peak memory | 573580 kb |
| Host | smart-9536f8bf-d1e4-4f8d-92b7-479ba639dc88 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=392667909 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 73.xbar_smoke_large_delays.392667909 |
| Directory | /workspace/73.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/73.xbar_smoke_slow_rsp.2978993243 |
| Short name | T605 |
| Test name | |
| Test status | |
| Simulation time | 5625545534 ps |
| CPU time | 96.19 seconds |
| Started | Aug 12 06:56:06 PM PDT 24 |
| Finished | Aug 12 06:57:43 PM PDT 24 |
| Peak memory | 574360 kb |
| Host | smart-660022c8-934c-457d-a6ea-d76e60d4690e |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2978993243 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 73.xbar_smoke_slow_rsp.2978993243 |
| Directory | /workspace/73.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/73.xbar_smoke_zero_delays.1356924673 |
| Short name | T2834 |
| Test name | |
| Test status | |
| Simulation time | 40350149 ps |
| CPU time | 5.92 seconds |
| Started | Aug 12 06:56:06 PM PDT 24 |
| Finished | Aug 12 06:56:12 PM PDT 24 |
| Peak memory | 574332 kb |
| Host | smart-cba4f117-c8b6-4a2c-beea-28a31a13c7ca |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1356924673 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 73.xbar_smoke_zero_delay s.1356924673 |
| Directory | /workspace/73.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/73.xbar_stress_all.879527016 |
| Short name | T530 |
| Test name | |
| Test status | |
| Simulation time | 10131545191 ps |
| CPU time | 369.66 seconds |
| Started | Aug 12 06:56:14 PM PDT 24 |
| Finished | Aug 12 07:02:24 PM PDT 24 |
| Peak memory | 576612 kb |
| Host | smart-5df2a63c-2d2a-4c33-83c3-cc6e654676ed |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=879527016 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 73.xbar_stress_all.879527016 |
| Directory | /workspace/73.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/73.xbar_stress_all_with_error.650932083 |
| Short name | T2377 |
| Test name | |
| Test status | |
| Simulation time | 5789861991 ps |
| CPU time | 203.84 seconds |
| Started | Aug 12 06:56:17 PM PDT 24 |
| Finished | Aug 12 06:59:40 PM PDT 24 |
| Peak memory | 575932 kb |
| Host | smart-c8ccfa98-2392-4c2a-8045-8f601bdd80c0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=650932083 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 73.xbar_stress_all_with_error.650932083 |
| Directory | /workspace/73.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/73.xbar_stress_all_with_rand_reset.3357604692 |
| Short name | T2651 |
| Test name | |
| Test status | |
| Simulation time | 2633949824 ps |
| CPU time | 450.08 seconds |
| Started | Aug 12 06:56:19 PM PDT 24 |
| Finished | Aug 12 07:03:50 PM PDT 24 |
| Peak memory | 576732 kb |
| Host | smart-a660f811-2c93-4302-9990-c32696092c68 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3357604692 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 73.xbar_stress_all _with_rand_reset.3357604692 |
| Directory | /workspace/73.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/73.xbar_stress_all_with_reset_error.1670401816 |
| Short name | T941 |
| Test name | |
| Test status | |
| Simulation time | 322665778 ps |
| CPU time | 82.09 seconds |
| Started | Aug 12 06:56:20 PM PDT 24 |
| Finished | Aug 12 06:57:42 PM PDT 24 |
| Peak memory | 576488 kb |
| Host | smart-7f1f63fc-0556-4d31-8ec2-92bed8f75536 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1670401816 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 73.xbar_stress_al l_with_reset_error.1670401816 |
| Directory | /workspace/73.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/73.xbar_unmapped_addr.1847686237 |
| Short name | T2261 |
| Test name | |
| Test status | |
| Simulation time | 1260771766 ps |
| CPU time | 50.71 seconds |
| Started | Aug 12 06:56:15 PM PDT 24 |
| Finished | Aug 12 06:57:06 PM PDT 24 |
| Peak memory | 575652 kb |
| Host | smart-08ab422b-b093-4dfa-9dc3-93fa807ab5de |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1847686237 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 73.xbar_unmapped_addr.1847686237 |
| Directory | /workspace/73.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/74.xbar_access_same_device.2551049754 |
| Short name | T1842 |
| Test name | |
| Test status | |
| Simulation time | 2868431857 ps |
| CPU time | 115.6 seconds |
| Started | Aug 12 06:56:16 PM PDT 24 |
| Finished | Aug 12 06:58:12 PM PDT 24 |
| Peak memory | 575692 kb |
| Host | smart-4010c945-d2b4-4fe5-b62c-4c6f578252a5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2551049754 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 74.xbar_access_same_device .2551049754 |
| Directory | /workspace/74.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/74.xbar_access_same_device_slow_rsp.3719525293 |
| Short name | T2644 |
| Test name | |
| Test status | |
| Simulation time | 27732391784 ps |
| CPU time | 459.4 seconds |
| Started | Aug 12 06:56:19 PM PDT 24 |
| Finished | Aug 12 07:03:59 PM PDT 24 |
| Peak memory | 575612 kb |
| Host | smart-63dd19f0-f936-4eba-a4d5-09ee171d08f3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3719525293 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 74.xbar_access_same_ device_slow_rsp.3719525293 |
| Directory | /workspace/74.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/74.xbar_error_and_unmapped_addr.7393207 |
| Short name | T2714 |
| Test name | |
| Test status | |
| Simulation time | 979923738 ps |
| CPU time | 38.98 seconds |
| Started | Aug 12 06:56:16 PM PDT 24 |
| Finished | Aug 12 06:56:55 PM PDT 24 |
| Peak memory | 575516 kb |
| Host | smart-2d08c0ad-b0cb-4ad4-99e6-dc180be17707 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=7393207 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 74.xbar_error_and_unmapped_addr.7393207 |
| Directory | /workspace/74.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/74.xbar_error_random.2500714453 |
| Short name | T1524 |
| Test name | |
| Test status | |
| Simulation time | 1854430528 ps |
| CPU time | 64.65 seconds |
| Started | Aug 12 06:56:18 PM PDT 24 |
| Finished | Aug 12 06:57:23 PM PDT 24 |
| Peak memory | 575676 kb |
| Host | smart-94bdc2fd-424b-44bc-8aae-085f572bcad7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2500714453 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 74.xbar_error_random.2500714453 |
| Directory | /workspace/74.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/74.xbar_random.3706191571 |
| Short name | T672 |
| Test name | |
| Test status | |
| Simulation time | 334954770 ps |
| CPU time | 30.92 seconds |
| Started | Aug 12 06:56:19 PM PDT 24 |
| Finished | Aug 12 06:56:51 PM PDT 24 |
| Peak memory | 575560 kb |
| Host | smart-075894a8-09e1-49e1-842c-852c09a28b87 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3706191571 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 74.xbar_random.3706191571 |
| Directory | /workspace/74.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/74.xbar_random_large_delays.329570101 |
| Short name | T2817 |
| Test name | |
| Test status | |
| Simulation time | 101931125498 ps |
| CPU time | 1082.81 seconds |
| Started | Aug 12 06:56:19 PM PDT 24 |
| Finished | Aug 12 07:14:22 PM PDT 24 |
| Peak memory | 575780 kb |
| Host | smart-4df20020-1695-455a-bfa7-391358aa5211 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=329570101 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 74.xbar_random_large_delays.329570101 |
| Directory | /workspace/74.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/74.xbar_random_slow_rsp.4015401974 |
| Short name | T2296 |
| Test name | |
| Test status | |
| Simulation time | 46288740463 ps |
| CPU time | 863.59 seconds |
| Started | Aug 12 06:56:18 PM PDT 24 |
| Finished | Aug 12 07:10:42 PM PDT 24 |
| Peak memory | 575712 kb |
| Host | smart-3bc15bbf-775c-4539-9b77-2e1b7254cb06 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4015401974 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 74.xbar_random_slow_rsp.4015401974 |
| Directory | /workspace/74.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/74.xbar_random_zero_delays.2658030649 |
| Short name | T1488 |
| Test name | |
| Test status | |
| Simulation time | 91448535 ps |
| CPU time | 10.19 seconds |
| Started | Aug 12 06:56:16 PM PDT 24 |
| Finished | Aug 12 06:56:26 PM PDT 24 |
| Peak memory | 575536 kb |
| Host | smart-8b6bfbe3-7429-42d0-a7af-56cf4191663a |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2658030649 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 74.xbar_random_zero_del ays.2658030649 |
| Directory | /workspace/74.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/74.xbar_same_source.3010527568 |
| Short name | T690 |
| Test name | |
| Test status | |
| Simulation time | 128328475 ps |
| CPU time | 10.51 seconds |
| Started | Aug 12 06:56:18 PM PDT 24 |
| Finished | Aug 12 06:56:28 PM PDT 24 |
| Peak memory | 575676 kb |
| Host | smart-9cc9cfdb-8901-4ff0-8569-1c85a14b4648 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3010527568 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 74.xbar_same_source.3010527568 |
| Directory | /workspace/74.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/74.xbar_smoke.3415628500 |
| Short name | T1607 |
| Test name | |
| Test status | |
| Simulation time | 129933573 ps |
| CPU time | 6.99 seconds |
| Started | Aug 12 06:56:16 PM PDT 24 |
| Finished | Aug 12 06:56:23 PM PDT 24 |
| Peak memory | 573596 kb |
| Host | smart-ee4d84ae-7e6d-4f59-aea2-121cafdef8b6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3415628500 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 74.xbar_smoke.3415628500 |
| Directory | /workspace/74.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/74.xbar_smoke_large_delays.2896395637 |
| Short name | T2728 |
| Test name | |
| Test status | |
| Simulation time | 8408103888 ps |
| CPU time | 81.43 seconds |
| Started | Aug 12 06:56:18 PM PDT 24 |
| Finished | Aug 12 06:57:39 PM PDT 24 |
| Peak memory | 573680 kb |
| Host | smart-d9bcb688-37c2-4568-bc37-5bc79a7a631d |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2896395637 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 74.xbar_smoke_large_delays.2896395637 |
| Directory | /workspace/74.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/74.xbar_smoke_slow_rsp.4229712278 |
| Short name | T1579 |
| Test name | |
| Test status | |
| Simulation time | 4011098622 ps |
| CPU time | 67.32 seconds |
| Started | Aug 12 06:56:16 PM PDT 24 |
| Finished | Aug 12 06:57:24 PM PDT 24 |
| Peak memory | 573684 kb |
| Host | smart-2b5229e0-9b55-4a33-b7be-cd885037ef14 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4229712278 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 74.xbar_smoke_slow_rsp.4229712278 |
| Directory | /workspace/74.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/74.xbar_smoke_zero_delays.3233288536 |
| Short name | T2255 |
| Test name | |
| Test status | |
| Simulation time | 50309177 ps |
| CPU time | 6.4 seconds |
| Started | Aug 12 06:56:19 PM PDT 24 |
| Finished | Aug 12 06:56:26 PM PDT 24 |
| Peak memory | 573560 kb |
| Host | smart-820c31f3-cf6e-43d2-88ff-942bdfaed100 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3233288536 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 74.xbar_smoke_zero_delay s.3233288536 |
| Directory | /workspace/74.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/74.xbar_stress_all.2590380711 |
| Short name | T1654 |
| Test name | |
| Test status | |
| Simulation time | 1066247112 ps |
| CPU time | 72.44 seconds |
| Started | Aug 12 06:56:17 PM PDT 24 |
| Finished | Aug 12 06:57:30 PM PDT 24 |
| Peak memory | 575764 kb |
| Host | smart-5da44d30-f5b0-49e2-8ef3-e36c1899c5d9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2590380711 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 74.xbar_stress_all.2590380711 |
| Directory | /workspace/74.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/74.xbar_stress_all_with_error.2550644998 |
| Short name | T2562 |
| Test name | |
| Test status | |
| Simulation time | 1176134335 ps |
| CPU time | 85.53 seconds |
| Started | Aug 12 06:56:20 PM PDT 24 |
| Finished | Aug 12 06:57:45 PM PDT 24 |
| Peak memory | 575760 kb |
| Host | smart-b14ff905-4f46-418b-9d64-89cbb248e6d3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2550644998 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 74.xbar_stress_all_with_error.2550644998 |
| Directory | /workspace/74.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/74.xbar_stress_all_with_rand_reset.2063005333 |
| Short name | T2546 |
| Test name | |
| Test status | |
| Simulation time | 105118463 ps |
| CPU time | 34.74 seconds |
| Started | Aug 12 06:56:17 PM PDT 24 |
| Finished | Aug 12 06:56:51 PM PDT 24 |
| Peak memory | 576168 kb |
| Host | smart-63577fa0-394e-4b77-a176-cf496c389def |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2063005333 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 74.xbar_stress_all _with_rand_reset.2063005333 |
| Directory | /workspace/74.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/74.xbar_stress_all_with_reset_error.1686235990 |
| Short name | T1674 |
| Test name | |
| Test status | |
| Simulation time | 2578567548 ps |
| CPU time | 367.23 seconds |
| Started | Aug 12 06:56:23 PM PDT 24 |
| Finished | Aug 12 07:02:31 PM PDT 24 |
| Peak memory | 576620 kb |
| Host | smart-a244a9ae-a9d8-41ae-8621-5f52a2f10fdc |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1686235990 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 74.xbar_stress_al l_with_reset_error.1686235990 |
| Directory | /workspace/74.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/74.xbar_unmapped_addr.1297632048 |
| Short name | T2568 |
| Test name | |
| Test status | |
| Simulation time | 743082509 ps |
| CPU time | 32.1 seconds |
| Started | Aug 12 06:56:16 PM PDT 24 |
| Finished | Aug 12 06:56:48 PM PDT 24 |
| Peak memory | 575752 kb |
| Host | smart-96675f95-fcc5-4172-9b62-7a29bb2850fb |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1297632048 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 74.xbar_unmapped_addr.1297632048 |
| Directory | /workspace/74.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/75.xbar_access_same_device.3532379222 |
| Short name | T1972 |
| Test name | |
| Test status | |
| Simulation time | 1096640032 ps |
| CPU time | 55.38 seconds |
| Started | Aug 12 06:56:28 PM PDT 24 |
| Finished | Aug 12 06:57:24 PM PDT 24 |
| Peak memory | 575732 kb |
| Host | smart-3c54703d-c31b-462b-8915-00e815066bf9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3532379222 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 75.xbar_access_same_device .3532379222 |
| Directory | /workspace/75.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/75.xbar_access_same_device_slow_rsp.2190809767 |
| Short name | T908 |
| Test name | |
| Test status | |
| Simulation time | 72348908772 ps |
| CPU time | 1320.69 seconds |
| Started | Aug 12 06:56:28 PM PDT 24 |
| Finished | Aug 12 07:18:28 PM PDT 24 |
| Peak memory | 575768 kb |
| Host | smart-29586e9a-00cd-487e-bd6c-c426682baf5a |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2190809767 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 75.xbar_access_same_ device_slow_rsp.2190809767 |
| Directory | /workspace/75.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/75.xbar_error_and_unmapped_addr.3490459265 |
| Short name | T1513 |
| Test name | |
| Test status | |
| Simulation time | 68254465 ps |
| CPU time | 10.12 seconds |
| Started | Aug 12 06:56:30 PM PDT 24 |
| Finished | Aug 12 06:56:41 PM PDT 24 |
| Peak memory | 575700 kb |
| Host | smart-746fb54c-c15e-4e2e-87a9-89d250456a5f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3490459265 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 75.xbar_error_and_unmapped_add r.3490459265 |
| Directory | /workspace/75.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/75.xbar_error_random.3777312312 |
| Short name | T1998 |
| Test name | |
| Test status | |
| Simulation time | 498003516 ps |
| CPU time | 39.19 seconds |
| Started | Aug 12 06:56:29 PM PDT 24 |
| Finished | Aug 12 06:57:08 PM PDT 24 |
| Peak memory | 575748 kb |
| Host | smart-b58c39d5-e132-4f8f-8877-a8dd35c9c750 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3777312312 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 75.xbar_error_random.3777312312 |
| Directory | /workspace/75.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/75.xbar_random.3935671729 |
| Short name | T661 |
| Test name | |
| Test status | |
| Simulation time | 803299231 ps |
| CPU time | 30.11 seconds |
| Started | Aug 12 06:56:28 PM PDT 24 |
| Finished | Aug 12 06:56:58 PM PDT 24 |
| Peak memory | 575600 kb |
| Host | smart-7a2967de-9e40-4af8-9922-d6d4965d5703 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3935671729 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 75.xbar_random.3935671729 |
| Directory | /workspace/75.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/75.xbar_random_large_delays.1308603037 |
| Short name | T2770 |
| Test name | |
| Test status | |
| Simulation time | 8137159925 ps |
| CPU time | 86.69 seconds |
| Started | Aug 12 06:56:29 PM PDT 24 |
| Finished | Aug 12 06:57:55 PM PDT 24 |
| Peak memory | 573684 kb |
| Host | smart-e84cc12d-9b3b-4316-babc-5ff38bb51669 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1308603037 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 75.xbar_random_large_delays.1308603037 |
| Directory | /workspace/75.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/75.xbar_random_slow_rsp.10790134 |
| Short name | T1932 |
| Test name | |
| Test status | |
| Simulation time | 17103643642 ps |
| CPU time | 289.96 seconds |
| Started | Aug 12 06:56:28 PM PDT 24 |
| Finished | Aug 12 07:01:19 PM PDT 24 |
| Peak memory | 575740 kb |
| Host | smart-ec566f0d-7567-45f2-9e68-5b58fd073338 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10790134 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 75.xbar_random_slow_rsp.10790134 |
| Directory | /workspace/75.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/75.xbar_random_zero_delays.1567215817 |
| Short name | T2590 |
| Test name | |
| Test status | |
| Simulation time | 344960996 ps |
| CPU time | 31.2 seconds |
| Started | Aug 12 06:56:30 PM PDT 24 |
| Finished | Aug 12 06:57:01 PM PDT 24 |
| Peak memory | 575596 kb |
| Host | smart-90420d32-fa66-4633-9024-622106f32ff1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1567215817 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 75.xbar_random_zero_del ays.1567215817 |
| Directory | /workspace/75.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/75.xbar_same_source.372071672 |
| Short name | T1871 |
| Test name | |
| Test status | |
| Simulation time | 2542498520 ps |
| CPU time | 71.01 seconds |
| Started | Aug 12 06:56:30 PM PDT 24 |
| Finished | Aug 12 06:57:41 PM PDT 24 |
| Peak memory | 575744 kb |
| Host | smart-8c68564b-a55f-49a8-b7a0-a8e80e0e8c00 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=372071672 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 75.xbar_same_source.372071672 |
| Directory | /workspace/75.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/75.xbar_smoke.2647987328 |
| Short name | T2507 |
| Test name | |
| Test status | |
| Simulation time | 175921639 ps |
| CPU time | 8.61 seconds |
| Started | Aug 12 06:56:28 PM PDT 24 |
| Finished | Aug 12 06:56:36 PM PDT 24 |
| Peak memory | 573588 kb |
| Host | smart-8fbfbecd-23c0-45bd-9f52-791f26f04231 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2647987328 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 75.xbar_smoke.2647987328 |
| Directory | /workspace/75.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/75.xbar_smoke_large_delays.131798239 |
| Short name | T1727 |
| Test name | |
| Test status | |
| Simulation time | 10403388335 ps |
| CPU time | 108.97 seconds |
| Started | Aug 12 06:56:29 PM PDT 24 |
| Finished | Aug 12 06:58:18 PM PDT 24 |
| Peak memory | 573704 kb |
| Host | smart-132e04f5-6f51-4859-bf46-d1e2e877db60 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=131798239 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 75.xbar_smoke_large_delays.131798239 |
| Directory | /workspace/75.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/75.xbar_smoke_slow_rsp.144938346 |
| Short name | T1682 |
| Test name | |
| Test status | |
| Simulation time | 4684678606 ps |
| CPU time | 82.95 seconds |
| Started | Aug 12 06:56:28 PM PDT 24 |
| Finished | Aug 12 06:57:51 PM PDT 24 |
| Peak memory | 574356 kb |
| Host | smart-1ddee0b7-544f-4b1c-b1b1-f12f59ea62f5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=144938346 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 75.xbar_smoke_slow_rsp.144938346 |
| Directory | /workspace/75.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/75.xbar_smoke_zero_delays.2574832466 |
| Short name | T2101 |
| Test name | |
| Test status | |
| Simulation time | 52202761 ps |
| CPU time | 6.93 seconds |
| Started | Aug 12 06:56:26 PM PDT 24 |
| Finished | Aug 12 06:56:33 PM PDT 24 |
| Peak memory | 574268 kb |
| Host | smart-a6b3a70b-dc6f-49f7-a39b-f1926a8b76dc |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2574832466 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 75.xbar_smoke_zero_delay s.2574832466 |
| Directory | /workspace/75.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/75.xbar_stress_all.458042862 |
| Short name | T422 |
| Test name | |
| Test status | |
| Simulation time | 7867070104 ps |
| CPU time | 274.49 seconds |
| Started | Aug 12 06:56:31 PM PDT 24 |
| Finished | Aug 12 07:01:05 PM PDT 24 |
| Peak memory | 575736 kb |
| Host | smart-d56ce0df-69ee-462f-963f-00ac7f1f30fa |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=458042862 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 75.xbar_stress_all.458042862 |
| Directory | /workspace/75.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/75.xbar_stress_all_with_error.2522459524 |
| Short name | T2058 |
| Test name | |
| Test status | |
| Simulation time | 546646230 ps |
| CPU time | 39.45 seconds |
| Started | Aug 12 06:56:30 PM PDT 24 |
| Finished | Aug 12 06:57:10 PM PDT 24 |
| Peak memory | 575728 kb |
| Host | smart-235a06b8-509c-4a55-bc26-9577a0c0320f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2522459524 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 75.xbar_stress_all_with_error.2522459524 |
| Directory | /workspace/75.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/75.xbar_stress_all_with_rand_reset.3927677009 |
| Short name | T2319 |
| Test name | |
| Test status | |
| Simulation time | 187874565 ps |
| CPU time | 119.38 seconds |
| Started | Aug 12 06:56:28 PM PDT 24 |
| Finished | Aug 12 06:58:28 PM PDT 24 |
| Peak memory | 575732 kb |
| Host | smart-0ed04600-e22b-4128-b67a-1352ed66ca26 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3927677009 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 75.xbar_stress_all _with_rand_reset.3927677009 |
| Directory | /workspace/75.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/75.xbar_stress_all_with_reset_error.1424028333 |
| Short name | T2655 |
| Test name | |
| Test status | |
| Simulation time | 405885002 ps |
| CPU time | 122.95 seconds |
| Started | Aug 12 06:56:30 PM PDT 24 |
| Finished | Aug 12 06:58:33 PM PDT 24 |
| Peak memory | 576540 kb |
| Host | smart-3f90be63-abf9-4558-9f9b-ae76d17cec32 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1424028333 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 75.xbar_stress_al l_with_reset_error.1424028333 |
| Directory | /workspace/75.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/75.xbar_unmapped_addr.1049836755 |
| Short name | T2772 |
| Test name | |
| Test status | |
| Simulation time | 810203749 ps |
| CPU time | 37.94 seconds |
| Started | Aug 12 06:56:28 PM PDT 24 |
| Finished | Aug 12 06:57:06 PM PDT 24 |
| Peak memory | 575760 kb |
| Host | smart-9a7f44bf-f855-49a6-b7f0-e6210b536ae7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1049836755 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 75.xbar_unmapped_addr.1049836755 |
| Directory | /workspace/75.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/76.xbar_access_same_device.2032324629 |
| Short name | T2766 |
| Test name | |
| Test status | |
| Simulation time | 2204355038 ps |
| CPU time | 94.12 seconds |
| Started | Aug 12 06:56:39 PM PDT 24 |
| Finished | Aug 12 06:58:13 PM PDT 24 |
| Peak memory | 575856 kb |
| Host | smart-d1e219fe-5100-4f39-a404-4aa281b53099 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2032324629 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 76.xbar_access_same_device .2032324629 |
| Directory | /workspace/76.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/76.xbar_access_same_device_slow_rsp.3964750664 |
| Short name | T2100 |
| Test name | |
| Test status | |
| Simulation time | 79562882150 ps |
| CPU time | 1402.91 seconds |
| Started | Aug 12 06:56:43 PM PDT 24 |
| Finished | Aug 12 07:20:07 PM PDT 24 |
| Peak memory | 575868 kb |
| Host | smart-eb00bc99-d8bd-4bda-8fce-e86deb6a4acf |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3964750664 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 76.xbar_access_same_ device_slow_rsp.3964750664 |
| Directory | /workspace/76.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/76.xbar_error_and_unmapped_addr.2075003232 |
| Short name | T2780 |
| Test name | |
| Test status | |
| Simulation time | 1038351363 ps |
| CPU time | 45.45 seconds |
| Started | Aug 12 06:56:46 PM PDT 24 |
| Finished | Aug 12 06:57:32 PM PDT 24 |
| Peak memory | 575728 kb |
| Host | smart-20e3746d-ff9d-4315-8700-03b0b5b8bd06 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2075003232 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 76.xbar_error_and_unmapped_add r.2075003232 |
| Directory | /workspace/76.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/76.xbar_error_random.711469413 |
| Short name | T2741 |
| Test name | |
| Test status | |
| Simulation time | 868942715 ps |
| CPU time | 28.18 seconds |
| Started | Aug 12 06:56:40 PM PDT 24 |
| Finished | Aug 12 06:57:08 PM PDT 24 |
| Peak memory | 575692 kb |
| Host | smart-2f475864-8019-45c3-8c09-d4cfa6747022 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=711469413 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 76.xbar_error_random.711469413 |
| Directory | /workspace/76.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/76.xbar_random.3101371873 |
| Short name | T703 |
| Test name | |
| Test status | |
| Simulation time | 1032237819 ps |
| CPU time | 40.81 seconds |
| Started | Aug 12 06:56:28 PM PDT 24 |
| Finished | Aug 12 06:57:09 PM PDT 24 |
| Peak memory | 575644 kb |
| Host | smart-9e8a931b-ab26-4f69-881f-b2330e1182a4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3101371873 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 76.xbar_random.3101371873 |
| Directory | /workspace/76.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/76.xbar_random_large_delays.3419771915 |
| Short name | T1652 |
| Test name | |
| Test status | |
| Simulation time | 36220710372 ps |
| CPU time | 409.89 seconds |
| Started | Aug 12 06:56:39 PM PDT 24 |
| Finished | Aug 12 07:03:29 PM PDT 24 |
| Peak memory | 575780 kb |
| Host | smart-4efc71d4-5ab8-4d29-b07e-aef3c26df6d9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3419771915 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 76.xbar_random_large_delays.3419771915 |
| Directory | /workspace/76.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/76.xbar_random_slow_rsp.2642006967 |
| Short name | T1505 |
| Test name | |
| Test status | |
| Simulation time | 30830655496 ps |
| CPU time | 530.38 seconds |
| Started | Aug 12 06:56:40 PM PDT 24 |
| Finished | Aug 12 07:05:31 PM PDT 24 |
| Peak memory | 575724 kb |
| Host | smart-8c79bda1-ddb4-4347-8d66-129b36c4d6ad |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2642006967 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 76.xbar_random_slow_rsp.2642006967 |
| Directory | /workspace/76.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/76.xbar_random_zero_delays.173223352 |
| Short name | T1922 |
| Test name | |
| Test status | |
| Simulation time | 184817090 ps |
| CPU time | 17.36 seconds |
| Started | Aug 12 06:56:41 PM PDT 24 |
| Finished | Aug 12 06:56:58 PM PDT 24 |
| Peak memory | 575544 kb |
| Host | smart-89e69d57-bfa0-4061-ba3a-09229accbdae |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=173223352 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 76.xbar_random_zero_dela ys.173223352 |
| Directory | /workspace/76.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/76.xbar_same_source.3424105947 |
| Short name | T2939 |
| Test name | |
| Test status | |
| Simulation time | 1069813639 ps |
| CPU time | 35 seconds |
| Started | Aug 12 06:56:38 PM PDT 24 |
| Finished | Aug 12 06:57:13 PM PDT 24 |
| Peak memory | 575676 kb |
| Host | smart-cc5f5e8b-d520-41b9-b8d9-b6d36af4700a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3424105947 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 76.xbar_same_source.3424105947 |
| Directory | /workspace/76.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/76.xbar_smoke.1726230856 |
| Short name | T1667 |
| Test name | |
| Test status | |
| Simulation time | 214150844 ps |
| CPU time | 8.92 seconds |
| Started | Aug 12 06:56:29 PM PDT 24 |
| Finished | Aug 12 06:56:38 PM PDT 24 |
| Peak memory | 574276 kb |
| Host | smart-b5553e37-2a00-4cef-bf14-b6eb91b8e2bd |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1726230856 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 76.xbar_smoke.1726230856 |
| Directory | /workspace/76.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/76.xbar_smoke_large_delays.697417953 |
| Short name | T2521 |
| Test name | |
| Test status | |
| Simulation time | 4613749185 ps |
| CPU time | 46.76 seconds |
| Started | Aug 12 06:56:30 PM PDT 24 |
| Finished | Aug 12 06:57:17 PM PDT 24 |
| Peak memory | 573644 kb |
| Host | smart-fbf6c40b-09fa-438d-b129-bec16e237403 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=697417953 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 76.xbar_smoke_large_delays.697417953 |
| Directory | /workspace/76.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/76.xbar_smoke_slow_rsp.553069852 |
| Short name | T1725 |
| Test name | |
| Test status | |
| Simulation time | 3695936383 ps |
| CPU time | 61.54 seconds |
| Started | Aug 12 06:56:28 PM PDT 24 |
| Finished | Aug 12 06:57:30 PM PDT 24 |
| Peak memory | 574340 kb |
| Host | smart-26d4cb06-8399-47ef-99e6-ad215eb7d7e3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=553069852 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 76.xbar_smoke_slow_rsp.553069852 |
| Directory | /workspace/76.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/76.xbar_smoke_zero_delays.41791252 |
| Short name | T2749 |
| Test name | |
| Test status | |
| Simulation time | 51956899 ps |
| CPU time | 6.51 seconds |
| Started | Aug 12 06:56:29 PM PDT 24 |
| Finished | Aug 12 06:56:35 PM PDT 24 |
| Peak memory | 573612 kb |
| Host | smart-550e9d92-9a3f-441e-a494-40c2c53b7697 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41791252 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 76.xbar_smoke_zero_delays.41791252 |
| Directory | /workspace/76.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/76.xbar_stress_all.1696935502 |
| Short name | T724 |
| Test name | |
| Test status | |
| Simulation time | 9761244951 ps |
| CPU time | 341.05 seconds |
| Started | Aug 12 06:56:45 PM PDT 24 |
| Finished | Aug 12 07:02:27 PM PDT 24 |
| Peak memory | 575752 kb |
| Host | smart-85e28ee5-71f3-4ecc-b1d8-d18b3b232c79 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1696935502 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 76.xbar_stress_all.1696935502 |
| Directory | /workspace/76.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/76.xbar_stress_all_with_error.4016527175 |
| Short name | T912 |
| Test name | |
| Test status | |
| Simulation time | 12918530077 ps |
| CPU time | 498.92 seconds |
| Started | Aug 12 06:56:40 PM PDT 24 |
| Finished | Aug 12 07:05:00 PM PDT 24 |
| Peak memory | 576588 kb |
| Host | smart-799b97dc-2d59-47b4-8273-f90cad0882b5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4016527175 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 76.xbar_stress_all_with_error.4016527175 |
| Directory | /workspace/76.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/76.xbar_stress_all_with_reset_error.1630773505 |
| Short name | T2353 |
| Test name | |
| Test status | |
| Simulation time | 5883811328 ps |
| CPU time | 607.29 seconds |
| Started | Aug 12 06:56:46 PM PDT 24 |
| Finished | Aug 12 07:06:54 PM PDT 24 |
| Peak memory | 576520 kb |
| Host | smart-325fe063-9210-4491-a6b4-96e573f9dd36 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1630773505 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 76.xbar_stress_al l_with_reset_error.1630773505 |
| Directory | /workspace/76.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/76.xbar_unmapped_addr.2398323862 |
| Short name | T652 |
| Test name | |
| Test status | |
| Simulation time | 179548752 ps |
| CPU time | 20.21 seconds |
| Started | Aug 12 06:56:38 PM PDT 24 |
| Finished | Aug 12 06:56:59 PM PDT 24 |
| Peak memory | 575756 kb |
| Host | smart-7e29a623-522b-453b-b1f5-013a90d322d2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2398323862 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 76.xbar_unmapped_addr.2398323862 |
| Directory | /workspace/76.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/77.xbar_access_same_device.1769158500 |
| Short name | T1645 |
| Test name | |
| Test status | |
| Simulation time | 1957574792 ps |
| CPU time | 81.38 seconds |
| Started | Aug 12 06:56:40 PM PDT 24 |
| Finished | Aug 12 06:58:02 PM PDT 24 |
| Peak memory | 575824 kb |
| Host | smart-4d1e77d3-0286-4e2a-8283-24bb618accd6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1769158500 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 77.xbar_access_same_device .1769158500 |
| Directory | /workspace/77.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/77.xbar_error_and_unmapped_addr.196332857 |
| Short name | T1566 |
| Test name | |
| Test status | |
| Simulation time | 1293766718 ps |
| CPU time | 48.73 seconds |
| Started | Aug 12 06:56:40 PM PDT 24 |
| Finished | Aug 12 06:57:29 PM PDT 24 |
| Peak memory | 575520 kb |
| Host | smart-01c38377-5900-4482-9665-7f5920297cbe |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=196332857 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 77.xbar_error_and_unmapped_addr .196332857 |
| Directory | /workspace/77.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/77.xbar_error_random.2134239649 |
| Short name | T1878 |
| Test name | |
| Test status | |
| Simulation time | 2109954515 ps |
| CPU time | 79.37 seconds |
| Started | Aug 12 06:56:40 PM PDT 24 |
| Finished | Aug 12 06:57:59 PM PDT 24 |
| Peak memory | 575708 kb |
| Host | smart-4c3a6935-c2a0-434b-82b0-0e8a54b907ec |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2134239649 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 77.xbar_error_random.2134239649 |
| Directory | /workspace/77.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/77.xbar_random.467051001 |
| Short name | T1863 |
| Test name | |
| Test status | |
| Simulation time | 1998841714 ps |
| CPU time | 72.92 seconds |
| Started | Aug 12 06:56:39 PM PDT 24 |
| Finished | Aug 12 06:57:52 PM PDT 24 |
| Peak memory | 575616 kb |
| Host | smart-d15a4d7a-7b5e-4734-a801-5dc4c9795042 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=467051001 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 77.xbar_random.467051001 |
| Directory | /workspace/77.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/77.xbar_random_large_delays.298214845 |
| Short name | T668 |
| Test name | |
| Test status | |
| Simulation time | 30874583503 ps |
| CPU time | 314.51 seconds |
| Started | Aug 12 06:56:41 PM PDT 24 |
| Finished | Aug 12 07:01:56 PM PDT 24 |
| Peak memory | 575820 kb |
| Host | smart-3767d79f-ef6c-404d-9f5f-9551218f9e87 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=298214845 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 77.xbar_random_large_delays.298214845 |
| Directory | /workspace/77.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/77.xbar_random_slow_rsp.49456327 |
| Short name | T2598 |
| Test name | |
| Test status | |
| Simulation time | 55689326025 ps |
| CPU time | 1031.09 seconds |
| Started | Aug 12 06:56:39 PM PDT 24 |
| Finished | Aug 12 07:13:51 PM PDT 24 |
| Peak memory | 575704 kb |
| Host | smart-7222d782-d44f-4df5-97ab-2b152e531590 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49456327 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 77.xbar_random_slow_rsp.49456327 |
| Directory | /workspace/77.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/77.xbar_random_zero_delays.1069981290 |
| Short name | T1960 |
| Test name | |
| Test status | |
| Simulation time | 332245711 ps |
| CPU time | 30.99 seconds |
| Started | Aug 12 06:56:40 PM PDT 24 |
| Finished | Aug 12 06:57:11 PM PDT 24 |
| Peak memory | 575708 kb |
| Host | smart-32df30d4-5af4-457c-b5ed-14354f5ea060 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1069981290 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 77.xbar_random_zero_del ays.1069981290 |
| Directory | /workspace/77.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/77.xbar_same_source.1482348309 |
| Short name | T1988 |
| Test name | |
| Test status | |
| Simulation time | 968779606 ps |
| CPU time | 29.38 seconds |
| Started | Aug 12 06:56:45 PM PDT 24 |
| Finished | Aug 12 06:57:14 PM PDT 24 |
| Peak memory | 575552 kb |
| Host | smart-d4ecfe15-118a-457b-bdb8-6d2fcaa774ed |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1482348309 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 77.xbar_same_source.1482348309 |
| Directory | /workspace/77.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/77.xbar_smoke.3413970195 |
| Short name | T1986 |
| Test name | |
| Test status | |
| Simulation time | 237929304 ps |
| CPU time | 9.43 seconds |
| Started | Aug 12 06:56:39 PM PDT 24 |
| Finished | Aug 12 06:56:48 PM PDT 24 |
| Peak memory | 573572 kb |
| Host | smart-23ac7249-7c50-4e8e-8b29-107491ef965e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3413970195 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 77.xbar_smoke.3413970195 |
| Directory | /workspace/77.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/77.xbar_smoke_large_delays.641903914 |
| Short name | T1525 |
| Test name | |
| Test status | |
| Simulation time | 7545634932 ps |
| CPU time | 75.98 seconds |
| Started | Aug 12 06:56:42 PM PDT 24 |
| Finished | Aug 12 06:57:58 PM PDT 24 |
| Peak memory | 573656 kb |
| Host | smart-f8e17659-6514-43d5-acb0-a32c2ed2eec0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=641903914 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 77.xbar_smoke_large_delays.641903914 |
| Directory | /workspace/77.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/77.xbar_smoke_slow_rsp.2637696863 |
| Short name | T1948 |
| Test name | |
| Test status | |
| Simulation time | 5604828435 ps |
| CPU time | 94.54 seconds |
| Started | Aug 12 06:56:45 PM PDT 24 |
| Finished | Aug 12 06:58:20 PM PDT 24 |
| Peak memory | 573704 kb |
| Host | smart-fb244ec8-3a53-42d5-b947-f2f71572ea4b |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2637696863 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 77.xbar_smoke_slow_rsp.2637696863 |
| Directory | /workspace/77.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/77.xbar_smoke_zero_delays.1624459654 |
| Short name | T1583 |
| Test name | |
| Test status | |
| Simulation time | 51850471 ps |
| CPU time | 5.96 seconds |
| Started | Aug 12 06:56:40 PM PDT 24 |
| Finished | Aug 12 06:56:46 PM PDT 24 |
| Peak memory | 574288 kb |
| Host | smart-b53b1408-fec2-4a63-b298-b824b41f0a89 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1624459654 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 77.xbar_smoke_zero_delay s.1624459654 |
| Directory | /workspace/77.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/77.xbar_stress_all.2236099130 |
| Short name | T1806 |
| Test name | |
| Test status | |
| Simulation time | 8117126952 ps |
| CPU time | 329.91 seconds |
| Started | Aug 12 06:56:46 PM PDT 24 |
| Finished | Aug 12 07:02:16 PM PDT 24 |
| Peak memory | 575704 kb |
| Host | smart-eb18dbe2-8615-4a79-ab1a-20d2e7a2683a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2236099130 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 77.xbar_stress_all.2236099130 |
| Directory | /workspace/77.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/77.xbar_stress_all_with_error.1321021801 |
| Short name | T1665 |
| Test name | |
| Test status | |
| Simulation time | 8057441382 ps |
| CPU time | 237.45 seconds |
| Started | Aug 12 06:56:50 PM PDT 24 |
| Finished | Aug 12 07:00:48 PM PDT 24 |
| Peak memory | 575960 kb |
| Host | smart-114f0d3b-e852-41c8-8efc-14098ff5e7f4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1321021801 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 77.xbar_stress_all_with_error.1321021801 |
| Directory | /workspace/77.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/77.xbar_stress_all_with_rand_reset.3015017111 |
| Short name | T2563 |
| Test name | |
| Test status | |
| Simulation time | 135196922 ps |
| CPU time | 77.83 seconds |
| Started | Aug 12 06:56:39 PM PDT 24 |
| Finished | Aug 12 06:57:57 PM PDT 24 |
| Peak memory | 576572 kb |
| Host | smart-2327b03e-3887-4c19-91ec-cf0fd9c8ab42 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3015017111 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 77.xbar_stress_all _with_rand_reset.3015017111 |
| Directory | /workspace/77.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/77.xbar_stress_all_with_reset_error.4154343921 |
| Short name | T945 |
| Test name | |
| Test status | |
| Simulation time | 6938041361 ps |
| CPU time | 422.38 seconds |
| Started | Aug 12 06:57:01 PM PDT 24 |
| Finished | Aug 12 07:04:03 PM PDT 24 |
| Peak memory | 576600 kb |
| Host | smart-119c3fbf-1137-4901-8e2b-949a6c23742e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4154343921 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 77.xbar_stress_al l_with_reset_error.4154343921 |
| Directory | /workspace/77.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/77.xbar_unmapped_addr.3266468021 |
| Short name | T1699 |
| Test name | |
| Test status | |
| Simulation time | 1256262932 ps |
| CPU time | 46.21 seconds |
| Started | Aug 12 06:56:47 PM PDT 24 |
| Finished | Aug 12 06:57:33 PM PDT 24 |
| Peak memory | 575768 kb |
| Host | smart-21dc96ee-9922-4a59-983c-6b58f748afc3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3266468021 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 77.xbar_unmapped_addr.3266468021 |
| Directory | /workspace/77.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/78.xbar_access_same_device.1529296279 |
| Short name | T2146 |
| Test name | |
| Test status | |
| Simulation time | 829157575 ps |
| CPU time | 56.58 seconds |
| Started | Aug 12 06:57:00 PM PDT 24 |
| Finished | Aug 12 06:57:57 PM PDT 24 |
| Peak memory | 575532 kb |
| Host | smart-7e6bc74a-85b8-4bd8-b11c-205583558ab0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1529296279 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 78.xbar_access_same_device .1529296279 |
| Directory | /workspace/78.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/78.xbar_access_same_device_slow_rsp.2242354144 |
| Short name | T2171 |
| Test name | |
| Test status | |
| Simulation time | 91335746946 ps |
| CPU time | 1831.49 seconds |
| Started | Aug 12 06:56:50 PM PDT 24 |
| Finished | Aug 12 07:27:22 PM PDT 24 |
| Peak memory | 575828 kb |
| Host | smart-2148ebe0-4bee-4f45-84cc-40267f632a84 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2242354144 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 78.xbar_access_same_ device_slow_rsp.2242354144 |
| Directory | /workspace/78.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/78.xbar_error_and_unmapped_addr.1876036007 |
| Short name | T1518 |
| Test name | |
| Test status | |
| Simulation time | 794312720 ps |
| CPU time | 31.37 seconds |
| Started | Aug 12 06:56:53 PM PDT 24 |
| Finished | Aug 12 06:57:25 PM PDT 24 |
| Peak memory | 575696 kb |
| Host | smart-efdefe37-4c29-44b6-a52e-cb30d38aac72 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1876036007 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 78.xbar_error_and_unmapped_add r.1876036007 |
| Directory | /workspace/78.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/78.xbar_error_random.2663412676 |
| Short name | T1532 |
| Test name | |
| Test status | |
| Simulation time | 448399406 ps |
| CPU time | 33.09 seconds |
| Started | Aug 12 06:56:48 PM PDT 24 |
| Finished | Aug 12 06:57:22 PM PDT 24 |
| Peak memory | 575748 kb |
| Host | smart-a69a218c-e7d9-4255-9b45-1789606b7923 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2663412676 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 78.xbar_error_random.2663412676 |
| Directory | /workspace/78.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/78.xbar_random.1817786879 |
| Short name | T2823 |
| Test name | |
| Test status | |
| Simulation time | 461711285 ps |
| CPU time | 18.94 seconds |
| Started | Aug 12 06:56:49 PM PDT 24 |
| Finished | Aug 12 06:57:09 PM PDT 24 |
| Peak memory | 575676 kb |
| Host | smart-b67ed828-fc10-4e8f-b272-f6c8d148a701 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1817786879 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 78.xbar_random.1817786879 |
| Directory | /workspace/78.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/78.xbar_random_large_delays.3418349534 |
| Short name | T451 |
| Test name | |
| Test status | |
| Simulation time | 54076924917 ps |
| CPU time | 636.54 seconds |
| Started | Aug 12 06:56:51 PM PDT 24 |
| Finished | Aug 12 07:07:28 PM PDT 24 |
| Peak memory | 575720 kb |
| Host | smart-cdcd09ba-530a-4e0a-baae-da72e964c406 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3418349534 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 78.xbar_random_large_delays.3418349534 |
| Directory | /workspace/78.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/78.xbar_random_slow_rsp.3535666902 |
| Short name | T681 |
| Test name | |
| Test status | |
| Simulation time | 10522651945 ps |
| CPU time | 177.57 seconds |
| Started | Aug 12 06:56:49 PM PDT 24 |
| Finished | Aug 12 06:59:47 PM PDT 24 |
| Peak memory | 575708 kb |
| Host | smart-bc0c5703-a9a4-4c5e-8b5a-d3f8c7695ab3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3535666902 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 78.xbar_random_slow_rsp.3535666902 |
| Directory | /workspace/78.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/78.xbar_random_zero_delays.1310937012 |
| Short name | T2501 |
| Test name | |
| Test status | |
| Simulation time | 257162560 ps |
| CPU time | 22.83 seconds |
| Started | Aug 12 06:56:56 PM PDT 24 |
| Finished | Aug 12 06:57:19 PM PDT 24 |
| Peak memory | 575580 kb |
| Host | smart-174d1e5d-c089-401b-9860-03745a8101b9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1310937012 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 78.xbar_random_zero_del ays.1310937012 |
| Directory | /workspace/78.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/78.xbar_same_source.630303243 |
| Short name | T2634 |
| Test name | |
| Test status | |
| Simulation time | 2412366919 ps |
| CPU time | 73.16 seconds |
| Started | Aug 12 06:56:54 PM PDT 24 |
| Finished | Aug 12 06:58:07 PM PDT 24 |
| Peak memory | 575588 kb |
| Host | smart-a5cd1f85-be32-4d94-905f-c71cde836035 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=630303243 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 78.xbar_same_source.630303243 |
| Directory | /workspace/78.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/78.xbar_smoke.1939810575 |
| Short name | T2359 |
| Test name | |
| Test status | |
| Simulation time | 52909470 ps |
| CPU time | 6.24 seconds |
| Started | Aug 12 06:56:50 PM PDT 24 |
| Finished | Aug 12 06:56:57 PM PDT 24 |
| Peak memory | 573624 kb |
| Host | smart-22561bab-1015-489e-9c9e-fe6abbd73eb9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1939810575 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 78.xbar_smoke.1939810575 |
| Directory | /workspace/78.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/78.xbar_smoke_large_delays.3985394388 |
| Short name | T1851 |
| Test name | |
| Test status | |
| Simulation time | 10423212542 ps |
| CPU time | 108.36 seconds |
| Started | Aug 12 06:56:50 PM PDT 24 |
| Finished | Aug 12 06:58:39 PM PDT 24 |
| Peak memory | 573604 kb |
| Host | smart-1a9491d2-be81-42a3-a598-a7546db38d8e |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3985394388 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 78.xbar_smoke_large_delays.3985394388 |
| Directory | /workspace/78.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/78.xbar_smoke_slow_rsp.745495502 |
| Short name | T664 |
| Test name | |
| Test status | |
| Simulation time | 3932790901 ps |
| CPU time | 64.5 seconds |
| Started | Aug 12 06:57:00 PM PDT 24 |
| Finished | Aug 12 06:58:05 PM PDT 24 |
| Peak memory | 573608 kb |
| Host | smart-584487ad-d858-4ae3-b7c8-3b64f08d4289 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=745495502 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 78.xbar_smoke_slow_rsp.745495502 |
| Directory | /workspace/78.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/78.xbar_smoke_zero_delays.1676167112 |
| Short name | T1896 |
| Test name | |
| Test status | |
| Simulation time | 50515538 ps |
| CPU time | 6.36 seconds |
| Started | Aug 12 06:56:50 PM PDT 24 |
| Finished | Aug 12 06:56:56 PM PDT 24 |
| Peak memory | 573608 kb |
| Host | smart-6d1f7ac5-7f9d-4dfb-9c92-efc0daea5fe0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1676167112 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 78.xbar_smoke_zero_delay s.1676167112 |
| Directory | /workspace/78.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/78.xbar_stress_all_with_error.2588391445 |
| Short name | T2543 |
| Test name | |
| Test status | |
| Simulation time | 17335612061 ps |
| CPU time | 647.25 seconds |
| Started | Aug 12 06:56:54 PM PDT 24 |
| Finished | Aug 12 07:07:42 PM PDT 24 |
| Peak memory | 575736 kb |
| Host | smart-efb3585f-91c6-401a-990f-747b4d9b4b0f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2588391445 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 78.xbar_stress_all_with_error.2588391445 |
| Directory | /workspace/78.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/78.xbar_stress_all_with_reset_error.819889225 |
| Short name | T2599 |
| Test name | |
| Test status | |
| Simulation time | 2186362417 ps |
| CPU time | 203.76 seconds |
| Started | Aug 12 06:56:56 PM PDT 24 |
| Finished | Aug 12 07:00:20 PM PDT 24 |
| Peak memory | 575788 kb |
| Host | smart-4421f24a-f75a-474c-a555-15513c779ff1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=819889225 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 78.xbar_stress_all _with_reset_error.819889225 |
| Directory | /workspace/78.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/78.xbar_unmapped_addr.2564083168 |
| Short name | T2620 |
| Test name | |
| Test status | |
| Simulation time | 1468562826 ps |
| CPU time | 64.38 seconds |
| Started | Aug 12 06:56:50 PM PDT 24 |
| Finished | Aug 12 06:57:54 PM PDT 24 |
| Peak memory | 575780 kb |
| Host | smart-df064e20-43b6-4b64-8609-d976cee65992 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2564083168 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 78.xbar_unmapped_addr.2564083168 |
| Directory | /workspace/78.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/79.xbar_access_same_device.3950066499 |
| Short name | T2166 |
| Test name | |
| Test status | |
| Simulation time | 3329116528 ps |
| CPU time | 140.86 seconds |
| Started | Aug 12 06:57:01 PM PDT 24 |
| Finished | Aug 12 06:59:22 PM PDT 24 |
| Peak memory | 575684 kb |
| Host | smart-894efc87-dcf9-4328-ad2b-30181f998bab |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3950066499 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 79.xbar_access_same_device .3950066499 |
| Directory | /workspace/79.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/79.xbar_access_same_device_slow_rsp.2508283742 |
| Short name | T2579 |
| Test name | |
| Test status | |
| Simulation time | 104358995804 ps |
| CPU time | 1900.64 seconds |
| Started | Aug 12 06:57:01 PM PDT 24 |
| Finished | Aug 12 07:28:42 PM PDT 24 |
| Peak memory | 575812 kb |
| Host | smart-f5a83613-f12b-4ede-9eb9-6903daf4b647 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2508283742 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 79.xbar_access_same_ device_slow_rsp.2508283742 |
| Directory | /workspace/79.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/79.xbar_error_and_unmapped_addr.3015618502 |
| Short name | T2053 |
| Test name | |
| Test status | |
| Simulation time | 304331522 ps |
| CPU time | 35.16 seconds |
| Started | Aug 12 06:57:00 PM PDT 24 |
| Finished | Aug 12 06:57:35 PM PDT 24 |
| Peak memory | 575660 kb |
| Host | smart-23773ec2-ae4f-41f9-8bb7-47dab661f815 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3015618502 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 79.xbar_error_and_unmapped_add r.3015618502 |
| Directory | /workspace/79.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/79.xbar_error_random.3334803042 |
| Short name | T1701 |
| Test name | |
| Test status | |
| Simulation time | 192737868 ps |
| CPU time | 16.86 seconds |
| Started | Aug 12 06:57:03 PM PDT 24 |
| Finished | Aug 12 06:57:20 PM PDT 24 |
| Peak memory | 575688 kb |
| Host | smart-d31d9e33-540b-41c7-8886-799d2ce64eda |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3334803042 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 79.xbar_error_random.3334803042 |
| Directory | /workspace/79.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/79.xbar_random.2524186675 |
| Short name | T650 |
| Test name | |
| Test status | |
| Simulation time | 312509891 ps |
| CPU time | 24.68 seconds |
| Started | Aug 12 06:57:00 PM PDT 24 |
| Finished | Aug 12 06:57:24 PM PDT 24 |
| Peak memory | 575624 kb |
| Host | smart-1bb27347-35ee-4a7e-80fb-ed342191d6cf |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2524186675 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 79.xbar_random.2524186675 |
| Directory | /workspace/79.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/79.xbar_random_large_delays.3252193665 |
| Short name | T679 |
| Test name | |
| Test status | |
| Simulation time | 36552953787 ps |
| CPU time | 375.57 seconds |
| Started | Aug 12 06:57:02 PM PDT 24 |
| Finished | Aug 12 07:03:19 PM PDT 24 |
| Peak memory | 575640 kb |
| Host | smart-b739a388-4feb-4cdb-b0d0-475f0c887196 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3252193665 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 79.xbar_random_large_delays.3252193665 |
| Directory | /workspace/79.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/79.xbar_random_slow_rsp.1879764353 |
| Short name | T2852 |
| Test name | |
| Test status | |
| Simulation time | 3828847333 ps |
| CPU time | 61.66 seconds |
| Started | Aug 12 06:57:06 PM PDT 24 |
| Finished | Aug 12 06:58:08 PM PDT 24 |
| Peak memory | 573632 kb |
| Host | smart-3517cc32-a86a-4cba-95d1-97a8fc1061e6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1879764353 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 79.xbar_random_slow_rsp.1879764353 |
| Directory | /workspace/79.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/79.xbar_random_zero_delays.3755075676 |
| Short name | T598 |
| Test name | |
| Test status | |
| Simulation time | 309372459 ps |
| CPU time | 24.56 seconds |
| Started | Aug 12 06:56:53 PM PDT 24 |
| Finished | Aug 12 06:57:18 PM PDT 24 |
| Peak memory | 575740 kb |
| Host | smart-526a25d1-0438-4eeb-bea4-c7ad7b5a90e0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3755075676 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 79.xbar_random_zero_del ays.3755075676 |
| Directory | /workspace/79.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/79.xbar_same_source.2140072937 |
| Short name | T2747 |
| Test name | |
| Test status | |
| Simulation time | 696357928 ps |
| CPU time | 20.07 seconds |
| Started | Aug 12 06:56:58 PM PDT 24 |
| Finished | Aug 12 06:57:18 PM PDT 24 |
| Peak memory | 575492 kb |
| Host | smart-e371c71a-75d8-47cc-a474-251728964aa0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2140072937 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 79.xbar_same_source.2140072937 |
| Directory | /workspace/79.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/79.xbar_smoke.426212051 |
| Short name | T2797 |
| Test name | |
| Test status | |
| Simulation time | 200727019 ps |
| CPU time | 8.48 seconds |
| Started | Aug 12 06:56:49 PM PDT 24 |
| Finished | Aug 12 06:56:58 PM PDT 24 |
| Peak memory | 574272 kb |
| Host | smart-8a34d76c-b8a6-45cf-a13e-5030a7a8a19c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=426212051 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 79.xbar_smoke.426212051 |
| Directory | /workspace/79.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/79.xbar_smoke_large_delays.2547423756 |
| Short name | T1893 |
| Test name | |
| Test status | |
| Simulation time | 7961709089 ps |
| CPU time | 79.05 seconds |
| Started | Aug 12 06:56:56 PM PDT 24 |
| Finished | Aug 12 06:58:15 PM PDT 24 |
| Peak memory | 573604 kb |
| Host | smart-e31ebba5-b577-4b8b-abb5-3a40c882ef97 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2547423756 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 79.xbar_smoke_large_delays.2547423756 |
| Directory | /workspace/79.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/79.xbar_smoke_slow_rsp.3823446140 |
| Short name | T2145 |
| Test name | |
| Test status | |
| Simulation time | 4835812521 ps |
| CPU time | 75 seconds |
| Started | Aug 12 06:56:53 PM PDT 24 |
| Finished | Aug 12 06:58:08 PM PDT 24 |
| Peak memory | 574352 kb |
| Host | smart-bb311fc4-6e83-44c8-843b-6ec56ea7994f |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3823446140 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 79.xbar_smoke_slow_rsp.3823446140 |
| Directory | /workspace/79.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/79.xbar_smoke_zero_delays.3731358099 |
| Short name | T2448 |
| Test name | |
| Test status | |
| Simulation time | 45176232 ps |
| CPU time | 6.04 seconds |
| Started | Aug 12 06:56:53 PM PDT 24 |
| Finished | Aug 12 06:56:59 PM PDT 24 |
| Peak memory | 573636 kb |
| Host | smart-1d641add-5ec6-43b5-a8ce-77f54123a2e3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3731358099 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 79.xbar_smoke_zero_delay s.3731358099 |
| Directory | /workspace/79.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/79.xbar_stress_all.493477711 |
| Short name | T474 |
| Test name | |
| Test status | |
| Simulation time | 8742490381 ps |
| CPU time | 346.54 seconds |
| Started | Aug 12 06:57:02 PM PDT 24 |
| Finished | Aug 12 07:02:49 PM PDT 24 |
| Peak memory | 576560 kb |
| Host | smart-244a2290-ae8f-449f-b1a1-5e21b369414a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=493477711 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 79.xbar_stress_all.493477711 |
| Directory | /workspace/79.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/79.xbar_stress_all_with_error.2525638339 |
| Short name | T2329 |
| Test name | |
| Test status | |
| Simulation time | 17715449828 ps |
| CPU time | 665.35 seconds |
| Started | Aug 12 06:57:02 PM PDT 24 |
| Finished | Aug 12 07:08:07 PM PDT 24 |
| Peak memory | 575732 kb |
| Host | smart-358ab352-5b60-400e-b331-1a2cda28def3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2525638339 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 79.xbar_stress_all_with_error.2525638339 |
| Directory | /workspace/79.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/79.xbar_stress_all_with_rand_reset.1282222195 |
| Short name | T687 |
| Test name | |
| Test status | |
| Simulation time | 204411823 ps |
| CPU time | 93.76 seconds |
| Started | Aug 12 06:57:03 PM PDT 24 |
| Finished | Aug 12 06:58:36 PM PDT 24 |
| Peak memory | 576504 kb |
| Host | smart-2df4e722-1885-44e3-8b77-5c8e35baf8b8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1282222195 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 79.xbar_stress_all _with_rand_reset.1282222195 |
| Directory | /workspace/79.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/79.xbar_stress_all_with_reset_error.1068071512 |
| Short name | T2204 |
| Test name | |
| Test status | |
| Simulation time | 99083209 ps |
| CPU time | 25.44 seconds |
| Started | Aug 12 06:57:00 PM PDT 24 |
| Finished | Aug 12 06:57:25 PM PDT 24 |
| Peak memory | 575728 kb |
| Host | smart-88fda8f4-0402-48b6-8f52-e970467c706b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1068071512 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 79.xbar_stress_al l_with_reset_error.1068071512 |
| Directory | /workspace/79.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/79.xbar_unmapped_addr.3680548194 |
| Short name | T1673 |
| Test name | |
| Test status | |
| Simulation time | 290825218 ps |
| CPU time | 13.93 seconds |
| Started | Aug 12 06:57:05 PM PDT 24 |
| Finished | Aug 12 06:57:19 PM PDT 24 |
| Peak memory | 575652 kb |
| Host | smart-2809f766-0c11-4366-9480-f38ad78a18a0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3680548194 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 79.xbar_unmapped_addr.3680548194 |
| Directory | /workspace/79.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/8.chip_csr_mem_rw_with_rand_reset.3033060397 |
| Short name | T2355 |
| Test name | |
| Test status | |
| Simulation time | 6427285571 ps |
| CPU time | 426.33 seconds |
| Started | Aug 12 06:47:32 PM PDT 24 |
| Finished | Aug 12 06:54:39 PM PDT 24 |
| Peak memory | 640292 kb |
| Host | smart-ab2196f1-55ee-4793-af5a-5138e2388b23 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3033060397 -assert nopostproc + UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top .vdb -cm_log /dev/null -cm_name 8.chip_csr_mem_rw_with_rand_reset.3033060397 |
| Directory | /workspace/8.chip_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/8.chip_csr_rw.3899681743 |
| Short name | T545 |
| Test name | |
| Test status | |
| Simulation time | 3939817325 ps |
| CPU time | 253.07 seconds |
| Started | Aug 12 06:47:31 PM PDT 24 |
| Finished | Aug 12 06:51:44 PM PDT 24 |
| Peak memory | 596800 kb |
| Host | smart-59fa936d-f7ae-4532-b01e-f11bb53c4c86 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3899681743 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.chip_csr_rw.3899681743 |
| Directory | /workspace/8.chip_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/8.chip_same_csr_outstanding.918835445 |
| Short name | T2336 |
| Test name | |
| Test status | |
| Simulation time | 32082657275 ps |
| CPU time | 4168.1 seconds |
| Started | Aug 12 06:47:44 PM PDT 24 |
| Finished | Aug 12 07:57:12 PM PDT 24 |
| Peak memory | 593048 kb |
| Host | smart-18771c97-c9cb-44bf-94c0-c38b1051dacc |
| User | root |
| Command | /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +run_same_csr_outstanding +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=918835445 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c m_log /dev/null -cm_name 8.chip_same_csr_outstanding.918835445 |
| Directory | /workspace/8.chip_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/8.chip_tl_errors.1504499892 |
| Short name | T600 |
| Test name | |
| Test status | |
| Simulation time | 3700259700 ps |
| CPU time | 215.92 seconds |
| Started | Aug 12 06:47:40 PM PDT 24 |
| Finished | Aug 12 06:51:16 PM PDT 24 |
| Peak memory | 603344 kb |
| Host | smart-88a3ad5a-31c6-44b9-bd56-6862446fc4ef |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1504499892 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.chip_tl_errors.1504499892 |
| Directory | /workspace/8.chip_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/8.xbar_access_same_device.3996245222 |
| Short name | T1843 |
| Test name | |
| Test status | |
| Simulation time | 3195557603 ps |
| CPU time | 132.28 seconds |
| Started | Aug 12 06:47:32 PM PDT 24 |
| Finished | Aug 12 06:49:45 PM PDT 24 |
| Peak memory | 575812 kb |
| Host | smart-429a60a2-ef6a-413f-8f3a-3bf60e16999a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3996245222 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.xbar_access_same_device. 3996245222 |
| Directory | /workspace/8.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/8.xbar_access_same_device_slow_rsp.1183075202 |
| Short name | T2365 |
| Test name | |
| Test status | |
| Simulation time | 121993963629 ps |
| CPU time | 2160.61 seconds |
| Started | Aug 12 06:47:33 PM PDT 24 |
| Finished | Aug 12 07:23:34 PM PDT 24 |
| Peak memory | 575896 kb |
| Host | smart-e617d7ed-7e6d-4d79-b655-b1f3d35a6610 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1183075202 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.xbar_access_same_d evice_slow_rsp.1183075202 |
| Directory | /workspace/8.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/8.xbar_error_and_unmapped_addr.190531951 |
| Short name | T2649 |
| Test name | |
| Test status | |
| Simulation time | 290967646 ps |
| CPU time | 12.05 seconds |
| Started | Aug 12 06:47:35 PM PDT 24 |
| Finished | Aug 12 06:47:47 PM PDT 24 |
| Peak memory | 575780 kb |
| Host | smart-66d0fb33-8aea-44d6-8df3-f3db265217cb |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=190531951 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.xbar_error_and_unmapped_addr. 190531951 |
| Directory | /workspace/8.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/8.xbar_error_random.1504669119 |
| Short name | T2736 |
| Test name | |
| Test status | |
| Simulation time | 71229674 ps |
| CPU time | 7.56 seconds |
| Started | Aug 12 06:47:47 PM PDT 24 |
| Finished | Aug 12 06:47:55 PM PDT 24 |
| Peak memory | 575504 kb |
| Host | smart-189056f5-6cc6-4e5a-b061-3e70bcdbb7cc |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1504669119 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.xbar_error_random.1504669119 |
| Directory | /workspace/8.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/8.xbar_random.3453276571 |
| Short name | T2776 |
| Test name | |
| Test status | |
| Simulation time | 229361668 ps |
| CPU time | 12.15 seconds |
| Started | Aug 12 06:47:35 PM PDT 24 |
| Finished | Aug 12 06:47:48 PM PDT 24 |
| Peak memory | 575720 kb |
| Host | smart-0969d1be-d8c9-4077-bd13-6045bee8c993 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3453276571 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.xbar_random.3453276571 |
| Directory | /workspace/8.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/8.xbar_random_large_delays.3317123297 |
| Short name | T2868 |
| Test name | |
| Test status | |
| Simulation time | 6109830478 ps |
| CPU time | 66.56 seconds |
| Started | Aug 12 06:47:34 PM PDT 24 |
| Finished | Aug 12 06:48:40 PM PDT 24 |
| Peak memory | 573664 kb |
| Host | smart-ebdf62da-64a2-4503-9c5a-9b43b7fc79d6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3317123297 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.xbar_random_large_delays.3317123297 |
| Directory | /workspace/8.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/8.xbar_random_slow_rsp.3060639575 |
| Short name | T2198 |
| Test name | |
| Test status | |
| Simulation time | 69828812251 ps |
| CPU time | 1066.65 seconds |
| Started | Aug 12 06:47:39 PM PDT 24 |
| Finished | Aug 12 07:05:27 PM PDT 24 |
| Peak memory | 575812 kb |
| Host | smart-3facb17e-d232-4f7f-838b-f261ee9f9645 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3060639575 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.xbar_random_slow_rsp.3060639575 |
| Directory | /workspace/8.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/8.xbar_random_zero_delays.3222204572 |
| Short name | T2881 |
| Test name | |
| Test status | |
| Simulation time | 600408231 ps |
| CPU time | 42.39 seconds |
| Started | Aug 12 06:47:49 PM PDT 24 |
| Finished | Aug 12 06:48:31 PM PDT 24 |
| Peak memory | 575704 kb |
| Host | smart-1029276b-d714-49ab-8287-b1e69d9c02f6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3222204572 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.xbar_random_zero_dela ys.3222204572 |
| Directory | /workspace/8.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/8.xbar_same_source.949265784 |
| Short name | T1744 |
| Test name | |
| Test status | |
| Simulation time | 328451513 ps |
| CPU time | 24.75 seconds |
| Started | Aug 12 06:47:34 PM PDT 24 |
| Finished | Aug 12 06:47:58 PM PDT 24 |
| Peak memory | 575656 kb |
| Host | smart-77811349-952a-4922-82e4-3b2d1f73ef4c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=949265784 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.xbar_same_source.949265784 |
| Directory | /workspace/8.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/8.xbar_smoke.3626860440 |
| Short name | T2068 |
| Test name | |
| Test status | |
| Simulation time | 178644001 ps |
| CPU time | 8.03 seconds |
| Started | Aug 12 06:47:39 PM PDT 24 |
| Finished | Aug 12 06:47:47 PM PDT 24 |
| Peak memory | 574276 kb |
| Host | smart-1b45df39-9f08-4244-9671-4957fdad7e1a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3626860440 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.xbar_smoke.3626860440 |
| Directory | /workspace/8.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/8.xbar_smoke_large_delays.3942954543 |
| Short name | T1862 |
| Test name | |
| Test status | |
| Simulation time | 9852134453 ps |
| CPU time | 95.62 seconds |
| Started | Aug 12 06:47:55 PM PDT 24 |
| Finished | Aug 12 06:49:31 PM PDT 24 |
| Peak memory | 573648 kb |
| Host | smart-d63811b9-f155-482b-9182-8a586416692b |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3942954543 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.xbar_smoke_large_delays.3942954543 |
| Directory | /workspace/8.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/8.xbar_smoke_slow_rsp.1689030274 |
| Short name | T2081 |
| Test name | |
| Test status | |
| Simulation time | 4069780396 ps |
| CPU time | 66.38 seconds |
| Started | Aug 12 06:47:36 PM PDT 24 |
| Finished | Aug 12 06:48:43 PM PDT 24 |
| Peak memory | 573676 kb |
| Host | smart-bbf340d9-47c5-4321-9b00-e01f403f09f0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1689030274 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.xbar_smoke_slow_rsp.1689030274 |
| Directory | /workspace/8.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/8.xbar_smoke_zero_delays.1336108205 |
| Short name | T1443 |
| Test name | |
| Test status | |
| Simulation time | 44947485 ps |
| CPU time | 6.52 seconds |
| Started | Aug 12 06:47:35 PM PDT 24 |
| Finished | Aug 12 06:47:42 PM PDT 24 |
| Peak memory | 573604 kb |
| Host | smart-aed388a5-240b-4cab-b0ec-0f2095e48d6c |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1336108205 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.xbar_smoke_zero_delays .1336108205 |
| Directory | /workspace/8.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/8.xbar_stress_all.1332939565 |
| Short name | T2760 |
| Test name | |
| Test status | |
| Simulation time | 15099805796 ps |
| CPU time | 586.36 seconds |
| Started | Aug 12 06:47:37 PM PDT 24 |
| Finished | Aug 12 06:57:23 PM PDT 24 |
| Peak memory | 575764 kb |
| Host | smart-7feae2d9-f1e8-4d24-a2e9-35a51a6bfd98 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1332939565 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.xbar_stress_all.1332939565 |
| Directory | /workspace/8.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/8.xbar_stress_all_with_error.3588037418 |
| Short name | T1610 |
| Test name | |
| Test status | |
| Simulation time | 19153965446 ps |
| CPU time | 686.92 seconds |
| Started | Aug 12 06:47:37 PM PDT 24 |
| Finished | Aug 12 06:59:04 PM PDT 24 |
| Peak memory | 575900 kb |
| Host | smart-5c1ba1f1-3494-4ed1-84ed-7af062e5bd2f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3588037418 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.xbar_stress_all_with_error.3588037418 |
| Directory | /workspace/8.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/8.xbar_stress_all_with_rand_reset.2273795366 |
| Short name | T1908 |
| Test name | |
| Test status | |
| Simulation time | 64911274 ps |
| CPU time | 15.89 seconds |
| Started | Aug 12 06:47:42 PM PDT 24 |
| Finished | Aug 12 06:47:57 PM PDT 24 |
| Peak memory | 574436 kb |
| Host | smart-b56a9e49-e3c5-4380-ac81-7f1582ad8559 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2273795366 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.xbar_stress_all_ with_rand_reset.2273795366 |
| Directory | /workspace/8.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/8.xbar_stress_all_with_reset_error.3596873915 |
| Short name | T906 |
| Test name | |
| Test status | |
| Simulation time | 12069546769 ps |
| CPU time | 610 seconds |
| Started | Aug 12 06:47:46 PM PDT 24 |
| Finished | Aug 12 06:57:56 PM PDT 24 |
| Peak memory | 576628 kb |
| Host | smart-0cbeca8c-6788-4858-9678-ea969dd5b4d1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3596873915 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.xbar_stress_all _with_reset_error.3596873915 |
| Directory | /workspace/8.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/8.xbar_unmapped_addr.3235111597 |
| Short name | T2460 |
| Test name | |
| Test status | |
| Simulation time | 1384082479 ps |
| CPU time | 53.01 seconds |
| Started | Aug 12 06:47:55 PM PDT 24 |
| Finished | Aug 12 06:48:48 PM PDT 24 |
| Peak memory | 575564 kb |
| Host | smart-93e5400a-fc5d-4349-a9b0-597e585e93ed |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3235111597 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.xbar_unmapped_addr.3235111597 |
| Directory | /workspace/8.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/80.xbar_access_same_device.3409122948 |
| Short name | T1543 |
| Test name | |
| Test status | |
| Simulation time | 36786108 ps |
| CPU time | 6.18 seconds |
| Started | Aug 12 06:57:02 PM PDT 24 |
| Finished | Aug 12 06:57:08 PM PDT 24 |
| Peak memory | 574280 kb |
| Host | smart-64978eaa-f9a2-4ac3-8b32-94ac04f3fdcc |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3409122948 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 80.xbar_access_same_device .3409122948 |
| Directory | /workspace/80.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/80.xbar_access_same_device_slow_rsp.3277394667 |
| Short name | T2855 |
| Test name | |
| Test status | |
| Simulation time | 67719441751 ps |
| CPU time | 1267.67 seconds |
| Started | Aug 12 06:56:59 PM PDT 24 |
| Finished | Aug 12 07:18:07 PM PDT 24 |
| Peak memory | 575800 kb |
| Host | smart-40cefe8e-8615-4e7c-b653-7f04eca152f5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3277394667 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 80.xbar_access_same_ device_slow_rsp.3277394667 |
| Directory | /workspace/80.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/80.xbar_error_and_unmapped_addr.200299270 |
| Short name | T1531 |
| Test name | |
| Test status | |
| Simulation time | 204961997 ps |
| CPU time | 21.63 seconds |
| Started | Aug 12 06:57:11 PM PDT 24 |
| Finished | Aug 12 06:57:33 PM PDT 24 |
| Peak memory | 575668 kb |
| Host | smart-92e34972-6b1e-461b-915b-fc446e68a7c4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=200299270 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 80.xbar_error_and_unmapped_addr .200299270 |
| Directory | /workspace/80.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/80.xbar_error_random.3002700350 |
| Short name | T2573 |
| Test name | |
| Test status | |
| Simulation time | 113650257 ps |
| CPU time | 10.57 seconds |
| Started | Aug 12 06:57:14 PM PDT 24 |
| Finished | Aug 12 06:57:24 PM PDT 24 |
| Peak memory | 575692 kb |
| Host | smart-12506292-82bb-4793-ad58-1e38c8719a96 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3002700350 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 80.xbar_error_random.3002700350 |
| Directory | /workspace/80.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/80.xbar_random.4152203519 |
| Short name | T604 |
| Test name | |
| Test status | |
| Simulation time | 1963800977 ps |
| CPU time | 68.46 seconds |
| Started | Aug 12 06:57:02 PM PDT 24 |
| Finished | Aug 12 06:58:10 PM PDT 24 |
| Peak memory | 575632 kb |
| Host | smart-704ed2a1-982b-41e2-a67d-c17345740425 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4152203519 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 80.xbar_random.4152203519 |
| Directory | /workspace/80.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/80.xbar_random_large_delays.2294248809 |
| Short name | T2383 |
| Test name | |
| Test status | |
| Simulation time | 66274581688 ps |
| CPU time | 748.47 seconds |
| Started | Aug 12 06:57:00 PM PDT 24 |
| Finished | Aug 12 07:09:29 PM PDT 24 |
| Peak memory | 575804 kb |
| Host | smart-b60f3065-4939-4344-a71f-d3edc305a925 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2294248809 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 80.xbar_random_large_delays.2294248809 |
| Directory | /workspace/80.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/80.xbar_random_slow_rsp.3974396566 |
| Short name | T2252 |
| Test name | |
| Test status | |
| Simulation time | 61735126644 ps |
| CPU time | 1049.11 seconds |
| Started | Aug 12 06:56:59 PM PDT 24 |
| Finished | Aug 12 07:14:29 PM PDT 24 |
| Peak memory | 575628 kb |
| Host | smart-1c30ac34-dc7a-4ed8-98c8-8dfa49ce86cf |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3974396566 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 80.xbar_random_slow_rsp.3974396566 |
| Directory | /workspace/80.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/80.xbar_random_zero_delays.726441326 |
| Short name | T541 |
| Test name | |
| Test status | |
| Simulation time | 622278476 ps |
| CPU time | 51.57 seconds |
| Started | Aug 12 06:57:02 PM PDT 24 |
| Finished | Aug 12 06:57:54 PM PDT 24 |
| Peak memory | 575652 kb |
| Host | smart-fee3b424-ba5a-4981-a0f3-28bd546d8137 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=726441326 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 80.xbar_random_zero_dela ys.726441326 |
| Directory | /workspace/80.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/80.xbar_same_source.2868634629 |
| Short name | T2727 |
| Test name | |
| Test status | |
| Simulation time | 403794281 ps |
| CPU time | 31.2 seconds |
| Started | Aug 12 06:57:11 PM PDT 24 |
| Finished | Aug 12 06:57:42 PM PDT 24 |
| Peak memory | 575620 kb |
| Host | smart-df5f259a-21ff-4652-9deb-89ba9a0e736d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2868634629 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 80.xbar_same_source.2868634629 |
| Directory | /workspace/80.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/80.xbar_smoke.3056840312 |
| Short name | T2325 |
| Test name | |
| Test status | |
| Simulation time | 51145549 ps |
| CPU time | 6.43 seconds |
| Started | Aug 12 06:57:04 PM PDT 24 |
| Finished | Aug 12 06:57:10 PM PDT 24 |
| Peak memory | 574280 kb |
| Host | smart-8c2e9f57-84cf-4bcf-b887-4543c9cf8390 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3056840312 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 80.xbar_smoke.3056840312 |
| Directory | /workspace/80.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/80.xbar_smoke_large_delays.1095388215 |
| Short name | T2831 |
| Test name | |
| Test status | |
| Simulation time | 8727953490 ps |
| CPU time | 83.39 seconds |
| Started | Aug 12 06:57:00 PM PDT 24 |
| Finished | Aug 12 06:58:23 PM PDT 24 |
| Peak memory | 573632 kb |
| Host | smart-afa56fec-08d8-4e15-bfb8-b534fe0d3743 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1095388215 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 80.xbar_smoke_large_delays.1095388215 |
| Directory | /workspace/80.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/80.xbar_smoke_slow_rsp.463693444 |
| Short name | T2260 |
| Test name | |
| Test status | |
| Simulation time | 5973006445 ps |
| CPU time | 100.65 seconds |
| Started | Aug 12 06:57:01 PM PDT 24 |
| Finished | Aug 12 06:58:42 PM PDT 24 |
| Peak memory | 573680 kb |
| Host | smart-aa2580ac-bd15-46ae-9a5e-1583a9661d59 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=463693444 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 80.xbar_smoke_slow_rsp.463693444 |
| Directory | /workspace/80.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/80.xbar_smoke_zero_delays.567550083 |
| Short name | T2392 |
| Test name | |
| Test status | |
| Simulation time | 48861639 ps |
| CPU time | 6.57 seconds |
| Started | Aug 12 06:57:02 PM PDT 24 |
| Finished | Aug 12 06:57:09 PM PDT 24 |
| Peak memory | 574320 kb |
| Host | smart-4ee72ce5-f8c2-4d9a-ba83-29014b88a443 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=567550083 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 80.xbar_smoke_zero_delays .567550083 |
| Directory | /workspace/80.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/80.xbar_stress_all.1525329031 |
| Short name | T2929 |
| Test name | |
| Test status | |
| Simulation time | 844083704 ps |
| CPU time | 30.31 seconds |
| Started | Aug 12 06:57:16 PM PDT 24 |
| Finished | Aug 12 06:57:46 PM PDT 24 |
| Peak memory | 575724 kb |
| Host | smart-02c61e03-9997-49c0-8585-8157788d270c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1525329031 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 80.xbar_stress_all.1525329031 |
| Directory | /workspace/80.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/80.xbar_stress_all_with_rand_reset.154574512 |
| Short name | T473 |
| Test name | |
| Test status | |
| Simulation time | 781743546 ps |
| CPU time | 282.84 seconds |
| Started | Aug 12 06:57:12 PM PDT 24 |
| Finished | Aug 12 07:01:55 PM PDT 24 |
| Peak memory | 575676 kb |
| Host | smart-bdfd9a5a-5955-4bdc-9341-885aef64bcfb |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=154574512 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_res et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 80.xbar_stress_all_ with_rand_reset.154574512 |
| Directory | /workspace/80.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/80.xbar_stress_all_with_reset_error.2129700756 |
| Short name | T1823 |
| Test name | |
| Test status | |
| Simulation time | 4139963069 ps |
| CPU time | 273.09 seconds |
| Started | Aug 12 06:57:16 PM PDT 24 |
| Finished | Aug 12 07:01:49 PM PDT 24 |
| Peak memory | 576628 kb |
| Host | smart-4286d237-0583-4f9e-8692-2f0bd57e33df |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2129700756 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 80.xbar_stress_al l_with_reset_error.2129700756 |
| Directory | /workspace/80.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/80.xbar_unmapped_addr.901954705 |
| Short name | T2653 |
| Test name | |
| Test status | |
| Simulation time | 993041150 ps |
| CPU time | 40.32 seconds |
| Started | Aug 12 06:57:11 PM PDT 24 |
| Finished | Aug 12 06:57:52 PM PDT 24 |
| Peak memory | 575820 kb |
| Host | smart-942cb37f-aa9d-4851-ab5e-70afb0f967cd |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=901954705 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 80.xbar_unmapped_addr.901954705 |
| Directory | /workspace/80.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/81.xbar_access_same_device.246162223 |
| Short name | T1635 |
| Test name | |
| Test status | |
| Simulation time | 1835899533 ps |
| CPU time | 73.39 seconds |
| Started | Aug 12 06:57:11 PM PDT 24 |
| Finished | Aug 12 06:58:25 PM PDT 24 |
| Peak memory | 575672 kb |
| Host | smart-1d6a9d87-ad58-4fc7-b165-c08ae0acb82b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=246162223 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 81.xbar_access_same_device. 246162223 |
| Directory | /workspace/81.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/81.xbar_access_same_device_slow_rsp.3925706467 |
| Short name | T2027 |
| Test name | |
| Test status | |
| Simulation time | 79752066873 ps |
| CPU time | 1496.58 seconds |
| Started | Aug 12 06:57:11 PM PDT 24 |
| Finished | Aug 12 07:22:08 PM PDT 24 |
| Peak memory | 575828 kb |
| Host | smart-bb6a583d-2bf9-40bc-8ed5-854d14281690 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3925706467 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 81.xbar_access_same_ device_slow_rsp.3925706467 |
| Directory | /workspace/81.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/81.xbar_error_and_unmapped_addr.1778059082 |
| Short name | T2499 |
| Test name | |
| Test status | |
| Simulation time | 584742536 ps |
| CPU time | 25 seconds |
| Started | Aug 12 06:57:11 PM PDT 24 |
| Finished | Aug 12 06:57:36 PM PDT 24 |
| Peak memory | 575672 kb |
| Host | smart-fb9aec22-c3dd-4343-9ad6-10ca2811ff91 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1778059082 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 81.xbar_error_and_unmapped_add r.1778059082 |
| Directory | /workspace/81.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/81.xbar_error_random.516065951 |
| Short name | T2533 |
| Test name | |
| Test status | |
| Simulation time | 1207571202 ps |
| CPU time | 38.55 seconds |
| Started | Aug 12 06:57:14 PM PDT 24 |
| Finished | Aug 12 06:57:53 PM PDT 24 |
| Peak memory | 575656 kb |
| Host | smart-96647fc0-1ed4-44a4-a059-36ba35e14b9a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=516065951 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 81.xbar_error_random.516065951 |
| Directory | /workspace/81.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/81.xbar_random.2958823604 |
| Short name | T462 |
| Test name | |
| Test status | |
| Simulation time | 423967518 ps |
| CPU time | 20.21 seconds |
| Started | Aug 12 06:57:12 PM PDT 24 |
| Finished | Aug 12 06:57:32 PM PDT 24 |
| Peak memory | 575636 kb |
| Host | smart-00cff4e7-340f-45e0-82c0-4d86c0145e05 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2958823604 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 81.xbar_random.2958823604 |
| Directory | /workspace/81.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/81.xbar_random_large_delays.2112814577 |
| Short name | T1742 |
| Test name | |
| Test status | |
| Simulation time | 42380709754 ps |
| CPU time | 424.6 seconds |
| Started | Aug 12 06:57:11 PM PDT 24 |
| Finished | Aug 12 07:04:15 PM PDT 24 |
| Peak memory | 575844 kb |
| Host | smart-40329130-45ba-48e3-b1bf-624ce15b8125 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2112814577 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 81.xbar_random_large_delays.2112814577 |
| Directory | /workspace/81.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/81.xbar_random_slow_rsp.3335600557 |
| Short name | T634 |
| Test name | |
| Test status | |
| Simulation time | 29102669225 ps |
| CPU time | 474.04 seconds |
| Started | Aug 12 06:57:15 PM PDT 24 |
| Finished | Aug 12 07:05:09 PM PDT 24 |
| Peak memory | 575804 kb |
| Host | smart-bf7bd237-8996-4750-b757-dd80342b696e |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3335600557 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 81.xbar_random_slow_rsp.3335600557 |
| Directory | /workspace/81.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/81.xbar_random_zero_delays.3987487810 |
| Short name | T2131 |
| Test name | |
| Test status | |
| Simulation time | 570137647 ps |
| CPU time | 47.97 seconds |
| Started | Aug 12 06:57:13 PM PDT 24 |
| Finished | Aug 12 06:58:01 PM PDT 24 |
| Peak memory | 575740 kb |
| Host | smart-32bc6220-9865-4401-9e92-a40d629f4efb |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3987487810 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 81.xbar_random_zero_del ays.3987487810 |
| Directory | /workspace/81.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/81.xbar_same_source.2551839860 |
| Short name | T1594 |
| Test name | |
| Test status | |
| Simulation time | 1114901568 ps |
| CPU time | 35.11 seconds |
| Started | Aug 12 06:57:11 PM PDT 24 |
| Finished | Aug 12 06:57:46 PM PDT 24 |
| Peak memory | 575616 kb |
| Host | smart-2a2ab36f-92c5-4573-8a03-60d108a66bbe |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2551839860 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 81.xbar_same_source.2551839860 |
| Directory | /workspace/81.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/81.xbar_smoke.3795890301 |
| Short name | T1447 |
| Test name | |
| Test status | |
| Simulation time | 259929428 ps |
| CPU time | 10.26 seconds |
| Started | Aug 12 06:57:10 PM PDT 24 |
| Finished | Aug 12 06:57:21 PM PDT 24 |
| Peak memory | 574264 kb |
| Host | smart-72fcfe55-272c-4c89-abdd-9a1bad99e835 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3795890301 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 81.xbar_smoke.3795890301 |
| Directory | /workspace/81.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/81.xbar_smoke_large_delays.2650345841 |
| Short name | T2032 |
| Test name | |
| Test status | |
| Simulation time | 7738224348 ps |
| CPU time | 71.63 seconds |
| Started | Aug 12 06:57:14 PM PDT 24 |
| Finished | Aug 12 06:58:26 PM PDT 24 |
| Peak memory | 573716 kb |
| Host | smart-ace8d322-50bc-4ff1-a792-ec86d0436445 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2650345841 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 81.xbar_smoke_large_delays.2650345841 |
| Directory | /workspace/81.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/81.xbar_smoke_slow_rsp.3071076309 |
| Short name | T2606 |
| Test name | |
| Test status | |
| Simulation time | 6033687088 ps |
| CPU time | 107.1 seconds |
| Started | Aug 12 06:57:17 PM PDT 24 |
| Finished | Aug 12 06:59:04 PM PDT 24 |
| Peak memory | 573688 kb |
| Host | smart-d2316489-7b3a-42e0-99fd-7c2eb0c82a22 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3071076309 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 81.xbar_smoke_slow_rsp.3071076309 |
| Directory | /workspace/81.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/81.xbar_smoke_zero_delays.3835000464 |
| Short name | T1491 |
| Test name | |
| Test status | |
| Simulation time | 52377115 ps |
| CPU time | 6.49 seconds |
| Started | Aug 12 06:57:13 PM PDT 24 |
| Finished | Aug 12 06:57:19 PM PDT 24 |
| Peak memory | 573636 kb |
| Host | smart-e63f37fc-a1a4-4879-996d-5770158bc274 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3835000464 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 81.xbar_smoke_zero_delay s.3835000464 |
| Directory | /workspace/81.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/81.xbar_stress_all.3268576564 |
| Short name | T2866 |
| Test name | |
| Test status | |
| Simulation time | 10441358440 ps |
| CPU time | 369.07 seconds |
| Started | Aug 12 06:57:13 PM PDT 24 |
| Finished | Aug 12 07:03:23 PM PDT 24 |
| Peak memory | 575700 kb |
| Host | smart-a6a6c108-35a3-4f0f-be57-7126af3b18f4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3268576564 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 81.xbar_stress_all.3268576564 |
| Directory | /workspace/81.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/81.xbar_stress_all_with_error.700159887 |
| Short name | T2298 |
| Test name | |
| Test status | |
| Simulation time | 10084280923 ps |
| CPU time | 410.83 seconds |
| Started | Aug 12 06:57:12 PM PDT 24 |
| Finished | Aug 12 07:04:03 PM PDT 24 |
| Peak memory | 575760 kb |
| Host | smart-dbbfddbb-9fa3-4b93-854f-68f9993c49cb |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=700159887 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 81.xbar_stress_all_with_error.700159887 |
| Directory | /workspace/81.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/81.xbar_stress_all_with_rand_reset.3973314936 |
| Short name | T2826 |
| Test name | |
| Test status | |
| Simulation time | 6041265958 ps |
| CPU time | 760.29 seconds |
| Started | Aug 12 06:57:12 PM PDT 24 |
| Finished | Aug 12 07:09:52 PM PDT 24 |
| Peak memory | 575840 kb |
| Host | smart-f30fdbeb-0176-4411-b5df-89901e5104cc |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3973314936 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 81.xbar_stress_all _with_rand_reset.3973314936 |
| Directory | /workspace/81.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/81.xbar_stress_all_with_reset_error.83427831 |
| Short name | T2761 |
| Test name | |
| Test status | |
| Simulation time | 207856444 ps |
| CPU time | 63.25 seconds |
| Started | Aug 12 06:57:10 PM PDT 24 |
| Finished | Aug 12 06:58:13 PM PDT 24 |
| Peak memory | 575704 kb |
| Host | smart-5adb6d10-027f-4886-a553-e341ebad5710 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=83427831 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_res et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 81.xbar_stress_all_ with_reset_error.83427831 |
| Directory | /workspace/81.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/81.xbar_unmapped_addr.3241897174 |
| Short name | T741 |
| Test name | |
| Test status | |
| Simulation time | 21441587 ps |
| CPU time | 5.43 seconds |
| Started | Aug 12 06:57:12 PM PDT 24 |
| Finished | Aug 12 06:57:17 PM PDT 24 |
| Peak memory | 573676 kb |
| Host | smart-515dfdd0-48ae-4ea5-9292-f256b8980bc7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3241897174 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 81.xbar_unmapped_addr.3241897174 |
| Directory | /workspace/81.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/82.xbar_access_same_device.2305070968 |
| Short name | T1642 |
| Test name | |
| Test status | |
| Simulation time | 1601979360 ps |
| CPU time | 73.24 seconds |
| Started | Aug 12 06:57:31 PM PDT 24 |
| Finished | Aug 12 06:58:44 PM PDT 24 |
| Peak memory | 575644 kb |
| Host | smart-83243f2f-416e-45fd-9901-48acaf33c1c1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2305070968 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 82.xbar_access_same_device .2305070968 |
| Directory | /workspace/82.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/82.xbar_access_same_device_slow_rsp.1376517821 |
| Short name | T2782 |
| Test name | |
| Test status | |
| Simulation time | 128348443759 ps |
| CPU time | 2407.9 seconds |
| Started | Aug 12 06:57:22 PM PDT 24 |
| Finished | Aug 12 07:37:31 PM PDT 24 |
| Peak memory | 575800 kb |
| Host | smart-70884c04-e458-4f71-85b9-a8f5a6bf2128 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1376517821 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 82.xbar_access_same_ device_slow_rsp.1376517821 |
| Directory | /workspace/82.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/82.xbar_error_and_unmapped_addr.3336200908 |
| Short name | T2614 |
| Test name | |
| Test status | |
| Simulation time | 688641319 ps |
| CPU time | 28.84 seconds |
| Started | Aug 12 06:57:26 PM PDT 24 |
| Finished | Aug 12 06:57:55 PM PDT 24 |
| Peak memory | 575752 kb |
| Host | smart-a6c1a7fd-3208-4500-8416-ecbb9ba14eab |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3336200908 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 82.xbar_error_and_unmapped_add r.3336200908 |
| Directory | /workspace/82.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/82.xbar_error_random.1467533799 |
| Short name | T1890 |
| Test name | |
| Test status | |
| Simulation time | 704936366 ps |
| CPU time | 26.03 seconds |
| Started | Aug 12 06:57:31 PM PDT 24 |
| Finished | Aug 12 06:57:57 PM PDT 24 |
| Peak memory | 575456 kb |
| Host | smart-55a15049-076a-4110-91d0-82abef2c6971 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1467533799 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 82.xbar_error_random.1467533799 |
| Directory | /workspace/82.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/82.xbar_random.2714674938 |
| Short name | T2063 |
| Test name | |
| Test status | |
| Simulation time | 2377922518 ps |
| CPU time | 84.26 seconds |
| Started | Aug 12 06:57:22 PM PDT 24 |
| Finished | Aug 12 06:58:46 PM PDT 24 |
| Peak memory | 575772 kb |
| Host | smart-bb0a13cf-7080-441e-9f87-4d7944a24080 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2714674938 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 82.xbar_random.2714674938 |
| Directory | /workspace/82.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/82.xbar_random_large_delays.3923588819 |
| Short name | T656 |
| Test name | |
| Test status | |
| Simulation time | 92671165860 ps |
| CPU time | 1020.57 seconds |
| Started | Aug 12 06:57:22 PM PDT 24 |
| Finished | Aug 12 07:14:23 PM PDT 24 |
| Peak memory | 575640 kb |
| Host | smart-b1ad7866-2ba3-4aa4-b9da-5e929ea41dd3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3923588819 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 82.xbar_random_large_delays.3923588819 |
| Directory | /workspace/82.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/82.xbar_random_slow_rsp.2500116330 |
| Short name | T1848 |
| Test name | |
| Test status | |
| Simulation time | 54455611655 ps |
| CPU time | 1046.16 seconds |
| Started | Aug 12 06:57:22 PM PDT 24 |
| Finished | Aug 12 07:14:48 PM PDT 24 |
| Peak memory | 575760 kb |
| Host | smart-4345bc45-1556-4bb9-9482-be5d6aee9065 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2500116330 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 82.xbar_random_slow_rsp.2500116330 |
| Directory | /workspace/82.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/82.xbar_random_zero_delays.260529 |
| Short name | T494 |
| Test name | |
| Test status | |
| Simulation time | 523584843 ps |
| CPU time | 39.96 seconds |
| Started | Aug 12 06:57:22 PM PDT 24 |
| Finished | Aug 12 06:58:03 PM PDT 24 |
| Peak memory | 575704 kb |
| Host | smart-6a40935a-e31e-49b1-8ad4-18c7d3b7f31f |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=260529 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 82.xbar_random_zero_delays.260529 |
| Directory | /workspace/82.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/82.xbar_same_source.336240174 |
| Short name | T2378 |
| Test name | |
| Test status | |
| Simulation time | 238774544 ps |
| CPU time | 18.32 seconds |
| Started | Aug 12 06:57:28 PM PDT 24 |
| Finished | Aug 12 06:57:47 PM PDT 24 |
| Peak memory | 575508 kb |
| Host | smart-b9de18a7-6439-4e5d-a260-312c597a87d4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=336240174 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 82.xbar_same_source.336240174 |
| Directory | /workspace/82.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/82.xbar_smoke.81379170 |
| Short name | T2292 |
| Test name | |
| Test status | |
| Simulation time | 40573567 ps |
| CPU time | 6.07 seconds |
| Started | Aug 12 06:57:14 PM PDT 24 |
| Finished | Aug 12 06:57:20 PM PDT 24 |
| Peak memory | 574248 kb |
| Host | smart-af3f50b6-1eef-4597-af4e-2cc245c2f4d3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=81379170 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 82.xbar_smoke.81379170 |
| Directory | /workspace/82.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/82.xbar_smoke_large_delays.3872653155 |
| Short name | T1892 |
| Test name | |
| Test status | |
| Simulation time | 9266719781 ps |
| CPU time | 100.67 seconds |
| Started | Aug 12 06:57:21 PM PDT 24 |
| Finished | Aug 12 06:59:02 PM PDT 24 |
| Peak memory | 573612 kb |
| Host | smart-c9542425-8ea7-4985-872c-bcacaea5840d |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3872653155 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 82.xbar_smoke_large_delays.3872653155 |
| Directory | /workspace/82.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/82.xbar_smoke_slow_rsp.1765983802 |
| Short name | T1790 |
| Test name | |
| Test status | |
| Simulation time | 3551748909 ps |
| CPU time | 61.93 seconds |
| Started | Aug 12 06:57:23 PM PDT 24 |
| Finished | Aug 12 06:58:25 PM PDT 24 |
| Peak memory | 573576 kb |
| Host | smart-ea872403-4343-41c9-b94b-7aad42f15da2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1765983802 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 82.xbar_smoke_slow_rsp.1765983802 |
| Directory | /workspace/82.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/82.xbar_smoke_zero_delays.4059410262 |
| Short name | T2003 |
| Test name | |
| Test status | |
| Simulation time | 47956106 ps |
| CPU time | 6.53 seconds |
| Started | Aug 12 06:57:23 PM PDT 24 |
| Finished | Aug 12 06:57:29 PM PDT 24 |
| Peak memory | 573588 kb |
| Host | smart-207253e1-35b2-4905-9a01-44fda2363081 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4059410262 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 82.xbar_smoke_zero_delay s.4059410262 |
| Directory | /workspace/82.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/82.xbar_stress_all.453870007 |
| Short name | T513 |
| Test name | |
| Test status | |
| Simulation time | 2054440801 ps |
| CPU time | 155.94 seconds |
| Started | Aug 12 06:57:23 PM PDT 24 |
| Finished | Aug 12 06:59:59 PM PDT 24 |
| Peak memory | 575732 kb |
| Host | smart-f106530c-3aaf-4de5-a22f-f6bc7a6ec2a3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=453870007 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 82.xbar_stress_all.453870007 |
| Directory | /workspace/82.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/82.xbar_stress_all_with_rand_reset.1958460083 |
| Short name | T951 |
| Test name | |
| Test status | |
| Simulation time | 7223546090 ps |
| CPU time | 391.01 seconds |
| Started | Aug 12 06:57:25 PM PDT 24 |
| Finished | Aug 12 07:03:56 PM PDT 24 |
| Peak memory | 576576 kb |
| Host | smart-e4f5e7d7-bb84-446d-bc93-304178bb7f26 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1958460083 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 82.xbar_stress_all _with_rand_reset.1958460083 |
| Directory | /workspace/82.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/82.xbar_stress_all_with_reset_error.2186177823 |
| Short name | T960 |
| Test name | |
| Test status | |
| Simulation time | 8543582530 ps |
| CPU time | 481.67 seconds |
| Started | Aug 12 06:57:25 PM PDT 24 |
| Finished | Aug 12 07:05:27 PM PDT 24 |
| Peak memory | 575764 kb |
| Host | smart-42139f9a-25da-4885-bace-fbaaec825167 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2186177823 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 82.xbar_stress_al l_with_reset_error.2186177823 |
| Directory | /workspace/82.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/82.xbar_unmapped_addr.436283093 |
| Short name | T2248 |
| Test name | |
| Test status | |
| Simulation time | 324223438 ps |
| CPU time | 14.55 seconds |
| Started | Aug 12 06:57:30 PM PDT 24 |
| Finished | Aug 12 06:57:45 PM PDT 24 |
| Peak memory | 575544 kb |
| Host | smart-4ad9410b-124a-4099-9e86-e107fa114fb7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=436283093 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 82.xbar_unmapped_addr.436283093 |
| Directory | /workspace/82.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/83.xbar_access_same_device.648883299 |
| Short name | T1661 |
| Test name | |
| Test status | |
| Simulation time | 353929401 ps |
| CPU time | 17.81 seconds |
| Started | Aug 12 06:57:23 PM PDT 24 |
| Finished | Aug 12 06:57:41 PM PDT 24 |
| Peak memory | 575532 kb |
| Host | smart-d12784bc-ae74-495b-82ad-e669a9063266 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=648883299 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 83.xbar_access_same_device. 648883299 |
| Directory | /workspace/83.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/83.xbar_access_same_device_slow_rsp.2764048041 |
| Short name | T1679 |
| Test name | |
| Test status | |
| Simulation time | 67419535419 ps |
| CPU time | 1246.94 seconds |
| Started | Aug 12 06:57:28 PM PDT 24 |
| Finished | Aug 12 07:18:15 PM PDT 24 |
| Peak memory | 575668 kb |
| Host | smart-bc2c4f31-255d-4392-a177-d397ffbb2041 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2764048041 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 83.xbar_access_same_ device_slow_rsp.2764048041 |
| Directory | /workspace/83.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/83.xbar_error_and_unmapped_addr.1654712467 |
| Short name | T2207 |
| Test name | |
| Test status | |
| Simulation time | 889425721 ps |
| CPU time | 35.97 seconds |
| Started | Aug 12 06:57:24 PM PDT 24 |
| Finished | Aug 12 06:58:00 PM PDT 24 |
| Peak memory | 575712 kb |
| Host | smart-ab6f94c4-89be-421e-82e4-dab439926818 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1654712467 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 83.xbar_error_and_unmapped_add r.1654712467 |
| Directory | /workspace/83.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/83.xbar_error_random.843765803 |
| Short name | T1481 |
| Test name | |
| Test status | |
| Simulation time | 1365305782 ps |
| CPU time | 48.62 seconds |
| Started | Aug 12 06:57:22 PM PDT 24 |
| Finished | Aug 12 06:58:11 PM PDT 24 |
| Peak memory | 575688 kb |
| Host | smart-40e697d7-498f-462a-b5c6-94b61a941b9a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=843765803 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 83.xbar_error_random.843765803 |
| Directory | /workspace/83.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/83.xbar_random.2951204280 |
| Short name | T720 |
| Test name | |
| Test status | |
| Simulation time | 212043620 ps |
| CPU time | 22.52 seconds |
| Started | Aug 12 06:57:31 PM PDT 24 |
| Finished | Aug 12 06:57:53 PM PDT 24 |
| Peak memory | 575640 kb |
| Host | smart-89e1b1ad-8655-4b05-b127-7911b2a54907 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2951204280 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 83.xbar_random.2951204280 |
| Directory | /workspace/83.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/83.xbar_random_large_delays.3745084200 |
| Short name | T623 |
| Test name | |
| Test status | |
| Simulation time | 89843163202 ps |
| CPU time | 977.69 seconds |
| Started | Aug 12 06:57:21 PM PDT 24 |
| Finished | Aug 12 07:13:39 PM PDT 24 |
| Peak memory | 575684 kb |
| Host | smart-6247e205-83de-40ba-a34d-6ff7d9df33c9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3745084200 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 83.xbar_random_large_delays.3745084200 |
| Directory | /workspace/83.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/83.xbar_random_slow_rsp.1099903014 |
| Short name | T1626 |
| Test name | |
| Test status | |
| Simulation time | 19011302952 ps |
| CPU time | 303.73 seconds |
| Started | Aug 12 06:57:23 PM PDT 24 |
| Finished | Aug 12 07:02:28 PM PDT 24 |
| Peak memory | 575612 kb |
| Host | smart-e80a7f99-8399-4c0d-b332-a8bfabee3ad4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1099903014 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 83.xbar_random_slow_rsp.1099903014 |
| Directory | /workspace/83.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/83.xbar_random_zero_delays.4064717918 |
| Short name | T2328 |
| Test name | |
| Test status | |
| Simulation time | 268748952 ps |
| CPU time | 24.48 seconds |
| Started | Aug 12 06:57:23 PM PDT 24 |
| Finished | Aug 12 06:57:47 PM PDT 24 |
| Peak memory | 575596 kb |
| Host | smart-06c6d31f-8e24-4f32-bbc4-cf0103a2005b |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4064717918 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 83.xbar_random_zero_del ays.4064717918 |
| Directory | /workspace/83.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/83.xbar_same_source.3475837432 |
| Short name | T1655 |
| Test name | |
| Test status | |
| Simulation time | 227463081 ps |
| CPU time | 16.75 seconds |
| Started | Aug 12 06:57:25 PM PDT 24 |
| Finished | Aug 12 06:57:42 PM PDT 24 |
| Peak memory | 575532 kb |
| Host | smart-5601f2bd-c6ba-4dc5-bc14-2bd80da96308 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3475837432 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 83.xbar_same_source.3475837432 |
| Directory | /workspace/83.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/83.xbar_smoke.1779584250 |
| Short name | T1507 |
| Test name | |
| Test status | |
| Simulation time | 51223805 ps |
| CPU time | 6.39 seconds |
| Started | Aug 12 06:57:20 PM PDT 24 |
| Finished | Aug 12 06:57:27 PM PDT 24 |
| Peak memory | 574280 kb |
| Host | smart-44b322b8-1212-4d58-8701-bd94b0385e19 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1779584250 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 83.xbar_smoke.1779584250 |
| Directory | /workspace/83.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/83.xbar_smoke_large_delays.2317854522 |
| Short name | T1480 |
| Test name | |
| Test status | |
| Simulation time | 10296335034 ps |
| CPU time | 110.06 seconds |
| Started | Aug 12 06:57:22 PM PDT 24 |
| Finished | Aug 12 06:59:12 PM PDT 24 |
| Peak memory | 574352 kb |
| Host | smart-f24a436b-4140-4c31-b6cf-d08d9b90810f |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2317854522 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 83.xbar_smoke_large_delays.2317854522 |
| Directory | /workspace/83.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/83.xbar_smoke_slow_rsp.3793003318 |
| Short name | T2098 |
| Test name | |
| Test status | |
| Simulation time | 5282397081 ps |
| CPU time | 91.45 seconds |
| Started | Aug 12 06:57:31 PM PDT 24 |
| Finished | Aug 12 06:59:02 PM PDT 24 |
| Peak memory | 573644 kb |
| Host | smart-d1d88da1-eece-4ba1-a575-f7406c2eb40a |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3793003318 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 83.xbar_smoke_slow_rsp.3793003318 |
| Directory | /workspace/83.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/83.xbar_smoke_zero_delays.367116569 |
| Short name | T2315 |
| Test name | |
| Test status | |
| Simulation time | 39573861 ps |
| CPU time | 5.84 seconds |
| Started | Aug 12 06:57:31 PM PDT 24 |
| Finished | Aug 12 06:57:37 PM PDT 24 |
| Peak memory | 573584 kb |
| Host | smart-6212500b-9c61-4aa3-abab-2b8580872c9d |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=367116569 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 83.xbar_smoke_zero_delays .367116569 |
| Directory | /workspace/83.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/83.xbar_stress_all.3221695318 |
| Short name | T641 |
| Test name | |
| Test status | |
| Simulation time | 4239190253 ps |
| CPU time | 165.03 seconds |
| Started | Aug 12 06:57:31 PM PDT 24 |
| Finished | Aug 12 07:00:16 PM PDT 24 |
| Peak memory | 575980 kb |
| Host | smart-e35080ed-b855-4439-8840-abdc981ad2e6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3221695318 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 83.xbar_stress_all.3221695318 |
| Directory | /workspace/83.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/83.xbar_stress_all_with_error.2487408154 |
| Short name | T2160 |
| Test name | |
| Test status | |
| Simulation time | 2436802772 ps |
| CPU time | 185.24 seconds |
| Started | Aug 12 06:57:31 PM PDT 24 |
| Finished | Aug 12 07:00:36 PM PDT 24 |
| Peak memory | 575768 kb |
| Host | smart-ea624a7b-dc8d-4d51-91e8-2493b140c4e1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2487408154 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 83.xbar_stress_all_with_error.2487408154 |
| Directory | /workspace/83.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/83.xbar_stress_all_with_rand_reset.1764799877 |
| Short name | T1577 |
| Test name | |
| Test status | |
| Simulation time | 105131625 ps |
| CPU time | 24.49 seconds |
| Started | Aug 12 06:57:32 PM PDT 24 |
| Finished | Aug 12 06:57:56 PM PDT 24 |
| Peak memory | 573784 kb |
| Host | smart-5d9091a3-20d1-483e-babe-268262ade527 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1764799877 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 83.xbar_stress_all _with_rand_reset.1764799877 |
| Directory | /workspace/83.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/83.xbar_stress_all_with_reset_error.283200408 |
| Short name | T2839 |
| Test name | |
| Test status | |
| Simulation time | 2069738894 ps |
| CPU time | 357.16 seconds |
| Started | Aug 12 06:57:33 PM PDT 24 |
| Finished | Aug 12 07:03:31 PM PDT 24 |
| Peak memory | 576544 kb |
| Host | smart-2ac9be79-6e65-4e32-b346-42bc1af21133 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=283200408 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 83.xbar_stress_all _with_reset_error.283200408 |
| Directory | /workspace/83.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/83.xbar_unmapped_addr.763080692 |
| Short name | T2870 |
| Test name | |
| Test status | |
| Simulation time | 24969482 ps |
| CPU time | 5.43 seconds |
| Started | Aug 12 06:57:21 PM PDT 24 |
| Finished | Aug 12 06:57:26 PM PDT 24 |
| Peak memory | 573544 kb |
| Host | smart-f9840be0-65d6-4230-b93f-f33dbfb336df |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=763080692 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 83.xbar_unmapped_addr.763080692 |
| Directory | /workspace/83.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/84.xbar_access_same_device.775873636 |
| Short name | T1643 |
| Test name | |
| Test status | |
| Simulation time | 283598998 ps |
| CPU time | 24.09 seconds |
| Started | Aug 12 06:57:33 PM PDT 24 |
| Finished | Aug 12 06:57:57 PM PDT 24 |
| Peak memory | 575704 kb |
| Host | smart-3113d951-657e-4644-98a2-c499623896bd |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=775873636 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 84.xbar_access_same_device. 775873636 |
| Directory | /workspace/84.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/84.xbar_access_same_device_slow_rsp.3299889192 |
| Short name | T1781 |
| Test name | |
| Test status | |
| Simulation time | 125790462584 ps |
| CPU time | 2238.19 seconds |
| Started | Aug 12 06:57:32 PM PDT 24 |
| Finished | Aug 12 07:34:51 PM PDT 24 |
| Peak memory | 575888 kb |
| Host | smart-39aea873-8db5-4643-81e1-9e3ca24982e1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3299889192 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 84.xbar_access_same_ device_slow_rsp.3299889192 |
| Directory | /workspace/84.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/84.xbar_error_and_unmapped_addr.3217525339 |
| Short name | T2167 |
| Test name | |
| Test status | |
| Simulation time | 923154202 ps |
| CPU time | 35.92 seconds |
| Started | Aug 12 06:57:34 PM PDT 24 |
| Finished | Aug 12 06:58:10 PM PDT 24 |
| Peak memory | 575700 kb |
| Host | smart-c96a243d-c8d4-489f-85bd-268f6e6d2434 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3217525339 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 84.xbar_error_and_unmapped_add r.3217525339 |
| Directory | /workspace/84.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/84.xbar_error_random.2753615903 |
| Short name | T2036 |
| Test name | |
| Test status | |
| Simulation time | 86555930 ps |
| CPU time | 6.31 seconds |
| Started | Aug 12 06:57:34 PM PDT 24 |
| Finished | Aug 12 06:57:41 PM PDT 24 |
| Peak memory | 574156 kb |
| Host | smart-2ea6bb0d-b386-4446-88c5-aee3687ce46a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2753615903 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 84.xbar_error_random.2753615903 |
| Directory | /workspace/84.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/84.xbar_random.2519992816 |
| Short name | T1454 |
| Test name | |
| Test status | |
| Simulation time | 765446238 ps |
| CPU time | 29.96 seconds |
| Started | Aug 12 06:57:32 PM PDT 24 |
| Finished | Aug 12 06:58:02 PM PDT 24 |
| Peak memory | 575612 kb |
| Host | smart-5d890006-ca15-4266-937b-09036390b85c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2519992816 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 84.xbar_random.2519992816 |
| Directory | /workspace/84.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/84.xbar_random_large_delays.844621313 |
| Short name | T2059 |
| Test name | |
| Test status | |
| Simulation time | 89830744931 ps |
| CPU time | 979.56 seconds |
| Started | Aug 12 06:57:33 PM PDT 24 |
| Finished | Aug 12 07:13:52 PM PDT 24 |
| Peak memory | 575732 kb |
| Host | smart-98515c4a-d6da-4769-9775-403bf53074c6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=844621313 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 84.xbar_random_large_delays.844621313 |
| Directory | /workspace/84.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/84.xbar_random_slow_rsp.3675982355 |
| Short name | T677 |
| Test name | |
| Test status | |
| Simulation time | 73716893077 ps |
| CPU time | 1357.51 seconds |
| Started | Aug 12 06:57:33 PM PDT 24 |
| Finished | Aug 12 07:20:11 PM PDT 24 |
| Peak memory | 575580 kb |
| Host | smart-dafd1347-08c4-4a2c-b272-05889ab6f7a4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3675982355 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 84.xbar_random_slow_rsp.3675982355 |
| Directory | /workspace/84.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/84.xbar_random_zero_delays.781694080 |
| Short name | T1614 |
| Test name | |
| Test status | |
| Simulation time | 183909423 ps |
| CPU time | 18.22 seconds |
| Started | Aug 12 06:57:32 PM PDT 24 |
| Finished | Aug 12 06:57:50 PM PDT 24 |
| Peak memory | 575588 kb |
| Host | smart-e2b62de2-96c8-4867-b1aa-5efd74bc120e |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=781694080 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 84.xbar_random_zero_dela ys.781694080 |
| Directory | /workspace/84.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/84.xbar_same_source.1449761144 |
| Short name | T1840 |
| Test name | |
| Test status | |
| Simulation time | 1013063683 ps |
| CPU time | 33.36 seconds |
| Started | Aug 12 06:57:33 PM PDT 24 |
| Finished | Aug 12 06:58:06 PM PDT 24 |
| Peak memory | 575548 kb |
| Host | smart-bbc6ac83-8b20-478f-8d35-4abca0ecd779 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1449761144 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 84.xbar_same_source.1449761144 |
| Directory | /workspace/84.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/84.xbar_smoke.676811680 |
| Short name | T1684 |
| Test name | |
| Test status | |
| Simulation time | 257009209 ps |
| CPU time | 10.32 seconds |
| Started | Aug 12 06:57:32 PM PDT 24 |
| Finished | Aug 12 06:57:42 PM PDT 24 |
| Peak memory | 573588 kb |
| Host | smart-776d16ed-19b4-4659-9594-304373ebfae9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=676811680 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 84.xbar_smoke.676811680 |
| Directory | /workspace/84.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/84.xbar_smoke_large_delays.2974402394 |
| Short name | T1860 |
| Test name | |
| Test status | |
| Simulation time | 7545307215 ps |
| CPU time | 78.86 seconds |
| Started | Aug 12 06:57:33 PM PDT 24 |
| Finished | Aug 12 06:58:52 PM PDT 24 |
| Peak memory | 573628 kb |
| Host | smart-01cb6cdc-c2d8-41ba-8759-3997f59f4f5c |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2974402394 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 84.xbar_smoke_large_delays.2974402394 |
| Directory | /workspace/84.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/84.xbar_smoke_slow_rsp.1178231688 |
| Short name | T2364 |
| Test name | |
| Test status | |
| Simulation time | 6855269711 ps |
| CPU time | 109.9 seconds |
| Started | Aug 12 06:57:31 PM PDT 24 |
| Finished | Aug 12 06:59:21 PM PDT 24 |
| Peak memory | 573676 kb |
| Host | smart-20ae00e1-761e-4a39-abf5-01d500ccd7fd |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1178231688 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 84.xbar_smoke_slow_rsp.1178231688 |
| Directory | /workspace/84.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/84.xbar_smoke_zero_delays.1902997673 |
| Short name | T1933 |
| Test name | |
| Test status | |
| Simulation time | 49804208 ps |
| CPU time | 6.97 seconds |
| Started | Aug 12 06:57:33 PM PDT 24 |
| Finished | Aug 12 06:57:40 PM PDT 24 |
| Peak memory | 573544 kb |
| Host | smart-91cb6902-a108-4db2-aa42-c98bf8dbec85 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1902997673 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 84.xbar_smoke_zero_delay s.1902997673 |
| Directory | /workspace/84.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/84.xbar_stress_all_with_error.1834762864 |
| Short name | T764 |
| Test name | |
| Test status | |
| Simulation time | 12038248160 ps |
| CPU time | 438.86 seconds |
| Started | Aug 12 06:57:34 PM PDT 24 |
| Finished | Aug 12 07:04:53 PM PDT 24 |
| Peak memory | 575764 kb |
| Host | smart-853dad96-4b5a-4aa6-94d1-6cb9f68d89f5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1834762864 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 84.xbar_stress_all_with_error.1834762864 |
| Directory | /workspace/84.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/84.xbar_stress_all_with_rand_reset.733367145 |
| Short name | T964 |
| Test name | |
| Test status | |
| Simulation time | 372075002 ps |
| CPU time | 137.96 seconds |
| Started | Aug 12 06:57:33 PM PDT 24 |
| Finished | Aug 12 06:59:51 PM PDT 24 |
| Peak memory | 576492 kb |
| Host | smart-ac2039c4-3e54-4ac0-ab14-9c0d24f78fa2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=733367145 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_res et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 84.xbar_stress_all_ with_rand_reset.733367145 |
| Directory | /workspace/84.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/84.xbar_stress_all_with_reset_error.487963529 |
| Short name | T909 |
| Test name | |
| Test status | |
| Simulation time | 619663929 ps |
| CPU time | 159.45 seconds |
| Started | Aug 12 06:57:34 PM PDT 24 |
| Finished | Aug 12 07:00:13 PM PDT 24 |
| Peak memory | 576524 kb |
| Host | smart-a1104d75-3197-4aee-9c63-1667f5a2ee71 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=487963529 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 84.xbar_stress_all _with_reset_error.487963529 |
| Directory | /workspace/84.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/84.xbar_unmapped_addr.3583287375 |
| Short name | T2227 |
| Test name | |
| Test status | |
| Simulation time | 72836768 ps |
| CPU time | 11.02 seconds |
| Started | Aug 12 06:57:36 PM PDT 24 |
| Finished | Aug 12 06:57:47 PM PDT 24 |
| Peak memory | 575664 kb |
| Host | smart-0a7ac7b4-3aa0-4318-8d91-f7376777d80a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3583287375 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 84.xbar_unmapped_addr.3583287375 |
| Directory | /workspace/84.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/85.xbar_access_same_device.3904326151 |
| Short name | T938 |
| Test name | |
| Test status | |
| Simulation time | 2848315000 ps |
| CPU time | 123.68 seconds |
| Started | Aug 12 06:57:34 PM PDT 24 |
| Finished | Aug 12 06:59:38 PM PDT 24 |
| Peak memory | 575656 kb |
| Host | smart-e17d94e0-87a8-4efa-908d-3285b9c6d899 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3904326151 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 85.xbar_access_same_device .3904326151 |
| Directory | /workspace/85.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/85.xbar_access_same_device_slow_rsp.2681115456 |
| Short name | T2396 |
| Test name | |
| Test status | |
| Simulation time | 130075074885 ps |
| CPU time | 2411.9 seconds |
| Started | Aug 12 06:57:50 PM PDT 24 |
| Finished | Aug 12 07:38:02 PM PDT 24 |
| Peak memory | 575632 kb |
| Host | smart-f82c2a04-7dfe-4323-9e2d-603ad3f095f1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2681115456 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 85.xbar_access_same_ device_slow_rsp.2681115456 |
| Directory | /workspace/85.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/85.xbar_error_and_unmapped_addr.453855566 |
| Short name | T563 |
| Test name | |
| Test status | |
| Simulation time | 131961721 ps |
| CPU time | 7.62 seconds |
| Started | Aug 12 06:57:39 PM PDT 24 |
| Finished | Aug 12 06:57:47 PM PDT 24 |
| Peak memory | 574272 kb |
| Host | smart-87553ace-ccb3-475d-97ab-0d0e6596f56c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=453855566 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 85.xbar_error_and_unmapped_addr .453855566 |
| Directory | /workspace/85.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/85.xbar_error_random.2624113908 |
| Short name | T1615 |
| Test name | |
| Test status | |
| Simulation time | 1740996348 ps |
| CPU time | 54.7 seconds |
| Started | Aug 12 06:57:39 PM PDT 24 |
| Finished | Aug 12 06:58:33 PM PDT 24 |
| Peak memory | 575808 kb |
| Host | smart-98a44cf4-2159-4ff0-9334-3e873e68c31e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2624113908 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 85.xbar_error_random.2624113908 |
| Directory | /workspace/85.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/85.xbar_random.933070155 |
| Short name | T2293 |
| Test name | |
| Test status | |
| Simulation time | 462624720 ps |
| CPU time | 38.9 seconds |
| Started | Aug 12 06:57:36 PM PDT 24 |
| Finished | Aug 12 06:58:15 PM PDT 24 |
| Peak memory | 575488 kb |
| Host | smart-8de2f915-79f9-4c5e-8480-958fc8878055 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=933070155 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 85.xbar_random.933070155 |
| Directory | /workspace/85.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/85.xbar_random_large_delays.2318081709 |
| Short name | T1737 |
| Test name | |
| Test status | |
| Simulation time | 98721288885 ps |
| CPU time | 1103.57 seconds |
| Started | Aug 12 06:57:33 PM PDT 24 |
| Finished | Aug 12 07:15:58 PM PDT 24 |
| Peak memory | 575804 kb |
| Host | smart-ec14a849-20c5-41be-a012-f4a313aa0902 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2318081709 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 85.xbar_random_large_delays.2318081709 |
| Directory | /workspace/85.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/85.xbar_random_slow_rsp.1139509640 |
| Short name | T1612 |
| Test name | |
| Test status | |
| Simulation time | 6247067646 ps |
| CPU time | 111.4 seconds |
| Started | Aug 12 06:57:36 PM PDT 24 |
| Finished | Aug 12 06:59:27 PM PDT 24 |
| Peak memory | 575744 kb |
| Host | smart-e0f813be-839b-4b3d-8951-8ae298bb3b99 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1139509640 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 85.xbar_random_slow_rsp.1139509640 |
| Directory | /workspace/85.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/85.xbar_random_zero_delays.3463802997 |
| Short name | T2262 |
| Test name | |
| Test status | |
| Simulation time | 57572777 ps |
| CPU time | 8.49 seconds |
| Started | Aug 12 06:57:37 PM PDT 24 |
| Finished | Aug 12 06:57:45 PM PDT 24 |
| Peak memory | 575632 kb |
| Host | smart-397471c0-176d-4f6e-9887-a55d4cbd6bba |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3463802997 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 85.xbar_random_zero_del ays.3463802997 |
| Directory | /workspace/85.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/85.xbar_same_source.4252494152 |
| Short name | T2692 |
| Test name | |
| Test status | |
| Simulation time | 1443926647 ps |
| CPU time | 43.21 seconds |
| Started | Aug 12 06:57:40 PM PDT 24 |
| Finished | Aug 12 06:58:24 PM PDT 24 |
| Peak memory | 575520 kb |
| Host | smart-95b365bc-5682-4762-8c80-326bcd1b271a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4252494152 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 85.xbar_same_source.4252494152 |
| Directory | /workspace/85.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/85.xbar_smoke.1467225598 |
| Short name | T2286 |
| Test name | |
| Test status | |
| Simulation time | 40505183 ps |
| CPU time | 5.69 seconds |
| Started | Aug 12 06:57:34 PM PDT 24 |
| Finished | Aug 12 06:57:40 PM PDT 24 |
| Peak memory | 574276 kb |
| Host | smart-f4520ac1-09da-4a3c-b43f-9288ea40818f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1467225598 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 85.xbar_smoke.1467225598 |
| Directory | /workspace/85.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/85.xbar_smoke_large_delays.2335655795 |
| Short name | T2348 |
| Test name | |
| Test status | |
| Simulation time | 7115168249 ps |
| CPU time | 76.8 seconds |
| Started | Aug 12 06:57:31 PM PDT 24 |
| Finished | Aug 12 06:58:48 PM PDT 24 |
| Peak memory | 574336 kb |
| Host | smart-30e3cfab-0ecf-4a4a-a9ad-75299c81ed5a |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2335655795 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 85.xbar_smoke_large_delays.2335655795 |
| Directory | /workspace/85.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/85.xbar_smoke_slow_rsp.830209722 |
| Short name | T2486 |
| Test name | |
| Test status | |
| Simulation time | 7124748790 ps |
| CPU time | 124.74 seconds |
| Started | Aug 12 06:57:35 PM PDT 24 |
| Finished | Aug 12 06:59:40 PM PDT 24 |
| Peak memory | 574336 kb |
| Host | smart-f10dbefb-cd1f-4f4c-938c-79cc16a4b54a |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=830209722 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 85.xbar_smoke_slow_rsp.830209722 |
| Directory | /workspace/85.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/85.xbar_smoke_zero_delays.120339585 |
| Short name | T1536 |
| Test name | |
| Test status | |
| Simulation time | 48168862 ps |
| CPU time | 6.37 seconds |
| Started | Aug 12 06:57:35 PM PDT 24 |
| Finished | Aug 12 06:57:42 PM PDT 24 |
| Peak memory | 573596 kb |
| Host | smart-fcf79e84-b9f8-4685-be8b-6199b2529bcd |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=120339585 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 85.xbar_smoke_zero_delays .120339585 |
| Directory | /workspace/85.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/85.xbar_stress_all.1488700970 |
| Short name | T528 |
| Test name | |
| Test status | |
| Simulation time | 3494799086 ps |
| CPU time | 261.46 seconds |
| Started | Aug 12 06:57:44 PM PDT 24 |
| Finished | Aug 12 07:02:06 PM PDT 24 |
| Peak memory | 575788 kb |
| Host | smart-07cd8905-6856-43ff-8d2a-c342da644bd4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1488700970 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 85.xbar_stress_all.1488700970 |
| Directory | /workspace/85.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/85.xbar_stress_all_with_error.1255768583 |
| Short name | T566 |
| Test name | |
| Test status | |
| Simulation time | 4378738404 ps |
| CPU time | 332.18 seconds |
| Started | Aug 12 06:57:39 PM PDT 24 |
| Finished | Aug 12 07:03:12 PM PDT 24 |
| Peak memory | 576600 kb |
| Host | smart-8fd47dd5-6971-4f99-8548-eda7dfc77f96 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1255768583 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 85.xbar_stress_all_with_error.1255768583 |
| Directory | /workspace/85.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/85.xbar_stress_all_with_rand_reset.1993589622 |
| Short name | T2387 |
| Test name | |
| Test status | |
| Simulation time | 4684041534 ps |
| CPU time | 575.73 seconds |
| Started | Aug 12 06:57:40 PM PDT 24 |
| Finished | Aug 12 07:07:16 PM PDT 24 |
| Peak memory | 575784 kb |
| Host | smart-9e474e6a-cc71-41a3-8fdc-0343223693e7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1993589622 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 85.xbar_stress_all _with_rand_reset.1993589622 |
| Directory | /workspace/85.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/85.xbar_stress_all_with_reset_error.439104008 |
| Short name | T2118 |
| Test name | |
| Test status | |
| Simulation time | 13692411290 ps |
| CPU time | 732.17 seconds |
| Started | Aug 12 06:57:39 PM PDT 24 |
| Finished | Aug 12 07:09:52 PM PDT 24 |
| Peak memory | 577680 kb |
| Host | smart-e625b18f-1686-4f2f-a40e-f128f5c904b2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=439104008 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 85.xbar_stress_all _with_reset_error.439104008 |
| Directory | /workspace/85.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/85.xbar_unmapped_addr.2293790690 |
| Short name | T1755 |
| Test name | |
| Test status | |
| Simulation time | 1123429280 ps |
| CPU time | 45.59 seconds |
| Started | Aug 12 06:57:40 PM PDT 24 |
| Finished | Aug 12 06:58:25 PM PDT 24 |
| Peak memory | 575716 kb |
| Host | smart-80c92059-a3df-49fc-a6e8-3bdd06149456 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2293790690 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 85.xbar_unmapped_addr.2293790690 |
| Directory | /workspace/85.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/86.xbar_access_same_device.23662432 |
| Short name | T533 |
| Test name | |
| Test status | |
| Simulation time | 3390973796 ps |
| CPU time | 143.39 seconds |
| Started | Aug 12 06:57:41 PM PDT 24 |
| Finished | Aug 12 07:00:04 PM PDT 24 |
| Peak memory | 575636 kb |
| Host | smart-dca4826a-aa88-4ea3-8def-4475dc163cce |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23662432 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 86.xbar_access_same_device.23662432 |
| Directory | /workspace/86.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/86.xbar_access_same_device_slow_rsp.1184658826 |
| Short name | T2795 |
| Test name | |
| Test status | |
| Simulation time | 30407422634 ps |
| CPU time | 506.89 seconds |
| Started | Aug 12 06:57:52 PM PDT 24 |
| Finished | Aug 12 07:06:20 PM PDT 24 |
| Peak memory | 575612 kb |
| Host | smart-09937958-92c4-448f-bb9c-06f3311bac2d |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1184658826 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 86.xbar_access_same_ device_slow_rsp.1184658826 |
| Directory | /workspace/86.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/86.xbar_error_and_unmapped_addr.668470097 |
| Short name | T1864 |
| Test name | |
| Test status | |
| Simulation time | 137906912 ps |
| CPU time | 17.84 seconds |
| Started | Aug 12 06:57:39 PM PDT 24 |
| Finished | Aug 12 06:57:57 PM PDT 24 |
| Peak memory | 575760 kb |
| Host | smart-0918ea0d-0542-4644-bd1e-ab6f08503b80 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=668470097 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 86.xbar_error_and_unmapped_addr .668470097 |
| Directory | /workspace/86.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/86.xbar_error_random.2247750509 |
| Short name | T2591 |
| Test name | |
| Test status | |
| Simulation time | 1706853518 ps |
| CPU time | 50.99 seconds |
| Started | Aug 12 06:57:41 PM PDT 24 |
| Finished | Aug 12 06:58:32 PM PDT 24 |
| Peak memory | 575440 kb |
| Host | smart-9208602c-0616-45e9-a36d-881ddeb094c0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2247750509 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 86.xbar_error_random.2247750509 |
| Directory | /workspace/86.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/86.xbar_random.2968503557 |
| Short name | T1977 |
| Test name | |
| Test status | |
| Simulation time | 1093956427 ps |
| CPU time | 36.41 seconds |
| Started | Aug 12 06:57:52 PM PDT 24 |
| Finished | Aug 12 06:58:29 PM PDT 24 |
| Peak memory | 575548 kb |
| Host | smart-fdd475d8-48b2-4344-b2cc-46a700e8cc1f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2968503557 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 86.xbar_random.2968503557 |
| Directory | /workspace/86.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/86.xbar_random_large_delays.2977425262 |
| Short name | T1941 |
| Test name | |
| Test status | |
| Simulation time | 113004495714 ps |
| CPU time | 1256.75 seconds |
| Started | Aug 12 06:57:44 PM PDT 24 |
| Finished | Aug 12 07:18:41 PM PDT 24 |
| Peak memory | 575664 kb |
| Host | smart-ea49947e-0ac3-472b-b08f-76454576550c |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2977425262 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 86.xbar_random_large_delays.2977425262 |
| Directory | /workspace/86.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/86.xbar_random_slow_rsp.2823094608 |
| Short name | T1942 |
| Test name | |
| Test status | |
| Simulation time | 2905456024 ps |
| CPU time | 46.14 seconds |
| Started | Aug 12 06:57:50 PM PDT 24 |
| Finished | Aug 12 06:58:37 PM PDT 24 |
| Peak memory | 573640 kb |
| Host | smart-2f56979e-c101-4f4c-af5b-4a0e1d6bdb85 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2823094608 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 86.xbar_random_slow_rsp.2823094608 |
| Directory | /workspace/86.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/86.xbar_random_zero_delays.3619828246 |
| Short name | T648 |
| Test name | |
| Test status | |
| Simulation time | 600500655 ps |
| CPU time | 48.64 seconds |
| Started | Aug 12 06:57:40 PM PDT 24 |
| Finished | Aug 12 06:58:28 PM PDT 24 |
| Peak memory | 575712 kb |
| Host | smart-dea7254e-65dc-4661-90cb-4ff9dd7428a6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3619828246 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 86.xbar_random_zero_del ays.3619828246 |
| Directory | /workspace/86.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/86.xbar_same_source.776406232 |
| Short name | T742 |
| Test name | |
| Test status | |
| Simulation time | 1192013367 ps |
| CPU time | 37.39 seconds |
| Started | Aug 12 06:57:50 PM PDT 24 |
| Finished | Aug 12 06:58:28 PM PDT 24 |
| Peak memory | 575672 kb |
| Host | smart-f4be3334-6b33-4274-ba07-fe930d8b4749 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=776406232 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 86.xbar_same_source.776406232 |
| Directory | /workspace/86.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/86.xbar_smoke.4288273864 |
| Short name | T2545 |
| Test name | |
| Test status | |
| Simulation time | 48090785 ps |
| CPU time | 6.17 seconds |
| Started | Aug 12 06:57:52 PM PDT 24 |
| Finished | Aug 12 06:57:58 PM PDT 24 |
| Peak memory | 573556 kb |
| Host | smart-201eea8f-f8b7-438a-be41-a2abd4d928f0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4288273864 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 86.xbar_smoke.4288273864 |
| Directory | /workspace/86.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/86.xbar_smoke_large_delays.236432027 |
| Short name | T1957 |
| Test name | |
| Test status | |
| Simulation time | 6328227843 ps |
| CPU time | 63.59 seconds |
| Started | Aug 12 06:57:44 PM PDT 24 |
| Finished | Aug 12 06:58:47 PM PDT 24 |
| Peak memory | 573692 kb |
| Host | smart-e758e88d-bed2-4c51-86dc-f7b00fa48db7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=236432027 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 86.xbar_smoke_large_delays.236432027 |
| Directory | /workspace/86.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/86.xbar_smoke_slow_rsp.2185797652 |
| Short name | T1951 |
| Test name | |
| Test status | |
| Simulation time | 3468735411 ps |
| CPU time | 57.49 seconds |
| Started | Aug 12 06:57:44 PM PDT 24 |
| Finished | Aug 12 06:58:41 PM PDT 24 |
| Peak memory | 573576 kb |
| Host | smart-1cf70666-f869-4062-8f11-7e22051e6479 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2185797652 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 86.xbar_smoke_slow_rsp.2185797652 |
| Directory | /workspace/86.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/86.xbar_smoke_zero_delays.1229438800 |
| Short name | T2369 |
| Test name | |
| Test status | |
| Simulation time | 53769890 ps |
| CPU time | 6.84 seconds |
| Started | Aug 12 06:57:40 PM PDT 24 |
| Finished | Aug 12 06:57:47 PM PDT 24 |
| Peak memory | 574404 kb |
| Host | smart-512a87f8-b8ff-4a25-85c6-4f7a7c6678d0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1229438800 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 86.xbar_smoke_zero_delay s.1229438800 |
| Directory | /workspace/86.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/86.xbar_stress_all.3441992703 |
| Short name | T2583 |
| Test name | |
| Test status | |
| Simulation time | 16330943300 ps |
| CPU time | 637.24 seconds |
| Started | Aug 12 06:57:50 PM PDT 24 |
| Finished | Aug 12 07:08:27 PM PDT 24 |
| Peak memory | 575808 kb |
| Host | smart-1120fb35-1680-48d2-a2b4-c70e7110699f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3441992703 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 86.xbar_stress_all.3441992703 |
| Directory | /workspace/86.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/86.xbar_stress_all_with_error.783945766 |
| Short name | T2864 |
| Test name | |
| Test status | |
| Simulation time | 409934570 ps |
| CPU time | 27.91 seconds |
| Started | Aug 12 06:57:41 PM PDT 24 |
| Finished | Aug 12 06:58:09 PM PDT 24 |
| Peak memory | 575640 kb |
| Host | smart-f529368f-d522-4618-a49d-19486162f7df |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=783945766 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 86.xbar_stress_all_with_error.783945766 |
| Directory | /workspace/86.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/86.xbar_stress_all_with_rand_reset.3839000433 |
| Short name | T2316 |
| Test name | |
| Test status | |
| Simulation time | 47033656 ps |
| CPU time | 12.76 seconds |
| Started | Aug 12 06:57:51 PM PDT 24 |
| Finished | Aug 12 06:58:04 PM PDT 24 |
| Peak memory | 575956 kb |
| Host | smart-8d5616c4-464c-48b7-8a01-d780fce205fe |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3839000433 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 86.xbar_stress_all _with_rand_reset.3839000433 |
| Directory | /workspace/86.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/86.xbar_stress_all_with_reset_error.1764781087 |
| Short name | T2163 |
| Test name | |
| Test status | |
| Simulation time | 357736742 ps |
| CPU time | 119.58 seconds |
| Started | Aug 12 06:57:45 PM PDT 24 |
| Finished | Aug 12 06:59:45 PM PDT 24 |
| Peak memory | 575712 kb |
| Host | smart-5a0b4d80-63c4-448c-8848-792e7b101d70 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1764781087 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 86.xbar_stress_al l_with_reset_error.1764781087 |
| Directory | /workspace/86.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/86.xbar_unmapped_addr.4272720975 |
| Short name | T1599 |
| Test name | |
| Test status | |
| Simulation time | 485882030 ps |
| CPU time | 21.41 seconds |
| Started | Aug 12 06:57:39 PM PDT 24 |
| Finished | Aug 12 06:58:01 PM PDT 24 |
| Peak memory | 575708 kb |
| Host | smart-d346f7fd-e404-4f8b-b625-e9c2bf696016 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4272720975 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 86.xbar_unmapped_addr.4272720975 |
| Directory | /workspace/86.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/87.xbar_access_same_device.1500019562 |
| Short name | T2111 |
| Test name | |
| Test status | |
| Simulation time | 686001323 ps |
| CPU time | 32.05 seconds |
| Started | Aug 12 06:57:52 PM PDT 24 |
| Finished | Aug 12 06:58:24 PM PDT 24 |
| Peak memory | 575716 kb |
| Host | smart-2ed10087-cbb9-4b18-ab42-3823f4efb321 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1500019562 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 87.xbar_access_same_device .1500019562 |
| Directory | /workspace/87.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/87.xbar_access_same_device_slow_rsp.408007747 |
| Short name | T2213 |
| Test name | |
| Test status | |
| Simulation time | 105118017205 ps |
| CPU time | 1743.36 seconds |
| Started | Aug 12 06:57:47 PM PDT 24 |
| Finished | Aug 12 07:26:50 PM PDT 24 |
| Peak memory | 575804 kb |
| Host | smart-c9f323c9-ddb8-4511-8cae-d40ecf28a83d |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=408007747 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 87.xbar_access_same_d evice_slow_rsp.408007747 |
| Directory | /workspace/87.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/87.xbar_error_and_unmapped_addr.746981049 |
| Short name | T2532 |
| Test name | |
| Test status | |
| Simulation time | 110608477 ps |
| CPU time | 14.08 seconds |
| Started | Aug 12 06:57:52 PM PDT 24 |
| Finished | Aug 12 06:58:07 PM PDT 24 |
| Peak memory | 575760 kb |
| Host | smart-c8a91a15-4a38-4eda-9b9d-63b98c558970 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=746981049 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 87.xbar_error_and_unmapped_addr .746981049 |
| Directory | /workspace/87.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/87.xbar_error_random.2468860553 |
| Short name | T2510 |
| Test name | |
| Test status | |
| Simulation time | 2301399568 ps |
| CPU time | 75.45 seconds |
| Started | Aug 12 06:57:49 PM PDT 24 |
| Finished | Aug 12 06:59:04 PM PDT 24 |
| Peak memory | 575764 kb |
| Host | smart-698eb5c7-57dc-4a6e-999a-fcc611fb1f48 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2468860553 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 87.xbar_error_random.2468860553 |
| Directory | /workspace/87.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/87.xbar_random.1597719051 |
| Short name | T1910 |
| Test name | |
| Test status | |
| Simulation time | 2445806925 ps |
| CPU time | 82.32 seconds |
| Started | Aug 12 06:57:50 PM PDT 24 |
| Finished | Aug 12 06:59:12 PM PDT 24 |
| Peak memory | 575632 kb |
| Host | smart-635a8a8c-d412-4d93-b4f2-da679e4aeb43 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1597719051 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 87.xbar_random.1597719051 |
| Directory | /workspace/87.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/87.xbar_random_large_delays.2425808921 |
| Short name | T2084 |
| Test name | |
| Test status | |
| Simulation time | 100106389737 ps |
| CPU time | 1127.36 seconds |
| Started | Aug 12 06:57:53 PM PDT 24 |
| Finished | Aug 12 07:16:41 PM PDT 24 |
| Peak memory | 575728 kb |
| Host | smart-72d7438f-5804-47c6-8c34-40d4d7f48ff0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2425808921 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 87.xbar_random_large_delays.2425808921 |
| Directory | /workspace/87.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/87.xbar_random_slow_rsp.1077836012 |
| Short name | T2006 |
| Test name | |
| Test status | |
| Simulation time | 27798123210 ps |
| CPU time | 460.68 seconds |
| Started | Aug 12 06:57:50 PM PDT 24 |
| Finished | Aug 12 07:05:32 PM PDT 24 |
| Peak memory | 575716 kb |
| Host | smart-d84f8f5b-fa29-47e7-aa47-a76610322623 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1077836012 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 87.xbar_random_slow_rsp.1077836012 |
| Directory | /workspace/87.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/87.xbar_random_zero_delays.219363288 |
| Short name | T2548 |
| Test name | |
| Test status | |
| Simulation time | 322536002 ps |
| CPU time | 33.19 seconds |
| Started | Aug 12 06:57:50 PM PDT 24 |
| Finished | Aug 12 06:58:23 PM PDT 24 |
| Peak memory | 575708 kb |
| Host | smart-c756c5df-fe43-43c2-932d-f3e327b73004 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=219363288 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 87.xbar_random_zero_dela ys.219363288 |
| Directory | /workspace/87.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/87.xbar_same_source.3367833193 |
| Short name | T2610 |
| Test name | |
| Test status | |
| Simulation time | 2163129525 ps |
| CPU time | 62.67 seconds |
| Started | Aug 12 06:57:54 PM PDT 24 |
| Finished | Aug 12 06:58:57 PM PDT 24 |
| Peak memory | 575684 kb |
| Host | smart-e5a3d36f-7575-4617-b7b0-f1ec427f96aa |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3367833193 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 87.xbar_same_source.3367833193 |
| Directory | /workspace/87.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/87.xbar_smoke.2358660375 |
| Short name | T2017 |
| Test name | |
| Test status | |
| Simulation time | 202147791 ps |
| CPU time | 9.35 seconds |
| Started | Aug 12 06:57:38 PM PDT 24 |
| Finished | Aug 12 06:57:47 PM PDT 24 |
| Peak memory | 573592 kb |
| Host | smart-f19ff619-847d-4c29-a384-f52e50d24760 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2358660375 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 87.xbar_smoke.2358660375 |
| Directory | /workspace/87.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/87.xbar_smoke_large_delays.538831342 |
| Short name | T2393 |
| Test name | |
| Test status | |
| Simulation time | 10060480704 ps |
| CPU time | 90.79 seconds |
| Started | Aug 12 06:57:54 PM PDT 24 |
| Finished | Aug 12 06:59:24 PM PDT 24 |
| Peak memory | 573632 kb |
| Host | smart-0c66ea2f-9bef-4932-a1a0-5187ab61c37f |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=538831342 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 87.xbar_smoke_large_delays.538831342 |
| Directory | /workspace/87.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/87.xbar_smoke_slow_rsp.3692192722 |
| Short name | T730 |
| Test name | |
| Test status | |
| Simulation time | 6234759260 ps |
| CPU time | 106.37 seconds |
| Started | Aug 12 06:57:48 PM PDT 24 |
| Finished | Aug 12 06:59:34 PM PDT 24 |
| Peak memory | 573684 kb |
| Host | smart-5d3a02c9-c1d2-4d4c-b2b4-0deff724ce4a |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3692192722 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 87.xbar_smoke_slow_rsp.3692192722 |
| Directory | /workspace/87.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/87.xbar_smoke_zero_delays.2046336265 |
| Short name | T1478 |
| Test name | |
| Test status | |
| Simulation time | 44131499 ps |
| CPU time | 5.78 seconds |
| Started | Aug 12 06:57:48 PM PDT 24 |
| Finished | Aug 12 06:57:54 PM PDT 24 |
| Peak memory | 574300 kb |
| Host | smart-febfa360-c436-4923-a1c2-c8426fe8a0c2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2046336265 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 87.xbar_smoke_zero_delay s.2046336265 |
| Directory | /workspace/87.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/87.xbar_stress_all.2232043352 |
| Short name | T2683 |
| Test name | |
| Test status | |
| Simulation time | 1322678687 ps |
| CPU time | 108.87 seconds |
| Started | Aug 12 06:57:48 PM PDT 24 |
| Finished | Aug 12 06:59:37 PM PDT 24 |
| Peak memory | 576424 kb |
| Host | smart-95ef23e5-c29c-4be4-ace4-3aa6a9fdb151 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2232043352 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 87.xbar_stress_all.2232043352 |
| Directory | /workspace/87.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/87.xbar_stress_all_with_error.830481774 |
| Short name | T1895 |
| Test name | |
| Test status | |
| Simulation time | 1865076104 ps |
| CPU time | 141.73 seconds |
| Started | Aug 12 06:57:48 PM PDT 24 |
| Finished | Aug 12 07:00:10 PM PDT 24 |
| Peak memory | 575844 kb |
| Host | smart-08f40602-613e-43c2-ae95-f14c68397b0b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=830481774 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 87.xbar_stress_all_with_error.830481774 |
| Directory | /workspace/87.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/87.xbar_stress_all_with_rand_reset.1832543821 |
| Short name | T1876 |
| Test name | |
| Test status | |
| Simulation time | 1222776817 ps |
| CPU time | 147.82 seconds |
| Started | Aug 12 06:57:52 PM PDT 24 |
| Finished | Aug 12 07:00:20 PM PDT 24 |
| Peak memory | 576508 kb |
| Host | smart-2e115c33-9bdc-4126-9fd8-0312bfd069f1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1832543821 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 87.xbar_stress_all _with_rand_reset.1832543821 |
| Directory | /workspace/87.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/87.xbar_stress_all_with_reset_error.2628812148 |
| Short name | T2022 |
| Test name | |
| Test status | |
| Simulation time | 3278822511 ps |
| CPU time | 259.82 seconds |
| Started | Aug 12 06:57:48 PM PDT 24 |
| Finished | Aug 12 07:02:08 PM PDT 24 |
| Peak memory | 576600 kb |
| Host | smart-e39dbdd6-2894-4d85-9e49-23e60201b819 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2628812148 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 87.xbar_stress_al l_with_reset_error.2628812148 |
| Directory | /workspace/87.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/87.xbar_unmapped_addr.4244905803 |
| Short name | T2128 |
| Test name | |
| Test status | |
| Simulation time | 622246743 ps |
| CPU time | 23.76 seconds |
| Started | Aug 12 06:57:48 PM PDT 24 |
| Finished | Aug 12 06:58:12 PM PDT 24 |
| Peak memory | 575572 kb |
| Host | smart-1d0f865b-78bd-4b2a-b171-10f49082bd5c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4244905803 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 87.xbar_unmapped_addr.4244905803 |
| Directory | /workspace/87.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/88.xbar_access_same_device.2852253098 |
| Short name | T2455 |
| Test name | |
| Test status | |
| Simulation time | 999156542 ps |
| CPU time | 66.25 seconds |
| Started | Aug 12 06:57:58 PM PDT 24 |
| Finished | Aug 12 06:59:04 PM PDT 24 |
| Peak memory | 575748 kb |
| Host | smart-3dc877b9-98cc-4711-85ff-55318ec4b253 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2852253098 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 88.xbar_access_same_device .2852253098 |
| Directory | /workspace/88.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/88.xbar_access_same_device_slow_rsp.293303318 |
| Short name | T2815 |
| Test name | |
| Test status | |
| Simulation time | 137267021810 ps |
| CPU time | 2252.9 seconds |
| Started | Aug 12 06:58:01 PM PDT 24 |
| Finished | Aug 12 07:35:34 PM PDT 24 |
| Peak memory | 575888 kb |
| Host | smart-caa8e60c-2ba3-406f-8b7a-0dc3df6ec053 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=293303318 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 88.xbar_access_same_d evice_slow_rsp.293303318 |
| Directory | /workspace/88.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/88.xbar_error_and_unmapped_addr.1920194368 |
| Short name | T1925 |
| Test name | |
| Test status | |
| Simulation time | 231383007 ps |
| CPU time | 11.57 seconds |
| Started | Aug 12 06:58:12 PM PDT 24 |
| Finished | Aug 12 06:58:24 PM PDT 24 |
| Peak memory | 575720 kb |
| Host | smart-d99f331f-b510-4700-b052-579051e5a5bf |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1920194368 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 88.xbar_error_and_unmapped_add r.1920194368 |
| Directory | /workspace/88.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/88.xbar_error_random.3866023041 |
| Short name | T1597 |
| Test name | |
| Test status | |
| Simulation time | 143280003 ps |
| CPU time | 14.4 seconds |
| Started | Aug 12 06:58:09 PM PDT 24 |
| Finished | Aug 12 06:58:24 PM PDT 24 |
| Peak memory | 575664 kb |
| Host | smart-1baa167f-bfe9-4ac7-8456-f16b284eadd2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3866023041 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 88.xbar_error_random.3866023041 |
| Directory | /workspace/88.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/88.xbar_random.718311071 |
| Short name | T527 |
| Test name | |
| Test status | |
| Simulation time | 1119182845 ps |
| CPU time | 33.34 seconds |
| Started | Aug 12 06:57:58 PM PDT 24 |
| Finished | Aug 12 06:58:31 PM PDT 24 |
| Peak memory | 575744 kb |
| Host | smart-e32c3305-268e-4e64-94ba-a24167428076 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=718311071 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 88.xbar_random.718311071 |
| Directory | /workspace/88.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/88.xbar_random_large_delays.391238191 |
| Short name | T2508 |
| Test name | |
| Test status | |
| Simulation time | 98018586077 ps |
| CPU time | 984.67 seconds |
| Started | Aug 12 06:57:59 PM PDT 24 |
| Finished | Aug 12 07:14:24 PM PDT 24 |
| Peak memory | 575832 kb |
| Host | smart-e280da2a-322f-40cb-8a85-a30c36298cd0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=391238191 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 88.xbar_random_large_delays.391238191 |
| Directory | /workspace/88.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/88.xbar_random_slow_rsp.1385346755 |
| Short name | T1680 |
| Test name | |
| Test status | |
| Simulation time | 6508653374 ps |
| CPU time | 113.75 seconds |
| Started | Aug 12 06:57:57 PM PDT 24 |
| Finished | Aug 12 06:59:51 PM PDT 24 |
| Peak memory | 575776 kb |
| Host | smart-505d0503-f7cd-41be-9715-f4ceb0a79583 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1385346755 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 88.xbar_random_slow_rsp.1385346755 |
| Directory | /workspace/88.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/88.xbar_random_zero_delays.4106031211 |
| Short name | T583 |
| Test name | |
| Test status | |
| Simulation time | 580105145 ps |
| CPU time | 49.57 seconds |
| Started | Aug 12 06:58:00 PM PDT 24 |
| Finished | Aug 12 06:58:50 PM PDT 24 |
| Peak memory | 575668 kb |
| Host | smart-44f3553c-797f-43bc-852a-87650507fe4a |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4106031211 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 88.xbar_random_zero_del ays.4106031211 |
| Directory | /workspace/88.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/88.xbar_same_source.2185320759 |
| Short name | T2034 |
| Test name | |
| Test status | |
| Simulation time | 40980208 ps |
| CPU time | 5.52 seconds |
| Started | Aug 12 06:57:57 PM PDT 24 |
| Finished | Aug 12 06:58:03 PM PDT 24 |
| Peak memory | 574292 kb |
| Host | smart-442239ef-5c58-411e-8c06-f9a8a2d3677b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2185320759 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 88.xbar_same_source.2185320759 |
| Directory | /workspace/88.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/88.xbar_smoke.3420802415 |
| Short name | T727 |
| Test name | |
| Test status | |
| Simulation time | 235043934 ps |
| CPU time | 9.29 seconds |
| Started | Aug 12 06:57:58 PM PDT 24 |
| Finished | Aug 12 06:58:07 PM PDT 24 |
| Peak memory | 574160 kb |
| Host | smart-1326e271-cbf6-4d52-9b15-e15e42196d04 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3420802415 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 88.xbar_smoke.3420802415 |
| Directory | /workspace/88.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/88.xbar_smoke_large_delays.1296437337 |
| Short name | T2126 |
| Test name | |
| Test status | |
| Simulation time | 7872651124 ps |
| CPU time | 80.53 seconds |
| Started | Aug 12 06:57:58 PM PDT 24 |
| Finished | Aug 12 06:59:19 PM PDT 24 |
| Peak memory | 573628 kb |
| Host | smart-4fc4dac8-ef4b-4773-ac62-b44496bb4c5c |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1296437337 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 88.xbar_smoke_large_delays.1296437337 |
| Directory | /workspace/88.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/88.xbar_smoke_slow_rsp.1101508551 |
| Short name | T1502 |
| Test name | |
| Test status | |
| Simulation time | 5654843372 ps |
| CPU time | 86.61 seconds |
| Started | Aug 12 06:58:00 PM PDT 24 |
| Finished | Aug 12 06:59:27 PM PDT 24 |
| Peak memory | 573672 kb |
| Host | smart-ca92b05b-21c5-4be8-9150-3c1ff3b8a087 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1101508551 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 88.xbar_smoke_slow_rsp.1101508551 |
| Directory | /workspace/88.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/88.xbar_smoke_zero_delays.1315552843 |
| Short name | T2863 |
| Test name | |
| Test status | |
| Simulation time | 51039083 ps |
| CPU time | 6.51 seconds |
| Started | Aug 12 06:57:59 PM PDT 24 |
| Finished | Aug 12 06:58:06 PM PDT 24 |
| Peak memory | 573600 kb |
| Host | smart-7898b116-82cc-4960-86b3-258ec01d2e3b |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1315552843 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 88.xbar_smoke_zero_delay s.1315552843 |
| Directory | /workspace/88.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/88.xbar_stress_all.2089326326 |
| Short name | T2161 |
| Test name | |
| Test status | |
| Simulation time | 9238911775 ps |
| CPU time | 313.3 seconds |
| Started | Aug 12 06:58:10 PM PDT 24 |
| Finished | Aug 12 07:03:24 PM PDT 24 |
| Peak memory | 576556 kb |
| Host | smart-579c8e42-172b-4449-aaaa-a05a9d1a705d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2089326326 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 88.xbar_stress_all.2089326326 |
| Directory | /workspace/88.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/88.xbar_stress_all_with_error.2345920219 |
| Short name | T1883 |
| Test name | |
| Test status | |
| Simulation time | 1135114327 ps |
| CPU time | 43.05 seconds |
| Started | Aug 12 06:58:08 PM PDT 24 |
| Finished | Aug 12 06:58:51 PM PDT 24 |
| Peak memory | 575696 kb |
| Host | smart-3f2df23e-ef87-4f4e-a40b-b9e09c44ec76 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2345920219 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 88.xbar_stress_all_with_error.2345920219 |
| Directory | /workspace/88.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/88.xbar_stress_all_with_rand_reset.3456840807 |
| Short name | T529 |
| Test name | |
| Test status | |
| Simulation time | 18072018253 ps |
| CPU time | 1148.26 seconds |
| Started | Aug 12 06:58:09 PM PDT 24 |
| Finished | Aug 12 07:17:17 PM PDT 24 |
| Peak memory | 576652 kb |
| Host | smart-e7448c3d-8e12-439b-a194-f7d4808f8117 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3456840807 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 88.xbar_stress_all _with_rand_reset.3456840807 |
| Directory | /workspace/88.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/88.xbar_stress_all_with_reset_error.3778475197 |
| Short name | T1574 |
| Test name | |
| Test status | |
| Simulation time | 3375792252 ps |
| CPU time | 334.87 seconds |
| Started | Aug 12 06:58:11 PM PDT 24 |
| Finished | Aug 12 07:03:47 PM PDT 24 |
| Peak memory | 576640 kb |
| Host | smart-762ba1ce-af83-4c88-98f3-a18635d04740 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3778475197 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 88.xbar_stress_al l_with_reset_error.3778475197 |
| Directory | /workspace/88.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/88.xbar_unmapped_addr.2677106497 |
| Short name | T2277 |
| Test name | |
| Test status | |
| Simulation time | 273161989 ps |
| CPU time | 31.44 seconds |
| Started | Aug 12 06:58:09 PM PDT 24 |
| Finished | Aug 12 06:58:41 PM PDT 24 |
| Peak memory | 575776 kb |
| Host | smart-2b12bcaf-456f-446e-a005-bc972e91ff58 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2677106497 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 88.xbar_unmapped_addr.2677106497 |
| Directory | /workspace/88.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/89.xbar_access_same_device.1902384216 |
| Short name | T2221 |
| Test name | |
| Test status | |
| Simulation time | 672150210 ps |
| CPU time | 65.53 seconds |
| Started | Aug 12 06:58:11 PM PDT 24 |
| Finished | Aug 12 06:59:17 PM PDT 24 |
| Peak memory | 575548 kb |
| Host | smart-b183fc4d-7faa-4e3c-9ce1-f2e11ffef8c3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1902384216 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 89.xbar_access_same_device .1902384216 |
| Directory | /workspace/89.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/89.xbar_access_same_device_slow_rsp.278266109 |
| Short name | T935 |
| Test name | |
| Test status | |
| Simulation time | 55392731936 ps |
| CPU time | 1055.85 seconds |
| Started | Aug 12 06:58:09 PM PDT 24 |
| Finished | Aug 12 07:15:45 PM PDT 24 |
| Peak memory | 575812 kb |
| Host | smart-a1388252-5927-463e-904c-bf7a6eebcf93 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=278266109 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 89.xbar_access_same_d evice_slow_rsp.278266109 |
| Directory | /workspace/89.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/89.xbar_error_and_unmapped_addr.959436064 |
| Short name | T1475 |
| Test name | |
| Test status | |
| Simulation time | 340854321 ps |
| CPU time | 14.34 seconds |
| Started | Aug 12 06:58:19 PM PDT 24 |
| Finished | Aug 12 06:58:34 PM PDT 24 |
| Peak memory | 575524 kb |
| Host | smart-0d00dda3-466c-4b7e-b2dc-17d0079618ed |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=959436064 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 89.xbar_error_and_unmapped_addr .959436064 |
| Directory | /workspace/89.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/89.xbar_error_random.69650889 |
| Short name | T1641 |
| Test name | |
| Test status | |
| Simulation time | 122632489 ps |
| CPU time | 12.55 seconds |
| Started | Aug 12 06:58:08 PM PDT 24 |
| Finished | Aug 12 06:58:21 PM PDT 24 |
| Peak memory | 575724 kb |
| Host | smart-40bf36bc-244a-4051-b74c-ede2dbc73d02 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=69650889 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 89.xbar_error_random.69650889 |
| Directory | /workspace/89.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/89.xbar_random.3165879169 |
| Short name | T2030 |
| Test name | |
| Test status | |
| Simulation time | 574767079 ps |
| CPU time | 47.29 seconds |
| Started | Aug 12 06:58:07 PM PDT 24 |
| Finished | Aug 12 06:58:55 PM PDT 24 |
| Peak memory | 575664 kb |
| Host | smart-832740cc-93df-4537-87b9-b28a55754d3a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3165879169 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 89.xbar_random.3165879169 |
| Directory | /workspace/89.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/89.xbar_random_large_delays.366324659 |
| Short name | T2733 |
| Test name | |
| Test status | |
| Simulation time | 14104742149 ps |
| CPU time | 158.61 seconds |
| Started | Aug 12 06:58:09 PM PDT 24 |
| Finished | Aug 12 07:00:48 PM PDT 24 |
| Peak memory | 575660 kb |
| Host | smart-d1465ad7-399e-4e48-ab5f-83aac77dab58 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=366324659 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 89.xbar_random_large_delays.366324659 |
| Directory | /workspace/89.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/89.xbar_random_slow_rsp.1524112443 |
| Short name | T717 |
| Test name | |
| Test status | |
| Simulation time | 68475494163 ps |
| CPU time | 1256.51 seconds |
| Started | Aug 12 06:58:08 PM PDT 24 |
| Finished | Aug 12 07:19:05 PM PDT 24 |
| Peak memory | 575732 kb |
| Host | smart-a7a2e835-e9f2-4447-8d66-e2f3495a6625 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1524112443 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 89.xbar_random_slow_rsp.1524112443 |
| Directory | /workspace/89.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/89.xbar_random_zero_delays.2786131173 |
| Short name | T1732 |
| Test name | |
| Test status | |
| Simulation time | 201074438 ps |
| CPU time | 20.05 seconds |
| Started | Aug 12 06:58:08 PM PDT 24 |
| Finished | Aug 12 06:58:28 PM PDT 24 |
| Peak memory | 575660 kb |
| Host | smart-f4808fe7-8ca1-4e2b-9571-01b73a4b0e51 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2786131173 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 89.xbar_random_zero_del ays.2786131173 |
| Directory | /workspace/89.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/89.xbar_same_source.769752239 |
| Short name | T1900 |
| Test name | |
| Test status | |
| Simulation time | 1842631827 ps |
| CPU time | 54.84 seconds |
| Started | Aug 12 06:58:09 PM PDT 24 |
| Finished | Aug 12 06:59:04 PM PDT 24 |
| Peak memory | 575532 kb |
| Host | smart-2a696ccd-f06f-4f55-9765-e0af3813c226 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=769752239 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 89.xbar_same_source.769752239 |
| Directory | /workspace/89.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/89.xbar_smoke.2445179987 |
| Short name | T1456 |
| Test name | |
| Test status | |
| Simulation time | 45151684 ps |
| CPU time | 6.36 seconds |
| Started | Aug 12 06:58:08 PM PDT 24 |
| Finished | Aug 12 06:58:14 PM PDT 24 |
| Peak memory | 573668 kb |
| Host | smart-503bcf31-a19b-41e6-b77f-12ac40f42edf |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2445179987 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 89.xbar_smoke.2445179987 |
| Directory | /workspace/89.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/89.xbar_smoke_large_delays.377239348 |
| Short name | T1913 |
| Test name | |
| Test status | |
| Simulation time | 4827494510 ps |
| CPU time | 52.6 seconds |
| Started | Aug 12 06:58:08 PM PDT 24 |
| Finished | Aug 12 06:59:01 PM PDT 24 |
| Peak memory | 573624 kb |
| Host | smart-124fa371-fb98-4f40-8e34-ec3d3952f935 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=377239348 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 89.xbar_smoke_large_delays.377239348 |
| Directory | /workspace/89.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/89.xbar_smoke_slow_rsp.542063129 |
| Short name | T1609 |
| Test name | |
| Test status | |
| Simulation time | 5526078470 ps |
| CPU time | 99.43 seconds |
| Started | Aug 12 06:58:08 PM PDT 24 |
| Finished | Aug 12 06:59:48 PM PDT 24 |
| Peak memory | 573656 kb |
| Host | smart-dbc13d62-bdaa-433b-a014-9aa0b2fce491 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=542063129 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 89.xbar_smoke_slow_rsp.542063129 |
| Directory | /workspace/89.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/89.xbar_smoke_zero_delays.2297563061 |
| Short name | T1592 |
| Test name | |
| Test status | |
| Simulation time | 51149408 ps |
| CPU time | 5.99 seconds |
| Started | Aug 12 06:58:11 PM PDT 24 |
| Finished | Aug 12 06:58:17 PM PDT 24 |
| Peak memory | 573612 kb |
| Host | smart-e2397e6d-42fb-4ed1-b994-ce8a2de319f8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2297563061 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 89.xbar_smoke_zero_delay s.2297563061 |
| Directory | /workspace/89.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/89.xbar_stress_all.3064372363 |
| Short name | T520 |
| Test name | |
| Test status | |
| Simulation time | 1177209919 ps |
| CPU time | 105.74 seconds |
| Started | Aug 12 06:58:18 PM PDT 24 |
| Finished | Aug 12 07:00:04 PM PDT 24 |
| Peak memory | 575700 kb |
| Host | smart-22348d40-3188-4cc1-a159-8485ce81d2b0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3064372363 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 89.xbar_stress_all.3064372363 |
| Directory | /workspace/89.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/89.xbar_stress_all_with_error.2836232253 |
| Short name | T1539 |
| Test name | |
| Test status | |
| Simulation time | 1195019228 ps |
| CPU time | 90.24 seconds |
| Started | Aug 12 06:58:17 PM PDT 24 |
| Finished | Aug 12 06:59:47 PM PDT 24 |
| Peak memory | 575744 kb |
| Host | smart-e1693c67-94fb-441d-9c93-db10f563dfd7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2836232253 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 89.xbar_stress_all_with_error.2836232253 |
| Directory | /workspace/89.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/89.xbar_stress_all_with_rand_reset.1621892801 |
| Short name | T1676 |
| Test name | |
| Test status | |
| Simulation time | 60440667 ps |
| CPU time | 51.24 seconds |
| Started | Aug 12 06:58:15 PM PDT 24 |
| Finished | Aug 12 06:59:07 PM PDT 24 |
| Peak memory | 576360 kb |
| Host | smart-82e4e472-27b3-4528-874c-ef346ca495fa |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1621892801 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 89.xbar_stress_all _with_rand_reset.1621892801 |
| Directory | /workspace/89.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/89.xbar_stress_all_with_reset_error.3778169055 |
| Short name | T1959 |
| Test name | |
| Test status | |
| Simulation time | 108384587 ps |
| CPU time | 28.82 seconds |
| Started | Aug 12 06:58:18 PM PDT 24 |
| Finished | Aug 12 06:58:47 PM PDT 24 |
| Peak memory | 575680 kb |
| Host | smart-5003dc4d-be1e-4501-890b-e373466d7f19 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3778169055 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 89.xbar_stress_al l_with_reset_error.3778169055 |
| Directory | /workspace/89.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/89.xbar_unmapped_addr.3632968932 |
| Short name | T683 |
| Test name | |
| Test status | |
| Simulation time | 727714684 ps |
| CPU time | 32.6 seconds |
| Started | Aug 12 06:58:10 PM PDT 24 |
| Finished | Aug 12 06:58:43 PM PDT 24 |
| Peak memory | 575648 kb |
| Host | smart-ffa37730-a1a2-474e-b548-e20b4d4e3b49 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3632968932 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 89.xbar_unmapped_addr.3632968932 |
| Directory | /workspace/89.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/9.chip_csr_mem_rw_with_rand_reset.1924346779 |
| Short name | T407 |
| Test name | |
| Test status | |
| Simulation time | 6595910260 ps |
| CPU time | 510.29 seconds |
| Started | Aug 12 06:47:39 PM PDT 24 |
| Finished | Aug 12 06:56:09 PM PDT 24 |
| Peak memory | 639956 kb |
| Host | smart-51eee357-db02-4578-8584-36a4acb73319 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1924346779 -assert nopostproc + UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top .vdb -cm_log /dev/null -cm_name 9.chip_csr_mem_rw_with_rand_reset.1924346779 |
| Directory | /workspace/9.chip_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/9.chip_csr_rw.3138268953 |
| Short name | T2173 |
| Test name | |
| Test status | |
| Simulation time | 3580146728 ps |
| CPU time | 253.64 seconds |
| Started | Aug 12 06:47:51 PM PDT 24 |
| Finished | Aug 12 06:52:05 PM PDT 24 |
| Peak memory | 596868 kb |
| Host | smart-7ce59c10-5987-4e32-9051-7ec64366a8a9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3138268953 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.chip_csr_rw.3138268953 |
| Directory | /workspace/9.chip_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/9.chip_same_csr_outstanding.4136507749 |
| Short name | T1801 |
| Test name | |
| Test status | |
| Simulation time | 16436890374 ps |
| CPU time | 2026.7 seconds |
| Started | Aug 12 06:47:37 PM PDT 24 |
| Finished | Aug 12 07:21:23 PM PDT 24 |
| Peak memory | 592920 kb |
| Host | smart-31b37083-b144-4f3b-8b90-bf8771a5f97d |
| User | root |
| Command | /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +run_same_csr_outstanding +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4136507749 -assert nopostproc +UVM_TE STNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb - cm_log /dev/null -cm_name 9.chip_same_csr_outstanding.4136507749 |
| Directory | /workspace/9.chip_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/9.chip_tl_errors.2351625456 |
| Short name | T2931 |
| Test name | |
| Test status | |
| Simulation time | 3756587514 ps |
| CPU time | 225.82 seconds |
| Started | Aug 12 06:47:36 PM PDT 24 |
| Finished | Aug 12 06:51:22 PM PDT 24 |
| Peak memory | 603328 kb |
| Host | smart-3a81d52b-5c22-48b5-bcc9-6cc710d8bb92 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2351625456 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.chip_tl_errors.2351625456 |
| Directory | /workspace/9.chip_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/9.xbar_access_same_device.531749227 |
| Short name | T2638 |
| Test name | |
| Test status | |
| Simulation time | 1483577816 ps |
| CPU time | 59.24 seconds |
| Started | Aug 12 06:47:55 PM PDT 24 |
| Finished | Aug 12 06:48:55 PM PDT 24 |
| Peak memory | 575600 kb |
| Host | smart-8bd879e0-81ae-4015-8f8b-ece25904da6d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=531749227 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.xbar_access_same_device.531749227 |
| Directory | /workspace/9.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/9.xbar_error_and_unmapped_addr.3065899768 |
| Short name | T2431 |
| Test name | |
| Test status | |
| Simulation time | 85948653 ps |
| CPU time | 6.3 seconds |
| Started | Aug 12 06:47:51 PM PDT 24 |
| Finished | Aug 12 06:47:58 PM PDT 24 |
| Peak memory | 573668 kb |
| Host | smart-d8d911db-d0eb-45f1-9c66-8fd1d10fb57f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3065899768 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.xbar_error_and_unmapped_addr .3065899768 |
| Directory | /workspace/9.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/9.xbar_error_random.878617446 |
| Short name | T1510 |
| Test name | |
| Test status | |
| Simulation time | 321018492 ps |
| CPU time | 27.07 seconds |
| Started | Aug 12 06:47:40 PM PDT 24 |
| Finished | Aug 12 06:48:07 PM PDT 24 |
| Peak memory | 575680 kb |
| Host | smart-b386d7e0-560b-461d-99cc-7a20760ffc82 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=878617446 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.xbar_error_random.878617446 |
| Directory | /workspace/9.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/9.xbar_random.517851438 |
| Short name | T2116 |
| Test name | |
| Test status | |
| Simulation time | 1515547889 ps |
| CPU time | 50.1 seconds |
| Started | Aug 12 06:47:35 PM PDT 24 |
| Finished | Aug 12 06:48:25 PM PDT 24 |
| Peak memory | 575628 kb |
| Host | smart-e4c69f4d-d727-4643-aa8e-7ceec1f80bc0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=517851438 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.xbar_random.517851438 |
| Directory | /workspace/9.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/9.xbar_random_large_delays.3897155043 |
| Short name | T2099 |
| Test name | |
| Test status | |
| Simulation time | 38930247197 ps |
| CPU time | 412.97 seconds |
| Started | Aug 12 06:47:35 PM PDT 24 |
| Finished | Aug 12 06:54:28 PM PDT 24 |
| Peak memory | 575740 kb |
| Host | smart-38873084-d812-4a2d-bd33-a0181a8e453e |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3897155043 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.xbar_random_large_delays.3897155043 |
| Directory | /workspace/9.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/9.xbar_random_slow_rsp.221748707 |
| Short name | T1830 |
| Test name | |
| Test status | |
| Simulation time | 57278185797 ps |
| CPU time | 1022.77 seconds |
| Started | Aug 12 06:47:35 PM PDT 24 |
| Finished | Aug 12 07:04:38 PM PDT 24 |
| Peak memory | 575636 kb |
| Host | smart-8c6f0a7b-5112-4bc2-a63c-d6656da01b3a |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=221748707 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.xbar_random_slow_rsp.221748707 |
| Directory | /workspace/9.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/9.xbar_random_zero_delays.1773765264 |
| Short name | T2333 |
| Test name | |
| Test status | |
| Simulation time | 315888004 ps |
| CPU time | 28.44 seconds |
| Started | Aug 12 06:47:31 PM PDT 24 |
| Finished | Aug 12 06:48:00 PM PDT 24 |
| Peak memory | 575556 kb |
| Host | smart-d31a994e-bcbb-4141-ac73-0914bac5ebd4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1773765264 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.xbar_random_zero_dela ys.1773765264 |
| Directory | /workspace/9.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/9.xbar_same_source.2646352335 |
| Short name | T1469 |
| Test name | |
| Test status | |
| Simulation time | 60096128 ps |
| CPU time | 7.03 seconds |
| Started | Aug 12 06:47:35 PM PDT 24 |
| Finished | Aug 12 06:47:42 PM PDT 24 |
| Peak memory | 575636 kb |
| Host | smart-08d5b0e1-0aee-4b0e-aa07-1395565a4eb1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2646352335 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.xbar_same_source.2646352335 |
| Directory | /workspace/9.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/9.xbar_smoke.3200223251 |
| Short name | T1578 |
| Test name | |
| Test status | |
| Simulation time | 165868778 ps |
| CPU time | 7.35 seconds |
| Started | Aug 12 06:47:43 PM PDT 24 |
| Finished | Aug 12 06:47:50 PM PDT 24 |
| Peak memory | 573576 kb |
| Host | smart-63340078-9df9-4667-bdd8-8eb87c571993 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3200223251 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.xbar_smoke.3200223251 |
| Directory | /workspace/9.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/9.xbar_smoke_large_delays.4157585736 |
| Short name | T2859 |
| Test name | |
| Test status | |
| Simulation time | 7233914417 ps |
| CPU time | 72.82 seconds |
| Started | Aug 12 06:47:36 PM PDT 24 |
| Finished | Aug 12 06:48:49 PM PDT 24 |
| Peak memory | 574320 kb |
| Host | smart-cd9561aa-4117-495f-85cd-26476a084f81 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4157585736 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.xbar_smoke_large_delays.4157585736 |
| Directory | /workspace/9.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/9.xbar_smoke_slow_rsp.39106408 |
| Short name | T2253 |
| Test name | |
| Test status | |
| Simulation time | 4697925920 ps |
| CPU time | 79.62 seconds |
| Started | Aug 12 06:47:32 PM PDT 24 |
| Finished | Aug 12 06:48:52 PM PDT 24 |
| Peak memory | 574320 kb |
| Host | smart-78abb216-a5c0-4234-8281-8cbf7a843d60 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39106408 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.xbar_smoke_slow_rsp.39106408 |
| Directory | /workspace/9.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/9.xbar_smoke_zero_delays.1409152518 |
| Short name | T1763 |
| Test name | |
| Test status | |
| Simulation time | 44542919 ps |
| CPU time | 6.04 seconds |
| Started | Aug 12 06:47:30 PM PDT 24 |
| Finished | Aug 12 06:47:37 PM PDT 24 |
| Peak memory | 574264 kb |
| Host | smart-70c692eb-4a8d-4def-ae53-a4ce421c64ef |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1409152518 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.xbar_smoke_zero_delays .1409152518 |
| Directory | /workspace/9.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/9.xbar_stress_all.2549253568 |
| Short name | T1969 |
| Test name | |
| Test status | |
| Simulation time | 6440329207 ps |
| CPU time | 250.4 seconds |
| Started | Aug 12 06:47:43 PM PDT 24 |
| Finished | Aug 12 06:51:54 PM PDT 24 |
| Peak memory | 575756 kb |
| Host | smart-eb621e2e-9e49-4d46-bf38-a0da8d0a087c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2549253568 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.xbar_stress_all.2549253568 |
| Directory | /workspace/9.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/9.xbar_stress_all_with_error.364537079 |
| Short name | T1463 |
| Test name | |
| Test status | |
| Simulation time | 1845518004 ps |
| CPU time | 140.11 seconds |
| Started | Aug 12 06:47:51 PM PDT 24 |
| Finished | Aug 12 06:50:12 PM PDT 24 |
| Peak memory | 575900 kb |
| Host | smart-0e07fea4-20c4-4861-9bfa-a1f76b2a1f03 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=364537079 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.xbar_stress_all_with_error.364537079 |
| Directory | /workspace/9.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/9.xbar_stress_all_with_rand_reset.3375405871 |
| Short name | T2803 |
| Test name | |
| Test status | |
| Simulation time | 462010128 ps |
| CPU time | 183.94 seconds |
| Started | Aug 12 06:47:39 PM PDT 24 |
| Finished | Aug 12 06:50:44 PM PDT 24 |
| Peak memory | 575692 kb |
| Host | smart-bc398c50-0c96-4d89-9df9-9adf4198886e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3375405871 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.xbar_stress_all_ with_rand_reset.3375405871 |
| Directory | /workspace/9.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/9.xbar_stress_all_with_reset_error.154893973 |
| Short name | T2621 |
| Test name | |
| Test status | |
| Simulation time | 2278429971 ps |
| CPU time | 365.87 seconds |
| Started | Aug 12 06:47:40 PM PDT 24 |
| Finished | Aug 12 06:53:46 PM PDT 24 |
| Peak memory | 575744 kb |
| Host | smart-e185b6d3-75b4-4cc5-8703-41f6f86bd73d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=154893973 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.xbar_stress_all_ with_reset_error.154893973 |
| Directory | /workspace/9.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/9.xbar_unmapped_addr.832812231 |
| Short name | T595 |
| Test name | |
| Test status | |
| Simulation time | 164666659 ps |
| CPU time | 20.42 seconds |
| Started | Aug 12 06:47:33 PM PDT 24 |
| Finished | Aug 12 06:47:54 PM PDT 24 |
| Peak memory | 575664 kb |
| Host | smart-097f1f80-df04-4658-80b2-3f28f798bbc5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=832812231 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.xbar_unmapped_addr.832812231 |
| Directory | /workspace/9.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/90.xbar_access_same_device.1007384343 |
| Short name | T2363 |
| Test name | |
| Test status | |
| Simulation time | 615522908 ps |
| CPU time | 53.48 seconds |
| Started | Aug 12 06:58:19 PM PDT 24 |
| Finished | Aug 12 06:59:13 PM PDT 24 |
| Peak memory | 575544 kb |
| Host | smart-d78e1d0d-7f78-4293-a62f-0c0db13bb85d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1007384343 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 90.xbar_access_same_device .1007384343 |
| Directory | /workspace/90.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/90.xbar_access_same_device_slow_rsp.717464829 |
| Short name | T492 |
| Test name | |
| Test status | |
| Simulation time | 133618574564 ps |
| CPU time | 2559.96 seconds |
| Started | Aug 12 06:58:24 PM PDT 24 |
| Finished | Aug 12 07:41:05 PM PDT 24 |
| Peak memory | 575832 kb |
| Host | smart-b7ba668b-7027-4bf6-93fd-f59e87ecbd01 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=717464829 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 90.xbar_access_same_d evice_slow_rsp.717464829 |
| Directory | /workspace/90.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/90.xbar_error_and_unmapped_addr.3049173930 |
| Short name | T1582 |
| Test name | |
| Test status | |
| Simulation time | 513623755 ps |
| CPU time | 22.97 seconds |
| Started | Aug 12 06:58:16 PM PDT 24 |
| Finished | Aug 12 06:58:39 PM PDT 24 |
| Peak memory | 575744 kb |
| Host | smart-d9a422d8-0aa7-4208-a92b-1571814b6cc8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3049173930 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 90.xbar_error_and_unmapped_add r.3049173930 |
| Directory | /workspace/90.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/90.xbar_error_random.1503814674 |
| Short name | T2821 |
| Test name | |
| Test status | |
| Simulation time | 643719431 ps |
| CPU time | 21.82 seconds |
| Started | Aug 12 06:58:18 PM PDT 24 |
| Finished | Aug 12 06:58:40 PM PDT 24 |
| Peak memory | 575688 kb |
| Host | smart-04e0d4a2-69e2-4e6f-9d9c-f3e88df0ede1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1503814674 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 90.xbar_error_random.1503814674 |
| Directory | /workspace/90.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/90.xbar_random.3378675874 |
| Short name | T2791 |
| Test name | |
| Test status | |
| Simulation time | 349934026 ps |
| CPU time | 29.09 seconds |
| Started | Aug 12 06:58:18 PM PDT 24 |
| Finished | Aug 12 06:58:47 PM PDT 24 |
| Peak memory | 575552 kb |
| Host | smart-3be44bac-f5f6-4691-956a-cac5d3539f1b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3378675874 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 90.xbar_random.3378675874 |
| Directory | /workspace/90.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/90.xbar_random_large_delays.1401885739 |
| Short name | T653 |
| Test name | |
| Test status | |
| Simulation time | 55116716901 ps |
| CPU time | 609.42 seconds |
| Started | Aug 12 06:58:16 PM PDT 24 |
| Finished | Aug 12 07:08:26 PM PDT 24 |
| Peak memory | 575808 kb |
| Host | smart-f7a5dedb-55e6-4bb6-b412-7163707cf5f8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1401885739 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 90.xbar_random_large_delays.1401885739 |
| Directory | /workspace/90.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/90.xbar_random_slow_rsp.3908358332 |
| Short name | T2433 |
| Test name | |
| Test status | |
| Simulation time | 11094690008 ps |
| CPU time | 194.44 seconds |
| Started | Aug 12 06:58:24 PM PDT 24 |
| Finished | Aug 12 07:01:39 PM PDT 24 |
| Peak memory | 575716 kb |
| Host | smart-727e2b40-c180-457c-8aa8-6f470595caaf |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3908358332 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 90.xbar_random_slow_rsp.3908358332 |
| Directory | /workspace/90.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/90.xbar_random_zero_delays.759914037 |
| Short name | T534 |
| Test name | |
| Test status | |
| Simulation time | 441175875 ps |
| CPU time | 34.66 seconds |
| Started | Aug 12 06:58:24 PM PDT 24 |
| Finished | Aug 12 06:58:59 PM PDT 24 |
| Peak memory | 575644 kb |
| Host | smart-05fcfbff-cbee-4f66-a489-86b198373c25 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=759914037 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 90.xbar_random_zero_dela ys.759914037 |
| Directory | /workspace/90.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/90.xbar_same_source.3015304752 |
| Short name | T2237 |
| Test name | |
| Test status | |
| Simulation time | 123143301 ps |
| CPU time | 7.07 seconds |
| Started | Aug 12 06:58:17 PM PDT 24 |
| Finished | Aug 12 06:58:24 PM PDT 24 |
| Peak memory | 573496 kb |
| Host | smart-9500d9cb-eeb5-4d05-b0bb-0779bcac7958 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3015304752 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 90.xbar_same_source.3015304752 |
| Directory | /workspace/90.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/90.xbar_smoke.1938916312 |
| Short name | T2340 |
| Test name | |
| Test status | |
| Simulation time | 202248986 ps |
| CPU time | 8.86 seconds |
| Started | Aug 12 06:58:18 PM PDT 24 |
| Finished | Aug 12 06:58:27 PM PDT 24 |
| Peak memory | 573620 kb |
| Host | smart-50d09ee7-d960-4ed5-aa83-24653912969f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1938916312 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 90.xbar_smoke.1938916312 |
| Directory | /workspace/90.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/90.xbar_smoke_large_delays.1707473081 |
| Short name | T2095 |
| Test name | |
| Test status | |
| Simulation time | 9548876335 ps |
| CPU time | 98.03 seconds |
| Started | Aug 12 06:58:18 PM PDT 24 |
| Finished | Aug 12 06:59:56 PM PDT 24 |
| Peak memory | 573700 kb |
| Host | smart-105cee76-853c-4031-ab3a-c266053ddf77 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1707473081 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 90.xbar_smoke_large_delays.1707473081 |
| Directory | /workspace/90.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/90.xbar_smoke_slow_rsp.3282181702 |
| Short name | T2401 |
| Test name | |
| Test status | |
| Simulation time | 5230923164 ps |
| CPU time | 86.02 seconds |
| Started | Aug 12 06:58:18 PM PDT 24 |
| Finished | Aug 12 06:59:44 PM PDT 24 |
| Peak memory | 574324 kb |
| Host | smart-dff52b57-f8f3-4b43-8c86-2f5efd2e6761 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3282181702 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 90.xbar_smoke_slow_rsp.3282181702 |
| Directory | /workspace/90.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/90.xbar_smoke_zero_delays.2684059905 |
| Short name | T2493 |
| Test name | |
| Test status | |
| Simulation time | 45445499 ps |
| CPU time | 6.19 seconds |
| Started | Aug 12 06:58:17 PM PDT 24 |
| Finished | Aug 12 06:58:24 PM PDT 24 |
| Peak memory | 573600 kb |
| Host | smart-5dcb1f49-80b5-4e5c-a4bc-e93a2cdc9458 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2684059905 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 90.xbar_smoke_zero_delay s.2684059905 |
| Directory | /workspace/90.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/90.xbar_stress_all.2255545159 |
| Short name | T2636 |
| Test name | |
| Test status | |
| Simulation time | 589898775 ps |
| CPU time | 55.98 seconds |
| Started | Aug 12 06:58:19 PM PDT 24 |
| Finished | Aug 12 06:59:15 PM PDT 24 |
| Peak memory | 575788 kb |
| Host | smart-e7ff5658-e5fe-4c94-ace2-93b1e175f9d6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2255545159 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 90.xbar_stress_all.2255545159 |
| Directory | /workspace/90.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/90.xbar_stress_all_with_rand_reset.1415588414 |
| Short name | T958 |
| Test name | |
| Test status | |
| Simulation time | 2776363604 ps |
| CPU time | 324.98 seconds |
| Started | Aug 12 06:58:24 PM PDT 24 |
| Finished | Aug 12 07:03:50 PM PDT 24 |
| Peak memory | 575776 kb |
| Host | smart-373a8710-ceb6-4e02-b379-a8a40665ada5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1415588414 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 90.xbar_stress_all _with_rand_reset.1415588414 |
| Directory | /workspace/90.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/90.xbar_stress_all_with_reset_error.2750029814 |
| Short name | T1832 |
| Test name | |
| Test status | |
| Simulation time | 2422935951 ps |
| CPU time | 323.75 seconds |
| Started | Aug 12 06:58:25 PM PDT 24 |
| Finished | Aug 12 07:03:48 PM PDT 24 |
| Peak memory | 576520 kb |
| Host | smart-9f51a40c-6f3b-4829-afb8-b9b479c9318b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2750029814 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 90.xbar_stress_al l_with_reset_error.2750029814 |
| Directory | /workspace/90.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/90.xbar_unmapped_addr.3733726479 |
| Short name | T524 |
| Test name | |
| Test status | |
| Simulation time | 204132743 ps |
| CPU time | 23.65 seconds |
| Started | Aug 12 06:58:17 PM PDT 24 |
| Finished | Aug 12 06:58:41 PM PDT 24 |
| Peak memory | 575776 kb |
| Host | smart-79a07bf4-f6f4-478c-b71c-c9b898234c6a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3733726479 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 90.xbar_unmapped_addr.3733726479 |
| Directory | /workspace/90.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/91.xbar_access_same_device.3719935879 |
| Short name | T2080 |
| Test name | |
| Test status | |
| Simulation time | 735772146 ps |
| CPU time | 54.21 seconds |
| Started | Aug 12 06:58:28 PM PDT 24 |
| Finished | Aug 12 06:59:22 PM PDT 24 |
| Peak memory | 575772 kb |
| Host | smart-455a4f7e-a6dc-49ae-a10d-96de439e0bd1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3719935879 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 91.xbar_access_same_device .3719935879 |
| Directory | /workspace/91.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/91.xbar_access_same_device_slow_rsp.1697499406 |
| Short name | T2657 |
| Test name | |
| Test status | |
| Simulation time | 136254553596 ps |
| CPU time | 2578.69 seconds |
| Started | Aug 12 06:58:26 PM PDT 24 |
| Finished | Aug 12 07:41:25 PM PDT 24 |
| Peak memory | 575696 kb |
| Host | smart-474c9eac-362c-4a83-a4c4-017c731a51ef |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1697499406 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 91.xbar_access_same_ device_slow_rsp.1697499406 |
| Directory | /workspace/91.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/91.xbar_error_and_unmapped_addr.3458934498 |
| Short name | T2043 |
| Test name | |
| Test status | |
| Simulation time | 131563026 ps |
| CPU time | 8.34 seconds |
| Started | Aug 12 06:58:28 PM PDT 24 |
| Finished | Aug 12 06:58:37 PM PDT 24 |
| Peak memory | 573664 kb |
| Host | smart-dd5e14ae-9821-415b-a832-d42536cd6e32 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3458934498 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 91.xbar_error_and_unmapped_add r.3458934498 |
| Directory | /workspace/91.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/91.xbar_error_random.2588029031 |
| Short name | T2039 |
| Test name | |
| Test status | |
| Simulation time | 2311675204 ps |
| CPU time | 79.87 seconds |
| Started | Aug 12 06:58:26 PM PDT 24 |
| Finished | Aug 12 06:59:46 PM PDT 24 |
| Peak memory | 575780 kb |
| Host | smart-0fa5f8ba-c3d1-4317-8767-d514a0cc9aaa |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2588029031 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 91.xbar_error_random.2588029031 |
| Directory | /workspace/91.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/91.xbar_random.438893980 |
| Short name | T2687 |
| Test name | |
| Test status | |
| Simulation time | 300861655 ps |
| CPU time | 26.73 seconds |
| Started | Aug 12 06:58:26 PM PDT 24 |
| Finished | Aug 12 06:58:53 PM PDT 24 |
| Peak memory | 575528 kb |
| Host | smart-286675b5-5784-4f7f-ab98-2399863eaeb0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=438893980 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 91.xbar_random.438893980 |
| Directory | /workspace/91.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/91.xbar_random_large_delays.1088851911 |
| Short name | T2490 |
| Test name | |
| Test status | |
| Simulation time | 22023833485 ps |
| CPU time | 238.24 seconds |
| Started | Aug 12 06:58:25 PM PDT 24 |
| Finished | Aug 12 07:02:24 PM PDT 24 |
| Peak memory | 575728 kb |
| Host | smart-f5fba0cb-3b2a-4dfd-8ae5-0420a1db3091 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1088851911 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 91.xbar_random_large_delays.1088851911 |
| Directory | /workspace/91.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/91.xbar_random_slow_rsp.4167649407 |
| Short name | T499 |
| Test name | |
| Test status | |
| Simulation time | 59447968964 ps |
| CPU time | 1093.18 seconds |
| Started | Aug 12 06:58:26 PM PDT 24 |
| Finished | Aug 12 07:16:40 PM PDT 24 |
| Peak memory | 575676 kb |
| Host | smart-9ebdca08-decb-47f7-aec4-4927242725b7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4167649407 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 91.xbar_random_slow_rsp.4167649407 |
| Directory | /workspace/91.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/91.xbar_random_zero_delays.425297402 |
| Short name | T2629 |
| Test name | |
| Test status | |
| Simulation time | 54677594 ps |
| CPU time | 8.84 seconds |
| Started | Aug 12 06:58:26 PM PDT 24 |
| Finished | Aug 12 06:58:35 PM PDT 24 |
| Peak memory | 575664 kb |
| Host | smart-fffc2ab0-40cf-48c6-8e29-e97e316ff844 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=425297402 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 91.xbar_random_zero_dela ys.425297402 |
| Directory | /workspace/91.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/91.xbar_same_source.106885009 |
| Short name | T2247 |
| Test name | |
| Test status | |
| Simulation time | 1776100844 ps |
| CPU time | 54.05 seconds |
| Started | Aug 12 06:58:26 PM PDT 24 |
| Finished | Aug 12 06:59:20 PM PDT 24 |
| Peak memory | 575648 kb |
| Host | smart-cdcf7718-2da8-4f33-a395-c11eb210321f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=106885009 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 91.xbar_same_source.106885009 |
| Directory | /workspace/91.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/91.xbar_smoke.388326728 |
| Short name | T1846 |
| Test name | |
| Test status | |
| Simulation time | 215957512 ps |
| CPU time | 8.54 seconds |
| Started | Aug 12 06:58:24 PM PDT 24 |
| Finished | Aug 12 06:58:33 PM PDT 24 |
| Peak memory | 573604 kb |
| Host | smart-3ff32932-50b6-4dd9-bdc5-f2c56e050ad7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=388326728 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 91.xbar_smoke.388326728 |
| Directory | /workspace/91.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/91.xbar_smoke_large_delays.485111706 |
| Short name | T531 |
| Test name | |
| Test status | |
| Simulation time | 8164494459 ps |
| CPU time | 85.55 seconds |
| Started | Aug 12 06:58:26 PM PDT 24 |
| Finished | Aug 12 06:59:51 PM PDT 24 |
| Peak memory | 573620 kb |
| Host | smart-e5568b78-a7b0-4310-aa34-63a83c873501 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=485111706 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 91.xbar_smoke_large_delays.485111706 |
| Directory | /workspace/91.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/91.xbar_smoke_slow_rsp.1470271870 |
| Short name | T2909 |
| Test name | |
| Test status | |
| Simulation time | 3422706446 ps |
| CPU time | 55.36 seconds |
| Started | Aug 12 06:58:27 PM PDT 24 |
| Finished | Aug 12 06:59:23 PM PDT 24 |
| Peak memory | 573648 kb |
| Host | smart-5e73f71d-c173-41f5-989e-8448a5d1a489 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1470271870 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 91.xbar_smoke_slow_rsp.1470271870 |
| Directory | /workspace/91.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/91.xbar_smoke_zero_delays.2188917055 |
| Short name | T1793 |
| Test name | |
| Test status | |
| Simulation time | 47915395 ps |
| CPU time | 6.46 seconds |
| Started | Aug 12 06:58:26 PM PDT 24 |
| Finished | Aug 12 06:58:33 PM PDT 24 |
| Peak memory | 573540 kb |
| Host | smart-79ac728b-df27-4f1f-991f-3c80ab6300a2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2188917055 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 91.xbar_smoke_zero_delay s.2188917055 |
| Directory | /workspace/91.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/91.xbar_stress_all.3460539997 |
| Short name | T586 |
| Test name | |
| Test status | |
| Simulation time | 2502840276 ps |
| CPU time | 199.39 seconds |
| Started | Aug 12 06:58:27 PM PDT 24 |
| Finished | Aug 12 07:01:46 PM PDT 24 |
| Peak memory | 575804 kb |
| Host | smart-ac195bd6-f130-43de-8353-028ad15e2796 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3460539997 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 91.xbar_stress_all.3460539997 |
| Directory | /workspace/91.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/91.xbar_stress_all_with_error.1440793049 |
| Short name | T2488 |
| Test name | |
| Test status | |
| Simulation time | 12236715244 ps |
| CPU time | 448.44 seconds |
| Started | Aug 12 06:58:25 PM PDT 24 |
| Finished | Aug 12 07:05:54 PM PDT 24 |
| Peak memory | 576592 kb |
| Host | smart-2f014e2b-55a7-467c-8da3-10ff7983157e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1440793049 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 91.xbar_stress_all_with_error.1440793049 |
| Directory | /workspace/91.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/91.xbar_stress_all_with_rand_reset.705407709 |
| Short name | T2895 |
| Test name | |
| Test status | |
| Simulation time | 115893702 ps |
| CPU time | 83.78 seconds |
| Started | Aug 12 06:58:25 PM PDT 24 |
| Finished | Aug 12 06:59:49 PM PDT 24 |
| Peak memory | 576320 kb |
| Host | smart-35506e6d-e509-4b40-a967-7c5afac31f4b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=705407709 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_res et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 91.xbar_stress_all_ with_rand_reset.705407709 |
| Directory | /workspace/91.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/91.xbar_stress_all_with_reset_error.3586831269 |
| Short name | T2477 |
| Test name | |
| Test status | |
| Simulation time | 810462369 ps |
| CPU time | 147.36 seconds |
| Started | Aug 12 06:58:27 PM PDT 24 |
| Finished | Aug 12 07:00:54 PM PDT 24 |
| Peak memory | 575668 kb |
| Host | smart-75b3dd94-48bb-49a9-a7cd-6d6254938c77 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3586831269 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 91.xbar_stress_al l_with_reset_error.3586831269 |
| Directory | /workspace/91.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/91.xbar_unmapped_addr.785303570 |
| Short name | T1945 |
| Test name | |
| Test status | |
| Simulation time | 605366037 ps |
| CPU time | 24.05 seconds |
| Started | Aug 12 06:58:26 PM PDT 24 |
| Finished | Aug 12 06:58:50 PM PDT 24 |
| Peak memory | 575772 kb |
| Host | smart-c6647296-9c08-413a-b53f-42e076beddd9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=785303570 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 91.xbar_unmapped_addr.785303570 |
| Directory | /workspace/91.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/92.xbar_access_same_device.2588556889 |
| Short name | T2752 |
| Test name | |
| Test status | |
| Simulation time | 82029879 ps |
| CPU time | 8.33 seconds |
| Started | Aug 12 06:58:38 PM PDT 24 |
| Finished | Aug 12 06:58:47 PM PDT 24 |
| Peak memory | 575660 kb |
| Host | smart-9c4c60f2-4da2-419a-a771-ef0dec5cb530 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2588556889 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 92.xbar_access_same_device .2588556889 |
| Directory | /workspace/92.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/92.xbar_access_same_device_slow_rsp.4246037768 |
| Short name | T2177 |
| Test name | |
| Test status | |
| Simulation time | 47523419469 ps |
| CPU time | 908.24 seconds |
| Started | Aug 12 06:58:40 PM PDT 24 |
| Finished | Aug 12 07:13:49 PM PDT 24 |
| Peak memory | 575632 kb |
| Host | smart-39cd53f9-25be-4449-b019-23718af40bd0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4246037768 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 92.xbar_access_same_ device_slow_rsp.4246037768 |
| Directory | /workspace/92.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/92.xbar_error_and_unmapped_addr.1440418249 |
| Short name | T1683 |
| Test name | |
| Test status | |
| Simulation time | 555839742 ps |
| CPU time | 21.8 seconds |
| Started | Aug 12 06:58:40 PM PDT 24 |
| Finished | Aug 12 06:59:02 PM PDT 24 |
| Peak memory | 575540 kb |
| Host | smart-0c0d35aa-d573-4a82-ada7-9b0af4a7167d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1440418249 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 92.xbar_error_and_unmapped_add r.1440418249 |
| Directory | /workspace/92.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/92.xbar_error_random.402465200 |
| Short name | T2230 |
| Test name | |
| Test status | |
| Simulation time | 447082901 ps |
| CPU time | 33.51 seconds |
| Started | Aug 12 06:58:38 PM PDT 24 |
| Finished | Aug 12 06:59:12 PM PDT 24 |
| Peak memory | 575708 kb |
| Host | smart-6a1f39c1-2c81-40d6-9341-32cbe092388c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=402465200 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 92.xbar_error_random.402465200 |
| Directory | /workspace/92.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/92.xbar_random.2681698033 |
| Short name | T1756 |
| Test name | |
| Test status | |
| Simulation time | 166223940 ps |
| CPU time | 9.33 seconds |
| Started | Aug 12 06:58:39 PM PDT 24 |
| Finished | Aug 12 06:58:49 PM PDT 24 |
| Peak memory | 574244 kb |
| Host | smart-435a2460-a4a4-412a-8ffb-1062f8fa7236 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2681698033 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 92.xbar_random.2681698033 |
| Directory | /workspace/92.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/92.xbar_random_large_delays.4293792244 |
| Short name | T2290 |
| Test name | |
| Test status | |
| Simulation time | 76407676753 ps |
| CPU time | 783.17 seconds |
| Started | Aug 12 06:58:42 PM PDT 24 |
| Finished | Aug 12 07:11:45 PM PDT 24 |
| Peak memory | 575688 kb |
| Host | smart-c9055ed3-4eeb-4ca2-8d32-7847d77fcb47 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4293792244 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 92.xbar_random_large_delays.4293792244 |
| Directory | /workspace/92.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/92.xbar_random_slow_rsp.2073616926 |
| Short name | T697 |
| Test name | |
| Test status | |
| Simulation time | 30261160895 ps |
| CPU time | 567.88 seconds |
| Started | Aug 12 06:58:39 PM PDT 24 |
| Finished | Aug 12 07:08:07 PM PDT 24 |
| Peak memory | 575640 kb |
| Host | smart-57266e3f-8d56-4a4d-98ae-709d0ea240c7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2073616926 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 92.xbar_random_slow_rsp.2073616926 |
| Directory | /workspace/92.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/92.xbar_random_zero_delays.1390120042 |
| Short name | T2722 |
| Test name | |
| Test status | |
| Simulation time | 397459484 ps |
| CPU time | 32.33 seconds |
| Started | Aug 12 06:58:38 PM PDT 24 |
| Finished | Aug 12 06:59:11 PM PDT 24 |
| Peak memory | 575680 kb |
| Host | smart-73d25341-1a2a-4ada-b1a4-22c5aaed9917 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1390120042 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 92.xbar_random_zero_del ays.1390120042 |
| Directory | /workspace/92.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/92.xbar_same_source.997404948 |
| Short name | T2193 |
| Test name | |
| Test status | |
| Simulation time | 1222489695 ps |
| CPU time | 37.58 seconds |
| Started | Aug 12 06:58:38 PM PDT 24 |
| Finished | Aug 12 06:59:16 PM PDT 24 |
| Peak memory | 575676 kb |
| Host | smart-d6966120-ac8a-4c70-a19b-aeac184ce261 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=997404948 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 92.xbar_same_source.997404948 |
| Directory | /workspace/92.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/92.xbar_smoke.1245977079 |
| Short name | T2337 |
| Test name | |
| Test status | |
| Simulation time | 234870316 ps |
| CPU time | 10.08 seconds |
| Started | Aug 12 06:58:25 PM PDT 24 |
| Finished | Aug 12 06:58:35 PM PDT 24 |
| Peak memory | 573500 kb |
| Host | smart-7db1037d-463b-4003-94ee-e5aae9b72d83 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1245977079 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 92.xbar_smoke.1245977079 |
| Directory | /workspace/92.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/92.xbar_smoke_large_delays.3657856785 |
| Short name | T2790 |
| Test name | |
| Test status | |
| Simulation time | 8606060319 ps |
| CPU time | 88.03 seconds |
| Started | Aug 12 06:58:27 PM PDT 24 |
| Finished | Aug 12 06:59:55 PM PDT 24 |
| Peak memory | 573700 kb |
| Host | smart-3acc1811-f993-450b-9b10-b39c9a4cec08 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3657856785 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 92.xbar_smoke_large_delays.3657856785 |
| Directory | /workspace/92.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/92.xbar_smoke_slow_rsp.492059962 |
| Short name | T2734 |
| Test name | |
| Test status | |
| Simulation time | 5097984665 ps |
| CPU time | 86.44 seconds |
| Started | Aug 12 06:58:40 PM PDT 24 |
| Finished | Aug 12 07:00:07 PM PDT 24 |
| Peak memory | 573592 kb |
| Host | smart-afbdf175-c9c1-439b-b5dd-9c9ddcd4d172 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=492059962 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 92.xbar_smoke_slow_rsp.492059962 |
| Directory | /workspace/92.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/92.xbar_smoke_zero_delays.2367188715 |
| Short name | T2647 |
| Test name | |
| Test status | |
| Simulation time | 45793677 ps |
| CPU time | 5.92 seconds |
| Started | Aug 12 06:58:25 PM PDT 24 |
| Finished | Aug 12 06:58:31 PM PDT 24 |
| Peak memory | 574292 kb |
| Host | smart-69abf586-a96a-41e2-aecb-344c73ce1f7d |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2367188715 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 92.xbar_smoke_zero_delay s.2367188715 |
| Directory | /workspace/92.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/92.xbar_stress_all.1544773527 |
| Short name | T522 |
| Test name | |
| Test status | |
| Simulation time | 184995403 ps |
| CPU time | 16.29 seconds |
| Started | Aug 12 06:58:38 PM PDT 24 |
| Finished | Aug 12 06:58:55 PM PDT 24 |
| Peak memory | 575728 kb |
| Host | smart-c61f6b47-eb71-448b-8f1f-000f848d6912 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1544773527 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 92.xbar_stress_all.1544773527 |
| Directory | /workspace/92.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/92.xbar_stress_all_with_error.2360229430 |
| Short name | T557 |
| Test name | |
| Test status | |
| Simulation time | 2700953490 ps |
| CPU time | 218.38 seconds |
| Started | Aug 12 06:58:40 PM PDT 24 |
| Finished | Aug 12 07:02:19 PM PDT 24 |
| Peak memory | 576620 kb |
| Host | smart-18c0fc4b-c95c-4846-be44-2c530d93746b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2360229430 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 92.xbar_stress_all_with_error.2360229430 |
| Directory | /workspace/92.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/92.xbar_stress_all_with_rand_reset.2522410935 |
| Short name | T2529 |
| Test name | |
| Test status | |
| Simulation time | 4329808184 ps |
| CPU time | 242.49 seconds |
| Started | Aug 12 06:58:38 PM PDT 24 |
| Finished | Aug 12 07:02:40 PM PDT 24 |
| Peak memory | 575768 kb |
| Host | smart-d99d8d8b-8421-4551-9820-bd693253b768 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2522410935 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 92.xbar_stress_all _with_rand_reset.2522410935 |
| Directory | /workspace/92.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/92.xbar_stress_all_with_reset_error.1843601942 |
| Short name | T1994 |
| Test name | |
| Test status | |
| Simulation time | 4801485734 ps |
| CPU time | 271.03 seconds |
| Started | Aug 12 06:58:40 PM PDT 24 |
| Finished | Aug 12 07:03:12 PM PDT 24 |
| Peak memory | 575728 kb |
| Host | smart-59594319-dac3-4a12-aaf7-0904b71d1405 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1843601942 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 92.xbar_stress_al l_with_reset_error.1843601942 |
| Directory | /workspace/92.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/92.xbar_unmapped_addr.2944393448 |
| Short name | T1869 |
| Test name | |
| Test status | |
| Simulation time | 64734319 ps |
| CPU time | 10.73 seconds |
| Started | Aug 12 06:58:38 PM PDT 24 |
| Finished | Aug 12 06:58:48 PM PDT 24 |
| Peak memory | 575712 kb |
| Host | smart-3ec704b0-c029-4e5f-8cd1-238781547867 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2944393448 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 92.xbar_unmapped_addr.2944393448 |
| Directory | /workspace/92.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/93.xbar_access_same_device.3890697036 |
| Short name | T2474 |
| Test name | |
| Test status | |
| Simulation time | 1765271525 ps |
| CPU time | 62.08 seconds |
| Started | Aug 12 06:59:01 PM PDT 24 |
| Finished | Aug 12 07:00:03 PM PDT 24 |
| Peak memory | 575684 kb |
| Host | smart-4677024d-54ee-42e9-bedf-e6f728cbb450 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3890697036 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 93.xbar_access_same_device .3890697036 |
| Directory | /workspace/93.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/93.xbar_error_and_unmapped_addr.3465254871 |
| Short name | T1515 |
| Test name | |
| Test status | |
| Simulation time | 67096258 ps |
| CPU time | 9.63 seconds |
| Started | Aug 12 06:58:55 PM PDT 24 |
| Finished | Aug 12 06:59:05 PM PDT 24 |
| Peak memory | 575724 kb |
| Host | smart-4433ca6c-b588-41b7-92a2-50ff3df34b21 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3465254871 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 93.xbar_error_and_unmapped_add r.3465254871 |
| Directory | /workspace/93.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/93.xbar_error_random.2133803879 |
| Short name | T1490 |
| Test name | |
| Test status | |
| Simulation time | 199263729 ps |
| CPU time | 19.18 seconds |
| Started | Aug 12 06:58:58 PM PDT 24 |
| Finished | Aug 12 06:59:17 PM PDT 24 |
| Peak memory | 575780 kb |
| Host | smart-7819d422-c242-4f7d-9d4e-1ef6e0f29fd7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2133803879 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 93.xbar_error_random.2133803879 |
| Directory | /workspace/93.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/93.xbar_random.2942562814 |
| Short name | T2928 |
| Test name | |
| Test status | |
| Simulation time | 632546027 ps |
| CPU time | 26.49 seconds |
| Started | Aug 12 06:58:38 PM PDT 24 |
| Finished | Aug 12 06:59:05 PM PDT 24 |
| Peak memory | 575560 kb |
| Host | smart-7b8d9868-c21c-4f33-b8e7-7a8473048672 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2942562814 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 93.xbar_random.2942562814 |
| Directory | /workspace/93.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/93.xbar_random_large_delays.3064902550 |
| Short name | T2660 |
| Test name | |
| Test status | |
| Simulation time | 25393862078 ps |
| CPU time | 294.72 seconds |
| Started | Aug 12 06:59:02 PM PDT 24 |
| Finished | Aug 12 07:03:57 PM PDT 24 |
| Peak memory | 575764 kb |
| Host | smart-1c379034-75c7-468c-b1cd-e933bf0ae073 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3064902550 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 93.xbar_random_large_delays.3064902550 |
| Directory | /workspace/93.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/93.xbar_random_slow_rsp.1323829504 |
| Short name | T631 |
| Test name | |
| Test status | |
| Simulation time | 18185579540 ps |
| CPU time | 281.05 seconds |
| Started | Aug 12 06:58:56 PM PDT 24 |
| Finished | Aug 12 07:03:37 PM PDT 24 |
| Peak memory | 575688 kb |
| Host | smart-2f76b3f8-af52-4850-af38-466216ec8006 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1323829504 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 93.xbar_random_slow_rsp.1323829504 |
| Directory | /workspace/93.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/93.xbar_random_zero_delays.1005493582 |
| Short name | T2087 |
| Test name | |
| Test status | |
| Simulation time | 446047128 ps |
| CPU time | 42.57 seconds |
| Started | Aug 12 06:58:58 PM PDT 24 |
| Finished | Aug 12 06:59:41 PM PDT 24 |
| Peak memory | 575676 kb |
| Host | smart-aa91d16f-c607-4a47-b70c-d2646d61a877 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1005493582 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 93.xbar_random_zero_del ays.1005493582 |
| Directory | /workspace/93.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/93.xbar_same_source.4279219644 |
| Short name | T2805 |
| Test name | |
| Test status | |
| Simulation time | 2016221502 ps |
| CPU time | 58.18 seconds |
| Started | Aug 12 06:58:56 PM PDT 24 |
| Finished | Aug 12 06:59:54 PM PDT 24 |
| Peak memory | 575600 kb |
| Host | smart-045cf569-e14c-4bcd-b656-9c23a332f504 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4279219644 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 93.xbar_same_source.4279219644 |
| Directory | /workspace/93.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/93.xbar_smoke.3510830860 |
| Short name | T2380 |
| Test name | |
| Test status | |
| Simulation time | 245714716 ps |
| CPU time | 10.13 seconds |
| Started | Aug 12 06:58:39 PM PDT 24 |
| Finished | Aug 12 06:58:50 PM PDT 24 |
| Peak memory | 573592 kb |
| Host | smart-da4c5741-dc6a-4499-a102-f76bba19eb1c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3510830860 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 93.xbar_smoke.3510830860 |
| Directory | /workspace/93.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/93.xbar_smoke_large_delays.1466192570 |
| Short name | T2303 |
| Test name | |
| Test status | |
| Simulation time | 7499111769 ps |
| CPU time | 80.26 seconds |
| Started | Aug 12 06:58:37 PM PDT 24 |
| Finished | Aug 12 06:59:58 PM PDT 24 |
| Peak memory | 573604 kb |
| Host | smart-e4107fc9-1af1-4c77-8b74-7787c990d0e6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1466192570 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 93.xbar_smoke_large_delays.1466192570 |
| Directory | /workspace/93.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/93.xbar_smoke_slow_rsp.3402603995 |
| Short name | T2113 |
| Test name | |
| Test status | |
| Simulation time | 6278961152 ps |
| CPU time | 105.74 seconds |
| Started | Aug 12 06:58:37 PM PDT 24 |
| Finished | Aug 12 07:00:23 PM PDT 24 |
| Peak memory | 574392 kb |
| Host | smart-d1b4d481-2bd5-4dc6-af37-b7d3ed4b7d76 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3402603995 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 93.xbar_smoke_slow_rsp.3402603995 |
| Directory | /workspace/93.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/93.xbar_smoke_zero_delays.366602624 |
| Short name | T1600 |
| Test name | |
| Test status | |
| Simulation time | 40687255 ps |
| CPU time | 5.67 seconds |
| Started | Aug 12 06:58:41 PM PDT 24 |
| Finished | Aug 12 06:58:46 PM PDT 24 |
| Peak memory | 573592 kb |
| Host | smart-75eaba25-086b-4b9b-b15a-a2edd49592b7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=366602624 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 93.xbar_smoke_zero_delays .366602624 |
| Directory | /workspace/93.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/93.xbar_stress_all.3165442889 |
| Short name | T606 |
| Test name | |
| Test status | |
| Simulation time | 7430606822 ps |
| CPU time | 293.9 seconds |
| Started | Aug 12 06:58:56 PM PDT 24 |
| Finished | Aug 12 07:03:50 PM PDT 24 |
| Peak memory | 575808 kb |
| Host | smart-c4a74646-be3d-40d1-a5a7-cd963b868177 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3165442889 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 93.xbar_stress_all.3165442889 |
| Directory | /workspace/93.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/93.xbar_stress_all_with_error.3186356618 |
| Short name | T1944 |
| Test name | |
| Test status | |
| Simulation time | 692781717 ps |
| CPU time | 49.98 seconds |
| Started | Aug 12 06:59:04 PM PDT 24 |
| Finished | Aug 12 06:59:54 PM PDT 24 |
| Peak memory | 575748 kb |
| Host | smart-9f918f7a-e5e8-41ca-a8ee-93a5d2bd2201 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3186356618 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 93.xbar_stress_all_with_error.3186356618 |
| Directory | /workspace/93.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/93.xbar_stress_all_with_rand_reset.1591455185 |
| Short name | T2841 |
| Test name | |
| Test status | |
| Simulation time | 4018801516 ps |
| CPU time | 480.42 seconds |
| Started | Aug 12 06:58:56 PM PDT 24 |
| Finished | Aug 12 07:06:57 PM PDT 24 |
| Peak memory | 576608 kb |
| Host | smart-a8dc7695-6e4d-427b-acf4-9d6135796d1d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1591455185 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 93.xbar_stress_all _with_rand_reset.1591455185 |
| Directory | /workspace/93.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/93.xbar_stress_all_with_reset_error.1100453665 |
| Short name | T2044 |
| Test name | |
| Test status | |
| Simulation time | 872907837 ps |
| CPU time | 180.68 seconds |
| Started | Aug 12 06:58:57 PM PDT 24 |
| Finished | Aug 12 07:01:58 PM PDT 24 |
| Peak memory | 575680 kb |
| Host | smart-9948f581-da0c-49e0-83d0-03f0567513e3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1100453665 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 93.xbar_stress_al l_with_reset_error.1100453665 |
| Directory | /workspace/93.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/93.xbar_unmapped_addr.103954729 |
| Short name | T2484 |
| Test name | |
| Test status | |
| Simulation time | 851200485 ps |
| CPU time | 31.78 seconds |
| Started | Aug 12 06:58:57 PM PDT 24 |
| Finished | Aug 12 06:59:29 PM PDT 24 |
| Peak memory | 575696 kb |
| Host | smart-f0829bb7-eca4-4d4d-8365-1dc9f7317087 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=103954729 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 93.xbar_unmapped_addr.103954729 |
| Directory | /workspace/93.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/94.xbar_access_same_device.1134555732 |
| Short name | T2645 |
| Test name | |
| Test status | |
| Simulation time | 472735717 ps |
| CPU time | 21.55 seconds |
| Started | Aug 12 06:58:59 PM PDT 24 |
| Finished | Aug 12 06:59:20 PM PDT 24 |
| Peak memory | 575564 kb |
| Host | smart-4eb7db21-9dd7-4ef3-b2d3-243862e65326 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1134555732 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 94.xbar_access_same_device .1134555732 |
| Directory | /workspace/94.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/94.xbar_access_same_device_slow_rsp.2028013954 |
| Short name | T2181 |
| Test name | |
| Test status | |
| Simulation time | 7833122636 ps |
| CPU time | 144.87 seconds |
| Started | Aug 12 06:58:57 PM PDT 24 |
| Finished | Aug 12 07:01:22 PM PDT 24 |
| Peak memory | 575784 kb |
| Host | smart-e237bfc6-ad61-43a3-8375-5ada7cbbe506 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2028013954 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 94.xbar_access_same_ device_slow_rsp.2028013954 |
| Directory | /workspace/94.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/94.xbar_error_and_unmapped_addr.4253629600 |
| Short name | T2640 |
| Test name | |
| Test status | |
| Simulation time | 1106335702 ps |
| CPU time | 41.6 seconds |
| Started | Aug 12 06:58:55 PM PDT 24 |
| Finished | Aug 12 06:59:37 PM PDT 24 |
| Peak memory | 575740 kb |
| Host | smart-b6f6ef95-b894-4fa3-8a53-36b73eacb6c3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4253629600 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 94.xbar_error_and_unmapped_add r.4253629600 |
| Directory | /workspace/94.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/94.xbar_error_random.2292849229 |
| Short name | T564 |
| Test name | |
| Test status | |
| Simulation time | 2427493449 ps |
| CPU time | 87.53 seconds |
| Started | Aug 12 06:58:59 PM PDT 24 |
| Finished | Aug 12 07:00:26 PM PDT 24 |
| Peak memory | 575724 kb |
| Host | smart-d28b4643-5c49-4ec9-958a-1fa439968e78 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2292849229 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 94.xbar_error_random.2292849229 |
| Directory | /workspace/94.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/94.xbar_random.3621370988 |
| Short name | T2082 |
| Test name | |
| Test status | |
| Simulation time | 1262652893 ps |
| CPU time | 45.04 seconds |
| Started | Aug 12 06:58:57 PM PDT 24 |
| Finished | Aug 12 06:59:42 PM PDT 24 |
| Peak memory | 575684 kb |
| Host | smart-8e912de9-19bf-4111-9cbf-8d2e72b5420f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3621370988 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 94.xbar_random.3621370988 |
| Directory | /workspace/94.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/94.xbar_random_large_delays.1110731507 |
| Short name | T1771 |
| Test name | |
| Test status | |
| Simulation time | 88691042585 ps |
| CPU time | 973.61 seconds |
| Started | Aug 12 06:58:56 PM PDT 24 |
| Finished | Aug 12 07:15:09 PM PDT 24 |
| Peak memory | 575880 kb |
| Host | smart-89517370-2085-4ece-80b1-ed2d5df53927 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1110731507 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 94.xbar_random_large_delays.1110731507 |
| Directory | /workspace/94.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/94.xbar_random_slow_rsp.4029229321 |
| Short name | T1865 |
| Test name | |
| Test status | |
| Simulation time | 36487233236 ps |
| CPU time | 728.39 seconds |
| Started | Aug 12 06:58:58 PM PDT 24 |
| Finished | Aug 12 07:11:07 PM PDT 24 |
| Peak memory | 575696 kb |
| Host | smart-53450f17-455c-4bdd-ae73-4fd4ebef5e04 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4029229321 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 94.xbar_random_slow_rsp.4029229321 |
| Directory | /workspace/94.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/94.xbar_random_zero_delays.2087717202 |
| Short name | T2132 |
| Test name | |
| Test status | |
| Simulation time | 104773957 ps |
| CPU time | 11.19 seconds |
| Started | Aug 12 06:59:01 PM PDT 24 |
| Finished | Aug 12 06:59:12 PM PDT 24 |
| Peak memory | 575680 kb |
| Host | smart-c630cc35-0b56-40d0-952e-2970796754e4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2087717202 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 94.xbar_random_zero_del ays.2087717202 |
| Directory | /workspace/94.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/94.xbar_same_source.2449240815 |
| Short name | T1855 |
| Test name | |
| Test status | |
| Simulation time | 280984474 ps |
| CPU time | 20.58 seconds |
| Started | Aug 12 06:59:00 PM PDT 24 |
| Finished | Aug 12 06:59:21 PM PDT 24 |
| Peak memory | 575608 kb |
| Host | smart-1cd1ef52-034e-435d-925c-9cc58ccb294c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2449240815 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 94.xbar_same_source.2449240815 |
| Directory | /workspace/94.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/94.xbar_smoke.3388223642 |
| Short name | T2853 |
| Test name | |
| Test status | |
| Simulation time | 176079279 ps |
| CPU time | 8.34 seconds |
| Started | Aug 12 06:58:57 PM PDT 24 |
| Finished | Aug 12 06:59:06 PM PDT 24 |
| Peak memory | 573560 kb |
| Host | smart-baef804c-b120-47cc-a607-84f6b7d77840 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3388223642 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 94.xbar_smoke.3388223642 |
| Directory | /workspace/94.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/94.xbar_smoke_large_delays.1202814941 |
| Short name | T2746 |
| Test name | |
| Test status | |
| Simulation time | 7225607394 ps |
| CPU time | 74.99 seconds |
| Started | Aug 12 06:59:04 PM PDT 24 |
| Finished | Aug 12 07:00:19 PM PDT 24 |
| Peak memory | 573572 kb |
| Host | smart-601badea-0c85-42e5-9a09-b19e8ac1d902 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1202814941 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 94.xbar_smoke_large_delays.1202814941 |
| Directory | /workspace/94.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/94.xbar_smoke_slow_rsp.472312167 |
| Short name | T2105 |
| Test name | |
| Test status | |
| Simulation time | 6386939620 ps |
| CPU time | 105.46 seconds |
| Started | Aug 12 06:58:58 PM PDT 24 |
| Finished | Aug 12 07:00:43 PM PDT 24 |
| Peak memory | 573692 kb |
| Host | smart-b4d94079-3ab4-4075-85d4-77b81d8ed887 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=472312167 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 94.xbar_smoke_slow_rsp.472312167 |
| Directory | /workspace/94.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/94.xbar_smoke_zero_delays.1838870137 |
| Short name | T2370 |
| Test name | |
| Test status | |
| Simulation time | 48639486 ps |
| CPU time | 5.92 seconds |
| Started | Aug 12 06:58:58 PM PDT 24 |
| Finished | Aug 12 06:59:04 PM PDT 24 |
| Peak memory | 573660 kb |
| Host | smart-07388be9-aa85-4266-a2e8-6659eeb91a0c |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1838870137 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 94.xbar_smoke_zero_delay s.1838870137 |
| Directory | /workspace/94.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/94.xbar_stress_all.1238956418 |
| Short name | T518 |
| Test name | |
| Test status | |
| Simulation time | 2445827832 ps |
| CPU time | 192.92 seconds |
| Started | Aug 12 06:59:03 PM PDT 24 |
| Finished | Aug 12 07:02:16 PM PDT 24 |
| Peak memory | 576688 kb |
| Host | smart-f1ec6a08-ced3-4cf8-bcbd-8d879580c447 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1238956418 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 94.xbar_stress_all.1238956418 |
| Directory | /workspace/94.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/94.xbar_stress_all_with_error.2392792737 |
| Short name | T692 |
| Test name | |
| Test status | |
| Simulation time | 214031157 ps |
| CPU time | 23.83 seconds |
| Started | Aug 12 06:59:01 PM PDT 24 |
| Finished | Aug 12 06:59:25 PM PDT 24 |
| Peak memory | 575600 kb |
| Host | smart-e8460a48-268c-4bea-8bcf-92538fb6213e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2392792737 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 94.xbar_stress_all_with_error.2392792737 |
| Directory | /workspace/94.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/94.xbar_stress_all_with_rand_reset.2917246935 |
| Short name | T535 |
| Test name | |
| Test status | |
| Simulation time | 1904811515 ps |
| CPU time | 420.09 seconds |
| Started | Aug 12 06:59:00 PM PDT 24 |
| Finished | Aug 12 07:06:00 PM PDT 24 |
| Peak memory | 576504 kb |
| Host | smart-84da6403-412b-4af3-af60-77f6ee631d6e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2917246935 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 94.xbar_stress_all _with_rand_reset.2917246935 |
| Directory | /workspace/94.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/94.xbar_stress_all_with_reset_error.3065397529 |
| Short name | T1874 |
| Test name | |
| Test status | |
| Simulation time | 115571554 ps |
| CPU time | 18.65 seconds |
| Started | Aug 12 06:59:03 PM PDT 24 |
| Finished | Aug 12 06:59:21 PM PDT 24 |
| Peak memory | 576420 kb |
| Host | smart-b48e6645-a807-485b-af1e-36bbbcbdaa44 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3065397529 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 94.xbar_stress_al l_with_reset_error.3065397529 |
| Directory | /workspace/94.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/94.xbar_unmapped_addr.1384307867 |
| Short name | T619 |
| Test name | |
| Test status | |
| Simulation time | 703058814 ps |
| CPU time | 34.02 seconds |
| Started | Aug 12 06:58:59 PM PDT 24 |
| Finished | Aug 12 06:59:33 PM PDT 24 |
| Peak memory | 575648 kb |
| Host | smart-08c509c9-7be2-45b5-b540-79ec1e6944c0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1384307867 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 94.xbar_unmapped_addr.1384307867 |
| Directory | /workspace/94.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/95.xbar_access_same_device.2359805537 |
| Short name | T2092 |
| Test name | |
| Test status | |
| Simulation time | 1117366494 ps |
| CPU time | 48.84 seconds |
| Started | Aug 12 06:59:01 PM PDT 24 |
| Finished | Aug 12 06:59:50 PM PDT 24 |
| Peak memory | 575720 kb |
| Host | smart-50d9783f-721f-4cc2-af55-45a12d93478b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2359805537 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 95.xbar_access_same_device .2359805537 |
| Directory | /workspace/95.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/95.xbar_access_same_device_slow_rsp.3000282021 |
| Short name | T2778 |
| Test name | |
| Test status | |
| Simulation time | 115932731993 ps |
| CPU time | 2026.09 seconds |
| Started | Aug 12 06:59:04 PM PDT 24 |
| Finished | Aug 12 07:32:50 PM PDT 24 |
| Peak memory | 575892 kb |
| Host | smart-23a5c31f-2bfc-442a-87cc-9454e2366be7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3000282021 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 95.xbar_access_same_ device_slow_rsp.3000282021 |
| Directory | /workspace/95.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/95.xbar_error_and_unmapped_addr.4177001048 |
| Short name | T1450 |
| Test name | |
| Test status | |
| Simulation time | 51944693 ps |
| CPU time | 8.37 seconds |
| Started | Aug 12 06:59:00 PM PDT 24 |
| Finished | Aug 12 06:59:08 PM PDT 24 |
| Peak memory | 575516 kb |
| Host | smart-39dd6252-3152-4cf6-a372-adb2b39d599c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4177001048 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 95.xbar_error_and_unmapped_add r.4177001048 |
| Directory | /workspace/95.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/95.xbar_error_random.3388309489 |
| Short name | T2905 |
| Test name | |
| Test status | |
| Simulation time | 836425213 ps |
| CPU time | 26.01 seconds |
| Started | Aug 12 06:59:04 PM PDT 24 |
| Finished | Aug 12 06:59:30 PM PDT 24 |
| Peak memory | 575748 kb |
| Host | smart-5642746c-5de2-424c-8f83-9299284e3065 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3388309489 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 95.xbar_error_random.3388309489 |
| Directory | /workspace/95.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/95.xbar_random.2207775735 |
| Short name | T2779 |
| Test name | |
| Test status | |
| Simulation time | 1919583127 ps |
| CPU time | 63.81 seconds |
| Started | Aug 12 06:59:00 PM PDT 24 |
| Finished | Aug 12 07:00:04 PM PDT 24 |
| Peak memory | 575684 kb |
| Host | smart-62b6c86b-620e-4781-90fa-0e30ecbda2a6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2207775735 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 95.xbar_random.2207775735 |
| Directory | /workspace/95.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/95.xbar_random_large_delays.78901903 |
| Short name | T718 |
| Test name | |
| Test status | |
| Simulation time | 35189127715 ps |
| CPU time | 350.66 seconds |
| Started | Aug 12 06:59:01 PM PDT 24 |
| Finished | Aug 12 07:04:52 PM PDT 24 |
| Peak memory | 575728 kb |
| Host | smart-eeb2c3c2-7abd-41b5-be09-982ce7fbbce8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=78901903 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 95.xbar_random_large_delays.78901903 |
| Directory | /workspace/95.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/95.xbar_random_slow_rsp.2015618850 |
| Short name | T626 |
| Test name | |
| Test status | |
| Simulation time | 68350739347 ps |
| CPU time | 1009.07 seconds |
| Started | Aug 12 06:59:00 PM PDT 24 |
| Finished | Aug 12 07:15:49 PM PDT 24 |
| Peak memory | 575676 kb |
| Host | smart-a27f7c1f-4455-4369-a07d-3037450f6acd |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2015618850 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 95.xbar_random_slow_rsp.2015618850 |
| Directory | /workspace/95.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/95.xbar_random_zero_delays.2771645424 |
| Short name | T1817 |
| Test name | |
| Test status | |
| Simulation time | 549579721 ps |
| CPU time | 44.81 seconds |
| Started | Aug 12 06:59:02 PM PDT 24 |
| Finished | Aug 12 06:59:47 PM PDT 24 |
| Peak memory | 575716 kb |
| Host | smart-77f0f008-b1a6-43eb-9b54-f4146afdfe3c |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2771645424 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 95.xbar_random_zero_del ays.2771645424 |
| Directory | /workspace/95.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/95.xbar_same_source.2033903919 |
| Short name | T607 |
| Test name | |
| Test status | |
| Simulation time | 1856977153 ps |
| CPU time | 54.66 seconds |
| Started | Aug 12 06:59:01 PM PDT 24 |
| Finished | Aug 12 06:59:55 PM PDT 24 |
| Peak memory | 575516 kb |
| Host | smart-aa5821d1-deb0-4121-a8dd-d3bd0e360018 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2033903919 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 95.xbar_same_source.2033903919 |
| Directory | /workspace/95.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/95.xbar_smoke.1029575909 |
| Short name | T1947 |
| Test name | |
| Test status | |
| Simulation time | 201449862 ps |
| CPU time | 8.88 seconds |
| Started | Aug 12 06:59:00 PM PDT 24 |
| Finished | Aug 12 06:59:09 PM PDT 24 |
| Peak memory | 573564 kb |
| Host | smart-5326da2b-2c37-4ea8-ab3a-de90c6fd5465 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1029575909 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 95.xbar_smoke.1029575909 |
| Directory | /workspace/95.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/95.xbar_smoke_large_delays.437410183 |
| Short name | T2745 |
| Test name | |
| Test status | |
| Simulation time | 7800485527 ps |
| CPU time | 81.09 seconds |
| Started | Aug 12 06:58:57 PM PDT 24 |
| Finished | Aug 12 07:00:18 PM PDT 24 |
| Peak memory | 573640 kb |
| Host | smart-62713f07-e86e-414e-8415-969cad2b9210 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=437410183 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 95.xbar_smoke_large_delays.437410183 |
| Directory | /workspace/95.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/95.xbar_smoke_slow_rsp.2256235466 |
| Short name | T2750 |
| Test name | |
| Test status | |
| Simulation time | 3622334214 ps |
| CPU time | 62.37 seconds |
| Started | Aug 12 06:58:58 PM PDT 24 |
| Finished | Aug 12 07:00:01 PM PDT 24 |
| Peak memory | 574284 kb |
| Host | smart-d8559f99-6126-48d7-a406-e8cc4a1a0790 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2256235466 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 95.xbar_smoke_slow_rsp.2256235466 |
| Directory | /workspace/95.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/95.xbar_smoke_zero_delays.3668515927 |
| Short name | T1514 |
| Test name | |
| Test status | |
| Simulation time | 43829073 ps |
| CPU time | 6.15 seconds |
| Started | Aug 12 06:59:01 PM PDT 24 |
| Finished | Aug 12 06:59:07 PM PDT 24 |
| Peak memory | 573676 kb |
| Host | smart-1347fd2c-4dd7-40b0-b537-ad67ecdcad8d |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3668515927 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 95.xbar_smoke_zero_delay s.3668515927 |
| Directory | /workspace/95.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/95.xbar_stress_all.3973107671 |
| Short name | T663 |
| Test name | |
| Test status | |
| Simulation time | 1088923013 ps |
| CPU time | 81.38 seconds |
| Started | Aug 12 06:59:04 PM PDT 24 |
| Finished | Aug 12 07:00:25 PM PDT 24 |
| Peak memory | 575760 kb |
| Host | smart-737f3a04-40e5-4c17-beb9-1b56f4da2bd2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3973107671 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 95.xbar_stress_all.3973107671 |
| Directory | /workspace/95.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/95.xbar_stress_all_with_error.4275105603 |
| Short name | T911 |
| Test name | |
| Test status | |
| Simulation time | 4966450826 ps |
| CPU time | 190.95 seconds |
| Started | Aug 12 06:59:02 PM PDT 24 |
| Finished | Aug 12 07:02:13 PM PDT 24 |
| Peak memory | 575920 kb |
| Host | smart-b1a06dd4-cfd9-4721-a20e-33c42aa84ead |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4275105603 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 95.xbar_stress_all_with_error.4275105603 |
| Directory | /workspace/95.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/95.xbar_stress_all_with_rand_reset.1441428829 |
| Short name | T490 |
| Test name | |
| Test status | |
| Simulation time | 2040026979 ps |
| CPU time | 275.34 seconds |
| Started | Aug 12 06:59:03 PM PDT 24 |
| Finished | Aug 12 07:03:39 PM PDT 24 |
| Peak memory | 576516 kb |
| Host | smart-62e60875-d26b-4b2e-ae9f-9ecc9b052613 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1441428829 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 95.xbar_stress_all _with_rand_reset.1441428829 |
| Directory | /workspace/95.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/95.xbar_stress_all_with_reset_error.1480329524 |
| Short name | T2689 |
| Test name | |
| Test status | |
| Simulation time | 3338612777 ps |
| CPU time | 252.8 seconds |
| Started | Aug 12 06:59:00 PM PDT 24 |
| Finished | Aug 12 07:03:13 PM PDT 24 |
| Peak memory | 576564 kb |
| Host | smart-71fdc425-1396-4915-90e5-b4281c227e51 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1480329524 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 95.xbar_stress_al l_with_reset_error.1480329524 |
| Directory | /workspace/95.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/95.xbar_unmapped_addr.2741180225 |
| Short name | T1803 |
| Test name | |
| Test status | |
| Simulation time | 314828713 ps |
| CPU time | 37.97 seconds |
| Started | Aug 12 06:59:00 PM PDT 24 |
| Finished | Aug 12 06:59:38 PM PDT 24 |
| Peak memory | 575732 kb |
| Host | smart-669537c0-e0cc-4cf4-9e25-ae6dd9522d2a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2741180225 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 95.xbar_unmapped_addr.2741180225 |
| Directory | /workspace/95.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/96.xbar_access_same_device.4283155811 |
| Short name | T2031 |
| Test name | |
| Test status | |
| Simulation time | 646968925 ps |
| CPU time | 30.24 seconds |
| Started | Aug 12 06:59:10 PM PDT 24 |
| Finished | Aug 12 06:59:40 PM PDT 24 |
| Peak memory | 575688 kb |
| Host | smart-0f8f9295-af88-4022-9c5e-115c7d4086e2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4283155811 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 96.xbar_access_same_device .4283155811 |
| Directory | /workspace/96.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/96.xbar_error_and_unmapped_addr.2455128940 |
| Short name | T2468 |
| Test name | |
| Test status | |
| Simulation time | 1230620304 ps |
| CPU time | 46.82 seconds |
| Started | Aug 12 06:59:18 PM PDT 24 |
| Finished | Aug 12 07:00:05 PM PDT 24 |
| Peak memory | 575516 kb |
| Host | smart-e6169628-5d7a-41e9-8c97-b5cc012218da |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2455128940 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 96.xbar_error_and_unmapped_add r.2455128940 |
| Directory | /workspace/96.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/96.xbar_error_random.953627253 |
| Short name | T1530 |
| Test name | |
| Test status | |
| Simulation time | 269822595 ps |
| CPU time | 23.96 seconds |
| Started | Aug 12 06:59:10 PM PDT 24 |
| Finished | Aug 12 06:59:34 PM PDT 24 |
| Peak memory | 575680 kb |
| Host | smart-9912efb7-cc9a-4710-83b3-0cb2c35f6441 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=953627253 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 96.xbar_error_random.953627253 |
| Directory | /workspace/96.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/96.xbar_random.3425959384 |
| Short name | T471 |
| Test name | |
| Test status | |
| Simulation time | 2586789321 ps |
| CPU time | 91.22 seconds |
| Started | Aug 12 06:59:07 PM PDT 24 |
| Finished | Aug 12 07:00:38 PM PDT 24 |
| Peak memory | 575740 kb |
| Host | smart-bf6521e2-ef14-4998-990c-614b334e39fd |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3425959384 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 96.xbar_random.3425959384 |
| Directory | /workspace/96.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/96.xbar_random_large_delays.3160834007 |
| Short name | T2288 |
| Test name | |
| Test status | |
| Simulation time | 108936157906 ps |
| CPU time | 1164.21 seconds |
| Started | Aug 12 06:59:06 PM PDT 24 |
| Finished | Aug 12 07:18:31 PM PDT 24 |
| Peak memory | 575800 kb |
| Host | smart-c1fc3e44-9321-49d2-b0ab-e874778ce2a4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3160834007 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 96.xbar_random_large_delays.3160834007 |
| Directory | /workspace/96.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/96.xbar_random_slow_rsp.1590449260 |
| Short name | T2074 |
| Test name | |
| Test status | |
| Simulation time | 37712603731 ps |
| CPU time | 670.15 seconds |
| Started | Aug 12 06:59:11 PM PDT 24 |
| Finished | Aug 12 07:10:21 PM PDT 24 |
| Peak memory | 575640 kb |
| Host | smart-6d6d1cbf-32da-44c1-b5c1-f98ef738e825 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1590449260 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 96.xbar_random_slow_rsp.1590449260 |
| Directory | /workspace/96.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/96.xbar_random_zero_delays.3273035460 |
| Short name | T562 |
| Test name | |
| Test status | |
| Simulation time | 143231736 ps |
| CPU time | 16.15 seconds |
| Started | Aug 12 06:59:17 PM PDT 24 |
| Finished | Aug 12 06:59:34 PM PDT 24 |
| Peak memory | 575612 kb |
| Host | smart-94f5c7d5-cdc8-44e3-8e20-4b5a35c1f76b |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3273035460 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 96.xbar_random_zero_del ays.3273035460 |
| Directory | /workspace/96.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/96.xbar_same_source.2759808049 |
| Short name | T676 |
| Test name | |
| Test status | |
| Simulation time | 181130838 ps |
| CPU time | 16.45 seconds |
| Started | Aug 12 06:59:08 PM PDT 24 |
| Finished | Aug 12 06:59:25 PM PDT 24 |
| Peak memory | 575664 kb |
| Host | smart-a4e286dd-6b7e-4709-96d6-ebc56f7251aa |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2759808049 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 96.xbar_same_source.2759808049 |
| Directory | /workspace/96.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/96.xbar_smoke.3619842455 |
| Short name | T2215 |
| Test name | |
| Test status | |
| Simulation time | 50889545 ps |
| CPU time | 6.45 seconds |
| Started | Aug 12 06:59:01 PM PDT 24 |
| Finished | Aug 12 06:59:08 PM PDT 24 |
| Peak memory | 573532 kb |
| Host | smart-0127ef17-52ca-4aaf-b6e5-81043a054a49 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3619842455 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 96.xbar_smoke.3619842455 |
| Directory | /workspace/96.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/96.xbar_smoke_large_delays.3127538332 |
| Short name | T1492 |
| Test name | |
| Test status | |
| Simulation time | 7592970136 ps |
| CPU time | 84.05 seconds |
| Started | Aug 12 06:59:01 PM PDT 24 |
| Finished | Aug 12 07:00:25 PM PDT 24 |
| Peak memory | 574360 kb |
| Host | smart-b58281a8-8470-4d09-81f9-4c23886f88b4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3127538332 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 96.xbar_smoke_large_delays.3127538332 |
| Directory | /workspace/96.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/96.xbar_smoke_slow_rsp.3635805960 |
| Short name | T502 |
| Test name | |
| Test status | |
| Simulation time | 5953034876 ps |
| CPU time | 92.3 seconds |
| Started | Aug 12 06:59:00 PM PDT 24 |
| Finished | Aug 12 07:00:32 PM PDT 24 |
| Peak memory | 574356 kb |
| Host | smart-e62ee15a-63cf-46c8-9bdf-dedb24f827d0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3635805960 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 96.xbar_smoke_slow_rsp.3635805960 |
| Directory | /workspace/96.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/96.xbar_smoke_zero_delays.2885463115 |
| Short name | T1576 |
| Test name | |
| Test status | |
| Simulation time | 43654646 ps |
| CPU time | 5.8 seconds |
| Started | Aug 12 06:59:00 PM PDT 24 |
| Finished | Aug 12 06:59:06 PM PDT 24 |
| Peak memory | 573608 kb |
| Host | smart-f11d94b9-0da0-4da6-b4da-d59306c315d7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2885463115 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 96.xbar_smoke_zero_delay s.2885463115 |
| Directory | /workspace/96.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/96.xbar_stress_all.1860513340 |
| Short name | T2594 |
| Test name | |
| Test status | |
| Simulation time | 10445768880 ps |
| CPU time | 343.68 seconds |
| Started | Aug 12 06:59:09 PM PDT 24 |
| Finished | Aug 12 07:04:53 PM PDT 24 |
| Peak memory | 575760 kb |
| Host | smart-273c0a6e-33b6-462b-801c-c1757717e53a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1860513340 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 96.xbar_stress_all.1860513340 |
| Directory | /workspace/96.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/96.xbar_stress_all_with_error.4254959275 |
| Short name | T1887 |
| Test name | |
| Test status | |
| Simulation time | 9438302594 ps |
| CPU time | 353.63 seconds |
| Started | Aug 12 06:59:07 PM PDT 24 |
| Finished | Aug 12 07:05:01 PM PDT 24 |
| Peak memory | 575856 kb |
| Host | smart-6b4dd8aa-2ae4-4810-a8b5-5d613746c3a3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4254959275 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 96.xbar_stress_all_with_error.4254959275 |
| Directory | /workspace/96.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/96.xbar_stress_all_with_rand_reset.3326542048 |
| Short name | T2188 |
| Test name | |
| Test status | |
| Simulation time | 611931368 ps |
| CPU time | 237.52 seconds |
| Started | Aug 12 06:59:21 PM PDT 24 |
| Finished | Aug 12 07:03:18 PM PDT 24 |
| Peak memory | 575720 kb |
| Host | smart-0bb3f335-059b-4071-96c4-f97949132478 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3326542048 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 96.xbar_stress_all _with_rand_reset.3326542048 |
| Directory | /workspace/96.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/96.xbar_stress_all_with_reset_error.900161542 |
| Short name | T894 |
| Test name | |
| Test status | |
| Simulation time | 442365266 ps |
| CPU time | 144.69 seconds |
| Started | Aug 12 06:59:20 PM PDT 24 |
| Finished | Aug 12 07:01:45 PM PDT 24 |
| Peak memory | 575720 kb |
| Host | smart-1d3fe955-ff70-4cb8-ad31-946ea5e9b179 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=900161542 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 96.xbar_stress_all _with_reset_error.900161542 |
| Directory | /workspace/96.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/96.xbar_unmapped_addr.2461117876 |
| Short name | T576 |
| Test name | |
| Test status | |
| Simulation time | 278615648 ps |
| CPU time | 31.43 seconds |
| Started | Aug 12 06:59:19 PM PDT 24 |
| Finished | Aug 12 06:59:51 PM PDT 24 |
| Peak memory | 575724 kb |
| Host | smart-0f45b896-87aa-4665-802d-e198bde0b866 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2461117876 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 96.xbar_unmapped_addr.2461117876 |
| Directory | /workspace/96.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/97.xbar_access_same_device.134781041 |
| Short name | T932 |
| Test name | |
| Test status | |
| Simulation time | 3530608996 ps |
| CPU time | 144.78 seconds |
| Started | Aug 12 06:59:08 PM PDT 24 |
| Finished | Aug 12 07:01:33 PM PDT 24 |
| Peak memory | 575684 kb |
| Host | smart-9e8ddc7e-4d8a-4f4d-96c1-d32f79148f79 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=134781041 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 97.xbar_access_same_device. 134781041 |
| Directory | /workspace/97.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/97.xbar_access_same_device_slow_rsp.562538613 |
| Short name | T934 |
| Test name | |
| Test status | |
| Simulation time | 19934990417 ps |
| CPU time | 360.39 seconds |
| Started | Aug 12 06:59:11 PM PDT 24 |
| Finished | Aug 12 07:05:11 PM PDT 24 |
| Peak memory | 575572 kb |
| Host | smart-737bdda8-e8ad-4dae-bbca-36a2c47fc5c4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=562538613 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 97.xbar_access_same_d evice_slow_rsp.562538613 |
| Directory | /workspace/97.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/97.xbar_error_and_unmapped_addr.1040543275 |
| Short name | T2577 |
| Test name | |
| Test status | |
| Simulation time | 115061587 ps |
| CPU time | 8.39 seconds |
| Started | Aug 12 06:59:17 PM PDT 24 |
| Finished | Aug 12 06:59:25 PM PDT 24 |
| Peak memory | 573636 kb |
| Host | smart-7e4fd1cf-2d09-4aa6-9f34-3ca0f7c2cb53 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1040543275 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 97.xbar_error_and_unmapped_add r.1040543275 |
| Directory | /workspace/97.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/97.xbar_random.917744353 |
| Short name | T2522 |
| Test name | |
| Test status | |
| Simulation time | 57017912 ps |
| CPU time | 8.02 seconds |
| Started | Aug 12 06:59:10 PM PDT 24 |
| Finished | Aug 12 06:59:19 PM PDT 24 |
| Peak memory | 574328 kb |
| Host | smart-42067db9-4cf9-4291-a022-7602e3a97f8b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=917744353 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 97.xbar_random.917744353 |
| Directory | /workspace/97.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/97.xbar_random_large_delays.3302305360 |
| Short name | T476 |
| Test name | |
| Test status | |
| Simulation time | 57685131858 ps |
| CPU time | 721.7 seconds |
| Started | Aug 12 06:59:07 PM PDT 24 |
| Finished | Aug 12 07:11:09 PM PDT 24 |
| Peak memory | 575776 kb |
| Host | smart-076f913e-bc9f-41f5-af28-b0e57bf3ea39 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3302305360 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 97.xbar_random_large_delays.3302305360 |
| Directory | /workspace/97.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/97.xbar_random_slow_rsp.1764617578 |
| Short name | T1982 |
| Test name | |
| Test status | |
| Simulation time | 49224607229 ps |
| CPU time | 879.28 seconds |
| Started | Aug 12 06:59:20 PM PDT 24 |
| Finished | Aug 12 07:13:59 PM PDT 24 |
| Peak memory | 575668 kb |
| Host | smart-f1bc8d47-ed11-47cd-b7da-5bb213654a33 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1764617578 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 97.xbar_random_slow_rsp.1764617578 |
| Directory | /workspace/97.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/97.xbar_random_zero_delays.1003876105 |
| Short name | T2799 |
| Test name | |
| Test status | |
| Simulation time | 559231585 ps |
| CPU time | 48.75 seconds |
| Started | Aug 12 06:59:11 PM PDT 24 |
| Finished | Aug 12 07:00:00 PM PDT 24 |
| Peak memory | 575684 kb |
| Host | smart-87a174a7-8af0-4511-a032-0c41e1ac6e81 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1003876105 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 97.xbar_random_zero_del ays.1003876105 |
| Directory | /workspace/97.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/97.xbar_same_source.3249612053 |
| Short name | T647 |
| Test name | |
| Test status | |
| Simulation time | 437791788 ps |
| CPU time | 27.77 seconds |
| Started | Aug 12 06:59:11 PM PDT 24 |
| Finished | Aug 12 06:59:38 PM PDT 24 |
| Peak memory | 575512 kb |
| Host | smart-d4e853ea-eda4-42b4-af94-c6202399f38b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3249612053 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 97.xbar_same_source.3249612053 |
| Directory | /workspace/97.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/97.xbar_smoke.2125744239 |
| Short name | T2850 |
| Test name | |
| Test status | |
| Simulation time | 239846119 ps |
| CPU time | 9.95 seconds |
| Started | Aug 12 06:59:18 PM PDT 24 |
| Finished | Aug 12 06:59:29 PM PDT 24 |
| Peak memory | 573528 kb |
| Host | smart-bef4cb0c-fb0b-4bc8-b159-2f43026e88eb |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2125744239 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 97.xbar_smoke.2125744239 |
| Directory | /workspace/97.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/97.xbar_smoke_large_delays.2356986521 |
| Short name | T2919 |
| Test name | |
| Test status | |
| Simulation time | 8525344027 ps |
| CPU time | 90.69 seconds |
| Started | Aug 12 06:59:11 PM PDT 24 |
| Finished | Aug 12 07:00:42 PM PDT 24 |
| Peak memory | 573612 kb |
| Host | smart-abfff2ec-1b74-4da7-8068-4026a747fb05 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2356986521 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 97.xbar_smoke_large_delays.2356986521 |
| Directory | /workspace/97.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/97.xbar_smoke_slow_rsp.4184430168 |
| Short name | T1509 |
| Test name | |
| Test status | |
| Simulation time | 4996409441 ps |
| CPU time | 85.07 seconds |
| Started | Aug 12 06:59:20 PM PDT 24 |
| Finished | Aug 12 07:00:45 PM PDT 24 |
| Peak memory | 573712 kb |
| Host | smart-64e03e2e-c844-436e-bf0f-a1c5b7d3fbfb |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4184430168 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 97.xbar_smoke_slow_rsp.4184430168 |
| Directory | /workspace/97.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/97.xbar_smoke_zero_delays.2622694818 |
| Short name | T2170 |
| Test name | |
| Test status | |
| Simulation time | 53571642 ps |
| CPU time | 6.82 seconds |
| Started | Aug 12 06:59:18 PM PDT 24 |
| Finished | Aug 12 06:59:25 PM PDT 24 |
| Peak memory | 573592 kb |
| Host | smart-cc42e366-8c83-43c7-9a37-ba5102a186ef |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2622694818 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 97.xbar_smoke_zero_delay s.2622694818 |
| Directory | /workspace/97.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/97.xbar_stress_all.3165916890 |
| Short name | T591 |
| Test name | |
| Test status | |
| Simulation time | 7472490258 ps |
| CPU time | 302.8 seconds |
| Started | Aug 12 06:59:19 PM PDT 24 |
| Finished | Aug 12 07:04:22 PM PDT 24 |
| Peak memory | 575796 kb |
| Host | smart-9511659e-b077-42b8-97e8-0a8d3543b118 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3165916890 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 97.xbar_stress_all.3165916890 |
| Directory | /workspace/97.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/97.xbar_stress_all_with_error.126443420 |
| Short name | T2762 |
| Test name | |
| Test status | |
| Simulation time | 2715763418 ps |
| CPU time | 101.14 seconds |
| Started | Aug 12 06:59:18 PM PDT 24 |
| Finished | Aug 12 07:00:59 PM PDT 24 |
| Peak memory | 575660 kb |
| Host | smart-faeb172d-ca01-4cc3-9ca7-01c86e62447d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=126443420 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 97.xbar_stress_all_with_error.126443420 |
| Directory | /workspace/97.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/97.xbar_stress_all_with_rand_reset.4190819020 |
| Short name | T1967 |
| Test name | |
| Test status | |
| Simulation time | 4057897458 ps |
| CPU time | 459.7 seconds |
| Started | Aug 12 06:59:19 PM PDT 24 |
| Finished | Aug 12 07:06:59 PM PDT 24 |
| Peak memory | 575768 kb |
| Host | smart-70715411-6e2b-466b-b27e-0dc524cd8396 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4190819020 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 97.xbar_stress_all _with_rand_reset.4190819020 |
| Directory | /workspace/97.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/97.xbar_stress_all_with_reset_error.3056748510 |
| Short name | T1819 |
| Test name | |
| Test status | |
| Simulation time | 146559640 ps |
| CPU time | 40.15 seconds |
| Started | Aug 12 06:59:18 PM PDT 24 |
| Finished | Aug 12 06:59:58 PM PDT 24 |
| Peak memory | 575808 kb |
| Host | smart-2baf0f1b-d534-4fba-a106-77b3de5fa878 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3056748510 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 97.xbar_stress_al l_with_reset_error.3056748510 |
| Directory | /workspace/97.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/97.xbar_unmapped_addr.462439303 |
| Short name | T484 |
| Test name | |
| Test status | |
| Simulation time | 920971636 ps |
| CPU time | 36.47 seconds |
| Started | Aug 12 06:59:19 PM PDT 24 |
| Finished | Aug 12 06:59:56 PM PDT 24 |
| Peak memory | 575576 kb |
| Host | smart-8c541d98-0bb3-4d96-a5d9-bcd075208c56 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=462439303 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 97.xbar_unmapped_addr.462439303 |
| Directory | /workspace/97.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/98.xbar_access_same_device.1367554417 |
| Short name | T910 |
| Test name | |
| Test status | |
| Simulation time | 1444524284 ps |
| CPU time | 59.81 seconds |
| Started | Aug 12 06:59:19 PM PDT 24 |
| Finished | Aug 12 07:00:18 PM PDT 24 |
| Peak memory | 575728 kb |
| Host | smart-cad28356-75f3-411f-ba63-52791f127398 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1367554417 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 98.xbar_access_same_device .1367554417 |
| Directory | /workspace/98.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/98.xbar_access_same_device_slow_rsp.2429467174 |
| Short name | T2666 |
| Test name | |
| Test status | |
| Simulation time | 93296099228 ps |
| CPU time | 1592.83 seconds |
| Started | Aug 12 06:59:22 PM PDT 24 |
| Finished | Aug 12 07:25:56 PM PDT 24 |
| Peak memory | 575748 kb |
| Host | smart-28472486-e487-4c24-8a8a-cfe36af194b3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2429467174 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 98.xbar_access_same_ device_slow_rsp.2429467174 |
| Directory | /workspace/98.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/98.xbar_error_and_unmapped_addr.2439893199 |
| Short name | T2674 |
| Test name | |
| Test status | |
| Simulation time | 236272909 ps |
| CPU time | 28.87 seconds |
| Started | Aug 12 06:59:28 PM PDT 24 |
| Finished | Aug 12 06:59:57 PM PDT 24 |
| Peak memory | 575736 kb |
| Host | smart-0b1f5657-33a0-47c1-97de-0063a062132f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2439893199 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 98.xbar_error_and_unmapped_add r.2439893199 |
| Directory | /workspace/98.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/98.xbar_error_random.394560986 |
| Short name | T2452 |
| Test name | |
| Test status | |
| Simulation time | 1156908062 ps |
| CPU time | 39.38 seconds |
| Started | Aug 12 06:59:26 PM PDT 24 |
| Finished | Aug 12 07:00:05 PM PDT 24 |
| Peak memory | 575672 kb |
| Host | smart-2f348aa0-3e24-486e-b6e2-37f3ee5693b0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=394560986 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 98.xbar_error_random.394560986 |
| Directory | /workspace/98.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/98.xbar_random.3358795132 |
| Short name | T1920 |
| Test name | |
| Test status | |
| Simulation time | 391763828 ps |
| CPU time | 34.09 seconds |
| Started | Aug 12 06:59:19 PM PDT 24 |
| Finished | Aug 12 06:59:53 PM PDT 24 |
| Peak memory | 575628 kb |
| Host | smart-89422cad-0d52-45d4-8b39-5df08fe6a8b2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3358795132 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 98.xbar_random.3358795132 |
| Directory | /workspace/98.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/98.xbar_random_large_delays.3546351558 |
| Short name | T2040 |
| Test name | |
| Test status | |
| Simulation time | 70258953148 ps |
| CPU time | 831.91 seconds |
| Started | Aug 12 06:59:17 PM PDT 24 |
| Finished | Aug 12 07:13:09 PM PDT 24 |
| Peak memory | 575684 kb |
| Host | smart-1aff4577-8d38-40e6-b60e-bf09822e8ca4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3546351558 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 98.xbar_random_large_delays.3546351558 |
| Directory | /workspace/98.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/98.xbar_random_slow_rsp.638630978 |
| Short name | T2658 |
| Test name | |
| Test status | |
| Simulation time | 2295972090 ps |
| CPU time | 37.87 seconds |
| Started | Aug 12 06:59:17 PM PDT 24 |
| Finished | Aug 12 06:59:55 PM PDT 24 |
| Peak memory | 573592 kb |
| Host | smart-062faf1e-0cdc-43db-b57b-72f97932816c |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=638630978 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 98.xbar_random_slow_rsp.638630978 |
| Directory | /workspace/98.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/98.xbar_random_zero_delays.579885621 |
| Short name | T2713 |
| Test name | |
| Test status | |
| Simulation time | 109821464 ps |
| CPU time | 11.03 seconds |
| Started | Aug 12 06:59:15 PM PDT 24 |
| Finished | Aug 12 06:59:26 PM PDT 24 |
| Peak memory | 574404 kb |
| Host | smart-0e31fb39-6237-4829-8a22-db8735dbe01b |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=579885621 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 98.xbar_random_zero_dela ys.579885621 |
| Directory | /workspace/98.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/98.xbar_same_source.881323703 |
| Short name | T2397 |
| Test name | |
| Test status | |
| Simulation time | 149869194 ps |
| CPU time | 11.4 seconds |
| Started | Aug 12 06:59:32 PM PDT 24 |
| Finished | Aug 12 06:59:44 PM PDT 24 |
| Peak memory | 575616 kb |
| Host | smart-99e8b3a9-bfd5-4023-8e4e-8cfa10fe7c66 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=881323703 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 98.xbar_same_source.881323703 |
| Directory | /workspace/98.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/98.xbar_smoke.3459264454 |
| Short name | T625 |
| Test name | |
| Test status | |
| Simulation time | 173145701 ps |
| CPU time | 8.19 seconds |
| Started | Aug 12 06:59:22 PM PDT 24 |
| Finished | Aug 12 06:59:31 PM PDT 24 |
| Peak memory | 574296 kb |
| Host | smart-75f37ca4-cbfe-4ccf-860a-809586e8fcfb |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3459264454 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 98.xbar_smoke.3459264454 |
| Directory | /workspace/98.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/98.xbar_smoke_large_delays.1837249300 |
| Short name | T2539 |
| Test name | |
| Test status | |
| Simulation time | 8114282558 ps |
| CPU time | 84.11 seconds |
| Started | Aug 12 06:59:17 PM PDT 24 |
| Finished | Aug 12 07:00:42 PM PDT 24 |
| Peak memory | 574344 kb |
| Host | smart-8df33b6d-0ca1-4c80-8073-fca561dce784 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1837249300 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 98.xbar_smoke_large_delays.1837249300 |
| Directory | /workspace/98.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/98.xbar_smoke_slow_rsp.1151905155 |
| Short name | T2526 |
| Test name | |
| Test status | |
| Simulation time | 4621429242 ps |
| CPU time | 75.38 seconds |
| Started | Aug 12 06:59:16 PM PDT 24 |
| Finished | Aug 12 07:00:32 PM PDT 24 |
| Peak memory | 574352 kb |
| Host | smart-89b1d343-958f-45ed-b6f2-0bba943d19b6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1151905155 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 98.xbar_smoke_slow_rsp.1151905155 |
| Directory | /workspace/98.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/98.xbar_smoke_zero_delays.1392037414 |
| Short name | T2069 |
| Test name | |
| Test status | |
| Simulation time | 51788884 ps |
| CPU time | 6.5 seconds |
| Started | Aug 12 06:59:18 PM PDT 24 |
| Finished | Aug 12 06:59:25 PM PDT 24 |
| Peak memory | 574292 kb |
| Host | smart-0756fc0b-9e92-4260-a86e-1a586b9f0355 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1392037414 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 98.xbar_smoke_zero_delay s.1392037414 |
| Directory | /workspace/98.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/98.xbar_stress_all.2515851166 |
| Short name | T2696 |
| Test name | |
| Test status | |
| Simulation time | 5968745278 ps |
| CPU time | 231.57 seconds |
| Started | Aug 12 06:59:27 PM PDT 24 |
| Finished | Aug 12 07:03:20 PM PDT 24 |
| Peak memory | 576184 kb |
| Host | smart-8284a57a-5027-446e-a93e-3354edd19b07 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2515851166 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 98.xbar_stress_all.2515851166 |
| Directory | /workspace/98.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/98.xbar_stress_all_with_error.4070675635 |
| Short name | T1581 |
| Test name | |
| Test status | |
| Simulation time | 210880010 ps |
| CPU time | 8.22 seconds |
| Started | Aug 12 06:59:28 PM PDT 24 |
| Finished | Aug 12 06:59:36 PM PDT 24 |
| Peak memory | 574148 kb |
| Host | smart-a43b4ce0-3939-4904-b6e5-2e0552a17e43 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4070675635 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 98.xbar_stress_all_with_error.4070675635 |
| Directory | /workspace/98.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/98.xbar_stress_all_with_rand_reset.3362590542 |
| Short name | T2694 |
| Test name | |
| Test status | |
| Simulation time | 2413337987 ps |
| CPU time | 260.66 seconds |
| Started | Aug 12 06:59:26 PM PDT 24 |
| Finished | Aug 12 07:03:48 PM PDT 24 |
| Peak memory | 575740 kb |
| Host | smart-62cb08f1-c840-45db-ab20-674d8d4abf72 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3362590542 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 98.xbar_stress_all _with_rand_reset.3362590542 |
| Directory | /workspace/98.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/98.xbar_stress_all_with_reset_error.201093827 |
| Short name | T1575 |
| Test name | |
| Test status | |
| Simulation time | 816615073 ps |
| CPU time | 217.65 seconds |
| Started | Aug 12 06:59:27 PM PDT 24 |
| Finished | Aug 12 07:03:05 PM PDT 24 |
| Peak memory | 576548 kb |
| Host | smart-ca579fb6-9b2f-45d7-9188-ab09897e8022 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=201093827 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 98.xbar_stress_all _with_reset_error.201093827 |
| Directory | /workspace/98.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/98.xbar_unmapped_addr.981546005 |
| Short name | T2404 |
| Test name | |
| Test status | |
| Simulation time | 145212802 ps |
| CPU time | 8.76 seconds |
| Started | Aug 12 06:59:26 PM PDT 24 |
| Finished | Aug 12 06:59:35 PM PDT 24 |
| Peak memory | 573704 kb |
| Host | smart-e30ceb25-75c9-4c5b-afba-79d7b83491e1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=981546005 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 98.xbar_unmapped_addr.981546005 |
| Directory | /workspace/98.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/99.xbar_access_same_device.1187097798 |
| Short name | T2047 |
| Test name | |
| Test status | |
| Simulation time | 3275978274 ps |
| CPU time | 133.95 seconds |
| Started | Aug 12 06:59:27 PM PDT 24 |
| Finished | Aug 12 07:01:41 PM PDT 24 |
| Peak memory | 575780 kb |
| Host | smart-6b446c81-1bde-4d66-af01-e300acceae85 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1187097798 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 99.xbar_access_same_device .1187097798 |
| Directory | /workspace/99.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/99.xbar_access_same_device_slow_rsp.1166200495 |
| Short name | T2211 |
| Test name | |
| Test status | |
| Simulation time | 47499394391 ps |
| CPU time | 898.37 seconds |
| Started | Aug 12 06:59:32 PM PDT 24 |
| Finished | Aug 12 07:14:31 PM PDT 24 |
| Peak memory | 575712 kb |
| Host | smart-ed7b3b3b-d4d1-4277-8904-f5782684eb90 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1166200495 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 99.xbar_access_same_ device_slow_rsp.1166200495 |
| Directory | /workspace/99.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/99.xbar_error_and_unmapped_addr.1206082807 |
| Short name | T2896 |
| Test name | |
| Test status | |
| Simulation time | 134477862 ps |
| CPU time | 14.76 seconds |
| Started | Aug 12 06:59:27 PM PDT 24 |
| Finished | Aug 12 06:59:42 PM PDT 24 |
| Peak memory | 575512 kb |
| Host | smart-0c76d5b3-6f46-4e9b-825c-443fc0a81e2a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1206082807 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 99.xbar_error_and_unmapped_add r.1206082807 |
| Directory | /workspace/99.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/99.xbar_error_random.359745156 |
| Short name | T2341 |
| Test name | |
| Test status | |
| Simulation time | 438003350 ps |
| CPU time | 33.27 seconds |
| Started | Aug 12 06:59:28 PM PDT 24 |
| Finished | Aug 12 07:00:01 PM PDT 24 |
| Peak memory | 575516 kb |
| Host | smart-436ff744-6bf1-4ef2-a97d-50f9fc85cec8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=359745156 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 99.xbar_error_random.359745156 |
| Directory | /workspace/99.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/99.xbar_random.1198300305 |
| Short name | T2311 |
| Test name | |
| Test status | |
| Simulation time | 525669118 ps |
| CPU time | 21.73 seconds |
| Started | Aug 12 06:59:28 PM PDT 24 |
| Finished | Aug 12 06:59:50 PM PDT 24 |
| Peak memory | 575684 kb |
| Host | smart-9b3ef284-07b0-4f57-9adb-d93201a24df1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1198300305 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 99.xbar_random.1198300305 |
| Directory | /workspace/99.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/99.xbar_random_large_delays.279200249 |
| Short name | T2011 |
| Test name | |
| Test status | |
| Simulation time | 26212291634 ps |
| CPU time | 299.52 seconds |
| Started | Aug 12 06:59:28 PM PDT 24 |
| Finished | Aug 12 07:04:28 PM PDT 24 |
| Peak memory | 575800 kb |
| Host | smart-48dcd7b4-5303-494d-a692-26c4d52edc45 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=279200249 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 99.xbar_random_large_delays.279200249 |
| Directory | /workspace/99.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/99.xbar_random_slow_rsp.3341724377 |
| Short name | T2516 |
| Test name | |
| Test status | |
| Simulation time | 24584767725 ps |
| CPU time | 448.25 seconds |
| Started | Aug 12 06:59:27 PM PDT 24 |
| Finished | Aug 12 07:06:56 PM PDT 24 |
| Peak memory | 575728 kb |
| Host | smart-1dd1cabf-f2b0-4a34-957c-280ffd20ac32 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3341724377 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 99.xbar_random_slow_rsp.3341724377 |
| Directory | /workspace/99.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/99.xbar_random_zero_delays.2311965163 |
| Short name | T2492 |
| Test name | |
| Test status | |
| Simulation time | 575704965 ps |
| CPU time | 51.73 seconds |
| Started | Aug 12 06:59:27 PM PDT 24 |
| Finished | Aug 12 07:00:19 PM PDT 24 |
| Peak memory | 575704 kb |
| Host | smart-f58803d4-dd57-48bf-806c-44f4be9812e6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2311965163 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 99.xbar_random_zero_del ays.2311965163 |
| Directory | /workspace/99.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/99.xbar_same_source.1826133019 |
| Short name | T2052 |
| Test name | |
| Test status | |
| Simulation time | 469257620 ps |
| CPU time | 28.84 seconds |
| Started | Aug 12 06:59:29 PM PDT 24 |
| Finished | Aug 12 06:59:58 PM PDT 24 |
| Peak memory | 575608 kb |
| Host | smart-cdcfd849-5895-476d-a0f4-310fc0e3bf34 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1826133019 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 99.xbar_same_source.1826133019 |
| Directory | /workspace/99.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/99.xbar_smoke.2213107246 |
| Short name | T1527 |
| Test name | |
| Test status | |
| Simulation time | 170383744 ps |
| CPU time | 7.91 seconds |
| Started | Aug 12 06:59:28 PM PDT 24 |
| Finished | Aug 12 06:59:36 PM PDT 24 |
| Peak memory | 574260 kb |
| Host | smart-506f10e1-fefd-46af-b60a-8e5d2ef867ed |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2213107246 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 99.xbar_smoke.2213107246 |
| Directory | /workspace/99.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/99.xbar_smoke_large_delays.2423199824 |
| Short name | T2704 |
| Test name | |
| Test status | |
| Simulation time | 7682365311 ps |
| CPU time | 79.37 seconds |
| Started | Aug 12 06:59:27 PM PDT 24 |
| Finished | Aug 12 07:00:46 PM PDT 24 |
| Peak memory | 573668 kb |
| Host | smart-affa83b1-c5ed-49ea-98d2-619c0c54607c |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2423199824 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 99.xbar_smoke_large_delays.2423199824 |
| Directory | /workspace/99.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/99.xbar_smoke_slow_rsp.2519060697 |
| Short name | T2625 |
| Test name | |
| Test status | |
| Simulation time | 6356689853 ps |
| CPU time | 114.77 seconds |
| Started | Aug 12 06:59:32 PM PDT 24 |
| Finished | Aug 12 07:01:27 PM PDT 24 |
| Peak memory | 573632 kb |
| Host | smart-a2b97ce2-687d-44ac-8849-893bdd909edf |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2519060697 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 99.xbar_smoke_slow_rsp.2519060697 |
| Directory | /workspace/99.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/99.xbar_smoke_zero_delays.500909670 |
| Short name | T1537 |
| Test name | |
| Test status | |
| Simulation time | 41425272 ps |
| CPU time | 5.81 seconds |
| Started | Aug 12 06:59:28 PM PDT 24 |
| Finished | Aug 12 06:59:34 PM PDT 24 |
| Peak memory | 573604 kb |
| Host | smart-53dda4af-23e8-4684-b5f4-97e4275d5c00 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=500909670 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 99.xbar_smoke_zero_delays .500909670 |
| Directory | /workspace/99.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/99.xbar_stress_all.3623104949 |
| Short name | T2818 |
| Test name | |
| Test status | |
| Simulation time | 1995944218 ps |
| CPU time | 179.6 seconds |
| Started | Aug 12 06:59:27 PM PDT 24 |
| Finished | Aug 12 07:02:27 PM PDT 24 |
| Peak memory | 575692 kb |
| Host | smart-b323ca52-269e-48af-839a-b1b8106d9971 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3623104949 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 99.xbar_stress_all.3623104949 |
| Directory | /workspace/99.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/99.xbar_stress_all_with_error.3174063106 |
| Short name | T766 |
| Test name | |
| Test status | |
| Simulation time | 4685568935 ps |
| CPU time | 393.63 seconds |
| Started | Aug 12 06:59:27 PM PDT 24 |
| Finished | Aug 12 07:06:01 PM PDT 24 |
| Peak memory | 576576 kb |
| Host | smart-6ea22e84-535d-40ac-91dc-e5f64bc1096e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3174063106 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 99.xbar_stress_all_with_error.3174063106 |
| Directory | /workspace/99.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/99.xbar_stress_all_with_rand_reset.4032645744 |
| Short name | T2835 |
| Test name | |
| Test status | |
| Simulation time | 316112211 ps |
| CPU time | 168.36 seconds |
| Started | Aug 12 06:59:27 PM PDT 24 |
| Finished | Aug 12 07:02:16 PM PDT 24 |
| Peak memory | 576476 kb |
| Host | smart-fa03085a-194d-499e-ae9d-40f4e6d1e044 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4032645744 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 99.xbar_stress_all _with_rand_reset.4032645744 |
| Directory | /workspace/99.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/99.xbar_stress_all_with_reset_error.3902936518 |
| Short name | T957 |
| Test name | |
| Test status | |
| Simulation time | 424536902 ps |
| CPU time | 115.86 seconds |
| Started | Aug 12 06:59:40 PM PDT 24 |
| Finished | Aug 12 07:01:37 PM PDT 24 |
| Peak memory | 575648 kb |
| Host | smart-8d516605-5bb9-4309-b2a4-18884997a690 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3902936518 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 99.xbar_stress_al l_with_reset_error.3902936518 |
| Directory | /workspace/99.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/99.xbar_unmapped_addr.3302823267 |
| Short name | T721 |
| Test name | |
| Test status | |
| Simulation time | 564871284 ps |
| CPU time | 25.8 seconds |
| Started | Aug 12 06:59:28 PM PDT 24 |
| Finished | Aug 12 06:59:53 PM PDT 24 |
| Peak memory | 575732 kb |
| Host | smart-2fb1386d-53ff-4cd1-aacb-6684abdcd0bc |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3302823267 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 99.xbar_unmapped_addr.3302823267 |
| Directory | /workspace/99.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/default/0.chip_jtag_mem_access.480298966 |
| Short name | T73 |
| Test name | |
| Test status | |
| Simulation time | 13473702312 ps |
| CPU time | 1059.88 seconds |
| Started | Aug 12 07:01:08 PM PDT 24 |
| Finished | Aug 12 07:18:48 PM PDT 24 |
| Peak memory | 608208 kb |
| Host | smart-0fe70c8f-00b8-44ff-b5ab-b8eadc43bf15 |
| User | root |
| Command | /workspace/default/simv +create_jtag_riscv_map=1 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=480298966 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_jtag_m em_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_jtag_mem_access.480298966 |
| Directory | /workspace/0.chip_jtag_mem_access/latest |
| Test location | /workspace/coverage/default/0.chip_sival_flash_info_access.2181427149 |
| Short name | T367 |
| Test name | |
| Test status | |
| Simulation time | 2608614274 ps |
| CPU time | 309.19 seconds |
| Started | Aug 12 07:08:04 PM PDT 24 |
| Finished | Aug 12 07:13:14 PM PDT 24 |
| Peak memory | 610396 kb |
| Host | smart-c1fcd5ae-af5c-4e3c-8ef2-03d9dc3f0827 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStTestUnlocked0 +sw_build_device=sim_dv +sw_images=flash_ctrl_info_access_lc:1:new_rules,test_rom:0 +c dc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_s eed=2181427149 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sival_flash_info_access.2181427149 |
| Directory | /workspace/0.chip_sival_flash_info_access/latest |
| Test location | /workspace/coverage/default/0.chip_sw_aes_enc_jitter_en.2053924547 |
| Short name | T3 |
| Test name | |
| Test status | |
| Simulation time | 2750680071 ps |
| CPU time | 259.95 seconds |
| Started | Aug 12 07:10:00 PM PDT 24 |
| Finished | Aug 12 07:14:22 PM PDT 24 |
| Peak memory | 609204 kb |
| Host | smart-3d1f128c-7416-4da1-9ae9-5e88c0b3ccc6 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=26_000_000 +en_jitter=1 +sw_build_device=sim_dv +sw_images=aes_smoketest:1:new_rules,test_rom:0 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2053 924547 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work space/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_aes_enc_jitter_en.2053924547 |
| Directory | /workspace/0.chip_sw_aes_enc_jitter_en/latest |
| Test location | /workspace/coverage/default/0.chip_sw_aes_enc_jitter_en_reduced_freq.796559473 |
| Short name | T294 |
| Test name | |
| Test status | |
| Simulation time | 3592812003 ps |
| CPU time | 304.59 seconds |
| Started | Aug 12 07:11:19 PM PDT 24 |
| Finished | Aug 12 07:16:24 PM PDT 24 |
| Peak memory | 609144 kb |
| Host | smart-8bb11173-5998-4a78-9896-0d808bde8c47 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=26_000_000 +en_jitter=1 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=aes_smoketest:1:new_rules, test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=796559473 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_aes_enc_jitter_en_reduced_freq.796559473 |
| Directory | /workspace/0.chip_sw_aes_enc_jitter_en_reduced_freq/latest |
| Test location | /workspace/coverage/default/0.chip_sw_aes_entropy.164634008 |
| Short name | T778 |
| Test name | |
| Test status | |
| Simulation time | 2885495784 ps |
| CPU time | 243.1 seconds |
| Started | Aug 12 07:08:42 PM PDT 24 |
| Finished | Aug 12 07:12:45 PM PDT 24 |
| Peak memory | 610076 kb |
| Host | smart-916e49f8-03c4-470b-89b7-1f4bb6c928dd |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=15_000_000 +sw_build_device=sim_dv +sw_images=aes_entropy_test:1:new_rules,test_rom:0 +cdc_instrumentation _enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=164634008 -ass ert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_aes_entropy.164634008 |
| Directory | /workspace/0.chip_sw_aes_entropy/latest |
| Test location | /workspace/coverage/default/0.chip_sw_aes_idle.3694634135 |
| Short name | T285 |
| Test name | |
| Test status | |
| Simulation time | 2427257342 ps |
| CPU time | 324.62 seconds |
| Started | Aug 12 07:09:53 PM PDT 24 |
| Finished | Aug 12 07:15:18 PM PDT 24 |
| Peak memory | 610112 kb |
| Host | smart-300fddb1-a014-4a9e-8c9c-3a56c9252773 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=25_000_000 +sw_build_device=sim_dv +sw_images=aes_idle_test:1:new_rules,test_rom:0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3694634135 -asser t nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag e/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_aes_idle.3694634135 |
| Directory | /workspace/0.chip_sw_aes_idle/latest |
| Test location | /workspace/coverage/default/0.chip_sw_aes_masking_off.2134093322 |
| Short name | T1261 |
| Test name | |
| Test status | |
| Simulation time | 2242865343 ps |
| CPU time | 316.17 seconds |
| Started | Aug 12 07:10:36 PM PDT 24 |
| Finished | Aug 12 07:15:53 PM PDT 24 |
| Peak memory | 609792 kb |
| Host | smart-af399f66-c23b-494f-8866-b65756cc84c1 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=aes_masking_off_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2134093322 -assert nopostproc +UVM_TESTNA ME=chip_base_test +UVM_TEST_SEQ=chip_sw_aes_masking_off_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_aes_masking_off.2134093322 |
| Directory | /workspace/0.chip_sw_aes_masking_off/latest |
| Test location | /workspace/coverage/default/0.chip_sw_aes_smoketest.2773890071 |
| Short name | T1105 |
| Test name | |
| Test status | |
| Simulation time | 3356443858 ps |
| CPU time | 251.08 seconds |
| Started | Aug 12 07:14:05 PM PDT 24 |
| Finished | Aug 12 07:18:17 PM PDT 24 |
| Peak memory | 610088 kb |
| Host | smart-806d6622-f09b-4d9a-8814-f8db99e8146e |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=aes_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2773890071 -assert nopostproc +UVM_TESTNAME=chip _base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_aes_smoketest.2773890071 |
| Directory | /workspace/0.chip_sw_aes_smoketest/latest |
| Test location | /workspace/coverage/default/0.chip_sw_alert_handler_entropy.1149321668 |
| Short name | T1099 |
| Test name | |
| Test status | |
| Simulation time | 3265480599 ps |
| CPU time | 290.1 seconds |
| Started | Aug 12 07:10:50 PM PDT 24 |
| Finished | Aug 12 07:15:41 PM PDT 24 |
| Peak memory | 610120 kb |
| Host | smart-68d4d4a9-b7e6-4c74-af01-cb35ca75a33a |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=alert_handler_entropy_test:1:new_rules,test_ro m:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=1149321668 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_alert_handler_entropy.1149321668 |
| Directory | /workspace/0.chip_sw_alert_handler_entropy/latest |
| Test location | /workspace/coverage/default/0.chip_sw_alert_handler_escalation.2820513669 |
| Short name | T1339 |
| Test name | |
| Test status | |
| Simulation time | 4739519790 ps |
| CPU time | 613.5 seconds |
| Started | Aug 12 07:10:34 PM PDT 24 |
| Finished | Aug 12 07:20:48 PM PDT 24 |
| Peak memory | 620040 kb |
| Host | smart-cc81047c-d60e-481f-84e6-7218c5f8af79 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=alert_handler_escalation_test:1:new_rules,test _rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb _random_seed=2820513669 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_alert_handler_escalation_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_alert_handler_escalation.2820513669 |
| Directory | /workspace/0.chip_sw_alert_handler_escalation/latest |
| Test location | /workspace/coverage/default/0.chip_sw_alert_handler_lpg_clkoff.1277959040 |
| Short name | T1437 |
| Test name | |
| Test status | |
| Simulation time | 8746410230 ps |
| CPU time | 1789.87 seconds |
| Started | Aug 12 07:11:34 PM PDT 24 |
| Finished | Aug 12 07:41:24 PM PDT 24 |
| Peak memory | 610660 kb |
| Host | smart-26811c43-fbad-4869-84bf-986ca2ec268c |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +sw_build_device=sim_dv +sw_images=alert_handler_lpg_clkoff_test:1:new_rules,test_r om:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r andom_seed=1277959040 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_alert_handler_lpg_clkoff_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_alert_handler_lpg_clkoff.1277959040 |
| Directory | /workspace/0.chip_sw_alert_handler_lpg_clkoff/latest |
| Test location | /workspace/coverage/default/0.chip_sw_alert_handler_lpg_reset_toggle.3456861873 |
| Short name | T1219 |
| Test name | |
| Test status | |
| Simulation time | 8213459432 ps |
| CPU time | 2087.88 seconds |
| Started | Aug 12 07:10:38 PM PDT 24 |
| Finished | Aug 12 07:45:27 PM PDT 24 |
| Peak memory | 610536 kb |
| Host | smart-a2b5cee9-65f5-42b0-9438-566295a56513 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +sw_build_device=sim_dv +sw_images=alert_handler_lpg_reset_toggle_test:1:new_rules, test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3456861873 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_alert_handler_shorten_ping_wait_cycle_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_alert_handler_lpg_reset_togg le.3456861873 |
| Directory | /workspace/0.chip_sw_alert_handler_lpg_reset_toggle/latest |
| Test location | /workspace/coverage/default/0.chip_sw_alert_handler_ping_ok.669139867 |
| Short name | T1337 |
| Test name | |
| Test status | |
| Simulation time | 8362997766 ps |
| CPU time | 1778.63 seconds |
| Started | Aug 12 07:10:47 PM PDT 24 |
| Finished | Aug 12 07:40:26 PM PDT 24 |
| Peak memory | 610400 kb |
| Host | smart-799488f9-0bd4-49a5-85fd-c6046e98030f |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=24000000 +sw_build_device=sim_dv +sw_images=alert_handler_ping_ok_test:1:new_rules,test_rom:0 +c dc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_s eed=669139867 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_alert_handler_ping_ok.669139867 |
| Directory | /workspace/0.chip_sw_alert_handler_ping_ok/latest |
| Test location | /workspace/coverage/default/0.chip_sw_alert_handler_ping_timeout.1841181001 |
| Short name | T1215 |
| Test name | |
| Test status | |
| Simulation time | 4050858600 ps |
| CPU time | 413.87 seconds |
| Started | Aug 12 07:09:58 PM PDT 24 |
| Finished | Aug 12 07:16:53 PM PDT 24 |
| Peak memory | 610268 kb |
| Host | smart-5c0c6084-9001-49aa-a966-f474848432d6 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=24000000 +sw_build_device=sim_dv +sw_images=alert_handler_ping_timeout_test:1:new_rules,test_rom :0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=1841181001 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_alert_handler_ping_timeout.1841181001 |
| Directory | /workspace/0.chip_sw_alert_handler_ping_timeout/latest |
| Test location | /workspace/coverage/default/0.chip_sw_alert_handler_reverse_ping_in_deep_sleep.135037427 |
| Short name | T84 |
| Test name | |
| Test status | |
| Simulation time | 256395583708 ps |
| CPU time | 13693.4 seconds |
| Started | Aug 12 07:08:05 PM PDT 24 |
| Finished | Aug 12 10:56:20 PM PDT 24 |
| Peak memory | 611292 kb |
| Host | smart-342668a9-b25d-4b04-8694-2f64e70d558b |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=300_000_000 +sw_build_device=sim_dv +sw_images=alert_handler_reverse_ping_in_deep_sleep_test:1:n ew_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=135037427 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tg l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_alert_handler_reverse_ping_in_deep_sleep.135037427 |
| Directory | /workspace/0.chip_sw_alert_handler_reverse_ping_in_deep_sleep/latest |
| Test location | /workspace/coverage/default/0.chip_sw_all_escalation_resets.3335347842 |
| Short name | T268 |
| Test name | |
| Test status | |
| Simulation time | 6087143336 ps |
| CPU time | 627.88 seconds |
| Started | Aug 12 07:08:18 PM PDT 24 |
| Finished | Aug 12 07:18:47 PM PDT 24 |
| Peak memory | 650468 kb |
| Host | smart-c97de664-e615-427c-8404-001629a6cf60 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 3335347842 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_all_escalation_resets.3335347842 |
| Directory | /workspace/0.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/0.chip_sw_aon_timer_irq.235082926 |
| Short name | T1335 |
| Test name | |
| Test status | |
| Simulation time | 3642076952 ps |
| CPU time | 476.16 seconds |
| Started | Aug 12 07:07:52 PM PDT 24 |
| Finished | Aug 12 07:15:48 PM PDT 24 |
| Peak memory | 610236 kb |
| Host | smart-877a28ac-0c4f-4831-b6e6-ea0268543b1f |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=aon_timer_irq_test:1:new_rules,test_rom:0 +cdc_instrumentati on_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=235082926 -a ssert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov erage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_aon_timer_irq.235082926 |
| Directory | /workspace/0.chip_sw_aon_timer_irq/latest |
| Test location | /workspace/coverage/default/0.chip_sw_aon_timer_sleep_wdog_sleep_pause.3955929779 |
| Short name | T1317 |
| Test name | |
| Test status | |
| Simulation time | 7398556604 ps |
| CPU time | 485.29 seconds |
| Started | Aug 12 07:08:50 PM PDT 24 |
| Finished | Aug 12 07:16:56 PM PDT 24 |
| Peak memory | 609924 kb |
| Host | smart-677e83ec-3087-4abf-965c-9d375ddbdf27 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=aon_timer_sleep_wdog_sleep_pause_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=3955929779 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_aon_timer_sleep_wdog_sleep_pause.3955929779 |
| Directory | /workspace/0.chip_sw_aon_timer_sleep_wdog_sleep_pause/latest |
| Test location | /workspace/coverage/default/0.chip_sw_aon_timer_smoketest.3965759622 |
| Short name | T1360 |
| Test name | |
| Test status | |
| Simulation time | 3521244812 ps |
| CPU time | 314.44 seconds |
| Started | Aug 12 07:14:02 PM PDT 24 |
| Finished | Aug 12 07:19:16 PM PDT 24 |
| Peak memory | 610140 kb |
| Host | smart-4dd169c5-8b91-4139-a318-623b5ffa2b1f |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=aon_timer_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3965759622 -assert nopostproc +UVM_TESTNAM E=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 0.chip_sw_aon_timer_smoketest.3965759622 |
| Directory | /workspace/0.chip_sw_aon_timer_smoketest/latest |
| Test location | /workspace/coverage/default/0.chip_sw_aon_timer_wdog_bite_reset.2917011286 |
| Short name | T1294 |
| Test name | |
| Test status | |
| Simulation time | 8968283296 ps |
| CPU time | 711.29 seconds |
| Started | Aug 12 07:09:07 PM PDT 24 |
| Finished | Aug 12 07:20:59 PM PDT 24 |
| Peak memory | 610992 kb |
| Host | smart-3531c6a8-2489-4a29-9d68-20bc04aeca11 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=aon_timer_wdog_bite_reset_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 2917011286 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_aon_timer_wdog_bite_reset.2917011286 |
| Directory | /workspace/0.chip_sw_aon_timer_wdog_bite_reset/latest |
| Test location | /workspace/coverage/default/0.chip_sw_aon_timer_wdog_lc_escalate.3757575794 |
| Short name | T1023 |
| Test name | |
| Test status | |
| Simulation time | 5485280680 ps |
| CPU time | 661.11 seconds |
| Started | Aug 12 07:07:48 PM PDT 24 |
| Finished | Aug 12 07:18:50 PM PDT 24 |
| Peak memory | 609772 kb |
| Host | smart-adfec71b-8761-47df-b4bc-268b405035a6 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=aon_timer_wdog_lc_escalate_test:1:new_rules,test_rom:0 +cdc_ instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed =3757575794 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_aon_timer_wdog_lc_escalate.3757575794 |
| Directory | /workspace/0.chip_sw_aon_timer_wdog_lc_escalate/latest |
| Test location | /workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_lc.876588768 |
| Short name | T1073 |
| Test name | |
| Test status | |
| Simulation time | 7482988860 ps |
| CPU time | 459.39 seconds |
| Started | Aug 12 07:08:02 PM PDT 24 |
| Finished | Aug 12 07:15:42 PM PDT 24 |
| Peak memory | 621600 kb |
| Host | smart-d5fee8f7-b99b-42eb-9c55-0a3aae555684 |
| User | root |
| Command | /workspace/default/simv +chip_clock_source=ChipClockSourceExternal48Mhz +sw_build_device=sim_dv +sw_images=clkmgr_external_clk_src_for_lc_test:1:new_r ules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim .tcl +ntb_random_seed=876588768 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_transition_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_clkmgr_external_clk_src_for_lc.876588768 |
| Directory | /workspace/0.chip_sw_clkmgr_external_clk_src_for_lc/latest |
| Test location | /workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_fast_rma.3345033908 |
| Short name | T1418 |
| Test name | |
| Test status | |
| Simulation time | 3998921556 ps |
| CPU time | 578.86 seconds |
| Started | Aug 12 07:09:47 PM PDT 24 |
| Finished | Aug 12 07:19:26 PM PDT 24 |
| Peak memory | 613544 kb |
| Host | smart-aea54629-2317-4c93-80fd-d0ccdaee0dbd |
| User | root |
| Command | /workspace/default/simv +chip_clock_source=ChipClockSourceExternal96Mhz +calibrate_usb_clk=1 +src_dec_state=DecLcStRma +sw_build_device=sim_dv +sw_ima ges=clkmgr_external_clk_src_for_sw_fast_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3345033908 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ =chip_sw_lc_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_c lkmgr_external_clk_src_for_sw_fast_rma.3345033908 |
| Directory | /workspace/0.chip_sw_clkmgr_external_clk_src_for_sw_fast_rma/latest |
| Test location | /workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0.3206839348 |
| Short name | T1146 |
| Test name | |
| Test status | |
| Simulation time | 3820382360 ps |
| CPU time | 599.27 seconds |
| Started | Aug 12 07:10:03 PM PDT 24 |
| Finished | Aug 12 07:20:02 PM PDT 24 |
| Peak memory | 613564 kb |
| Host | smart-7cb48184-0d9f-44b1-ab5a-e71661618fde |
| User | root |
| Command | /workspace/default/simv +chip_clock_source=ChipClockSourceExternal96Mhz +calibrate_usb_clk=1 +src_dec_state=DecLcStTestUnlocked0 +sw_build_device=sim_ dv +sw_images=clkmgr_external_clk_src_for_sw_fast_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3206839348 -assert nopostproc +UVM_TESTNAME=chip_base_test +UV M_TEST_SEQ=chip_sw_lc_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0 .chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0.3206839348 |
| Directory | /workspace/0.chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0/latest |
| Test location | /workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_slow_dev.2889610785 |
| Short name | T1078 |
| Test name | |
| Test status | |
| Simulation time | 4153926188 ps |
| CPU time | 570.45 seconds |
| Started | Aug 12 07:10:36 PM PDT 24 |
| Finished | Aug 12 07:20:07 PM PDT 24 |
| Peak memory | 613324 kb |
| Host | smart-aef521cb-33fa-4b3c-99a7-aa90d7ee7665 |
| User | root |
| Command | /workspace/default/simv +chip_clock_source=ChipClockSourceExternal48Mhz +calibrate_usb_clk=1 +src_dec_state=DecLcStDev +sw_build_device=sim_dv +sw_ima ges=clkmgr_external_clk_src_for_sw_slow_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2889610785 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ =chip_sw_lc_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_c lkmgr_external_clk_src_for_sw_slow_dev.2889610785 |
| Directory | /workspace/0.chip_sw_clkmgr_external_clk_src_for_sw_slow_dev/latest |
| Test location | /workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_slow_rma.1777067890 |
| Short name | T1324 |
| Test name | |
| Test status | |
| Simulation time | 5062385744 ps |
| CPU time | 674.91 seconds |
| Started | Aug 12 07:11:03 PM PDT 24 |
| Finished | Aug 12 07:22:19 PM PDT 24 |
| Peak memory | 613280 kb |
| Host | smart-c376925d-510c-4e02-84b2-21f8925c2a70 |
| User | root |
| Command | /workspace/default/simv +chip_clock_source=ChipClockSourceExternal48Mhz +calibrate_usb_clk=1 +src_dec_state=DecLcStRma +sw_build_device=sim_dv +sw_ima ges=clkmgr_external_clk_src_for_sw_slow_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1777067890 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ =chip_sw_lc_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_c lkmgr_external_clk_src_for_sw_slow_rma.1777067890 |
| Directory | /workspace/0.chip_sw_clkmgr_external_clk_src_for_sw_slow_rma/latest |
| Test location | /workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0.1631099847 |
| Short name | T1247 |
| Test name | |
| Test status | |
| Simulation time | 5213156480 ps |
| CPU time | 715.52 seconds |
| Started | Aug 12 07:09:07 PM PDT 24 |
| Finished | Aug 12 07:21:02 PM PDT 24 |
| Peak memory | 613356 kb |
| Host | smart-ca887f61-2b01-4424-bdc0-f84ae493f552 |
| User | root |
| Command | /workspace/default/simv +chip_clock_source=ChipClockSourceExternal48Mhz +calibrate_usb_clk=1 +src_dec_state=DecLcStTestUnlocked0 +sw_build_device=sim_ dv +sw_images=clkmgr_external_clk_src_for_sw_slow_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1631099847 -assert nopostproc +UVM_TESTNAME=chip_base_test +UV M_TEST_SEQ=chip_sw_lc_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0 .chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0.1631099847 |
| Directory | /workspace/0.chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0/latest |
| Test location | /workspace/coverage/default/0.chip_sw_clkmgr_jitter.4012102949 |
| Short name | T1257 |
| Test name | |
| Test status | |
| Simulation time | 2461362778 ps |
| CPU time | 205.15 seconds |
| Started | Aug 12 07:11:14 PM PDT 24 |
| Finished | Aug 12 07:14:39 PM PDT 24 |
| Peak memory | 608804 kb |
| Host | smart-6865ae5d-debb-472f-8e7f-472c9000ccec |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=clkmgr_jitter_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4012102949 -assert nopostproc +UVM_TESTNAME =chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 0.chip_sw_clkmgr_jitter.4012102949 |
| Directory | /workspace/0.chip_sw_clkmgr_jitter/latest |
| Test location | /workspace/coverage/default/0.chip_sw_clkmgr_jitter_frequency.3704453335 |
| Short name | T1375 |
| Test name | |
| Test status | |
| Simulation time | 3699611026 ps |
| CPU time | 429.43 seconds |
| Started | Aug 12 07:09:15 PM PDT 24 |
| Finished | Aug 12 07:16:25 PM PDT 24 |
| Peak memory | 609924 kb |
| Host | smart-0b17e1df-003e-45e6-b4c6-24ebf966b10c |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=clkmgr_jitter_frequency_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3704453335 -assert nopostproc +UV M_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -c m_log /dev/null -cm_name 0.chip_sw_clkmgr_jitter_frequency.3704453335 |
| Directory | /workspace/0.chip_sw_clkmgr_jitter_frequency/latest |
| Test location | /workspace/coverage/default/0.chip_sw_clkmgr_jitter_reduced_freq.2621181812 |
| Short name | T1082 |
| Test name | |
| Test status | |
| Simulation time | 2754061298 ps |
| CPU time | 236.87 seconds |
| Started | Aug 12 07:09:32 PM PDT 24 |
| Finished | Aug 12 07:13:29 PM PDT 24 |
| Peak memory | 610104 kb |
| Host | smart-e1f03d09-6051-47f3-b54b-c5aa27f978c3 |
| User | root |
| Command | /workspace/default/simv +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=clkmgr_jitter_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2621181812 -assert nop ostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def ault.vdb -cm_log /dev/null -cm_name 0.chip_sw_clkmgr_jitter_reduced_freq.2621181812 |
| Directory | /workspace/0.chip_sw_clkmgr_jitter_reduced_freq/latest |
| Test location | /workspace/coverage/default/0.chip_sw_clkmgr_off_aes_trans.1318788889 |
| Short name | T432 |
| Test name | |
| Test status | |
| Simulation time | 4495197200 ps |
| CPU time | 419.59 seconds |
| Started | Aug 12 07:08:16 PM PDT 24 |
| Finished | Aug 12 07:15:15 PM PDT 24 |
| Peak memory | 610544 kb |
| Host | smart-90268849-5b3b-4765-8463-ce9e55ff2336 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=clkmgr_off_aes_trans_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1318788889 -assert nopostproc +UVM_T ESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l og /dev/null -cm_name 0.chip_sw_clkmgr_off_aes_trans.1318788889 |
| Directory | /workspace/0.chip_sw_clkmgr_off_aes_trans/latest |
| Test location | /workspace/coverage/default/0.chip_sw_clkmgr_off_hmac_trans.3216750582 |
| Short name | T1364 |
| Test name | |
| Test status | |
| Simulation time | 3936826336 ps |
| CPU time | 470.89 seconds |
| Started | Aug 12 07:10:36 PM PDT 24 |
| Finished | Aug 12 07:18:28 PM PDT 24 |
| Peak memory | 610516 kb |
| Host | smart-c188daa0-2265-4c68-8e93-4f6af49f3499 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=clkmgr_off_hmac_trans_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3216750582 -assert nopostproc +UVM_ TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_ log /dev/null -cm_name 0.chip_sw_clkmgr_off_hmac_trans.3216750582 |
| Directory | /workspace/0.chip_sw_clkmgr_off_hmac_trans/latest |
| Test location | /workspace/coverage/default/0.chip_sw_clkmgr_off_kmac_trans.633907143 |
| Short name | T985 |
| Test name | |
| Test status | |
| Simulation time | 4166935726 ps |
| CPU time | 730.63 seconds |
| Started | Aug 12 07:09:42 PM PDT 24 |
| Finished | Aug 12 07:21:53 PM PDT 24 |
| Peak memory | 609776 kb |
| Host | smart-9eda1aac-4d05-4132-9881-4a0dc0f53f85 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=clkmgr_off_kmac_trans_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=633907143 -assert nopostproc +UVM_T ESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l og /dev/null -cm_name 0.chip_sw_clkmgr_off_kmac_trans.633907143 |
| Directory | /workspace/0.chip_sw_clkmgr_off_kmac_trans/latest |
| Test location | /workspace/coverage/default/0.chip_sw_clkmgr_off_otbn_trans.2181804990 |
| Short name | T779 |
| Test name | |
| Test status | |
| Simulation time | 6062023448 ps |
| CPU time | 567.7 seconds |
| Started | Aug 12 07:08:41 PM PDT 24 |
| Finished | Aug 12 07:18:09 PM PDT 24 |
| Peak memory | 609960 kb |
| Host | smart-8442ae48-1571-4680-89eb-dea5115abcf8 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=clkmgr_off_otbn_trans_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2181804990 -assert nopostproc +UVM_ TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_ log /dev/null -cm_name 0.chip_sw_clkmgr_off_otbn_trans.2181804990 |
| Directory | /workspace/0.chip_sw_clkmgr_off_otbn_trans/latest |
| Test location | /workspace/coverage/default/0.chip_sw_clkmgr_off_peri.2983700591 |
| Short name | T1124 |
| Test name | |
| Test status | |
| Simulation time | 10258936088 ps |
| CPU time | 1637.92 seconds |
| Started | Aug 12 07:09:25 PM PDT 24 |
| Finished | Aug 12 07:36:43 PM PDT 24 |
| Peak memory | 610888 kb |
| Host | smart-fe31a035-378a-4ec5-9238-36eb261338ef |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=30_000_000 +sw_build_device=sim_dv +sw_images=clkmgr_off_peri_test:1:new_rules,test_rom:0 +cdc_instrumenta tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2983700591 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/ coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_clkmgr_off_peri.2983700591 |
| Directory | /workspace/0.chip_sw_clkmgr_off_peri/latest |
| Test location | /workspace/coverage/default/0.chip_sw_clkmgr_reset_frequency.617582392 |
| Short name | T1062 |
| Test name | |
| Test status | |
| Simulation time | 2800361742 ps |
| CPU time | 317.96 seconds |
| Started | Aug 12 07:13:28 PM PDT 24 |
| Finished | Aug 12 07:18:48 PM PDT 24 |
| Peak memory | 609044 kb |
| Host | smart-3634439f-25ea-4c7a-91a9-bb2181cc805e |
| User | root |
| Command | /workspace/default/simv +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=clkmgr_reset_frequency_test:1:new_rules,test_rom:0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=617582392 -as sert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove rage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_clkmgr_reset_frequency.617582392 |
| Directory | /workspace/0.chip_sw_clkmgr_reset_frequency/latest |
| Test location | /workspace/coverage/default/0.chip_sw_clkmgr_sleep_frequency.801964356 |
| Short name | T1293 |
| Test name | |
| Test status | |
| Simulation time | 4476271728 ps |
| CPU time | 863.51 seconds |
| Started | Aug 12 07:15:12 PM PDT 24 |
| Finished | Aug 12 07:29:37 PM PDT 24 |
| Peak memory | 610672 kb |
| Host | smart-4d3cae4a-5c5c-4e17-86b4-116b748720f8 |
| User | root |
| Command | /workspace/default/simv +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=clkmgr_sleep_frequency_test:1:new_rules,test_rom:0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=801964356 -as sert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove rage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_clkmgr_sleep_frequency.801964356 |
| Directory | /workspace/0.chip_sw_clkmgr_sleep_frequency/latest |
| Test location | /workspace/coverage/default/0.chip_sw_clkmgr_smoketest.2972747711 |
| Short name | T1259 |
| Test name | |
| Test status | |
| Simulation time | 2355819408 ps |
| CPU time | 238.94 seconds |
| Started | Aug 12 07:10:15 PM PDT 24 |
| Finished | Aug 12 07:14:15 PM PDT 24 |
| Peak memory | 609700 kb |
| Host | smart-8a3c74aa-d702-4fe8-a558-013c5d750013 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=clkmgr_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2972747711 -assert nopostproc +UVM_TESTNAME=c hip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n ull -cm_name 0.chip_sw_clkmgr_smoketest.2972747711 |
| Directory | /workspace/0.chip_sw_clkmgr_smoketest/latest |
| Test location | /workspace/coverage/default/0.chip_sw_coremark.2654440069 |
| Short name | T984 |
| Test name | |
| Test status | |
| Simulation time | 71732611344 ps |
| CPU time | 13374.2 seconds |
| Started | Aug 12 07:11:45 PM PDT 24 |
| Finished | Aug 12 10:54:41 PM PDT 24 |
| Peak memory | 610792 kb |
| Host | smart-6cb6f977-c139-4d5e-8a0e-79f82ca8e2a1 |
| User | root |
| Command | /workspace/default/simv +en_uart_logger=1 +sw_test_timeout_ns=200_000_000 +sw_build_device=sim_dv +sw_images=coremark_test:1:new_rules,test_rom:0 +cdc _instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see d=2654440069 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_coremark.2654440069 |
| Directory | /workspace/0.chip_sw_coremark/latest |
| Test location | /workspace/coverage/default/0.chip_sw_csrng_edn_concurrency.2431169829 |
| Short name | T263 |
| Test name | |
| Test status | |
| Simulation time | 25148011100 ps |
| CPU time | 5851.03 seconds |
| Started | Aug 12 07:11:35 PM PDT 24 |
| Finished | Aug 12 08:49:07 PM PDT 24 |
| Peak memory | 610792 kb |
| Host | smart-a98d9bb9-4fa1-4d10-863e-1ba29a83460f |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=140_000_000 +rng_srate_value_min=15 +rng_srate_value_max=20 +sw_build_device=sim_dv +sw_images=csrng_edn_c oncurrency_test:1:new_rules,test_rom:0 +accelerate_cold_power_up_time=3 +accelerate_regulators_power_up_time=2 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2431169829 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd b -cm_log /dev/null -cm_name 0.chip_sw_csrng_edn_concurrency.2431169829 |
| Directory | /workspace/0.chip_sw_csrng_edn_concurrency/latest |
| Test location | /workspace/coverage/default/0.chip_sw_csrng_edn_concurrency_reduced_freq.4037813400 |
| Short name | T96 |
| Test name | |
| Test status | |
| Simulation time | 9933692252 ps |
| CPU time | 1759.36 seconds |
| Started | Aug 12 07:10:51 PM PDT 24 |
| Finished | Aug 12 07:40:10 PM PDT 24 |
| Peak memory | 610520 kb |
| Host | smart-db82da49-7ce7-4e5b-b9ea-c772bbd721e4 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=360_000_000 +rng_srate_value_min=15 +rng_srate_value_max=20 +cal_sys_clk_70mhz=1 +en_jitter=1 +sw_build_de vice=sim_dv +sw_images=csrng_edn_concurrency_test:1:new_rules,test_rom:0 +accelerate_cold_power_up_time=3 +accelerate_regulators_power_up_time=2 + cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_ seed=4037813400 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_csrng_edn_concurrency_reduced_freq.4037813400 |
| Directory | /workspace/0.chip_sw_csrng_edn_concurrency_reduced_freq/latest |
| Test location | /workspace/coverage/default/0.chip_sw_csrng_fuse_en_sw_app_read_test.2065099475 |
| Short name | T1210 |
| Test name | |
| Test status | |
| Simulation time | 3700599086 ps |
| CPU time | 391.03 seconds |
| Started | Aug 12 07:08:39 PM PDT 24 |
| Finished | Aug 12 07:15:10 PM PDT 24 |
| Peak memory | 609980 kb |
| Host | smart-8218faf6-adc7-44d3-a23a-1993544432fe |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=15_000_000 +sw_build_device=sim_dv +sw_images=csrng_fuse_en_sw_app_read:1:new_rules,test_rom:0 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20650 99475 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_entropy_src_fuse_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_csrng_fuse_en_sw_app_read_test.2065099475 |
| Directory | /workspace/0.chip_sw_csrng_fuse_en_sw_app_read_test/latest |
| Test location | /workspace/coverage/default/0.chip_sw_csrng_kat_test.585668967 |
| Short name | T1049 |
| Test name | |
| Test status | |
| Simulation time | 2760682176 ps |
| CPU time | 269.79 seconds |
| Started | Aug 12 07:11:05 PM PDT 24 |
| Finished | Aug 12 07:15:37 PM PDT 24 |
| Peak memory | 610048 kb |
| Host | smart-38c26d6d-b54b-4ec9-8d37-afea89fc46a2 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=csrng_kat_test:1:new_rules,test_rom:0 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=585668967 -asser t nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag e/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_csrng_kat_test.585668967 |
| Directory | /workspace/0.chip_sw_csrng_kat_test/latest |
| Test location | /workspace/coverage/default/0.chip_sw_csrng_lc_hw_debug_en_test.2521689046 |
| Short name | T1403 |
| Test name | |
| Test status | |
| Simulation time | 5150092212 ps |
| CPU time | 658 seconds |
| Started | Aug 12 07:12:28 PM PDT 24 |
| Finished | Aug 12 07:23:27 PM PDT 24 |
| Peak memory | 611764 kb |
| Host | smart-889ef58b-5821-4d7e-88f0-bbb170aa235a |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=15_000_000 +rng_srate_value_min=15 +use_otp_image=OtpTypeLcStTestUnlocked0 +sw_build_device=sim_dv +sw_ima ges=csrng_lc_hw_debug_en_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2521689046 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_csrng_ lc_hw_debug_en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_csr ng_lc_hw_debug_en_test.2521689046 |
| Directory | /workspace/0.chip_sw_csrng_lc_hw_debug_en_test/latest |
| Test location | /workspace/coverage/default/0.chip_sw_csrng_smoketest.952990817 |
| Short name | T981 |
| Test name | |
| Test status | |
| Simulation time | 2707233090 ps |
| CPU time | 274.7 seconds |
| Started | Aug 12 07:13:39 PM PDT 24 |
| Finished | Aug 12 07:18:13 PM PDT 24 |
| Peak memory | 610136 kb |
| Host | smart-ad2bd24b-21fc-442d-885c-51141ca961c5 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=csrng_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=952990817 -assert nopostproc +UVM_TESTNAME=chi p_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul l -cm_name 0.chip_sw_csrng_smoketest.952990817 |
| Directory | /workspace/0.chip_sw_csrng_smoketest/latest |
| Test location | /workspace/coverage/default/0.chip_sw_data_integrity_escalation.942006967 |
| Short name | T1270 |
| Test name | |
| Test status | |
| Simulation time | 6693079100 ps |
| CPU time | 918.37 seconds |
| Started | Aug 12 07:07:00 PM PDT 24 |
| Finished | Aug 12 07:22:19 PM PDT 24 |
| Peak memory | 611520 kb |
| Host | smart-a01bb69d-fc5a-4432-a1b6-5af504c311ab |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=data_integrity_escalation_reset_test:1:new_rules,test_ro m:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=942006967 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_data_integrity_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_data_integrity_escalation.942006967 |
| Directory | /workspace/0.chip_sw_data_integrity_escalation/latest |
| Test location | /workspace/coverage/default/0.chip_sw_edn_auto_mode.2953382009 |
| Short name | T1414 |
| Test name | |
| Test status | |
| Simulation time | 4841879780 ps |
| CPU time | 1291.14 seconds |
| Started | Aug 12 07:10:41 PM PDT 24 |
| Finished | Aug 12 07:32:13 PM PDT 24 |
| Peak memory | 610660 kb |
| Host | smart-03332fcf-9108-4b5a-a5f4-548e0df852a7 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +rng_srate_value=5 +sw_build_device=sim_dv +sw_images=edn_auto_mode:1:new_rules,test_rom:0 +acc elerate_cold_power_up_time=3 +accelerate_regulators_power_up_time=2 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2953382009 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ =chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_edn_ auto_mode.2953382009 |
| Directory | /workspace/0.chip_sw_edn_auto_mode/latest |
| Test location | /workspace/coverage/default/0.chip_sw_edn_entropy_reqs.2988891468 |
| Short name | T1054 |
| Test name | |
| Test status | |
| Simulation time | 6108394736 ps |
| CPU time | 1071.15 seconds |
| Started | Aug 12 07:08:58 PM PDT 24 |
| Finished | Aug 12 07:26:50 PM PDT 24 |
| Peak memory | 610068 kb |
| Host | smart-6fcf7b8e-44e4-41fa-98f6-fb382608c653 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=15000000 +rng_srate_value_min=15 +rng_srate_value_max=30 +sw_build_device=sim_dv +sw_images=entropy_src_ed n_reqs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2988891468 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_edn_entropy_reqs.2988891468 |
| Directory | /workspace/0.chip_sw_edn_entropy_reqs/latest |
| Test location | /workspace/coverage/default/0.chip_sw_edn_entropy_reqs_jitter.2632324156 |
| Short name | T461 |
| Test name | |
| Test status | |
| Simulation time | 7523232175 ps |
| CPU time | 1250.52 seconds |
| Started | Aug 12 07:10:55 PM PDT 24 |
| Finished | Aug 12 07:31:46 PM PDT 24 |
| Peak memory | 611324 kb |
| Host | smart-459b5f48-90e5-40d6-b9f5-1b4ba6c5b6a3 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=15000000 +rng_srate_value_min=15 +rng_srate_value_max=30 +en_jitter=1 +sw_build_device=sim_dv +sw_images=e ntropy_src_edn_reqs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2632324156 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_edn_entropy_reqs_jitter.2632324156 |
| Directory | /workspace/0.chip_sw_edn_entropy_reqs_jitter/latest |
| Test location | /workspace/coverage/default/0.chip_sw_edn_kat.2649889833 |
| Short name | T1208 |
| Test name | |
| Test status | |
| Simulation time | 3543966348 ps |
| CPU time | 620.54 seconds |
| Started | Aug 12 07:11:22 PM PDT 24 |
| Finished | Aug 12 07:21:43 PM PDT 24 |
| Peak memory | 617020 kb |
| Host | smart-2e310ffb-7071-4722-91b3-b46fdc0afdd4 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +rng_srate_value=5 +disable_assert_edn_output_diff_from_prev=1 +sw_build_device=sim_dv +sw_imag es=edn_kat:1:new_rules,test_rom:0 +accelerate_cold_power_up_time=3 +accelerate_regulators_power_up_time=2 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2649889833 -assert nopostproc +UVM _TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm _log /dev/null -cm_name 0.chip_sw_edn_kat.2649889833 |
| Directory | /workspace/0.chip_sw_edn_kat/latest |
| Test location | /workspace/coverage/default/0.chip_sw_edn_sw_mode.1565238666 |
| Short name | T1252 |
| Test name | |
| Test status | |
| Simulation time | 8518886476 ps |
| CPU time | 2031.13 seconds |
| Started | Aug 12 07:08:09 PM PDT 24 |
| Finished | Aug 12 07:42:01 PM PDT 24 |
| Peak memory | 610452 kb |
| Host | smart-efadeab7-3bda-41cf-aee3-bc9419855941 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=edn_sw_mode:1:new_rules,test_rom:0 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1565238666 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/ default.vdb -cm_log /dev/null -cm_name 0.chip_sw_edn_sw_mode.1565238666 |
| Directory | /workspace/0.chip_sw_edn_sw_mode/latest |
| Test location | /workspace/coverage/default/0.chip_sw_entropy_src_ast_rng_req.1578453309 |
| Short name | T1157 |
| Test name | |
| Test status | |
| Simulation time | 2521382248 ps |
| CPU time | 166.06 seconds |
| Started | Aug 12 07:10:15 PM PDT 24 |
| Finished | Aug 12 07:13:01 PM PDT 24 |
| Peak memory | 610132 kb |
| Host | smart-37657a6a-ec9e-40d1-8da7-354ee56e3f2a |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=15_000_000 +sw_build_device=sim_dv +sw_images=entropy_src_ast_rng_req_test:1:new_rules,test_rom:0 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15 78453309 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_entropy_src_ast_rng_req.1578453309 |
| Directory | /workspace/0.chip_sw_entropy_src_ast_rng_req/latest |
| Test location | /workspace/coverage/default/0.chip_sw_entropy_src_csrng.2156660045 |
| Short name | T343 |
| Test name | |
| Test status | |
| Simulation time | 6223189276 ps |
| CPU time | 1502.93 seconds |
| Started | Aug 12 07:10:30 PM PDT 24 |
| Finished | Aug 12 07:35:33 PM PDT 24 |
| Peak memory | 610704 kb |
| Host | smart-3136b24e-da45-4abf-8915-3e4beb58ab34 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=50_000_000 +rng_srate_value_min=15 +rng_srate_value_max=30 +sw_build_device=sim_dv +sw_images=entropy_src_ csrng_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2156660045 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_entropy_src_csrng.2156660045 |
| Directory | /workspace/0.chip_sw_entropy_src_csrng/latest |
| Test location | /workspace/coverage/default/0.chip_sw_entropy_src_kat_test.3773602220 |
| Short name | T1212 |
| Test name | |
| Test status | |
| Simulation time | 2172060052 ps |
| CPU time | 248.28 seconds |
| Started | Aug 12 07:10:16 PM PDT 24 |
| Finished | Aug 12 07:14:25 PM PDT 24 |
| Peak memory | 609860 kb |
| Host | smart-7e7d4e4b-d37d-4c6c-bb6b-222ca6717fd8 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=entropy_src_kat_test:1:new_rules,test_rom:0 +cdc_instrumenta tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3773602220 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/ coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_entropy_src_kat_test.3773602220 |
| Directory | /workspace/0.chip_sw_entropy_src_kat_test/latest |
| Test location | /workspace/coverage/default/0.chip_sw_entropy_src_smoketest.2516389177 |
| Short name | T1084 |
| Test name | |
| Test status | |
| Simulation time | 4072473684 ps |
| CPU time | 623.21 seconds |
| Started | Aug 12 07:11:06 PM PDT 24 |
| Finished | Aug 12 07:21:29 PM PDT 24 |
| Peak memory | 610152 kb |
| Host | smart-db173be8-25c1-464b-ac5f-6bb711eee837 |
| User | root |
| Command | /workspace/default/simv +rng_srate_value_min=15 +rng_srate_value_max=30 +sw_build_device=sim_dv +sw_images=entropy_src_smoketest:1:new_rules,test_rom: 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand om_seed=2516389177 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_entropy_src_smoketest.2516389177 |
| Directory | /workspace/0.chip_sw_entropy_src_smoketest/latest |
| Test location | /workspace/coverage/default/0.chip_sw_example_concurrency.3650581348 |
| Short name | T1302 |
| Test name | |
| Test status | |
| Simulation time | 2812509720 ps |
| CPU time | 306.65 seconds |
| Started | Aug 12 07:08:31 PM PDT 24 |
| Finished | Aug 12 07:13:40 PM PDT 24 |
| Peak memory | 609804 kb |
| Host | smart-eb865081-ae57-47f7-bdb1-4a722c14445b |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=example_concurrency_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3650581348 -assert nopostproc +UVM_TE STNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_lo g /dev/null -cm_name 0.chip_sw_example_concurrency.3650581348 |
| Directory | /workspace/0.chip_sw_example_concurrency/latest |
| Test location | /workspace/coverage/default/0.chip_sw_example_flash.3340727243 |
| Short name | T1267 |
| Test name | |
| Test status | |
| Simulation time | 2321084856 ps |
| CPU time | 176.31 seconds |
| Started | Aug 12 07:06:36 PM PDT 24 |
| Finished | Aug 12 07:09:33 PM PDT 24 |
| Peak memory | 609736 kb |
| Host | smart-ba97f9da-2d3a-41dc-8a73-bf14048d4286 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=example_test_from_flash:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3340727243 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_example_flash.3340727243 |
| Directory | /workspace/0.chip_sw_example_flash/latest |
| Test location | /workspace/coverage/default/0.chip_sw_example_manufacturer.3283601336 |
| Short name | T1154 |
| Test name | |
| Test status | |
| Simulation time | 2807767260 ps |
| CPU time | 241.02 seconds |
| Started | Aug 12 07:09:56 PM PDT 24 |
| Finished | Aug 12 07:13:58 PM PDT 24 |
| Peak memory | 609828 kb |
| Host | smart-221c9cdc-5e95-4477-8f37-c55367c69b7c |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=example_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3283601336 -assert nopostproc +UVM_TESTNAME=chip_ base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_example_manufacturer.3283601336 |
| Directory | /workspace/0.chip_sw_example_manufacturer/latest |
| Test location | /workspace/coverage/default/0.chip_sw_example_rom.557920459 |
| Short name | T997 |
| Test name | |
| Test status | |
| Simulation time | 1907215282 ps |
| CPU time | 120.19 seconds |
| Started | Aug 12 07:08:18 PM PDT 24 |
| Finished | Aug 12 07:10:19 PM PDT 24 |
| Peak memory | 609348 kb |
| Host | smart-78de9469-a1fa-4996-9e7d-e2e6583b415f |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=example_test_from_rom:0:test_in_rom:new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=557920459 -assert nopostproc +UVM_TESTN AME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log / dev/null -cm_name 0.chip_sw_example_rom.557920459 |
| Directory | /workspace/0.chip_sw_example_rom/latest |
| Test location | /workspace/coverage/default/0.chip_sw_exit_test_unlocked_bootstrap.3071571658 |
| Short name | T165 |
| Test name | |
| Test status | |
| Simulation time | 57879427466 ps |
| CPU time | 10584.5 seconds |
| Started | Aug 12 07:09:48 PM PDT 24 |
| Finished | Aug 12 10:06:14 PM PDT 24 |
| Peak memory | 625224 kb |
| Host | smart-40fb414e-4d38-40d3-9e84-1bf5a6980455 |
| User | root |
| Command | /workspace/default/simv +flash_program_latency=5 +sw_test_timeout_ns=150_000_000 +sw_build_device=sim_dv +sw_images=exit_test_unlocked_bootstrap:1:new _rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/s im.tcl +ntb_random_seed=3071571658 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_exit_test_unlocked_bootstrap_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_exit_test_unlocked_bootstrap.3071571658 |
| Directory | /workspace/0.chip_sw_exit_test_unlocked_bootstrap/latest |
| Test location | /workspace/coverage/default/0.chip_sw_flash_crash_alert.1095047403 |
| Short name | T320 |
| Test name | |
| Test status | |
| Simulation time | 5311691952 ps |
| CPU time | 668.19 seconds |
| Started | Aug 12 07:10:56 PM PDT 24 |
| Finished | Aug 12 07:22:04 PM PDT 24 |
| Peak memory | 611252 kb |
| Host | smart-a2df496a-bffa-4176-8bb9-cd9908a0fad0 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=8_000_000 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1: new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tool s/sim.tcl +ntb_random_seed=1095047403 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_flash_host_gnt_err_inj_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_flash_crash_alert.1095047403 |
| Directory | /workspace/0.chip_sw_flash_crash_alert/latest |
| Test location | /workspace/coverage/default/0.chip_sw_flash_ctrl_access.3781987272 |
| Short name | T1164 |
| Test name | |
| Test status | |
| Simulation time | 4961981208 ps |
| CPU time | 1109.17 seconds |
| Started | Aug 12 07:06:34 PM PDT 24 |
| Finished | Aug 12 07:25:04 PM PDT 24 |
| Peak memory | 609756 kb |
| Host | smart-96c0b850-faf9-4fc2-9912-372f9b670975 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=flash_ctrl_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3781987272 -assert nopostproc +UVM_TESTNAME=ch ip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu ll -cm_name 0.chip_sw_flash_ctrl_access.3781987272 |
| Directory | /workspace/0.chip_sw_flash_ctrl_access/latest |
| Test location | /workspace/coverage/default/0.chip_sw_flash_ctrl_access_jitter_en.1454696073 |
| Short name | T1141 |
| Test name | |
| Test status | |
| Simulation time | 6140877084 ps |
| CPU time | 1136.4 seconds |
| Started | Aug 12 07:07:41 PM PDT 24 |
| Finished | Aug 12 07:26:38 PM PDT 24 |
| Peak memory | 610544 kb |
| Host | smart-558c2009-a02d-4bc8-8ca0-a5d907d2f040 |
| User | root |
| Command | /workspace/default/simv +en_jitter=1 +sw_build_device=sim_dv +sw_images=flash_ctrl_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1454696073 -assert nopostproc +UV M_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -c m_log /dev/null -cm_name 0.chip_sw_flash_ctrl_access_jitter_en.1454696073 |
| Directory | /workspace/0.chip_sw_flash_ctrl_access_jitter_en/latest |
| Test location | /workspace/coverage/default/0.chip_sw_flash_ctrl_access_jitter_en_reduced_freq.331025045 |
| Short name | T1410 |
| Test name | |
| Test status | |
| Simulation time | 7233855851 ps |
| CPU time | 917.61 seconds |
| Started | Aug 12 07:08:47 PM PDT 24 |
| Finished | Aug 12 07:24:05 PM PDT 24 |
| Peak memory | 610624 kb |
| Host | smart-9ca6cdf9-7082-449e-8a65-191b4d67f20b |
| User | root |
| Command | /workspace/default/simv +en_jitter=1 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=flash_ctrl_test:1:new_rules,test_rom:0 +cdc_instrumentati on_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=331025045 -a ssert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov erage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_flash_ctrl_access_jitter_en_reduced_freq.331025045 |
| Directory | /workspace/0.chip_sw_flash_ctrl_access_jitter_en_reduced_freq/latest |
| Test location | /workspace/coverage/default/0.chip_sw_flash_ctrl_clock_freqs.3533475439 |
| Short name | T1340 |
| Test name | |
| Test status | |
| Simulation time | 5633685460 ps |
| CPU time | 1014.81 seconds |
| Started | Aug 12 07:06:11 PM PDT 24 |
| Finished | Aug 12 07:23:06 PM PDT 24 |
| Peak memory | 609792 kb |
| Host | smart-f9d76bdb-2322-404a-9821-a2f947d15106 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=flash_ctrl_clock_freqs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3533475439 -assert nopostproc +UVM _TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm _log /dev/null -cm_name 0.chip_sw_flash_ctrl_clock_freqs.3533475439 |
| Directory | /workspace/0.chip_sw_flash_ctrl_clock_freqs/latest |
| Test location | /workspace/coverage/default/0.chip_sw_flash_ctrl_idle_low_power.2080915550 |
| Short name | T1305 |
| Test name | |
| Test status | |
| Simulation time | 2854573856 ps |
| CPU time | 428.54 seconds |
| Started | Aug 12 07:09:41 PM PDT 24 |
| Finished | Aug 12 07:16:49 PM PDT 24 |
| Peak memory | 610012 kb |
| Host | smart-ffca0d5f-2683-4c71-99ee-76defab1e444 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=flash_ctrl_idle_low_power_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2080915550 -assert nopostproc + UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_flash_ctrl_idle_low_power.2080915550 |
| Directory | /workspace/0.chip_sw_flash_ctrl_idle_low_power/latest |
| Test location | /workspace/coverage/default/0.chip_sw_flash_ctrl_lc_rw_en.467486494 |
| Short name | T243 |
| Test name | |
| Test status | |
| Simulation time | 4082309432 ps |
| CPU time | 405.66 seconds |
| Started | Aug 12 07:09:09 PM PDT 24 |
| Finished | Aug 12 07:15:56 PM PDT 24 |
| Peak memory | 610944 kb |
| Host | smart-06c51951-deb5-41ee-ab37-89f3110ffdb1 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=flash_ctrl_lc_rw_en_test:1:new_rules,test_rom:0 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=46 7486494 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_flash_ctrl_lc_rw_en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_flash_ctrl_lc_rw_en.467486494 |
| Directory | /workspace/0.chip_sw_flash_ctrl_lc_rw_en/latest |
| Test location | /workspace/coverage/default/0.chip_sw_flash_ctrl_mem_protection.1272396235 |
| Short name | T1341 |
| Test name | |
| Test status | |
| Simulation time | 5485950218 ps |
| CPU time | 1072.7 seconds |
| Started | Aug 12 07:13:03 PM PDT 24 |
| Finished | Aug 12 07:30:56 PM PDT 24 |
| Peak memory | 609832 kb |
| Host | smart-928139ac-d409-4e84-956c-ec8f25f1b923 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=flash_ctrl_mem_protection_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1272396235 -assert nopostproc + UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_flash_ctrl_mem_protection.1272396235 |
| Directory | /workspace/0.chip_sw_flash_ctrl_mem_protection/latest |
| Test location | /workspace/coverage/default/0.chip_sw_flash_ctrl_ops.753821682 |
| Short name | T300 |
| Test name | |
| Test status | |
| Simulation time | 4203402976 ps |
| CPU time | 618.14 seconds |
| Started | Aug 12 07:10:32 PM PDT 24 |
| Finished | Aug 12 07:20:50 PM PDT 24 |
| Peak memory | 610084 kb |
| Host | smart-6afbd0f7-8290-41ac-839b-4a5a345a6a32 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=50_000_000 +sw_build_device=sim_dv +sw_images=flash_ctrl_ops_test:1:new_rules,test_rom:0 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=753821682 - assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co verage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_flash_ctrl_ops.753821682 |
| Directory | /workspace/0.chip_sw_flash_ctrl_ops/latest |
| Test location | /workspace/coverage/default/0.chip_sw_flash_ctrl_ops_jitter_en.4153806058 |
| Short name | T366 |
| Test name | |
| Test status | |
| Simulation time | 4730061423 ps |
| CPU time | 673.04 seconds |
| Started | Aug 12 07:08:37 PM PDT 24 |
| Finished | Aug 12 07:19:51 PM PDT 24 |
| Peak memory | 609336 kb |
| Host | smart-04e56659-ff60-4d12-9ae4-aabe20e8dc67 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=50_000_000 +en_jitter=1 +sw_build_device=sim_dv +sw_images=flash_ctrl_ops_test:1:new_rules,test_rom:0 +cdc _instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see d=4153806058 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_flash_ctrl_ops_jitter_en.4153806058 |
| Directory | /workspace/0.chip_sw_flash_ctrl_ops_jitter_en/latest |
| Test location | /workspace/coverage/default/0.chip_sw_flash_ctrl_write_clear.1350740017 |
| Short name | T1088 |
| Test name | |
| Test status | |
| Simulation time | 3230912918 ps |
| CPU time | 358.15 seconds |
| Started | Aug 12 07:10:25 PM PDT 24 |
| Finished | Aug 12 07:16:23 PM PDT 24 |
| Peak memory | 609224 kb |
| Host | smart-e03844a5-02da-4748-93b6-18a36ed8e4d4 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=8_000_000 +sw_build_device=sim_dv +sw_images=flash_ctrl_write_clear_test:1:new_rules,test_rom:0 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1350740 017 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ce/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_flash_ctrl_write_clear.1350740017 |
| Directory | /workspace/0.chip_sw_flash_ctrl_write_clear/latest |
| Test location | /workspace/coverage/default/0.chip_sw_flash_init.2558496242 |
| Short name | T239 |
| Test name | |
| Test status | |
| Simulation time | 20536170528 ps |
| CPU time | 2308.19 seconds |
| Started | Aug 12 07:08:10 PM PDT 24 |
| Finished | Aug 12 07:46:40 PM PDT 24 |
| Peak memory | 613792 kb |
| Host | smart-c57e7afc-d1eb-42d2-a4ac-5b475c24316d |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=25_000_000 +sw_build_device=sim_dv +sw_images=flash_init_test:0:test_in_rom:new_rules +cdc_instrumentation _enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2558496242 -as sert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_flash_init_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac e/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_flash_init.2558496242 |
| Directory | /workspace/0.chip_sw_flash_init/latest |
| Test location | /workspace/coverage/default/0.chip_sw_flash_scrambling_smoketest.1513435390 |
| Short name | T1286 |
| Test name | |
| Test status | |
| Simulation time | 2305026176 ps |
| CPU time | 202.1 seconds |
| Started | Aug 12 07:15:44 PM PDT 24 |
| Finished | Aug 12 07:19:07 PM PDT 24 |
| Peak memory | 610244 kb |
| Host | smart-3030bf13-0084-4b83-9d09-951528de6212 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=flash_scrambling_smoketest:1:new_rules,flash_scrambling_smoket est_otp_img_rma:4,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=1513435390 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_flash_scrambling_smoketest.1513435390 |
| Directory | /workspace/0.chip_sw_flash_scrambling_smoketest/latest |
| Test location | /workspace/coverage/default/0.chip_sw_hmac_enc.1134262901 |
| Short name | T1255 |
| Test name | |
| Test status | |
| Simulation time | 3404260776 ps |
| CPU time | 315.34 seconds |
| Started | Aug 12 07:10:57 PM PDT 24 |
| Finished | Aug 12 07:16:13 PM PDT 24 |
| Peak memory | 609700 kb |
| Host | smart-7ced48e4-486f-4066-a26d-b402f8992575 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=hmac_enc_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1134262901 -assert nopostproc +UVM_TESTNAME=chip _base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_hmac_enc.1134262901 |
| Directory | /workspace/0.chip_sw_hmac_enc/latest |
| Test location | /workspace/coverage/default/0.chip_sw_hmac_enc_idle.2320369806 |
| Short name | T1112 |
| Test name | |
| Test status | |
| Simulation time | 2654972568 ps |
| CPU time | 280.78 seconds |
| Started | Aug 12 07:08:49 PM PDT 24 |
| Finished | Aug 12 07:13:30 PM PDT 24 |
| Peak memory | 609740 kb |
| Host | smart-c1bc7b82-645a-4393-8eea-640ad0e6974e |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=hmac_enc_idle_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2320369806 -assert nopostproc +UVM_TESTNAME =chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 0.chip_sw_hmac_enc_idle.2320369806 |
| Directory | /workspace/0.chip_sw_hmac_enc_idle/latest |
| Test location | /workspace/coverage/default/0.chip_sw_hmac_enc_jitter_en_reduced_freq.868255484 |
| Short name | T356 |
| Test name | |
| Test status | |
| Simulation time | 3441277286 ps |
| CPU time | 288.06 seconds |
| Started | Aug 12 07:11:05 PM PDT 24 |
| Finished | Aug 12 07:15:54 PM PDT 24 |
| Peak memory | 610212 kb |
| Host | smart-0ec4f74b-8583-4373-af50-87141a84a405 |
| User | root |
| Command | /workspace/default/simv +en_jitter=1 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=hmac_enc_test:1:new_rules,test_rom:0 +cdc_instrumentation _enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=868255484 -ass ert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_hmac_enc_jitter_en_reduced_freq.868255484 |
| Directory | /workspace/0.chip_sw_hmac_enc_jitter_en_reduced_freq/latest |
| Test location | /workspace/coverage/default/0.chip_sw_hmac_multistream.1654427937 |
| Short name | T1123 |
| Test name | |
| Test status | |
| Simulation time | 7945239104 ps |
| CPU time | 2112.8 seconds |
| Started | Aug 12 07:09:58 PM PDT 24 |
| Finished | Aug 12 07:45:11 PM PDT 24 |
| Peak memory | 609772 kb |
| Host | smart-69ed2dfe-7f4b-4db9-8c65-198e5736a15c |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=hmac_multistream_functest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1654427937 -assert nopostproc +UVM_T ESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l og /dev/null -cm_name 0.chip_sw_hmac_multistream.1654427937 |
| Directory | /workspace/0.chip_sw_hmac_multistream/latest |
| Test location | /workspace/coverage/default/0.chip_sw_hmac_oneshot.93470778 |
| Short name | T308 |
| Test name | |
| Test status | |
| Simulation time | 3009606856 ps |
| CPU time | 310.09 seconds |
| Started | Aug 12 07:12:39 PM PDT 24 |
| Finished | Aug 12 07:17:50 PM PDT 24 |
| Peak memory | 609720 kb |
| Host | smart-39672614-154b-41b9-88b8-0d1060d43a8b |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=hmac_functest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=93470778 -assert nopostproc +UVM_TESTNAME=chip_b ase_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 0.chip_sw_hmac_oneshot.93470778 |
| Directory | /workspace/0.chip_sw_hmac_oneshot/latest |
| Test location | /workspace/coverage/default/0.chip_sw_hmac_smoketest.2164602813 |
| Short name | T1387 |
| Test name | |
| Test status | |
| Simulation time | 3092180816 ps |
| CPU time | 369.1 seconds |
| Started | Aug 12 07:12:13 PM PDT 24 |
| Finished | Aug 12 07:18:22 PM PDT 24 |
| Peak memory | 610100 kb |
| Host | smart-e4f8b868-03cc-4849-b6ad-0c27759626f0 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=hmac_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2164602813 -assert nopostproc +UVM_TESTNAME=chi p_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul l -cm_name 0.chip_sw_hmac_smoketest.2164602813 |
| Directory | /workspace/0.chip_sw_hmac_smoketest/latest |
| Test location | /workspace/coverage/default/0.chip_sw_i2c_device_tx_rx.2102815154 |
| Short name | T348 |
| Test name | |
| Test status | |
| Simulation time | 4402710420 ps |
| CPU time | 777.5 seconds |
| Started | Aug 12 07:08:57 PM PDT 24 |
| Finished | Aug 12 07:21:55 PM PDT 24 |
| Peak memory | 610944 kb |
| Host | smart-952b7f5d-36a4-492a-8a1b-995f9c8ef07a |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=i2c_device_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2102815154 -assert nopostproc +UVM_TESTN AME=chip_base_test +UVM_TEST_SEQ=chip_sw_i2c_device_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v db -cm_log /dev/null -cm_name 0.chip_sw_i2c_device_tx_rx.2102815154 |
| Directory | /workspace/0.chip_sw_i2c_device_tx_rx/latest |
| Test location | /workspace/coverage/default/0.chip_sw_i2c_host_tx_rx.491780603 |
| Short name | T1287 |
| Test name | |
| Test status | |
| Simulation time | 5593480800 ps |
| CPU time | 838 seconds |
| Started | Aug 12 07:07:46 PM PDT 24 |
| Finished | Aug 12 07:21:44 PM PDT 24 |
| Peak memory | 609636 kb |
| Host | smart-8b184334-7cde-441c-930d-3dc20f99e8ff |
| User | root |
| Command | /workspace/default/simv +i2c_idx=0 +sw_build_device=sim_dv +sw_images=i2c_host_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=491780603 -assert nopostproc +U VM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_i2c_host_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def ault.vdb -cm_log /dev/null -cm_name 0.chip_sw_i2c_host_tx_rx.491780603 |
| Directory | /workspace/0.chip_sw_i2c_host_tx_rx/latest |
| Test location | /workspace/coverage/default/0.chip_sw_i2c_host_tx_rx_idx1.3910513828 |
| Short name | T1388 |
| Test name | |
| Test status | |
| Simulation time | 5769805640 ps |
| CPU time | 825.35 seconds |
| Started | Aug 12 07:07:06 PM PDT 24 |
| Finished | Aug 12 07:20:52 PM PDT 24 |
| Peak memory | 609888 kb |
| Host | smart-0e44e2a5-0ec6-4349-9ac6-3dc3399b5db7 |
| User | root |
| Command | /workspace/default/simv +i2c_idx=1 +sw_build_device=sim_dv +sw_images=i2c_host_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3910513828 -assert nopostproc + UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_i2c_host_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de fault.vdb -cm_log /dev/null -cm_name 0.chip_sw_i2c_host_tx_rx_idx1.3910513828 |
| Directory | /workspace/0.chip_sw_i2c_host_tx_rx_idx1/latest |
| Test location | /workspace/coverage/default/0.chip_sw_inject_scramble_seed.954042225 |
| Short name | T1328 |
| Test name | |
| Test status | |
| Simulation time | 65460538714 ps |
| CPU time | 11170.3 seconds |
| Started | Aug 12 07:07:14 PM PDT 24 |
| Finished | Aug 12 10:13:25 PM PDT 24 |
| Peak memory | 625136 kb |
| Host | smart-4ea8226f-ef95-4163-8e11-f11479c9172e |
| User | root |
| Command | /workspace/default/simv +lc_at_prod=1 +flash_program_latency=5 +sw_test_timeout_ns=150_000_000 +sw_build_device=sim_dv +sw_images=inject_scramble_seed :1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=954042225 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_inject_scramble_seed_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_inject_scramble_seed.954042225 |
| Directory | /workspace/0.chip_sw_inject_scramble_seed/latest |
| Test location | /workspace/coverage/default/0.chip_sw_keymgr_key_derivation.3874641605 |
| Short name | T1155 |
| Test name | |
| Test status | |
| Simulation time | 9798033024 ps |
| CPU time | 1903.62 seconds |
| Started | Aug 12 07:09:41 PM PDT 24 |
| Finished | Aug 12 07:41:26 PM PDT 24 |
| Peak memory | 618336 kb |
| Host | smart-880dcccb-73c8-4f9c-9cc9-48d5585ef365 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=20_000_000 +sw_build_device=sim_dv +sw_images=keymgr_key_derivation_test:1:new_rules,test_rom:0 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3874 641605 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_keymgr_key_derivation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_keymgr_key_derivation.3874641605 |
| Directory | /workspace/0.chip_sw_keymgr_key_derivation/latest |
| Test location | /workspace/coverage/default/0.chip_sw_keymgr_key_derivation_jitter_en.4095452610 |
| Short name | T124 |
| Test name | |
| Test status | |
| Simulation time | 9249323464 ps |
| CPU time | 1702.65 seconds |
| Started | Aug 12 07:08:34 PM PDT 24 |
| Finished | Aug 12 07:36:57 PM PDT 24 |
| Peak memory | 617376 kb |
| Host | smart-605c63ae-3426-4814-896d-802c272bf358 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=20_000_000 +en_jitter=1 +sw_build_device=sim_dv +sw_images=keymgr_key_derivation_test:1:new_rules,test_rom :0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=4095452610 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_keymgr_key_derivation_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_keymgr_key_derivation_jitter_en.4095452610 |
| Directory | /workspace/0.chip_sw_keymgr_key_derivation_jitter_en/latest |
| Test location | /workspace/coverage/default/0.chip_sw_keymgr_key_derivation_jitter_en_reduced_freq.1957610832 |
| Short name | T1395 |
| Test name | |
| Test status | |
| Simulation time | 12885796705 ps |
| CPU time | 2250.12 seconds |
| Started | Aug 12 07:11:36 PM PDT 24 |
| Finished | Aug 12 07:49:07 PM PDT 24 |
| Peak memory | 618656 kb |
| Host | smart-b24b11c2-5956-400b-9aab-c96062e9105e |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=20_000_000 +en_jitter=1 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=keymgr_key_derivation_test :1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=1957610832 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_keymgr_key_derivation_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_keymgr_key_derivation_jitter_en _reduced_freq.1957610832 |
| Directory | /workspace/0.chip_sw_keymgr_key_derivation_jitter_en_reduced_freq/latest |
| Test location | /workspace/coverage/default/0.chip_sw_keymgr_key_derivation_prod.3307361517 |
| Short name | T1221 |
| Test name | |
| Test status | |
| Simulation time | 7319371408 ps |
| CPU time | 1345.06 seconds |
| Started | Aug 12 07:11:22 PM PDT 24 |
| Finished | Aug 12 07:33:47 PM PDT 24 |
| Peak memory | 618320 kb |
| Host | smart-c1fc8e6c-ab8c-488d-b405-ffce78f32b9a |
| User | root |
| Command | /workspace/default/simv +lc_at_prod=1 +sw_test_timeout_ns=20_000_000 +sw_build_device=sim_dv +sw_images=keymgr_key_derivation_test:1:new_rules,test_ro m:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=3307361517 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_keymgr_key_derivation_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_keymgr_key_derivation_prod.3307361517 |
| Directory | /workspace/0.chip_sw_keymgr_key_derivation_prod/latest |
| Test location | /workspace/coverage/default/0.chip_sw_keymgr_sideload_kmac.3744941990 |
| Short name | T1440 |
| Test name | |
| Test status | |
| Simulation time | 7335949160 ps |
| CPU time | 1392.56 seconds |
| Started | Aug 12 07:10:16 PM PDT 24 |
| Finished | Aug 12 07:33:30 PM PDT 24 |
| Peak memory | 610840 kb |
| Host | smart-1f69f511-be40-4057-be48-938edabed8bb |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=20_000_000 +sw_build_device=sim_dv +sw_images=keymgr_sideload_kmac_test:1:new_rules,test_rom:0 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37449 41990 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_keymgr_sideload_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_keymgr_sideload_kmac.3744941990 |
| Directory | /workspace/0.chip_sw_keymgr_sideload_kmac/latest |
| Test location | /workspace/coverage/default/0.chip_sw_keymgr_sideload_otbn.819710992 |
| Short name | T234 |
| Test name | |
| Test status | |
| Simulation time | 16108129200 ps |
| CPU time | 3968.41 seconds |
| Started | Aug 12 07:11:09 PM PDT 24 |
| Finished | Aug 12 08:17:18 PM PDT 24 |
| Peak memory | 611244 kb |
| Host | smart-26ead3b4-736a-4079-8c00-00fbf4271b61 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=20_000_000 +sw_build_device=sim_dv +sw_images=keymgr_sideload_otbn_test:1:new_rules,test_rom:0 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=81971 0992 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_keymgr_sideload_otbn.819710992 |
| Directory | /workspace/0.chip_sw_keymgr_sideload_otbn/latest |
| Test location | /workspace/coverage/default/0.chip_sw_kmac_app_rom.706752500 |
| Short name | T411 |
| Test name | |
| Test status | |
| Simulation time | 3050966122 ps |
| CPU time | 212.18 seconds |
| Started | Aug 12 07:08:54 PM PDT 24 |
| Finished | Aug 12 07:12:26 PM PDT 24 |
| Peak memory | 609944 kb |
| Host | smart-2c40c77a-119c-45b9-8dbd-3ef1c2ff3176 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=kmac_app_rom_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=706752500 -assert nopostproc +UVM_TESTNAME=c hip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n ull -cm_name 0.chip_sw_kmac_app_rom.706752500 |
| Directory | /workspace/0.chip_sw_kmac_app_rom/latest |
| Test location | /workspace/coverage/default/0.chip_sw_kmac_entropy.3499655640 |
| Short name | T460 |
| Test name | |
| Test status | |
| Simulation time | 2478498776 ps |
| CPU time | 257.45 seconds |
| Started | Aug 12 07:07:39 PM PDT 24 |
| Finished | Aug 12 07:11:56 PM PDT 24 |
| Peak memory | 610232 kb |
| Host | smart-0c7aac1d-6577-4bc8-830e-dde4b590dac8 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=kmac_entropy_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3499655640 -assert nopostproc +UVM_TESTNAME= chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/ null -cm_name 0.chip_sw_kmac_entropy.3499655640 |
| Directory | /workspace/0.chip_sw_kmac_entropy/latest |
| Test location | /workspace/coverage/default/0.chip_sw_kmac_idle.815343624 |
| Short name | T1292 |
| Test name | |
| Test status | |
| Simulation time | 2522531238 ps |
| CPU time | 244.68 seconds |
| Started | Aug 12 07:12:57 PM PDT 24 |
| Finished | Aug 12 07:17:02 PM PDT 24 |
| Peak memory | 610104 kb |
| Host | smart-69790ff7-6e8a-4953-baff-5b1977cb3a38 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=kmac_idle_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=815343624 -assert nopostproc +UVM_TESTNAME=chip _base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_kmac_idle.815343624 |
| Directory | /workspace/0.chip_sw_kmac_idle/latest |
| Test location | /workspace/coverage/default/0.chip_sw_kmac_mode_cshake.1281429643 |
| Short name | T1009 |
| Test name | |
| Test status | |
| Simulation time | 2693299190 ps |
| CPU time | 296.81 seconds |
| Started | Aug 12 07:11:27 PM PDT 24 |
| Finished | Aug 12 07:16:25 PM PDT 24 |
| Peak memory | 610132 kb |
| Host | smart-999745a6-2ab1-48b8-9c41-29be2f4e1765 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=kmac_mode_cshake_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1281429643 -assert nopostproc +UVM_TESTN AME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log / dev/null -cm_name 0.chip_sw_kmac_mode_cshake.1281429643 |
| Directory | /workspace/0.chip_sw_kmac_mode_cshake/latest |
| Test location | /workspace/coverage/default/0.chip_sw_kmac_mode_kmac.3740302482 |
| Short name | T1249 |
| Test name | |
| Test status | |
| Simulation time | 3070005344 ps |
| CPU time | 251.08 seconds |
| Started | Aug 12 07:08:19 PM PDT 24 |
| Finished | Aug 12 07:12:31 PM PDT 24 |
| Peak memory | 608920 kb |
| Host | smart-968767ab-2958-4de2-8507-2d32d7149be8 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=kmac_mode_kmac_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3740302482 -assert nopostproc +UVM_TESTNAM E=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 0.chip_sw_kmac_mode_kmac.3740302482 |
| Directory | /workspace/0.chip_sw_kmac_mode_kmac/latest |
| Test location | /workspace/coverage/default/0.chip_sw_kmac_mode_kmac_jitter_en.3654259772 |
| Short name | T998 |
| Test name | |
| Test status | |
| Simulation time | 3083486140 ps |
| CPU time | 251.89 seconds |
| Started | Aug 12 07:10:16 PM PDT 24 |
| Finished | Aug 12 07:14:28 PM PDT 24 |
| Peak memory | 609780 kb |
| Host | smart-4cf4efdd-b1b7-41d2-a70d-bd12c06b0782 |
| User | root |
| Command | /workspace/default/simv +en_jitter=1 +sw_build_device=sim_dv +sw_images=kmac_mode_kmac_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3654259772 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd b -cm_log /dev/null -cm_name 0.chip_sw_kmac_mode_kmac_jitter_en.3654259772 |
| Directory | /workspace/0.chip_sw_kmac_mode_kmac_jitter_en/latest |
| Test location | /workspace/coverage/default/0.chip_sw_kmac_mode_kmac_jitter_en_reduced_freq.1064813354 |
| Short name | T1000 |
| Test name | |
| Test status | |
| Simulation time | 3215359572 ps |
| CPU time | 426.69 seconds |
| Started | Aug 12 07:14:16 PM PDT 24 |
| Finished | Aug 12 07:21:24 PM PDT 24 |
| Peak memory | 610124 kb |
| Host | smart-e2d93140-368a-468e-a2ba-da7549a877a9 |
| User | root |
| Command | /workspace/default/simv +en_jitter=1 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=kmac_mode_kmac_test:1:new_rules,test_rom:0 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10648133 54 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac e/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_kmac_mode_kmac_jitter_en_reduced_freq.1064813354 |
| Directory | /workspace/0.chip_sw_kmac_mode_kmac_jitter_en_reduced_freq/latest |
| Test location | /workspace/coverage/default/0.chip_sw_kmac_smoketest.3009205721 |
| Short name | T1243 |
| Test name | |
| Test status | |
| Simulation time | 2530461392 ps |
| CPU time | 293.04 seconds |
| Started | Aug 12 07:13:19 PM PDT 24 |
| Finished | Aug 12 07:18:13 PM PDT 24 |
| Peak memory | 610128 kb |
| Host | smart-3a394647-52b6-4415-b42a-15137befe91b |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=kmac_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3009205721 -assert nopostproc +UVM_TESTNAME=chi p_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul l -cm_name 0.chip_sw_kmac_smoketest.3009205721 |
| Directory | /workspace/0.chip_sw_kmac_smoketest/latest |
| Test location | /workspace/coverage/default/0.chip_sw_lc_ctrl_otp_hw_cfg0.3268649682 |
| Short name | T989 |
| Test name | |
| Test status | |
| Simulation time | 3591289750 ps |
| CPU time | 391.94 seconds |
| Started | Aug 12 07:11:04 PM PDT 24 |
| Finished | Aug 12 07:17:36 PM PDT 24 |
| Peak memory | 609800 kb |
| Host | smart-9751e553-7507-4f81-889f-d86de76ba567 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=lc_ctrl_otp_hw_cfg0_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3268649682 -assert nopostproc +UVM_TE STNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_lo g /dev/null -cm_name 0.chip_sw_lc_ctrl_otp_hw_cfg0.3268649682 |
| Directory | /workspace/0.chip_sw_lc_ctrl_otp_hw_cfg0/latest |
| Test location | /workspace/coverage/default/0.chip_sw_lc_ctrl_raw_to_scrap.3140780362 |
| Short name | T757 |
| Test name | |
| Test status | |
| Simulation time | 3150194928 ps |
| CPU time | 138.7 seconds |
| Started | Aug 12 07:08:52 PM PDT 24 |
| Finished | Aug 12 07:11:12 PM PDT 24 |
| Peak memory | 620380 kb |
| Host | smart-5b517e9e-ce87-41d1-b1e4-1fee233a0550 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +src_dec_state=DecLcStRaw +sw_build_device=sim_dv +sw_images=lc_ctrl_scrap_test:1:new_rules ,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3140780362 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_scrap_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_lc_ctrl_raw_to_scrap.3140780362 |
| Directory | /workspace/0.chip_sw_lc_ctrl_raw_to_scrap/latest |
| Test location | /workspace/coverage/default/0.chip_sw_lc_ctrl_rma_to_scrap.3444881793 |
| Short name | T756 |
| Test name | |
| Test status | |
| Simulation time | 3235400434 ps |
| CPU time | 224.66 seconds |
| Started | Aug 12 07:08:45 PM PDT 24 |
| Finished | Aug 12 07:12:30 PM PDT 24 |
| Peak memory | 622160 kb |
| Host | smart-d028001d-336a-4b76-bfc1-309f5a6135dd |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +src_dec_state=DecLcStRma +sw_build_device=sim_dv +sw_images=lc_ctrl_scrap_test:1:new_rules ,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3444881793 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_scrap_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_lc_ctrl_rma_to_scrap.3444881793 |
| Directory | /workspace/0.chip_sw_lc_ctrl_rma_to_scrap/latest |
| Test location | /workspace/coverage/default/0.chip_sw_lc_ctrl_test_locked0_to_scrap.3401438128 |
| Short name | T186 |
| Test name | |
| Test status | |
| Simulation time | 3495544002 ps |
| CPU time | 160.76 seconds |
| Started | Aug 12 07:09:42 PM PDT 24 |
| Finished | Aug 12 07:12:23 PM PDT 24 |
| Peak memory | 620384 kb |
| Host | smart-405f63d5-25da-4fa6-811b-fdaef1b226bc |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +src_dec_state=DecLcStTestLocked0 +sw_build_device=sim_dv +sw_images=lc_ctrl_scrap_test:1:n ew_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3401438128 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_scrap_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_lc_ctrl_test_locked0_to_scrap.3401438128 |
| Directory | /workspace/0.chip_sw_lc_ctrl_test_locked0_to_scrap/latest |
| Test location | /workspace/coverage/default/0.chip_sw_lc_ctrl_transition.215214986 |
| Short name | T1079 |
| Test name | |
| Test status | |
| Simulation time | 12530241877 ps |
| CPU time | 1009.72 seconds |
| Started | Aug 12 07:09:06 PM PDT 24 |
| Finished | Aug 12 07:25:57 PM PDT 24 |
| Peak memory | 625132 kb |
| Host | smart-98851f81-588b-42ab-8456-bed4bdf02657 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=lc_ctrl_transition_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=215214986 -assert nopostproc +UVM_TEST NAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_transition_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul t.vdb -cm_log /dev/null -cm_name 0.chip_sw_lc_ctrl_transition.215214986 |
| Directory | /workspace/0.chip_sw_lc_ctrl_transition/latest |
| Test location | /workspace/coverage/default/0.chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz.3887281554 |
| Short name | T1426 |
| Test name | |
| Test status | |
| Simulation time | 2555704595 ps |
| CPU time | 104.15 seconds |
| Started | Aug 12 07:07:35 PM PDT 24 |
| Finished | Aug 12 07:09:19 PM PDT 24 |
| Peak memory | 618016 kb |
| Host | smart-0aef136a-be0c-44d5-8138-41c344cbaa18 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStRaw +chip_clock_source=ChipClockSourceExternal48Mhz +exp_volatile_raw_unlock_en=0 +sw_build_device=s im_dv +sw_images=lc_ctrl_volatile_raw_unlock_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3887281554 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TES T_SEQ=chip_sw_lc_volatile_raw_unlock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz.3887281554 |
| Directory | /workspace/0.chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz/latest |
| Test location | /workspace/coverage/default/0.chip_sw_lc_walkthrough_prodend.2921833596 |
| Short name | T1097 |
| Test name | |
| Test status | |
| Simulation time | 8380687605 ps |
| CPU time | 982.41 seconds |
| Started | Aug 12 07:08:47 PM PDT 24 |
| Finished | Aug 12 07:25:10 PM PDT 24 |
| Peak memory | 620436 kb |
| Host | smart-5c547165-3298-48ce-a9c4-043eafadacf3 |
| User | root |
| Command | /workspace/default/simv +flash_program_latency=5 +use_otp_image=OtpTypeLcStRaw +dest_dec_state=DecLcStProdEnd +sw_build_device=sim_dv +sw_images=lc_wa lkthrough_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2921833596 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_walkthrough_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_lc_walkthrough_prodend.2921833596 |
| Directory | /workspace/0.chip_sw_lc_walkthrough_prodend/latest |
| Test location | /workspace/coverage/default/0.chip_sw_lc_walkthrough_rma.3840607708 |
| Short name | T198 |
| Test name | |
| Test status | |
| Simulation time | 46764858668 ps |
| CPU time | 5817.32 seconds |
| Started | Aug 12 07:07:36 PM PDT 24 |
| Finished | Aug 12 08:44:35 PM PDT 24 |
| Peak memory | 621088 kb |
| Host | smart-60764da6-506d-4db7-9213-b4d3a3e58515 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStRaw +dest_dec_state=DecLcStRma +flash_program_latency=5 +sw_test_timeout_ns=200_000_000 +sw_build_de vice=sim_dv +sw_images=lc_walkthrough_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3840607708 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=c hip_sw_lc_walkthrough_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip _sw_lc_walkthrough_rma.3840607708 |
| Directory | /workspace/0.chip_sw_lc_walkthrough_rma/latest |
| Test location | /workspace/coverage/default/0.chip_sw_lc_walkthrough_testunlocks.2082297654 |
| Short name | T175 |
| Test name | |
| Test status | |
| Simulation time | 23496515576 ps |
| CPU time | 2276.55 seconds |
| Started | Aug 12 07:10:17 PM PDT 24 |
| Finished | Aug 12 07:48:15 PM PDT 24 |
| Peak memory | 621612 kb |
| Host | smart-836228c2-de23-4fbe-8e88-a67c02da64aa |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStRaw +dest_dec_state=DecLcStTestUnlock7 +sw_build_device=sim_dv +sw_images=lc_walkthrough_testunlocks _test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=2082297654 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_walkthrough_testunlocks_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_lc_walkthrough_testun locks.2082297654 |
| Directory | /workspace/0.chip_sw_lc_walkthrough_testunlocks/latest |
| Test location | /workspace/coverage/default/0.chip_sw_otbn_ecdsa_op_irq_jitter_en.3759241691 |
| Short name | T1174 |
| Test name | |
| Test status | |
| Simulation time | 19177043297 ps |
| CPU time | 3814.8 seconds |
| Started | Aug 12 07:10:37 PM PDT 24 |
| Finished | Aug 12 08:14:12 PM PDT 24 |
| Peak memory | 610648 kb |
| Host | smart-73a4bff0-d3c0-405e-9569-e3f0097acb33 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=33_000_000 +rng_srate_value=30 +en_jitter=1 +sw_build_device=sim_dv +sw_images=otbn_ecdsa_op_irq_test:1:ne w_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/ sim.tcl +ntb_random_seed=3759241691 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tg l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_otbn_ecdsa_op_irq_jitter_en.3759241691 |
| Directory | /workspace/0.chip_sw_otbn_ecdsa_op_irq_jitter_en/latest |
| Test location | /workspace/coverage/default/0.chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq.4072956552 |
| Short name | T1290 |
| Test name | |
| Test status | |
| Simulation time | 24356626232 ps |
| CPU time | 4065.11 seconds |
| Started | Aug 12 07:09:59 PM PDT 24 |
| Finished | Aug 12 08:17:45 PM PDT 24 |
| Peak memory | 610736 kb |
| Host | smart-333b1ef7-28e0-4c7b-99fe-9568a6c800a7 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=33_000_000 +rng_srate_value=30 +en_jitter=1 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=otbn_e cdsa_op_irq_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/ repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4072956552 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_otbn_ecdsa_op_irq_jitter_en_redu ced_freq.4072956552 |
| Directory | /workspace/0.chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq/latest |
| Test location | /workspace/coverage/default/0.chip_sw_otbn_mem_scramble.1134808666 |
| Short name | T288 |
| Test name | |
| Test status | |
| Simulation time | 3201292942 ps |
| CPU time | 467.86 seconds |
| Started | Aug 12 07:09:55 PM PDT 24 |
| Finished | Aug 12 07:17:45 PM PDT 24 |
| Peak memory | 609028 kb |
| Host | smart-8421c3cf-d9f3-460f-b438-eee24e0424a5 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=15_000_000 +en_scb_tl_err_chk=0 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=otbn _mem_scramble_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1134808666 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_otbn_mem_scramble.1134808666 |
| Directory | /workspace/0.chip_sw_otbn_mem_scramble/latest |
| Test location | /workspace/coverage/default/0.chip_sw_otbn_randomness.2862222033 |
| Short name | T1166 |
| Test name | |
| Test status | |
| Simulation time | 5975826040 ps |
| CPU time | 1036.74 seconds |
| Started | Aug 12 07:08:11 PM PDT 24 |
| Finished | Aug 12 07:25:28 PM PDT 24 |
| Peak memory | 610696 kb |
| Host | smart-df4d38d1-22f3-4a3d-bdfb-4e59ecae4fd1 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +rng_srate_value=30 +sw_build_device=sim_dv +sw_images=otbn_randomness_test:1:new_rules,test_ro m:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=2862222033 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_otbn_randomness.2862222033 |
| Directory | /workspace/0.chip_sw_otbn_randomness/latest |
| Test location | /workspace/coverage/default/0.chip_sw_otbn_smoketest.3554904853 |
| Short name | T1187 |
| Test name | |
| Test status | |
| Simulation time | 9644935484 ps |
| CPU time | 2578.34 seconds |
| Started | Aug 12 07:13:09 PM PDT 24 |
| Finished | Aug 12 07:56:08 PM PDT 24 |
| Peak memory | 609896 kb |
| Host | smart-5580dbe5-7f3f-4b55-ae80-a3f88279151c |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=otbn_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3554904853 -assert nopostproc +UVM_TESTNAME=chi p_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul l -cm_name 0.chip_sw_otbn_smoketest.3554904853 |
| Directory | /workspace/0.chip_sw_otbn_smoketest/latest |
| Test location | /workspace/coverage/default/0.chip_sw_otp_ctrl_dai_lock.1310434961 |
| Short name | T1218 |
| Test name | |
| Test status | |
| Simulation time | 27963674512 ps |
| CPU time | 5977.99 seconds |
| Started | Aug 12 07:11:52 PM PDT 24 |
| Finished | Aug 12 08:51:31 PM PDT 24 |
| Peak memory | 609556 kb |
| Host | smart-42c88b5f-c72b-4422-9fea-c11ce28b2531 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=30_000_000 +sw_build_device=sim_dv +sw_images=otp_ctrl_mem_access_test:1:new_rules,test_rom:0 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=131043 4961 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_otp_ctrl_dai_lock.1310434961 |
| Directory | /workspace/0.chip_sw_otp_ctrl_dai_lock/latest |
| Test location | /workspace/coverage/default/0.chip_sw_otp_ctrl_ecc_error_vendor_test.120616556 |
| Short name | T967 |
| Test name | |
| Test status | |
| Simulation time | 2809026410 ps |
| CPU time | 263.98 seconds |
| Started | Aug 12 07:08:22 PM PDT 24 |
| Finished | Aug 12 07:12:47 PM PDT 24 |
| Peak memory | 609748 kb |
| Host | smart-867c6ebc-f1ec-4edd-aa95-31898464df47 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=otp_ctrl_vendor_test_ecc_error_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=120616556 -assert nopostpr oc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_otp_ctrl_vendor_test_ecc_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_otp_ctrl_ecc_error_vendor_test.120616556 |
| Directory | /workspace/0.chip_sw_otp_ctrl_ecc_error_vendor_test/latest |
| Test location | /workspace/coverage/default/0.chip_sw_otp_ctrl_escalation.3768860484 |
| Short name | T178 |
| Test name | |
| Test status | |
| Simulation time | 5979538984 ps |
| CPU time | 780.25 seconds |
| Started | Aug 12 07:09:05 PM PDT 24 |
| Finished | Aug 12 07:22:06 PM PDT 24 |
| Peak memory | 611592 kb |
| Host | smart-384917d8-0577-4b9d-b401-44dacdb00786 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 3768860484 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_otp_ctrl_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_otp_ctrl_escalation.3768860484 |
| Directory | /workspace/0.chip_sw_otp_ctrl_escalation/latest |
| Test location | /workspace/coverage/default/0.chip_sw_otp_ctrl_lc_signals_dev.413597601 |
| Short name | T1080 |
| Test name | |
| Test status | |
| Simulation time | 7444330548 ps |
| CPU time | 1394.17 seconds |
| Started | Aug 12 07:07:32 PM PDT 24 |
| Finished | Aug 12 07:30:47 PM PDT 24 |
| Peak memory | 611120 kb |
| Host | smart-f8891fa9-b68a-4d55-9611-22a4f7269bbb |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStDev +otp_clear_secret2=1 +sw_build_device=sim_dv +sw_images=otp_ctrl_lc_signals_test:1:new_rules,tes t_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +nt b_random_seed=413597601 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_otp_ctrl_lc_signals_dev.413597601 |
| Directory | /workspace/0.chip_sw_otp_ctrl_lc_signals_dev/latest |
| Test location | /workspace/coverage/default/0.chip_sw_otp_ctrl_lc_signals_prod.1330497792 |
| Short name | T1213 |
| Test name | |
| Test status | |
| Simulation time | 7939658168 ps |
| CPU time | 1452.27 seconds |
| Started | Aug 12 07:07:04 PM PDT 24 |
| Finished | Aug 12 07:31:16 PM PDT 24 |
| Peak memory | 610840 kb |
| Host | smart-8853ddaf-0f4b-4a93-8937-f1d0d1405d68 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStProd +otp_clear_secret2=1 +sw_build_device=sim_dv +sw_images=otp_ctrl_lc_signals_test:1:new_rules,te st_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n tb_random_seed=1330497792 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_otp_ctrl_lc_signals_prod.1330497792 |
| Directory | /workspace/0.chip_sw_otp_ctrl_lc_signals_prod/latest |
| Test location | /workspace/coverage/default/0.chip_sw_otp_ctrl_lc_signals_rma.362172907 |
| Short name | T1232 |
| Test name | |
| Test status | |
| Simulation time | 7936326496 ps |
| CPU time | 1203.93 seconds |
| Started | Aug 12 07:07:09 PM PDT 24 |
| Finished | Aug 12 07:27:13 PM PDT 24 |
| Peak memory | 611108 kb |
| Host | smart-6210e82e-48bd-483e-bc7a-27240c11791d |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStRma +otp_clear_secret2=1 +sw_build_device=sim_dv +sw_images=otp_ctrl_lc_signals_test:1:new_rules,tes t_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +nt b_random_seed=362172907 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_otp_ctrl_lc_signals_rma.362172907 |
| Directory | /workspace/0.chip_sw_otp_ctrl_lc_signals_rma/latest |
| Test location | /workspace/coverage/default/0.chip_sw_otp_ctrl_lc_signals_test_unlocked0.3413726122 |
| Short name | T1327 |
| Test name | |
| Test status | |
| Simulation time | 4506285330 ps |
| CPU time | 865.1 seconds |
| Started | Aug 12 07:11:24 PM PDT 24 |
| Finished | Aug 12 07:25:50 PM PDT 24 |
| Peak memory | 610564 kb |
| Host | smart-77106a63-c0b1-43cd-946d-551430b1ce96 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStTestUnlocked0 +otp_clear_secret2=1 +sw_build_device=sim_dv +sw_images=otp_ctrl_lc_signals_test:1:new _rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/s im.tcl +ntb_random_seed=3413726122 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_otp_ctrl_lc_signals_test_unlocked0.3413726122 |
| Directory | /workspace/0.chip_sw_otp_ctrl_lc_signals_test_unlocked0/latest |
| Test location | /workspace/coverage/default/0.chip_sw_otp_ctrl_smoketest.1848731156 |
| Short name | T1409 |
| Test name | |
| Test status | |
| Simulation time | 2815955628 ps |
| CPU time | 332.55 seconds |
| Started | Aug 12 07:14:05 PM PDT 24 |
| Finished | Aug 12 07:19:38 PM PDT 24 |
| Peak memory | 609732 kb |
| Host | smart-a2514c9f-3903-43e2-9b2c-81ac6490ad44 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=otp_ctrl_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1848731156 -assert nopostproc +UVM_TESTNAME =chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 0.chip_sw_otp_ctrl_smoketest.1848731156 |
| Directory | /workspace/0.chip_sw_otp_ctrl_smoketest/latest |
| Test location | /workspace/coverage/default/0.chip_sw_pattgen_ios.2517713962 |
| Short name | T361 |
| Test name | |
| Test status | |
| Simulation time | 3467308266 ps |
| CPU time | 233.87 seconds |
| Started | Aug 12 07:07:31 PM PDT 24 |
| Finished | Aug 12 07:11:26 PM PDT 24 |
| Peak memory | 610716 kb |
| Host | smart-6d7746a0-a3cb-4e62-9618-841fa610af83 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=5_000_000 +sw_build_device=sim_dv +sw_images=pattgen_ios_test:1:new_rules,test_rom:0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2517713962 -ass ert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_patt_ios_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/c overage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_pattgen_ios.2517713962 |
| Directory | /workspace/0.chip_sw_pattgen_ios/latest |
| Test location | /workspace/coverage/default/0.chip_sw_plic_sw_irq.3178046987 |
| Short name | T252 |
| Test name | |
| Test status | |
| Simulation time | 2521845572 ps |
| CPU time | 224.51 seconds |
| Started | Aug 12 07:08:51 PM PDT 24 |
| Finished | Aug 12 07:12:36 PM PDT 24 |
| Peak memory | 610156 kb |
| Host | smart-a183b48e-1c8f-4313-89c1-23cca19c20ee |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=plic_sw_irq_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3178046987 -assert nopostproc +UVM_TESTNAME=c hip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n ull -cm_name 0.chip_sw_plic_sw_irq.3178046987 |
| Directory | /workspace/0.chip_sw_plic_sw_irq/latest |
| Test location | /workspace/coverage/default/0.chip_sw_power_idle_load.1664236995 |
| Short name | T429 |
| Test name | |
| Test status | |
| Simulation time | 4616192750 ps |
| CPU time | 775.39 seconds |
| Started | Aug 12 07:09:44 PM PDT 24 |
| Finished | Aug 12 07:22:41 PM PDT 24 |
| Peak memory | 609848 kb |
| Host | smart-151ba7ab-de3d-4a93-ab73-2c03c4490742 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=chip_power_idle_load:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1664236995 -assert nopostproc +UVM_TESTNA ME=chip_base_test +UVM_TEST_SEQ=chip_sw_power_idle_load_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_power_idle_load.1664236995 |
| Directory | /workspace/0.chip_sw_power_idle_load/latest |
| Test location | /workspace/coverage/default/0.chip_sw_power_sleep_load.2627763225 |
| Short name | T253 |
| Test name | |
| Test status | |
| Simulation time | 4622572440 ps |
| CPU time | 411.16 seconds |
| Started | Aug 12 07:13:32 PM PDT 24 |
| Finished | Aug 12 07:20:23 PM PDT 24 |
| Peak memory | 610944 kb |
| Host | smart-79bc9da4-8f31-427a-8629-5b85f54de42f |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=chip_power_sleep_load:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2627763225 -assert nopostproc +UVM_TESTN AME=chip_base_test +UVM_TEST_SEQ=chip_sw_power_sleep_load_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v db -cm_log /dev/null -cm_name 0.chip_sw_power_sleep_load.2627763225 |
| Directory | /workspace/0.chip_sw_power_sleep_load/latest |
| Test location | /workspace/coverage/default/0.chip_sw_pwrmgr_all_reset_reqs.3345504092 |
| Short name | T551 |
| Test name | |
| Test status | |
| Simulation time | 13204650495 ps |
| CPU time | 1541.63 seconds |
| Started | Aug 12 07:06:53 PM PDT 24 |
| Finished | Aug 12 07:32:35 PM PDT 24 |
| Peak memory | 611648 kb |
| Host | smart-46014c91-46ef-4419-9b93-6956484bab61 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=50_000_000 +sw_build_device=sim_dv +sw_images=pwrmgr_all_reset_reqs_test:1:new_rules,test_rom:0 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3345 504092 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_deep_sleep_all_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_pwrmgr_all_reset_reqs.3345504092 |
| Directory | /workspace/0.chip_sw_pwrmgr_all_reset_reqs/latest |
| Test location | /workspace/coverage/default/0.chip_sw_pwrmgr_b2b_sleep_reset_req.27827764 |
| Short name | T1052 |
| Test name | |
| Test status | |
| Simulation time | 32425460860 ps |
| CPU time | 2729.04 seconds |
| Started | Aug 12 07:08:38 PM PDT 24 |
| Finished | Aug 12 07:54:07 PM PDT 24 |
| Peak memory | 611092 kb |
| Host | smart-395e0070-d619-4de8-8a60-645bb4563d48 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=35_000_000 +sw_build_device=sim_dv +sw_images=pwrmgr_b2b_sleep_reset_test:1:new_rules,test_rom:0 +cdc_inst rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=278 27764 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_repeat_reset_wkup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_pwrmgr_b2b_sleep_reset_req.27827764 |
| Directory | /workspace/0.chip_sw_pwrmgr_b2b_sleep_reset_req/latest |
| Test location | /workspace/coverage/default/0.chip_sw_pwrmgr_deep_sleep_all_reset_reqs.2729314802 |
| Short name | T982 |
| Test name | |
| Test status | |
| Simulation time | 18810539236 ps |
| CPU time | 1926.14 seconds |
| Started | Aug 12 07:11:58 PM PDT 24 |
| Finished | Aug 12 07:44:05 PM PDT 24 |
| Peak memory | 611948 kb |
| Host | smart-b008c0f7-fb02-4959-afa1-b2fa078e0937 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=50_000_000 +sw_build_device=sim_dv +sw_images=pwrmgr_deep_sleep_all_reset_reqs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=2729314802 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_deep_sleep_all_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_pwrmgr_deep_sleep_all_reset_reqs.2729314802 |
| Directory | /workspace/0.chip_sw_pwrmgr_deep_sleep_all_reset_reqs/latest |
| Test location | /workspace/coverage/default/0.chip_sw_pwrmgr_deep_sleep_all_wake_ups.162783921 |
| Short name | T425 |
| Test name | |
| Test status | |
| Simulation time | 23777012840 ps |
| CPU time | 1942.13 seconds |
| Started | Aug 12 07:14:28 PM PDT 24 |
| Finished | Aug 12 07:46:52 PM PDT 24 |
| Peak memory | 611480 kb |
| Host | smart-5b1e82d5-4530-4fd6-9096-5920cadaefef |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=pwrmgr_deep_sleep_all_wake_ups:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 162783921 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_pwrmgr_deep_sleep_all_wake_ups_vseq +en_cov=1 -cm line+cond+fsm+tg l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_pwrmgr_deep_sleep_all_wake_ups.162783921 |
| Directory | /workspace/0.chip_sw_pwrmgr_deep_sleep_all_wake_ups/latest |
| Test location | /workspace/coverage/default/0.chip_sw_pwrmgr_deep_sleep_por_reset.2820784666 |
| Short name | T968 |
| Test name | |
| Test status | |
| Simulation time | 7410302700 ps |
| CPU time | 741.62 seconds |
| Started | Aug 12 07:10:41 PM PDT 24 |
| Finished | Aug 12 07:23:03 PM PDT 24 |
| Peak memory | 611056 kb |
| Host | smart-d8760894-b2e8-4ccb-a197-32450c7af6f2 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_deep_sleep_por_reset_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2820784666 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sleep_por_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage /default.vdb -cm_log /dev/null -cm_name 0.chip_sw_pwrmgr_deep_sleep_por_reset.2820784666 |
| Directory | /workspace/0.chip_sw_pwrmgr_deep_sleep_por_reset/latest |
| Test location | /workspace/coverage/default/0.chip_sw_pwrmgr_main_power_glitch_reset.1238189012 |
| Short name | T1225 |
| Test name | |
| Test status | |
| Simulation time | 3519857170 ps |
| CPU time | 570.91 seconds |
| Started | Aug 12 07:07:57 PM PDT 24 |
| Finished | Aug 12 07:17:28 PM PDT 24 |
| Peak memory | 617468 kb |
| Host | smart-d826c972-b2d9-46e5-9a13-f0a7eb7dea50 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=pwrmgr_main_power_glitch_test:1:new_rules,test_rom:0 +cd c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se ed=1238189012 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_main_power_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_pwrmgr_main_power_glitch_reset.1238189012 |
| Directory | /workspace/0.chip_sw_pwrmgr_main_power_glitch_reset/latest |
| Test location | /workspace/coverage/default/0.chip_sw_pwrmgr_normal_sleep_all_reset_reqs.911778681 |
| Short name | T374 |
| Test name | |
| Test status | |
| Simulation time | 12999789000 ps |
| CPU time | 1558.39 seconds |
| Started | Aug 12 07:09:46 PM PDT 24 |
| Finished | Aug 12 07:35:45 PM PDT 24 |
| Peak memory | 611616 kb |
| Host | smart-d4e1ddb8-541b-4cf6-915e-e684a168f9a6 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_normal_sleep_all_reset_reqs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=911778681 -assert nopo stproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_deep_sleep_all_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ce/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_pwrmgr_normal_sleep_all_reset_reqs.911778681 |
| Directory | /workspace/0.chip_sw_pwrmgr_normal_sleep_all_reset_reqs/latest |
| Test location | /workspace/coverage/default/0.chip_sw_pwrmgr_normal_sleep_all_wake_ups.305738203 |
| Short name | T423 |
| Test name | |
| Test status | |
| Simulation time | 7401921728 ps |
| CPU time | 377.1 seconds |
| Started | Aug 12 07:12:24 PM PDT 24 |
| Finished | Aug 12 07:18:41 PM PDT 24 |
| Peak memory | 610768 kb |
| Host | smart-46b3e107-920d-4644-baea-863f15ab9565 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_normal_sleep_all_wake_ups:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=305738203 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_pwrmgr_deep_sleep_all_wake_ups_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work space/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_pwrmgr_normal_sleep_all_wake_ups.305738203 |
| Directory | /workspace/0.chip_sw_pwrmgr_normal_sleep_all_wake_ups/latest |
| Test location | /workspace/coverage/default/0.chip_sw_pwrmgr_normal_sleep_por_reset.293121710 |
| Short name | T1224 |
| Test name | |
| Test status | |
| Simulation time | 6945607668 ps |
| CPU time | 626.12 seconds |
| Started | Aug 12 07:08:50 PM PDT 24 |
| Finished | Aug 12 07:19:16 PM PDT 24 |
| Peak memory | 611268 kb |
| Host | smart-4b347692-adc6-46cf-abc9-b43b5f67e9db |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_normal_sleep_por_reset_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=293121710 -assert nopostpro c +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sleep_por_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag e/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_pwrmgr_normal_sleep_por_reset.293121710 |
| Directory | /workspace/0.chip_sw_pwrmgr_normal_sleep_por_reset/latest |
| Test location | /workspace/coverage/default/0.chip_sw_pwrmgr_random_sleep_power_glitch_reset.1373587455 |
| Short name | T1344 |
| Test name | |
| Test status | |
| Simulation time | 37877649760 ps |
| CPU time | 3105.24 seconds |
| Started | Aug 12 07:08:33 PM PDT 24 |
| Finished | Aug 12 08:00:18 PM PDT 24 |
| Peak memory | 612304 kb |
| Host | smart-52142389-a4a0-4dd3-a806-af7dfd59a29e |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_test_timeout_ns=24_000_000 +sw_build_device=sim_dv +sw_images=pwrmgr_random_sleep_power _glitch_reset_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1373587455 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_random_power_glit ch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_pwrmgr_random_s leep_power_glitch_reset.1373587455 |
| Directory | /workspace/0.chip_sw_pwrmgr_random_sleep_power_glitch_reset/latest |
| Test location | /workspace/coverage/default/0.chip_sw_pwrmgr_sleep_disabled.3720855408 |
| Short name | T767 |
| Test name | |
| Test status | |
| Simulation time | 2899900176 ps |
| CPU time | 260.88 seconds |
| Started | Aug 12 07:08:05 PM PDT 24 |
| Finished | Aug 12 07:12:26 PM PDT 24 |
| Peak memory | 609736 kb |
| Host | smart-e0f72991-9c13-49d3-8469-24e71a26ded4 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_sleep_disabled_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3720855408 -assert nopostproc +UVM_ TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_ log /dev/null -cm_name 0.chip_sw_pwrmgr_sleep_disabled.3720855408 |
| Directory | /workspace/0.chip_sw_pwrmgr_sleep_disabled/latest |
| Test location | /workspace/coverage/default/0.chip_sw_pwrmgr_sleep_power_glitch_reset.430380446 |
| Short name | T991 |
| Test name | |
| Test status | |
| Simulation time | 5996473344 ps |
| CPU time | 444.43 seconds |
| Started | Aug 12 07:07:57 PM PDT 24 |
| Finished | Aug 12 07:15:22 PM PDT 24 |
| Peak memory | 616992 kb |
| Host | smart-e76cb5e0-d6b3-4ab2-b5b2-f7cba679d0b9 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=pwrmgr_sleep_power_glitch_test:1:new_rules,test_rom:0 +c dc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_s eed=430380446 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_main_power_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_pwrmgr_sleep_power_glitch_reset.430380446 |
| Directory | /workspace/0.chip_sw_pwrmgr_sleep_power_glitch_reset/latest |
| Test location | /workspace/coverage/default/0.chip_sw_pwrmgr_sleep_wake_5_bug.2950226641 |
| Short name | T138 |
| Test name | |
| Test status | |
| Simulation time | 6792423344 ps |
| CPU time | 426.01 seconds |
| Started | Aug 12 07:12:50 PM PDT 24 |
| Finished | Aug 12 07:19:56 PM PDT 24 |
| Peak memory | 610964 kb |
| Host | smart-9e17e629-7e2a-41e4-a1c2-1631eb88ff25 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +do_random=1 +sw_build_device=sim_dv +sw_images=pwrmgr_sleep_wake_5_bug_test:1:new_rules,test_r om:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r andom_seed=2950226641 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_pwrmgr_sleep_wake_5_bug.2950226641 |
| Directory | /workspace/0.chip_sw_pwrmgr_sleep_wake_5_bug/latest |
| Test location | /workspace/coverage/default/0.chip_sw_pwrmgr_smoketest.3435022575 |
| Short name | T1014 |
| Test name | |
| Test status | |
| Simulation time | 5748049860 ps |
| CPU time | 448.05 seconds |
| Started | Aug 12 07:10:46 PM PDT 24 |
| Finished | Aug 12 07:18:14 PM PDT 24 |
| Peak memory | 610904 kb |
| Host | smart-d3697dd0-dc84-4be5-b8a2-971d6416303b |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=10000000 +sw_build_device=sim_dv +sw_images=pwrmgr_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3435022575 -asse rt nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera ge/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_pwrmgr_smoketest.3435022575 |
| Directory | /workspace/0.chip_sw_pwrmgr_smoketest/latest |
| Test location | /workspace/coverage/default/0.chip_sw_pwrmgr_sysrst_ctrl_reset.1082210125 |
| Short name | T1197 |
| Test name | |
| Test status | |
| Simulation time | 7739680264 ps |
| CPU time | 1497.03 seconds |
| Started | Aug 12 07:10:53 PM PDT 24 |
| Finished | Aug 12 07:35:50 PM PDT 24 |
| Peak memory | 610312 kb |
| Host | smart-2cbe17c0-ec6c-43dc-85ac-ce21f177e6d8 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_sysrst_ctrl_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1082210125 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sysrst_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_pwrmgr_sysrst_ctrl_reset.1082210125 |
| Directory | /workspace/0.chip_sw_pwrmgr_sysrst_ctrl_reset/latest |
| Test location | /workspace/coverage/default/0.chip_sw_pwrmgr_usb_clk_disabled_when_active.2451043318 |
| Short name | T1130 |
| Test name | |
| Test status | |
| Simulation time | 5802374972 ps |
| CPU time | 597.83 seconds |
| Started | Aug 12 07:09:22 PM PDT 24 |
| Finished | Aug 12 07:19:20 PM PDT 24 |
| Peak memory | 610936 kb |
| Host | smart-e7ad9b20-8a5a-42c9-b1ad-a4dc6c53ba55 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_usb_clk_disabled_when_active_test:1:new_rules,test_rom:0 +cdc_instrumentation_enable d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2451043318 -assert no postproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de fault.vdb -cm_log /dev/null -cm_name 0.chip_sw_pwrmgr_usb_clk_disabled_when_active.2451043318 |
| Directory | /workspace/0.chip_sw_pwrmgr_usb_clk_disabled_when_active/latest |
| Test location | /workspace/coverage/default/0.chip_sw_pwrmgr_usbdev_smoketest.1152439896 |
| Short name | T1425 |
| Test name | |
| Test status | |
| Simulation time | 4801027232 ps |
| CPU time | 410.4 seconds |
| Started | Aug 12 07:13:21 PM PDT 24 |
| Finished | Aug 12 07:20:11 PM PDT 24 |
| Peak memory | 610640 kb |
| Host | smart-b0188640-07a0-4d43-9a0f-b4bfa58e2e5d |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_usbdev_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1152439896 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_pwrmgr_usbdev_smoketest.1152439896 |
| Directory | /workspace/0.chip_sw_pwrmgr_usbdev_smoketest/latest |
| Test location | /workspace/coverage/default/0.chip_sw_pwrmgr_wdog_reset.2801605593 |
| Short name | T1258 |
| Test name | |
| Test status | |
| Simulation time | 5987775872 ps |
| CPU time | 643.98 seconds |
| Started | Aug 12 07:09:17 PM PDT 24 |
| Finished | Aug 12 07:20:01 PM PDT 24 |
| Peak memory | 610808 kb |
| Host | smart-b71a981d-183a-47c8-96ad-f6e60c0df72d |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=pwrmgr_wdog_reset_reqs_test:1:new_rules,test_rom:0 +cdc_inst rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=280 1605593 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_pwrmgr_wdog_reset.2801605593 |
| Directory | /workspace/0.chip_sw_pwrmgr_wdog_reset/latest |
| Test location | /workspace/coverage/default/0.chip_sw_rom_ctrl_integrity_check.3965742097 |
| Short name | T8 |
| Test name | |
| Test status | |
| Simulation time | 9784400582 ps |
| CPU time | 676.84 seconds |
| Started | Aug 12 07:10:51 PM PDT 24 |
| Finished | Aug 12 07:22:08 PM PDT 24 |
| Peak memory | 610960 kb |
| Host | smart-b0ac3636-8b92-4f0c-ae92-1ba3b44fcbd8 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=rom_ctrl_integrity_check_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3965742097 -assert nopostproc +U VM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rom_ctrl_integrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co verage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_rom_ctrl_integrity_check.3965742097 |
| Directory | /workspace/0.chip_sw_rom_ctrl_integrity_check/latest |
| Test location | /workspace/coverage/default/0.chip_sw_rstmgr_cpu_info.1432576761 |
| Short name | T267 |
| Test name | |
| Test status | |
| Simulation time | 5575715528 ps |
| CPU time | 580.12 seconds |
| Started | Aug 12 07:07:14 PM PDT 24 |
| Finished | Aug 12 07:16:54 PM PDT 24 |
| Peak memory | 610908 kb |
| Host | smart-a9ab463f-77b8-4b86-ad9b-bc27a65096f2 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=rstmgr_cpu_info_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1432576761 -assert nopostproc +UVM_TESTNA ME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 0.chip_sw_rstmgr_cpu_info.1432576761 |
| Directory | /workspace/0.chip_sw_rstmgr_cpu_info/latest |
| Test location | /workspace/coverage/default/0.chip_sw_rstmgr_rst_cnsty_escalation.4242507797 |
| Short name | T1308 |
| Test name | |
| Test status | |
| Simulation time | 6504961240 ps |
| CPU time | 668.92 seconds |
| Started | Aug 12 07:06:45 PM PDT 24 |
| Finished | Aug 12 07:17:54 PM PDT 24 |
| Peak memory | 642128 kb |
| Host | smart-09a051dd-607d-4b93-8005-56a81c77785e |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 4242507797 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rstmgr_cnsty_fault_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_rstmgr_rst_cnsty_escalation.4242507797 |
| Directory | /workspace/0.chip_sw_rstmgr_rst_cnsty_escalation/latest |
| Test location | /workspace/coverage/default/0.chip_sw_rstmgr_smoketest.1563691468 |
| Short name | T301 |
| Test name | |
| Test status | |
| Simulation time | 2603724088 ps |
| CPU time | 157.23 seconds |
| Started | Aug 12 07:10:17 PM PDT 24 |
| Finished | Aug 12 07:12:54 PM PDT 24 |
| Peak memory | 609848 kb |
| Host | smart-f53b0b44-1d0c-4c5e-ae1c-4681cac32786 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=rstmgr_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1563691468 -assert nopostproc +UVM_TESTNAME=c hip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n ull -cm_name 0.chip_sw_rstmgr_smoketest.1563691468 |
| Directory | /workspace/0.chip_sw_rstmgr_smoketest/latest |
| Test location | /workspace/coverage/default/0.chip_sw_rstmgr_sw_req.1443957314 |
| Short name | T388 |
| Test name | |
| Test status | |
| Simulation time | 4106355140 ps |
| CPU time | 281.49 seconds |
| Started | Aug 12 07:06:42 PM PDT 24 |
| Finished | Aug 12 07:11:24 PM PDT 24 |
| Peak memory | 610476 kb |
| Host | smart-a25d8452-4131-4824-8437-d0418cff1fa9 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=rstmgr_sw_req_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1443957314 -assert nopostproc +UVM_TESTNAME =chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 0.chip_sw_rstmgr_sw_req.1443957314 |
| Directory | /workspace/0.chip_sw_rstmgr_sw_req/latest |
| Test location | /workspace/coverage/default/0.chip_sw_rstmgr_sw_rst.3352423043 |
| Short name | T415 |
| Test name | |
| Test status | |
| Simulation time | 3038866032 ps |
| CPU time | 225.84 seconds |
| Started | Aug 12 07:09:16 PM PDT 24 |
| Finished | Aug 12 07:13:02 PM PDT 24 |
| Peak memory | 610132 kb |
| Host | smart-579bda20-a3d1-4584-beca-13eb7d8caa28 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=rstmgr_sw_rst_ctrl_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3352423043 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_rstmgr_sw_rst.3352423043 |
| Directory | /workspace/0.chip_sw_rstmgr_sw_rst/latest |
| Test location | /workspace/coverage/default/0.chip_sw_rv_core_ibex_icache_invalidate.3752582919 |
| Short name | T306 |
| Test name | |
| Test status | |
| Simulation time | 2661455252 ps |
| CPU time | 224.97 seconds |
| Started | Aug 12 07:12:14 PM PDT 24 |
| Finished | Aug 12 07:15:59 PM PDT 24 |
| Peak memory | 609156 kb |
| Host | smart-b3b62fd8-b9dd-4ce8-93fc-f0ab314bb6ff |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=rv_core_ibex_icache_invalidate_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3752582919 -assert nopostp roc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rv_core_ibex_icache_invalidate_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_rv_core_ibex_icache_invalidate.3752582919 |
| Directory | /workspace/0.chip_sw_rv_core_ibex_icache_invalidate/latest |
| Test location | /workspace/coverage/default/0.chip_sw_rv_core_ibex_lockstep_glitch.2217965861 |
| Short name | T966 |
| Test name | |
| Test status | |
| Simulation time | 2958486000 ps |
| CPU time | 190.02 seconds |
| Started | Aug 12 07:11:59 PM PDT 24 |
| Finished | Aug 12 07:15:10 PM PDT 24 |
| Peak memory | 647476 kb |
| Host | smart-711274da-f9c0-44a6-922e-1cf1ccdeba6e |
| User | root |
| Command | /workspace/default/simv +disable_assert_final_checks +sw_build_device=sim_dv +sw_images=aes_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2217965861 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rv_core_ibex_lockstep_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_rv_core_ibex_lockstep_glitch.2217965861 |
| Directory | /workspace/0.chip_sw_rv_core_ibex_lockstep_glitch/latest |
| Test location | /workspace/coverage/default/0.chip_sw_rv_core_ibex_rnd.4082428783 |
| Short name | T1230 |
| Test name | |
| Test status | |
| Simulation time | 5245279096 ps |
| CPU time | 1148.47 seconds |
| Started | Aug 12 07:08:09 PM PDT 24 |
| Finished | Aug 12 07:27:18 PM PDT 24 |
| Peak memory | 610440 kb |
| Host | smart-480770a2-b7ea-4dd5-88ec-d3dbdd7c11bc |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=20_000_000 +rng_srate_value_max=32 +sw_build_device=sim_dv +sw_images=rv_core_ibex_rnd_test:1:new_rules,te st_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n tb_random_seed=4082428783 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_rv_core_ibex_rnd.4082428783 |
| Directory | /workspace/0.chip_sw_rv_core_ibex_rnd/latest |
| Test location | /workspace/coverage/default/0.chip_sw_rv_dm_access_after_wakeup.663051687 |
| Short name | T783 |
| Test name | |
| Test status | |
| Simulation time | 5817064144 ps |
| CPU time | 486.92 seconds |
| Started | Aug 12 07:08:37 PM PDT 24 |
| Finished | Aug 12 07:16:45 PM PDT 24 |
| Peak memory | 620356 kb |
| Host | smart-f5213491-b0da-420f-a89f-43e989dcffdf |
| User | root |
| Command | /workspace/default/simv +use_jtag_dmi=1 +sw_build_device=sim_dv +sw_images=rv_dm_access_after_wakeup_rma:1:new_rules,test_rom:0 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=663051687 -asser t nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rv_dm_access_after_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_rv_dm_access_after_wakeup.663051687 |
| Directory | /workspace/0.chip_sw_rv_dm_access_after_wakeup/latest |
| Test location | /workspace/coverage/default/0.chip_sw_rv_dm_ndm_reset_req_when_cpu_halted.2026282903 |
| Short name | T70 |
| Test name | |
| Test status | |
| Simulation time | 4370804294 ps |
| CPU time | 538.19 seconds |
| Started | Aug 12 07:09:35 PM PDT 24 |
| Finished | Aug 12 07:18:33 PM PDT 24 |
| Peak memory | 619288 kb |
| Host | smart-bbbf39d1-bad9-4c88-829c-ce3538cb3c1e |
| User | root |
| Command | /workspace/default/simv +use_jtag_dmi=1 +sw_build_device=sim_dv +sw_images=rv_dm_ndm_reset_req_when_cpu_halted_rma:1:new_rules,test_rom:0 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=202628 2903 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rv_dm_ndm_reset_when_cpu_halted_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_rv_dm_ndm_reset_req_when_cpu_halted.2026282903 |
| Directory | /workspace/0.chip_sw_rv_dm_ndm_reset_req_when_cpu_halted/latest |
| Test location | /workspace/coverage/default/0.chip_sw_rv_plic_smoketest.2564003652 |
| Short name | T990 |
| Test name | |
| Test status | |
| Simulation time | 2756129032 ps |
| CPU time | 301.81 seconds |
| Started | Aug 12 07:11:58 PM PDT 24 |
| Finished | Aug 12 07:17:01 PM PDT 24 |
| Peak memory | 609992 kb |
| Host | smart-d9f02199-f398-470c-9dd3-4a06217ab850 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=rv_plic_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2564003652 -assert nopostproc +UVM_TESTNAME= chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/ null -cm_name 0.chip_sw_rv_plic_smoketest.2564003652 |
| Directory | /workspace/0.chip_sw_rv_plic_smoketest/latest |
| Test location | /workspace/coverage/default/0.chip_sw_rv_timer_irq.940421844 |
| Short name | T1120 |
| Test name | |
| Test status | |
| Simulation time | 2976969208 ps |
| CPU time | 211.99 seconds |
| Started | Aug 12 07:07:23 PM PDT 24 |
| Finished | Aug 12 07:10:55 PM PDT 24 |
| Peak memory | 610124 kb |
| Host | smart-723b5cdb-2d4a-4002-a9ef-cabb867d1e23 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=rv_timer_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=940421844 -assert nopostproc +UVM_TESTNAME= chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/ null -cm_name 0.chip_sw_rv_timer_irq.940421844 |
| Directory | /workspace/0.chip_sw_rv_timer_irq/latest |
| Test location | /workspace/coverage/default/0.chip_sw_rv_timer_smoketest.2492933051 |
| Short name | T256 |
| Test name | |
| Test status | |
| Simulation time | 2715012744 ps |
| CPU time | 222.7 seconds |
| Started | Aug 12 07:10:41 PM PDT 24 |
| Finished | Aug 12 07:14:24 PM PDT 24 |
| Peak memory | 608760 kb |
| Host | smart-a8f63207-9477-4603-8870-98d6b022eba6 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=rv_timer_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2492933051 -assert nopostproc +UVM_TESTNAME =chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 0.chip_sw_rv_timer_smoketest.2492933051 |
| Directory | /workspace/0.chip_sw_rv_timer_smoketest/latest |
| Test location | /workspace/coverage/default/0.chip_sw_sensor_ctrl_status.203644677 |
| Short name | T155 |
| Test name | |
| Test status | |
| Simulation time | 3167718691 ps |
| CPU time | 313.82 seconds |
| Started | Aug 12 07:09:43 PM PDT 24 |
| Finished | Aug 12 07:14:57 PM PDT 24 |
| Peak memory | 609980 kb |
| Host | smart-14e25fe5-a259-4873-a388-a3bcc9961bfa |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=40_000_000 +sw_build_device=sim_dv +sw_images=sensor_ctrl_status_test:1:new_rules,test_rom:0 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2036446 77 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sensor_ctrl_status_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_sensor_ctrl_status.203644677 |
| Directory | /workspace/0.chip_sw_sensor_ctrl_status/latest |
| Test location | /workspace/coverage/default/0.chip_sw_sleep_pin_retention.740349720 |
| Short name | T61 |
| Test name | |
| Test status | |
| Simulation time | 2780154152 ps |
| CPU time | 337.78 seconds |
| Started | Aug 12 07:09:46 PM PDT 24 |
| Finished | Aug 12 07:15:25 PM PDT 24 |
| Peak memory | 609376 kb |
| Host | smart-ca2823d2-5070-4f70-acfa-8b13614bcef8 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=sleep_pin_retention_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=740349720 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sleep_pin_retention_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defa ult.vdb -cm_log /dev/null -cm_name 0.chip_sw_sleep_pin_retention.740349720 |
| Directory | /workspace/0.chip_sw_sleep_pin_retention/latest |
| Test location | /workspace/coverage/default/0.chip_sw_sleep_pwm_pulses.3545184594 |
| Short name | T307 |
| Test name | |
| Test status | |
| Simulation time | 7927818424 ps |
| CPU time | 1386.14 seconds |
| Started | Aug 12 07:06:43 PM PDT 24 |
| Finished | Aug 12 07:29:50 PM PDT 24 |
| Peak memory | 611228 kb |
| Host | smart-ff261eb6-e940-435b-ab6a-7dc9afa1a834 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=sleep_pwm_pulses_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3545184594 -assert nopostproc +UVM_TESTN AME=chip_base_test +UVM_TEST_SEQ=chip_sw_pwm_pulses_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm _log /dev/null -cm_name 0.chip_sw_sleep_pwm_pulses.3545184594 |
| Directory | /workspace/0.chip_sw_sleep_pwm_pulses/latest |
| Test location | /workspace/coverage/default/0.chip_sw_sleep_sram_ret_contents_no_scramble.3918816262 |
| Short name | T980 |
| Test name | |
| Test status | |
| Simulation time | 7290845736 ps |
| CPU time | 825.05 seconds |
| Started | Aug 12 07:09:15 PM PDT 24 |
| Finished | Aug 12 07:23:00 PM PDT 24 |
| Peak memory | 611104 kb |
| Host | smart-d67133c4-9236-4829-8c96-d09782c2fd7b |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=20_000_000 +en_scb_tl_err_chk=0 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=sram _ctrl_sleep_sram_ret_contents_no_scramble_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3918816262 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_S EQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_sl eep_sram_ret_contents_no_scramble.3918816262 |
| Directory | /workspace/0.chip_sw_sleep_sram_ret_contents_no_scramble/latest |
| Test location | /workspace/coverage/default/0.chip_sw_sleep_sram_ret_contents_scramble.4064707536 |
| Short name | T983 |
| Test name | |
| Test status | |
| Simulation time | 9118427182 ps |
| CPU time | 680.12 seconds |
| Started | Aug 12 07:10:53 PM PDT 24 |
| Finished | Aug 12 07:22:14 PM PDT 24 |
| Peak memory | 611072 kb |
| Host | smart-99a463a9-8827-46d7-846f-9953288d323a |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=20_000_000 +en_scb_tl_err_chk=0 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=sram _ctrl_sleep_sram_ret_contents_scramble_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4064707536 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ= chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_sleep _sram_ret_contents_scramble.4064707536 |
| Directory | /workspace/0.chip_sw_sleep_sram_ret_contents_scramble/latest |
| Test location | /workspace/coverage/default/0.chip_sw_spi_device_pass_through.3760234492 |
| Short name | T13 |
| Test name | |
| Test status | |
| Simulation time | 6316448835 ps |
| CPU time | 790.95 seconds |
| Started | Aug 12 07:07:14 PM PDT 24 |
| Finished | Aug 12 07:20:26 PM PDT 24 |
| Peak memory | 625244 kb |
| Host | smart-09b7b9a5-cc2c-4f9c-9872-5092dae87e33 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=spi_passthrough_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3760234492 -assert nopostproc +UVM_TESTNA ME=chip_base_test +UVM_TEST_SEQ=chip_sw_spi_passthrough_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_spi_device_pass_through.3760234492 |
| Directory | /workspace/0.chip_sw_spi_device_pass_through/latest |
| Test location | /workspace/coverage/default/0.chip_sw_spi_device_tpm.1115531442 |
| Short name | T45 |
| Test name | |
| Test status | |
| Simulation time | 3912507210 ps |
| CPU time | 312.24 seconds |
| Started | Aug 12 07:06:36 PM PDT 24 |
| Finished | Aug 12 07:11:48 PM PDT 24 |
| Peak memory | 618944 kb |
| Host | smart-30bd51e8-f5f4-4810-a021-4c37f69f22e5 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=spi_device_tpm_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1115531442 -assert nopostproc +UVM_T ESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_spi_device_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default .vdb -cm_log /dev/null -cm_name 0.chip_sw_spi_device_tpm.1115531442 |
| Directory | /workspace/0.chip_sw_spi_device_tpm/latest |
| Test location | /workspace/coverage/default/0.chip_sw_spi_host_tx_rx.3708502036 |
| Short name | T37 |
| Test name | |
| Test status | |
| Simulation time | 2648070632 ps |
| CPU time | 233.09 seconds |
| Started | Aug 12 07:08:44 PM PDT 24 |
| Finished | Aug 12 07:12:37 PM PDT 24 |
| Peak memory | 609332 kb |
| Host | smart-44cfae2c-d59b-40a9-a7a0-137b2634d187 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=spi_host_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3708502036 -assert nopostproc +UVM_TESTNAM E=chip_base_test +UVM_TEST_SEQ=chip_sw_spi_host_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb - cm_log /dev/null -cm_name 0.chip_sw_spi_host_tx_rx.3708502036 |
| Directory | /workspace/0.chip_sw_spi_host_tx_rx/latest |
| Test location | /workspace/coverage/default/0.chip_sw_sram_ctrl_scrambled_access.1179799221 |
| Short name | T289 |
| Test name | |
| Test status | |
| Simulation time | 3765705724 ps |
| CPU time | 616.55 seconds |
| Started | Aug 12 07:10:30 PM PDT 24 |
| Finished | Aug 12 07:20:48 PM PDT 24 |
| Peak memory | 611052 kb |
| Host | smart-f6460c49-7cec-480a-aa58-52cf8a0bdc4f |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=12_000_000 +en_scb_tl_err_chk=0 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=sram _ctrl_scrambled_access_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1179799221 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sram_ctr l_scrambled_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw _sram_ctrl_scrambled_access.1179799221 |
| Directory | /workspace/0.chip_sw_sram_ctrl_scrambled_access/latest |
| Test location | /workspace/coverage/default/0.chip_sw_sram_ctrl_scrambled_access_jitter_en.3273913774 |
| Short name | T97 |
| Test name | |
| Test status | |
| Simulation time | 4708224706 ps |
| CPU time | 620.26 seconds |
| Started | Aug 12 07:09:43 PM PDT 24 |
| Finished | Aug 12 07:20:03 PM PDT 24 |
| Peak memory | 611468 kb |
| Host | smart-614e4065-e13e-49fb-be91-e86c81b90a44 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=12_000_000 +bypass_alert_ready_to_end_check=1 +en_jitter=1 +en_scb_tl_err_chk=0 +sw_build_device=sim_dv +s w_images=sram_ctrl_scrambled_access_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3273913774 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chi p_sw_sram_ctrl_scrambled_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n ame 0.chip_sw_sram_ctrl_scrambled_access_jitter_en.3273913774 |
| Directory | /workspace/0.chip_sw_sram_ctrl_scrambled_access_jitter_en/latest |
| Test location | /workspace/coverage/default/0.chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq.3752944996 |
| Short name | T293 |
| Test name | |
| Test status | |
| Simulation time | 4848717284 ps |
| CPU time | 558.62 seconds |
| Started | Aug 12 07:10:41 PM PDT 24 |
| Finished | Aug 12 07:20:00 PM PDT 24 |
| Peak memory | 611256 kb |
| Host | smart-70ef3967-491a-4d2e-8044-88a70fa3afde |
| User | root |
| Command | /workspace/default/simv +mem_sel=main +sw_test_timeout_ns=12_000_000 +bypass_alert_ready_to_end_check=1 +en_jitter=1 +en_scb_tl_err_chk=0 +cal_sys_clk _70mhz=1 +sw_build_device=sim_dv +sw_images=sram_ctrl_scrambled_access_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3752944996 -assert nopostproc +UVM_TESTNA ME=chip_base_test +UVM_TEST_SEQ=chip_sw_sram_ctrl_scrambled_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/ default.vdb -cm_log /dev/null -cm_name 0.chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq.3752944996 |
| Directory | /workspace/0.chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq/latest |
| Test location | /workspace/coverage/default/0.chip_sw_sram_ctrl_smoketest.3839395703 |
| Short name | T1002 |
| Test name | |
| Test status | |
| Simulation time | 3084154466 ps |
| CPU time | 205.6 seconds |
| Started | Aug 12 07:14:09 PM PDT 24 |
| Finished | Aug 12 07:17:35 PM PDT 24 |
| Peak memory | 610076 kb |
| Host | smart-79e5b9a3-b1a8-4790-9759-7940adbfdd92 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=sram_ctrl_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3839395703 -assert nopostproc +UVM_TESTNAM E=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 0.chip_sw_sram_ctrl_smoketest.3839395703 |
| Directory | /workspace/0.chip_sw_sram_ctrl_smoketest/latest |
| Test location | /workspace/coverage/default/0.chip_sw_sysrst_ctrl_ec_rst_l.4111786125 |
| Short name | T24 |
| Test name | |
| Test status | |
| Simulation time | 20803044185 ps |
| CPU time | 3289.32 seconds |
| Started | Aug 12 07:09:08 PM PDT 24 |
| Finished | Aug 12 08:03:58 PM PDT 24 |
| Peak memory | 611216 kb |
| Host | smart-79a4df28-9203-4201-a1f8-8e6d4a7c6b3d |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=sysrst_ctrl_ec_rst_l_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4111786125 -assert nopostproc +UVM_T ESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sysrst_ctrl_ec_rst_l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/d efault.vdb -cm_log /dev/null -cm_name 0.chip_sw_sysrst_ctrl_ec_rst_l.4111786125 |
| Directory | /workspace/0.chip_sw_sysrst_ctrl_ec_rst_l/latest |
| Test location | /workspace/coverage/default/0.chip_sw_sysrst_ctrl_in_irq.3326297015 |
| Short name | T1417 |
| Test name | |
| Test status | |
| Simulation time | 5505408030 ps |
| CPU time | 778.51 seconds |
| Started | Aug 12 07:08:34 PM PDT 24 |
| Finished | Aug 12 07:21:35 PM PDT 24 |
| Peak memory | 614012 kb |
| Host | smart-e62f9ab2-3af2-4c51-8a52-4cec079af8e6 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=sysrst_ctrl_in_irq_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3326297015 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sysrst_ctrl_in_irq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau lt.vdb -cm_log /dev/null -cm_name 0.chip_sw_sysrst_ctrl_in_irq.3326297015 |
| Directory | /workspace/0.chip_sw_sysrst_ctrl_in_irq/latest |
| Test location | /workspace/coverage/default/0.chip_sw_sysrst_ctrl_inputs.2619408583 |
| Short name | T1256 |
| Test name | |
| Test status | |
| Simulation time | 3174752490 ps |
| CPU time | 298.51 seconds |
| Started | Aug 12 07:07:59 PM PDT 24 |
| Finished | Aug 12 07:12:58 PM PDT 24 |
| Peak memory | 613772 kb |
| Host | smart-541f666a-3043-460b-9f93-ed206351566c |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=sysrst_ctrl_inputs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2619408583 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sysrst_ctrl_inputs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau lt.vdb -cm_log /dev/null -cm_name 0.chip_sw_sysrst_ctrl_inputs.2619408583 |
| Directory | /workspace/0.chip_sw_sysrst_ctrl_inputs/latest |
| Test location | /workspace/coverage/default/0.chip_sw_sysrst_ctrl_outputs.325185169 |
| Short name | T212 |
| Test name | |
| Test status | |
| Simulation time | 3203480572 ps |
| CPU time | 344.03 seconds |
| Started | Aug 12 07:10:33 PM PDT 24 |
| Finished | Aug 12 07:16:17 PM PDT 24 |
| Peak memory | 609668 kb |
| Host | smart-610a1054-7444-4714-8cb5-87f8405eccc1 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=sysrst_ctrl_outputs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=325185169 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sysrst_ctrl_outputs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defa ult.vdb -cm_log /dev/null -cm_name 0.chip_sw_sysrst_ctrl_outputs.325185169 |
| Directory | /workspace/0.chip_sw_sysrst_ctrl_outputs/latest |
| Test location | /workspace/coverage/default/0.chip_sw_sysrst_ctrl_reset.2521651991 |
| Short name | T1391 |
| Test name | |
| Test status | |
| Simulation time | 22034899916 ps |
| CPU time | 1869.65 seconds |
| Started | Aug 12 07:09:10 PM PDT 24 |
| Finished | Aug 12 07:40:21 PM PDT 24 |
| Peak memory | 615376 kb |
| Host | smart-b7577e5d-d952-4ecc-9f48-1d7efad7f59d |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=36_000_000 +sw_build_device=sim_dv +sw_images=sysrst_ctrl_reset_test:1:new_rules,test_rom:0 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25216519 91 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sysrst_ctrl_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_sysrst_ctrl_reset.2521651991 |
| Directory | /workspace/0.chip_sw_sysrst_ctrl_reset/latest |
| Test location | /workspace/coverage/default/0.chip_sw_sysrst_ctrl_ulp_z3_wakeup.3692007875 |
| Short name | T41 |
| Test name | |
| Test status | |
| Simulation time | 5646985800 ps |
| CPU time | 549.94 seconds |
| Started | Aug 12 07:09:29 PM PDT 24 |
| Finished | Aug 12 07:18:40 PM PDT 24 |
| Peak memory | 610256 kb |
| Host | smart-127456b9-e69c-4adb-82b3-27435399ef2c |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=sysrst_ctrl_ulp_z3_wakeup_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3692007875 -assert nopostproc + UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sysrst_ctrl_ulp_z3_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/ coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_sysrst_ctrl_ulp_z3_wakeup.3692007875 |
| Directory | /workspace/0.chip_sw_sysrst_ctrl_ulp_z3_wakeup/latest |
| Test location | /workspace/coverage/default/0.chip_sw_uart_rand_baudrate.1197231634 |
| Short name | T1125 |
| Test name | |
| Test status | |
| Simulation time | 4585219640 ps |
| CPU time | 487.55 seconds |
| Started | Aug 12 07:07:33 PM PDT 24 |
| Finished | Aug 12 07:15:41 PM PDT 24 |
| Peak memory | 624960 kb |
| Host | smart-d6088a23-61a4-404c-8bae-2ba8c4d5ca87 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random _seed=1197231634 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_uart_rand_baudrate.1197231634 |
| Directory | /workspace/0.chip_sw_uart_rand_baudrate/latest |
| Test location | /workspace/coverage/default/0.chip_sw_uart_smoketest.1626138149 |
| Short name | T1060 |
| Test name | |
| Test status | |
| Simulation time | 3365480900 ps |
| CPU time | 202.57 seconds |
| Started | Aug 12 07:15:21 PM PDT 24 |
| Finished | Aug 12 07:18:44 PM PDT 24 |
| Peak memory | 610384 kb |
| Host | smart-e1829538-ab25-49cc-b34a-afeef7dc46bd |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=uart_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1626138149 -assert nopostproc +UVM_TESTNAME=chi p_base_test +UVM_TEST_SEQ=chip_sw_uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 0.chip_sw_uart_smoketest.1626138149 |
| Directory | /workspace/0.chip_sw_uart_smoketest/latest |
| Test location | /workspace/coverage/default/0.chip_sw_uart_tx_rx_alt_clk_freq.1236189096 |
| Short name | T1209 |
| Test name | |
| Test status | |
| Simulation time | 8664465048 ps |
| CPU time | 1956.37 seconds |
| Started | Aug 12 07:08:09 PM PDT 24 |
| Finished | Aug 12 07:40:47 PM PDT 24 |
| Peak memory | 624000 kb |
| Host | smart-be9849b9-3c91-41c1-bffe-430d328818e3 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=80_000_000 +chip_clock_source=ChipClockSourceExternal96Mhz +calibrate_usb_clk=1 +sw_build_device=sim_dv +s w_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1236189096 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_b audrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_uart_tx_rx _alt_clk_freq.1236189096 |
| Directory | /workspace/0.chip_sw_uart_tx_rx_alt_clk_freq/latest |
| Test location | /workspace/coverage/default/0.chip_sw_uart_tx_rx_alt_clk_freq_low_speed.1226347463 |
| Short name | T1075 |
| Test name | |
| Test status | |
| Simulation time | 13573656765 ps |
| CPU time | 1986.86 seconds |
| Started | Aug 12 07:09:04 PM PDT 24 |
| Finished | Aug 12 07:42:12 PM PDT 24 |
| Peak memory | 624992 kb |
| Host | smart-fde9047b-c38d-4273-8ef0-154d1ccef5eb |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +chip_clock_source=ChipClockSourceExternal48Mhz +sw_build_device=sim_dv +s w_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1226347463 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_b audrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_uart_tx_rx _alt_clk_freq_low_speed.1226347463 |
| Directory | /workspace/0.chip_sw_uart_tx_rx_alt_clk_freq_low_speed/latest |
| Test location | /workspace/coverage/default/0.chip_sw_uart_tx_rx_bootstrap.612929844 |
| Short name | T1200 |
| Test name | |
| Test status | |
| Simulation time | 79132576321 ps |
| CPU time | 13481.1 seconds |
| Started | Aug 12 07:08:35 PM PDT 24 |
| Finished | Aug 12 10:53:17 PM PDT 24 |
| Peak memory | 636508 kb |
| Host | smart-32ba7708-cf6e-4fdf-8ef5-a6cc1322f9d1 |
| User | root |
| Command | /workspace/default/simv +use_spi_load_bootstrap=1 +calibrate_usb_clk=1 +test_timeout_ns=160_000_000 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test :1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=612929844 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_uart_tx_rx_bootstrap.612929844 |
| Directory | /workspace/0.chip_sw_uart_tx_rx_bootstrap/latest |
| Test location | /workspace/coverage/default/0.chip_sw_uart_tx_rx_idx1.284614861 |
| Short name | T1386 |
| Test name | |
| Test status | |
| Simulation time | 4753393828 ps |
| CPU time | 740.53 seconds |
| Started | Aug 12 07:10:21 PM PDT 24 |
| Finished | Aug 12 07:22:43 PM PDT 24 |
| Peak memory | 624596 kb |
| Host | smart-dab453b6-37a3-4ed4-ace8-e86f83683b0b |
| User | root |
| Command | /workspace/default/simv +uart_idx=1 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=284614861 -as sert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac e/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_uart_tx_rx_idx1.284614861 |
| Directory | /workspace/0.chip_sw_uart_tx_rx_idx1/latest |
| Test location | /workspace/coverage/default/0.chip_sw_uart_tx_rx_idx2.1195383115 |
| Short name | T1171 |
| Test name | |
| Test status | |
| Simulation time | 4312629028 ps |
| CPU time | 663.32 seconds |
| Started | Aug 12 07:11:24 PM PDT 24 |
| Finished | Aug 12 07:22:28 PM PDT 24 |
| Peak memory | 624320 kb |
| Host | smart-5db3425a-ccc3-44c3-bcde-d2fb2fa9ff6b |
| User | root |
| Command | /workspace/default/simv +uart_idx=2 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1195383115 -a ssert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ce/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_uart_tx_rx_idx2.1195383115 |
| Directory | /workspace/0.chip_sw_uart_tx_rx_idx2/latest |
| Test location | /workspace/coverage/default/0.chip_sw_usb_ast_clk_calib.2663441444 |
| Short name | T1393 |
| Test name | |
| Test status | |
| Simulation time | 3128204017 ps |
| CPU time | 296.03 seconds |
| Started | Aug 12 07:07:54 PM PDT 24 |
| Finished | Aug 12 07:12:50 PM PDT 24 |
| Peak memory | 610544 kb |
| Host | smart-0a7b154f-dad1-4306-a4f5-8be214f89da6 |
| User | root |
| Command | /workspace/default/simv +usb_max_drift=1 +usb_fast_sof=1 +sw_build_device=sim_dv +sw_images=ast_usb_clk_calib:1:new_rules,test_rom:0 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2663441444 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_usb_ast_clk_calib_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_usb_ast_clk_calib.2663441444 |
| Directory | /workspace/0.chip_sw_usb_ast_clk_calib/latest |
| Test location | /workspace/coverage/default/0.chip_sw_usbdev_dpi.81015872 |
| Short name | T1394 |
| Test name | |
| Test status | |
| Simulation time | 11798617456 ps |
| CPU time | 2955.01 seconds |
| Started | Aug 12 07:10:01 PM PDT 24 |
| Finished | Aug 12 07:59:17 PM PDT 24 |
| Peak memory | 610520 kb |
| Host | smart-6aaad4ac-adc8-4cb2-960e-9efa818e5459 |
| User | root |
| Command | /workspace/default/simv +uart_idx=0 +calibrate_usb_clk=1 +sw_test_timeout_ns=30_000_000 +sw_build_device=sim_dv +sw_images=usbdev_test:1:new_rules,tes t_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +nt b_random_seed=81015872 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_usbdev_dpi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_usbdev_dpi.81015872 |
| Directory | /workspace/0.chip_sw_usbdev_dpi/latest |
| Test location | /workspace/coverage/default/0.chip_sw_usbdev_pincfg.2740337546 |
| Short name | T25 |
| Test name | |
| Test status | |
| Simulation time | 31752535590 ps |
| CPU time | 7219.32 seconds |
| Started | Aug 12 07:07:49 PM PDT 24 |
| Finished | Aug 12 09:08:10 PM PDT 24 |
| Peak memory | 610612 kb |
| Host | smart-54e83d10-7daa-408a-8ec8-6827bd34c717 |
| User | root |
| Command | /workspace/default/simv +uart_idx=0 +calibrate_usb_clk=1 +sw_test_timeout_ns=100_000_000 +sw_build_device=sim_dv +sw_images=usbdev_pincfg_test:1:new_r ules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim .tcl +ntb_random_seed=2740337546 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_usbdev_dpi_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_usbdev_pincfg.2740337546 |
| Directory | /workspace/0.chip_sw_usbdev_pincfg/latest |
| Test location | /workspace/coverage/default/0.chip_sw_usbdev_pullup.2225010098 |
| Short name | T78 |
| Test name | |
| Test status | |
| Simulation time | 2966625564 ps |
| CPU time | 278.16 seconds |
| Started | Aug 12 07:07:42 PM PDT 24 |
| Finished | Aug 12 07:12:21 PM PDT 24 |
| Peak memory | 610232 kb |
| Host | smart-091c1d18-f1a1-4649-904c-d4e3f20da6cf |
| User | root |
| Command | /workspace/default/simv +uart_idx=0 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=usbdev_pullup_test:1:new_rules,test_rom:0 +cdc_instrumenta tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2225010098 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_usbdev_dpi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work space/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_usbdev_pullup.2225010098 |
| Directory | /workspace/0.chip_sw_usbdev_pullup/latest |
| Test location | /workspace/coverage/default/0.chip_sw_usbdev_setuprx.2651881589 |
| Short name | T159 |
| Test name | |
| Test status | |
| Simulation time | 4023933000 ps |
| CPU time | 489.95 seconds |
| Started | Aug 12 07:07:22 PM PDT 24 |
| Finished | Aug 12 07:15:32 PM PDT 24 |
| Peak memory | 610184 kb |
| Host | smart-50dd11eb-9e88-4c9d-8477-f84c540d07e4 |
| User | root |
| Command | /workspace/default/simv +uart_idx=0 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=usbdev_setuprx_test:1:new_rules,test_rom:0 +cdc_instrument ation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=265188158 9 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_usbdev_dpi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_usbdev_setuprx.2651881589 |
| Directory | /workspace/0.chip_sw_usbdev_setuprx/latest |
| Test location | /workspace/coverage/default/0.chip_sw_usbdev_stream.2710187068 |
| Short name | T21 |
| Test name | |
| Test status | |
| Simulation time | 18898415464 ps |
| CPU time | 6059.39 seconds |
| Started | Aug 12 07:10:21 PM PDT 24 |
| Finished | Aug 12 08:51:21 PM PDT 24 |
| Peak memory | 609372 kb |
| Host | smart-19c0036a-7fe2-41e3-a588-847eff83f76f |
| User | root |
| Command | /workspace/default/simv +uart_idx=0 +calibrate_usb_clk=1 +sw_test_timeout_ns=60_000_000 +sw_build_device=sim_dv +sw_images=usbdev_stream_test:1:new_ru les,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim. tcl +ntb_random_seed=2710187068 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_usbdev_stream_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_usbdev_stream.2710187068 |
| Directory | /workspace/0.chip_sw_usbdev_stream/latest |
| Test location | /workspace/coverage/default/0.chip_sw_usbdev_vbus.1420624030 |
| Short name | T1381 |
| Test name | |
| Test status | |
| Simulation time | 3481648728 ps |
| CPU time | 370 seconds |
| Started | Aug 12 07:08:44 PM PDT 24 |
| Finished | Aug 12 07:14:54 PM PDT 24 |
| Peak memory | 610140 kb |
| Host | smart-d7e6c792-9294-483b-aafb-c40cf208e36d |
| User | root |
| Command | /workspace/default/simv +uart_idx=0 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=usbdev_vbus_test:1:new_rules,test_rom:0 +cdc_instrumentati on_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1420624030 - assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_usbdev_dpi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_usbdev_vbus.1420624030 |
| Directory | /workspace/0.chip_sw_usbdev_vbus/latest |
| Test location | /workspace/coverage/default/0.chip_tap_straps_prod.1257126762 |
| Short name | T759 |
| Test name | |
| Test status | |
| Simulation time | 10218171497 ps |
| CPU time | 1293.93 seconds |
| Started | Aug 12 07:08:41 PM PDT 24 |
| Finished | Aug 12 07:30:16 PM PDT 24 |
| Peak memory | 624972 kb |
| Host | smart-eb619cf6-6aad-4296-9c6d-07a1c0602ea2 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStProd +create_jtag_riscv_map=1 +sw_build_device=sim_dv +sw_images=example_test_from_rom:0:test_in_rom :new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1257126762 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_tap_straps_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_tap_straps_prod.1257126762 |
| Directory | /workspace/0.chip_tap_straps_prod/latest |
| Test location | /workspace/coverage/default/0.chip_tap_straps_rma.327044024 |
| Short name | T74 |
| Test name | |
| Test status | |
| Simulation time | 2846209983 ps |
| CPU time | 143.81 seconds |
| Started | Aug 12 07:10:33 PM PDT 24 |
| Finished | Aug 12 07:12:56 PM PDT 24 |
| Peak memory | 633236 kb |
| Host | smart-3907f342-ceed-4df0-ad1c-714915ea8dd2 |
| User | root |
| Command | /workspace/default/simv +create_jtag_riscv_map=1 +sw_build_device=sim_dv +sw_images=example_test_from_rom:0:test_in_rom:new_rules +cdc_instrumentation _enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=327044024 -ass ert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_tap_straps_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co verage/default.vdb -cm_log /dev/null -cm_name 0.chip_tap_straps_rma.327044024 |
| Directory | /workspace/0.chip_tap_straps_rma/latest |
| Test location | /workspace/coverage/default/0.chip_tap_straps_testunlock0.298918504 |
| Short name | T69 |
| Test name | |
| Test status | |
| Simulation time | 4348384476 ps |
| CPU time | 229.39 seconds |
| Started | Aug 12 07:08:57 PM PDT 24 |
| Finished | Aug 12 07:12:47 PM PDT 24 |
| Peak memory | 633540 kb |
| Host | smart-93a7470b-d87d-4a75-84f6-25248b7f2f57 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStTestUnlocked0 +create_jtag_riscv_map=1 +sw_build_device=sim_dv +sw_images=example_test_from_rom:0:te st_in_rom:new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=298918504 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_tap_straps_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_tap_straps_testunlock0.298918504 |
| Directory | /workspace/0.chip_tap_straps_testunlock0/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_asm_init_dev.3700068249 |
| Short name | T1385 |
| Test name | |
| Test status | |
| Simulation time | 15072799096 ps |
| CPU time | 3716.33 seconds |
| Started | Aug 12 07:15:15 PM PDT 24 |
| Finished | Aug 12 08:17:11 PM PDT 24 |
| Peak memory | 610604 kb |
| Host | smart-f9534597-7175-42ea-a202-98540c7df8ec |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeCustom +sw_test_timeout_ns=20000000 +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_prod _key_0:1:ot_flash_binary,otp_img_e2e_bootstrap_entry_dev:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3700068249 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_S EQ=chip_sw_rom_e2e_asm_init_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_asm_init_dev.3700068249 |
| Directory | /workspace/0.rom_e2e_asm_init_dev/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_asm_init_prod.2776196547 |
| Short name | T1192 |
| Test name | |
| Test status | |
| Simulation time | 15482827290 ps |
| CPU time | 3508.28 seconds |
| Started | Aug 12 07:15:14 PM PDT 24 |
| Finished | Aug 12 08:13:43 PM PDT 24 |
| Peak memory | 610516 kb |
| Host | smart-bd9278fb-5362-493c-86ee-fb46804ac2eb |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeCustom +sw_test_timeout_ns=20000000 +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_prod _key_0:1:ot_flash_binary,otp_img_e2e_bootstrap_entry_prod:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2776196547 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_ SEQ=chip_sw_rom_e2e_asm_init_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_asm_init_prod.2776196547 |
| Directory | /workspace/0.rom_e2e_asm_init_prod/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_asm_init_prod_end.570159148 |
| Short name | T1184 |
| Test name | |
| Test status | |
| Simulation time | 15399108682 ps |
| CPU time | 3339.94 seconds |
| Started | Aug 12 07:16:27 PM PDT 24 |
| Finished | Aug 12 08:12:07 PM PDT 24 |
| Peak memory | 610640 kb |
| Host | smart-7b1f05c6-45e2-412b-98fd-2d7b256443da |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeCustom +sw_test_timeout_ns=20000000 +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_prod _key_0:1:ot_flash_binary,otp_img_e2e_bootstrap_entry_prod_end:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=570159148 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TE ST_SEQ=chip_sw_rom_e2e_asm_init_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n ame 0.rom_e2e_asm_init_prod_end.570159148 |
| Directory | /workspace/0.rom_e2e_asm_init_prod_end/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_asm_init_rma.3467965680 |
| Short name | T1020 |
| Test name | |
| Test status | |
| Simulation time | 14842561738 ps |
| CPU time | 3272.17 seconds |
| Started | Aug 12 07:14:43 PM PDT 24 |
| Finished | Aug 12 08:09:16 PM PDT 24 |
| Peak memory | 610672 kb |
| Host | smart-a2f6d3a6-33fc-43e9-9045-e13072567434 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeCustom +sw_test_timeout_ns=20000000 +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_prod _key_0:1:ot_flash_binary,otp_img_e2e_bootstrap_entry_rma:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3467965680 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_S EQ=chip_sw_rom_e2e_asm_init_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_asm_init_rma.3467965680 |
| Directory | /workspace/0.rom_e2e_asm_init_rma/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_asm_init_test_unlocked0.2167197556 |
| Short name | T111 |
| Test name | |
| Test status | |
| Simulation time | 11172984280 ps |
| CPU time | 3067.03 seconds |
| Started | Aug 12 07:14:27 PM PDT 24 |
| Finished | Aug 12 08:05:35 PM PDT 24 |
| Peak memory | 610992 kb |
| Host | smart-e6c41690-bc6d-4d26-b4ad-773c3b96659d |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeCustom +sw_test_timeout_ns=410_000_000 +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_p rod_key_0:1:ot_flash_binary,otp_img_e2e_bootstrap_entry_test_unlocked0:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY =UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2167197556 -assert nopostproc +UVM_TESTNAME=chip_base_te st +UVM_TEST_SEQ=chip_sw_rom_e2e_asm_init_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/ null -cm_name 0.rom_e2e_asm_init_test_unlocked0.2167197556 |
| Directory | /workspace/0.rom_e2e_asm_init_test_unlocked0/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_bad_b_good_prod.222270833 |
| Short name | T400 |
| Test name | |
| Test status | |
| Simulation time | 24210150940 ps |
| CPU time | 7011.24 seconds |
| Started | Aug 12 07:16:01 PM PDT 24 |
| Finished | Aug 12 09:12:54 PM PDT 24 |
| Peak memory | 609956 kb |
| Host | smart-9324065d-e2cd-40cf-bd12-f5ad91f83c3a |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=100_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_corrupted:1: ot_flash_binary:signed:fake_ecdsa_prod_key_0,empty_test_slot_b_fake_ecdsa_prod_key_0:2:ot_flash_binary,otp_img_boot_policy_valid_prod:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=222270833 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_boot_policy_valid_a_bad_b_good_prod.222270833 |
| Directory | /workspace/0.rom_e2e_boot_policy_valid_a_bad_b_good_prod/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_bad_b_good_prod_end.1716516270 |
| Short name | T399 |
| Test name | |
| Test status | |
| Simulation time | 24472466792 ps |
| CPU time | 6637.95 seconds |
| Started | Aug 12 07:16:48 PM PDT 24 |
| Finished | Aug 12 09:07:27 PM PDT 24 |
| Peak memory | 610580 kb |
| Host | smart-c7d9236b-1ce6-4cd8-9425-cd292feaa3ae |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=100_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_corrupted:1: ot_flash_binary:signed:fake_ecdsa_prod_key_0,empty_test_slot_b_fake_ecdsa_prod_key_0:2:ot_flash_binary,otp_img_boot_policy_valid_prod_end:4,mask_r om:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r andom_seed=1716516270 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_boot_policy_valid_a_bad_b_good_prod_end.1716516270 |
| Directory | /workspace/0.rom_e2e_boot_policy_valid_a_bad_b_good_prod_end/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_bad_b_good_rma.2732245022 |
| Short name | T398 |
| Test name | |
| Test status | |
| Simulation time | 23488473200 ps |
| CPU time | 5710.86 seconds |
| Started | Aug 12 07:15:14 PM PDT 24 |
| Finished | Aug 12 08:50:26 PM PDT 24 |
| Peak memory | 609948 kb |
| Host | smart-7589054f-51a8-4198-904a-fc85e13b6b4d |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=100_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_corrupted:1: ot_flash_binary:signed:fake_ecdsa_prod_key_0,empty_test_slot_b_fake_ecdsa_prod_key_0:2:ot_flash_binary,otp_img_boot_policy_valid_rma:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random _seed=2732245022 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_boot_policy_valid_a_bad_b_good_rma.2732245022 |
| Directory | /workspace/0.rom_e2e_boot_policy_valid_a_bad_b_good_rma/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0.2452708162 |
| Short name | T1315 |
| Test name | |
| Test status | |
| Simulation time | 18654171848 ps |
| CPU time | 4849.3 seconds |
| Started | Aug 12 07:16:00 PM PDT 24 |
| Finished | Aug 12 08:36:50 PM PDT 24 |
| Peak memory | 610260 kb |
| Host | smart-325303a7-1dee-476c-8979-5b399c6d6e3f |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=410_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_corrupted:1: ot_flash_binary:signed:fake_ecdsa_prod_key_0,empty_test_slot_b_fake_ecdsa_prod_key_0:2:ot_flash_binary,otp_img_boot_policy_valid_test_unlocked0:4, mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2452708162 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0.2452708162 |
| Directory | /workspace/0.rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_bad_dev.987688396 |
| Short name | T1039 |
| Test name | |
| Test status | |
| Simulation time | 14908929144 ps |
| CPU time | 4348.25 seconds |
| Started | Aug 12 07:16:23 PM PDT 24 |
| Finished | Aug 12 08:28:52 PM PDT 24 |
| Peak memory | 610480 kb |
| Host | smart-819c9d07-b137-4f39-96eb-a2fe4a53a0e4 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=100_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_p rod_key_0:1:ot_flash_binary,empty_test_slot_b_corrupted:2:ot_flash_binary:signed:fake_ecdsa_prod_key_0,otp_img_boot_policy_valid_dev:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random _seed=987688396 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_boot_policy_valid_a_good_b_bad_dev.987688396 |
| Directory | /workspace/0.rom_e2e_boot_policy_valid_a_good_b_bad_dev/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_bad_prod.798595803 |
| Short name | T1196 |
| Test name | |
| Test status | |
| Simulation time | 14989051488 ps |
| CPU time | 4177.54 seconds |
| Started | Aug 12 07:17:40 PM PDT 24 |
| Finished | Aug 12 08:27:19 PM PDT 24 |
| Peak memory | 610492 kb |
| Host | smart-a08b27ad-cc39-4a87-82cf-fe731173ef03 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=100_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_p rod_key_0:1:ot_flash_binary,empty_test_slot_b_corrupted:2:ot_flash_binary:signed:fake_ecdsa_prod_key_0,otp_img_boot_policy_valid_prod:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=798595803 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_boot_policy_valid_a_good_b_bad_prod.798595803 |
| Directory | /workspace/0.rom_e2e_boot_policy_valid_a_good_b_bad_prod/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_bad_prod_end.874398607 |
| Short name | T988 |
| Test name | |
| Test status | |
| Simulation time | 15998227768 ps |
| CPU time | 3534.02 seconds |
| Started | Aug 12 07:16:52 PM PDT 24 |
| Finished | Aug 12 08:15:46 PM PDT 24 |
| Peak memory | 609904 kb |
| Host | smart-89effd51-c416-4bea-84c7-5218add7d003 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=100_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_p rod_key_0:1:ot_flash_binary,empty_test_slot_b_corrupted:2:ot_flash_binary:signed:fake_ecdsa_prod_key_0,otp_img_boot_policy_valid_prod_end:4,mask_r om:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r andom_seed=874398607 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_boot_policy_valid_a_good_b_bad_prod_end.874398607 |
| Directory | /workspace/0.rom_e2e_boot_policy_valid_a_good_b_bad_prod_end/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_bad_rma.3129622258 |
| Short name | T1400 |
| Test name | |
| Test status | |
| Simulation time | 15214476212 ps |
| CPU time | 3819.6 seconds |
| Started | Aug 12 07:18:33 PM PDT 24 |
| Finished | Aug 12 08:22:14 PM PDT 24 |
| Peak memory | 609856 kb |
| Host | smart-89637301-e1e3-42b6-bd7b-046ba130b56e |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=100_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_p rod_key_0:1:ot_flash_binary,empty_test_slot_b_corrupted:2:ot_flash_binary:signed:fake_ecdsa_prod_key_0,otp_img_boot_policy_valid_rma:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random _seed=3129622258 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_boot_policy_valid_a_good_b_bad_rma.3129622258 |
| Directory | /workspace/0.rom_e2e_boot_policy_valid_a_good_b_bad_rma/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0.3025139695 |
| Short name | T1183 |
| Test name | |
| Test status | |
| Simulation time | 11726213296 ps |
| CPU time | 2724.47 seconds |
| Started | Aug 12 07:18:36 PM PDT 24 |
| Finished | Aug 12 08:04:02 PM PDT 24 |
| Peak memory | 610248 kb |
| Host | smart-fe498877-e7cb-43b1-824e-88d7cb16cc25 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=410_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_p rod_key_0:1:ot_flash_binary,empty_test_slot_b_corrupted:2:ot_flash_binary:signed:fake_ecdsa_prod_key_0,otp_img_boot_policy_valid_test_unlocked0:4, mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3025139695 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0.3025139695 |
| Directory | /workspace/0.rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_good_dev.182812320 |
| Short name | T1005 |
| Test name | |
| Test status | |
| Simulation time | 15535610544 ps |
| CPU time | 3448.41 seconds |
| Started | Aug 12 07:14:19 PM PDT 24 |
| Finished | Aug 12 08:11:48 PM PDT 24 |
| Peak memory | 610676 kb |
| Host | smart-02cd2c42-f473-4232-ab54-453158bb6f5b |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=100_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_p rod_key_0:1:ot_flash_binary,empty_test_slot_b_fake_ecdsa_prod_key_0:2:ot_flash_binary,otp_img_boot_policy_valid_dev:4,mask_rom:0 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=182812320 - assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co verage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_boot_policy_valid_a_good_b_good_dev.182812320 |
| Directory | /workspace/0.rom_e2e_boot_policy_valid_a_good_b_good_dev/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_good_prod.4100247848 |
| Short name | T1170 |
| Test name | |
| Test status | |
| Simulation time | 16090124650 ps |
| CPU time | 4055.52 seconds |
| Started | Aug 12 07:13:59 PM PDT 24 |
| Finished | Aug 12 08:21:35 PM PDT 24 |
| Peak memory | 609908 kb |
| Host | smart-82c68451-6cd1-452f-a2e8-eade12ef3ab1 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=100_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_p rod_key_0:1:ot_flash_binary,empty_test_slot_b_fake_ecdsa_prod_key_0:2:ot_flash_binary,otp_img_boot_policy_valid_prod:4,mask_rom:0 +cdc_instrumenta tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4100247848 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/ coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_boot_policy_valid_a_good_b_good_prod.4100247848 |
| Directory | /workspace/0.rom_e2e_boot_policy_valid_a_good_b_good_prod/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_good_prod_end.4067331575 |
| Short name | T1406 |
| Test name | |
| Test status | |
| Simulation time | 15698001230 ps |
| CPU time | 3974.69 seconds |
| Started | Aug 12 07:16:03 PM PDT 24 |
| Finished | Aug 12 08:22:19 PM PDT 24 |
| Peak memory | 609928 kb |
| Host | smart-7356de21-f4b6-4d22-914d-0d419b265e72 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=100_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_p rod_key_0:1:ot_flash_binary,empty_test_slot_b_fake_ecdsa_prod_key_0:2:ot_flash_binary,otp_img_boot_policy_valid_prod_end:4,mask_rom:0 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=406733 1575 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_boot_policy_valid_a_good_b_good_prod_end.4067331575 |
| Directory | /workspace/0.rom_e2e_boot_policy_valid_a_good_b_good_prod_end/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_good_rma.4245300158 |
| Short name | T1343 |
| Test name | |
| Test status | |
| Simulation time | 14990652400 ps |
| CPU time | 4666.13 seconds |
| Started | Aug 12 07:15:46 PM PDT 24 |
| Finished | Aug 12 08:33:33 PM PDT 24 |
| Peak memory | 609912 kb |
| Host | smart-7a27fe95-9e36-4e86-b05c-8f313ec3360f |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=100_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_p rod_key_0:1:ot_flash_binary,empty_test_slot_b_fake_ecdsa_prod_key_0:2:ot_flash_binary,otp_img_boot_policy_valid_rma:4,mask_rom:0 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4245300158 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/c overage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_boot_policy_valid_a_good_b_good_rma.4245300158 |
| Directory | /workspace/0.rom_e2e_boot_policy_valid_a_good_b_good_rma/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_good_test_unlocked0.3489286305 |
| Short name | T1295 |
| Test name | |
| Test status | |
| Simulation time | 11129125872 ps |
| CPU time | 2989.66 seconds |
| Started | Aug 12 07:16:27 PM PDT 24 |
| Finished | Aug 12 08:06:18 PM PDT 24 |
| Peak memory | 609936 kb |
| Host | smart-cf8618b1-178a-47dd-aa32-c9cd546e8970 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=410_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_p rod_key_0:1:ot_flash_binary,empty_test_slot_b_fake_ecdsa_prod_key_0:2:ot_flash_binary,otp_img_boot_policy_valid_test_unlocked0:4,mask_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 3489286305 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_boot_policy_valid_a_good_b_good_test_unlocked0.3489286305 |
| Directory | /workspace/0.rom_e2e_boot_policy_valid_a_good_b_good_test_unlocked0/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_jtag_debug_dev.1809346643 |
| Short name | T261 |
| Test name | |
| Test status | |
| Simulation time | 11343046306 ps |
| CPU time | 1963.98 seconds |
| Started | Aug 12 07:09:19 PM PDT 24 |
| Finished | Aug 12 07:42:04 PM PDT 24 |
| Peak memory | 624736 kb |
| Host | smart-80faa21a-6d02-4a35-bf06-4e379a7e8a1b |
| User | root |
| Command | /workspace/default/simv +use_jtag_dmi=1 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=img_dev_exec_disabled:4,mask_rom:0 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18093 46643 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rom_e2e_jtag_debug_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_jtag_debug_dev.1809346643 |
| Directory | /workspace/0.rom_e2e_jtag_debug_dev/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_jtag_debug_test_unlocked0.1114231620 |
| Short name | T260 |
| Test name | |
| Test status | |
| Simulation time | 11508872026 ps |
| CPU time | 2156.33 seconds |
| Started | Aug 12 07:09:48 PM PDT 24 |
| Finished | Aug 12 07:45:46 PM PDT 24 |
| Peak memory | 624596 kb |
| Host | smart-b97ecfa2-7797-4ae8-a437-92c01c74198f |
| User | root |
| Command | /workspace/default/simv +use_jtag_dmi=1 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=img_test_unlocked0_exec_disabled:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random _seed=1114231620 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rom_e2e_jtag_debug_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_jtag_debug_test_unlocked0.1114231620 |
| Directory | /workspace/0.rom_e2e_jtag_debug_test_unlocked0/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_jtag_inject_dev.3379741155 |
| Short name | T1372 |
| Test name | |
| Test status | |
| Simulation time | 26250717557 ps |
| CPU time | 2350.62 seconds |
| Started | Aug 12 07:11:34 PM PDT 24 |
| Finished | Aug 12 07:50:45 PM PDT 24 |
| Peak memory | 619240 kb |
| Host | smart-e43dead3-f650-4c59-b62b-007b90afee01 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=40_000_000 +use_jtag_dmi=1 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=img_dev_exec_di sabled:4,sram_program:5,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3379741155 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rom_e2e_jtag_inject_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_jtag_inject_dev.3379741155 |
| Directory | /workspace/0.rom_e2e_jtag_inject_dev/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_jtag_inject_rma.3516640490 |
| Short name | T788 |
| Test name | |
| Test status | |
| Simulation time | 21524863711 ps |
| CPU time | 2685.12 seconds |
| Started | Aug 12 07:09:41 PM PDT 24 |
| Finished | Aug 12 07:54:27 PM PDT 24 |
| Peak memory | 624020 kb |
| Host | smart-caa2f7bb-38ab-4523-9fd5-3ed0f52d618b |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=40_000_000 +use_jtag_dmi=1 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=img_rma_exec_di sabled:4,sram_program:5,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3516640490 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rom_e2e_jtag_inject_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_jtag_inject_rma.3516640490 |
| Directory | /workspace/0.rom_e2e_jtag_inject_rma/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_jtag_inject_test_unlocked0.875300134 |
| Short name | T455 |
| Test name | |
| Test status | |
| Simulation time | 27075520619 ps |
| CPU time | 2828.77 seconds |
| Started | Aug 12 07:13:53 PM PDT 24 |
| Finished | Aug 12 08:01:02 PM PDT 24 |
| Peak memory | 619256 kb |
| Host | smart-1871ef3f-2f0b-4114-af69-0eaa29746b94 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=40_000_000 +use_jtag_dmi=1 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=img_test_unlock ed0_exec_disabled:4,sram_program:5,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=875300134 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rom_e2e_jtag_i nject_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_jtag_inject_ test_unlocked0.875300134 |
| Directory | /workspace/0.rom_e2e_jtag_inject_test_unlocked0/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_keymgr_init_rom_ext_invalid_meas.3055824496 |
| Short name | T50 |
| Test name | |
| Test status | |
| Simulation time | 14620311904 ps |
| CPU time | 3750.76 seconds |
| Started | Aug 12 07:16:47 PM PDT 24 |
| Finished | Aug 12 08:19:18 PM PDT 24 |
| Peak memory | 610576 kb |
| Host | smart-9d3255ce-4e30-4b53-9742-e04a03919d91 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=40_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=rom_e2e_keymgr_init_otp_invalid _meas:1:new_rules,otp_img_keymgr_otp_invalid_meas:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3055824496 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip _sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_keymgr_in it_rom_ext_invalid_meas.3055824496 |
| Directory | /workspace/0.rom_e2e_keymgr_init_rom_ext_invalid_meas/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_keymgr_init_rom_ext_meas.1578550169 |
| Short name | T1355 |
| Test name | |
| Test status | |
| Simulation time | 15237898370 ps |
| CPU time | 3686.37 seconds |
| Started | Aug 12 07:17:09 PM PDT 24 |
| Finished | Aug 12 08:18:36 PM PDT 24 |
| Peak memory | 610556 kb |
| Host | smart-36091fb7-4a1e-4a52-bff5-7f5c9d3d4097 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=40_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=rom_e2e_keymgr_init_otp_meas:1: new_rules,otp_img_keymgr_otp_meas:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1578550169 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_keymgr_init_rom_ext_meas.1578550169 |
| Directory | /workspace/0.rom_e2e_keymgr_init_rom_ext_meas/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_keymgr_init_rom_ext_no_meas.1228501044 |
| Short name | T309 |
| Test name | |
| Test status | |
| Simulation time | 14784390344 ps |
| CPU time | 3467.23 seconds |
| Started | Aug 12 07:16:57 PM PDT 24 |
| Finished | Aug 12 08:14:45 PM PDT 24 |
| Peak memory | 610432 kb |
| Host | smart-3f649cad-189a-4550-a098-7f66b2d7916e |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=40_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=rom_e2e_keymgr_init_otp_no_meas :1:new_rules,otp_img_keymgr_otp_no_meas:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1228501044 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_keymgr_init_rom_ext _no_meas.1228501044 |
| Directory | /workspace/0.rom_e2e_keymgr_init_rom_ext_no_meas/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_self_hash.2332419586 |
| Short name | T1153 |
| Test name | |
| Test status | |
| Simulation time | 25478980752 ps |
| CPU time | 5827.61 seconds |
| Started | Aug 12 07:18:45 PM PDT 24 |
| Finished | Aug 12 08:55:53 PM PDT 24 |
| Peak memory | 610480 kb |
| Host | smart-7ed87328-6fef-4098-b5b6-9695ce348e92 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=200_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=rom_e2e_self_hash_test:1:new_r ules,otp_img_sigverify_spx_prod:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2332419586 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_self_hash.2332419586 |
| Directory | /workspace/0.rom_e2e_self_hash/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_shutdown_exception_c.2996462182 |
| Short name | T1068 |
| Test name | |
| Test status | |
| Simulation time | 14693734310 ps |
| CPU time | 4310.52 seconds |
| Started | Aug 12 07:15:03 PM PDT 24 |
| Finished | Aug 12 08:26:54 PM PDT 24 |
| Peak memory | 611492 kb |
| Host | smart-f456ac12-3188-40f6-9aac-2f7d240f77b3 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=40000000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=rom_e2e_shutdown_exception_c:1:ne w_rules,otp_img_secret2_locked_rma:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2996462182 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rom_e2e_shu tdown_exception_c_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_ shutdown_exception_c.2996462182 |
| Directory | /workspace/0.rom_e2e_shutdown_exception_c/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_shutdown_output.1419561364 |
| Short name | T1279 |
| Test name | |
| Test status | |
| Simulation time | 25622408625 ps |
| CPU time | 3945.67 seconds |
| Started | Aug 12 07:12:56 PM PDT 24 |
| Finished | Aug 12 08:18:42 PM PDT 24 |
| Peak memory | 612080 kb |
| Host | smart-85f9f030-174d-4577-bf20-e8d02ef3304b |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=20000000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_unsigned:1:ot_f lash_binary,otp_img_shutdown_output_test_unlocked0:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1419561364 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chi p_sw_rom_e2e_shutdown_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_shutdown_output.1419561364 |
| Directory | /workspace/0.rom_e2e_shutdown_output/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_bad_dev.2721788600 |
| Short name | T1117 |
| Test name | |
| Test status | |
| Simulation time | 23544462968 ps |
| CPU time | 6186.26 seconds |
| Started | Aug 12 07:14:43 PM PDT 24 |
| Finished | Aug 12 08:57:50 PM PDT 24 |
| Peak memory | 610604 kb |
| Host | smart-20b13cf6-dd19-4e93-9f31-e923f53e7034 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=100_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_corrupted:1: ot_flash_binary:signed:fake_ecdsa_dev_key_0,empty_test_slot_b_corrupted:2:ot_flash_binary:signed:fake_ecdsa_dev_key_0,otp_img_sigverify_always_dev :4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t cl +ntb_random_seed=2721788600 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rom_e2e_sigverify_always_a_bad_b_bad_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_sigverify_always_a_bad_b_b ad_dev.2721788600 |
| Directory | /workspace/0.rom_e2e_sigverify_always_a_bad_b_bad_dev/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_bad_prod.1788628252 |
| Short name | T1055 |
| Test name | |
| Test status | |
| Simulation time | 23746658085 ps |
| CPU time | 5529.16 seconds |
| Started | Aug 12 07:15:13 PM PDT 24 |
| Finished | Aug 12 08:47:23 PM PDT 24 |
| Peak memory | 610656 kb |
| Host | smart-4a0a58e6-4dc6-4556-a12b-26c9c20051e9 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=100_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_corrupted:1: ot_flash_binary:signed:fake_ecdsa_prod_key_0,empty_test_slot_b_corrupted:2:ot_flash_binary:signed:fake_ecdsa_prod_key_0,otp_img_sigverify_always_p rod:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si m.tcl +ntb_random_seed=1788628252 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rom_e2e_sigverify_always_a_bad_b_bad_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_sigverify_always_a_bad_ b_bad_prod.1788628252 |
| Directory | /workspace/0.rom_e2e_sigverify_always_a_bad_b_bad_prod/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_bad_prod_end.2154410976 |
| Short name | T48 |
| Test name | |
| Test status | |
| Simulation time | 23665717850 ps |
| CPU time | 5274.81 seconds |
| Started | Aug 12 07:17:48 PM PDT 24 |
| Finished | Aug 12 08:45:44 PM PDT 24 |
| Peak memory | 610576 kb |
| Host | smart-a2bef246-099f-4f04-a6f0-6af5760b92cd |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=100_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_corrupted:1: ot_flash_binary:signed:fake_ecdsa_prod_key_0,empty_test_slot_b_corrupted:2:ot_flash_binary:signed:fake_ecdsa_prod_key_0,otp_img_sigverify_always_p rod_end:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tool s/sim.tcl +ntb_random_seed=2154410976 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rom_e2e_sigverify_always_a_bad_b_bad_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_sigverify_always_a_ bad_b_bad_prod_end.2154410976 |
| Directory | /workspace/0.rom_e2e_sigverify_always_a_bad_b_bad_prod_end/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_bad_rma.2553546698 |
| Short name | T312 |
| Test name | |
| Test status | |
| Simulation time | 22738571934 ps |
| CPU time | 6305.5 seconds |
| Started | Aug 12 07:19:03 PM PDT 24 |
| Finished | Aug 12 09:04:10 PM PDT 24 |
| Peak memory | 610628 kb |
| Host | smart-3183bf42-c462-439a-99b4-dbd464cde87e |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=100_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_corrupted:1: ot_flash_binary:signed:fake_ecdsa_prod_key_0,empty_test_slot_b_corrupted:2:ot_flash_binary:signed:fake_ecdsa_prod_key_0,otp_img_sigverify_always_r ma:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim .tcl +ntb_random_seed=2553546698 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rom_e2e_sigverify_always_a_bad_b_bad_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_sigverify_always_a_bad_b _bad_rma.2553546698 |
| Directory | /workspace/0.rom_e2e_sigverify_always_a_bad_b_bad_rma/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0.1447101509 |
| Short name | T1413 |
| Test name | |
| Test status | |
| Simulation time | 17820211320 ps |
| CPU time | 5657.95 seconds |
| Started | Aug 12 07:17:31 PM PDT 24 |
| Finished | Aug 12 08:51:49 PM PDT 24 |
| Peak memory | 610836 kb |
| Host | smart-b79ebc5a-c26b-4331-98b7-9bb86342b391 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=600_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_corrupted:1: ot_flash_binary:signed:fake_ecdsa_test_key_0,empty_test_slot_b_corrupted:2:ot_flash_binary:signed:fake_ecdsa_test_key_0,otp_img_sigverify_always_t est_unlocked0:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d v/tools/sim.tcl +ntb_random_seed=1447101509 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rom_e2e_sigverify_always_a_bad_b _bad_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_sigverify_alw ays_a_bad_b_bad_test_unlocked0.1447101509 |
| Directory | /workspace/0.rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_nothing_dev.2715893091 |
| Short name | T1415 |
| Test name | |
| Test status | |
| Simulation time | 14447221304 ps |
| CPU time | 3462.5 seconds |
| Started | Aug 12 07:11:28 PM PDT 24 |
| Finished | Aug 12 08:09:11 PM PDT 24 |
| Peak memory | 611440 kb |
| Host | smart-75186375-03e5-402a-bf00-a680ccf46e21 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=100_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_corrupted:1: ot_flash_binary:signed:fake_ecdsa_dev_key_0,otp_img_sigverify_always_dev:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2715893091 -assert nopostproc +UVM_TESTNAME=chip_base_ test +UVM_TEST_SEQ=chip_sw_rom_e2e_sigverify_always_a_bad_b_bad_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def ault.vdb -cm_log /dev/null -cm_name 0.rom_e2e_sigverify_always_a_bad_b_nothing_dev.2715893091 |
| Directory | /workspace/0.rom_e2e_sigverify_always_a_bad_b_nothing_dev/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_nothing_prod.777430764 |
| Short name | T280 |
| Test name | |
| Test status | |
| Simulation time | 14844366404 ps |
| CPU time | 3505.12 seconds |
| Started | Aug 12 07:15:42 PM PDT 24 |
| Finished | Aug 12 08:14:08 PM PDT 24 |
| Peak memory | 610416 kb |
| Host | smart-16ea944f-faef-4578-9d92-6ef2790d21a1 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=100_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_corrupted:1: ot_flash_binary:signed:fake_ecdsa_prod_key_0,otp_img_sigverify_always_prod:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=777430764 -assert nopostproc +UVM_TESTNAME=chip_base _test +UVM_TEST_SEQ=chip_sw_rom_e2e_sigverify_always_a_bad_b_bad_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de fault.vdb -cm_log /dev/null -cm_name 0.rom_e2e_sigverify_always_a_bad_b_nothing_prod.777430764 |
| Directory | /workspace/0.rom_e2e_sigverify_always_a_bad_b_nothing_prod/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_nothing_prod_end.2773458528 |
| Short name | T49 |
| Test name | |
| Test status | |
| Simulation time | 15196100875 ps |
| CPU time | 4409.82 seconds |
| Started | Aug 12 07:14:19 PM PDT 24 |
| Finished | Aug 12 08:27:49 PM PDT 24 |
| Peak memory | 610728 kb |
| Host | smart-f660244a-c2ea-4b37-9bb4-7d708cfb0b0a |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=100_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_corrupted:1: ot_flash_binary:signed:fake_ecdsa_prod_key_0,otp_img_sigverify_always_prod_end:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2773458528 -assert nopostproc +UVM_TESTNAME=chip _base_test +UVM_TEST_SEQ=chip_sw_rom_e2e_sigverify_always_a_bad_b_bad_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera ge/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_sigverify_always_a_bad_b_nothing_prod_end.2773458528 |
| Directory | /workspace/0.rom_e2e_sigverify_always_a_bad_b_nothing_prod_end/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_nothing_rma.1516550183 |
| Short name | T281 |
| Test name | |
| Test status | |
| Simulation time | 14133856236 ps |
| CPU time | 3983.08 seconds |
| Started | Aug 12 07:16:58 PM PDT 24 |
| Finished | Aug 12 08:23:22 PM PDT 24 |
| Peak memory | 610652 kb |
| Host | smart-72a42e92-5e5e-4db7-98da-17ce07c70421 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=100_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_corrupted:1: ot_flash_binary:signed:fake_ecdsa_prod_key_0,otp_img_sigverify_always_rma:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1516550183 -assert nopostproc +UVM_TESTNAME=chip_base _test +UVM_TEST_SEQ=chip_sw_rom_e2e_sigverify_always_a_bad_b_bad_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de fault.vdb -cm_log /dev/null -cm_name 0.rom_e2e_sigverify_always_a_bad_b_nothing_rma.1516550183 |
| Directory | /workspace/0.rom_e2e_sigverify_always_a_bad_b_nothing_rma/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0.2387407870 |
| Short name | T1206 |
| Test name | |
| Test status | |
| Simulation time | 10995392732 ps |
| CPU time | 3075.31 seconds |
| Started | Aug 12 07:18:05 PM PDT 24 |
| Finished | Aug 12 08:09:20 PM PDT 24 |
| Peak memory | 608844 kb |
| Host | smart-5ecc2d21-5335-486e-aadf-b5b6b213eae4 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=410_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_corrupted:1: ot_flash_binary:signed:fake_ecdsa_test_key_0:new_rules,otp_img_sigverify_always_test_unlocked0:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2387407870 -assert nopostproc +U VM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rom_e2e_sigverify_always_a_bad_b_bad_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0.2387407870 |
| Directory | /workspace/0.rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_sigverify_always_a_nothing_b_bad_dev.348471287 |
| Short name | T282 |
| Test name | |
| Test status | |
| Simulation time | 14463281546 ps |
| CPU time | 3291.01 seconds |
| Started | Aug 12 07:13:54 PM PDT 24 |
| Finished | Aug 12 08:08:46 PM PDT 24 |
| Peak memory | 610412 kb |
| Host | smart-7edeb75f-f5e1-4c1a-a064-b2a8d6ec9271 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=100_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_b_corrupted:1: ot_flash_binary:signed:fake_ecdsa_dev_key_0,otp_img_sigverify_always_dev:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=348471287 -assert nopostproc +UVM_TESTNAME=chip_base_t est +UVM_TEST_SEQ=chip_sw_rom_e2e_sigverify_always_a_bad_b_bad_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defa ult.vdb -cm_log /dev/null -cm_name 0.rom_e2e_sigverify_always_a_nothing_b_bad_dev.348471287 |
| Directory | /workspace/0.rom_e2e_sigverify_always_a_nothing_b_bad_dev/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_sigverify_always_a_nothing_b_bad_prod.2245639801 |
| Short name | T1310 |
| Test name | |
| Test status | |
| Simulation time | 15527628567 ps |
| CPU time | 4058.99 seconds |
| Started | Aug 12 07:17:51 PM PDT 24 |
| Finished | Aug 12 08:25:30 PM PDT 24 |
| Peak memory | 610696 kb |
| Host | smart-a7c48683-54b5-40fb-9b42-8a926a571b22 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=100_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_b_corrupted:1: ot_flash_binary:signed:fake_ecdsa_prod_key_0,otp_img_sigverify_always_prod:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2245639801 -assert nopostproc +UVM_TESTNAME=chip_bas e_test +UVM_TEST_SEQ=chip_sw_rom_e2e_sigverify_always_a_bad_b_bad_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/d efault.vdb -cm_log /dev/null -cm_name 0.rom_e2e_sigverify_always_a_nothing_b_bad_prod.2245639801 |
| Directory | /workspace/0.rom_e2e_sigverify_always_a_nothing_b_bad_prod/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_sigverify_always_a_nothing_b_bad_rma.2010903573 |
| Short name | T1278 |
| Test name | |
| Test status | |
| Simulation time | 13597909992 ps |
| CPU time | 4471.75 seconds |
| Started | Aug 12 07:17:25 PM PDT 24 |
| Finished | Aug 12 08:31:58 PM PDT 24 |
| Peak memory | 610960 kb |
| Host | smart-beaff16b-f2f0-403b-a68d-af635ae5515e |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=100_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_b_corrupted:1: ot_flash_binary:signed:fake_ecdsa_prod_key_0,otp_img_sigverify_always_rma:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2010903573 -assert nopostproc +UVM_TESTNAME=chip_base _test +UVM_TEST_SEQ=chip_sw_rom_e2e_sigverify_always_a_bad_b_bad_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de fault.vdb -cm_log /dev/null -cm_name 0.rom_e2e_sigverify_always_a_nothing_b_bad_rma.2010903573 |
| Directory | /workspace/0.rom_e2e_sigverify_always_a_nothing_b_bad_rma/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0.1897831329 |
| Short name | T1412 |
| Test name | |
| Test status | |
| Simulation time | 11405665727 ps |
| CPU time | 2777.12 seconds |
| Started | Aug 12 07:17:22 PM PDT 24 |
| Finished | Aug 12 08:03:40 PM PDT 24 |
| Peak memory | 610992 kb |
| Host | smart-59c1be2b-4ca1-42e7-b1ae-afc440168ca3 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=410_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_b_corrupted:1: ot_flash_binary:signed:fake_ecdsa_test_key_0,otp_img_sigverify_always_test_unlocked0:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1897831329 -assert nopostproc +UVM_TESTNAM E=chip_base_test +UVM_TEST_SEQ=chip_sw_rom_e2e_sigverify_always_a_bad_b_bad_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/ coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0.1897831329 |
| Directory | /workspace/0.rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_smoke.4119945085 |
| Short name | T1100 |
| Test name | |
| Test status | |
| Simulation time | 15048220640 ps |
| CPU time | 3368.91 seconds |
| Started | Aug 12 07:15:15 PM PDT 24 |
| Finished | Aug 12 08:11:24 PM PDT 24 |
| Peak memory | 610440 kb |
| Host | smart-3870b1e6-b315-404f-a765-336d9c47e123 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=40000000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=rom_e2e_smoke:1:new_rules,otp_img _secret2_locked_rma:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_to p/hw/dv/tools/sim.tcl +ntb_random_seed=4119945085 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_smoke.4119945085 |
| Directory | /workspace/0.rom_e2e_smoke/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_static_critical.684261364 |
| Short name | T1356 |
| Test name | |
| Test status | |
| Simulation time | 17523807250 ps |
| CPU time | 3926.16 seconds |
| Started | Aug 12 07:15:30 PM PDT 24 |
| Finished | Aug 12 08:20:56 PM PDT 24 |
| Peak memory | 610512 kb |
| Host | smart-19427a66-9512-4ea2-b560-3c39df9707e6 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=40000000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=rom_e2e_static_critical:1:new_rul es,otp_img_secret2_locked_rma:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=684261364 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_static_critical.684261364 |
| Directory | /workspace/0.rom_e2e_static_critical/latest |
| Test location | /workspace/coverage/default/0.rom_keymgr_functest.2657330900 |
| Short name | T1067 |
| Test name | |
| Test status | |
| Simulation time | 3729738630 ps |
| CPU time | 463.74 seconds |
| Started | Aug 12 07:11:18 PM PDT 24 |
| Finished | Aug 12 07:19:02 PM PDT 24 |
| Peak memory | 610684 kb |
| Host | smart-6c537295-f8de-453f-b77f-77299aa7eb13 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=10_000_000 +sw_build_device=sim_dv +sw_images=keymgr_functest:1:new_rules,test_rom:0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2657330900 -ass ert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 0.rom_keymgr_functest.2657330900 |
| Directory | /workspace/0.rom_keymgr_functest/latest |
| Test location | /workspace/coverage/default/0.rom_raw_unlock.3070481139 |
| Short name | T786 |
| Test name | |
| Test status | |
| Simulation time | 4984047136 ps |
| CPU time | 243.95 seconds |
| Started | Aug 12 07:11:07 PM PDT 24 |
| Finished | Aug 12 07:15:11 PM PDT 24 |
| Peak memory | 620064 kb |
| Host | smart-d563374a-681f-4886-bce8-e6039ad49c13 |
| User | root |
| Command | /workspace/default/simv +do_creator_sw_cfg_ast_cfg=0 +sw_test_timeout_ns=200_000_000 +use_otp_image=OtpTypeLcStRaw +chip_clock_source=ChipClockSourceE xternal48Mhz +rom_prod_mode=1 +use_jtag_dmi=1 +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_test_key_0:1:ot_flash_binary,mask_ro m:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=3070481139 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_raw_unlock_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_raw_unlock.3070481139 |
| Directory | /workspace/0.rom_raw_unlock/latest |
| Test location | /workspace/coverage/default/0.rom_volatile_raw_unlock.4004541499 |
| Short name | T1357 |
| Test name | |
| Test status | |
| Simulation time | 2435550397 ps |
| CPU time | 105.3 seconds |
| Started | Aug 12 07:10:54 PM PDT 24 |
| Finished | Aug 12 07:12:39 PM PDT 24 |
| Peak memory | 617936 kb |
| Host | smart-5d38398e-0325-4e79-ae4f-9528f779383d |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=200_000_000 +use_otp_image=OtpTypeLcStRaw +chip_clock_source=ChipClockSourceExternal48Mhz +rom_prod_mode=1 +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_test_key_0:1:ot_flash_binary,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4004541499 -assert nopostproc +UVM_ TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_volatile_raw_unlock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag e/default.vdb -cm_log /dev/null -cm_name 0.rom_volatile_raw_unlock.4004541499 |
| Directory | /workspace/0.rom_volatile_raw_unlock/latest |
| Test location | /workspace/coverage/default/1.chip_jtag_mem_access.794671467 |
| Short name | T965 |
| Test name | |
| Test status | |
| Simulation time | 13937606243 ps |
| CPU time | 1581.12 seconds |
| Started | Aug 12 07:11:49 PM PDT 24 |
| Finished | Aug 12 07:38:10 PM PDT 24 |
| Peak memory | 608212 kb |
| Host | smart-87a88340-cba5-4630-a958-a90d689d10b7 |
| User | root |
| Command | /workspace/default/simv +create_jtag_riscv_map=1 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=794671467 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_jtag_m em_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_jtag_mem_access.794671467 |
| Directory | /workspace/1.chip_jtag_mem_access/latest |
| Test location | /workspace/coverage/default/1.chip_rv_dm_ndm_reset_req.3077991016 |
| Short name | T416 |
| Test name | |
| Test status | |
| Simulation time | 3837972928 ps |
| CPU time | 368.23 seconds |
| Started | Aug 12 07:19:56 PM PDT 24 |
| Finished | Aug 12 07:26:05 PM PDT 24 |
| Peak memory | 621148 kb |
| Host | smart-fcafb5d2-dd4b-47d8-a8bb-bbf9784978a7 |
| User | root |
| Command | /workspace/default/simv +en_scb_tl_err_chk=0 +use_jtag_dmi=1 +sw_build_device=sim_dv +sw_images=rv_dm_ndm_reset_req_rma:1:new_rules,test_rom:0 +cdc_in strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3 077991016 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_rv_dm_ndm_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_rv_dm_ndm_reset_req.3077991016 |
| Directory | /workspace/1.chip_rv_dm_ndm_reset_req/latest |
| Test location | /workspace/coverage/default/1.chip_sival_flash_info_access.3985913058 |
| Short name | T1350 |
| Test name | |
| Test status | |
| Simulation time | 3667385954 ps |
| CPU time | 300.72 seconds |
| Started | Aug 12 07:13:37 PM PDT 24 |
| Finished | Aug 12 07:18:38 PM PDT 24 |
| Peak memory | 608920 kb |
| Host | smart-f87f87b4-6ec9-48b6-91e4-723f65243178 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStTestUnlocked0 +sw_build_device=sim_dv +sw_images=flash_ctrl_info_access_lc:1:new_rules,test_rom:0 +c dc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_s eed=3985913058 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sival_flash_info_access.3985913058 |
| Directory | /workspace/1.chip_sival_flash_info_access/latest |
| Test location | /workspace/coverage/default/1.chip_sw_adc_ctrl_sleep_debug_cable_wakeup.3885142528 |
| Short name | T118 |
| Test name | |
| Test status | |
| Simulation time | 19977650600 ps |
| CPU time | 750.17 seconds |
| Started | Aug 12 07:14:54 PM PDT 24 |
| Finished | Aug 12 07:27:25 PM PDT 24 |
| Peak memory | 620032 kb |
| Host | smart-f1cb86af-e794-492b-abc6-f42fe8cd2dec |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=adc_ctrl_sleep_debug_cable_wakeup_test:1:new_rules,test_rom: 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand om_seed=3885142528 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_adc_ctrl_sleep_debug_cable_wakeup_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_adc_ctrl_sleep_debug_cable_wakeup.3885142528 |
| Directory | /workspace/1.chip_sw_adc_ctrl_sleep_debug_cable_wakeup/latest |
| Test location | /workspace/coverage/default/1.chip_sw_aes_enc.2806440976 |
| Short name | T971 |
| Test name | |
| Test status | |
| Simulation time | 2721202216 ps |
| CPU time | 227.43 seconds |
| Started | Aug 12 07:15:34 PM PDT 24 |
| Finished | Aug 12 07:19:21 PM PDT 24 |
| Peak memory | 610096 kb |
| Host | smart-554e2b8f-c70c-4e96-bc05-5e0a953b2e5d |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=22_000_000 +sw_build_device=sim_dv +sw_images=aes_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2806440976 -asser t nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag e/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_aes_enc.2806440976 |
| Directory | /workspace/1.chip_sw_aes_enc/latest |
| Test location | /workspace/coverage/default/1.chip_sw_aes_enc_jitter_en.2705105696 |
| Short name | T1346 |
| Test name | |
| Test status | |
| Simulation time | 2541540061 ps |
| CPU time | 274.27 seconds |
| Started | Aug 12 07:17:39 PM PDT 24 |
| Finished | Aug 12 07:22:14 PM PDT 24 |
| Peak memory | 610176 kb |
| Host | smart-a0c38f6c-e887-4e9a-abdd-562a82b46571 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=26_000_000 +en_jitter=1 +sw_build_device=sim_dv +sw_images=aes_smoketest:1:new_rules,test_rom:0 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2705 105696 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work space/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_aes_enc_jitter_en.2705105696 |
| Directory | /workspace/1.chip_sw_aes_enc_jitter_en/latest |
| Test location | /workspace/coverage/default/1.chip_sw_aes_enc_jitter_en_reduced_freq.2681097463 |
| Short name | T1366 |
| Test name | |
| Test status | |
| Simulation time | 3343346336 ps |
| CPU time | 284.9 seconds |
| Started | Aug 12 07:20:47 PM PDT 24 |
| Finished | Aug 12 07:25:32 PM PDT 24 |
| Peak memory | 609936 kb |
| Host | smart-3a45834a-4a48-4dee-b48d-5dd9bea0d7e8 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=26_000_000 +en_jitter=1 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=aes_smoketest:1:new_rules, test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2681097463 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_aes_enc_jitter_en_reduced_freq.2681097463 |
| Directory | /workspace/1.chip_sw_aes_enc_jitter_en_reduced_freq/latest |
| Test location | /workspace/coverage/default/1.chip_sw_aes_entropy.400744472 |
| Short name | T1380 |
| Test name | |
| Test status | |
| Simulation time | 2810245000 ps |
| CPU time | 213.09 seconds |
| Started | Aug 12 07:17:52 PM PDT 24 |
| Finished | Aug 12 07:21:25 PM PDT 24 |
| Peak memory | 609872 kb |
| Host | smart-947ad728-c9b1-4ba4-95d0-63486423a256 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=15_000_000 +sw_build_device=sim_dv +sw_images=aes_entropy_test:1:new_rules,test_rom:0 +cdc_instrumentation _enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=400744472 -ass ert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_aes_entropy.400744472 |
| Directory | /workspace/1.chip_sw_aes_entropy/latest |
| Test location | /workspace/coverage/default/1.chip_sw_aes_idle.802224307 |
| Short name | T1241 |
| Test name | |
| Test status | |
| Simulation time | 3560736888 ps |
| CPU time | 341.58 seconds |
| Started | Aug 12 07:15:04 PM PDT 24 |
| Finished | Aug 12 07:20:46 PM PDT 24 |
| Peak memory | 610160 kb |
| Host | smart-8c702eff-178c-414f-8dfb-5714d34efcb9 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=25_000_000 +sw_build_device=sim_dv +sw_images=aes_idle_test:1:new_rules,test_rom:0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=802224307 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage /default.vdb -cm_log /dev/null -cm_name 1.chip_sw_aes_idle.802224307 |
| Directory | /workspace/1.chip_sw_aes_idle/latest |
| Test location | /workspace/coverage/default/1.chip_sw_aes_masking_off.1904912036 |
| Short name | T1143 |
| Test name | |
| Test status | |
| Simulation time | 2896278547 ps |
| CPU time | 339.13 seconds |
| Started | Aug 12 07:15:35 PM PDT 24 |
| Finished | Aug 12 07:21:14 PM PDT 24 |
| Peak memory | 609792 kb |
| Host | smart-c43ed265-a014-4ad0-be4f-f21091f25be3 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=aes_masking_off_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1904912036 -assert nopostproc +UVM_TESTNA ME=chip_base_test +UVM_TEST_SEQ=chip_sw_aes_masking_off_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_aes_masking_off.1904912036 |
| Directory | /workspace/1.chip_sw_aes_masking_off/latest |
| Test location | /workspace/coverage/default/1.chip_sw_aes_smoketest.2579644572 |
| Short name | T1031 |
| Test name | |
| Test status | |
| Simulation time | 3076640504 ps |
| CPU time | 333.08 seconds |
| Started | Aug 12 07:21:20 PM PDT 24 |
| Finished | Aug 12 07:26:53 PM PDT 24 |
| Peak memory | 609724 kb |
| Host | smart-317c32fa-fa9d-4182-8dcf-b3c7f17e8f70 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=aes_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2579644572 -assert nopostproc +UVM_TESTNAME=chip _base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_aes_smoketest.2579644572 |
| Directory | /workspace/1.chip_sw_aes_smoketest/latest |
| Test location | /workspace/coverage/default/1.chip_sw_alert_handler_entropy.678771487 |
| Short name | T789 |
| Test name | |
| Test status | |
| Simulation time | 2886375717 ps |
| CPU time | 304.16 seconds |
| Started | Aug 12 07:16:46 PM PDT 24 |
| Finished | Aug 12 07:21:50 PM PDT 24 |
| Peak memory | 610092 kb |
| Host | smart-89a22172-5386-44ca-9d41-8141f8f646bd |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=alert_handler_entropy_test:1:new_rules,test_ro m:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=678771487 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_alert_handler_entropy.678771487 |
| Directory | /workspace/1.chip_sw_alert_handler_entropy/latest |
| Test location | /workspace/coverage/default/1.chip_sw_alert_handler_escalation.2758272694 |
| Short name | T54 |
| Test name | |
| Test status | |
| Simulation time | 5336921188 ps |
| CPU time | 516.19 seconds |
| Started | Aug 12 07:16:29 PM PDT 24 |
| Finished | Aug 12 07:25:06 PM PDT 24 |
| Peak memory | 620012 kb |
| Host | smart-d7b343bc-cfba-4e82-9bde-45dc667fdb53 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=alert_handler_escalation_test:1:new_rules,test _rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb _random_seed=2758272694 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_alert_handler_escalation_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_alert_handler_escalation.2758272694 |
| Directory | /workspace/1.chip_sw_alert_handler_escalation/latest |
| Test location | /workspace/coverage/default/1.chip_sw_alert_handler_lpg_clkoff.150731717 |
| Short name | T1365 |
| Test name | |
| Test status | |
| Simulation time | 8467500216 ps |
| CPU time | 1874.11 seconds |
| Started | Aug 12 07:15:03 PM PDT 24 |
| Finished | Aug 12 07:46:17 PM PDT 24 |
| Peak memory | 610392 kb |
| Host | smart-e4adb69b-da6a-4fbb-b2ce-2c969afc5418 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +sw_build_device=sim_dv +sw_images=alert_handler_lpg_clkoff_test:1:new_rules,test_r om:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r andom_seed=150731717 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_alert_handler_lpg_clkoff_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_alert_handler_lpg_clkoff.150731717 |
| Directory | /workspace/1.chip_sw_alert_handler_lpg_clkoff/latest |
| Test location | /workspace/coverage/default/1.chip_sw_alert_handler_lpg_reset_toggle.4267077400 |
| Short name | T1401 |
| Test name | |
| Test status | |
| Simulation time | 7670676634 ps |
| CPU time | 1786.11 seconds |
| Started | Aug 12 07:16:29 PM PDT 24 |
| Finished | Aug 12 07:46:15 PM PDT 24 |
| Peak memory | 610408 kb |
| Host | smart-17189c7a-9696-4bb1-aa35-ad0ebe4bf39d |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +sw_build_device=sim_dv +sw_images=alert_handler_lpg_reset_toggle_test:1:new_rules, test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4267077400 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_alert_handler_shorten_ping_wait_cycle_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_alert_handler_lpg_reset_togg le.4267077400 |
| Directory | /workspace/1.chip_sw_alert_handler_lpg_reset_toggle/latest |
| Test location | /workspace/coverage/default/1.chip_sw_alert_handler_lpg_sleep_mode_pings.1209774384 |
| Short name | T85 |
| Test name | |
| Test status | |
| Simulation time | 13117802746 ps |
| CPU time | 1699.02 seconds |
| Started | Aug 12 07:18:38 PM PDT 24 |
| Finished | Aug 12 07:46:58 PM PDT 24 |
| Peak memory | 612444 kb |
| Host | smart-34f00341-f4f2-489c-b386-d88d663dc6c1 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=alert_handler _lpg_sleep_mode_pings_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1209774384 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_alert_han dler_shorten_ping_wait_cycle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_alert_handler_lpg_sleep_mode_pings.1209774384 |
| Directory | /workspace/1.chip_sw_alert_handler_lpg_sleep_mode_pings/latest |
| Test location | /workspace/coverage/default/1.chip_sw_alert_handler_ping_ok.1777756254 |
| Short name | T792 |
| Test name | |
| Test status | |
| Simulation time | 8411111920 ps |
| CPU time | 1487.11 seconds |
| Started | Aug 12 07:17:34 PM PDT 24 |
| Finished | Aug 12 07:42:22 PM PDT 24 |
| Peak memory | 610472 kb |
| Host | smart-23613f0f-4bf8-4ab9-a9b6-2308636a2ae6 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=24000000 +sw_build_device=sim_dv +sw_images=alert_handler_ping_ok_test:1:new_rules,test_rom:0 +c dc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_s eed=1777756254 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_alert_handler_ping_ok.1777756254 |
| Directory | /workspace/1.chip_sw_alert_handler_ping_ok/latest |
| Test location | /workspace/coverage/default/1.chip_sw_alert_handler_ping_timeout.3994642959 |
| Short name | T1089 |
| Test name | |
| Test status | |
| Simulation time | 5135940600 ps |
| CPU time | 573.2 seconds |
| Started | Aug 12 07:16:39 PM PDT 24 |
| Finished | Aug 12 07:26:13 PM PDT 24 |
| Peak memory | 610524 kb |
| Host | smart-c6dc773c-4f25-4c4a-9db1-25f450aba084 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=24000000 +sw_build_device=sim_dv +sw_images=alert_handler_ping_timeout_test:1:new_rules,test_rom :0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=3994642959 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_alert_handler_ping_timeout.3994642959 |
| Directory | /workspace/1.chip_sw_alert_handler_ping_timeout/latest |
| Test location | /workspace/coverage/default/1.chip_sw_alert_handler_reverse_ping_in_deep_sleep.2180221030 |
| Short name | T402 |
| Test name | |
| Test status | |
| Simulation time | 255531530066 ps |
| CPU time | 13027.3 seconds |
| Started | Aug 12 07:15:40 PM PDT 24 |
| Finished | Aug 12 10:52:48 PM PDT 24 |
| Peak memory | 611060 kb |
| Host | smart-e447a14e-bf5a-405d-868c-4ab926bf4ad5 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=300_000_000 +sw_build_device=sim_dv +sw_images=alert_handler_reverse_ping_in_deep_sleep_test:1:n ew_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2180221030 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_alert_handler_reverse_ping_in_deep_sleep.2180221030 |
| Directory | /workspace/1.chip_sw_alert_handler_reverse_ping_in_deep_sleep/latest |
| Test location | /workspace/coverage/default/1.chip_sw_alert_test.589237073 |
| Short name | T58 |
| Test name | |
| Test status | |
| Simulation time | 3914628732 ps |
| CPU time | 361.05 seconds |
| Started | Aug 12 07:16:49 PM PDT 24 |
| Finished | Aug 12 07:22:51 PM PDT 24 |
| Peak memory | 610444 kb |
| Host | smart-3e560fb6-32c5-422f-a3dd-2dbf4dd72e01 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=alert_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=589237073 -assert nopostproc +UVM_TESTNAME=chip_bas e_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm _name 1.chip_sw_alert_test.589237073 |
| Directory | /workspace/1.chip_sw_alert_test/latest |
| Test location | /workspace/coverage/default/1.chip_sw_aon_timer_irq.2536294721 |
| Short name | T1142 |
| Test name | |
| Test status | |
| Simulation time | 3055770730 ps |
| CPU time | 312.65 seconds |
| Started | Aug 12 07:13:14 PM PDT 24 |
| Finished | Aug 12 07:18:26 PM PDT 24 |
| Peak memory | 609864 kb |
| Host | smart-f690cd22-79b6-44f0-a3dd-bdfe865e3f2c |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=aon_timer_irq_test:1:new_rules,test_rom:0 +cdc_instrumentati on_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2536294721 - assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co verage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_aon_timer_irq.2536294721 |
| Directory | /workspace/1.chip_sw_aon_timer_irq/latest |
| Test location | /workspace/coverage/default/1.chip_sw_aon_timer_sleep_wdog_sleep_pause.973310958 |
| Short name | T132 |
| Test name | |
| Test status | |
| Simulation time | 7433983818 ps |
| CPU time | 500.88 seconds |
| Started | Aug 12 07:15:20 PM PDT 24 |
| Finished | Aug 12 07:23:41 PM PDT 24 |
| Peak memory | 609688 kb |
| Host | smart-ee74560f-de39-4a31-8823-8dd07c0bae86 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=aon_timer_sleep_wdog_sleep_pause_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=973310958 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_aon_timer_sleep_wdog_sleep_pause.973310958 |
| Directory | /workspace/1.chip_sw_aon_timer_sleep_wdog_sleep_pause/latest |
| Test location | /workspace/coverage/default/1.chip_sw_aon_timer_smoketest.1529236412 |
| Short name | T257 |
| Test name | |
| Test status | |
| Simulation time | 3397769154 ps |
| CPU time | 421.14 seconds |
| Started | Aug 12 07:21:14 PM PDT 24 |
| Finished | Aug 12 07:28:15 PM PDT 24 |
| Peak memory | 610156 kb |
| Host | smart-b1f286a0-cc15-4e25-81c6-e53f30eeeaba |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=aon_timer_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1529236412 -assert nopostproc +UVM_TESTNAM E=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 1.chip_sw_aon_timer_smoketest.1529236412 |
| Directory | /workspace/1.chip_sw_aon_timer_smoketest/latest |
| Test location | /workspace/coverage/default/1.chip_sw_aon_timer_wdog_bite_reset.1006242207 |
| Short name | T1318 |
| Test name | |
| Test status | |
| Simulation time | 9526891138 ps |
| CPU time | 810.47 seconds |
| Started | Aug 12 07:14:17 PM PDT 24 |
| Finished | Aug 12 07:27:48 PM PDT 24 |
| Peak memory | 610944 kb |
| Host | smart-000aa3f8-ac4a-4451-8be9-c2e9c3be6978 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=aon_timer_wdog_bite_reset_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 1006242207 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_aon_timer_wdog_bite_reset.1006242207 |
| Directory | /workspace/1.chip_sw_aon_timer_wdog_bite_reset/latest |
| Test location | /workspace/coverage/default/1.chip_sw_aon_timer_wdog_lc_escalate.1824421498 |
| Short name | T976 |
| Test name | |
| Test status | |
| Simulation time | 4863583026 ps |
| CPU time | 933.48 seconds |
| Started | Aug 12 07:14:04 PM PDT 24 |
| Finished | Aug 12 07:29:38 PM PDT 24 |
| Peak memory | 610096 kb |
| Host | smart-babbf5c8-aa53-45be-8390-f1d32fd68b7c |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=aon_timer_wdog_lc_escalate_test:1:new_rules,test_rom:0 +cdc_ instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed =1824421498 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_aon_timer_wdog_lc_escalate.1824421498 |
| Directory | /workspace/1.chip_sw_aon_timer_wdog_lc_escalate/latest |
| Test location | /workspace/coverage/default/1.chip_sw_ast_clk_outputs.2637393388 |
| Short name | T1159 |
| Test name | |
| Test status | |
| Simulation time | 7374527440 ps |
| CPU time | 1060.01 seconds |
| Started | Aug 12 07:20:03 PM PDT 24 |
| Finished | Aug 12 07:37:43 PM PDT 24 |
| Peak memory | 616732 kb |
| Host | smart-f6200f5f-b48d-46b0-99fd-e52dc8c60398 |
| User | root |
| Command | /workspace/default/simv +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=ast_clk_outs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled= 1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2637393388 -assert nopo stproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_ast_clk_outputs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co verage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_ast_clk_outputs.2637393388 |
| Directory | /workspace/1.chip_sw_ast_clk_outputs/latest |
| Test location | /workspace/coverage/default/1.chip_sw_ast_clk_rst_inputs.983085207 |
| Short name | T154 |
| Test name | |
| Test status | |
| Simulation time | 26578121599 ps |
| CPU time | 4289.33 seconds |
| Started | Aug 12 07:22:54 PM PDT 24 |
| Finished | Aug 12 08:34:25 PM PDT 24 |
| Peak memory | 611272 kb |
| Host | smart-8fa731ba-8eed-4205-a711-b9f4e4b4b0bf |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=200_000_000 +sw_build_device=sim_dv +sw_images=ast_clk_rst_inputs:1:new_rules,test_rom:0 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=983085207 - assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_ast_clk_rst_inputs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_ast_clk_rst_inputs.983085207 |
| Directory | /workspace/1.chip_sw_ast_clk_rst_inputs/latest |
| Test location | /workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_lc.3230198313 |
| Short name | T1021 |
| Test name | |
| Test status | |
| Simulation time | 12034711563 ps |
| CPU time | 1050.21 seconds |
| Started | Aug 12 07:17:28 PM PDT 24 |
| Finished | Aug 12 07:34:59 PM PDT 24 |
| Peak memory | 620888 kb |
| Host | smart-982406ad-588c-4143-bf0a-dbd927e0dc86 |
| User | root |
| Command | /workspace/default/simv +chip_clock_source=ChipClockSourceExternal48Mhz +sw_build_device=sim_dv +sw_images=clkmgr_external_clk_src_for_lc_test:1:new_r ules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim .tcl +ntb_random_seed=3230198313 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_transition_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_clkmgr_external_clk_src_for_lc.3230198313 |
| Directory | /workspace/1.chip_sw_clkmgr_external_clk_src_for_lc/latest |
| Test location | /workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_fast_dev.3804891791 |
| Short name | T1178 |
| Test name | |
| Test status | |
| Simulation time | 4352450176 ps |
| CPU time | 630.93 seconds |
| Started | Aug 12 07:22:34 PM PDT 24 |
| Finished | Aug 12 07:33:05 PM PDT 24 |
| Peak memory | 612576 kb |
| Host | smart-51ed774e-e2a4-4dd3-9b20-71a2939e3b45 |
| User | root |
| Command | /workspace/default/simv +chip_clock_source=ChipClockSourceExternal96Mhz +calibrate_usb_clk=1 +src_dec_state=DecLcStDev +sw_build_device=sim_dv +sw_ima ges=clkmgr_external_clk_src_for_sw_fast_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3804891791 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ =chip_sw_lc_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_c lkmgr_external_clk_src_for_sw_fast_dev.3804891791 |
| Directory | /workspace/1.chip_sw_clkmgr_external_clk_src_for_sw_fast_dev/latest |
| Test location | /workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_fast_rma.469196153 |
| Short name | T1177 |
| Test name | |
| Test status | |
| Simulation time | 4116491742 ps |
| CPU time | 677.44 seconds |
| Started | Aug 12 07:18:44 PM PDT 24 |
| Finished | Aug 12 07:30:02 PM PDT 24 |
| Peak memory | 612528 kb |
| Host | smart-6fbbde98-dd9a-4308-84c1-db4d7fbfc027 |
| User | root |
| Command | /workspace/default/simv +chip_clock_source=ChipClockSourceExternal96Mhz +calibrate_usb_clk=1 +src_dec_state=DecLcStRma +sw_build_device=sim_dv +sw_ima ges=clkmgr_external_clk_src_for_sw_fast_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=469196153 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ= chip_sw_lc_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_cl kmgr_external_clk_src_for_sw_fast_rma.469196153 |
| Directory | /workspace/1.chip_sw_clkmgr_external_clk_src_for_sw_fast_rma/latest |
| Test location | /workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0.646267175 |
| Short name | T445 |
| Test name | |
| Test status | |
| Simulation time | 4525293538 ps |
| CPU time | 701.22 seconds |
| Started | Aug 12 07:18:12 PM PDT 24 |
| Finished | Aug 12 07:29:54 PM PDT 24 |
| Peak memory | 613656 kb |
| Host | smart-4bc023ac-864d-48ff-9519-6170d45092a8 |
| User | root |
| Command | /workspace/default/simv +chip_clock_source=ChipClockSourceExternal96Mhz +calibrate_usb_clk=1 +src_dec_state=DecLcStTestUnlocked0 +sw_build_device=sim_ dv +sw_images=clkmgr_external_clk_src_for_sw_fast_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=646267175 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM _TEST_SEQ=chip_sw_lc_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1. chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0.646267175 |
| Directory | /workspace/1.chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0/latest |
| Test location | /workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_slow_dev.2737751463 |
| Short name | T128 |
| Test name | |
| Test status | |
| Simulation time | 4887485560 ps |
| CPU time | 662.89 seconds |
| Started | Aug 12 07:18:19 PM PDT 24 |
| Finished | Aug 12 07:29:22 PM PDT 24 |
| Peak memory | 613324 kb |
| Host | smart-35335899-8207-4b05-9cf2-e94dcda0c6be |
| User | root |
| Command | /workspace/default/simv +chip_clock_source=ChipClockSourceExternal48Mhz +calibrate_usb_clk=1 +src_dec_state=DecLcStDev +sw_build_device=sim_dv +sw_ima ges=clkmgr_external_clk_src_for_sw_slow_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2737751463 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ =chip_sw_lc_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_c lkmgr_external_clk_src_for_sw_slow_dev.2737751463 |
| Directory | /workspace/1.chip_sw_clkmgr_external_clk_src_for_sw_slow_dev/latest |
| Test location | /workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_slow_rma.2432551377 |
| Short name | T1347 |
| Test name | |
| Test status | |
| Simulation time | 5092961442 ps |
| CPU time | 681.02 seconds |
| Started | Aug 12 07:19:06 PM PDT 24 |
| Finished | Aug 12 07:30:27 PM PDT 24 |
| Peak memory | 612544 kb |
| Host | smart-c93978e8-acf4-4ed6-b9ec-5dc9ea1e7055 |
| User | root |
| Command | /workspace/default/simv +chip_clock_source=ChipClockSourceExternal48Mhz +calibrate_usb_clk=1 +src_dec_state=DecLcStRma +sw_build_device=sim_dv +sw_ima ges=clkmgr_external_clk_src_for_sw_slow_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2432551377 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ =chip_sw_lc_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_c lkmgr_external_clk_src_for_sw_slow_rma.2432551377 |
| Directory | /workspace/1.chip_sw_clkmgr_external_clk_src_for_sw_slow_rma/latest |
| Test location | /workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0.3141755129 |
| Short name | T126 |
| Test name | |
| Test status | |
| Simulation time | 4325041732 ps |
| CPU time | 694.3 seconds |
| Started | Aug 12 07:18:31 PM PDT 24 |
| Finished | Aug 12 07:30:05 PM PDT 24 |
| Peak memory | 612660 kb |
| Host | smart-21106604-00c7-48cd-9db5-d74c116aa1e7 |
| User | root |
| Command | /workspace/default/simv +chip_clock_source=ChipClockSourceExternal48Mhz +calibrate_usb_clk=1 +src_dec_state=DecLcStTestUnlocked0 +sw_build_device=sim_ dv +sw_images=clkmgr_external_clk_src_for_sw_slow_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3141755129 -assert nopostproc +UVM_TESTNAME=chip_base_test +UV M_TEST_SEQ=chip_sw_lc_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1 .chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0.3141755129 |
| Directory | /workspace/1.chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0/latest |
| Test location | /workspace/coverage/default/1.chip_sw_clkmgr_jitter.151182692 |
| Short name | T979 |
| Test name | |
| Test status | |
| Simulation time | 3208114119 ps |
| CPU time | 334 seconds |
| Started | Aug 12 07:19:23 PM PDT 24 |
| Finished | Aug 12 07:24:57 PM PDT 24 |
| Peak memory | 610088 kb |
| Host | smart-9783cd9f-aa88-4f05-bc63-3fafc6c29f74 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=clkmgr_jitter_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=151182692 -assert nopostproc +UVM_TESTNAME= chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/ null -cm_name 1.chip_sw_clkmgr_jitter.151182692 |
| Directory | /workspace/1.chip_sw_clkmgr_jitter/latest |
| Test location | /workspace/coverage/default/1.chip_sw_clkmgr_jitter_frequency.636013168 |
| Short name | T1194 |
| Test name | |
| Test status | |
| Simulation time | 4151517184 ps |
| CPU time | 481.67 seconds |
| Started | Aug 12 07:18:55 PM PDT 24 |
| Finished | Aug 12 07:26:57 PM PDT 24 |
| Peak memory | 609904 kb |
| Host | smart-f454c976-4ee5-470a-9190-6b9c063efbb9 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=clkmgr_jitter_frequency_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=636013168 -assert nopostproc +UVM _TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm _log /dev/null -cm_name 1.chip_sw_clkmgr_jitter_frequency.636013168 |
| Directory | /workspace/1.chip_sw_clkmgr_jitter_frequency/latest |
| Test location | /workspace/coverage/default/1.chip_sw_clkmgr_jitter_reduced_freq.1970885329 |
| Short name | T2 |
| Test name | |
| Test status | |
| Simulation time | 2610208920 ps |
| CPU time | 232.03 seconds |
| Started | Aug 12 07:20:09 PM PDT 24 |
| Finished | Aug 12 07:24:01 PM PDT 24 |
| Peak memory | 609956 kb |
| Host | smart-c23eebaa-07de-4a34-a2cc-06d19a3ddab8 |
| User | root |
| Command | /workspace/default/simv +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=clkmgr_jitter_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1970885329 -assert nop ostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def ault.vdb -cm_log /dev/null -cm_name 1.chip_sw_clkmgr_jitter_reduced_freq.1970885329 |
| Directory | /workspace/1.chip_sw_clkmgr_jitter_reduced_freq/latest |
| Test location | /workspace/coverage/default/1.chip_sw_clkmgr_off_aes_trans.2788800394 |
| Short name | T974 |
| Test name | |
| Test status | |
| Simulation time | 5829908000 ps |
| CPU time | 668.05 seconds |
| Started | Aug 12 07:18:53 PM PDT 24 |
| Finished | Aug 12 07:30:01 PM PDT 24 |
| Peak memory | 609816 kb |
| Host | smart-ddee3757-be0a-40d1-8501-1a61ee08397e |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=clkmgr_off_aes_trans_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2788800394 -assert nopostproc +UVM_T ESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l og /dev/null -cm_name 1.chip_sw_clkmgr_off_aes_trans.2788800394 |
| Directory | /workspace/1.chip_sw_clkmgr_off_aes_trans/latest |
| Test location | /workspace/coverage/default/1.chip_sw_clkmgr_off_hmac_trans.864363287 |
| Short name | T1074 |
| Test name | |
| Test status | |
| Simulation time | 3611167000 ps |
| CPU time | 332.56 seconds |
| Started | Aug 12 07:18:25 PM PDT 24 |
| Finished | Aug 12 07:23:58 PM PDT 24 |
| Peak memory | 609876 kb |
| Host | smart-c6274987-f58e-49e0-8de0-706988998832 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=clkmgr_off_hmac_trans_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=864363287 -assert nopostproc +UVM_T ESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l og /dev/null -cm_name 1.chip_sw_clkmgr_off_hmac_trans.864363287 |
| Directory | /workspace/1.chip_sw_clkmgr_off_hmac_trans/latest |
| Test location | /workspace/coverage/default/1.chip_sw_clkmgr_off_kmac_trans.1167884004 |
| Short name | T1108 |
| Test name | |
| Test status | |
| Simulation time | 5240759634 ps |
| CPU time | 690.39 seconds |
| Started | Aug 12 07:19:21 PM PDT 24 |
| Finished | Aug 12 07:30:51 PM PDT 24 |
| Peak memory | 610676 kb |
| Host | smart-83279049-ef16-4c6d-ba85-9b32573fa07a |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=clkmgr_off_kmac_trans_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1167884004 -assert nopostproc +UVM_ TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_ log /dev/null -cm_name 1.chip_sw_clkmgr_off_kmac_trans.1167884004 |
| Directory | /workspace/1.chip_sw_clkmgr_off_kmac_trans/latest |
| Test location | /workspace/coverage/default/1.chip_sw_clkmgr_off_otbn_trans.4025689853 |
| Short name | T1081 |
| Test name | |
| Test status | |
| Simulation time | 4952788460 ps |
| CPU time | 588.01 seconds |
| Started | Aug 12 07:22:36 PM PDT 24 |
| Finished | Aug 12 07:32:24 PM PDT 24 |
| Peak memory | 610592 kb |
| Host | smart-daba5ff9-1e6f-4930-9f9e-f5a49f6ad5d7 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=clkmgr_off_otbn_trans_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4025689853 -assert nopostproc +UVM_ TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_ log /dev/null -cm_name 1.chip_sw_clkmgr_off_otbn_trans.4025689853 |
| Directory | /workspace/1.chip_sw_clkmgr_off_otbn_trans/latest |
| Test location | /workspace/coverage/default/1.chip_sw_clkmgr_off_peri.228545718 |
| Short name | T1139 |
| Test name | |
| Test status | |
| Simulation time | 9131232560 ps |
| CPU time | 1566.88 seconds |
| Started | Aug 12 07:18:15 PM PDT 24 |
| Finished | Aug 12 07:44:23 PM PDT 24 |
| Peak memory | 610644 kb |
| Host | smart-4fbf99c1-7e98-4c02-87f3-b80324182ba6 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=30_000_000 +sw_build_device=sim_dv +sw_images=clkmgr_off_peri_test:1:new_rules,test_rom:0 +cdc_instrumenta tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=228545718 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/c overage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_clkmgr_off_peri.228545718 |
| Directory | /workspace/1.chip_sw_clkmgr_off_peri/latest |
| Test location | /workspace/coverage/default/1.chip_sw_clkmgr_reset_frequency.3600492394 |
| Short name | T1275 |
| Test name | |
| Test status | |
| Simulation time | 3452619832 ps |
| CPU time | 570.76 seconds |
| Started | Aug 12 07:18:29 PM PDT 24 |
| Finished | Aug 12 07:28:00 PM PDT 24 |
| Peak memory | 610228 kb |
| Host | smart-abc21d66-eef7-4688-8d9e-45a11010a5ce |
| User | root |
| Command | /workspace/default/simv +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=clkmgr_reset_frequency_test:1:new_rules,test_rom:0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3600492394 -a ssert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov erage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_clkmgr_reset_frequency.3600492394 |
| Directory | /workspace/1.chip_sw_clkmgr_reset_frequency/latest |
| Test location | /workspace/coverage/default/1.chip_sw_clkmgr_sleep_frequency.2990090239 |
| Short name | T1304 |
| Test name | |
| Test status | |
| Simulation time | 4901282352 ps |
| CPU time | 815.5 seconds |
| Started | Aug 12 07:19:49 PM PDT 24 |
| Finished | Aug 12 07:33:25 PM PDT 24 |
| Peak memory | 610484 kb |
| Host | smart-60752030-54c1-41d8-8506-fa1d1f0cb353 |
| User | root |
| Command | /workspace/default/simv +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=clkmgr_sleep_frequency_test:1:new_rules,test_rom:0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2990090239 -a ssert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov erage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_clkmgr_sleep_frequency.2990090239 |
| Directory | /workspace/1.chip_sw_clkmgr_sleep_frequency/latest |
| Test location | /workspace/coverage/default/1.chip_sw_clkmgr_smoketest.2524513234 |
| Short name | T113 |
| Test name | |
| Test status | |
| Simulation time | 3080670668 ps |
| CPU time | 228.14 seconds |
| Started | Aug 12 07:24:24 PM PDT 24 |
| Finished | Aug 12 07:28:12 PM PDT 24 |
| Peak memory | 610072 kb |
| Host | smart-eab53326-f515-42ae-94c1-939b75f441ef |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=clkmgr_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2524513234 -assert nopostproc +UVM_TESTNAME=c hip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n ull -cm_name 1.chip_sw_clkmgr_smoketest.2524513234 |
| Directory | /workspace/1.chip_sw_clkmgr_smoketest/latest |
| Test location | /workspace/coverage/default/1.chip_sw_csrng_edn_concurrency.3636817506 |
| Short name | T1338 |
| Test name | |
| Test status | |
| Simulation time | 31516191912 ps |
| CPU time | 6359.66 seconds |
| Started | Aug 12 07:15:46 PM PDT 24 |
| Finished | Aug 12 09:01:46 PM PDT 24 |
| Peak memory | 609748 kb |
| Host | smart-3dabce76-fc4b-4ba8-a6a3-ae10252a0e1f |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=140_000_000 +rng_srate_value_min=15 +rng_srate_value_max=20 +sw_build_device=sim_dv +sw_images=csrng_edn_c oncurrency_test:1:new_rules,test_rom:0 +accelerate_cold_power_up_time=3 +accelerate_regulators_power_up_time=2 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3636817506 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd b -cm_log /dev/null -cm_name 1.chip_sw_csrng_edn_concurrency.3636817506 |
| Directory | /workspace/1.chip_sw_csrng_edn_concurrency/latest |
| Test location | /workspace/coverage/default/1.chip_sw_csrng_fuse_en_sw_app_read_test.514340039 |
| Short name | T1435 |
| Test name | |
| Test status | |
| Simulation time | 4535560464 ps |
| CPU time | 506.74 seconds |
| Started | Aug 12 07:15:15 PM PDT 24 |
| Finished | Aug 12 07:23:42 PM PDT 24 |
| Peak memory | 611248 kb |
| Host | smart-9354c14a-f685-4dbc-b81d-138f17cdda20 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=15_000_000 +sw_build_device=sim_dv +sw_images=csrng_fuse_en_sw_app_read:1:new_rules,test_rom:0 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=51434 0039 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_entropy_src_fuse_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_csrng_fuse_en_sw_app_read_test.514340039 |
| Directory | /workspace/1.chip_sw_csrng_fuse_en_sw_app_read_test/latest |
| Test location | /workspace/coverage/default/1.chip_sw_csrng_kat_test.1444429645 |
| Short name | T1402 |
| Test name | |
| Test status | |
| Simulation time | 2469923080 ps |
| CPU time | 227.1 seconds |
| Started | Aug 12 07:15:19 PM PDT 24 |
| Finished | Aug 12 07:19:06 PM PDT 24 |
| Peak memory | 610176 kb |
| Host | smart-2598304d-de2a-4243-84fe-ebbbeb41e3e9 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=csrng_kat_test:1:new_rules,test_rom:0 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1444429645 -asse rt nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera ge/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_csrng_kat_test.1444429645 |
| Directory | /workspace/1.chip_sw_csrng_kat_test/latest |
| Test location | /workspace/coverage/default/1.chip_sw_csrng_lc_hw_debug_en_test.3306833614 |
| Short name | T1284 |
| Test name | |
| Test status | |
| Simulation time | 6094638039 ps |
| CPU time | 705.83 seconds |
| Started | Aug 12 07:15:34 PM PDT 24 |
| Finished | Aug 12 07:27:21 PM PDT 24 |
| Peak memory | 611428 kb |
| Host | smart-c9e9ef1a-78a3-4b5c-829a-c45391f6585c |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=15_000_000 +rng_srate_value_min=15 +use_otp_image=OtpTypeLcStTestUnlocked0 +sw_build_device=sim_dv +sw_ima ges=csrng_lc_hw_debug_en_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3306833614 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_csrng_ lc_hw_debug_en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_csr ng_lc_hw_debug_en_test.3306833614 |
| Directory | /workspace/1.chip_sw_csrng_lc_hw_debug_en_test/latest |
| Test location | /workspace/coverage/default/1.chip_sw_csrng_smoketest.3972621833 |
| Short name | T1436 |
| Test name | |
| Test status | |
| Simulation time | 2653940000 ps |
| CPU time | 197.51 seconds |
| Started | Aug 12 07:21:35 PM PDT 24 |
| Finished | Aug 12 07:24:53 PM PDT 24 |
| Peak memory | 610036 kb |
| Host | smart-b2c96909-a8bb-4112-845f-fbc7a45fa42d |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=csrng_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3972621833 -assert nopostproc +UVM_TESTNAME=ch ip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu ll -cm_name 1.chip_sw_csrng_smoketest.3972621833 |
| Directory | /workspace/1.chip_sw_csrng_smoketest/latest |
| Test location | /workspace/coverage/default/1.chip_sw_data_integrity_escalation.4063856680 |
| Short name | T283 |
| Test name | |
| Test status | |
| Simulation time | 6411719688 ps |
| CPU time | 784.65 seconds |
| Started | Aug 12 07:14:14 PM PDT 24 |
| Finished | Aug 12 07:27:19 PM PDT 24 |
| Peak memory | 611532 kb |
| Host | smart-e2b6ebcb-a5cc-4ac0-9587-63cbcc8c8951 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=data_integrity_escalation_reset_test:1:new_rules,test_ro m:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=4063856680 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_data_integrity_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_data_integrity_escalation.4063856680 |
| Directory | /workspace/1.chip_sw_data_integrity_escalation/latest |
| Test location | /workspace/coverage/default/1.chip_sw_edn_auto_mode.2470342516 |
| Short name | T1276 |
| Test name | |
| Test status | |
| Simulation time | 4833855788 ps |
| CPU time | 1184.83 seconds |
| Started | Aug 12 07:14:58 PM PDT 24 |
| Finished | Aug 12 07:34:44 PM PDT 24 |
| Peak memory | 610656 kb |
| Host | smart-a92c0e8f-00b0-4382-a9a6-c6172f965239 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +rng_srate_value=5 +sw_build_device=sim_dv +sw_images=edn_auto_mode:1:new_rules,test_rom:0 +acc elerate_cold_power_up_time=3 +accelerate_regulators_power_up_time=2 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2470342516 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ =chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_edn_ auto_mode.2470342516 |
| Directory | /workspace/1.chip_sw_edn_auto_mode/latest |
| Test location | /workspace/coverage/default/1.chip_sw_edn_boot_mode.2461927651 |
| Short name | T434 |
| Test name | |
| Test status | |
| Simulation time | 2765678586 ps |
| CPU time | 654.11 seconds |
| Started | Aug 12 07:16:54 PM PDT 24 |
| Finished | Aug 12 07:27:49 PM PDT 24 |
| Peak memory | 610452 kb |
| Host | smart-76b6d58f-fa37-4ee5-a7cd-fa699c3e619c |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +rng_srate_value=5 +sw_build_device=sim_dv +sw_images=edn_boot_mode:1:new_rules,test_rom:0 +acc elerate_cold_power_up_time=3 +accelerate_regulators_power_up_time=2 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2461927651 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ =chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_edn_ boot_mode.2461927651 |
| Directory | /workspace/1.chip_sw_edn_boot_mode/latest |
| Test location | /workspace/coverage/default/1.chip_sw_edn_entropy_reqs.1870057338 |
| Short name | T1383 |
| Test name | |
| Test status | |
| Simulation time | 6815261682 ps |
| CPU time | 1405.56 seconds |
| Started | Aug 12 07:16:03 PM PDT 24 |
| Finished | Aug 12 07:39:29 PM PDT 24 |
| Peak memory | 611372 kb |
| Host | smart-aed5ea85-f7fa-4d6c-ae97-39b7f0552b9b |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=15000000 +rng_srate_value_min=15 +rng_srate_value_max=30 +sw_build_device=sim_dv +sw_images=entropy_src_ed n_reqs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1870057338 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_edn_entropy_reqs.1870057338 |
| Directory | /workspace/1.chip_sw_edn_entropy_reqs/latest |
| Test location | /workspace/coverage/default/1.chip_sw_edn_entropy_reqs_jitter.2504093593 |
| Short name | T1085 |
| Test name | |
| Test status | |
| Simulation time | 6580795596 ps |
| CPU time | 1319.38 seconds |
| Started | Aug 12 07:20:47 PM PDT 24 |
| Finished | Aug 12 07:42:47 PM PDT 24 |
| Peak memory | 611380 kb |
| Host | smart-d48055b9-aac6-4b1f-a79f-cd5127b6d076 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=15000000 +rng_srate_value_min=15 +rng_srate_value_max=30 +en_jitter=1 +sw_build_device=sim_dv +sw_images=e ntropy_src_edn_reqs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2504093593 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_edn_entropy_reqs_jitter.2504093593 |
| Directory | /workspace/1.chip_sw_edn_entropy_reqs_jitter/latest |
| Test location | /workspace/coverage/default/1.chip_sw_edn_kat.185632930 |
| Short name | T1191 |
| Test name | |
| Test status | |
| Simulation time | 3390098652 ps |
| CPU time | 569.43 seconds |
| Started | Aug 12 07:16:44 PM PDT 24 |
| Finished | Aug 12 07:26:14 PM PDT 24 |
| Peak memory | 615760 kb |
| Host | smart-721ade16-a5d7-41fe-9bdc-f945de92c6f0 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +rng_srate_value=5 +disable_assert_edn_output_diff_from_prev=1 +sw_build_device=sim_dv +sw_imag es=edn_kat:1:new_rules,test_rom:0 +accelerate_cold_power_up_time=3 +accelerate_regulators_power_up_time=2 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=185632930 -assert nopostproc +UVM_ TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_ log /dev/null -cm_name 1.chip_sw_edn_kat.185632930 |
| Directory | /workspace/1.chip_sw_edn_kat/latest |
| Test location | /workspace/coverage/default/1.chip_sw_edn_sw_mode.1275195233 |
| Short name | T1066 |
| Test name | |
| Test status | |
| Simulation time | 10203376996 ps |
| CPU time | 2175.31 seconds |
| Started | Aug 12 07:16:46 PM PDT 24 |
| Finished | Aug 12 07:53:02 PM PDT 24 |
| Peak memory | 610456 kb |
| Host | smart-c3972f33-634c-4b14-bc20-15e7f1945958 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=edn_sw_mode:1:new_rules,test_rom:0 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1275195233 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/ default.vdb -cm_log /dev/null -cm_name 1.chip_sw_edn_sw_mode.1275195233 |
| Directory | /workspace/1.chip_sw_edn_sw_mode/latest |
| Test location | /workspace/coverage/default/1.chip_sw_entropy_src_ast_rng_req.260451242 |
| Short name | T435 |
| Test name | |
| Test status | |
| Simulation time | 3041094130 ps |
| CPU time | 267.28 seconds |
| Started | Aug 12 07:15:54 PM PDT 24 |
| Finished | Aug 12 07:20:22 PM PDT 24 |
| Peak memory | 610064 kb |
| Host | smart-29c32b2c-aacc-4586-9ba5-9eda7e160424 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=15_000_000 +sw_build_device=sim_dv +sw_images=entropy_src_ast_rng_req_test:1:new_rules,test_rom:0 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26 0451242 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_entropy_src_ast_rng_req.260451242 |
| Directory | /workspace/1.chip_sw_entropy_src_ast_rng_req/latest |
| Test location | /workspace/coverage/default/1.chip_sw_entropy_src_kat_test.998533221 |
| Short name | T970 |
| Test name | |
| Test status | |
| Simulation time | 2815113480 ps |
| CPU time | 243.14 seconds |
| Started | Aug 12 07:14:50 PM PDT 24 |
| Finished | Aug 12 07:18:53 PM PDT 24 |
| Peak memory | 609896 kb |
| Host | smart-640960ef-95a9-4b9b-91c9-66ba9a405b6d |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=entropy_src_kat_test:1:new_rules,test_rom:0 +cdc_instrumenta tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=998533221 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/c overage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_entropy_src_kat_test.998533221 |
| Directory | /workspace/1.chip_sw_entropy_src_kat_test/latest |
| Test location | /workspace/coverage/default/1.chip_sw_entropy_src_smoketest.421419099 |
| Short name | T1137 |
| Test name | |
| Test status | |
| Simulation time | 4061324620 ps |
| CPU time | 557.36 seconds |
| Started | Aug 12 07:21:41 PM PDT 24 |
| Finished | Aug 12 07:30:59 PM PDT 24 |
| Peak memory | 610196 kb |
| Host | smart-ffb3db1f-0e6c-46b2-92f0-d4c2fac8aba8 |
| User | root |
| Command | /workspace/default/simv +rng_srate_value_min=15 +rng_srate_value_max=30 +sw_build_device=sim_dv +sw_images=entropy_src_smoketest:1:new_rules,test_rom: 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand om_seed=421419099 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_entropy_src_smoketest.421419099 |
| Directory | /workspace/1.chip_sw_entropy_src_smoketest/latest |
| Test location | /workspace/coverage/default/1.chip_sw_example_concurrency.575923964 |
| Short name | T1175 |
| Test name | |
| Test status | |
| Simulation time | 2494355840 ps |
| CPU time | 182.96 seconds |
| Started | Aug 12 07:11:08 PM PDT 24 |
| Finished | Aug 12 07:14:11 PM PDT 24 |
| Peak memory | 610136 kb |
| Host | smart-e7d26f08-d544-4890-9594-94cc68577e73 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=example_concurrency_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=575923964 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_example_concurrency.575923964 |
| Directory | /workspace/1.chip_sw_example_concurrency/latest |
| Test location | /workspace/coverage/default/1.chip_sw_example_flash.2117251555 |
| Short name | T1296 |
| Test name | |
| Test status | |
| Simulation time | 3012526680 ps |
| CPU time | 215.93 seconds |
| Started | Aug 12 07:13:11 PM PDT 24 |
| Finished | Aug 12 07:16:47 PM PDT 24 |
| Peak memory | 607392 kb |
| Host | smart-e6c2c67e-167e-4562-878c-540a0ed71b6a |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=example_test_from_flash:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2117251555 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_example_flash.2117251555 |
| Directory | /workspace/1.chip_sw_example_flash/latest |
| Test location | /workspace/coverage/default/1.chip_sw_example_manufacturer.233773787 |
| Short name | T1329 |
| Test name | |
| Test status | |
| Simulation time | 2859212836 ps |
| CPU time | 201.96 seconds |
| Started | Aug 12 07:15:12 PM PDT 24 |
| Finished | Aug 12 07:18:34 PM PDT 24 |
| Peak memory | 610124 kb |
| Host | smart-c762cf7e-7f2f-400f-8091-7cc0f19c2439 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=example_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=233773787 -assert nopostproc +UVM_TESTNAME=chip_b ase_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 1.chip_sw_example_manufacturer.233773787 |
| Directory | /workspace/1.chip_sw_example_manufacturer/latest |
| Test location | /workspace/coverage/default/1.chip_sw_example_rom.472450649 |
| Short name | T295 |
| Test name | |
| Test status | |
| Simulation time | 2540776536 ps |
| CPU time | 125.63 seconds |
| Started | Aug 12 07:12:15 PM PDT 24 |
| Finished | Aug 12 07:14:20 PM PDT 24 |
| Peak memory | 608348 kb |
| Host | smart-2fd5133e-c100-4b9c-8a9e-bccc238caf55 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=example_test_from_rom:0:test_in_rom:new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=472450649 -assert nopostproc +UVM_TESTN AME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log / dev/null -cm_name 1.chip_sw_example_rom.472450649 |
| Directory | /workspace/1.chip_sw_example_rom/latest |
| Test location | /workspace/coverage/default/1.chip_sw_exit_test_unlocked_bootstrap.188763782 |
| Short name | T1269 |
| Test name | |
| Test status | |
| Simulation time | 57777119448 ps |
| CPU time | 10042.4 seconds |
| Started | Aug 12 07:12:16 PM PDT 24 |
| Finished | Aug 12 09:59:39 PM PDT 24 |
| Peak memory | 625204 kb |
| Host | smart-c017438e-343f-40ad-a4e3-fc1eac3bec50 |
| User | root |
| Command | /workspace/default/simv +flash_program_latency=5 +sw_test_timeout_ns=150_000_000 +sw_build_device=sim_dv +sw_images=exit_test_unlocked_bootstrap:1:new _rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/s im.tcl +ntb_random_seed=188763782 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_exit_test_unlocked_bootstrap_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_exit_test_unlocked_bootstrap.188763782 |
| Directory | /workspace/1.chip_sw_exit_test_unlocked_bootstrap/latest |
| Test location | /workspace/coverage/default/1.chip_sw_flash_crash_alert.3754233648 |
| Short name | T1140 |
| Test name | |
| Test status | |
| Simulation time | 4905456200 ps |
| CPU time | 815.92 seconds |
| Started | Aug 12 07:19:59 PM PDT 24 |
| Finished | Aug 12 07:33:36 PM PDT 24 |
| Peak memory | 611572 kb |
| Host | smart-95157baf-f416-4569-8865-6472aaf930e1 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=8_000_000 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1: new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tool s/sim.tcl +ntb_random_seed=3754233648 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_flash_host_gnt_err_inj_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_flash_crash_alert.3754233648 |
| Directory | /workspace/1.chip_sw_flash_crash_alert/latest |
| Test location | /workspace/coverage/default/1.chip_sw_flash_ctrl_access.815564760 |
| Short name | T1012 |
| Test name | |
| Test status | |
| Simulation time | 5510911690 ps |
| CPU time | 1058.94 seconds |
| Started | Aug 12 07:13:06 PM PDT 24 |
| Finished | Aug 12 07:30:46 PM PDT 24 |
| Peak memory | 609764 kb |
| Host | smart-d1a031b2-8116-4215-9166-fa458cd13507 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=flash_ctrl_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=815564760 -assert nopostproc +UVM_TESTNAME=chi p_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul l -cm_name 1.chip_sw_flash_ctrl_access.815564760 |
| Directory | /workspace/1.chip_sw_flash_ctrl_access/latest |
| Test location | /workspace/coverage/default/1.chip_sw_flash_ctrl_access_jitter_en.412757439 |
| Short name | T1044 |
| Test name | |
| Test status | |
| Simulation time | 6084727500 ps |
| CPU time | 1176.84 seconds |
| Started | Aug 12 07:16:14 PM PDT 24 |
| Finished | Aug 12 07:35:52 PM PDT 24 |
| Peak memory | 610540 kb |
| Host | smart-77e3bc69-9c9e-447d-b206-81def6b815fc |
| User | root |
| Command | /workspace/default/simv +en_jitter=1 +sw_build_device=sim_dv +sw_images=flash_ctrl_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=412757439 -assert nopostproc +UVM _TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm _log /dev/null -cm_name 1.chip_sw_flash_ctrl_access_jitter_en.412757439 |
| Directory | /workspace/1.chip_sw_flash_ctrl_access_jitter_en/latest |
| Test location | /workspace/coverage/default/1.chip_sw_flash_ctrl_access_jitter_en_reduced_freq.2907258395 |
| Short name | T1234 |
| Test name | |
| Test status | |
| Simulation time | 7129557354 ps |
| CPU time | 1250.77 seconds |
| Started | Aug 12 07:20:45 PM PDT 24 |
| Finished | Aug 12 07:41:36 PM PDT 24 |
| Peak memory | 609280 kb |
| Host | smart-20241fda-b585-44c2-aff0-e78811aa7f31 |
| User | root |
| Command | /workspace/default/simv +en_jitter=1 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=flash_ctrl_test:1:new_rules,test_rom:0 +cdc_instrumentati on_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2907258395 - assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co verage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_flash_ctrl_access_jitter_en_reduced_freq.2907258395 |
| Directory | /workspace/1.chip_sw_flash_ctrl_access_jitter_en_reduced_freq/latest |
| Test location | /workspace/coverage/default/1.chip_sw_flash_ctrl_clock_freqs.1592582770 |
| Short name | T409 |
| Test name | |
| Test status | |
| Simulation time | 6282863184 ps |
| CPU time | 1357.64 seconds |
| Started | Aug 12 07:13:54 PM PDT 24 |
| Finished | Aug 12 07:36:32 PM PDT 24 |
| Peak memory | 609808 kb |
| Host | smart-c47b41c2-713b-4462-aa76-ea627d2ce165 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=flash_ctrl_clock_freqs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1592582770 -assert nopostproc +UVM _TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm _log /dev/null -cm_name 1.chip_sw_flash_ctrl_clock_freqs.1592582770 |
| Directory | /workspace/1.chip_sw_flash_ctrl_clock_freqs/latest |
| Test location | /workspace/coverage/default/1.chip_sw_flash_ctrl_idle_low_power.1228700373 |
| Short name | T1198 |
| Test name | |
| Test status | |
| Simulation time | 3526281930 ps |
| CPU time | 420.94 seconds |
| Started | Aug 12 07:17:36 PM PDT 24 |
| Finished | Aug 12 07:24:37 PM PDT 24 |
| Peak memory | 610068 kb |
| Host | smart-2f52ef16-8ac0-4845-a9ea-d6d7b7c1fdf9 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=flash_ctrl_idle_low_power_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1228700373 -assert nopostproc + UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_flash_ctrl_idle_low_power.1228700373 |
| Directory | /workspace/1.chip_sw_flash_ctrl_idle_low_power/latest |
| Test location | /workspace/coverage/default/1.chip_sw_flash_ctrl_mem_protection.1192441920 |
| Short name | T1331 |
| Test name | |
| Test status | |
| Simulation time | 5600594500 ps |
| CPU time | 1092.31 seconds |
| Started | Aug 12 07:22:11 PM PDT 24 |
| Finished | Aug 12 07:40:24 PM PDT 24 |
| Peak memory | 610544 kb |
| Host | smart-4d65aab1-aa48-453a-af6a-4212b7689ad6 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=flash_ctrl_mem_protection_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1192441920 -assert nopostproc + UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_flash_ctrl_mem_protection.1192441920 |
| Directory | /workspace/1.chip_sw_flash_ctrl_mem_protection/latest |
| Test location | /workspace/coverage/default/1.chip_sw_flash_ctrl_ops.2079587124 |
| Short name | T1260 |
| Test name | |
| Test status | |
| Simulation time | 3371615396 ps |
| CPU time | 639.13 seconds |
| Started | Aug 12 07:13:36 PM PDT 24 |
| Finished | Aug 12 07:24:16 PM PDT 24 |
| Peak memory | 610280 kb |
| Host | smart-fd847e36-0472-4e7a-a9fb-d4389ea7403a |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=50_000_000 +sw_build_device=sim_dv +sw_images=flash_ctrl_ops_test:1:new_rules,test_rom:0 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2079587124 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/c overage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_flash_ctrl_ops.2079587124 |
| Directory | /workspace/1.chip_sw_flash_ctrl_ops/latest |
| Test location | /workspace/coverage/default/1.chip_sw_flash_ctrl_ops_jitter_en.3662056843 |
| Short name | T376 |
| Test name | |
| Test status | |
| Simulation time | 4303298820 ps |
| CPU time | 776.79 seconds |
| Started | Aug 12 07:14:01 PM PDT 24 |
| Finished | Aug 12 07:26:58 PM PDT 24 |
| Peak memory | 610628 kb |
| Host | smart-ec03e0ba-6048-4fec-89d1-38b329191325 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=50_000_000 +en_jitter=1 +sw_build_device=sim_dv +sw_images=flash_ctrl_ops_test:1:new_rules,test_rom:0 +cdc _instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see d=3662056843 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_flash_ctrl_ops_jitter_en.3662056843 |
| Directory | /workspace/1.chip_sw_flash_ctrl_ops_jitter_en/latest |
| Test location | /workspace/coverage/default/1.chip_sw_flash_ctrl_write_clear.2106971501 |
| Short name | T992 |
| Test name | |
| Test status | |
| Simulation time | 3266146536 ps |
| CPU time | 321.77 seconds |
| Started | Aug 12 07:20:53 PM PDT 24 |
| Finished | Aug 12 07:26:15 PM PDT 24 |
| Peak memory | 608916 kb |
| Host | smart-afaf49b6-2740-4d03-bc74-1c38e398bad1 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=8_000_000 +sw_build_device=sim_dv +sw_images=flash_ctrl_write_clear_test:1:new_rules,test_rom:0 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2106971 501 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ce/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_flash_ctrl_write_clear.2106971501 |
| Directory | /workspace/1.chip_sw_flash_ctrl_write_clear/latest |
| Test location | /workspace/coverage/default/1.chip_sw_flash_init.3660780580 |
| Short name | T235 |
| Test name | |
| Test status | |
| Simulation time | 17885083712 ps |
| CPU time | 2445.97 seconds |
| Started | Aug 12 07:11:52 PM PDT 24 |
| Finished | Aug 12 07:52:39 PM PDT 24 |
| Peak memory | 615132 kb |
| Host | smart-dfea259d-8512-40e0-a276-c7b200611f2e |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=25_000_000 +sw_build_device=sim_dv +sw_images=flash_init_test:0:test_in_rom:new_rules +cdc_instrumentation _enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3660780580 -as sert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_flash_init_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac e/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_flash_init.3660780580 |
| Directory | /workspace/1.chip_sw_flash_init/latest |
| Test location | /workspace/coverage/default/1.chip_sw_flash_init_reduced_freq.4280015958 |
| Short name | T1237 |
| Test name | |
| Test status | |
| Simulation time | 24999240461 ps |
| CPU time | 2226.88 seconds |
| Started | Aug 12 07:19:54 PM PDT 24 |
| Finished | Aug 12 07:57:01 PM PDT 24 |
| Peak memory | 610948 kb |
| Host | smart-9d172bd0-37c3-4548-a31e-be8d7b0530bd |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=25_000_000 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=flash_init_test:0:test_in_rom:new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=4280015958 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_flash_init_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_flash_init_reduced_freq.4280015958 |
| Directory | /workspace/1.chip_sw_flash_init_reduced_freq/latest |
| Test location | /workspace/coverage/default/1.chip_sw_flash_scrambling_smoketest.2679623695 |
| Short name | T276 |
| Test name | |
| Test status | |
| Simulation time | 3380775812 ps |
| CPU time | 265.81 seconds |
| Started | Aug 12 07:27:11 PM PDT 24 |
| Finished | Aug 12 07:31:37 PM PDT 24 |
| Peak memory | 609908 kb |
| Host | smart-f406f34b-6468-45b7-8206-42d30de15e3f |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=flash_scrambling_smoketest:1:new_rules,flash_scrambling_smoket est_otp_img_rma:4,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=2679623695 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_flash_scrambling_smoketest.2679623695 |
| Directory | /workspace/1.chip_sw_flash_scrambling_smoketest/latest |
| Test location | /workspace/coverage/default/1.chip_sw_gpio.281634324 |
| Short name | T30 |
| Test name | |
| Test status | |
| Simulation time | 3980195395 ps |
| CPU time | 460.32 seconds |
| Started | Aug 12 07:13:06 PM PDT 24 |
| Finished | Aug 12 07:20:46 PM PDT 24 |
| Peak memory | 609672 kb |
| Host | smart-7cf2b95d-11c3-4486-9c3c-5c117c14d88f |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=gpio_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=281634324 -assert nopostproc +UVM_TESTNAME=chip_base _test +UVM_TEST_SEQ=chip_sw_gpio_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 1.chip_sw_gpio.281634324 |
| Directory | /workspace/1.chip_sw_gpio/latest |
| Test location | /workspace/coverage/default/1.chip_sw_gpio_smoketest.3750363286 |
| Short name | T1087 |
| Test name | |
| Test status | |
| Simulation time | 3752176369 ps |
| CPU time | 271.9 seconds |
| Started | Aug 12 07:22:22 PM PDT 24 |
| Finished | Aug 12 07:26:54 PM PDT 24 |
| Peak memory | 610364 kb |
| Host | smart-a2692ea7-01e3-4763-be24-9f6c533df20e |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=gpio_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3750363286 -assert nopostproc +UVM_TESTNAME=chi p_base_test +UVM_TEST_SEQ=chip_sw_gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 1.chip_sw_gpio_smoketest.3750363286 |
| Directory | /workspace/1.chip_sw_gpio_smoketest/latest |
| Test location | /workspace/coverage/default/1.chip_sw_hmac_enc.2860373019 |
| Short name | T379 |
| Test name | |
| Test status | |
| Simulation time | 3682624660 ps |
| CPU time | 363.47 seconds |
| Started | Aug 12 07:15:25 PM PDT 24 |
| Finished | Aug 12 07:21:29 PM PDT 24 |
| Peak memory | 609760 kb |
| Host | smart-3fc44709-9c14-4b9b-bfe1-efa272c41fc2 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=hmac_enc_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2860373019 -assert nopostproc +UVM_TESTNAME=chip _base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_hmac_enc.2860373019 |
| Directory | /workspace/1.chip_sw_hmac_enc/latest |
| Test location | /workspace/coverage/default/1.chip_sw_hmac_enc_idle.1933378828 |
| Short name | T1004 |
| Test name | |
| Test status | |
| Simulation time | 2721239480 ps |
| CPU time | 212.79 seconds |
| Started | Aug 12 07:18:25 PM PDT 24 |
| Finished | Aug 12 07:21:58 PM PDT 24 |
| Peak memory | 608680 kb |
| Host | smart-eae78e30-512e-4590-9e77-c9f5b8258c04 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=hmac_enc_idle_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1933378828 -assert nopostproc +UVM_TESTNAME =chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 1.chip_sw_hmac_enc_idle.1933378828 |
| Directory | /workspace/1.chip_sw_hmac_enc_idle/latest |
| Test location | /workspace/coverage/default/1.chip_sw_hmac_enc_jitter_en.1224537145 |
| Short name | T1163 |
| Test name | |
| Test status | |
| Simulation time | 2833244237 ps |
| CPU time | 313.78 seconds |
| Started | Aug 12 07:18:51 PM PDT 24 |
| Finished | Aug 12 07:24:05 PM PDT 24 |
| Peak memory | 609940 kb |
| Host | smart-4eaba4dc-bbf5-4f34-971f-0cfec525a410 |
| User | root |
| Command | /workspace/default/simv +en_jitter=1 +sw_build_device=sim_dv +sw_images=hmac_enc_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1224537145 -assert nopostproc +UVM_ TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_ log /dev/null -cm_name 1.chip_sw_hmac_enc_jitter_en.1224537145 |
| Directory | /workspace/1.chip_sw_hmac_enc_jitter_en/latest |
| Test location | /workspace/coverage/default/1.chip_sw_hmac_enc_jitter_en_reduced_freq.319245894 |
| Short name | T355 |
| Test name | |
| Test status | |
| Simulation time | 2870871586 ps |
| CPU time | 349.69 seconds |
| Started | Aug 12 07:20:43 PM PDT 24 |
| Finished | Aug 12 07:26:33 PM PDT 24 |
| Peak memory | 609028 kb |
| Host | smart-12835a7e-c87e-4614-bb34-1d5926e8d2ac |
| User | root |
| Command | /workspace/default/simv +en_jitter=1 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=hmac_enc_test:1:new_rules,test_rom:0 +cdc_instrumentation _enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=319245894 -ass ert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_hmac_enc_jitter_en_reduced_freq.319245894 |
| Directory | /workspace/1.chip_sw_hmac_enc_jitter_en_reduced_freq/latest |
| Test location | /workspace/coverage/default/1.chip_sw_hmac_multistream.507636728 |
| Short name | T1300 |
| Test name | |
| Test status | |
| Simulation time | 7437458104 ps |
| CPU time | 1782.81 seconds |
| Started | Aug 12 07:17:48 PM PDT 24 |
| Finished | Aug 12 07:47:31 PM PDT 24 |
| Peak memory | 610588 kb |
| Host | smart-6379e812-8d6c-4872-a397-5210c523630a |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=hmac_multistream_functest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=507636728 -assert nopostproc +UVM_TE STNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_lo g /dev/null -cm_name 1.chip_sw_hmac_multistream.507636728 |
| Directory | /workspace/1.chip_sw_hmac_multistream/latest |
| Test location | /workspace/coverage/default/1.chip_sw_hmac_oneshot.3932098472 |
| Short name | T1264 |
| Test name | |
| Test status | |
| Simulation time | 2935145046 ps |
| CPU time | 312.43 seconds |
| Started | Aug 12 07:18:39 PM PDT 24 |
| Finished | Aug 12 07:23:51 PM PDT 24 |
| Peak memory | 610268 kb |
| Host | smart-3815e509-f431-4d35-94b3-0766be005bd8 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=hmac_functest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3932098472 -assert nopostproc +UVM_TESTNAME=chip _base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_hmac_oneshot.3932098472 |
| Directory | /workspace/1.chip_sw_hmac_oneshot/latest |
| Test location | /workspace/coverage/default/1.chip_sw_hmac_smoketest.422590600 |
| Short name | T1046 |
| Test name | |
| Test status | |
| Simulation time | 3624021016 ps |
| CPU time | 365.51 seconds |
| Started | Aug 12 07:22:06 PM PDT 24 |
| Finished | Aug 12 07:28:12 PM PDT 24 |
| Peak memory | 609904 kb |
| Host | smart-10d25f7c-b7f3-40ed-82e1-4eb73fa76708 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=hmac_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=422590600 -assert nopostproc +UVM_TESTNAME=chip _base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_hmac_smoketest.422590600 |
| Directory | /workspace/1.chip_sw_hmac_smoketest/latest |
| Test location | /workspace/coverage/default/1.chip_sw_i2c_device_tx_rx.3418849864 |
| Short name | T110 |
| Test name | |
| Test status | |
| Simulation time | 3391615008 ps |
| CPU time | 472.71 seconds |
| Started | Aug 12 07:16:18 PM PDT 24 |
| Finished | Aug 12 07:24:12 PM PDT 24 |
| Peak memory | 610180 kb |
| Host | smart-06a3016f-d2c9-46b5-8553-bed055d8ee52 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=i2c_device_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3418849864 -assert nopostproc +UVM_TESTN AME=chip_base_test +UVM_TEST_SEQ=chip_sw_i2c_device_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v db -cm_log /dev/null -cm_name 1.chip_sw_i2c_device_tx_rx.3418849864 |
| Directory | /workspace/1.chip_sw_i2c_device_tx_rx/latest |
| Test location | /workspace/coverage/default/1.chip_sw_i2c_host_tx_rx.2242070072 |
| Short name | T1407 |
| Test name | |
| Test status | |
| Simulation time | 4942887094 ps |
| CPU time | 938.29 seconds |
| Started | Aug 12 07:13:54 PM PDT 24 |
| Finished | Aug 12 07:29:33 PM PDT 24 |
| Peak memory | 609880 kb |
| Host | smart-f840b9e9-7798-4869-a685-6b6f2dde9378 |
| User | root |
| Command | /workspace/default/simv +i2c_idx=0 +sw_build_device=sim_dv +sw_images=i2c_host_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2242070072 -assert nopostproc + UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_i2c_host_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de fault.vdb -cm_log /dev/null -cm_name 1.chip_sw_i2c_host_tx_rx.2242070072 |
| Directory | /workspace/1.chip_sw_i2c_host_tx_rx/latest |
| Test location | /workspace/coverage/default/1.chip_sw_i2c_host_tx_rx_idx1.1160818747 |
| Short name | T334 |
| Test name | |
| Test status | |
| Simulation time | 5692075288 ps |
| CPU time | 928.29 seconds |
| Started | Aug 12 07:17:13 PM PDT 24 |
| Finished | Aug 12 07:32:42 PM PDT 24 |
| Peak memory | 609860 kb |
| Host | smart-0f3c4363-8dea-43d4-b0bb-53a2d6d89b7a |
| User | root |
| Command | /workspace/default/simv +i2c_idx=1 +sw_build_device=sim_dv +sw_images=i2c_host_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1160818747 -assert nopostproc + UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_i2c_host_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de fault.vdb -cm_log /dev/null -cm_name 1.chip_sw_i2c_host_tx_rx_idx1.1160818747 |
| Directory | /workspace/1.chip_sw_i2c_host_tx_rx_idx1/latest |
| Test location | /workspace/coverage/default/1.chip_sw_i2c_host_tx_rx_idx2.2488336853 |
| Short name | T344 |
| Test name | |
| Test status | |
| Simulation time | 4869333792 ps |
| CPU time | 747.14 seconds |
| Started | Aug 12 07:12:50 PM PDT 24 |
| Finished | Aug 12 07:25:18 PM PDT 24 |
| Peak memory | 609884 kb |
| Host | smart-36b5ab94-8375-43d9-b41e-7869966b88f3 |
| User | root |
| Command | /workspace/default/simv +i2c_idx=2 +sw_build_device=sim_dv +sw_images=i2c_host_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2488336853 -assert nopostproc + UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_i2c_host_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de fault.vdb -cm_log /dev/null -cm_name 1.chip_sw_i2c_host_tx_rx_idx2.2488336853 |
| Directory | /workspace/1.chip_sw_i2c_host_tx_rx_idx2/latest |
| Test location | /workspace/coverage/default/1.chip_sw_inject_scramble_seed.3432844813 |
| Short name | T1320 |
| Test name | |
| Test status | |
| Simulation time | 64579908355 ps |
| CPU time | 10565.8 seconds |
| Started | Aug 12 07:15:56 PM PDT 24 |
| Finished | Aug 12 10:12:03 PM PDT 24 |
| Peak memory | 625204 kb |
| Host | smart-d7ac4043-0a14-45ff-9c8f-44fcd7b3c336 |
| User | root |
| Command | /workspace/default/simv +lc_at_prod=1 +flash_program_latency=5 +sw_test_timeout_ns=150_000_000 +sw_build_device=sim_dv +sw_images=inject_scramble_seed :1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=3432844813 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_inject_scramble_seed_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_inject_scramble_seed.3432844813 |
| Directory | /workspace/1.chip_sw_inject_scramble_seed/latest |
| Test location | /workspace/coverage/default/1.chip_sw_keymgr_key_derivation.1808958777 |
| Short name | T313 |
| Test name | |
| Test status | |
| Simulation time | 8085509640 ps |
| CPU time | 1168.52 seconds |
| Started | Aug 12 07:15:37 PM PDT 24 |
| Finished | Aug 12 07:35:06 PM PDT 24 |
| Peak memory | 617352 kb |
| Host | smart-6cfd92df-f6d2-405a-b84b-d7d8786dceb3 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=20_000_000 +sw_build_device=sim_dv +sw_images=keymgr_key_derivation_test:1:new_rules,test_rom:0 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1808 958777 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_keymgr_key_derivation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_keymgr_key_derivation.1808958777 |
| Directory | /workspace/1.chip_sw_keymgr_key_derivation/latest |
| Test location | /workspace/coverage/default/1.chip_sw_keymgr_key_derivation_jitter_en.3827079192 |
| Short name | T123 |
| Test name | |
| Test status | |
| Simulation time | 8081958725 ps |
| CPU time | 1166.54 seconds |
| Started | Aug 12 07:16:12 PM PDT 24 |
| Finished | Aug 12 07:35:38 PM PDT 24 |
| Peak memory | 617080 kb |
| Host | smart-d84b24d3-8ff8-4202-8380-8534172edc7e |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=20_000_000 +en_jitter=1 +sw_build_device=sim_dv +sw_images=keymgr_key_derivation_test:1:new_rules,test_rom :0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=3827079192 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_keymgr_key_derivation_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_keymgr_key_derivation_jitter_en.3827079192 |
| Directory | /workspace/1.chip_sw_keymgr_key_derivation_jitter_en/latest |
| Test location | /workspace/coverage/default/1.chip_sw_keymgr_key_derivation_prod.3020428175 |
| Short name | T226 |
| Test name | |
| Test status | |
| Simulation time | 7116143380 ps |
| CPU time | 1413.46 seconds |
| Started | Aug 12 07:17:57 PM PDT 24 |
| Finished | Aug 12 07:41:31 PM PDT 24 |
| Peak memory | 618668 kb |
| Host | smart-5c462a65-e298-4507-a198-34efe427a7e0 |
| User | root |
| Command | /workspace/default/simv +lc_at_prod=1 +sw_test_timeout_ns=20_000_000 +sw_build_device=sim_dv +sw_images=keymgr_key_derivation_test:1:new_rules,test_ro m:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=3020428175 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_keymgr_key_derivation_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_keymgr_key_derivation_prod.3020428175 |
| Directory | /workspace/1.chip_sw_keymgr_key_derivation_prod/latest |
| Test location | /workspace/coverage/default/1.chip_sw_keymgr_sideload_aes.830917036 |
| Short name | T231 |
| Test name | |
| Test status | |
| Simulation time | 10083829462 ps |
| CPU time | 2287.95 seconds |
| Started | Aug 12 07:16:50 PM PDT 24 |
| Finished | Aug 12 07:54:59 PM PDT 24 |
| Peak memory | 610520 kb |
| Host | smart-786f33b5-057a-4686-b354-385b54330ba3 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=20_000_000 +sw_build_device=sim_dv +sw_images=keymgr_sideload_aes_test:1:new_rules,test_rom:0 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=830917 036 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_keymgr_sideload_aes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_keymgr_sideload_aes.830917036 |
| Directory | /workspace/1.chip_sw_keymgr_sideload_aes/latest |
| Test location | /workspace/coverage/default/1.chip_sw_keymgr_sideload_kmac.1028261549 |
| Short name | T228 |
| Test name | |
| Test status | |
| Simulation time | 7800113468 ps |
| CPU time | 1518.72 seconds |
| Started | Aug 12 07:18:10 PM PDT 24 |
| Finished | Aug 12 07:43:30 PM PDT 24 |
| Peak memory | 610300 kb |
| Host | smart-1c2dad57-0828-4156-bf73-2d789d833524 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=20_000_000 +sw_build_device=sim_dv +sw_images=keymgr_sideload_kmac_test:1:new_rules,test_rom:0 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10282 61549 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_keymgr_sideload_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_keymgr_sideload_kmac.1028261549 |
| Directory | /workspace/1.chip_sw_keymgr_sideload_kmac/latest |
| Test location | /workspace/coverage/default/1.chip_sw_keymgr_sideload_otbn.1450668700 |
| Short name | T233 |
| Test name | |
| Test status | |
| Simulation time | 15414083200 ps |
| CPU time | 3428.71 seconds |
| Started | Aug 12 07:18:54 PM PDT 24 |
| Finished | Aug 12 08:16:03 PM PDT 24 |
| Peak memory | 611348 kb |
| Host | smart-d2e51d32-7e7a-4318-92d8-23014318a065 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=20_000_000 +sw_build_device=sim_dv +sw_images=keymgr_sideload_otbn_test:1:new_rules,test_rom:0 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14506 68700 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_keymgr_sideload_otbn.1450668700 |
| Directory | /workspace/1.chip_sw_keymgr_sideload_otbn/latest |
| Test location | /workspace/coverage/default/1.chip_sw_kmac_app_rom.4256410547 |
| Short name | T410 |
| Test name | |
| Test status | |
| Simulation time | 2556995000 ps |
| CPU time | 190.88 seconds |
| Started | Aug 12 07:17:05 PM PDT 24 |
| Finished | Aug 12 07:20:17 PM PDT 24 |
| Peak memory | 609976 kb |
| Host | smart-8ad33d70-b8c0-4d69-bcbf-4a24e1096df6 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=kmac_app_rom_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4256410547 -assert nopostproc +UVM_TESTNAME= chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/ null -cm_name 1.chip_sw_kmac_app_rom.4256410547 |
| Directory | /workspace/1.chip_sw_kmac_app_rom/latest |
| Test location | /workspace/coverage/default/1.chip_sw_kmac_entropy.288552494 |
| Short name | T1028 |
| Test name | |
| Test status | |
| Simulation time | 2947431800 ps |
| CPU time | 260.87 seconds |
| Started | Aug 12 07:14:55 PM PDT 24 |
| Finished | Aug 12 07:19:16 PM PDT 24 |
| Peak memory | 610160 kb |
| Host | smart-6a2c98be-2220-476b-ab0b-4f5e4590c737 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=kmac_entropy_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=288552494 -assert nopostproc +UVM_TESTNAME=c hip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n ull -cm_name 1.chip_sw_kmac_entropy.288552494 |
| Directory | /workspace/1.chip_sw_kmac_entropy/latest |
| Test location | /workspace/coverage/default/1.chip_sw_kmac_idle.2498738666 |
| Short name | T286 |
| Test name | |
| Test status | |
| Simulation time | 3140148840 ps |
| CPU time | 207.74 seconds |
| Started | Aug 12 07:17:22 PM PDT 24 |
| Finished | Aug 12 07:20:50 PM PDT 24 |
| Peak memory | 609972 kb |
| Host | smart-22fa8ba2-68db-4b24-bff9-855b0f101f11 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=kmac_idle_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2498738666 -assert nopostproc +UVM_TESTNAME=chi p_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul l -cm_name 1.chip_sw_kmac_idle.2498738666 |
| Directory | /workspace/1.chip_sw_kmac_idle/latest |
| Test location | /workspace/coverage/default/1.chip_sw_kmac_mode_cshake.729562282 |
| Short name | T1334 |
| Test name | |
| Test status | |
| Simulation time | 2823196104 ps |
| CPU time | 264.35 seconds |
| Started | Aug 12 07:16:44 PM PDT 24 |
| Finished | Aug 12 07:21:08 PM PDT 24 |
| Peak memory | 610176 kb |
| Host | smart-6d66b2e7-b12c-4618-b24e-f9ae455bbdb5 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=kmac_mode_cshake_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=729562282 -assert nopostproc +UVM_TESTNA ME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 1.chip_sw_kmac_mode_cshake.729562282 |
| Directory | /workspace/1.chip_sw_kmac_mode_cshake/latest |
| Test location | /workspace/coverage/default/1.chip_sw_kmac_mode_kmac.3116635317 |
| Short name | T1165 |
| Test name | |
| Test status | |
| Simulation time | 2501597180 ps |
| CPU time | 319.59 seconds |
| Started | Aug 12 07:17:49 PM PDT 24 |
| Finished | Aug 12 07:23:08 PM PDT 24 |
| Peak memory | 609932 kb |
| Host | smart-3273c1e9-511b-4030-a84a-4fa6ffdc7287 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=kmac_mode_kmac_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3116635317 -assert nopostproc +UVM_TESTNAM E=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 1.chip_sw_kmac_mode_kmac.3116635317 |
| Directory | /workspace/1.chip_sw_kmac_mode_kmac/latest |
| Test location | /workspace/coverage/default/1.chip_sw_kmac_mode_kmac_jitter_en.3512695069 |
| Short name | T1389 |
| Test name | |
| Test status | |
| Simulation time | 3386858981 ps |
| CPU time | 313.18 seconds |
| Started | Aug 12 07:20:47 PM PDT 24 |
| Finished | Aug 12 07:26:01 PM PDT 24 |
| Peak memory | 610116 kb |
| Host | smart-3a4bbd6b-3155-42f7-a904-3ebd54a18a4c |
| User | root |
| Command | /workspace/default/simv +en_jitter=1 +sw_build_device=sim_dv +sw_images=kmac_mode_kmac_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3512695069 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd b -cm_log /dev/null -cm_name 1.chip_sw_kmac_mode_kmac_jitter_en.3512695069 |
| Directory | /workspace/1.chip_sw_kmac_mode_kmac_jitter_en/latest |
| Test location | /workspace/coverage/default/1.chip_sw_kmac_mode_kmac_jitter_en_reduced_freq.434507338 |
| Short name | T458 |
| Test name | |
| Test status | |
| Simulation time | 2929972633 ps |
| CPU time | 238.4 seconds |
| Started | Aug 12 07:20:41 PM PDT 24 |
| Finished | Aug 12 07:24:40 PM PDT 24 |
| Peak memory | 610176 kb |
| Host | smart-2ee2b64f-1128-45a9-a81b-08b236946a8e |
| User | root |
| Command | /workspace/default/simv +en_jitter=1 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=kmac_mode_kmac_test:1:new_rules,test_rom:0 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=43450733 8 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace /coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_kmac_mode_kmac_jitter_en_reduced_freq.434507338 |
| Directory | /workspace/1.chip_sw_kmac_mode_kmac_jitter_en_reduced_freq/latest |
| Test location | /workspace/coverage/default/1.chip_sw_kmac_smoketest.1322723201 |
| Short name | T1390 |
| Test name | |
| Test status | |
| Simulation time | 2376572448 ps |
| CPU time | 349.61 seconds |
| Started | Aug 12 07:23:14 PM PDT 24 |
| Finished | Aug 12 07:29:04 PM PDT 24 |
| Peak memory | 609736 kb |
| Host | smart-441631d1-1220-4ae9-b95e-42581b13caaf |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=kmac_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1322723201 -assert nopostproc +UVM_TESTNAME=chi p_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul l -cm_name 1.chip_sw_kmac_smoketest.1322723201 |
| Directory | /workspace/1.chip_sw_kmac_smoketest/latest |
| Test location | /workspace/coverage/default/1.chip_sw_lc_ctrl_otp_hw_cfg0.2411517993 |
| Short name | T975 |
| Test name | |
| Test status | |
| Simulation time | 2773648840 ps |
| CPU time | 294.34 seconds |
| Started | Aug 12 07:12:33 PM PDT 24 |
| Finished | Aug 12 07:17:28 PM PDT 24 |
| Peak memory | 609804 kb |
| Host | smart-6cfd93fc-1572-4262-bb4f-0ad348d18ad9 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=lc_ctrl_otp_hw_cfg0_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2411517993 -assert nopostproc +UVM_TE STNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_lo g /dev/null -cm_name 1.chip_sw_lc_ctrl_otp_hw_cfg0.2411517993 |
| Directory | /workspace/1.chip_sw_lc_ctrl_otp_hw_cfg0/latest |
| Test location | /workspace/coverage/default/1.chip_sw_lc_ctrl_program_error.1321739935 |
| Short name | T180 |
| Test name | |
| Test status | |
| Simulation time | 4333465032 ps |
| CPU time | 618.87 seconds |
| Started | Aug 12 07:23:32 PM PDT 24 |
| Finished | Aug 12 07:33:52 PM PDT 24 |
| Peak memory | 611464 kb |
| Host | smart-b83be33d-d9af-4b44-87b1-36bc65acc393 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=lc_ctrl_program_error:1:new_rules,test_rom:0 + cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_ seed=1321739935 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_program_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_lc_ctrl_program_error.1321739935 |
| Directory | /workspace/1.chip_sw_lc_ctrl_program_error/latest |
| Test location | /workspace/coverage/default/1.chip_sw_lc_ctrl_rand_to_scrap.3743514098 |
| Short name | T755 |
| Test name | |
| Test status | |
| Simulation time | 4110391905 ps |
| CPU time | 160.36 seconds |
| Started | Aug 12 07:15:04 PM PDT 24 |
| Finished | Aug 12 07:17:44 PM PDT 24 |
| Peak memory | 620392 kb |
| Host | smart-c527e16b-1589-4143-a690-4d33d47d89a9 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=lc_ctrl_scrap_test:1:new_rules,test_rom:0 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37435140 98 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_scrap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_lc_ctrl_rand_to_scrap.3743514098 |
| Directory | /workspace/1.chip_sw_lc_ctrl_rand_to_scrap/latest |
| Test location | /workspace/coverage/default/1.chip_sw_lc_ctrl_transition.2776616678 |
| Short name | T125 |
| Test name | |
| Test status | |
| Simulation time | 6581982210 ps |
| CPU time | 616.95 seconds |
| Started | Aug 12 07:12:06 PM PDT 24 |
| Finished | Aug 12 07:22:23 PM PDT 24 |
| Peak memory | 622856 kb |
| Host | smart-e0916db5-ff95-4d5e-907d-5c239a7d7bd0 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=lc_ctrl_transition_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2776616678 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_transition_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau lt.vdb -cm_log /dev/null -cm_name 1.chip_sw_lc_ctrl_transition.2776616678 |
| Directory | /workspace/1.chip_sw_lc_ctrl_transition/latest |
| Test location | /workspace/coverage/default/1.chip_sw_lc_ctrl_volatile_raw_unlock.61223212 |
| Short name | T758 |
| Test name | |
| Test status | |
| Simulation time | 2818264847 ps |
| CPU time | 106.16 seconds |
| Started | Aug 12 07:13:43 PM PDT 24 |
| Finished | Aug 12 07:15:30 PM PDT 24 |
| Peak memory | 618288 kb |
| Host | smart-fdba95b8-2e41-428f-b6f2-2a07fa675405 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStRaw +exp_volatile_raw_unlock_en=0 +sw_build_device=sim_dv +sw_images=lc_ctrl_volatile_raw_unlock_tes t:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/ tools/sim.tcl +ntb_random_seed=61223212 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_volatile_raw_unlock_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_lc_ctrl_volatile_raw_unlock.61223212 |
| Directory | /workspace/1.chip_sw_lc_ctrl_volatile_raw_unlock/latest |
| Test location | /workspace/coverage/default/1.chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz.1319314502 |
| Short name | T1307 |
| Test name | |
| Test status | |
| Simulation time | 2222850455 ps |
| CPU time | 110.1 seconds |
| Started | Aug 12 07:14:48 PM PDT 24 |
| Finished | Aug 12 07:16:38 PM PDT 24 |
| Peak memory | 617960 kb |
| Host | smart-5dda4462-9c2d-4242-84f0-d3f503c856db |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStRaw +chip_clock_source=ChipClockSourceExternal48Mhz +exp_volatile_raw_unlock_en=0 +sw_build_device=s im_dv +sw_images=lc_ctrl_volatile_raw_unlock_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1319314502 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TES T_SEQ=chip_sw_lc_volatile_raw_unlock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz.1319314502 |
| Directory | /workspace/1.chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz/latest |
| Test location | /workspace/coverage/default/1.chip_sw_lc_walkthrough_dev.3730612838 |
| Short name | T1427 |
| Test name | |
| Test status | |
| Simulation time | 51080869773 ps |
| CPU time | 5173.61 seconds |
| Started | Aug 12 07:14:20 PM PDT 24 |
| Finished | Aug 12 08:40:35 PM PDT 24 |
| Peak memory | 620776 kb |
| Host | smart-5a9eecbe-6029-40a0-b6fc-121b7ac17992 |
| User | root |
| Command | /workspace/default/simv +flash_program_latency=5 +use_otp_image=OtpTypeLcStRaw +dest_dec_state=DecLcStDev +sw_test_timeout_ns=200_000_000 +sw_build_de vice=sim_dv +sw_images=lc_walkthrough_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3730612838 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=c hip_sw_lc_walkthrough_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip _sw_lc_walkthrough_dev.3730612838 |
| Directory | /workspace/1.chip_sw_lc_walkthrough_dev/latest |
| Test location | /workspace/coverage/default/1.chip_sw_lc_walkthrough_prod.1603514499 |
| Short name | T1268 |
| Test name | |
| Test status | |
| Simulation time | 50778284388 ps |
| CPU time | 5474.5 seconds |
| Started | Aug 12 07:11:48 PM PDT 24 |
| Finished | Aug 12 08:43:03 PM PDT 24 |
| Peak memory | 621372 kb |
| Host | smart-177b8012-f2d1-4f5b-889e-9f13006d0e6e |
| User | root |
| Command | /workspace/default/simv +flash_program_latency=5 +use_otp_image=OtpTypeLcStRaw +dest_dec_state=DecLcStProd +sw_test_timeout_ns=200_000_000 +sw_build_d evice=sim_dv +sw_images=lc_walkthrough_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1603514499 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ= chip_sw_lc_walkthrough_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chi p_sw_lc_walkthrough_prod.1603514499 |
| Directory | /workspace/1.chip_sw_lc_walkthrough_prod/latest |
| Test location | /workspace/coverage/default/1.chip_sw_lc_walkthrough_prodend.2538929957 |
| Short name | T1048 |
| Test name | |
| Test status | |
| Simulation time | 7988880030 ps |
| CPU time | 850.6 seconds |
| Started | Aug 12 07:12:37 PM PDT 24 |
| Finished | Aug 12 07:26:48 PM PDT 24 |
| Peak memory | 620596 kb |
| Host | smart-0afc14c3-d10a-4dc9-9cb5-9c5fb5c3d743 |
| User | root |
| Command | /workspace/default/simv +flash_program_latency=5 +use_otp_image=OtpTypeLcStRaw +dest_dec_state=DecLcStProdEnd +sw_build_device=sim_dv +sw_images=lc_wa lkthrough_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2538929957 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_walkthrough_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_lc_walkthrough_prodend.2538929957 |
| Directory | /workspace/1.chip_sw_lc_walkthrough_prodend/latest |
| Test location | /workspace/coverage/default/1.chip_sw_lc_walkthrough_rma.2040725670 |
| Short name | T242 |
| Test name | |
| Test status | |
| Simulation time | 49472063020 ps |
| CPU time | 5537.33 seconds |
| Started | Aug 12 07:12:21 PM PDT 24 |
| Finished | Aug 12 08:44:39 PM PDT 24 |
| Peak memory | 619712 kb |
| Host | smart-4b2f7a91-da6e-4201-b02f-831258c13540 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStRaw +dest_dec_state=DecLcStRma +flash_program_latency=5 +sw_test_timeout_ns=200_000_000 +sw_build_de vice=sim_dv +sw_images=lc_walkthrough_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2040725670 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=c hip_sw_lc_walkthrough_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip _sw_lc_walkthrough_rma.2040725670 |
| Directory | /workspace/1.chip_sw_lc_walkthrough_rma/latest |
| Test location | /workspace/coverage/default/1.chip_sw_lc_walkthrough_testunlocks.2524304174 |
| Short name | T183 |
| Test name | |
| Test status | |
| Simulation time | 25964250970 ps |
| CPU time | 1951 seconds |
| Started | Aug 12 07:12:57 PM PDT 24 |
| Finished | Aug 12 07:45:28 PM PDT 24 |
| Peak memory | 621308 kb |
| Host | smart-902aa0be-fe02-49bc-8bd4-e25c769967a6 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStRaw +dest_dec_state=DecLcStTestUnlock7 +sw_build_device=sim_dv +sw_images=lc_walkthrough_testunlocks _test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=2524304174 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_walkthrough_testunlocks_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_lc_walkthrough_testun locks.2524304174 |
| Directory | /workspace/1.chip_sw_lc_walkthrough_testunlocks/latest |
| Test location | /workspace/coverage/default/1.chip_sw_otbn_ecdsa_op_irq.774027492 |
| Short name | T1103 |
| Test name | |
| Test status | |
| Simulation time | 16971551682 ps |
| CPU time | 3820.09 seconds |
| Started | Aug 12 07:16:19 PM PDT 24 |
| Finished | Aug 12 08:20:00 PM PDT 24 |
| Peak memory | 610748 kb |
| Host | smart-206406b4-02ab-42c0-b688-8af8d8522a00 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=28_000_000 +rng_srate_value=30 +sw_build_device=sim_dv +sw_images=otbn_ecdsa_op_irq_test:1:new_rules,test_ rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ random_seed=774027492 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_otbn_ecdsa_op_irq.774027492 |
| Directory | /workspace/1.chip_sw_otbn_ecdsa_op_irq/latest |
| Test location | /workspace/coverage/default/1.chip_sw_otbn_ecdsa_op_irq_jitter_en.349663894 |
| Short name | T163 |
| Test name | |
| Test status | |
| Simulation time | 18887039984 ps |
| CPU time | 3691.17 seconds |
| Started | Aug 12 07:14:30 PM PDT 24 |
| Finished | Aug 12 08:16:01 PM PDT 24 |
| Peak memory | 610804 kb |
| Host | smart-1bfa5517-6ffa-4cf2-b164-f7ef2582580c |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=33_000_000 +rng_srate_value=30 +en_jitter=1 +sw_build_device=sim_dv +sw_images=otbn_ecdsa_op_irq_test:1:ne w_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/ sim.tcl +ntb_random_seed=349663894 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_otbn_ecdsa_op_irq_jitter_en.349663894 |
| Directory | /workspace/1.chip_sw_otbn_ecdsa_op_irq_jitter_en/latest |
| Test location | /workspace/coverage/default/1.chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq.426065184 |
| Short name | T1128 |
| Test name | |
| Test status | |
| Simulation time | 24799304421 ps |
| CPU time | 3806.7 seconds |
| Started | Aug 12 07:21:23 PM PDT 24 |
| Finished | Aug 12 08:24:50 PM PDT 24 |
| Peak memory | 610444 kb |
| Host | smart-00e97323-aa53-4e1a-aef4-4a3f12a4aca8 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=33_000_000 +rng_srate_value=30 +en_jitter=1 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=otbn_e cdsa_op_irq_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/ repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=426065184 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_otbn_ecdsa_op_irq_jitter_en_reduc ed_freq.426065184 |
| Directory | /workspace/1.chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq/latest |
| Test location | /workspace/coverage/default/1.chip_sw_otbn_mem_scramble.74403347 |
| Short name | T292 |
| Test name | |
| Test status | |
| Simulation time | 3858862060 ps |
| CPU time | 489.57 seconds |
| Started | Aug 12 07:17:27 PM PDT 24 |
| Finished | Aug 12 07:25:37 PM PDT 24 |
| Peak memory | 610100 kb |
| Host | smart-7953b5fc-cfb2-4761-bb62-4b61326833fe |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=15_000_000 +en_scb_tl_err_chk=0 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=otbn _mem_scramble_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=74403347 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_otbn_mem_scramble.74403347 |
| Directory | /workspace/1.chip_sw_otbn_mem_scramble/latest |
| Test location | /workspace/coverage/default/1.chip_sw_otbn_randomness.1405131709 |
| Short name | T136 |
| Test name | |
| Test status | |
| Simulation time | 5955286584 ps |
| CPU time | 1208.68 seconds |
| Started | Aug 12 07:14:16 PM PDT 24 |
| Finished | Aug 12 07:34:25 PM PDT 24 |
| Peak memory | 610492 kb |
| Host | smart-bef081af-6aa2-471c-86fd-93ec4c67179e |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +rng_srate_value=30 +sw_build_device=sim_dv +sw_images=otbn_randomness_test:1:new_rules,test_ro m:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=1405131709 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_otbn_randomness.1405131709 |
| Directory | /workspace/1.chip_sw_otbn_randomness/latest |
| Test location | /workspace/coverage/default/1.chip_sw_otbn_smoketest.1145763333 |
| Short name | T1118 |
| Test name | |
| Test status | |
| Simulation time | 9768018232 ps |
| CPU time | 2171.25 seconds |
| Started | Aug 12 07:21:43 PM PDT 24 |
| Finished | Aug 12 07:57:55 PM PDT 24 |
| Peak memory | 610456 kb |
| Host | smart-10eb455b-3485-4e77-bfe1-7aac495931b1 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=otbn_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1145763333 -assert nopostproc +UVM_TESTNAME=chi p_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul l -cm_name 1.chip_sw_otbn_smoketest.1145763333 |
| Directory | /workspace/1.chip_sw_otbn_smoketest/latest |
| Test location | /workspace/coverage/default/1.chip_sw_otp_ctrl_ecc_error_vendor_test.2800194275 |
| Short name | T1152 |
| Test name | |
| Test status | |
| Simulation time | 2514499732 ps |
| CPU time | 271.96 seconds |
| Started | Aug 12 07:14:13 PM PDT 24 |
| Finished | Aug 12 07:18:45 PM PDT 24 |
| Peak memory | 609192 kb |
| Host | smart-3b5f6a56-96bf-4ef4-88e5-02cd39052b2e |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=otp_ctrl_vendor_test_ecc_error_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2800194275 -assert nopostp roc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_otp_ctrl_vendor_test_ecc_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_otp_ctrl_ecc_error_vendor_test.2800194275 |
| Directory | /workspace/1.chip_sw_otp_ctrl_ecc_error_vendor_test/latest |
| Test location | /workspace/coverage/default/1.chip_sw_otp_ctrl_lc_signals_dev.382316737 |
| Short name | T1271 |
| Test name | |
| Test status | |
| Simulation time | 8330810350 ps |
| CPU time | 1290.4 seconds |
| Started | Aug 12 07:14:52 PM PDT 24 |
| Finished | Aug 12 07:36:23 PM PDT 24 |
| Peak memory | 611204 kb |
| Host | smart-608ae2f2-0b2e-47d9-aad9-0a6f3e61cb89 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStDev +otp_clear_secret2=1 +sw_build_device=sim_dv +sw_images=otp_ctrl_lc_signals_test:1:new_rules,tes t_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +nt b_random_seed=382316737 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_otp_ctrl_lc_signals_dev.382316737 |
| Directory | /workspace/1.chip_sw_otp_ctrl_lc_signals_dev/latest |
| Test location | /workspace/coverage/default/1.chip_sw_otp_ctrl_lc_signals_prod.1973054821 |
| Short name | T1439 |
| Test name | |
| Test status | |
| Simulation time | 9414598270 ps |
| CPU time | 1265.73 seconds |
| Started | Aug 12 07:12:00 PM PDT 24 |
| Finished | Aug 12 07:33:06 PM PDT 24 |
| Peak memory | 610808 kb |
| Host | smart-beea9b13-4b13-4bab-a91a-46dfb354038e |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStProd +otp_clear_secret2=1 +sw_build_device=sim_dv +sw_images=otp_ctrl_lc_signals_test:1:new_rules,te st_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n tb_random_seed=1973054821 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_otp_ctrl_lc_signals_prod.1973054821 |
| Directory | /workspace/1.chip_sw_otp_ctrl_lc_signals_prod/latest |
| Test location | /workspace/coverage/default/1.chip_sw_otp_ctrl_lc_signals_rma.4087821681 |
| Short name | T229 |
| Test name | |
| Test status | |
| Simulation time | 8155877032 ps |
| CPU time | 1200.51 seconds |
| Started | Aug 12 07:16:12 PM PDT 24 |
| Finished | Aug 12 07:36:13 PM PDT 24 |
| Peak memory | 611100 kb |
| Host | smart-0206fbe2-5f35-4135-936b-db6f51d8cd73 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStRma +otp_clear_secret2=1 +sw_build_device=sim_dv +sw_images=otp_ctrl_lc_signals_test:1:new_rules,tes t_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +nt b_random_seed=4087821681 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_otp_ctrl_lc_signals_rma.4087821681 |
| Directory | /workspace/1.chip_sw_otp_ctrl_lc_signals_rma/latest |
| Test location | /workspace/coverage/default/1.chip_sw_otp_ctrl_lc_signals_test_unlocked0.125894093 |
| Short name | T1022 |
| Test name | |
| Test status | |
| Simulation time | 4367520712 ps |
| CPU time | 759.85 seconds |
| Started | Aug 12 07:15:11 PM PDT 24 |
| Finished | Aug 12 07:27:51 PM PDT 24 |
| Peak memory | 610244 kb |
| Host | smart-c900ed06-5a9e-481d-88b1-e63df7cbff59 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStTestUnlocked0 +otp_clear_secret2=1 +sw_build_device=sim_dv +sw_images=otp_ctrl_lc_signals_test:1:new _rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/s im.tcl +ntb_random_seed=125894093 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_otp_ctrl_lc_signals_test_unlocked0.125894093 |
| Directory | /workspace/1.chip_sw_otp_ctrl_lc_signals_test_unlocked0/latest |
| Test location | /workspace/coverage/default/1.chip_sw_otp_ctrl_smoketest.1069550675 |
| Short name | T1288 |
| Test name | |
| Test status | |
| Simulation time | 2455889780 ps |
| CPU time | 224.13 seconds |
| Started | Aug 12 07:22:09 PM PDT 24 |
| Finished | Aug 12 07:25:53 PM PDT 24 |
| Peak memory | 608828 kb |
| Host | smart-73d8acfa-196a-469c-801d-79541a3c8c95 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=otp_ctrl_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1069550675 -assert nopostproc +UVM_TESTNAME =chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 1.chip_sw_otp_ctrl_smoketest.1069550675 |
| Directory | /workspace/1.chip_sw_otp_ctrl_smoketest/latest |
| Test location | /workspace/coverage/default/1.chip_sw_pattgen_ios.1978143030 |
| Short name | T371 |
| Test name | |
| Test status | |
| Simulation time | 2834890656 ps |
| CPU time | 173.57 seconds |
| Started | Aug 12 07:13:31 PM PDT 24 |
| Finished | Aug 12 07:16:25 PM PDT 24 |
| Peak memory | 611344 kb |
| Host | smart-607da990-dc0d-45db-be9f-68ae530311d1 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=5_000_000 +sw_build_device=sim_dv +sw_images=pattgen_ios_test:1:new_rules,test_rom:0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1978143030 -ass ert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_patt_ios_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/c overage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_pattgen_ios.1978143030 |
| Directory | /workspace/1.chip_sw_pattgen_ios/latest |
| Test location | /workspace/coverage/default/1.chip_sw_plic_sw_irq.3025711272 |
| Short name | T769 |
| Test name | |
| Test status | |
| Simulation time | 3229794984 ps |
| CPU time | 241.42 seconds |
| Started | Aug 12 07:17:30 PM PDT 24 |
| Finished | Aug 12 07:21:32 PM PDT 24 |
| Peak memory | 609888 kb |
| Host | smart-39df7a90-463e-45c8-8e48-f50bfa673945 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=plic_sw_irq_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3025711272 -assert nopostproc +UVM_TESTNAME=c hip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n ull -cm_name 1.chip_sw_plic_sw_irq.3025711272 |
| Directory | /workspace/1.chip_sw_plic_sw_irq/latest |
| Test location | /workspace/coverage/default/1.chip_sw_power_idle_load.4279759986 |
| Short name | T1277 |
| Test name | |
| Test status | |
| Simulation time | 4508368322 ps |
| CPU time | 648.29 seconds |
| Started | Aug 12 07:21:18 PM PDT 24 |
| Finished | Aug 12 07:32:07 PM PDT 24 |
| Peak memory | 610552 kb |
| Host | smart-5cdae4b3-aa80-4368-9c4c-35cc4b575a86 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=chip_power_idle_load:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4279759986 -assert nopostproc +UVM_TESTNA ME=chip_base_test +UVM_TEST_SEQ=chip_sw_power_idle_load_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_power_idle_load.4279759986 |
| Directory | /workspace/1.chip_sw_power_idle_load/latest |
| Test location | /workspace/coverage/default/1.chip_sw_power_virus.2647493437 |
| Short name | T207 |
| Test name | |
| Test status | |
| Simulation time | 5959241992 ps |
| CPU time | 1500.53 seconds |
| Started | Aug 12 07:24:38 PM PDT 24 |
| Finished | Aug 12 07:49:39 PM PDT 24 |
| Peak memory | 625412 kb |
| Host | smart-74c91356-c218-463b-981d-83dfeebe6e1e |
| User | root |
| Command | /workspace/default/simv +rng_srate_value_min=15 +rng_srate_value_max=20 +sw_test_timeout_ns=400_000_000 +use_otp_image=OtpTypeCustom +sw_build_device= sim_dv +sw_images=power_virus_systemtest:1:new_rules,power_virus_systemtest_otp_img_rma:4,test_rom:0 +accelerate_cold_power_up_time=3 +accelerate_ regulators_power_up_time=2 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d v/tools/sim.tcl +ntb_random_seed=2647493437 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_power_virus_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_power_virus.2647493437 |
| Directory | /workspace/1.chip_sw_power_virus/latest |
| Test location | /workspace/coverage/default/1.chip_sw_pwrmgr_all_reset_reqs.3009770334 |
| Short name | T1104 |
| Test name | |
| Test status | |
| Simulation time | 12667511929 ps |
| CPU time | 1997.78 seconds |
| Started | Aug 12 07:15:19 PM PDT 24 |
| Finished | Aug 12 07:48:37 PM PDT 24 |
| Peak memory | 611892 kb |
| Host | smart-bb838fd2-80fa-44a8-8a0a-fb742ac22dd5 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=50_000_000 +sw_build_device=sim_dv +sw_images=pwrmgr_all_reset_reqs_test:1:new_rules,test_rom:0 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3009 770334 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_deep_sleep_all_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_pwrmgr_all_reset_reqs.3009770334 |
| Directory | /workspace/1.chip_sw_pwrmgr_all_reset_reqs/latest |
| Test location | /workspace/coverage/default/1.chip_sw_pwrmgr_b2b_sleep_reset_req.350462923 |
| Short name | T130 |
| Test name | |
| Test status | |
| Simulation time | 18825810818 ps |
| CPU time | 1850.07 seconds |
| Started | Aug 12 07:17:49 PM PDT 24 |
| Finished | Aug 12 07:48:40 PM PDT 24 |
| Peak memory | 611328 kb |
| Host | smart-6e05f22d-db7d-4382-8a37-e8a3f63d887e |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=35_000_000 +sw_build_device=sim_dv +sw_images=pwrmgr_b2b_sleep_reset_test:1:new_rules,test_rom:0 +cdc_inst rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=350 462923 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_repeat_reset_wkup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_pwrmgr_b2b_sleep_reset_req.350462923 |
| Directory | /workspace/1.chip_sw_pwrmgr_b2b_sleep_reset_req/latest |
| Test location | /workspace/coverage/default/1.chip_sw_pwrmgr_deep_sleep_all_reset_reqs.72157912 |
| Short name | T1042 |
| Test name | |
| Test status | |
| Simulation time | 18876127670 ps |
| CPU time | 2001.21 seconds |
| Started | Aug 12 07:16:33 PM PDT 24 |
| Finished | Aug 12 07:49:55 PM PDT 24 |
| Peak memory | 611928 kb |
| Host | smart-25457a30-6e50-431d-be30-26daeef7c334 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=50_000_000 +sw_build_device=sim_dv +sw_images=pwrmgr_deep_sleep_all_reset_reqs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=72157912 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_deep_sleep_all_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_pwrmgr_deep_sleep_all_reset_reqs.72157912 |
| Directory | /workspace/1.chip_sw_pwrmgr_deep_sleep_all_reset_reqs/latest |
| Test location | /workspace/coverage/default/1.chip_sw_pwrmgr_deep_sleep_por_reset.2166860071 |
| Short name | T107 |
| Test name | |
| Test status | |
| Simulation time | 8838537256 ps |
| CPU time | 718.57 seconds |
| Started | Aug 12 07:13:12 PM PDT 24 |
| Finished | Aug 12 07:25:10 PM PDT 24 |
| Peak memory | 611000 kb |
| Host | smart-9fd28b4a-4a16-4ac1-a6a2-06fe0d08acae |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_deep_sleep_por_reset_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2166860071 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sleep_por_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage /default.vdb -cm_log /dev/null -cm_name 1.chip_sw_pwrmgr_deep_sleep_por_reset.2166860071 |
| Directory | /workspace/1.chip_sw_pwrmgr_deep_sleep_por_reset/latest |
| Test location | /workspace/coverage/default/1.chip_sw_pwrmgr_deep_sleep_power_glitch_reset.1195735513 |
| Short name | T1064 |
| Test name | |
| Test status | |
| Simulation time | 7367965000 ps |
| CPU time | 563.65 seconds |
| Started | Aug 12 07:13:31 PM PDT 24 |
| Finished | Aug 12 07:22:55 PM PDT 24 |
| Peak memory | 616808 kb |
| Host | smart-34cfefc5-5b7b-4e28-bb31-ac7cfd544cdc |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=pwrmgr_deep_sleep_power_glitch_test:1:new_rules,test_rom :0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=1195735513 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_deep_power_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_pwrmgr_deep_sleep_power_glitch_reset.1195735513 |
| Directory | /workspace/1.chip_sw_pwrmgr_deep_sleep_power_glitch_reset/latest |
| Test location | /workspace/coverage/default/1.chip_sw_pwrmgr_full_aon_reset.3197868937 |
| Short name | T1 |
| Test name | |
| Test status | |
| Simulation time | 7558833600 ps |
| CPU time | 411.16 seconds |
| Started | Aug 12 07:13:32 PM PDT 24 |
| Finished | Aug 12 07:20:24 PM PDT 24 |
| Peak memory | 611008 kb |
| Host | smart-a7228d97-741b-4738-b25d-f3c8facf37ea |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=rstmgr_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3197868937 -assert nopostproc +UVM_TESTNAME=c hip_base_test +UVM_TEST_SEQ=chip_sw_full_aon_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_ log /dev/null -cm_name 1.chip_sw_pwrmgr_full_aon_reset.3197868937 |
| Directory | /workspace/1.chip_sw_pwrmgr_full_aon_reset/latest |
| Test location | /workspace/coverage/default/1.chip_sw_pwrmgr_lowpower_cancel.2714264217 |
| Short name | T350 |
| Test name | |
| Test status | |
| Simulation time | 3626230226 ps |
| CPU time | 375.13 seconds |
| Started | Aug 12 07:19:42 PM PDT 24 |
| Finished | Aug 12 07:25:57 PM PDT 24 |
| Peak memory | 610188 kb |
| Host | smart-3add5684-254a-4670-98fc-f48dbc8f2280 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_lowpower_cancel_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2714264217 -assert nopostproc +UVM _TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm _log /dev/null -cm_name 1.chip_sw_pwrmgr_lowpower_cancel.2714264217 |
| Directory | /workspace/1.chip_sw_pwrmgr_lowpower_cancel/latest |
| Test location | /workspace/coverage/default/1.chip_sw_pwrmgr_main_power_glitch_reset.4036117616 |
| Short name | T1186 |
| Test name | |
| Test status | |
| Simulation time | 3513054961 ps |
| CPU time | 281.61 seconds |
| Started | Aug 12 07:13:36 PM PDT 24 |
| Finished | Aug 12 07:18:18 PM PDT 24 |
| Peak memory | 616740 kb |
| Host | smart-6bfe66eb-d040-4949-89f9-955572606e44 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=pwrmgr_main_power_glitch_test:1:new_rules,test_rom:0 +cd c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se ed=4036117616 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_main_power_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_pwrmgr_main_power_glitch_reset.4036117616 |
| Directory | /workspace/1.chip_sw_pwrmgr_main_power_glitch_reset/latest |
| Test location | /workspace/coverage/default/1.chip_sw_pwrmgr_normal_sleep_all_reset_reqs.2292888672 |
| Short name | T1036 |
| Test name | |
| Test status | |
| Simulation time | 10125039093 ps |
| CPU time | 1484.25 seconds |
| Started | Aug 12 07:15:56 PM PDT 24 |
| Finished | Aug 12 07:40:40 PM PDT 24 |
| Peak memory | 612048 kb |
| Host | smart-aae5566c-b5d4-4700-8bfb-d6ef39367035 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_normal_sleep_all_reset_reqs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2292888672 -assert nop ostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_deep_sleep_all_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_pwrmgr_normal_sleep_all_reset_reqs.2292888672 |
| Directory | /workspace/1.chip_sw_pwrmgr_normal_sleep_all_reset_reqs/latest |
| Test location | /workspace/coverage/default/1.chip_sw_pwrmgr_normal_sleep_all_wake_ups.4141379058 |
| Short name | T18 |
| Test name | |
| Test status | |
| Simulation time | 7134833992 ps |
| CPU time | 398.12 seconds |
| Started | Aug 12 07:23:39 PM PDT 24 |
| Finished | Aug 12 07:30:17 PM PDT 24 |
| Peak memory | 610780 kb |
| Host | smart-95cfb534-08db-4cc4-9f2e-50e0fccd1021 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_normal_sleep_all_wake_ups:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4141379058 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_pwrmgr_deep_sleep_all_wake_ups_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_pwrmgr_normal_sleep_all_wake_ups.4141379058 |
| Directory | /workspace/1.chip_sw_pwrmgr_normal_sleep_all_wake_ups/latest |
| Test location | /workspace/coverage/default/1.chip_sw_pwrmgr_normal_sleep_por_reset.4081076777 |
| Short name | T973 |
| Test name | |
| Test status | |
| Simulation time | 6829440164 ps |
| CPU time | 588.67 seconds |
| Started | Aug 12 07:12:41 PM PDT 24 |
| Finished | Aug 12 07:22:30 PM PDT 24 |
| Peak memory | 611040 kb |
| Host | smart-289386b9-214f-4135-b4e5-c0aacf5f1d73 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_normal_sleep_por_reset_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4081076777 -assert nopostpr oc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sleep_por_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera ge/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_pwrmgr_normal_sleep_por_reset.4081076777 |
| Directory | /workspace/1.chip_sw_pwrmgr_normal_sleep_por_reset/latest |
| Test location | /workspace/coverage/default/1.chip_sw_pwrmgr_random_sleep_all_reset_reqs.4054487054 |
| Short name | T349 |
| Test name | |
| Test status | |
| Simulation time | 23405718571 ps |
| CPU time | 2322.41 seconds |
| Started | Aug 12 07:16:52 PM PDT 24 |
| Finished | Aug 12 07:55:35 PM PDT 24 |
| Peak memory | 612012 kb |
| Host | smart-9500e30c-c448-4094-83cd-558dc19ad470 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=50_000_000 +sw_build_device=sim_dv +sw_images=pwrmgr_random_sleep_all_reset_reqs_test:1:new_rules,test_rom :0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=4054487054 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_deep_sleep_all_reset_vseq +en_cov=1 -cm line+cond+fsm+tg l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_pwrmgr_random_sleep_all_reset_reqs.4054487054 |
| Directory | /workspace/1.chip_sw_pwrmgr_random_sleep_all_reset_reqs/latest |
| Test location | /workspace/coverage/default/1.chip_sw_pwrmgr_random_sleep_all_wake_ups.4079398132 |
| Short name | T65 |
| Test name | |
| Test status | |
| Simulation time | 25052961422 ps |
| CPU time | 1609.1 seconds |
| Started | Aug 12 07:20:34 PM PDT 24 |
| Finished | Aug 12 07:47:23 PM PDT 24 |
| Peak memory | 611200 kb |
| Host | smart-d1f029d0-2d21-4622-842e-accd105c6acb |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +do_random=1 +sw_build_device=sim_dv +sw_images=pwrmgr_random_sleep_all_wake_ups:1:new_rules,te st_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n tb_random_seed=4079398132 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_pwrmgr_deep_sleep_all_wake_ups_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_pwrmgr_random_sleep_all_wake_ups.4079398132 |
| Directory | /workspace/1.chip_sw_pwrmgr_random_sleep_all_wake_ups/latest |
| Test location | /workspace/coverage/default/1.chip_sw_pwrmgr_random_sleep_power_glitch_reset.390041061 |
| Short name | T1240 |
| Test name | |
| Test status | |
| Simulation time | 30992483789 ps |
| CPU time | 3025.03 seconds |
| Started | Aug 12 07:16:04 PM PDT 24 |
| Finished | Aug 12 08:06:30 PM PDT 24 |
| Peak memory | 612276 kb |
| Host | smart-75f210c0-b573-4591-9b5c-0270ad7edab0 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_test_timeout_ns=24_000_000 +sw_build_device=sim_dv +sw_images=pwrmgr_random_sleep_power _glitch_reset_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=390041061 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_random_power_glitc h_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_pwrmgr_random_sl eep_power_glitch_reset.390041061 |
| Directory | /workspace/1.chip_sw_pwrmgr_random_sleep_power_glitch_reset/latest |
| Test location | /workspace/coverage/default/1.chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up.3443999236 |
| Short name | T383 |
| Test name | |
| Test status | |
| Simulation time | 6426310836 ps |
| CPU time | 458.33 seconds |
| Started | Aug 12 07:19:29 PM PDT 24 |
| Finished | Aug 12 07:27:08 PM PDT 24 |
| Peak memory | 611100 kb |
| Host | smart-9a3d217f-3e60-4e6d-a428-aaff78dc5b5b |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +do_random=1 +sw_build_device=sim_dv +sw_images=pwrmgr_sensor_ctrl_deep_sleep_wake_up:1:new_rul es,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t cl +ntb_random_seed=3443999236 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_pwrmgr_sensor_ctrl_deep_s leep_wake_up.3443999236 |
| Directory | /workspace/1.chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up/latest |
| Test location | /workspace/coverage/default/1.chip_sw_pwrmgr_sleep_disabled.3984867401 |
| Short name | T768 |
| Test name | |
| Test status | |
| Simulation time | 3271345454 ps |
| CPU time | 210.24 seconds |
| Started | Aug 12 07:12:44 PM PDT 24 |
| Finished | Aug 12 07:16:15 PM PDT 24 |
| Peak memory | 609924 kb |
| Host | smart-80c2cc5f-bacc-4d2f-93f6-773e586fee25 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_sleep_disabled_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3984867401 -assert nopostproc +UVM_ TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_ log /dev/null -cm_name 1.chip_sw_pwrmgr_sleep_disabled.3984867401 |
| Directory | /workspace/1.chip_sw_pwrmgr_sleep_disabled/latest |
| Test location | /workspace/coverage/default/1.chip_sw_pwrmgr_sleep_power_glitch_reset.1935380857 |
| Short name | T1242 |
| Test name | |
| Test status | |
| Simulation time | 4851020908 ps |
| CPU time | 534.38 seconds |
| Started | Aug 12 07:14:51 PM PDT 24 |
| Finished | Aug 12 07:23:47 PM PDT 24 |
| Peak memory | 617964 kb |
| Host | smart-274c713d-ad06-498c-83bb-94f3ff464997 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=pwrmgr_sleep_power_glitch_test:1:new_rules,test_rom:0 +c dc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_s eed=1935380857 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_main_power_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_pwrmgr_sleep_power_glitch_reset.1935380857 |
| Directory | /workspace/1.chip_sw_pwrmgr_sleep_power_glitch_reset/latest |
| Test location | /workspace/coverage/default/1.chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup.1557080804 |
| Short name | T140 |
| Test name | |
| Test status | |
| Simulation time | 5274822200 ps |
| CPU time | 483.58 seconds |
| Started | Aug 12 07:18:33 PM PDT 24 |
| Finished | Aug 12 07:26:37 PM PDT 24 |
| Peak memory | 610372 kb |
| Host | smart-8cca8d8b-e2e8-438a-bc6e-586811ebbe78 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=8_000_000 +sw_build_device=sim_dv +sw_images=sensor_ctrl_wakeup_test:1:new_rules,test_rom:0 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15570808 04 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac e/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup.1557080804 |
| Directory | /workspace/1.chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup/latest |
| Test location | /workspace/coverage/default/1.chip_sw_pwrmgr_sleep_wake_5_bug.1399024468 |
| Short name | T139 |
| Test name | |
| Test status | |
| Simulation time | 5472099092 ps |
| CPU time | 519.92 seconds |
| Started | Aug 12 07:20:15 PM PDT 24 |
| Finished | Aug 12 07:28:55 PM PDT 24 |
| Peak memory | 610952 kb |
| Host | smart-2b2797c5-ff97-42b8-aa46-417f207c31b0 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +do_random=1 +sw_build_device=sim_dv +sw_images=pwrmgr_sleep_wake_5_bug_test:1:new_rules,test_r om:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r andom_seed=1399024468 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_pwrmgr_sleep_wake_5_bug.1399024468 |
| Directory | /workspace/1.chip_sw_pwrmgr_sleep_wake_5_bug/latest |
| Test location | /workspace/coverage/default/1.chip_sw_pwrmgr_smoketest.135636995 |
| Short name | T1421 |
| Test name | |
| Test status | |
| Simulation time | 6130195538 ps |
| CPU time | 560.88 seconds |
| Started | Aug 12 07:21:40 PM PDT 24 |
| Finished | Aug 12 07:31:01 PM PDT 24 |
| Peak memory | 610572 kb |
| Host | smart-b3f73e7a-b8ed-42ac-b810-0c48c17c6bd9 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=10000000 +sw_build_device=sim_dv +sw_images=pwrmgr_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=135636995 -asser t nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag e/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_pwrmgr_smoketest.135636995 |
| Directory | /workspace/1.chip_sw_pwrmgr_smoketest/latest |
| Test location | /workspace/coverage/default/1.chip_sw_pwrmgr_sysrst_ctrl_reset.3802739301 |
| Short name | T1115 |
| Test name | |
| Test status | |
| Simulation time | 6897293175 ps |
| CPU time | 1651.7 seconds |
| Started | Aug 12 07:12:13 PM PDT 24 |
| Finished | Aug 12 07:39:45 PM PDT 24 |
| Peak memory | 610960 kb |
| Host | smart-7a2f223e-b26e-487c-9f38-ce40695e3925 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_sysrst_ctrl_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3802739301 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sysrst_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_pwrmgr_sysrst_ctrl_reset.3802739301 |
| Directory | /workspace/1.chip_sw_pwrmgr_sysrst_ctrl_reset/latest |
| Test location | /workspace/coverage/default/1.chip_sw_pwrmgr_usb_clk_disabled_when_active.1338861576 |
| Short name | T272 |
| Test name | |
| Test status | |
| Simulation time | 4231363382 ps |
| CPU time | 389.9 seconds |
| Started | Aug 12 07:14:37 PM PDT 24 |
| Finished | Aug 12 07:21:08 PM PDT 24 |
| Peak memory | 609876 kb |
| Host | smart-6813e038-a906-40e0-b245-0318e1231d39 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_usb_clk_disabled_when_active_test:1:new_rules,test_rom:0 +cdc_instrumentation_enable d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1338861576 -assert no postproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de fault.vdb -cm_log /dev/null -cm_name 1.chip_sw_pwrmgr_usb_clk_disabled_when_active.1338861576 |
| Directory | /workspace/1.chip_sw_pwrmgr_usb_clk_disabled_when_active/latest |
| Test location | /workspace/coverage/default/1.chip_sw_pwrmgr_usbdev_smoketest.3060695982 |
| Short name | T1316 |
| Test name | |
| Test status | |
| Simulation time | 6261963008 ps |
| CPU time | 618.31 seconds |
| Started | Aug 12 07:21:43 PM PDT 24 |
| Finished | Aug 12 07:32:01 PM PDT 24 |
| Peak memory | 609792 kb |
| Host | smart-ad089b2b-2eb5-493f-a16f-737b164ff96c |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_usbdev_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3060695982 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_pwrmgr_usbdev_smoketest.3060695982 |
| Directory | /workspace/1.chip_sw_pwrmgr_usbdev_smoketest/latest |
| Test location | /workspace/coverage/default/1.chip_sw_pwrmgr_wdog_reset.2838794532 |
| Short name | T1070 |
| Test name | |
| Test status | |
| Simulation time | 5470477928 ps |
| CPU time | 561.96 seconds |
| Started | Aug 12 07:16:47 PM PDT 24 |
| Finished | Aug 12 07:26:09 PM PDT 24 |
| Peak memory | 610804 kb |
| Host | smart-f3c7f422-74e4-47ea-98e5-759f3bf2c814 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=pwrmgr_wdog_reset_reqs_test:1:new_rules,test_rom:0 +cdc_inst rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=283 8794532 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_pwrmgr_wdog_reset.2838794532 |
| Directory | /workspace/1.chip_sw_pwrmgr_wdog_reset/latest |
| Test location | /workspace/coverage/default/1.chip_sw_rom_ctrl_integrity_check.1023881785 |
| Short name | T1423 |
| Test name | |
| Test status | |
| Simulation time | 9125556519 ps |
| CPU time | 527.46 seconds |
| Started | Aug 12 07:17:21 PM PDT 24 |
| Finished | Aug 12 07:26:09 PM PDT 24 |
| Peak memory | 611012 kb |
| Host | smart-43898791-cba0-4c4f-a2c5-7e6947efad3b |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=rom_ctrl_integrity_check_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1023881785 -assert nopostproc +U VM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rom_ctrl_integrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co verage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_rom_ctrl_integrity_check.1023881785 |
| Directory | /workspace/1.chip_sw_rom_ctrl_integrity_check/latest |
| Test location | /workspace/coverage/default/1.chip_sw_rstmgr_alert_info.71347751 |
| Short name | T340 |
| Test name | |
| Test status | |
| Simulation time | 14719137500 ps |
| CPU time | 2088.72 seconds |
| Started | Aug 12 07:15:25 PM PDT 24 |
| Finished | Aug 12 07:50:14 PM PDT 24 |
| Peak memory | 611104 kb |
| Host | smart-a442bf78-6615-4de0-bd8d-3337fff1f7b1 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=30_000_000 +en_scb_tl_err_chk=0 +sw_build_device=sim_dv +sw_images=rstmgr_alert_info_test:1:new_rules,test _rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb _random_seed=71347751 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_rstmgr_alert_info.71347751 |
| Directory | /workspace/1.chip_sw_rstmgr_alert_info/latest |
| Test location | /workspace/coverage/default/1.chip_sw_rstmgr_cpu_info.4171653278 |
| Short name | T269 |
| Test name | |
| Test status | |
| Simulation time | 6234461384 ps |
| CPU time | 612.23 seconds |
| Started | Aug 12 07:13:54 PM PDT 24 |
| Finished | Aug 12 07:24:07 PM PDT 24 |
| Peak memory | 610968 kb |
| Host | smart-c5523a54-0b29-4cab-9164-b3f19b49170a |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=rstmgr_cpu_info_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4171653278 -assert nopostproc +UVM_TESTNA ME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 1.chip_sw_rstmgr_cpu_info.4171653278 |
| Directory | /workspace/1.chip_sw_rstmgr_cpu_info/latest |
| Test location | /workspace/coverage/default/1.chip_sw_rstmgr_rst_cnsty_escalation.266585360 |
| Short name | T1098 |
| Test name | |
| Test status | |
| Simulation time | 5778358490 ps |
| CPU time | 729.85 seconds |
| Started | Aug 12 07:14:23 PM PDT 24 |
| Finished | Aug 12 07:26:33 PM PDT 24 |
| Peak memory | 642128 kb |
| Host | smart-45ba45e6-cb0c-471a-858c-fe2bda4d35ca |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 266585360 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rstmgr_cnsty_fault_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_rstmgr_rst_cnsty_escalation.266585360 |
| Directory | /workspace/1.chip_sw_rstmgr_rst_cnsty_escalation/latest |
| Test location | /workspace/coverage/default/1.chip_sw_rstmgr_smoketest.1621304745 |
| Short name | T1129 |
| Test name | |
| Test status | |
| Simulation time | 2628181750 ps |
| CPU time | 206.31 seconds |
| Started | Aug 12 07:23:00 PM PDT 24 |
| Finished | Aug 12 07:26:27 PM PDT 24 |
| Peak memory | 610124 kb |
| Host | smart-15739fab-4ab9-4456-b772-0a6ac8422325 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=rstmgr_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1621304745 -assert nopostproc +UVM_TESTNAME=c hip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n ull -cm_name 1.chip_sw_rstmgr_smoketest.1621304745 |
| Directory | /workspace/1.chip_sw_rstmgr_smoketest/latest |
| Test location | /workspace/coverage/default/1.chip_sw_rstmgr_sw_req.737055274 |
| Short name | T1025 |
| Test name | |
| Test status | |
| Simulation time | 4521503340 ps |
| CPU time | 361 seconds |
| Started | Aug 12 07:16:40 PM PDT 24 |
| Finished | Aug 12 07:22:42 PM PDT 24 |
| Peak memory | 610864 kb |
| Host | smart-8130094b-84dd-41b0-a337-a525ab509b1b |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=rstmgr_sw_req_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=737055274 -assert nopostproc +UVM_TESTNAME= chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/ null -cm_name 1.chip_sw_rstmgr_sw_req.737055274 |
| Directory | /workspace/1.chip_sw_rstmgr_sw_req/latest |
| Test location | /workspace/coverage/default/1.chip_sw_rstmgr_sw_rst.170373699 |
| Short name | T397 |
| Test name | |
| Test status | |
| Simulation time | 2950539134 ps |
| CPU time | 238.52 seconds |
| Started | Aug 12 07:14:13 PM PDT 24 |
| Finished | Aug 12 07:18:12 PM PDT 24 |
| Peak memory | 608940 kb |
| Host | smart-60e14878-66e2-40a0-881a-94517f3e64a2 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=rstmgr_sw_rst_ctrl_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=170373699 -assert nopostproc +UVM_TEST NAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_rstmgr_sw_rst.170373699 |
| Directory | /workspace/1.chip_sw_rstmgr_sw_rst/latest |
| Test location | /workspace/coverage/default/1.chip_sw_rv_core_ibex_address_translation.1393151788 |
| Short name | T193 |
| Test name | |
| Test status | |
| Simulation time | 3633352052 ps |
| CPU time | 339.6 seconds |
| Started | Aug 12 07:21:14 PM PDT 24 |
| Finished | Aug 12 07:26:54 PM PDT 24 |
| Peak memory | 610200 kb |
| Host | smart-b24feecd-317e-4889-832a-9b2d70179975 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=7_000_000 +sw_build_device=sim_dv +sw_images=rv_core_ibex_address_translation_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random _seed=1393151788 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_rv_core_ibex_address_translation.1393151788 |
| Directory | /workspace/1.chip_sw_rv_core_ibex_address_translation/latest |
| Test location | /workspace/coverage/default/1.chip_sw_rv_core_ibex_icache_invalidate.2148984447 |
| Short name | T305 |
| Test name | |
| Test status | |
| Simulation time | 2571235021 ps |
| CPU time | 212.68 seconds |
| Started | Aug 12 07:21:12 PM PDT 24 |
| Finished | Aug 12 07:24:45 PM PDT 24 |
| Peak memory | 608980 kb |
| Host | smart-f009e0b0-e228-4e57-9978-12b8fc711782 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=rv_core_ibex_icache_invalidate_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2148984447 -assert nopostp roc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rv_core_ibex_icache_invalidate_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_rv_core_ibex_icache_invalidate.2148984447 |
| Directory | /workspace/1.chip_sw_rv_core_ibex_icache_invalidate/latest |
| Test location | /workspace/coverage/default/1.chip_sw_rv_core_ibex_nmi_irq.743519422 |
| Short name | T548 |
| Test name | |
| Test status | |
| Simulation time | 4566196162 ps |
| CPU time | 767.65 seconds |
| Started | Aug 12 07:14:11 PM PDT 24 |
| Finished | Aug 12 07:26:59 PM PDT 24 |
| Peak memory | 609452 kb |
| Host | smart-9dca4785-9476-404f-aeec-e8617b7d46e4 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=10_000_000 +sw_build_device=sim_dv +sw_images=rv_core_ibex_nmi_irq_test:1:new_rules,test_rom:0 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=74351 9422 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_rv_core_ibex_nmi_irq.743519422 |
| Directory | /workspace/1.chip_sw_rv_core_ibex_nmi_irq/latest |
| Test location | /workspace/coverage/default/1.chip_sw_rv_core_ibex_rnd.1373690882 |
| Short name | T1101 |
| Test name | |
| Test status | |
| Simulation time | 5218232088 ps |
| CPU time | 1124.93 seconds |
| Started | Aug 12 07:16:10 PM PDT 24 |
| Finished | Aug 12 07:34:56 PM PDT 24 |
| Peak memory | 610408 kb |
| Host | smart-9d3b94a3-a188-4ca3-b42b-ce81978d1763 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=20_000_000 +rng_srate_value_max=32 +sw_build_device=sim_dv +sw_images=rv_core_ibex_rnd_test:1:new_rules,te st_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n tb_random_seed=1373690882 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_rv_core_ibex_rnd.1373690882 |
| Directory | /workspace/1.chip_sw_rv_core_ibex_rnd/latest |
| Test location | /workspace/coverage/default/1.chip_sw_rv_dm_access_after_escalation_reset.3754147483 |
| Short name | T750 |
| Test name | |
| Test status | |
| Simulation time | 6561452413 ps |
| CPU time | 663.88 seconds |
| Started | Aug 12 07:20:12 PM PDT 24 |
| Finished | Aug 12 07:31:16 PM PDT 24 |
| Peak memory | 624852 kb |
| Host | smart-7551a856-0925-4a38-ba05-b7dfc2740f6d |
| User | root |
| Command | /workspace/default/simv +use_jtag_dmi=1 +sw_build_device=sim_dv +sw_images=alert_handler_escalation_test:1:new_rules,test_rom:0 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3754147483 -asse rt nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rv_dm_access_after_escalation_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_rv_dm_access_after_escalation_reset.3754147483 |
| Directory | /workspace/1.chip_sw_rv_dm_access_after_escalation_reset/latest |
| Test location | /workspace/coverage/default/1.chip_sw_rv_dm_access_after_wakeup.2471459406 |
| Short name | T437 |
| Test name | |
| Test status | |
| Simulation time | 5521637700 ps |
| CPU time | 427.3 seconds |
| Started | Aug 12 07:19:23 PM PDT 24 |
| Finished | Aug 12 07:26:30 PM PDT 24 |
| Peak memory | 621072 kb |
| Host | smart-0762a2cb-f2ba-425d-aa77-411aa3646a0c |
| User | root |
| Command | /workspace/default/simv +use_jtag_dmi=1 +sw_build_device=sim_dv +sw_images=rv_dm_access_after_wakeup_rma:1:new_rules,test_rom:0 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2471459406 -asse rt nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rv_dm_access_after_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_rv_dm_access_after_wakeup.2471459406 |
| Directory | /workspace/1.chip_sw_rv_dm_access_after_wakeup/latest |
| Test location | /workspace/coverage/default/1.chip_sw_rv_dm_ndm_reset_req_when_cpu_halted.2074295471 |
| Short name | T315 |
| Test name | |
| Test status | |
| Simulation time | 4847509722 ps |
| CPU time | 658.2 seconds |
| Started | Aug 12 07:20:16 PM PDT 24 |
| Finished | Aug 12 07:31:16 PM PDT 24 |
| Peak memory | 621120 kb |
| Host | smart-246be103-387c-43ee-8ca3-786873d918b1 |
| User | root |
| Command | /workspace/default/simv +use_jtag_dmi=1 +sw_build_device=sim_dv +sw_images=rv_dm_ndm_reset_req_when_cpu_halted_rma:1:new_rules,test_rom:0 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=207429 5471 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rv_dm_ndm_reset_when_cpu_halted_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_rv_dm_ndm_reset_req_when_cpu_halted.2074295471 |
| Directory | /workspace/1.chip_sw_rv_dm_ndm_reset_req_when_cpu_halted/latest |
| Test location | /workspace/coverage/default/1.chip_sw_rv_plic_smoketest.2480644654 |
| Short name | T5 |
| Test name | |
| Test status | |
| Simulation time | 2985041996 ps |
| CPU time | 332.38 seconds |
| Started | Aug 12 07:20:57 PM PDT 24 |
| Finished | Aug 12 07:26:29 PM PDT 24 |
| Peak memory | 609732 kb |
| Host | smart-7f0d06ee-704e-4124-bdb7-d970cfca8ae5 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=rv_plic_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2480644654 -assert nopostproc +UVM_TESTNAME= chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/ null -cm_name 1.chip_sw_rv_plic_smoketest.2480644654 |
| Directory | /workspace/1.chip_sw_rv_plic_smoketest/latest |
| Test location | /workspace/coverage/default/1.chip_sw_rv_timer_irq.499753530 |
| Short name | T254 |
| Test name | |
| Test status | |
| Simulation time | 3036118812 ps |
| CPU time | 241.66 seconds |
| Started | Aug 12 07:14:10 PM PDT 24 |
| Finished | Aug 12 07:18:12 PM PDT 24 |
| Peak memory | 609732 kb |
| Host | smart-497555fa-8a74-4899-a3c5-53a175493ad6 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=rv_timer_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=499753530 -assert nopostproc +UVM_TESTNAME= chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/ null -cm_name 1.chip_sw_rv_timer_irq.499753530 |
| Directory | /workspace/1.chip_sw_rv_timer_irq/latest |
| Test location | /workspace/coverage/default/1.chip_sw_rv_timer_smoketest.2286616101 |
| Short name | T1065 |
| Test name | |
| Test status | |
| Simulation time | 3005542582 ps |
| CPU time | 236.21 seconds |
| Started | Aug 12 07:26:36 PM PDT 24 |
| Finished | Aug 12 07:30:33 PM PDT 24 |
| Peak memory | 610172 kb |
| Host | smart-b9f5e05e-71bb-4e99-a6a9-4a79baf0169a |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=rv_timer_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2286616101 -assert nopostproc +UVM_TESTNAME =chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 1.chip_sw_rv_timer_smoketest.2286616101 |
| Directory | /workspace/1.chip_sw_rv_timer_smoketest/latest |
| Test location | /workspace/coverage/default/1.chip_sw_sensor_ctrl_alert.1011792792 |
| Short name | T144 |
| Test name | |
| Test status | |
| Simulation time | 5423150490 ps |
| CPU time | 618.55 seconds |
| Started | Aug 12 07:19:22 PM PDT 24 |
| Finished | Aug 12 07:29:41 PM PDT 24 |
| Peak memory | 609924 kb |
| Host | smart-07ab4bf4-39ab-4d37-97d9-33f15d6faaa9 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=40_000_000 +sw_build_device=sim_dv +sw_images=sensor_ctrl_alert_test:1:new_rules,test_rom:0 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10117927 92 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac e/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_sensor_ctrl_alert.1011792792 |
| Directory | /workspace/1.chip_sw_sensor_ctrl_alert/latest |
| Test location | /workspace/coverage/default/1.chip_sw_sensor_ctrl_status.2710272433 |
| Short name | T365 |
| Test name | |
| Test status | |
| Simulation time | 2914617199 ps |
| CPU time | 269.5 seconds |
| Started | Aug 12 07:18:23 PM PDT 24 |
| Finished | Aug 12 07:22:53 PM PDT 24 |
| Peak memory | 609964 kb |
| Host | smart-9dcc0e29-6ab2-4dbc-aff5-24424fe04014 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=40_000_000 +sw_build_device=sim_dv +sw_images=sensor_ctrl_status_test:1:new_rules,test_rom:0 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2710272 433 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sensor_ctrl_status_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_sensor_ctrl_status.2710272433 |
| Directory | /workspace/1.chip_sw_sensor_ctrl_status/latest |
| Test location | /workspace/coverage/default/1.chip_sw_sleep_pin_retention.3135548842 |
| Short name | T60 |
| Test name | |
| Test status | |
| Simulation time | 4445147882 ps |
| CPU time | 336.48 seconds |
| Started | Aug 12 07:13:06 PM PDT 24 |
| Finished | Aug 12 07:18:44 PM PDT 24 |
| Peak memory | 608152 kb |
| Host | smart-c2bbfc35-fa95-4efa-99e8-abc0c8510d93 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=sleep_pin_retention_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3135548842 -assert nopostproc +UVM_TE STNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sleep_pin_retention_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def ault.vdb -cm_log /dev/null -cm_name 1.chip_sw_sleep_pin_retention.3135548842 |
| Directory | /workspace/1.chip_sw_sleep_pin_retention/latest |
| Test location | /workspace/coverage/default/1.chip_sw_sleep_pin_wake.3832316538 |
| Short name | T104 |
| Test name | |
| Test status | |
| Simulation time | 3468751640 ps |
| CPU time | 208.68 seconds |
| Started | Aug 12 07:11:08 PM PDT 24 |
| Finished | Aug 12 07:14:37 PM PDT 24 |
| Peak memory | 609852 kb |
| Host | smart-b3d36f01-26f2-4dfe-aaeb-e2334a956cd1 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStProd +sw_build_device=sim_dv +sw_images=sleep_pin_wake_test:1:new_rules,test_rom:0 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3832316538 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sleep_pin_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_sleep_pin_wake.3832316538 |
| Directory | /workspace/1.chip_sw_sleep_pin_wake/latest |
| Test location | /workspace/coverage/default/1.chip_sw_sleep_pwm_pulses.1871462860 |
| Short name | T781 |
| Test name | |
| Test status | |
| Simulation time | 9561816504 ps |
| CPU time | 1158.84 seconds |
| Started | Aug 12 07:11:14 PM PDT 24 |
| Finished | Aug 12 07:30:34 PM PDT 24 |
| Peak memory | 609992 kb |
| Host | smart-f6d0f624-790e-47a8-81a4-7c1d3ba75cb8 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=sleep_pwm_pulses_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1871462860 -assert nopostproc +UVM_TESTN AME=chip_base_test +UVM_TEST_SEQ=chip_sw_pwm_pulses_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm _log /dev/null -cm_name 1.chip_sw_sleep_pwm_pulses.1871462860 |
| Directory | /workspace/1.chip_sw_sleep_pwm_pulses/latest |
| Test location | /workspace/coverage/default/1.chip_sw_sleep_sram_ret_contents_no_scramble.4144369802 |
| Short name | T1216 |
| Test name | |
| Test status | |
| Simulation time | 8222354566 ps |
| CPU time | 535.01 seconds |
| Started | Aug 12 07:17:30 PM PDT 24 |
| Finished | Aug 12 07:26:25 PM PDT 24 |
| Peak memory | 611068 kb |
| Host | smart-c968c568-1f49-4d64-8b84-1e586c0230c9 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=20_000_000 +en_scb_tl_err_chk=0 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=sram _ctrl_sleep_sram_ret_contents_no_scramble_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4144369802 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_S EQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_sl eep_sram_ret_contents_no_scramble.4144369802 |
| Directory | /workspace/1.chip_sw_sleep_sram_ret_contents_no_scramble/latest |
| Test location | /workspace/coverage/default/1.chip_sw_sleep_sram_ret_contents_scramble.4067357617 |
| Short name | T1205 |
| Test name | |
| Test status | |
| Simulation time | 7590284088 ps |
| CPU time | 650.15 seconds |
| Started | Aug 12 07:19:52 PM PDT 24 |
| Finished | Aug 12 07:30:42 PM PDT 24 |
| Peak memory | 610808 kb |
| Host | smart-09283028-85f9-4fa8-891e-2cf32440d289 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=20_000_000 +en_scb_tl_err_chk=0 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=sram _ctrl_sleep_sram_ret_contents_scramble_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4067357617 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ= chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_sleep _sram_ret_contents_scramble.4067357617 |
| Directory | /workspace/1.chip_sw_sleep_sram_ret_contents_scramble/latest |
| Test location | /workspace/coverage/default/1.chip_sw_spi_device_pass_through.3293640857 |
| Short name | T46 |
| Test name | |
| Test status | |
| Simulation time | 7006886071 ps |
| CPU time | 895.61 seconds |
| Started | Aug 12 07:15:15 PM PDT 24 |
| Finished | Aug 12 07:30:11 PM PDT 24 |
| Peak memory | 625192 kb |
| Host | smart-8d56c70c-3d13-4d83-b5db-0116bb797ed9 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=spi_passthrough_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3293640857 -assert nopostproc +UVM_TESTNA ME=chip_base_test +UVM_TEST_SEQ=chip_sw_spi_passthrough_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_spi_device_pass_through.3293640857 |
| Directory | /workspace/1.chip_sw_spi_device_pass_through/latest |
| Test location | /workspace/coverage/default/1.chip_sw_spi_device_pass_through_collision.1205541086 |
| Short name | T206 |
| Test name | |
| Test status | |
| Simulation time | 4522105691 ps |
| CPU time | 537.09 seconds |
| Started | Aug 12 07:12:43 PM PDT 24 |
| Finished | Aug 12 07:21:41 PM PDT 24 |
| Peak memory | 625216 kb |
| Host | smart-06d2ab65-29b6-4808-bfb5-c473643a496a |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=spi_passthrough_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1205541086 -assert nopostproc +UVM_TESTNA ME=chip_base_test +UVM_TEST_SEQ=chip_sw_spi_passthrough_collision_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/d efault.vdb -cm_log /dev/null -cm_name 1.chip_sw_spi_device_pass_through_collision.1205541086 |
| Directory | /workspace/1.chip_sw_spi_device_pass_through_collision/latest |
| Test location | /workspace/coverage/default/1.chip_sw_spi_device_pinmux_sleep_retention.545839058 |
| Short name | T62 |
| Test name | |
| Test status | |
| Simulation time | 3404905536 ps |
| CPU time | 281.17 seconds |
| Started | Aug 12 07:11:10 PM PDT 24 |
| Finished | Aug 12 07:15:52 PM PDT 24 |
| Peak memory | 618288 kb |
| Host | smart-a4441996-1efa-4280-9264-f9d0b672531b |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=spi_device_sleep_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=545839058 -assert nopostproc +UVM_TESTNA ME=chip_base_test +UVM_TEST_SEQ=chip_sw_spi_device_pinmux_sleep_retention_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co verage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_spi_device_pinmux_sleep_retention.545839058 |
| Directory | /workspace/1.chip_sw_spi_device_pinmux_sleep_retention/latest |
| Test location | /workspace/coverage/default/1.chip_sw_spi_device_tpm.1127124642 |
| Short name | T44 |
| Test name | |
| Test status | |
| Simulation time | 3703815014 ps |
| CPU time | 320.98 seconds |
| Started | Aug 12 07:14:01 PM PDT 24 |
| Finished | Aug 12 07:19:22 PM PDT 24 |
| Peak memory | 618684 kb |
| Host | smart-0a54e5d4-8f47-4fb4-ace1-c8cbecdb1b9b |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=spi_device_tpm_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1127124642 -assert nopostproc +UVM_T ESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_spi_device_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default .vdb -cm_log /dev/null -cm_name 1.chip_sw_spi_device_tpm.1127124642 |
| Directory | /workspace/1.chip_sw_spi_device_tpm/latest |
| Test location | /workspace/coverage/default/1.chip_sw_spi_host_tx_rx.3358337367 |
| Short name | T38 |
| Test name | |
| Test status | |
| Simulation time | 3121782806 ps |
| CPU time | 318.26 seconds |
| Started | Aug 12 07:15:57 PM PDT 24 |
| Finished | Aug 12 07:21:16 PM PDT 24 |
| Peak memory | 609360 kb |
| Host | smart-9a0dcd32-54de-459a-b38d-b687ce2a6f16 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=spi_host_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3358337367 -assert nopostproc +UVM_TESTNAM E=chip_base_test +UVM_TEST_SEQ=chip_sw_spi_host_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb - cm_log /dev/null -cm_name 1.chip_sw_spi_host_tx_rx.3358337367 |
| Directory | /workspace/1.chip_sw_spi_host_tx_rx/latest |
| Test location | /workspace/coverage/default/1.chip_sw_sram_ctrl_execution_main.3065847493 |
| Short name | T191 |
| Test name | |
| Test status | |
| Simulation time | 6589716089 ps |
| CPU time | 812.24 seconds |
| Started | Aug 12 07:18:23 PM PDT 24 |
| Finished | Aug 12 07:31:55 PM PDT 24 |
| Peak memory | 610948 kb |
| Host | smart-a4b67961-fcce-4346-ae63-3483d77b0abb |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=sram_ctrl_execution_main_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3065847493 -assert nopostproc +U VM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sram_ctrl_execution_main_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co verage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_sram_ctrl_execution_main.3065847493 |
| Directory | /workspace/1.chip_sw_sram_ctrl_execution_main/latest |
| Test location | /workspace/coverage/default/1.chip_sw_sram_ctrl_scrambled_access.3404487091 |
| Short name | T1273 |
| Test name | |
| Test status | |
| Simulation time | 5377612060 ps |
| CPU time | 657.79 seconds |
| Started | Aug 12 07:18:11 PM PDT 24 |
| Finished | Aug 12 07:29:09 PM PDT 24 |
| Peak memory | 611592 kb |
| Host | smart-8c89dd3a-e19e-43d6-a6b2-f6608f0262d0 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=12_000_000 +en_scb_tl_err_chk=0 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=sram _ctrl_scrambled_access_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3404487091 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sram_ctr l_scrambled_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw _sram_ctrl_scrambled_access.3404487091 |
| Directory | /workspace/1.chip_sw_sram_ctrl_scrambled_access/latest |
| Test location | /workspace/coverage/default/1.chip_sw_sram_ctrl_scrambled_access_jitter_en.214944745 |
| Short name | T188 |
| Test name | |
| Test status | |
| Simulation time | 5343936245 ps |
| CPU time | 549.77 seconds |
| Started | Aug 12 07:17:55 PM PDT 24 |
| Finished | Aug 12 07:27:05 PM PDT 24 |
| Peak memory | 610224 kb |
| Host | smart-ee5ea593-11d0-4f46-a58f-8b92962e04f1 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=12_000_000 +bypass_alert_ready_to_end_check=1 +en_jitter=1 +en_scb_tl_err_chk=0 +sw_build_device=sim_dv +s w_images=sram_ctrl_scrambled_access_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=214944745 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip _sw_sram_ctrl_scrambled_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na me 1.chip_sw_sram_ctrl_scrambled_access_jitter_en.214944745 |
| Directory | /workspace/1.chip_sw_sram_ctrl_scrambled_access_jitter_en/latest |
| Test location | /workspace/coverage/default/1.chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq.3234306580 |
| Short name | T1420 |
| Test name | |
| Test status | |
| Simulation time | 4290680615 ps |
| CPU time | 584.85 seconds |
| Started | Aug 12 07:21:26 PM PDT 24 |
| Finished | Aug 12 07:31:11 PM PDT 24 |
| Peak memory | 611172 kb |
| Host | smart-2061b058-9cb2-491e-8f48-de67c17fda68 |
| User | root |
| Command | /workspace/default/simv +mem_sel=main +sw_test_timeout_ns=12_000_000 +bypass_alert_ready_to_end_check=1 +en_jitter=1 +en_scb_tl_err_chk=0 +cal_sys_clk _70mhz=1 +sw_build_device=sim_dv +sw_images=sram_ctrl_scrambled_access_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3234306580 -assert nopostproc +UVM_TESTNA ME=chip_base_test +UVM_TEST_SEQ=chip_sw_sram_ctrl_scrambled_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/ default.vdb -cm_log /dev/null -cm_name 1.chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq.3234306580 |
| Directory | /workspace/1.chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq/latest |
| Test location | /workspace/coverage/default/1.chip_sw_sram_ctrl_smoketest.2008495923 |
| Short name | T977 |
| Test name | |
| Test status | |
| Simulation time | 2981871832 ps |
| CPU time | 221.58 seconds |
| Started | Aug 12 07:23:02 PM PDT 24 |
| Finished | Aug 12 07:26:44 PM PDT 24 |
| Peak memory | 609804 kb |
| Host | smart-63f78be4-1f28-4659-8810-6546ed9f5597 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=sram_ctrl_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2008495923 -assert nopostproc +UVM_TESTNAM E=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 1.chip_sw_sram_ctrl_smoketest.2008495923 |
| Directory | /workspace/1.chip_sw_sram_ctrl_smoketest/latest |
| Test location | /workspace/coverage/default/1.chip_sw_sysrst_ctrl_ec_rst_l.3623497900 |
| Short name | T1322 |
| Test name | |
| Test status | |
| Simulation time | 20875075724 ps |
| CPU time | 3038.08 seconds |
| Started | Aug 12 07:15:16 PM PDT 24 |
| Finished | Aug 12 08:05:54 PM PDT 24 |
| Peak memory | 611208 kb |
| Host | smart-92698071-be32-468f-8454-c1adf00898be |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=sysrst_ctrl_ec_rst_l_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3623497900 -assert nopostproc +UVM_T ESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sysrst_ctrl_ec_rst_l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/d efault.vdb -cm_log /dev/null -cm_name 1.chip_sw_sysrst_ctrl_ec_rst_l.3623497900 |
| Directory | /workspace/1.chip_sw_sysrst_ctrl_ec_rst_l/latest |
| Test location | /workspace/coverage/default/1.chip_sw_sysrst_ctrl_in_irq.363480674 |
| Short name | T216 |
| Test name | |
| Test status | |
| Simulation time | 5196331557 ps |
| CPU time | 548.93 seconds |
| Started | Aug 12 07:13:19 PM PDT 24 |
| Finished | Aug 12 07:22:31 PM PDT 24 |
| Peak memory | 614224 kb |
| Host | smart-cd247877-9355-4734-bc5c-ff6166c27204 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=sysrst_ctrl_in_irq_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=363480674 -assert nopostproc +UVM_TEST NAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sysrst_ctrl_in_irq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul t.vdb -cm_log /dev/null -cm_name 1.chip_sw_sysrst_ctrl_in_irq.363480674 |
| Directory | /workspace/1.chip_sw_sysrst_ctrl_in_irq/latest |
| Test location | /workspace/coverage/default/1.chip_sw_sysrst_ctrl_inputs.782284250 |
| Short name | T215 |
| Test name | |
| Test status | |
| Simulation time | 2588799333 ps |
| CPU time | 334.99 seconds |
| Started | Aug 12 07:14:32 PM PDT 24 |
| Finished | Aug 12 07:20:08 PM PDT 24 |
| Peak memory | 613516 kb |
| Host | smart-1146f155-6a6d-4204-8287-5c3a1c7e995b |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=sysrst_ctrl_inputs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=782284250 -assert nopostproc +UVM_TEST NAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sysrst_ctrl_inputs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul t.vdb -cm_log /dev/null -cm_name 1.chip_sw_sysrst_ctrl_inputs.782284250 |
| Directory | /workspace/1.chip_sw_sysrst_ctrl_inputs/latest |
| Test location | /workspace/coverage/default/1.chip_sw_sysrst_ctrl_outputs.3721443533 |
| Short name | T23 |
| Test name | |
| Test status | |
| Simulation time | 3457358608 ps |
| CPU time | 404.97 seconds |
| Started | Aug 12 07:13:23 PM PDT 24 |
| Finished | Aug 12 07:20:10 PM PDT 24 |
| Peak memory | 610520 kb |
| Host | smart-b5a8dcbb-49f7-4b33-8975-c92a980da7cc |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=sysrst_ctrl_outputs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3721443533 -assert nopostproc +UVM_TE STNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sysrst_ctrl_outputs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def ault.vdb -cm_log /dev/null -cm_name 1.chip_sw_sysrst_ctrl_outputs.3721443533 |
| Directory | /workspace/1.chip_sw_sysrst_ctrl_outputs/latest |
| Test location | /workspace/coverage/default/1.chip_sw_uart_rand_baudrate.4032261570 |
| Short name | T1172 |
| Test name | |
| Test status | |
| Simulation time | 4688258000 ps |
| CPU time | 654.42 seconds |
| Started | Aug 12 07:14:40 PM PDT 24 |
| Finished | Aug 12 07:25:36 PM PDT 24 |
| Peak memory | 623908 kb |
| Host | smart-c7842ab0-a5f4-4e4e-98a9-0b29cf53d577 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random _seed=4032261570 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_uart_rand_baudrate.4032261570 |
| Directory | /workspace/1.chip_sw_uart_rand_baudrate/latest |
| Test location | /workspace/coverage/default/1.chip_sw_uart_smoketest.3565764948 |
| Short name | T1367 |
| Test name | |
| Test status | |
| Simulation time | 2477077600 ps |
| CPU time | 222.85 seconds |
| Started | Aug 12 07:22:44 PM PDT 24 |
| Finished | Aug 12 07:26:27 PM PDT 24 |
| Peak memory | 615212 kb |
| Host | smart-595fefcf-0317-4adc-b3ba-7c0b647ab8bf |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=uart_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3565764948 -assert nopostproc +UVM_TESTNAME=chi p_base_test +UVM_TEST_SEQ=chip_sw_uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 1.chip_sw_uart_smoketest.3565764948 |
| Directory | /workspace/1.chip_sw_uart_smoketest/latest |
| Test location | /workspace/coverage/default/1.chip_sw_uart_tx_rx.1512035725 |
| Short name | T1110 |
| Test name | |
| Test status | |
| Simulation time | 3910587880 ps |
| CPU time | 610.3 seconds |
| Started | Aug 12 07:10:28 PM PDT 24 |
| Finished | Aug 12 07:20:39 PM PDT 24 |
| Peak memory | 624268 kb |
| Host | smart-6300fabc-d0b0-44bf-b0f0-5dbf51c2ffbf |
| User | root |
| Command | /workspace/default/simv +uart_idx=0 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1512035725 -a ssert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ce/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_uart_tx_rx.1512035725 |
| Directory | /workspace/1.chip_sw_uart_tx_rx/latest |
| Test location | /workspace/coverage/default/1.chip_sw_uart_tx_rx_alt_clk_freq.3292004530 |
| Short name | T1227 |
| Test name | |
| Test status | |
| Simulation time | 12633595389 ps |
| CPU time | 2591.55 seconds |
| Started | Aug 12 07:14:37 PM PDT 24 |
| Finished | Aug 12 07:57:49 PM PDT 24 |
| Peak memory | 620088 kb |
| Host | smart-5a7ef5a6-40b6-49ee-baf2-e20b4f67e255 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=80_000_000 +chip_clock_source=ChipClockSourceExternal96Mhz +calibrate_usb_clk=1 +sw_build_device=sim_dv +s w_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3292004530 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_b audrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_uart_tx_rx _alt_clk_freq.3292004530 |
| Directory | /workspace/1.chip_sw_uart_tx_rx_alt_clk_freq/latest |
| Test location | /workspace/coverage/default/1.chip_sw_uart_tx_rx_alt_clk_freq_low_speed.1563744313 |
| Short name | T1285 |
| Test name | |
| Test status | |
| Simulation time | 4007034610 ps |
| CPU time | 498.8 seconds |
| Started | Aug 12 07:12:52 PM PDT 24 |
| Finished | Aug 12 07:21:11 PM PDT 24 |
| Peak memory | 622904 kb |
| Host | smart-0f085cac-3894-47db-a7a9-df64adab8ae9 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +chip_clock_source=ChipClockSourceExternal48Mhz +sw_build_device=sim_dv +s w_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1563744313 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_b audrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_uart_tx_rx _alt_clk_freq_low_speed.1563744313 |
| Directory | /workspace/1.chip_sw_uart_tx_rx_alt_clk_freq_low_speed/latest |
| Test location | /workspace/coverage/default/1.chip_sw_uart_tx_rx_bootstrap.3047678905 |
| Short name | T86 |
| Test name | |
| Test status | |
| Simulation time | 78183866664 ps |
| CPU time | 13735.6 seconds |
| Started | Aug 12 07:12:58 PM PDT 24 |
| Finished | Aug 12 11:01:55 PM PDT 24 |
| Peak memory | 635472 kb |
| Host | smart-4975b408-c9d5-4302-a617-b442d9807419 |
| User | root |
| Command | /workspace/default/simv +use_spi_load_bootstrap=1 +calibrate_usb_clk=1 +test_timeout_ns=160_000_000 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test :1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=3047678905 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_uart_tx_rx_bootstrap.3047678905 |
| Directory | /workspace/1.chip_sw_uart_tx_rx_bootstrap/latest |
| Test location | /workspace/coverage/default/1.chip_sw_uart_tx_rx_idx1.3448390961 |
| Short name | T1297 |
| Test name | |
| Test status | |
| Simulation time | 4221809176 ps |
| CPU time | 528.46 seconds |
| Started | Aug 12 07:11:44 PM PDT 24 |
| Finished | Aug 12 07:20:33 PM PDT 24 |
| Peak memory | 624060 kb |
| Host | smart-b83d1ba9-43b2-461b-a86c-eb87e8f28e9c |
| User | root |
| Command | /workspace/default/simv +uart_idx=1 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3448390961 -a ssert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ce/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_uart_tx_rx_idx1.3448390961 |
| Directory | /workspace/1.chip_sw_uart_tx_rx_idx1/latest |
| Test location | /workspace/coverage/default/1.chip_sw_uart_tx_rx_idx2.2332140275 |
| Short name | T1405 |
| Test name | |
| Test status | |
| Simulation time | 5077565038 ps |
| CPU time | 687.84 seconds |
| Started | Aug 12 07:13:00 PM PDT 24 |
| Finished | Aug 12 07:24:29 PM PDT 24 |
| Peak memory | 624680 kb |
| Host | smart-99934611-2e2d-497a-b1cb-684e9b0f1f8e |
| User | root |
| Command | /workspace/default/simv +uart_idx=2 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2332140275 -a ssert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ce/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_uart_tx_rx_idx2.2332140275 |
| Directory | /workspace/1.chip_sw_uart_tx_rx_idx2/latest |
| Test location | /workspace/coverage/default/1.chip_sw_uart_tx_rx_idx3.165445301 |
| Short name | T1263 |
| Test name | |
| Test status | |
| Simulation time | 4405290312 ps |
| CPU time | 668.12 seconds |
| Started | Aug 12 07:13:09 PM PDT 24 |
| Finished | Aug 12 07:24:18 PM PDT 24 |
| Peak memory | 624280 kb |
| Host | smart-39ae732b-16aa-4bcb-8ae5-83fdf6ad331a |
| User | root |
| Command | /workspace/default/simv +uart_idx=3 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=165445301 -as sert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac e/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_uart_tx_rx_idx3.165445301 |
| Directory | /workspace/1.chip_sw_uart_tx_rx_idx3/latest |
| Test location | /workspace/coverage/default/1.chip_tap_straps_dev.3240493452 |
| Short name | T1303 |
| Test name | |
| Test status | |
| Simulation time | 15223597111 ps |
| CPU time | 1390.1 seconds |
| Started | Aug 12 07:20:59 PM PDT 24 |
| Finished | Aug 12 07:44:09 PM PDT 24 |
| Peak memory | 621456 kb |
| Host | smart-7fee53ec-d107-40fe-8ed8-dc5895e17823 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStDev +create_jtag_riscv_map=1 +sw_build_device=sim_dv +sw_images=example_test_from_rom:0:test_in_rom: new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=3240493452 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_tap_straps_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_tap_straps_dev.3240493452 |
| Directory | /workspace/1.chip_tap_straps_dev/latest |
| Test location | /workspace/coverage/default/1.chip_tap_straps_prod.2536571639 |
| Short name | T1220 |
| Test name | |
| Test status | |
| Simulation time | 3128628219 ps |
| CPU time | 136.39 seconds |
| Started | Aug 12 07:18:42 PM PDT 24 |
| Finished | Aug 12 07:20:58 PM PDT 24 |
| Peak memory | 623724 kb |
| Host | smart-76ffd1fb-d0e9-4d5e-944a-212b82b47749 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStProd +create_jtag_riscv_map=1 +sw_build_device=sim_dv +sw_images=example_test_from_rom:0:test_in_rom :new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2536571639 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_tap_straps_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_tap_straps_prod.2536571639 |
| Directory | /workspace/1.chip_tap_straps_prod/latest |
| Test location | /workspace/coverage/default/1.chip_tap_straps_rma.3721147584 |
| Short name | T1250 |
| Test name | |
| Test status | |
| Simulation time | 5648389925 ps |
| CPU time | 500.54 seconds |
| Started | Aug 12 07:19:50 PM PDT 24 |
| Finished | Aug 12 07:28:10 PM PDT 24 |
| Peak memory | 623732 kb |
| Host | smart-5409570d-a9b9-4abf-ac4e-bb04693de7c9 |
| User | root |
| Command | /workspace/default/simv +create_jtag_riscv_map=1 +sw_build_device=sim_dv +sw_images=example_test_from_rom:0:test_in_rom:new_rules +cdc_instrumentation _enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3721147584 -as sert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_tap_straps_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/c overage/default.vdb -cm_log /dev/null -cm_name 1.chip_tap_straps_rma.3721147584 |
| Directory | /workspace/1.chip_tap_straps_rma/latest |
| Test location | /workspace/coverage/default/1.chip_tap_straps_testunlock0.1077985906 |
| Short name | T1190 |
| Test name | |
| Test status | |
| Simulation time | 5756487414 ps |
| CPU time | 472.71 seconds |
| Started | Aug 12 07:19:44 PM PDT 24 |
| Finished | Aug 12 07:27:37 PM PDT 24 |
| Peak memory | 633152 kb |
| Host | smart-f4a5c509-f2fe-4930-b6f2-128ee538594d |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStTestUnlocked0 +create_jtag_riscv_map=1 +sw_build_device=sim_dv +sw_images=example_test_from_rom:0:te st_in_rom:new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1077985906 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_tap_straps_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_tap_straps_testunlock0.1077985906 |
| Directory | /workspace/1.chip_tap_straps_testunlock0/latest |
| Test location | /workspace/coverage/default/1.rom_e2e_asm_init_dev.1505708357 |
| Short name | T1045 |
| Test name | |
| Test status | |
| Simulation time | 15377318796 ps |
| CPU time | 3796.16 seconds |
| Started | Aug 12 07:27:39 PM PDT 24 |
| Finished | Aug 12 08:30:56 PM PDT 24 |
| Peak memory | 610704 kb |
| Host | smart-ed801eef-95e3-40dc-85ad-678d08ca47ee |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeCustom +sw_test_timeout_ns=20000000 +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_prod _key_0:1:ot_flash_binary,otp_img_e2e_bootstrap_entry_dev:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1505708357 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_S EQ=chip_sw_rom_e2e_asm_init_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_e2e_asm_init_dev.1505708357 |
| Directory | /workspace/1.rom_e2e_asm_init_dev/latest |
| Test location | /workspace/coverage/default/1.rom_e2e_asm_init_prod.1253872839 |
| Short name | T1422 |
| Test name | |
| Test status | |
| Simulation time | 15776832335 ps |
| CPU time | 3817.52 seconds |
| Started | Aug 12 07:26:21 PM PDT 24 |
| Finished | Aug 12 08:29:59 PM PDT 24 |
| Peak memory | 610692 kb |
| Host | smart-0caa3351-1cd7-4d87-9191-0b4e87377b47 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeCustom +sw_test_timeout_ns=20000000 +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_prod _key_0:1:ot_flash_binary,otp_img_e2e_bootstrap_entry_prod:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1253872839 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_ SEQ=chip_sw_rom_e2e_asm_init_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_e2e_asm_init_prod.1253872839 |
| Directory | /workspace/1.rom_e2e_asm_init_prod/latest |
| Test location | /workspace/coverage/default/1.rom_e2e_asm_init_prod_end.4286398565 |
| Short name | T390 |
| Test name | |
| Test status | |
| Simulation time | 15786077227 ps |
| CPU time | 3448.63 seconds |
| Started | Aug 12 07:25:49 PM PDT 24 |
| Finished | Aug 12 08:23:18 PM PDT 24 |
| Peak memory | 610756 kb |
| Host | smart-1585fc03-9a88-461e-8c3d-52eac7c85e66 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeCustom +sw_test_timeout_ns=20000000 +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_prod _key_0:1:ot_flash_binary,otp_img_e2e_bootstrap_entry_prod_end:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4286398565 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_T EST_SEQ=chip_sw_rom_e2e_asm_init_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 1.rom_e2e_asm_init_prod_end.4286398565 |
| Directory | /workspace/1.rom_e2e_asm_init_prod_end/latest |
| Test location | /workspace/coverage/default/1.rom_e2e_asm_init_rma.1662054423 |
| Short name | T1251 |
| Test name | |
| Test status | |
| Simulation time | 15190602464 ps |
| CPU time | 3734.41 seconds |
| Started | Aug 12 07:26:21 PM PDT 24 |
| Finished | Aug 12 08:28:36 PM PDT 24 |
| Peak memory | 610416 kb |
| Host | smart-78880be8-c469-4ea1-863e-ea8c7ce45034 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeCustom +sw_test_timeout_ns=20000000 +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_prod _key_0:1:ot_flash_binary,otp_img_e2e_bootstrap_entry_rma:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1662054423 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_S EQ=chip_sw_rom_e2e_asm_init_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_e2e_asm_init_rma.1662054423 |
| Directory | /workspace/1.rom_e2e_asm_init_rma/latest |
| Test location | /workspace/coverage/default/1.rom_e2e_asm_init_test_unlocked0.4044673082 |
| Short name | T1176 |
| Test name | |
| Test status | |
| Simulation time | 11406712418 ps |
| CPU time | 2694.78 seconds |
| Started | Aug 12 07:27:28 PM PDT 24 |
| Finished | Aug 12 08:12:23 PM PDT 24 |
| Peak memory | 610976 kb |
| Host | smart-ba6c824c-46b7-45ca-9ae8-4fde720d8a37 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeCustom +sw_test_timeout_ns=410_000_000 +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_p rod_key_0:1:ot_flash_binary,otp_img_e2e_bootstrap_entry_test_unlocked0:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY =UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4044673082 -assert nopostproc +UVM_TESTNAME=chip_base_te st +UVM_TEST_SEQ=chip_sw_rom_e2e_asm_init_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/ null -cm_name 1.rom_e2e_asm_init_test_unlocked0.4044673082 |
| Directory | /workspace/1.rom_e2e_asm_init_test_unlocked0/latest |
| Test location | /workspace/coverage/default/1.rom_e2e_keymgr_init_rom_ext_invalid_meas.170210548 |
| Short name | T439 |
| Test name | |
| Test status | |
| Simulation time | 15120866740 ps |
| CPU time | 3186.84 seconds |
| Started | Aug 12 07:25:59 PM PDT 24 |
| Finished | Aug 12 08:19:07 PM PDT 24 |
| Peak memory | 610464 kb |
| Host | smart-cb6918a8-f452-40a4-a99d-473f75c1b5fd |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=40_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=rom_e2e_keymgr_init_otp_invalid _meas:1:new_rules,otp_img_keymgr_otp_invalid_meas:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=170210548 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_ sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_e2e_keymgr_ini t_rom_ext_invalid_meas.170210548 |
| Directory | /workspace/1.rom_e2e_keymgr_init_rom_ext_invalid_meas/latest |
| Test location | /workspace/coverage/default/1.rom_e2e_keymgr_init_rom_ext_meas.2660832490 |
| Short name | T1024 |
| Test name | |
| Test status | |
| Simulation time | 14882185192 ps |
| CPU time | 3379.54 seconds |
| Started | Aug 12 07:27:49 PM PDT 24 |
| Finished | Aug 12 08:24:09 PM PDT 24 |
| Peak memory | 610512 kb |
| Host | smart-ac04f4ab-d5d1-4e44-a6a5-dd92649bd139 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=40_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=rom_e2e_keymgr_init_otp_meas:1: new_rules,otp_img_keymgr_otp_meas:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2660832490 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_e2e_keymgr_init_rom_ext_meas.2660832490 |
| Directory | /workspace/1.rom_e2e_keymgr_init_rom_ext_meas/latest |
| Test location | /workspace/coverage/default/1.rom_e2e_keymgr_init_rom_ext_no_meas.3335447663 |
| Short name | T51 |
| Test name | |
| Test status | |
| Simulation time | 15172664224 ps |
| CPU time | 3252.31 seconds |
| Started | Aug 12 07:25:20 PM PDT 24 |
| Finished | Aug 12 08:19:33 PM PDT 24 |
| Peak memory | 610488 kb |
| Host | smart-e5959a19-6c4e-474e-8107-9e68875db3ae |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=40_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=rom_e2e_keymgr_init_otp_no_meas :1:new_rules,otp_img_keymgr_otp_no_meas:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3335447663 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_e2e_keymgr_init_rom_ext _no_meas.3335447663 |
| Directory | /workspace/1.rom_e2e_keymgr_init_rom_ext_no_meas/latest |
| Test location | /workspace/coverage/default/1.rom_e2e_self_hash.2085071555 |
| Short name | T1377 |
| Test name | |
| Test status | |
| Simulation time | 26402207870 ps |
| CPU time | 6026.32 seconds |
| Started | Aug 12 07:27:38 PM PDT 24 |
| Finished | Aug 12 09:08:06 PM PDT 24 |
| Peak memory | 610552 kb |
| Host | smart-e36b66a4-e06f-462b-84d5-8e1a0c60b1e5 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=200_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=rom_e2e_self_hash_test:1:new_r ules,otp_img_sigverify_spx_prod:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2085071555 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_e2e_self_hash.2085071555 |
| Directory | /workspace/1.rom_e2e_self_hash/latest |
| Test location | /workspace/coverage/default/1.rom_e2e_shutdown_exception_c.3339128272 |
| Short name | T1321 |
| Test name | |
| Test status | |
| Simulation time | 14284411575 ps |
| CPU time | 4688.59 seconds |
| Started | Aug 12 07:27:06 PM PDT 24 |
| Finished | Aug 12 08:45:15 PM PDT 24 |
| Peak memory | 611804 kb |
| Host | smart-a1de31a0-55bc-4ed7-88a7-6b1472a96405 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=40000000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=rom_e2e_shutdown_exception_c:1:ne w_rules,otp_img_secret2_locked_rma:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3339128272 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rom_e2e_shu tdown_exception_c_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_e2e_ shutdown_exception_c.3339128272 |
| Directory | /workspace/1.rom_e2e_shutdown_exception_c/latest |
| Test location | /workspace/coverage/default/1.rom_e2e_shutdown_output.2060010160 |
| Short name | T382 |
| Test name | |
| Test status | |
| Simulation time | 25213504048 ps |
| CPU time | 3685.92 seconds |
| Started | Aug 12 07:26:00 PM PDT 24 |
| Finished | Aug 12 08:27:27 PM PDT 24 |
| Peak memory | 612120 kb |
| Host | smart-b0871167-cd13-4d62-87da-4fd544769f0f |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=20000000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_unsigned:1:ot_f lash_binary,otp_img_shutdown_output_test_unlocked0:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2060010160 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chi p_sw_rom_e2e_shutdown_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_e2e_shutdown_output.2060010160 |
| Directory | /workspace/1.rom_e2e_shutdown_output/latest |
| Test location | /workspace/coverage/default/1.rom_e2e_smoke.61077799 |
| Short name | T1095 |
| Test name | |
| Test status | |
| Simulation time | 15383121820 ps |
| CPU time | 3231.96 seconds |
| Started | Aug 12 07:25:56 PM PDT 24 |
| Finished | Aug 12 08:19:49 PM PDT 24 |
| Peak memory | 610336 kb |
| Host | smart-b3189a80-119c-4949-8e31-bb6b6f63eb3a |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=40000000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=rom_e2e_smoke:1:new_rules,otp_img _secret2_locked_rma:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_to p/hw/dv/tools/sim.tcl +ntb_random_seed=61077799 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_e2e_smoke.61077799 |
| Directory | /workspace/1.rom_e2e_smoke/latest |
| Test location | /workspace/coverage/default/1.rom_e2e_static_critical.3928777842 |
| Short name | T1001 |
| Test name | |
| Test status | |
| Simulation time | 16895699320 ps |
| CPU time | 3613.85 seconds |
| Started | Aug 12 07:25:46 PM PDT 24 |
| Finished | Aug 12 08:26:00 PM PDT 24 |
| Peak memory | 610576 kb |
| Host | smart-b2b84f5a-16f7-4f65-ba5e-1d930e326da8 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=40000000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=rom_e2e_static_critical:1:new_rul es,otp_img_secret2_locked_rma:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3928777842 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_e2e_static_critical.3928777842 |
| Directory | /workspace/1.rom_e2e_static_critical/latest |
| Test location | /workspace/coverage/default/1.rom_keymgr_functest.670872820 |
| Short name | T1011 |
| Test name | |
| Test status | |
| Simulation time | 5144701780 ps |
| CPU time | 647.21 seconds |
| Started | Aug 12 07:23:57 PM PDT 24 |
| Finished | Aug 12 07:34:45 PM PDT 24 |
| Peak memory | 610936 kb |
| Host | smart-e53905c0-fac6-490f-a8e1-89dfe9586cc3 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=10_000_000 +sw_build_device=sim_dv +sw_images=keymgr_functest:1:new_rules,test_rom:0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=670872820 -asse rt nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera ge/default.vdb -cm_log /dev/null -cm_name 1.rom_keymgr_functest.670872820 |
| Directory | /workspace/1.rom_keymgr_functest/latest |
| Test location | /workspace/coverage/default/1.rom_raw_unlock.1794385683 |
| Short name | T166 |
| Test name | |
| Test status | |
| Simulation time | 5090731932 ps |
| CPU time | 255.61 seconds |
| Started | Aug 12 07:22:26 PM PDT 24 |
| Finished | Aug 12 07:26:42 PM PDT 24 |
| Peak memory | 624040 kb |
| Host | smart-60588c18-0af0-4aaa-9249-0d124b284bd9 |
| User | root |
| Command | /workspace/default/simv +do_creator_sw_cfg_ast_cfg=0 +sw_test_timeout_ns=200_000_000 +use_otp_image=OtpTypeLcStRaw +chip_clock_source=ChipClockSourceE xternal48Mhz +rom_prod_mode=1 +use_jtag_dmi=1 +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_test_key_0:1:ot_flash_binary,mask_ro m:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=1794385683 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_raw_unlock_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_raw_unlock.1794385683 |
| Directory | /workspace/1.rom_raw_unlock/latest |
| Test location | /workspace/coverage/default/1.rom_volatile_raw_unlock.1218249743 |
| Short name | T1282 |
| Test name | |
| Test status | |
| Simulation time | 2217400113 ps |
| CPU time | 122.95 seconds |
| Started | Aug 12 07:22:25 PM PDT 24 |
| Finished | Aug 12 07:24:28 PM PDT 24 |
| Peak memory | 617852 kb |
| Host | smart-0fb81356-221f-49e5-a6e7-374e8cd51614 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=200_000_000 +use_otp_image=OtpTypeLcStRaw +chip_clock_source=ChipClockSourceExternal48Mhz +rom_prod_mode=1 +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_test_key_0:1:ot_flash_binary,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1218249743 -assert nopostproc +UVM_ TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_volatile_raw_unlock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag e/default.vdb -cm_log /dev/null -cm_name 1.rom_volatile_raw_unlock.1218249743 |
| Directory | /workspace/1.rom_volatile_raw_unlock/latest |
| Test location | /workspace/coverage/default/10.chip_sw_all_escalation_resets.4121623735 |
| Short name | T171 |
| Test name | |
| Test status | |
| Simulation time | 5050181474 ps |
| CPU time | 782.04 seconds |
| Started | Aug 12 07:34:11 PM PDT 24 |
| Finished | Aug 12 07:47:14 PM PDT 24 |
| Peak memory | 617312 kb |
| Host | smart-0482f6e9-2ab1-4d47-8207-4b862dd45138 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 4121623735 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.chip_sw_all_escalation_resets.4121623735 |
| Directory | /workspace/10.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/10.chip_sw_lc_ctrl_transition.2644172884 |
| Short name | T1071 |
| Test name | |
| Test status | |
| Simulation time | 10701160022 ps |
| CPU time | 1105.84 seconds |
| Started | Aug 12 07:34:25 PM PDT 24 |
| Finished | Aug 12 07:52:51 PM PDT 24 |
| Peak memory | 625144 kb |
| Host | smart-2b94311d-8014-4c7d-a17d-d705d3d97b6a |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=lc_ctrl_transition_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2644172884 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_transition_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau lt.vdb -cm_log /dev/null -cm_name 10.chip_sw_lc_ctrl_transition.2644172884 |
| Directory | /workspace/10.chip_sw_lc_ctrl_transition/latest |
| Test location | /workspace/coverage/default/10.chip_sw_uart_rand_baudrate.630797166 |
| Short name | T1109 |
| Test name | |
| Test status | |
| Simulation time | 13259040362 ps |
| CPU time | 2484.21 seconds |
| Started | Aug 12 07:33:48 PM PDT 24 |
| Finished | Aug 12 08:15:12 PM PDT 24 |
| Peak memory | 624972 kb |
| Host | smart-a4e17182-baaf-41c4-b7ae-18d48d82e2ab |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random _seed=630797166 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.chip_sw_uart_rand_baudrate.630797166 |
| Directory | /workspace/10.chip_sw_uart_rand_baudrate/latest |
| Test location | /workspace/coverage/default/11.chip_sw_all_escalation_resets.3269095989 |
| Short name | T841 |
| Test name | |
| Test status | |
| Simulation time | 5496297488 ps |
| CPU time | 605 seconds |
| Started | Aug 12 07:34:03 PM PDT 24 |
| Finished | Aug 12 07:44:08 PM PDT 24 |
| Peak memory | 650580 kb |
| Host | smart-1a53ad10-f4c0-4c2a-8c8a-455e45756348 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 3269095989 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.chip_sw_all_escalation_resets.3269095989 |
| Directory | /workspace/11.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/11.chip_sw_lc_ctrl_transition.2081969786 |
| Short name | T1162 |
| Test name | |
| Test status | |
| Simulation time | 11814563537 ps |
| CPU time | 954.56 seconds |
| Started | Aug 12 07:34:32 PM PDT 24 |
| Finished | Aug 12 07:50:28 PM PDT 24 |
| Peak memory | 622836 kb |
| Host | smart-d550c28d-da77-4595-bedb-5c80bb0d3816 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=lc_ctrl_transition_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2081969786 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_transition_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau lt.vdb -cm_log /dev/null -cm_name 11.chip_sw_lc_ctrl_transition.2081969786 |
| Directory | /workspace/11.chip_sw_lc_ctrl_transition/latest |
| Test location | /workspace/coverage/default/11.chip_sw_uart_rand_baudrate.3042532924 |
| Short name | T1182 |
| Test name | |
| Test status | |
| Simulation time | 4036736256 ps |
| CPU time | 438.91 seconds |
| Started | Aug 12 07:34:21 PM PDT 24 |
| Finished | Aug 12 07:41:41 PM PDT 24 |
| Peak memory | 622852 kb |
| Host | smart-ae4f1e16-ace3-4a21-b626-7b94b91a218e |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random _seed=3042532924 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.chip_sw_uart_rand_baudrate.3042532924 |
| Directory | /workspace/11.chip_sw_uart_rand_baudrate/latest |
| Test location | /workspace/coverage/default/12.chip_sw_lc_ctrl_transition.1053681000 |
| Short name | T1003 |
| Test name | |
| Test status | |
| Simulation time | 9736348492 ps |
| CPU time | 1118.24 seconds |
| Started | Aug 12 07:34:15 PM PDT 24 |
| Finished | Aug 12 07:52:53 PM PDT 24 |
| Peak memory | 621588 kb |
| Host | smart-10ea1b73-a670-4d67-b685-ea4011795d89 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=lc_ctrl_transition_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1053681000 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_transition_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau lt.vdb -cm_log /dev/null -cm_name 12.chip_sw_lc_ctrl_transition.1053681000 |
| Directory | /workspace/12.chip_sw_lc_ctrl_transition/latest |
| Test location | /workspace/coverage/default/12.chip_sw_uart_rand_baudrate.211947840 |
| Short name | T1008 |
| Test name | |
| Test status | |
| Simulation time | 4535897356 ps |
| CPU time | 588.46 seconds |
| Started | Aug 12 07:34:52 PM PDT 24 |
| Finished | Aug 12 07:44:41 PM PDT 24 |
| Peak memory | 624972 kb |
| Host | smart-ce5bc27c-a084-48de-9b04-5a2e8cf42320 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random _seed=211947840 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.chip_sw_uart_rand_baudrate.211947840 |
| Directory | /workspace/12.chip_sw_uart_rand_baudrate/latest |
| Test location | /workspace/coverage/default/13.chip_sw_lc_ctrl_transition.68896579 |
| Short name | T1131 |
| Test name | |
| Test status | |
| Simulation time | 7232155980 ps |
| CPU time | 475.59 seconds |
| Started | Aug 12 07:35:13 PM PDT 24 |
| Finished | Aug 12 07:43:09 PM PDT 24 |
| Peak memory | 622876 kb |
| Host | smart-e296bc62-9996-4f21-b4df-23d574f19581 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=lc_ctrl_transition_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=68896579 -assert nopostproc +UVM_TESTN AME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_transition_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default .vdb -cm_log /dev/null -cm_name 13.chip_sw_lc_ctrl_transition.68896579 |
| Directory | /workspace/13.chip_sw_lc_ctrl_transition/latest |
| Test location | /workspace/coverage/default/13.chip_sw_uart_rand_baudrate.1239607565 |
| Short name | T1379 |
| Test name | |
| Test status | |
| Simulation time | 4753269710 ps |
| CPU time | 699.34 seconds |
| Started | Aug 12 07:35:04 PM PDT 24 |
| Finished | Aug 12 07:46:44 PM PDT 24 |
| Peak memory | 624956 kb |
| Host | smart-16bf401c-4de1-4bd7-add3-88604cc47ec5 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random _seed=1239607565 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.chip_sw_uart_rand_baudrate.1239607565 |
| Directory | /workspace/13.chip_sw_uart_rand_baudrate/latest |
| Test location | /workspace/coverage/default/14.chip_sw_lc_ctrl_transition.2479210743 |
| Short name | T1059 |
| Test name | |
| Test status | |
| Simulation time | 12595348455 ps |
| CPU time | 944.48 seconds |
| Started | Aug 12 07:35:15 PM PDT 24 |
| Finished | Aug 12 07:51:00 PM PDT 24 |
| Peak memory | 621564 kb |
| Host | smart-6a368416-2a9d-40c8-bd39-adebfeb9b1aa |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=lc_ctrl_transition_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2479210743 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_transition_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau lt.vdb -cm_log /dev/null -cm_name 14.chip_sw_lc_ctrl_transition.2479210743 |
| Directory | /workspace/14.chip_sw_lc_ctrl_transition/latest |
| Test location | /workspace/coverage/default/14.chip_sw_uart_rand_baudrate.1302555621 |
| Short name | T1061 |
| Test name | |
| Test status | |
| Simulation time | 4314868280 ps |
| CPU time | 573.42 seconds |
| Started | Aug 12 07:35:55 PM PDT 24 |
| Finished | Aug 12 07:45:29 PM PDT 24 |
| Peak memory | 625196 kb |
| Host | smart-96cb9078-ead8-4190-9007-7eb722df35da |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random _seed=1302555621 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.chip_sw_uart_rand_baudrate.1302555621 |
| Directory | /workspace/14.chip_sw_uart_rand_baudrate/latest |
| Test location | /workspace/coverage/default/15.chip_sw_uart_rand_baudrate.522422733 |
| Short name | T359 |
| Test name | |
| Test status | |
| Simulation time | 9453983554 ps |
| CPU time | 1612.71 seconds |
| Started | Aug 12 07:34:59 PM PDT 24 |
| Finished | Aug 12 08:01:52 PM PDT 24 |
| Peak memory | 624980 kb |
| Host | smart-2af414e1-628b-48c2-b9d6-ce221cdd47d2 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random _seed=522422733 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.chip_sw_uart_rand_baudrate.522422733 |
| Directory | /workspace/15.chip_sw_uart_rand_baudrate/latest |
| Test location | /workspace/coverage/default/16.chip_sw_all_escalation_resets.221382246 |
| Short name | T811 |
| Test name | |
| Test status | |
| Simulation time | 4696555888 ps |
| CPU time | 784.04 seconds |
| Started | Aug 12 07:35:00 PM PDT 24 |
| Finished | Aug 12 07:48:04 PM PDT 24 |
| Peak memory | 650640 kb |
| Host | smart-6c98f0cf-9a57-4c4e-a21d-54ed8bc65e85 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 221382246 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.chip_sw_all_escalation_resets.221382246 |
| Directory | /workspace/16.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/16.chip_sw_uart_rand_baudrate.2736652860 |
| Short name | T221 |
| Test name | |
| Test status | |
| Simulation time | 8169574676 ps |
| CPU time | 1328.44 seconds |
| Started | Aug 12 07:35:03 PM PDT 24 |
| Finished | Aug 12 07:57:12 PM PDT 24 |
| Peak memory | 625000 kb |
| Host | smart-780b56e6-f746-499b-9ba4-133e2dac6acd |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random _seed=2736652860 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.chip_sw_uart_rand_baudrate.2736652860 |
| Directory | /workspace/16.chip_sw_uart_rand_baudrate/latest |
| Test location | /workspace/coverage/default/17.chip_sw_all_escalation_resets.280208058 |
| Short name | T93 |
| Test name | |
| Test status | |
| Simulation time | 4919575164 ps |
| CPU time | 648.67 seconds |
| Started | Aug 12 07:37:10 PM PDT 24 |
| Finished | Aug 12 07:47:59 PM PDT 24 |
| Peak memory | 650780 kb |
| Host | smart-2d07e147-f126-4207-84ee-68e683e71a71 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 280208058 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.chip_sw_all_escalation_resets.280208058 |
| Directory | /workspace/17.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/17.chip_sw_uart_rand_baudrate.87406435 |
| Short name | T1051 |
| Test name | |
| Test status | |
| Simulation time | 8682630928 ps |
| CPU time | 1548.65 seconds |
| Started | Aug 12 07:34:58 PM PDT 24 |
| Finished | Aug 12 08:00:48 PM PDT 24 |
| Peak memory | 623768 kb |
| Host | smart-2c038c3b-8e20-4f13-b1ab-306020105070 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random _seed=87406435 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.chip_sw_uart_rand_baudrate.87406435 |
| Directory | /workspace/17.chip_sw_uart_rand_baudrate/latest |
| Test location | /workspace/coverage/default/18.chip_sw_alert_handler_lpg_sleep_mode_alerts.1412368083 |
| Short name | T817 |
| Test name | |
| Test status | |
| Simulation time | 3840659314 ps |
| CPU time | 477.64 seconds |
| Started | Aug 12 07:34:52 PM PDT 24 |
| Finished | Aug 12 07:42:50 PM PDT 24 |
| Peak memory | 649336 kb |
| Host | smart-74424bdb-40e9-41ec-b082-160a424df4d6 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1412368083 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.chip_ sw_alert_handler_lpg_sleep_mode_alerts.1412368083 |
| Directory | /workspace/18.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/18.chip_sw_uart_rand_baudrate.2239322661 |
| Short name | T1239 |
| Test name | |
| Test status | |
| Simulation time | 8585220120 ps |
| CPU time | 1542.28 seconds |
| Started | Aug 12 07:38:58 PM PDT 24 |
| Finished | Aug 12 08:04:41 PM PDT 24 |
| Peak memory | 624960 kb |
| Host | smart-dc90dbe3-e89e-4d56-a938-8265f1221f1f |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random _seed=2239322661 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.chip_sw_uart_rand_baudrate.2239322661 |
| Directory | /workspace/18.chip_sw_uart_rand_baudrate/latest |
| Test location | /workspace/coverage/default/19.chip_sw_alert_handler_lpg_sleep_mode_alerts.2290230740 |
| Short name | T846 |
| Test name | |
| Test status | |
| Simulation time | 3361491200 ps |
| CPU time | 392.32 seconds |
| Started | Aug 12 07:37:33 PM PDT 24 |
| Finished | Aug 12 07:44:05 PM PDT 24 |
| Peak memory | 649116 kb |
| Host | smart-8ed7f184-7425-48bd-b225-1509266513f4 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2290230740 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.chip_ sw_alert_handler_lpg_sleep_mode_alerts.2290230740 |
| Directory | /workspace/19.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/19.chip_sw_uart_rand_baudrate.1636502530 |
| Short name | T224 |
| Test name | |
| Test status | |
| Simulation time | 3402524788 ps |
| CPU time | 585.86 seconds |
| Started | Aug 12 07:36:05 PM PDT 24 |
| Finished | Aug 12 07:45:52 PM PDT 24 |
| Peak memory | 624920 kb |
| Host | smart-6245e1e8-727d-4d17-adf3-a8ea911f31bb |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random _seed=1636502530 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.chip_sw_uart_rand_baudrate.1636502530 |
| Directory | /workspace/19.chip_sw_uart_rand_baudrate/latest |
| Test location | /workspace/coverage/default/2.chip_jtag_csr_rw.2344203753 |
| Short name | T82 |
| Test name | |
| Test status | |
| Simulation time | 10641127888 ps |
| CPU time | 1502.66 seconds |
| Started | Aug 12 07:21:06 PM PDT 24 |
| Finished | Aug 12 07:46:09 PM PDT 24 |
| Peak memory | 608276 kb |
| Host | smart-da681de3-4df2-42ff-bc15-f47c1eaa15f4 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +csr_rw +create_jtag_riscv_map=1 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2344203753 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_T EST_SEQ=chip_jtag_csr_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.c hip_jtag_csr_rw.2344203753 |
| Directory | /workspace/2.chip_jtag_csr_rw/latest |
| Test location | /workspace/coverage/default/2.chip_jtag_mem_access.415506481 |
| Short name | T209 |
| Test name | |
| Test status | |
| Simulation time | 13497979475 ps |
| CPU time | 1333.59 seconds |
| Started | Aug 12 07:21:12 PM PDT 24 |
| Finished | Aug 12 07:43:26 PM PDT 24 |
| Peak memory | 608244 kb |
| Host | smart-ccdd4bff-a1ec-4ae1-a1f8-7adb8a1d49f7 |
| User | root |
| Command | /workspace/default/simv +create_jtag_riscv_map=1 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=415506481 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_jtag_m em_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_jtag_mem_access.415506481 |
| Directory | /workspace/2.chip_jtag_mem_access/latest |
| Test location | /workspace/coverage/default/2.chip_rv_dm_ndm_reset_req.3553312366 |
| Short name | T115 |
| Test name | |
| Test status | |
| Simulation time | 4300973544 ps |
| CPU time | 351.39 seconds |
| Started | Aug 12 07:28:51 PM PDT 24 |
| Finished | Aug 12 07:34:43 PM PDT 24 |
| Peak memory | 620128 kb |
| Host | smart-fb2f29bb-8501-423a-b387-62e9347da815 |
| User | root |
| Command | /workspace/default/simv +en_scb_tl_err_chk=0 +use_jtag_dmi=1 +sw_build_device=sim_dv +sw_images=rv_dm_ndm_reset_req_rma:1:new_rules,test_rom:0 +cdc_in strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3 553312366 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_rv_dm_ndm_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_rv_dm_ndm_reset_req.3553312366 |
| Directory | /workspace/2.chip_rv_dm_ndm_reset_req/latest |
| Test location | /workspace/coverage/default/2.chip_sival_flash_info_access.933198389 |
| Short name | T357 |
| Test name | |
| Test status | |
| Simulation time | 2345584428 ps |
| CPU time | 270.82 seconds |
| Started | Aug 12 07:26:58 PM PDT 24 |
| Finished | Aug 12 07:31:29 PM PDT 24 |
| Peak memory | 609120 kb |
| Host | smart-fc5ac6fc-fa80-4cec-acc8-c7f9fa9f6396 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStTestUnlocked0 +sw_build_device=sim_dv +sw_images=flash_ctrl_info_access_lc:1:new_rules,test_rom:0 +c dc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_s eed=933198389 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sival_flash_info_access.933198389 |
| Directory | /workspace/2.chip_sival_flash_info_access/latest |
| Test location | /workspace/coverage/default/2.chip_sw_adc_ctrl_sleep_debug_cable_wakeup.337848380 |
| Short name | T1313 |
| Test name | |
| Test status | |
| Simulation time | 19794443608 ps |
| CPU time | 608.49 seconds |
| Started | Aug 12 07:25:35 PM PDT 24 |
| Finished | Aug 12 07:35:44 PM PDT 24 |
| Peak memory | 620096 kb |
| Host | smart-3394a372-acda-4750-81ba-309b3636ad18 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=adc_ctrl_sleep_debug_cable_wakeup_test:1:new_rules,test_rom: 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand om_seed=337848380 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_adc_ctrl_sleep_debug_cable_wakeup_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_adc_ctrl_sleep_debug_cable_wakeup.337848380 |
| Directory | /workspace/2.chip_sw_adc_ctrl_sleep_debug_cable_wakeup/latest |
| Test location | /workspace/coverage/default/2.chip_sw_aes_enc.1129437138 |
| Short name | T1396 |
| Test name | |
| Test status | |
| Simulation time | 2514500952 ps |
| CPU time | 254.03 seconds |
| Started | Aug 12 07:27:08 PM PDT 24 |
| Finished | Aug 12 07:31:23 PM PDT 24 |
| Peak memory | 609808 kb |
| Host | smart-0d612c8f-efeb-4815-b883-97d46f807d05 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=22_000_000 +sw_build_device=sim_dv +sw_images=aes_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1129437138 -asser t nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag e/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_aes_enc.1129437138 |
| Directory | /workspace/2.chip_sw_aes_enc/latest |
| Test location | /workspace/coverage/default/2.chip_sw_aes_enc_jitter_en.736205875 |
| Short name | T1168 |
| Test name | |
| Test status | |
| Simulation time | 3202667743 ps |
| CPU time | 292.15 seconds |
| Started | Aug 12 07:26:59 PM PDT 24 |
| Finished | Aug 12 07:31:52 PM PDT 24 |
| Peak memory | 610076 kb |
| Host | smart-8abb948c-f462-4297-8943-2809af1f0369 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=26_000_000 +en_jitter=1 +sw_build_device=sim_dv +sw_images=aes_smoketest:1:new_rules,test_rom:0 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=7362 05875 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_aes_enc_jitter_en.736205875 |
| Directory | /workspace/2.chip_sw_aes_enc_jitter_en/latest |
| Test location | /workspace/coverage/default/2.chip_sw_aes_enc_jitter_en_reduced_freq.701223868 |
| Short name | T447 |
| Test name | |
| Test status | |
| Simulation time | 2803948987 ps |
| CPU time | 258.15 seconds |
| Started | Aug 12 07:28:48 PM PDT 24 |
| Finished | Aug 12 07:33:06 PM PDT 24 |
| Peak memory | 610104 kb |
| Host | smart-e05dc4ab-99c4-4d76-9945-962148d555cf |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=26_000_000 +en_jitter=1 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=aes_smoketest:1:new_rules, test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=701223868 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_aes_enc_jitter_en_reduced_freq.701223868 |
| Directory | /workspace/2.chip_sw_aes_enc_jitter_en_reduced_freq/latest |
| Test location | /workspace/coverage/default/2.chip_sw_aes_entropy.2631513817 |
| Short name | T1185 |
| Test name | |
| Test status | |
| Simulation time | 3073729538 ps |
| CPU time | 219.3 seconds |
| Started | Aug 12 07:26:40 PM PDT 24 |
| Finished | Aug 12 07:30:19 PM PDT 24 |
| Peak memory | 610136 kb |
| Host | smart-b3b06ecb-fe6e-47db-b164-addb69a61ec9 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=15_000_000 +sw_build_device=sim_dv +sw_images=aes_entropy_test:1:new_rules,test_rom:0 +cdc_instrumentation _enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2631513817 -as sert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove rage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_aes_entropy.2631513817 |
| Directory | /workspace/2.chip_sw_aes_entropy/latest |
| Test location | /workspace/coverage/default/2.chip_sw_aes_idle.1224240693 |
| Short name | T1056 |
| Test name | |
| Test status | |
| Simulation time | 2651770316 ps |
| CPU time | 337.55 seconds |
| Started | Aug 12 07:26:20 PM PDT 24 |
| Finished | Aug 12 07:31:58 PM PDT 24 |
| Peak memory | 610092 kb |
| Host | smart-271e507c-ddb8-4600-a2a7-805949b9c326 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=25_000_000 +sw_build_device=sim_dv +sw_images=aes_idle_test:1:new_rules,test_rom:0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1224240693 -asser t nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag e/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_aes_idle.1224240693 |
| Directory | /workspace/2.chip_sw_aes_idle/latest |
| Test location | /workspace/coverage/default/2.chip_sw_aes_masking_off.3125828568 |
| Short name | T1312 |
| Test name | |
| Test status | |
| Simulation time | 2761064166 ps |
| CPU time | 275.46 seconds |
| Started | Aug 12 07:25:50 PM PDT 24 |
| Finished | Aug 12 07:30:26 PM PDT 24 |
| Peak memory | 609776 kb |
| Host | smart-abe1b2a3-3d4e-4233-9e76-29e437d4184c |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=aes_masking_off_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3125828568 -assert nopostproc +UVM_TESTNA ME=chip_base_test +UVM_TEST_SEQ=chip_sw_aes_masking_off_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_aes_masking_off.3125828568 |
| Directory | /workspace/2.chip_sw_aes_masking_off/latest |
| Test location | /workspace/coverage/default/2.chip_sw_aes_smoketest.2792956551 |
| Short name | T1245 |
| Test name | |
| Test status | |
| Simulation time | 3212907700 ps |
| CPU time | 307.79 seconds |
| Started | Aug 12 07:29:44 PM PDT 24 |
| Finished | Aug 12 07:34:52 PM PDT 24 |
| Peak memory | 609708 kb |
| Host | smart-60a49dc1-1f69-4969-8173-90bda60dcc3d |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=aes_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2792956551 -assert nopostproc +UVM_TESTNAME=chip _base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_aes_smoketest.2792956551 |
| Directory | /workspace/2.chip_sw_aes_smoketest/latest |
| Test location | /workspace/coverage/default/2.chip_sw_alert_handler_entropy.3943440520 |
| Short name | T170 |
| Test name | |
| Test status | |
| Simulation time | 3358244135 ps |
| CPU time | 402.87 seconds |
| Started | Aug 12 07:26:26 PM PDT 24 |
| Finished | Aug 12 07:33:10 PM PDT 24 |
| Peak memory | 610096 kb |
| Host | smart-6148a8ea-d0c2-4255-93b3-f635d2178be9 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=alert_handler_entropy_test:1:new_rules,test_ro m:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=3943440520 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_alert_handler_entropy.3943440520 |
| Directory | /workspace/2.chip_sw_alert_handler_entropy/latest |
| Test location | /workspace/coverage/default/2.chip_sw_alert_handler_escalation.1109806612 |
| Short name | T1127 |
| Test name | |
| Test status | |
| Simulation time | 5091247330 ps |
| CPU time | 543.55 seconds |
| Started | Aug 12 07:27:09 PM PDT 24 |
| Finished | Aug 12 07:36:13 PM PDT 24 |
| Peak memory | 620036 kb |
| Host | smart-99765097-f4d8-438e-a82b-bee8848d8256 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=alert_handler_escalation_test:1:new_rules,test _rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb _random_seed=1109806612 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_alert_handler_escalation_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_alert_handler_escalation.1109806612 |
| Directory | /workspace/2.chip_sw_alert_handler_escalation/latest |
| Test location | /workspace/coverage/default/2.chip_sw_alert_handler_lpg_clkoff.964791681 |
| Short name | T1180 |
| Test name | |
| Test status | |
| Simulation time | 5757884962 ps |
| CPU time | 866.62 seconds |
| Started | Aug 12 07:31:14 PM PDT 24 |
| Finished | Aug 12 07:45:41 PM PDT 24 |
| Peak memory | 610636 kb |
| Host | smart-f20bdffc-9591-47c9-87ab-16ad192e0ca7 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +sw_build_device=sim_dv +sw_images=alert_handler_lpg_clkoff_test:1:new_rules,test_r om:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r andom_seed=964791681 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_alert_handler_lpg_clkoff_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_alert_handler_lpg_clkoff.964791681 |
| Directory | /workspace/2.chip_sw_alert_handler_lpg_clkoff/latest |
| Test location | /workspace/coverage/default/2.chip_sw_alert_handler_lpg_reset_toggle.940797427 |
| Short name | T220 |
| Test name | |
| Test status | |
| Simulation time | 6553779388 ps |
| CPU time | 1376.19 seconds |
| Started | Aug 12 07:28:50 PM PDT 24 |
| Finished | Aug 12 07:51:46 PM PDT 24 |
| Peak memory | 610420 kb |
| Host | smart-b6154fc4-a25e-4cf8-8f07-18556ae96011 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +sw_build_device=sim_dv +sw_images=alert_handler_lpg_reset_toggle_test:1:new_rules, test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=940797427 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_alert_handler_shorten_ping_wait_cycle_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_alert_handler_lpg_reset_toggle.940797427 |
| Directory | /workspace/2.chip_sw_alert_handler_lpg_reset_toggle/latest |
| Test location | /workspace/coverage/default/2.chip_sw_alert_handler_lpg_sleep_mode_pings.145544820 |
| Short name | T1325 |
| Test name | |
| Test status | |
| Simulation time | 11368410584 ps |
| CPU time | 1167.35 seconds |
| Started | Aug 12 07:27:22 PM PDT 24 |
| Finished | Aug 12 07:46:49 PM PDT 24 |
| Peak memory | 611324 kb |
| Host | smart-ae28cedd-fcf3-4c04-ad48-d76352539b09 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=alert_handler _lpg_sleep_mode_pings_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=145544820 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_alert_hand ler_shorten_ping_wait_cycle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_alert_handler_lpg_sleep_mode_pings.145544820 |
| Directory | /workspace/2.chip_sw_alert_handler_lpg_sleep_mode_pings/latest |
| Test location | /workspace/coverage/default/2.chip_sw_alert_handler_ping_ok.2687912303 |
| Short name | T329 |
| Test name | |
| Test status | |
| Simulation time | 7937848732 ps |
| CPU time | 1694.5 seconds |
| Started | Aug 12 07:27:05 PM PDT 24 |
| Finished | Aug 12 07:55:20 PM PDT 24 |
| Peak memory | 610220 kb |
| Host | smart-1bde137d-3d6d-4c64-827d-873f7c254944 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=24000000 +sw_build_device=sim_dv +sw_images=alert_handler_ping_ok_test:1:new_rules,test_rom:0 +c dc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_s eed=2687912303 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_alert_handler_ping_ok.2687912303 |
| Directory | /workspace/2.chip_sw_alert_handler_ping_ok/latest |
| Test location | /workspace/coverage/default/2.chip_sw_alert_handler_ping_timeout.616120758 |
| Short name | T790 |
| Test name | |
| Test status | |
| Simulation time | 3776349666 ps |
| CPU time | 490.78 seconds |
| Started | Aug 12 07:26:49 PM PDT 24 |
| Finished | Aug 12 07:35:00 PM PDT 24 |
| Peak memory | 610204 kb |
| Host | smart-e4e29d04-646e-47ea-babb-cbc51616f94c |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=24000000 +sw_build_device=sim_dv +sw_images=alert_handler_ping_timeout_test:1:new_rules,test_rom :0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=616120758 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_alert_handler_ping_timeout.616120758 |
| Directory | /workspace/2.chip_sw_alert_handler_ping_timeout/latest |
| Test location | /workspace/coverage/default/2.chip_sw_alert_handler_reverse_ping_in_deep_sleep.3962616748 |
| Short name | T1416 |
| Test name | |
| Test status | |
| Simulation time | 255356788230 ps |
| CPU time | 13273.4 seconds |
| Started | Aug 12 07:27:14 PM PDT 24 |
| Finished | Aug 12 11:08:29 PM PDT 24 |
| Peak memory | 611280 kb |
| Host | smart-afc3fb45-4e78-40ab-b646-d5c508a1eec1 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=300_000_000 +sw_build_device=sim_dv +sw_images=alert_handler_reverse_ping_in_deep_sleep_test:1:n ew_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3962616748 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_alert_handler_reverse_ping_in_deep_sleep.3962616748 |
| Directory | /workspace/2.chip_sw_alert_handler_reverse_ping_in_deep_sleep/latest |
| Test location | /workspace/coverage/default/2.chip_sw_alert_test.2391775131 |
| Short name | T59 |
| Test name | |
| Test status | |
| Simulation time | 3004637454 ps |
| CPU time | 337.68 seconds |
| Started | Aug 12 07:26:16 PM PDT 24 |
| Finished | Aug 12 07:31:54 PM PDT 24 |
| Peak memory | 610392 kb |
| Host | smart-295ef2c1-4fbc-4837-aed1-08ef2a3bb7c9 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=alert_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2391775131 -assert nopostproc +UVM_TESTNAME=chip_ba se_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 2.chip_sw_alert_test.2391775131 |
| Directory | /workspace/2.chip_sw_alert_test/latest |
| Test location | /workspace/coverage/default/2.chip_sw_aon_timer_irq.3586948847 |
| Short name | T1038 |
| Test name | |
| Test status | |
| Simulation time | 4441481874 ps |
| CPU time | 402.29 seconds |
| Started | Aug 12 07:28:07 PM PDT 24 |
| Finished | Aug 12 07:34:49 PM PDT 24 |
| Peak memory | 609684 kb |
| Host | smart-415fe70e-89b0-46bd-b87e-604b1bc6b027 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=aon_timer_irq_test:1:new_rules,test_rom:0 +cdc_instrumentati on_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3586948847 - assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co verage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_aon_timer_irq.3586948847 |
| Directory | /workspace/2.chip_sw_aon_timer_irq/latest |
| Test location | /workspace/coverage/default/2.chip_sw_aon_timer_sleep_wdog_sleep_pause.66834440 |
| Short name | T995 |
| Test name | |
| Test status | |
| Simulation time | 7264261096 ps |
| CPU time | 430.27 seconds |
| Started | Aug 12 07:26:10 PM PDT 24 |
| Finished | Aug 12 07:33:21 PM PDT 24 |
| Peak memory | 609724 kb |
| Host | smart-53979556-1300-4264-bce4-2301a49fa1de |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=aon_timer_sleep_wdog_sleep_pause_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=66834440 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_aon_timer_sleep_wdog_sleep_pause.66834440 |
| Directory | /workspace/2.chip_sw_aon_timer_sleep_wdog_sleep_pause/latest |
| Test location | /workspace/coverage/default/2.chip_sw_aon_timer_smoketest.2371848115 |
| Short name | T1384 |
| Test name | |
| Test status | |
| Simulation time | 3119707670 ps |
| CPU time | 368.33 seconds |
| Started | Aug 12 07:32:51 PM PDT 24 |
| Finished | Aug 12 07:39:00 PM PDT 24 |
| Peak memory | 609800 kb |
| Host | smart-fc4b7003-d8e2-43bb-99e6-14494dcfefa4 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=aon_timer_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2371848115 -assert nopostproc +UVM_TESTNAM E=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 2.chip_sw_aon_timer_smoketest.2371848115 |
| Directory | /workspace/2.chip_sw_aon_timer_smoketest/latest |
| Test location | /workspace/coverage/default/2.chip_sw_aon_timer_wdog_bite_reset.2182690068 |
| Short name | T978 |
| Test name | |
| Test status | |
| Simulation time | 10001093864 ps |
| CPU time | 1065.45 seconds |
| Started | Aug 12 07:25:01 PM PDT 24 |
| Finished | Aug 12 07:42:47 PM PDT 24 |
| Peak memory | 610648 kb |
| Host | smart-875895a0-3f06-44a7-97cf-f06038a94155 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=aon_timer_wdog_bite_reset_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 2182690068 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_aon_timer_wdog_bite_reset.2182690068 |
| Directory | /workspace/2.chip_sw_aon_timer_wdog_bite_reset/latest |
| Test location | /workspace/coverage/default/2.chip_sw_aon_timer_wdog_lc_escalate.3512969928 |
| Short name | T1202 |
| Test name | |
| Test status | |
| Simulation time | 4457438954 ps |
| CPU time | 594.71 seconds |
| Started | Aug 12 07:26:57 PM PDT 24 |
| Finished | Aug 12 07:36:52 PM PDT 24 |
| Peak memory | 611104 kb |
| Host | smart-003e6795-9ea7-4524-9d86-e0b36a6e32f6 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=aon_timer_wdog_lc_escalate_test:1:new_rules,test_rom:0 +cdc_ instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed =3512969928 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_aon_timer_wdog_lc_escalate.3512969928 |
| Directory | /workspace/2.chip_sw_aon_timer_wdog_lc_escalate/latest |
| Test location | /workspace/coverage/default/2.chip_sw_ast_clk_outputs.3246680018 |
| Short name | T1057 |
| Test name | |
| Test status | |
| Simulation time | 8480845308 ps |
| CPU time | 1142.11 seconds |
| Started | Aug 12 07:29:00 PM PDT 24 |
| Finished | Aug 12 07:48:03 PM PDT 24 |
| Peak memory | 616748 kb |
| Host | smart-9e411897-452d-4db7-af12-11d7db2e9492 |
| User | root |
| Command | /workspace/default/simv +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=ast_clk_outs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled= 1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3246680018 -assert nopo stproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_ast_clk_outputs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co verage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_ast_clk_outputs.3246680018 |
| Directory | /workspace/2.chip_sw_ast_clk_outputs/latest |
| Test location | /workspace/coverage/default/2.chip_sw_ast_clk_rst_inputs.2545246231 |
| Short name | T153 |
| Test name | |
| Test status | |
| Simulation time | 16334346526 ps |
| CPU time | 1640.65 seconds |
| Started | Aug 12 07:30:35 PM PDT 24 |
| Finished | Aug 12 07:57:57 PM PDT 24 |
| Peak memory | 611516 kb |
| Host | smart-5eb75e97-b5fa-40da-aa70-2286d22f9196 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=200_000_000 +sw_build_device=sim_dv +sw_images=ast_clk_rst_inputs:1:new_rules,test_rom:0 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2545246231 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_ast_clk_rst_inputs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_ast_clk_rst_inputs.2545246231 |
| Directory | /workspace/2.chip_sw_ast_clk_rst_inputs/latest |
| Test location | /workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_lc.1760662928 |
| Short name | T1314 |
| Test name | |
| Test status | |
| Simulation time | 12210660837 ps |
| CPU time | 706.54 seconds |
| Started | Aug 12 07:28:36 PM PDT 24 |
| Finished | Aug 12 07:40:23 PM PDT 24 |
| Peak memory | 620884 kb |
| Host | smart-6e0a778e-5c81-4763-85c4-8da992108b07 |
| User | root |
| Command | /workspace/default/simv +chip_clock_source=ChipClockSourceExternal48Mhz +sw_build_device=sim_dv +sw_images=clkmgr_external_clk_src_for_lc_test:1:new_r ules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim .tcl +ntb_random_seed=1760662928 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_transition_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_clkmgr_external_clk_src_for_lc.1760662928 |
| Directory | /workspace/2.chip_sw_clkmgr_external_clk_src_for_lc/latest |
| Test location | /workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_fast_dev.2404504959 |
| Short name | T1289 |
| Test name | |
| Test status | |
| Simulation time | 3859095768 ps |
| CPU time | 702.87 seconds |
| Started | Aug 12 07:27:42 PM PDT 24 |
| Finished | Aug 12 07:39:25 PM PDT 24 |
| Peak memory | 612472 kb |
| Host | smart-6907da7c-f5bf-4f84-afa8-566fa6a6a4e9 |
| User | root |
| Command | /workspace/default/simv +chip_clock_source=ChipClockSourceExternal96Mhz +calibrate_usb_clk=1 +src_dec_state=DecLcStDev +sw_build_device=sim_dv +sw_ima ges=clkmgr_external_clk_src_for_sw_fast_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2404504959 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ =chip_sw_lc_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_c lkmgr_external_clk_src_for_sw_fast_dev.2404504959 |
| Directory | /workspace/2.chip_sw_clkmgr_external_clk_src_for_sw_fast_dev/latest |
| Test location | /workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_fast_rma.528106856 |
| Short name | T1352 |
| Test name | |
| Test status | |
| Simulation time | 4265250402 ps |
| CPU time | 681.48 seconds |
| Started | Aug 12 07:30:07 PM PDT 24 |
| Finished | Aug 12 07:41:29 PM PDT 24 |
| Peak memory | 613328 kb |
| Host | smart-1702dfa8-d9f1-4568-8fa6-9f7082754d05 |
| User | root |
| Command | /workspace/default/simv +chip_clock_source=ChipClockSourceExternal96Mhz +calibrate_usb_clk=1 +src_dec_state=DecLcStRma +sw_build_device=sim_dv +sw_ima ges=clkmgr_external_clk_src_for_sw_fast_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=528106856 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ= chip_sw_lc_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_cl kmgr_external_clk_src_for_sw_fast_rma.528106856 |
| Directory | /workspace/2.chip_sw_clkmgr_external_clk_src_for_sw_fast_rma/latest |
| Test location | /workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0.1720846569 |
| Short name | T1262 |
| Test name | |
| Test status | |
| Simulation time | 4424450898 ps |
| CPU time | 870.71 seconds |
| Started | Aug 12 07:27:30 PM PDT 24 |
| Finished | Aug 12 07:42:01 PM PDT 24 |
| Peak memory | 612612 kb |
| Host | smart-fb62def3-b27b-48fd-b770-c1ff36deab15 |
| User | root |
| Command | /workspace/default/simv +chip_clock_source=ChipClockSourceExternal96Mhz +calibrate_usb_clk=1 +src_dec_state=DecLcStTestUnlocked0 +sw_build_device=sim_ dv +sw_images=clkmgr_external_clk_src_for_sw_fast_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1720846569 -assert nopostproc +UVM_TESTNAME=chip_base_test +UV M_TEST_SEQ=chip_sw_lc_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2 .chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0.1720846569 |
| Directory | /workspace/2.chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0/latest |
| Test location | /workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_slow_dev.931593981 |
| Short name | T1326 |
| Test name | |
| Test status | |
| Simulation time | 5327874700 ps |
| CPU time | 578 seconds |
| Started | Aug 12 07:28:45 PM PDT 24 |
| Finished | Aug 12 07:38:23 PM PDT 24 |
| Peak memory | 612544 kb |
| Host | smart-9c88c568-dff6-48f1-8b30-5197f98fe491 |
| User | root |
| Command | /workspace/default/simv +chip_clock_source=ChipClockSourceExternal48Mhz +calibrate_usb_clk=1 +src_dec_state=DecLcStDev +sw_build_device=sim_dv +sw_ima ges=clkmgr_external_clk_src_for_sw_slow_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=931593981 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ= chip_sw_lc_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_cl kmgr_external_clk_src_for_sw_slow_dev.931593981 |
| Directory | /workspace/2.chip_sw_clkmgr_external_clk_src_for_sw_slow_dev/latest |
| Test location | /workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_slow_rma.2756436136 |
| Short name | T129 |
| Test name | |
| Test status | |
| Simulation time | 4483704990 ps |
| CPU time | 647.3 seconds |
| Started | Aug 12 07:28:44 PM PDT 24 |
| Finished | Aug 12 07:39:31 PM PDT 24 |
| Peak memory | 612528 kb |
| Host | smart-5a39d80c-405c-4806-94b6-d73b1ef78b4e |
| User | root |
| Command | /workspace/default/simv +chip_clock_source=ChipClockSourceExternal48Mhz +calibrate_usb_clk=1 +src_dec_state=DecLcStRma +sw_build_device=sim_dv +sw_ima ges=clkmgr_external_clk_src_for_sw_slow_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2756436136 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ =chip_sw_lc_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_c lkmgr_external_clk_src_for_sw_slow_rma.2756436136 |
| Directory | /workspace/2.chip_sw_clkmgr_external_clk_src_for_sw_slow_rma/latest |
| Test location | /workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0.2747532179 |
| Short name | T1058 |
| Test name | |
| Test status | |
| Simulation time | 4514507480 ps |
| CPU time | 651.02 seconds |
| Started | Aug 12 07:28:01 PM PDT 24 |
| Finished | Aug 12 07:38:53 PM PDT 24 |
| Peak memory | 612608 kb |
| Host | smart-d65300a9-d1ab-450c-94b1-bbd6f4afad44 |
| User | root |
| Command | /workspace/default/simv +chip_clock_source=ChipClockSourceExternal48Mhz +calibrate_usb_clk=1 +src_dec_state=DecLcStTestUnlocked0 +sw_build_device=sim_ dv +sw_images=clkmgr_external_clk_src_for_sw_slow_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2747532179 -assert nopostproc +UVM_TESTNAME=chip_base_test +UV M_TEST_SEQ=chip_sw_lc_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2 .chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0.2747532179 |
| Directory | /workspace/2.chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0/latest |
| Test location | /workspace/coverage/default/2.chip_sw_clkmgr_jitter.1105701401 |
| Short name | T1274 |
| Test name | |
| Test status | |
| Simulation time | 2193071826 ps |
| CPU time | 231.88 seconds |
| Started | Aug 12 07:28:56 PM PDT 24 |
| Finished | Aug 12 07:32:48 PM PDT 24 |
| Peak memory | 610052 kb |
| Host | smart-631caa1c-4e11-4f6a-9967-4852e9bf1843 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=clkmgr_jitter_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1105701401 -assert nopostproc +UVM_TESTNAME =chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 2.chip_sw_clkmgr_jitter.1105701401 |
| Directory | /workspace/2.chip_sw_clkmgr_jitter/latest |
| Test location | /workspace/coverage/default/2.chip_sw_clkmgr_jitter_frequency.2688862344 |
| Short name | T1010 |
| Test name | |
| Test status | |
| Simulation time | 3244702904 ps |
| CPU time | 501.75 seconds |
| Started | Aug 12 07:28:38 PM PDT 24 |
| Finished | Aug 12 07:37:00 PM PDT 24 |
| Peak memory | 609736 kb |
| Host | smart-258308b0-61a9-420f-8489-d47712b9ddb9 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=clkmgr_jitter_frequency_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2688862344 -assert nopostproc +UV M_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -c m_log /dev/null -cm_name 2.chip_sw_clkmgr_jitter_frequency.2688862344 |
| Directory | /workspace/2.chip_sw_clkmgr_jitter_frequency/latest |
| Test location | /workspace/coverage/default/2.chip_sw_clkmgr_jitter_reduced_freq.2105313252 |
| Short name | T1397 |
| Test name | |
| Test status | |
| Simulation time | 2718406217 ps |
| CPU time | 204.89 seconds |
| Started | Aug 12 07:29:57 PM PDT 24 |
| Finished | Aug 12 07:33:22 PM PDT 24 |
| Peak memory | 610004 kb |
| Host | smart-9f6131f4-3403-4c16-83c2-4c4f26fc80b8 |
| User | root |
| Command | /workspace/default/simv +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=clkmgr_jitter_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2105313252 -assert nop ostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def ault.vdb -cm_log /dev/null -cm_name 2.chip_sw_clkmgr_jitter_reduced_freq.2105313252 |
| Directory | /workspace/2.chip_sw_clkmgr_jitter_reduced_freq/latest |
| Test location | /workspace/coverage/default/2.chip_sw_clkmgr_off_aes_trans.3404093389 |
| Short name | T1228 |
| Test name | |
| Test status | |
| Simulation time | 5973514300 ps |
| CPU time | 656.58 seconds |
| Started | Aug 12 07:32:33 PM PDT 24 |
| Finished | Aug 12 07:43:31 PM PDT 24 |
| Peak memory | 610884 kb |
| Host | smart-21e07aee-de65-4685-864b-2b6960871dc8 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=clkmgr_off_aes_trans_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3404093389 -assert nopostproc +UVM_T ESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l og /dev/null -cm_name 2.chip_sw_clkmgr_off_aes_trans.3404093389 |
| Directory | /workspace/2.chip_sw_clkmgr_off_aes_trans/latest |
| Test location | /workspace/coverage/default/2.chip_sw_clkmgr_off_hmac_trans.2070994509 |
| Short name | T1050 |
| Test name | |
| Test status | |
| Simulation time | 4873574080 ps |
| CPU time | 498.15 seconds |
| Started | Aug 12 07:32:17 PM PDT 24 |
| Finished | Aug 12 07:40:37 PM PDT 24 |
| Peak memory | 610524 kb |
| Host | smart-9b731386-5fcf-4b9e-a1cb-19c07ea8f303 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=clkmgr_off_hmac_trans_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2070994509 -assert nopostproc +UVM_ TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_ log /dev/null -cm_name 2.chip_sw_clkmgr_off_hmac_trans.2070994509 |
| Directory | /workspace/2.chip_sw_clkmgr_off_hmac_trans/latest |
| Test location | /workspace/coverage/default/2.chip_sw_clkmgr_off_kmac_trans.3934517374 |
| Short name | T1217 |
| Test name | |
| Test status | |
| Simulation time | 4393587910 ps |
| CPU time | 623.23 seconds |
| Started | Aug 12 07:28:39 PM PDT 24 |
| Finished | Aug 12 07:39:03 PM PDT 24 |
| Peak memory | 610572 kb |
| Host | smart-08900121-e00c-4502-bf65-7d8ae9b60c84 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=clkmgr_off_kmac_trans_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3934517374 -assert nopostproc +UVM_ TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_ log /dev/null -cm_name 2.chip_sw_clkmgr_off_kmac_trans.3934517374 |
| Directory | /workspace/2.chip_sw_clkmgr_off_kmac_trans/latest |
| Test location | /workspace/coverage/default/2.chip_sw_clkmgr_off_otbn_trans.3821553672 |
| Short name | T1229 |
| Test name | |
| Test status | |
| Simulation time | 4099200976 ps |
| CPU time | 685.23 seconds |
| Started | Aug 12 07:27:33 PM PDT 24 |
| Finished | Aug 12 07:38:59 PM PDT 24 |
| Peak memory | 609812 kb |
| Host | smart-f03bc23c-9acd-4974-a6cc-0ea8d998e590 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=clkmgr_off_otbn_trans_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3821553672 -assert nopostproc +UVM_ TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_ log /dev/null -cm_name 2.chip_sw_clkmgr_off_otbn_trans.3821553672 |
| Directory | /workspace/2.chip_sw_clkmgr_off_otbn_trans/latest |
| Test location | /workspace/coverage/default/2.chip_sw_clkmgr_off_peri.3206897048 |
| Short name | T1119 |
| Test name | |
| Test status | |
| Simulation time | 9705920748 ps |
| CPU time | 1104.29 seconds |
| Started | Aug 12 07:32:31 PM PDT 24 |
| Finished | Aug 12 07:50:57 PM PDT 24 |
| Peak memory | 610944 kb |
| Host | smart-2d1a2e8a-e308-4731-aa2a-69de94bd4df0 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=30_000_000 +sw_build_device=sim_dv +sw_images=clkmgr_off_peri_test:1:new_rules,test_rom:0 +cdc_instrumenta tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3206897048 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/ coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_clkmgr_off_peri.3206897048 |
| Directory | /workspace/2.chip_sw_clkmgr_off_peri/latest |
| Test location | /workspace/coverage/default/2.chip_sw_clkmgr_reset_frequency.1840481105 |
| Short name | T1189 |
| Test name | |
| Test status | |
| Simulation time | 3608487520 ps |
| CPU time | 408.6 seconds |
| Started | Aug 12 07:28:15 PM PDT 24 |
| Finished | Aug 12 07:35:04 PM PDT 24 |
| Peak memory | 610224 kb |
| Host | smart-388ee50e-5cab-4aa5-b145-e8f8624d6949 |
| User | root |
| Command | /workspace/default/simv +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=clkmgr_reset_frequency_test:1:new_rules,test_rom:0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1840481105 -a ssert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov erage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_clkmgr_reset_frequency.1840481105 |
| Directory | /workspace/2.chip_sw_clkmgr_reset_frequency/latest |
| Test location | /workspace/coverage/default/2.chip_sw_clkmgr_sleep_frequency.3439944174 |
| Short name | T1319 |
| Test name | |
| Test status | |
| Simulation time | 4946828744 ps |
| CPU time | 517.54 seconds |
| Started | Aug 12 07:28:37 PM PDT 24 |
| Finished | Aug 12 07:37:15 PM PDT 24 |
| Peak memory | 610688 kb |
| Host | smart-d60fabf3-82eb-4f23-affb-0e2c669fc00a |
| User | root |
| Command | /workspace/default/simv +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=clkmgr_sleep_frequency_test:1:new_rules,test_rom:0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3439944174 -a ssert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov erage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_clkmgr_sleep_frequency.3439944174 |
| Directory | /workspace/2.chip_sw_clkmgr_sleep_frequency/latest |
| Test location | /workspace/coverage/default/2.chip_sw_clkmgr_smoketest.1911161246 |
| Short name | T275 |
| Test name | |
| Test status | |
| Simulation time | 2866731190 ps |
| CPU time | 301.6 seconds |
| Started | Aug 12 07:29:56 PM PDT 24 |
| Finished | Aug 12 07:34:58 PM PDT 24 |
| Peak memory | 610168 kb |
| Host | smart-c5d58ad3-b07a-4fc7-bc45-7184156af667 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=clkmgr_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1911161246 -assert nopostproc +UVM_TESTNAME=c hip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n ull -cm_name 2.chip_sw_clkmgr_smoketest.1911161246 |
| Directory | /workspace/2.chip_sw_clkmgr_smoketest/latest |
| Test location | /workspace/coverage/default/2.chip_sw_csrng_edn_concurrency.3635553404 |
| Short name | T1160 |
| Test name | |
| Test status | |
| Simulation time | 28143041816 ps |
| CPU time | 6281.94 seconds |
| Started | Aug 12 07:26:48 PM PDT 24 |
| Finished | Aug 12 09:11:31 PM PDT 24 |
| Peak memory | 610804 kb |
| Host | smart-b2925a9f-e4c1-4681-8d49-50bd709f4b53 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=140_000_000 +rng_srate_value_min=15 +rng_srate_value_max=20 +sw_build_device=sim_dv +sw_images=csrng_edn_c oncurrency_test:1:new_rules,test_rom:0 +accelerate_cold_power_up_time=3 +accelerate_regulators_power_up_time=2 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3635553404 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd b -cm_log /dev/null -cm_name 2.chip_sw_csrng_edn_concurrency.3635553404 |
| Directory | /workspace/2.chip_sw_csrng_edn_concurrency/latest |
| Test location | /workspace/coverage/default/2.chip_sw_csrng_edn_concurrency_reduced_freq.3308952492 |
| Short name | T120 |
| Test name | |
| Test status | |
| Simulation time | 143210333584 ps |
| CPU time | 18610.4 seconds |
| Started | Aug 12 07:29:38 PM PDT 24 |
| Finished | Aug 13 12:39:51 AM PDT 24 |
| Peak memory | 610784 kb |
| Host | smart-f6444668-a5ac-4f4f-9d9b-d60de8fa2535 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=360_000_000 +rng_srate_value_min=15 +rng_srate_value_max=20 +cal_sys_clk_70mhz=1 +en_jitter=1 +sw_build_de vice=sim_dv +sw_images=csrng_edn_concurrency_test:1:new_rules,test_rom:0 +accelerate_cold_power_up_time=3 +accelerate_regulators_power_up_time=2 + cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_ seed=3308952492 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_csrng_edn_concurrency_reduced_freq.3308952492 |
| Directory | /workspace/2.chip_sw_csrng_edn_concurrency_reduced_freq/latest |
| Test location | /workspace/coverage/default/2.chip_sw_csrng_fuse_en_sw_app_read_test.3896904289 |
| Short name | T1280 |
| Test name | |
| Test status | |
| Simulation time | 4776002664 ps |
| CPU time | 385.91 seconds |
| Started | Aug 12 07:26:45 PM PDT 24 |
| Finished | Aug 12 07:33:11 PM PDT 24 |
| Peak memory | 609884 kb |
| Host | smart-43504bdf-294e-4213-99ca-679356eee0d7 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=15_000_000 +sw_build_device=sim_dv +sw_images=csrng_fuse_en_sw_app_read:1:new_rules,test_rom:0 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38969 04289 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_entropy_src_fuse_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_csrng_fuse_en_sw_app_read_test.3896904289 |
| Directory | /workspace/2.chip_sw_csrng_fuse_en_sw_app_read_test/latest |
| Test location | /workspace/coverage/default/2.chip_sw_csrng_kat_test.1126601228 |
| Short name | T1161 |
| Test name | |
| Test status | |
| Simulation time | 3272732488 ps |
| CPU time | 280.87 seconds |
| Started | Aug 12 07:30:54 PM PDT 24 |
| Finished | Aug 12 07:35:36 PM PDT 24 |
| Peak memory | 610012 kb |
| Host | smart-8bc475e3-7acf-48a4-a99d-6ac1a1607653 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=csrng_kat_test:1:new_rules,test_rom:0 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1126601228 -asse rt nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera ge/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_csrng_kat_test.1126601228 |
| Directory | /workspace/2.chip_sw_csrng_kat_test/latest |
| Test location | /workspace/coverage/default/2.chip_sw_csrng_smoketest.3823227239 |
| Short name | T1207 |
| Test name | |
| Test status | |
| Simulation time | 2943146572 ps |
| CPU time | 288.03 seconds |
| Started | Aug 12 07:32:35 PM PDT 24 |
| Finished | Aug 12 07:37:23 PM PDT 24 |
| Peak memory | 610016 kb |
| Host | smart-abd154d6-3c53-4c8f-a5fa-fec04dc21152 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=csrng_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3823227239 -assert nopostproc +UVM_TESTNAME=ch ip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu ll -cm_name 2.chip_sw_csrng_smoketest.3823227239 |
| Directory | /workspace/2.chip_sw_csrng_smoketest/latest |
| Test location | /workspace/coverage/default/2.chip_sw_edn_auto_mode.2970591500 |
| Short name | T134 |
| Test name | |
| Test status | |
| Simulation time | 5273750210 ps |
| CPU time | 1418.49 seconds |
| Started | Aug 12 07:28:55 PM PDT 24 |
| Finished | Aug 12 07:52:34 PM PDT 24 |
| Peak memory | 610732 kb |
| Host | smart-cedec2e5-b978-4be2-af29-8805069dcd8b |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +rng_srate_value=5 +sw_build_device=sim_dv +sw_images=edn_auto_mode:1:new_rules,test_rom:0 +acc elerate_cold_power_up_time=3 +accelerate_regulators_power_up_time=2 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2970591500 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ =chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_edn_ auto_mode.2970591500 |
| Directory | /workspace/2.chip_sw_edn_auto_mode/latest |
| Test location | /workspace/coverage/default/2.chip_sw_edn_boot_mode.609567271 |
| Short name | T135 |
| Test name | |
| Test status | |
| Simulation time | 3218997552 ps |
| CPU time | 641.1 seconds |
| Started | Aug 12 07:26:36 PM PDT 24 |
| Finished | Aug 12 07:37:18 PM PDT 24 |
| Peak memory | 610432 kb |
| Host | smart-4c27208b-f124-45c7-a42c-6d7ebf067976 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +rng_srate_value=5 +sw_build_device=sim_dv +sw_images=edn_boot_mode:1:new_rules,test_rom:0 +acc elerate_cold_power_up_time=3 +accelerate_regulators_power_up_time=2 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=609567271 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ= chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_edn_b oot_mode.609567271 |
| Directory | /workspace/2.chip_sw_edn_boot_mode/latest |
| Test location | /workspace/coverage/default/2.chip_sw_edn_entropy_reqs.1913665709 |
| Short name | T1090 |
| Test name | |
| Test status | |
| Simulation time | 5933466096 ps |
| CPU time | 1242.07 seconds |
| Started | Aug 12 07:28:07 PM PDT 24 |
| Finished | Aug 12 07:48:50 PM PDT 24 |
| Peak memory | 611428 kb |
| Host | smart-7cb59b92-9380-461d-93d4-6dadd979232e |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=15000000 +rng_srate_value_min=15 +rng_srate_value_max=30 +sw_build_device=sim_dv +sw_images=entropy_src_ed n_reqs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1913665709 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_edn_entropy_reqs.1913665709 |
| Directory | /workspace/2.chip_sw_edn_entropy_reqs/latest |
| Test location | /workspace/coverage/default/2.chip_sw_edn_entropy_reqs_jitter.3561489454 |
| Short name | T459 |
| Test name | |
| Test status | |
| Simulation time | 6488498834 ps |
| CPU time | 918.6 seconds |
| Started | Aug 12 07:28:12 PM PDT 24 |
| Finished | Aug 12 07:43:31 PM PDT 24 |
| Peak memory | 611140 kb |
| Host | smart-9a029dac-b2e5-4c34-a70b-79d5330d5d77 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=15000000 +rng_srate_value_min=15 +rng_srate_value_max=30 +en_jitter=1 +sw_build_device=sim_dv +sw_images=e ntropy_src_edn_reqs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3561489454 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_edn_entropy_reqs_jitter.3561489454 |
| Directory | /workspace/2.chip_sw_edn_entropy_reqs_jitter/latest |
| Test location | /workspace/coverage/default/2.chip_sw_edn_kat.188313611 |
| Short name | T1017 |
| Test name | |
| Test status | |
| Simulation time | 3035537146 ps |
| CPU time | 779.33 seconds |
| Started | Aug 12 07:27:01 PM PDT 24 |
| Finished | Aug 12 07:40:00 PM PDT 24 |
| Peak memory | 615936 kb |
| Host | smart-d0e97128-5c23-421e-ba57-d9c197401838 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +rng_srate_value=5 +disable_assert_edn_output_diff_from_prev=1 +sw_build_device=sim_dv +sw_imag es=edn_kat:1:new_rules,test_rom:0 +accelerate_cold_power_up_time=3 +accelerate_regulators_power_up_time=2 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=188313611 -assert nopostproc +UVM_ TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_ log /dev/null -cm_name 2.chip_sw_edn_kat.188313611 |
| Directory | /workspace/2.chip_sw_edn_kat/latest |
| Test location | /workspace/coverage/default/2.chip_sw_edn_sw_mode.4097893218 |
| Short name | T1053 |
| Test name | |
| Test status | |
| Simulation time | 8552742838 ps |
| CPU time | 1494.7 seconds |
| Started | Aug 12 07:28:00 PM PDT 24 |
| Finished | Aug 12 07:52:56 PM PDT 24 |
| Peak memory | 610448 kb |
| Host | smart-baf7b5a8-e3a4-4b60-96a9-b481e5babde1 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=edn_sw_mode:1:new_rules,test_rom:0 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4097893218 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/ default.vdb -cm_log /dev/null -cm_name 2.chip_sw_edn_sw_mode.4097893218 |
| Directory | /workspace/2.chip_sw_edn_sw_mode/latest |
| Test location | /workspace/coverage/default/2.chip_sw_entropy_src_ast_rng_req.4210057962 |
| Short name | T1093 |
| Test name | |
| Test status | |
| Simulation time | 3248340660 ps |
| CPU time | 351.12 seconds |
| Started | Aug 12 07:27:05 PM PDT 24 |
| Finished | Aug 12 07:32:57 PM PDT 24 |
| Peak memory | 608932 kb |
| Host | smart-de91671f-6bd5-492c-8766-a27e97c44991 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=15_000_000 +sw_build_device=sim_dv +sw_images=entropy_src_ast_rng_req_test:1:new_rules,test_rom:0 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42 10057962 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_entropy_src_ast_rng_req.4210057962 |
| Directory | /workspace/2.chip_sw_entropy_src_ast_rng_req/latest |
| Test location | /workspace/coverage/default/2.chip_sw_entropy_src_csrng.1398372804 |
| Short name | T341 |
| Test name | |
| Test status | |
| Simulation time | 6877289096 ps |
| CPU time | 1533.32 seconds |
| Started | Aug 12 07:29:31 PM PDT 24 |
| Finished | Aug 12 07:55:04 PM PDT 24 |
| Peak memory | 610532 kb |
| Host | smart-1aed8040-3d85-4fd0-beae-fa8192ed44d8 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=50_000_000 +rng_srate_value_min=15 +rng_srate_value_max=30 +sw_build_device=sim_dv +sw_images=entropy_src_ csrng_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1398372804 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_entropy_src_csrng.1398372804 |
| Directory | /workspace/2.chip_sw_entropy_src_csrng/latest |
| Test location | /workspace/coverage/default/2.chip_sw_entropy_src_kat_test.2786970711 |
| Short name | T1438 |
| Test name | |
| Test status | |
| Simulation time | 2618814400 ps |
| CPU time | 200.27 seconds |
| Started | Aug 12 07:28:58 PM PDT 24 |
| Finished | Aug 12 07:32:19 PM PDT 24 |
| Peak memory | 609884 kb |
| Host | smart-d79ef3e2-6e3b-4a17-bc54-ef1afb2ac279 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=entropy_src_kat_test:1:new_rules,test_rom:0 +cdc_instrumenta tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2786970711 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/ coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_entropy_src_kat_test.2786970711 |
| Directory | /workspace/2.chip_sw_entropy_src_kat_test/latest |
| Test location | /workspace/coverage/default/2.chip_sw_entropy_src_smoketest.1442318139 |
| Short name | T987 |
| Test name | |
| Test status | |
| Simulation time | 3327083976 ps |
| CPU time | 592.44 seconds |
| Started | Aug 12 07:31:56 PM PDT 24 |
| Finished | Aug 12 07:41:49 PM PDT 24 |
| Peak memory | 608976 kb |
| Host | smart-cfdf3a56-fa86-426c-aaac-3a9756959a6f |
| User | root |
| Command | /workspace/default/simv +rng_srate_value_min=15 +rng_srate_value_max=30 +sw_build_device=sim_dv +sw_images=entropy_src_smoketest:1:new_rules,test_rom: 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand om_seed=1442318139 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_entropy_src_smoketest.1442318139 |
| Directory | /workspace/2.chip_sw_entropy_src_smoketest/latest |
| Test location | /workspace/coverage/default/2.chip_sw_example_concurrency.1158998636 |
| Short name | T446 |
| Test name | |
| Test status | |
| Simulation time | 2836486480 ps |
| CPU time | 276.77 seconds |
| Started | Aug 12 07:22:37 PM PDT 24 |
| Finished | Aug 12 07:27:13 PM PDT 24 |
| Peak memory | 610180 kb |
| Host | smart-f259b38a-4265-452e-88a2-e8d500def4d0 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=example_concurrency_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1158998636 -assert nopostproc +UVM_TE STNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_lo g /dev/null -cm_name 2.chip_sw_example_concurrency.1158998636 |
| Directory | /workspace/2.chip_sw_example_concurrency/latest |
| Test location | /workspace/coverage/default/2.chip_sw_example_flash.3478820643 |
| Short name | T1236 |
| Test name | |
| Test status | |
| Simulation time | 3339833800 ps |
| CPU time | 310.95 seconds |
| Started | Aug 12 07:21:08 PM PDT 24 |
| Finished | Aug 12 07:26:19 PM PDT 24 |
| Peak memory | 610160 kb |
| Host | smart-7eb193a8-7871-4ad3-8490-53f013d67609 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=example_test_from_flash:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3478820643 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_example_flash.3478820643 |
| Directory | /workspace/2.chip_sw_example_flash/latest |
| Test location | /workspace/coverage/default/2.chip_sw_example_manufacturer.2228251153 |
| Short name | T427 |
| Test name | |
| Test status | |
| Simulation time | 2832319500 ps |
| CPU time | 251.86 seconds |
| Started | Aug 12 07:24:06 PM PDT 24 |
| Finished | Aug 12 07:28:18 PM PDT 24 |
| Peak memory | 609816 kb |
| Host | smart-8c5bf7d9-b76f-49e8-82bc-7564d8f13151 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=example_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2228251153 -assert nopostproc +UVM_TESTNAME=chip_ base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_example_manufacturer.2228251153 |
| Directory | /workspace/2.chip_sw_example_manufacturer/latest |
| Test location | /workspace/coverage/default/2.chip_sw_example_rom.122092941 |
| Short name | T392 |
| Test name | |
| Test status | |
| Simulation time | 2624892260 ps |
| CPU time | 117.54 seconds |
| Started | Aug 12 07:21:24 PM PDT 24 |
| Finished | Aug 12 07:23:22 PM PDT 24 |
| Peak memory | 608380 kb |
| Host | smart-7a10b369-9f0f-40ca-9437-3c8cee85441a |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=example_test_from_rom:0:test_in_rom:new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=122092941 -assert nopostproc +UVM_TESTN AME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log / dev/null -cm_name 2.chip_sw_example_rom.122092941 |
| Directory | /workspace/2.chip_sw_example_rom/latest |
| Test location | /workspace/coverage/default/2.chip_sw_flash_crash_alert.2422691839 |
| Short name | T363 |
| Test name | |
| Test status | |
| Simulation time | 5807718136 ps |
| CPU time | 808.12 seconds |
| Started | Aug 12 07:28:50 PM PDT 24 |
| Finished | Aug 12 07:42:18 PM PDT 24 |
| Peak memory | 611620 kb |
| Host | smart-514b2b5e-2a6d-42d6-928f-057b7a11704c |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=8_000_000 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1: new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tool s/sim.tcl +ntb_random_seed=2422691839 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_flash_host_gnt_err_inj_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_flash_crash_alert.2422691839 |
| Directory | /workspace/2.chip_sw_flash_crash_alert/latest |
| Test location | /workspace/coverage/default/2.chip_sw_flash_ctrl_access.1646248946 |
| Short name | T1135 |
| Test name | |
| Test status | |
| Simulation time | 5477003224 ps |
| CPU time | 1001.11 seconds |
| Started | Aug 12 07:25:05 PM PDT 24 |
| Finished | Aug 12 07:41:48 PM PDT 24 |
| Peak memory | 610336 kb |
| Host | smart-950cd982-2e18-49c4-bed5-4f9229b90701 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=flash_ctrl_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1646248946 -assert nopostproc +UVM_TESTNAME=ch ip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu ll -cm_name 2.chip_sw_flash_ctrl_access.1646248946 |
| Directory | /workspace/2.chip_sw_flash_ctrl_access/latest |
| Test location | /workspace/coverage/default/2.chip_sw_flash_ctrl_access_jitter_en.862982122 |
| Short name | T1235 |
| Test name | |
| Test status | |
| Simulation time | 6124136750 ps |
| CPU time | 1165.89 seconds |
| Started | Aug 12 07:23:16 PM PDT 24 |
| Finished | Aug 12 07:42:42 PM PDT 24 |
| Peak memory | 610500 kb |
| Host | smart-cf7aa21c-76d0-474d-97a1-647b7b67354c |
| User | root |
| Command | /workspace/default/simv +en_jitter=1 +sw_build_device=sim_dv +sw_images=flash_ctrl_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=862982122 -assert nopostproc +UVM _TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm _log /dev/null -cm_name 2.chip_sw_flash_ctrl_access_jitter_en.862982122 |
| Directory | /workspace/2.chip_sw_flash_ctrl_access_jitter_en/latest |
| Test location | /workspace/coverage/default/2.chip_sw_flash_ctrl_access_jitter_en_reduced_freq.1847593308 |
| Short name | T999 |
| Test name | |
| Test status | |
| Simulation time | 7930989442 ps |
| CPU time | 1144.33 seconds |
| Started | Aug 12 07:29:57 PM PDT 24 |
| Finished | Aug 12 07:49:01 PM PDT 24 |
| Peak memory | 610584 kb |
| Host | smart-563d9138-5cc7-4052-b302-649e3f80e050 |
| User | root |
| Command | /workspace/default/simv +en_jitter=1 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=flash_ctrl_test:1:new_rules,test_rom:0 +cdc_instrumentati on_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1847593308 - assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co verage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_flash_ctrl_access_jitter_en_reduced_freq.1847593308 |
| Directory | /workspace/2.chip_sw_flash_ctrl_access_jitter_en_reduced_freq/latest |
| Test location | /workspace/coverage/default/2.chip_sw_flash_ctrl_clock_freqs.2852174530 |
| Short name | T1107 |
| Test name | |
| Test status | |
| Simulation time | 5674105436 ps |
| CPU time | 1222.96 seconds |
| Started | Aug 12 07:24:15 PM PDT 24 |
| Finished | Aug 12 07:44:38 PM PDT 24 |
| Peak memory | 610248 kb |
| Host | smart-d0ac4c0b-ab1c-4bb0-acd9-74025c4a70e2 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=flash_ctrl_clock_freqs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2852174530 -assert nopostproc +UVM _TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm _log /dev/null -cm_name 2.chip_sw_flash_ctrl_clock_freqs.2852174530 |
| Directory | /workspace/2.chip_sw_flash_ctrl_clock_freqs/latest |
| Test location | /workspace/coverage/default/2.chip_sw_flash_ctrl_idle_low_power.3912657523 |
| Short name | T1113 |
| Test name | |
| Test status | |
| Simulation time | 3725341136 ps |
| CPU time | 373.22 seconds |
| Started | Aug 12 07:24:38 PM PDT 24 |
| Finished | Aug 12 07:30:51 PM PDT 24 |
| Peak memory | 610008 kb |
| Host | smart-706f9c13-029f-44de-8aaf-f8ab400d49bb |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=flash_ctrl_idle_low_power_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3912657523 -assert nopostproc + UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_flash_ctrl_idle_low_power.3912657523 |
| Directory | /workspace/2.chip_sw_flash_ctrl_idle_low_power/latest |
| Test location | /workspace/coverage/default/2.chip_sw_flash_ctrl_lc_rw_en.1255317191 |
| Short name | T1349 |
| Test name | |
| Test status | |
| Simulation time | 4069585420 ps |
| CPU time | 359.24 seconds |
| Started | Aug 12 07:23:33 PM PDT 24 |
| Finished | Aug 12 07:29:33 PM PDT 24 |
| Peak memory | 611004 kb |
| Host | smart-a68625c1-d879-4fa4-897a-2ec66e290a62 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=flash_ctrl_lc_rw_en_test:1:new_rules,test_rom:0 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12 55317191 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_flash_ctrl_lc_rw_en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_flash_ctrl_lc_rw_en.1255317191 |
| Directory | /workspace/2.chip_sw_flash_ctrl_lc_rw_en/latest |
| Test location | /workspace/coverage/default/2.chip_sw_flash_ctrl_mem_protection.887476025 |
| Short name | T993 |
| Test name | |
| Test status | |
| Simulation time | 5391656360 ps |
| CPU time | 1137.88 seconds |
| Started | Aug 12 07:31:11 PM PDT 24 |
| Finished | Aug 12 07:50:10 PM PDT 24 |
| Peak memory | 610548 kb |
| Host | smart-039e20de-4c4a-460e-a832-570a0b3a1d3b |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=flash_ctrl_mem_protection_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=887476025 -assert nopostproc +U VM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb - cm_log /dev/null -cm_name 2.chip_sw_flash_ctrl_mem_protection.887476025 |
| Directory | /workspace/2.chip_sw_flash_ctrl_mem_protection/latest |
| Test location | /workspace/coverage/default/2.chip_sw_flash_ctrl_ops.1643896881 |
| Short name | T377 |
| Test name | |
| Test status | |
| Simulation time | 4570272730 ps |
| CPU time | 671.07 seconds |
| Started | Aug 12 07:26:43 PM PDT 24 |
| Finished | Aug 12 07:37:55 PM PDT 24 |
| Peak memory | 610260 kb |
| Host | smart-c5d0d92a-556d-4985-b251-55f5d6d58ac2 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=50_000_000 +sw_build_device=sim_dv +sw_images=flash_ctrl_ops_test:1:new_rules,test_rom:0 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1643896881 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/c overage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_flash_ctrl_ops.1643896881 |
| Directory | /workspace/2.chip_sw_flash_ctrl_ops/latest |
| Test location | /workspace/coverage/default/2.chip_sw_flash_ctrl_ops_jitter_en.2573799338 |
| Short name | T353 |
| Test name | |
| Test status | |
| Simulation time | 3773282859 ps |
| CPU time | 660.54 seconds |
| Started | Aug 12 07:23:24 PM PDT 24 |
| Finished | Aug 12 07:34:25 PM PDT 24 |
| Peak memory | 610312 kb |
| Host | smart-6f8357fb-0e1f-4b77-8106-5531c2143d1f |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=50_000_000 +en_jitter=1 +sw_build_device=sim_dv +sw_images=flash_ctrl_ops_test:1:new_rules,test_rom:0 +cdc _instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see d=2573799338 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_flash_ctrl_ops_jitter_en.2573799338 |
| Directory | /workspace/2.chip_sw_flash_ctrl_ops_jitter_en/latest |
| Test location | /workspace/coverage/default/2.chip_sw_flash_ctrl_ops_jitter_en_reduced_freq.3950351541 |
| Short name | T354 |
| Test name | |
| Test status | |
| Simulation time | 5052915251 ps |
| CPU time | 688.73 seconds |
| Started | Aug 12 07:29:24 PM PDT 24 |
| Finished | Aug 12 07:40:53 PM PDT 24 |
| Peak memory | 610664 kb |
| Host | smart-7f90df0d-270e-4f74-ab69-71e0204f837e |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=50_000_000 +en_jitter=1 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=flash_ctrl_ops_test:1:new_ rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si m.tcl +ntb_random_seed=3950351541 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_flash_ctrl_ops_jitter_en_reduced_freq.3950351541 |
| Directory | /workspace/2.chip_sw_flash_ctrl_ops_jitter_en_reduced_freq/latest |
| Test location | /workspace/coverage/default/2.chip_sw_flash_ctrl_write_clear.3718475734 |
| Short name | T1015 |
| Test name | |
| Test status | |
| Simulation time | 3016942280 ps |
| CPU time | 321.48 seconds |
| Started | Aug 12 07:28:54 PM PDT 24 |
| Finished | Aug 12 07:34:16 PM PDT 24 |
| Peak memory | 608932 kb |
| Host | smart-fdacaa32-2273-473b-bed9-3059ff402c24 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=8_000_000 +sw_build_device=sim_dv +sw_images=flash_ctrl_write_clear_test:1:new_rules,test_rom:0 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3718475 734 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ce/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_flash_ctrl_write_clear.3718475734 |
| Directory | /workspace/2.chip_sw_flash_ctrl_write_clear/latest |
| Test location | /workspace/coverage/default/2.chip_sw_flash_init.1926170939 |
| Short name | T240 |
| Test name | |
| Test status | |
| Simulation time | 27086774553 ps |
| CPU time | 2385.25 seconds |
| Started | Aug 12 07:22:33 PM PDT 24 |
| Finished | Aug 12 08:02:18 PM PDT 24 |
| Peak memory | 616124 kb |
| Host | smart-77cade1f-a9e8-4b68-ac4f-fcefae985123 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=25_000_000 +sw_build_device=sim_dv +sw_images=flash_init_test:0:test_in_rom:new_rules +cdc_instrumentation _enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1926170939 -as sert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_flash_init_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac e/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_flash_init.1926170939 |
| Directory | /workspace/2.chip_sw_flash_init/latest |
| Test location | /workspace/coverage/default/2.chip_sw_flash_init_reduced_freq.3783374563 |
| Short name | T237 |
| Test name | |
| Test status | |
| Simulation time | 19226585774 ps |
| CPU time | 1930.29 seconds |
| Started | Aug 12 07:28:47 PM PDT 24 |
| Finished | Aug 12 08:00:58 PM PDT 24 |
| Peak memory | 615940 kb |
| Host | smart-9d573a93-5a4e-4711-abba-d17b7acf1942 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=25_000_000 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=flash_init_test:0:test_in_rom:new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=3783374563 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_flash_init_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_flash_init_reduced_freq.3783374563 |
| Directory | /workspace/2.chip_sw_flash_init_reduced_freq/latest |
| Test location | /workspace/coverage/default/2.chip_sw_flash_scrambling_smoketest.2628388612 |
| Short name | T972 |
| Test name | |
| Test status | |
| Simulation time | 3153456044 ps |
| CPU time | 209.91 seconds |
| Started | Aug 12 07:33:07 PM PDT 24 |
| Finished | Aug 12 07:36:37 PM PDT 24 |
| Peak memory | 610136 kb |
| Host | smart-18280d5e-56da-451c-9131-71c7beb58146 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=flash_scrambling_smoketest:1:new_rules,flash_scrambling_smoket est_otp_img_rma:4,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=2628388612 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_flash_scrambling_smoketest.2628388612 |
| Directory | /workspace/2.chip_sw_flash_scrambling_smoketest/latest |
| Test location | /workspace/coverage/default/2.chip_sw_gpio_smoketest.42484736 |
| Short name | T27 |
| Test name | |
| Test status | |
| Simulation time | 3096588674 ps |
| CPU time | 355.43 seconds |
| Started | Aug 12 07:30:21 PM PDT 24 |
| Finished | Aug 12 07:36:17 PM PDT 24 |
| Peak memory | 609452 kb |
| Host | smart-9bc0d7f9-350d-4d45-baee-5a3d59059c20 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=gpio_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42484736 -assert nopostproc +UVM_TESTNAME=chip_ base_test +UVM_TEST_SEQ=chip_sw_gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 2.chip_sw_gpio_smoketest.42484736 |
| Directory | /workspace/2.chip_sw_gpio_smoketest/latest |
| Test location | /workspace/coverage/default/2.chip_sw_hmac_enc.3603418451 |
| Short name | T380 |
| Test name | |
| Test status | |
| Simulation time | 2908455128 ps |
| CPU time | 280.23 seconds |
| Started | Aug 12 07:26:38 PM PDT 24 |
| Finished | Aug 12 07:31:19 PM PDT 24 |
| Peak memory | 610220 kb |
| Host | smart-95327755-04ae-4a2c-8f65-3d6639233a9d |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=hmac_enc_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3603418451 -assert nopostproc +UVM_TESTNAME=chip _base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_hmac_enc.3603418451 |
| Directory | /workspace/2.chip_sw_hmac_enc/latest |
| Test location | /workspace/coverage/default/2.chip_sw_hmac_enc_idle.2808000135 |
| Short name | T1032 |
| Test name | |
| Test status | |
| Simulation time | 3197223660 ps |
| CPU time | 383.24 seconds |
| Started | Aug 12 07:27:10 PM PDT 24 |
| Finished | Aug 12 07:33:34 PM PDT 24 |
| Peak memory | 609984 kb |
| Host | smart-358b79a3-f810-47d1-a178-bda4ed847215 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=hmac_enc_idle_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2808000135 -assert nopostproc +UVM_TESTNAME =chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 2.chip_sw_hmac_enc_idle.2808000135 |
| Directory | /workspace/2.chip_sw_hmac_enc_idle/latest |
| Test location | /workspace/coverage/default/2.chip_sw_hmac_enc_jitter_en.1965082818 |
| Short name | T1332 |
| Test name | |
| Test status | |
| Simulation time | 3370104361 ps |
| CPU time | 222.9 seconds |
| Started | Aug 12 07:26:21 PM PDT 24 |
| Finished | Aug 12 07:30:04 PM PDT 24 |
| Peak memory | 610128 kb |
| Host | smart-c6d5b04c-aabd-4d6c-a689-d436b20c4294 |
| User | root |
| Command | /workspace/default/simv +en_jitter=1 +sw_build_device=sim_dv +sw_images=hmac_enc_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1965082818 -assert nopostproc +UVM_ TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_ log /dev/null -cm_name 2.chip_sw_hmac_enc_jitter_en.1965082818 |
| Directory | /workspace/2.chip_sw_hmac_enc_jitter_en/latest |
| Test location | /workspace/coverage/default/2.chip_sw_hmac_enc_jitter_en_reduced_freq.2124799816 |
| Short name | T368 |
| Test name | |
| Test status | |
| Simulation time | 3425552242 ps |
| CPU time | 347.92 seconds |
| Started | Aug 12 07:29:32 PM PDT 24 |
| Finished | Aug 12 07:35:20 PM PDT 24 |
| Peak memory | 610164 kb |
| Host | smart-e13ac11c-f09e-4eee-a67d-4515df07ee93 |
| User | root |
| Command | /workspace/default/simv +en_jitter=1 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=hmac_enc_test:1:new_rules,test_rom:0 +cdc_instrumentation _enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2124799816 -as sert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove rage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_hmac_enc_jitter_en_reduced_freq.2124799816 |
| Directory | /workspace/2.chip_sw_hmac_enc_jitter_en_reduced_freq/latest |
| Test location | /workspace/coverage/default/2.chip_sw_hmac_multistream.297416262 |
| Short name | T1371 |
| Test name | |
| Test status | |
| Simulation time | 7414337880 ps |
| CPU time | 1607.17 seconds |
| Started | Aug 12 07:26:37 PM PDT 24 |
| Finished | Aug 12 07:53:25 PM PDT 24 |
| Peak memory | 610540 kb |
| Host | smart-471c2024-bd93-4939-ba76-371820ebfd8a |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=hmac_multistream_functest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=297416262 -assert nopostproc +UVM_TE STNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_lo g /dev/null -cm_name 2.chip_sw_hmac_multistream.297416262 |
| Directory | /workspace/2.chip_sw_hmac_multistream/latest |
| Test location | /workspace/coverage/default/2.chip_sw_hmac_oneshot.3904514124 |
| Short name | T1434 |
| Test name | |
| Test status | |
| Simulation time | 3111990002 ps |
| CPU time | 359.71 seconds |
| Started | Aug 12 07:29:01 PM PDT 24 |
| Finished | Aug 12 07:35:00 PM PDT 24 |
| Peak memory | 609728 kb |
| Host | smart-297e5780-222c-4130-bd38-84fc7db79a21 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=hmac_functest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3904514124 -assert nopostproc +UVM_TESTNAME=chip _base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_hmac_oneshot.3904514124 |
| Directory | /workspace/2.chip_sw_hmac_oneshot/latest |
| Test location | /workspace/coverage/default/2.chip_sw_hmac_smoketest.3271785503 |
| Short name | T1041 |
| Test name | |
| Test status | |
| Simulation time | 3626566692 ps |
| CPU time | 316.03 seconds |
| Started | Aug 12 07:29:57 PM PDT 24 |
| Finished | Aug 12 07:35:13 PM PDT 24 |
| Peak memory | 609732 kb |
| Host | smart-500622ed-cab5-49a8-94f4-0beb67bb80ea |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=hmac_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3271785503 -assert nopostproc +UVM_TESTNAME=chi p_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul l -cm_name 2.chip_sw_hmac_smoketest.3271785503 |
| Directory | /workspace/2.chip_sw_hmac_smoketest/latest |
| Test location | /workspace/coverage/default/2.chip_sw_i2c_device_tx_rx.961433000 |
| Short name | T346 |
| Test name | |
| Test status | |
| Simulation time | 4464880246 ps |
| CPU time | 738.68 seconds |
| Started | Aug 12 07:23:19 PM PDT 24 |
| Finished | Aug 12 07:35:38 PM PDT 24 |
| Peak memory | 610000 kb |
| Host | smart-4ed32a4c-ce49-4280-a1cb-954251ab6a9d |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=i2c_device_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=961433000 -assert nopostproc +UVM_TESTNA ME=chip_base_test +UVM_TEST_SEQ=chip_sw_i2c_device_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd b -cm_log /dev/null -cm_name 2.chip_sw_i2c_device_tx_rx.961433000 |
| Directory | /workspace/2.chip_sw_i2c_device_tx_rx/latest |
| Test location | /workspace/coverage/default/2.chip_sw_i2c_host_tx_rx.503302938 |
| Short name | T335 |
| Test name | |
| Test status | |
| Simulation time | 4224910158 ps |
| CPU time | 651.83 seconds |
| Started | Aug 12 07:26:30 PM PDT 24 |
| Finished | Aug 12 07:37:22 PM PDT 24 |
| Peak memory | 609828 kb |
| Host | smart-63a1ce7b-1afd-43d0-8dc6-d28a787d4a58 |
| User | root |
| Command | /workspace/default/simv +i2c_idx=0 +sw_build_device=sim_dv +sw_images=i2c_host_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=503302938 -assert nopostproc +U VM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_i2c_host_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def ault.vdb -cm_log /dev/null -cm_name 2.chip_sw_i2c_host_tx_rx.503302938 |
| Directory | /workspace/2.chip_sw_i2c_host_tx_rx/latest |
| Test location | /workspace/coverage/default/2.chip_sw_i2c_host_tx_rx_idx2.3556201720 |
| Short name | T370 |
| Test name | |
| Test status | |
| Simulation time | 4640574428 ps |
| CPU time | 886.94 seconds |
| Started | Aug 12 07:24:13 PM PDT 24 |
| Finished | Aug 12 07:39:00 PM PDT 24 |
| Peak memory | 609644 kb |
| Host | smart-eeac9793-a602-4d7f-8810-d11f62546a8b |
| User | root |
| Command | /workspace/default/simv +i2c_idx=2 +sw_build_device=sim_dv +sw_images=i2c_host_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3556201720 -assert nopostproc + UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_i2c_host_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de fault.vdb -cm_log /dev/null -cm_name 2.chip_sw_i2c_host_tx_rx_idx2.3556201720 |
| Directory | /workspace/2.chip_sw_i2c_host_tx_rx_idx2/latest |
| Test location | /workspace/coverage/default/2.chip_sw_inject_scramble_seed.849719190 |
| Short name | T218 |
| Test name | |
| Test status | |
| Simulation time | 64489476226 ps |
| CPU time | 11098.3 seconds |
| Started | Aug 12 07:23:18 PM PDT 24 |
| Finished | Aug 12 10:28:18 PM PDT 24 |
| Peak memory | 625260 kb |
| Host | smart-dbbb2823-e71e-4dda-8585-023bae0876d8 |
| User | root |
| Command | /workspace/default/simv +lc_at_prod=1 +flash_program_latency=5 +sw_test_timeout_ns=150_000_000 +sw_build_device=sim_dv +sw_images=inject_scramble_seed :1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=849719190 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_inject_scramble_seed_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_inject_scramble_seed.849719190 |
| Directory | /workspace/2.chip_sw_inject_scramble_seed/latest |
| Test location | /workspace/coverage/default/2.chip_sw_keymgr_key_derivation.1685656403 |
| Short name | T1145 |
| Test name | |
| Test status | |
| Simulation time | 8594793816 ps |
| CPU time | 1454.09 seconds |
| Started | Aug 12 07:27:42 PM PDT 24 |
| Finished | Aug 12 07:51:58 PM PDT 24 |
| Peak memory | 618644 kb |
| Host | smart-0dc620c5-4390-42c3-b04d-d0973444971c |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=20_000_000 +sw_build_device=sim_dv +sw_images=keymgr_key_derivation_test:1:new_rules,test_rom:0 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1685 656403 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_keymgr_key_derivation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_keymgr_key_derivation.1685656403 |
| Directory | /workspace/2.chip_sw_keymgr_key_derivation/latest |
| Test location | /workspace/coverage/default/2.chip_sw_keymgr_key_derivation_jitter_en.3231707200 |
| Short name | T1369 |
| Test name | |
| Test status | |
| Simulation time | 6575395788 ps |
| CPU time | 1287.24 seconds |
| Started | Aug 12 07:27:09 PM PDT 24 |
| Finished | Aug 12 07:48:36 PM PDT 24 |
| Peak memory | 618724 kb |
| Host | smart-4d825112-8e3f-4ded-8f29-5239bf975d91 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=20_000_000 +en_jitter=1 +sw_build_device=sim_dv +sw_images=keymgr_key_derivation_test:1:new_rules,test_rom :0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=3231707200 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_keymgr_key_derivation_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_keymgr_key_derivation_jitter_en.3231707200 |
| Directory | /workspace/2.chip_sw_keymgr_key_derivation_jitter_en/latest |
| Test location | /workspace/coverage/default/2.chip_sw_keymgr_key_derivation_jitter_en_reduced_freq.1460205411 |
| Short name | T1301 |
| Test name | |
| Test status | |
| Simulation time | 8739061369 ps |
| CPU time | 1443.77 seconds |
| Started | Aug 12 07:29:48 PM PDT 24 |
| Finished | Aug 12 07:53:52 PM PDT 24 |
| Peak memory | 618408 kb |
| Host | smart-0f9ed2f9-d5ef-4af8-888a-a6f24c74b409 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=20_000_000 +en_jitter=1 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=keymgr_key_derivation_test :1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=1460205411 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_keymgr_key_derivation_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_keymgr_key_derivation_jitter_en _reduced_freq.1460205411 |
| Directory | /workspace/2.chip_sw_keymgr_key_derivation_jitter_en_reduced_freq/latest |
| Test location | /workspace/coverage/default/2.chip_sw_keymgr_key_derivation_prod.1959203569 |
| Short name | T1382 |
| Test name | |
| Test status | |
| Simulation time | 9759460904 ps |
| CPU time | 1918.27 seconds |
| Started | Aug 12 07:27:13 PM PDT 24 |
| Finished | Aug 12 07:59:12 PM PDT 24 |
| Peak memory | 615320 kb |
| Host | smart-9dcc8e3d-8125-4349-b503-476d559ab0d3 |
| User | root |
| Command | /workspace/default/simv +lc_at_prod=1 +sw_test_timeout_ns=20_000_000 +sw_build_device=sim_dv +sw_images=keymgr_key_derivation_test:1:new_rules,test_ro m:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=1959203569 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_keymgr_key_derivation_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_keymgr_key_derivation_prod.1959203569 |
| Directory | /workspace/2.chip_sw_keymgr_key_derivation_prod/latest |
| Test location | /workspace/coverage/default/2.chip_sw_keymgr_sideload_aes.2564860818 |
| Short name | T232 |
| Test name | |
| Test status | |
| Simulation time | 13125542920 ps |
| CPU time | 2565.67 seconds |
| Started | Aug 12 07:28:09 PM PDT 24 |
| Finished | Aug 12 08:10:55 PM PDT 24 |
| Peak memory | 611916 kb |
| Host | smart-96aa6a5f-d23b-4a0a-a5cb-f4475d7f9dd8 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=20_000_000 +sw_build_device=sim_dv +sw_images=keymgr_sideload_aes_test:1:new_rules,test_rom:0 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=256486 0818 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_keymgr_sideload_aes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_keymgr_sideload_aes.2564860818 |
| Directory | /workspace/2.chip_sw_keymgr_sideload_aes/latest |
| Test location | /workspace/coverage/default/2.chip_sw_keymgr_sideload_kmac.3853140584 |
| Short name | T1211 |
| Test name | |
| Test status | |
| Simulation time | 12969323456 ps |
| CPU time | 2119.83 seconds |
| Started | Aug 12 07:26:45 PM PDT 24 |
| Finished | Aug 12 08:02:05 PM PDT 24 |
| Peak memory | 612200 kb |
| Host | smart-6fcf5f59-2118-4992-b50b-1d8dfbbf4ad4 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=20_000_000 +sw_build_device=sim_dv +sw_images=keymgr_sideload_kmac_test:1:new_rules,test_rom:0 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38531 40584 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_keymgr_sideload_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_keymgr_sideload_kmac.3853140584 |
| Directory | /workspace/2.chip_sw_keymgr_sideload_kmac/latest |
| Test location | /workspace/coverage/default/2.chip_sw_kmac_app_rom.618866531 |
| Short name | T1069 |
| Test name | |
| Test status | |
| Simulation time | 2771938960 ps |
| CPU time | 181.94 seconds |
| Started | Aug 12 07:27:03 PM PDT 24 |
| Finished | Aug 12 07:30:05 PM PDT 24 |
| Peak memory | 610172 kb |
| Host | smart-bc2687fe-d034-4fd9-a977-171049cea1ce |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=kmac_app_rom_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=618866531 -assert nopostproc +UVM_TESTNAME=c hip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n ull -cm_name 2.chip_sw_kmac_app_rom.618866531 |
| Directory | /workspace/2.chip_sw_kmac_app_rom/latest |
| Test location | /workspace/coverage/default/2.chip_sw_kmac_entropy.539880524 |
| Short name | T1238 |
| Test name | |
| Test status | |
| Simulation time | 2712682300 ps |
| CPU time | 190.69 seconds |
| Started | Aug 12 07:24:59 PM PDT 24 |
| Finished | Aug 12 07:28:09 PM PDT 24 |
| Peak memory | 610232 kb |
| Host | smart-e7050184-bd85-4d54-a6c4-3cf42ea58b89 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=kmac_entropy_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=539880524 -assert nopostproc +UVM_TESTNAME=c hip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n ull -cm_name 2.chip_sw_kmac_entropy.539880524 |
| Directory | /workspace/2.chip_sw_kmac_entropy/latest |
| Test location | /workspace/coverage/default/2.chip_sw_kmac_idle.1016103869 |
| Short name | T1169 |
| Test name | |
| Test status | |
| Simulation time | 2656196518 ps |
| CPU time | 310.96 seconds |
| Started | Aug 12 07:28:02 PM PDT 24 |
| Finished | Aug 12 07:33:13 PM PDT 24 |
| Peak memory | 610084 kb |
| Host | smart-ce50e162-3cdb-4693-919a-1203fa5f311b |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=kmac_idle_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1016103869 -assert nopostproc +UVM_TESTNAME=chi p_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul l -cm_name 2.chip_sw_kmac_idle.1016103869 |
| Directory | /workspace/2.chip_sw_kmac_idle/latest |
| Test location | /workspace/coverage/default/2.chip_sw_kmac_mode_cshake.3423318756 |
| Short name | T1323 |
| Test name | |
| Test status | |
| Simulation time | 2642219408 ps |
| CPU time | 323.64 seconds |
| Started | Aug 12 07:26:56 PM PDT 24 |
| Finished | Aug 12 07:32:20 PM PDT 24 |
| Peak memory | 609728 kb |
| Host | smart-17e8622c-46de-4e3e-b4c2-697531c60746 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=kmac_mode_cshake_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3423318756 -assert nopostproc +UVM_TESTN AME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log / dev/null -cm_name 2.chip_sw_kmac_mode_cshake.3423318756 |
| Directory | /workspace/2.chip_sw_kmac_mode_cshake/latest |
| Test location | /workspace/coverage/default/2.chip_sw_kmac_mode_kmac.846376217 |
| Short name | T1333 |
| Test name | |
| Test status | |
| Simulation time | 3725602344 ps |
| CPU time | 362.42 seconds |
| Started | Aug 12 07:27:03 PM PDT 24 |
| Finished | Aug 12 07:33:06 PM PDT 24 |
| Peak memory | 609756 kb |
| Host | smart-e86f7d11-e6e7-4d31-9c93-016f790ffb63 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=kmac_mode_kmac_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=846376217 -assert nopostproc +UVM_TESTNAME =chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 2.chip_sw_kmac_mode_kmac.846376217 |
| Directory | /workspace/2.chip_sw_kmac_mode_kmac/latest |
| Test location | /workspace/coverage/default/2.chip_sw_kmac_mode_kmac_jitter_en.2019507822 |
| Short name | T391 |
| Test name | |
| Test status | |
| Simulation time | 2923923387 ps |
| CPU time | 405.19 seconds |
| Started | Aug 12 07:27:23 PM PDT 24 |
| Finished | Aug 12 07:34:08 PM PDT 24 |
| Peak memory | 610196 kb |
| Host | smart-9599e87b-1499-4ac5-8daf-b7324e6b4155 |
| User | root |
| Command | /workspace/default/simv +en_jitter=1 +sw_build_device=sim_dv +sw_images=kmac_mode_kmac_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2019507822 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd b -cm_log /dev/null -cm_name 2.chip_sw_kmac_mode_kmac_jitter_en.2019507822 |
| Directory | /workspace/2.chip_sw_kmac_mode_kmac_jitter_en/latest |
| Test location | /workspace/coverage/default/2.chip_sw_kmac_mode_kmac_jitter_en_reduced_freq.1207665683 |
| Short name | T1033 |
| Test name | |
| Test status | |
| Simulation time | 3352701560 ps |
| CPU time | 277.29 seconds |
| Started | Aug 12 07:29:11 PM PDT 24 |
| Finished | Aug 12 07:33:48 PM PDT 24 |
| Peak memory | 610196 kb |
| Host | smart-8034465f-daa8-4e62-9a09-3065244c7592 |
| User | root |
| Command | /workspace/default/simv +en_jitter=1 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=kmac_mode_kmac_test:1:new_rules,test_rom:0 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12076656 83 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac e/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_kmac_mode_kmac_jitter_en_reduced_freq.1207665683 |
| Directory | /workspace/2.chip_sw_kmac_mode_kmac_jitter_en_reduced_freq/latest |
| Test location | /workspace/coverage/default/2.chip_sw_kmac_smoketest.734381056 |
| Short name | T1244 |
| Test name | |
| Test status | |
| Simulation time | 2591317360 ps |
| CPU time | 317.61 seconds |
| Started | Aug 12 07:31:47 PM PDT 24 |
| Finished | Aug 12 07:37:05 PM PDT 24 |
| Peak memory | 610148 kb |
| Host | smart-34631888-107f-4c3a-b333-3518c60693ad |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=kmac_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=734381056 -assert nopostproc +UVM_TESTNAME=chip _base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_kmac_smoketest.734381056 |
| Directory | /workspace/2.chip_sw_kmac_smoketest/latest |
| Test location | /workspace/coverage/default/2.chip_sw_lc_ctrl_otp_hw_cfg0.3127362545 |
| Short name | T1150 |
| Test name | |
| Test status | |
| Simulation time | 3150608032 ps |
| CPU time | 373.1 seconds |
| Started | Aug 12 07:23:43 PM PDT 24 |
| Finished | Aug 12 07:29:56 PM PDT 24 |
| Peak memory | 609828 kb |
| Host | smart-93d54818-a69c-4945-9f0b-04a6535f7803 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=lc_ctrl_otp_hw_cfg0_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3127362545 -assert nopostproc +UVM_TE STNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_lo g /dev/null -cm_name 2.chip_sw_lc_ctrl_otp_hw_cfg0.3127362545 |
| Directory | /workspace/2.chip_sw_lc_ctrl_otp_hw_cfg0/latest |
| Test location | /workspace/coverage/default/2.chip_sw_lc_ctrl_program_error.1486445708 |
| Short name | T181 |
| Test name | |
| Test status | |
| Simulation time | 4250367044 ps |
| CPU time | 471.35 seconds |
| Started | Aug 12 07:27:46 PM PDT 24 |
| Finished | Aug 12 07:35:38 PM PDT 24 |
| Peak memory | 611220 kb |
| Host | smart-327daf47-b6ac-46ad-8773-bc3d06257748 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=lc_ctrl_program_error:1:new_rules,test_rom:0 + cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_ seed=1486445708 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_program_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_lc_ctrl_program_error.1486445708 |
| Directory | /workspace/2.chip_sw_lc_ctrl_program_error/latest |
| Test location | /workspace/coverage/default/2.chip_sw_lc_ctrl_rand_to_scrap.612707778 |
| Short name | T184 |
| Test name | |
| Test status | |
| Simulation time | 4287462254 ps |
| CPU time | 338.97 seconds |
| Started | Aug 12 07:24:36 PM PDT 24 |
| Finished | Aug 12 07:30:15 PM PDT 24 |
| Peak memory | 621724 kb |
| Host | smart-d082c257-6cef-4ff3-a2d3-1b70b40de5f3 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=lc_ctrl_scrap_test:1:new_rules,test_rom:0 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=61270777 8 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_scrap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_lc_ctrl_rand_to_scrap.612707778 |
| Directory | /workspace/2.chip_sw_lc_ctrl_rand_to_scrap/latest |
| Test location | /workspace/coverage/default/2.chip_sw_lc_ctrl_transition.766345329 |
| Short name | T53 |
| Test name | |
| Test status | |
| Simulation time | 12379662813 ps |
| CPU time | 1141.34 seconds |
| Started | Aug 12 07:24:28 PM PDT 24 |
| Finished | Aug 12 07:43:30 PM PDT 24 |
| Peak memory | 621580 kb |
| Host | smart-9aa30aad-7ceb-416f-913c-08b9fd667db7 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=lc_ctrl_transition_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=766345329 -assert nopostproc +UVM_TEST NAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_transition_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul t.vdb -cm_log /dev/null -cm_name 2.chip_sw_lc_ctrl_transition.766345329 |
| Directory | /workspace/2.chip_sw_lc_ctrl_transition/latest |
| Test location | /workspace/coverage/default/2.chip_sw_lc_ctrl_volatile_raw_unlock.1328339447 |
| Short name | T1378 |
| Test name | |
| Test status | |
| Simulation time | 2470889628 ps |
| CPU time | 94.04 seconds |
| Started | Aug 12 07:24:59 PM PDT 24 |
| Finished | Aug 12 07:26:33 PM PDT 24 |
| Peak memory | 618280 kb |
| Host | smart-088e2a75-7944-40d3-852f-b6bdf88668ec |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStRaw +exp_volatile_raw_unlock_en=0 +sw_build_device=sim_dv +sw_images=lc_ctrl_volatile_raw_unlock_tes t:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/ tools/sim.tcl +ntb_random_seed=1328339447 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_volatile_raw_unlock_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_lc_ctrl_volatile_raw_unlock.1328339447 |
| Directory | /workspace/2.chip_sw_lc_ctrl_volatile_raw_unlock/latest |
| Test location | /workspace/coverage/default/2.chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz.1766924692 |
| Short name | T754 |
| Test name | |
| Test status | |
| Simulation time | 2152806994 ps |
| CPU time | 115.28 seconds |
| Started | Aug 12 07:24:48 PM PDT 24 |
| Finished | Aug 12 07:26:43 PM PDT 24 |
| Peak memory | 618324 kb |
| Host | smart-f6c43ba9-cf4e-4faa-955f-48cebbe92d27 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStRaw +chip_clock_source=ChipClockSourceExternal48Mhz +exp_volatile_raw_unlock_en=0 +sw_build_device=s im_dv +sw_images=lc_ctrl_volatile_raw_unlock_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1766924692 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TES T_SEQ=chip_sw_lc_volatile_raw_unlock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz.1766924692 |
| Directory | /workspace/2.chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz/latest |
| Test location | /workspace/coverage/default/2.chip_sw_lc_walkthrough_prod.2872019118 |
| Short name | T238 |
| Test name | |
| Test status | |
| Simulation time | 46168747490 ps |
| CPU time | 5641.36 seconds |
| Started | Aug 12 07:24:49 PM PDT 24 |
| Finished | Aug 12 08:58:51 PM PDT 24 |
| Peak memory | 619668 kb |
| Host | smart-00ff586b-f3fd-4b6e-b1e3-728834c0bf3e |
| User | root |
| Command | /workspace/default/simv +flash_program_latency=5 +use_otp_image=OtpTypeLcStRaw +dest_dec_state=DecLcStProd +sw_test_timeout_ns=200_000_000 +sw_build_d evice=sim_dv +sw_images=lc_walkthrough_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2872019118 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ= chip_sw_lc_walkthrough_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chi p_sw_lc_walkthrough_prod.2872019118 |
| Directory | /workspace/2.chip_sw_lc_walkthrough_prod/latest |
| Test location | /workspace/coverage/default/2.chip_sw_lc_walkthrough_prodend.1109551357 |
| Short name | T1083 |
| Test name | |
| Test status | |
| Simulation time | 10644430254 ps |
| CPU time | 1046.71 seconds |
| Started | Aug 12 07:26:25 PM PDT 24 |
| Finished | Aug 12 07:43:53 PM PDT 24 |
| Peak memory | 619752 kb |
| Host | smart-025e05f6-ed72-4fbf-9d03-c002904c2d91 |
| User | root |
| Command | /workspace/default/simv +flash_program_latency=5 +use_otp_image=OtpTypeLcStRaw +dest_dec_state=DecLcStProdEnd +sw_build_device=sim_dv +sw_images=lc_wa lkthrough_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1109551357 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_walkthrough_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_lc_walkthrough_prodend.1109551357 |
| Directory | /workspace/2.chip_sw_lc_walkthrough_prodend/latest |
| Test location | /workspace/coverage/default/2.chip_sw_lc_walkthrough_rma.668162748 |
| Short name | T1374 |
| Test name | |
| Test status | |
| Simulation time | 48163024504 ps |
| CPU time | 5219.04 seconds |
| Started | Aug 12 07:24:13 PM PDT 24 |
| Finished | Aug 12 08:51:14 PM PDT 24 |
| Peak memory | 621148 kb |
| Host | smart-87c47234-d4f5-4279-b5af-c57fbbecae90 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStRaw +dest_dec_state=DecLcStRma +flash_program_latency=5 +sw_test_timeout_ns=200_000_000 +sw_build_de vice=sim_dv +sw_images=lc_walkthrough_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=668162748 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=ch ip_sw_lc_walkthrough_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_ sw_lc_walkthrough_rma.668162748 |
| Directory | /workspace/2.chip_sw_lc_walkthrough_rma/latest |
| Test location | /workspace/coverage/default/2.chip_sw_lc_walkthrough_testunlocks.466052482 |
| Short name | T1430 |
| Test name | |
| Test status | |
| Simulation time | 24132701798 ps |
| CPU time | 2339.51 seconds |
| Started | Aug 12 07:24:23 PM PDT 24 |
| Finished | Aug 12 08:03:23 PM PDT 24 |
| Peak memory | 620216 kb |
| Host | smart-1be15237-18ac-4592-a608-5dded5633531 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStRaw +dest_dec_state=DecLcStTestUnlock7 +sw_build_device=sim_dv +sw_images=lc_walkthrough_testunlocks _test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=466052482 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_walkthrough_testunlocks_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_lc_walkthrough_testunl ocks.466052482 |
| Directory | /workspace/2.chip_sw_lc_walkthrough_testunlocks/latest |
| Test location | /workspace/coverage/default/2.chip_sw_otbn_ecdsa_op_irq.1177425861 |
| Short name | T1265 |
| Test name | |
| Test status | |
| Simulation time | 16597918848 ps |
| CPU time | 3259.65 seconds |
| Started | Aug 12 07:26:01 PM PDT 24 |
| Finished | Aug 12 08:20:21 PM PDT 24 |
| Peak memory | 610668 kb |
| Host | smart-187b5c3a-6b7a-4660-97d6-c9bdb56e50c0 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=28_000_000 +rng_srate_value=30 +sw_build_device=sim_dv +sw_images=otbn_ecdsa_op_irq_test:1:new_rules,test_ rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ random_seed=1177425861 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_otbn_ecdsa_op_irq.1177425861 |
| Directory | /workspace/2.chip_sw_otbn_ecdsa_op_irq/latest |
| Test location | /workspace/coverage/default/2.chip_sw_otbn_ecdsa_op_irq_jitter_en.720744865 |
| Short name | T1091 |
| Test name | |
| Test status | |
| Simulation time | 18592689544 ps |
| CPU time | 3383.29 seconds |
| Started | Aug 12 07:25:35 PM PDT 24 |
| Finished | Aug 12 08:21:58 PM PDT 24 |
| Peak memory | 610812 kb |
| Host | smart-69ae7b40-99fd-42ad-b32e-4def6cc29de2 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=33_000_000 +rng_srate_value=30 +en_jitter=1 +sw_build_device=sim_dv +sw_images=otbn_ecdsa_op_irq_test:1:ne w_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/ sim.tcl +ntb_random_seed=720744865 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_otbn_ecdsa_op_irq_jitter_en.720744865 |
| Directory | /workspace/2.chip_sw_otbn_ecdsa_op_irq_jitter_en/latest |
| Test location | /workspace/coverage/default/2.chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq.1271548597 |
| Short name | T162 |
| Test name | |
| Test status | |
| Simulation time | 24430294870 ps |
| CPU time | 2953.13 seconds |
| Started | Aug 12 07:28:52 PM PDT 24 |
| Finished | Aug 12 08:18:06 PM PDT 24 |
| Peak memory | 610820 kb |
| Host | smart-b2f19b9f-fa7c-47b1-b499-bc3749dbe606 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=33_000_000 +rng_srate_value=30 +en_jitter=1 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=otbn_e cdsa_op_irq_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/ repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1271548597 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_otbn_ecdsa_op_irq_jitter_en_redu ced_freq.1271548597 |
| Directory | /workspace/2.chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq/latest |
| Test location | /workspace/coverage/default/2.chip_sw_otbn_mem_scramble.1819147080 |
| Short name | T290 |
| Test name | |
| Test status | |
| Simulation time | 4153933480 ps |
| CPU time | 498.76 seconds |
| Started | Aug 12 07:25:52 PM PDT 24 |
| Finished | Aug 12 07:34:11 PM PDT 24 |
| Peak memory | 610168 kb |
| Host | smart-e09b479c-ae7d-4958-99d9-4e211072bfa1 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=15_000_000 +en_scb_tl_err_chk=0 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=otbn _mem_scramble_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1819147080 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_otbn_mem_scramble.1819147080 |
| Directory | /workspace/2.chip_sw_otbn_mem_scramble/latest |
| Test location | /workspace/coverage/default/2.chip_sw_otbn_randomness.1826152479 |
| Short name | T1029 |
| Test name | |
| Test status | |
| Simulation time | 5674679898 ps |
| CPU time | 1004.4 seconds |
| Started | Aug 12 07:27:29 PM PDT 24 |
| Finished | Aug 12 07:44:13 PM PDT 24 |
| Peak memory | 610672 kb |
| Host | smart-44233c1d-755e-456d-b8df-7e00d2ec4c94 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +rng_srate_value=30 +sw_build_device=sim_dv +sw_images=otbn_randomness_test:1:new_rules,test_ro m:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=1826152479 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_otbn_randomness.1826152479 |
| Directory | /workspace/2.chip_sw_otbn_randomness/latest |
| Test location | /workspace/coverage/default/2.chip_sw_otbn_smoketest.351911009 |
| Short name | T1114 |
| Test name | |
| Test status | |
| Simulation time | 8077665334 ps |
| CPU time | 1318.85 seconds |
| Started | Aug 12 07:33:07 PM PDT 24 |
| Finished | Aug 12 07:55:06 PM PDT 24 |
| Peak memory | 610748 kb |
| Host | smart-54ac97a9-4843-460d-aa9f-f7a0a483156b |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=otbn_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=351911009 -assert nopostproc +UVM_TESTNAME=chip _base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_otbn_smoketest.351911009 |
| Directory | /workspace/2.chip_sw_otbn_smoketest/latest |
| Test location | /workspace/coverage/default/2.chip_sw_otp_ctrl_ecc_error_vendor_test.4265813544 |
| Short name | T87 |
| Test name | |
| Test status | |
| Simulation time | 3793719547 ps |
| CPU time | 339.18 seconds |
| Started | Aug 12 07:26:23 PM PDT 24 |
| Finished | Aug 12 07:32:02 PM PDT 24 |
| Peak memory | 609476 kb |
| Host | smart-e7fde128-7801-416b-843f-109892ca1cba |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=otp_ctrl_vendor_test_ecc_error_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4265813544 -assert nopostp roc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_otp_ctrl_vendor_test_ecc_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_otp_ctrl_ecc_error_vendor_test.4265813544 |
| Directory | /workspace/2.chip_sw_otp_ctrl_ecc_error_vendor_test/latest |
| Test location | /workspace/coverage/default/2.chip_sw_otp_ctrl_lc_signals_dev.1473476485 |
| Short name | T1111 |
| Test name | |
| Test status | |
| Simulation time | 10037853016 ps |
| CPU time | 1352.57 seconds |
| Started | Aug 12 07:26:26 PM PDT 24 |
| Finished | Aug 12 07:48:59 PM PDT 24 |
| Peak memory | 611092 kb |
| Host | smart-dd50b3d9-a1d8-436b-bc16-a1ff1c360efe |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStDev +otp_clear_secret2=1 +sw_build_device=sim_dv +sw_images=otp_ctrl_lc_signals_test:1:new_rules,tes t_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +nt b_random_seed=1473476485 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_otp_ctrl_lc_signals_dev.1473476485 |
| Directory | /workspace/2.chip_sw_otp_ctrl_lc_signals_dev/latest |
| Test location | /workspace/coverage/default/2.chip_sw_otp_ctrl_lc_signals_prod.2199256541 |
| Short name | T1428 |
| Test name | |
| Test status | |
| Simulation time | 8293950568 ps |
| CPU time | 1343.63 seconds |
| Started | Aug 12 07:24:53 PM PDT 24 |
| Finished | Aug 12 07:47:17 PM PDT 24 |
| Peak memory | 610824 kb |
| Host | smart-a5ab227a-72c0-4c7c-b1a4-81ea4a5cd880 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStProd +otp_clear_secret2=1 +sw_build_device=sim_dv +sw_images=otp_ctrl_lc_signals_test:1:new_rules,te st_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n tb_random_seed=2199256541 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_otp_ctrl_lc_signals_prod.2199256541 |
| Directory | /workspace/2.chip_sw_otp_ctrl_lc_signals_prod/latest |
| Test location | /workspace/coverage/default/2.chip_sw_otp_ctrl_lc_signals_rma.622505372 |
| Short name | T1311 |
| Test name | |
| Test status | |
| Simulation time | 7022601760 ps |
| CPU time | 1367.76 seconds |
| Started | Aug 12 07:25:07 PM PDT 24 |
| Finished | Aug 12 07:47:55 PM PDT 24 |
| Peak memory | 611128 kb |
| Host | smart-b46d3b12-67d1-4522-886f-7f9f1c0e8e8b |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStRma +otp_clear_secret2=1 +sw_build_device=sim_dv +sw_images=otp_ctrl_lc_signals_test:1:new_rules,tes t_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +nt b_random_seed=622505372 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_otp_ctrl_lc_signals_rma.622505372 |
| Directory | /workspace/2.chip_sw_otp_ctrl_lc_signals_rma/latest |
| Test location | /workspace/coverage/default/2.chip_sw_otp_ctrl_lc_signals_test_unlocked0.4185042096 |
| Short name | T1106 |
| Test name | |
| Test status | |
| Simulation time | 4669902492 ps |
| CPU time | 774.52 seconds |
| Started | Aug 12 07:25:01 PM PDT 24 |
| Finished | Aug 12 07:37:56 PM PDT 24 |
| Peak memory | 610340 kb |
| Host | smart-0ad8d352-87c8-4662-bc73-5dbe357a783d |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStTestUnlocked0 +otp_clear_secret2=1 +sw_build_device=sim_dv +sw_images=otp_ctrl_lc_signals_test:1:new _rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/s im.tcl +ntb_random_seed=4185042096 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_otp_ctrl_lc_signals_test_unlocked0.4185042096 |
| Directory | /workspace/2.chip_sw_otp_ctrl_lc_signals_test_unlocked0/latest |
| Test location | /workspace/coverage/default/2.chip_sw_otp_ctrl_smoketest.3860749201 |
| Short name | T1126 |
| Test name | |
| Test status | |
| Simulation time | 2287876392 ps |
| CPU time | 250.72 seconds |
| Started | Aug 12 07:33:00 PM PDT 24 |
| Finished | Aug 12 07:37:11 PM PDT 24 |
| Peak memory | 610192 kb |
| Host | smart-4f4d729a-833a-4dc1-9b46-e3ae9b658a92 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=otp_ctrl_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3860749201 -assert nopostproc +UVM_TESTNAME =chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 2.chip_sw_otp_ctrl_smoketest.3860749201 |
| Directory | /workspace/2.chip_sw_otp_ctrl_smoketest/latest |
| Test location | /workspace/coverage/default/2.chip_sw_pattgen_ios.427500558 |
| Short name | T360 |
| Test name | |
| Test status | |
| Simulation time | 3730258502 ps |
| CPU time | 356.59 seconds |
| Started | Aug 12 07:22:43 PM PDT 24 |
| Finished | Aug 12 07:28:40 PM PDT 24 |
| Peak memory | 612776 kb |
| Host | smart-61a53f02-9f49-4214-bf36-8d8da9b449b8 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=5_000_000 +sw_build_device=sim_dv +sw_images=pattgen_ios_test:1:new_rules,test_rom:0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=427500558 -asse rt nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_patt_ios_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co verage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_pattgen_ios.427500558 |
| Directory | /workspace/2.chip_sw_pattgen_ios/latest |
| Test location | /workspace/coverage/default/2.chip_sw_plic_sw_irq.1766290283 |
| Short name | T1281 |
| Test name | |
| Test status | |
| Simulation time | 2901515000 ps |
| CPU time | 294.25 seconds |
| Started | Aug 12 07:30:18 PM PDT 24 |
| Finished | Aug 12 07:35:12 PM PDT 24 |
| Peak memory | 610108 kb |
| Host | smart-e001532c-8f78-4227-872d-a1a2605bbce1 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=plic_sw_irq_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1766290283 -assert nopostproc +UVM_TESTNAME=c hip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n ull -cm_name 2.chip_sw_plic_sw_irq.1766290283 |
| Directory | /workspace/2.chip_sw_plic_sw_irq/latest |
| Test location | /workspace/coverage/default/2.chip_sw_power_idle_load.2127442769 |
| Short name | T763 |
| Test name | |
| Test status | |
| Simulation time | 4123035636 ps |
| CPU time | 658.12 seconds |
| Started | Aug 12 07:30:42 PM PDT 24 |
| Finished | Aug 12 07:41:40 PM PDT 24 |
| Peak memory | 610296 kb |
| Host | smart-1a73ab57-1e96-4722-b489-5e1abb53bb3a |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=chip_power_idle_load:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2127442769 -assert nopostproc +UVM_TESTNA ME=chip_base_test +UVM_TEST_SEQ=chip_sw_power_idle_load_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_power_idle_load.2127442769 |
| Directory | /workspace/2.chip_sw_power_idle_load/latest |
| Test location | /workspace/coverage/default/2.chip_sw_power_sleep_load.3281921758 |
| Short name | T1309 |
| Test name | |
| Test status | |
| Simulation time | 10759534372 ps |
| CPU time | 660.84 seconds |
| Started | Aug 12 07:28:58 PM PDT 24 |
| Finished | Aug 12 07:39:59 PM PDT 24 |
| Peak memory | 610328 kb |
| Host | smart-1b8b09bd-5210-4cf4-8676-df11d43378eb |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=chip_power_sleep_load:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3281921758 -assert nopostproc +UVM_TESTN AME=chip_base_test +UVM_TEST_SEQ=chip_sw_power_sleep_load_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v db -cm_log /dev/null -cm_name 2.chip_sw_power_sleep_load.3281921758 |
| Directory | /workspace/2.chip_sw_power_sleep_load/latest |
| Test location | /workspace/coverage/default/2.chip_sw_power_virus.4229923332 |
| Short name | T47 |
| Test name | |
| Test status | |
| Simulation time | 5271624480 ps |
| CPU time | 1385.06 seconds |
| Started | Aug 12 07:33:46 PM PDT 24 |
| Finished | Aug 12 07:56:52 PM PDT 24 |
| Peak memory | 625440 kb |
| Host | smart-2214c691-4bc8-4cbb-92fb-b2c55e966dde |
| User | root |
| Command | /workspace/default/simv +rng_srate_value_min=15 +rng_srate_value_max=20 +sw_test_timeout_ns=400_000_000 +use_otp_image=OtpTypeCustom +sw_build_device= sim_dv +sw_images=power_virus_systemtest:1:new_rules,power_virus_systemtest_otp_img_rma:4,test_rom:0 +accelerate_cold_power_up_time=3 +accelerate_ regulators_power_up_time=2 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d v/tools/sim.tcl +ntb_random_seed=4229923332 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_power_virus_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_power_virus.4229923332 |
| Directory | /workspace/2.chip_sw_power_virus/latest |
| Test location | /workspace/coverage/default/2.chip_sw_pwrmgr_all_reset_reqs.1336425194 |
| Short name | T550 |
| Test name | |
| Test status | |
| Simulation time | 9315210721 ps |
| CPU time | 1746.94 seconds |
| Started | Aug 12 07:27:30 PM PDT 24 |
| Finished | Aug 12 07:56:38 PM PDT 24 |
| Peak memory | 611936 kb |
| Host | smart-5560267e-5a8a-4666-bc03-62c41808b26d |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=50_000_000 +sw_build_device=sim_dv +sw_images=pwrmgr_all_reset_reqs_test:1:new_rules,test_rom:0 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1336 425194 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_deep_sleep_all_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_pwrmgr_all_reset_reqs.1336425194 |
| Directory | /workspace/2.chip_sw_pwrmgr_all_reset_reqs/latest |
| Test location | /workspace/coverage/default/2.chip_sw_pwrmgr_b2b_sleep_reset_req.1032344650 |
| Short name | T986 |
| Test name | |
| Test status | |
| Simulation time | 25152064752 ps |
| CPU time | 2562.97 seconds |
| Started | Aug 12 07:32:26 PM PDT 24 |
| Finished | Aug 12 08:15:11 PM PDT 24 |
| Peak memory | 611372 kb |
| Host | smart-7322eb52-2b61-4ff2-935f-2131102a08e8 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=35_000_000 +sw_build_device=sim_dv +sw_images=pwrmgr_b2b_sleep_reset_test:1:new_rules,test_rom:0 +cdc_inst rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=103 2344650 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_repeat_reset_wkup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_pwrmgr_b2b_sleep_reset_req.1032344650 |
| Directory | /workspace/2.chip_sw_pwrmgr_b2b_sleep_reset_req/latest |
| Test location | /workspace/coverage/default/2.chip_sw_pwrmgr_deep_sleep_all_reset_reqs.4038850230 |
| Short name | T1203 |
| Test name | |
| Test status | |
| Simulation time | 15429514185 ps |
| CPU time | 1501.57 seconds |
| Started | Aug 12 07:26:39 PM PDT 24 |
| Finished | Aug 12 07:51:40 PM PDT 24 |
| Peak memory | 611984 kb |
| Host | smart-e5151d10-71cc-4bbf-85d0-f89c5cb0c541 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=50_000_000 +sw_build_device=sim_dv +sw_images=pwrmgr_deep_sleep_all_reset_reqs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=4038850230 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_deep_sleep_all_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_pwrmgr_deep_sleep_all_reset_reqs.4038850230 |
| Directory | /workspace/2.chip_sw_pwrmgr_deep_sleep_all_reset_reqs/latest |
| Test location | /workspace/coverage/default/2.chip_sw_pwrmgr_deep_sleep_all_wake_ups.252681928 |
| Short name | T424 |
| Test name | |
| Test status | |
| Simulation time | 21704359804 ps |
| CPU time | 1568.34 seconds |
| Started | Aug 12 07:28:52 PM PDT 24 |
| Finished | Aug 12 07:55:00 PM PDT 24 |
| Peak memory | 612044 kb |
| Host | smart-fe1b5e57-fa6c-4390-8a1f-b9fce9630655 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=pwrmgr_deep_sleep_all_wake_ups:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 252681928 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_pwrmgr_deep_sleep_all_wake_ups_vseq +en_cov=1 -cm line+cond+fsm+tg l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_pwrmgr_deep_sleep_all_wake_ups.252681928 |
| Directory | /workspace/2.chip_sw_pwrmgr_deep_sleep_all_wake_ups/latest |
| Test location | /workspace/coverage/default/2.chip_sw_pwrmgr_deep_sleep_por_reset.2198115474 |
| Short name | T1408 |
| Test name | |
| Test status | |
| Simulation time | 7447959438 ps |
| CPU time | 673.54 seconds |
| Started | Aug 12 07:27:15 PM PDT 24 |
| Finished | Aug 12 07:38:28 PM PDT 24 |
| Peak memory | 611032 kb |
| Host | smart-87a53ba4-e1c2-4270-8cef-1210f8abd7de |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_deep_sleep_por_reset_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2198115474 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sleep_por_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage /default.vdb -cm_log /dev/null -cm_name 2.chip_sw_pwrmgr_deep_sleep_por_reset.2198115474 |
| Directory | /workspace/2.chip_sw_pwrmgr_deep_sleep_por_reset/latest |
| Test location | /workspace/coverage/default/2.chip_sw_pwrmgr_deep_sleep_power_glitch_reset.2314764801 |
| Short name | T1151 |
| Test name | |
| Test status | |
| Simulation time | 6416130286 ps |
| CPU time | 435.57 seconds |
| Started | Aug 12 07:25:14 PM PDT 24 |
| Finished | Aug 12 07:32:29 PM PDT 24 |
| Peak memory | 616760 kb |
| Host | smart-e24d4ce2-31ee-43c6-8733-3d9d77606e4a |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=pwrmgr_deep_sleep_power_glitch_test:1:new_rules,test_rom :0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=2314764801 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_deep_power_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_pwrmgr_deep_sleep_power_glitch_reset.2314764801 |
| Directory | /workspace/2.chip_sw_pwrmgr_deep_sleep_power_glitch_reset/latest |
| Test location | /workspace/coverage/default/2.chip_sw_pwrmgr_full_aon_reset.301722538 |
| Short name | T443 |
| Test name | |
| Test status | |
| Simulation time | 6574322320 ps |
| CPU time | 601.29 seconds |
| Started | Aug 12 07:24:08 PM PDT 24 |
| Finished | Aug 12 07:34:10 PM PDT 24 |
| Peak memory | 611152 kb |
| Host | smart-8445763a-913c-4be3-9c1c-e954108662d8 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=rstmgr_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=301722538 -assert nopostproc +UVM_TESTNAME=ch ip_base_test +UVM_TEST_SEQ=chip_sw_full_aon_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l og /dev/null -cm_name 2.chip_sw_pwrmgr_full_aon_reset.301722538 |
| Directory | /workspace/2.chip_sw_pwrmgr_full_aon_reset/latest |
| Test location | /workspace/coverage/default/2.chip_sw_pwrmgr_lowpower_cancel.1084264316 |
| Short name | T351 |
| Test name | |
| Test status | |
| Simulation time | 3435501994 ps |
| CPU time | 368.9 seconds |
| Started | Aug 12 07:28:01 PM PDT 24 |
| Finished | Aug 12 07:34:10 PM PDT 24 |
| Peak memory | 609864 kb |
| Host | smart-f8d2f90c-1e4b-4bfe-a68b-81920dc3d514 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_lowpower_cancel_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1084264316 -assert nopostproc +UVM _TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm _log /dev/null -cm_name 2.chip_sw_pwrmgr_lowpower_cancel.1084264316 |
| Directory | /workspace/2.chip_sw_pwrmgr_lowpower_cancel/latest |
| Test location | /workspace/coverage/default/2.chip_sw_pwrmgr_main_power_glitch_reset.3247415251 |
| Short name | T108 |
| Test name | |
| Test status | |
| Simulation time | 3877929356 ps |
| CPU time | 398.25 seconds |
| Started | Aug 12 07:24:26 PM PDT 24 |
| Finished | Aug 12 07:31:04 PM PDT 24 |
| Peak memory | 616744 kb |
| Host | smart-e242f37f-30c8-4486-8565-6404968c242c |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=pwrmgr_main_power_glitch_test:1:new_rules,test_rom:0 +cd c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se ed=3247415251 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_main_power_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_pwrmgr_main_power_glitch_reset.3247415251 |
| Directory | /workspace/2.chip_sw_pwrmgr_main_power_glitch_reset/latest |
| Test location | /workspace/coverage/default/2.chip_sw_pwrmgr_normal_sleep_all_reset_reqs.3550984170 |
| Short name | T1433 |
| Test name | |
| Test status | |
| Simulation time | 12710063458 ps |
| CPU time | 1269.08 seconds |
| Started | Aug 12 07:27:14 PM PDT 24 |
| Finished | Aug 12 07:48:23 PM PDT 24 |
| Peak memory | 611700 kb |
| Host | smart-9f16c3bc-8756-4909-9f47-6d8111ee5102 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_normal_sleep_all_reset_reqs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3550984170 -assert nop ostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_deep_sleep_all_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_pwrmgr_normal_sleep_all_reset_reqs.3550984170 |
| Directory | /workspace/2.chip_sw_pwrmgr_normal_sleep_all_reset_reqs/latest |
| Test location | /workspace/coverage/default/2.chip_sw_pwrmgr_normal_sleep_all_wake_ups.518007180 |
| Short name | T417 |
| Test name | |
| Test status | |
| Simulation time | 7848253968 ps |
| CPU time | 530.55 seconds |
| Started | Aug 12 07:28:28 PM PDT 24 |
| Finished | Aug 12 07:37:19 PM PDT 24 |
| Peak memory | 610756 kb |
| Host | smart-da89231b-7ec3-48c3-b42f-6d5a7e940197 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_normal_sleep_all_wake_ups:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=518007180 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_pwrmgr_deep_sleep_all_wake_ups_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work space/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_pwrmgr_normal_sleep_all_wake_ups.518007180 |
| Directory | /workspace/2.chip_sw_pwrmgr_normal_sleep_all_wake_ups/latest |
| Test location | /workspace/coverage/default/2.chip_sw_pwrmgr_normal_sleep_por_reset.349385909 |
| Short name | T287 |
| Test name | |
| Test status | |
| Simulation time | 5393210808 ps |
| CPU time | 555.79 seconds |
| Started | Aug 12 07:25:32 PM PDT 24 |
| Finished | Aug 12 07:34:49 PM PDT 24 |
| Peak memory | 610988 kb |
| Host | smart-0ec28078-3505-4e87-be24-06fb0f39796d |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_normal_sleep_por_reset_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=349385909 -assert nopostpro c +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sleep_por_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag e/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_pwrmgr_normal_sleep_por_reset.349385909 |
| Directory | /workspace/2.chip_sw_pwrmgr_normal_sleep_por_reset/latest |
| Test location | /workspace/coverage/default/2.chip_sw_pwrmgr_random_sleep_all_reset_reqs.96450551 |
| Short name | T1132 |
| Test name | |
| Test status | |
| Simulation time | 23598993741 ps |
| CPU time | 2029.54 seconds |
| Started | Aug 12 07:26:56 PM PDT 24 |
| Finished | Aug 12 08:00:46 PM PDT 24 |
| Peak memory | 611960 kb |
| Host | smart-561fda2c-99d1-4964-beb7-b17ed56e1440 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=50_000_000 +sw_build_device=sim_dv +sw_images=pwrmgr_random_sleep_all_reset_reqs_test:1:new_rules,test_rom :0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=96450551 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_deep_sleep_all_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_pwrmgr_random_sleep_all_reset_reqs.96450551 |
| Directory | /workspace/2.chip_sw_pwrmgr_random_sleep_all_reset_reqs/latest |
| Test location | /workspace/coverage/default/2.chip_sw_pwrmgr_random_sleep_all_wake_ups.3624116927 |
| Short name | T105 |
| Test name | |
| Test status | |
| Simulation time | 23252439916 ps |
| CPU time | 1180.72 seconds |
| Started | Aug 12 07:28:20 PM PDT 24 |
| Finished | Aug 12 07:48:01 PM PDT 24 |
| Peak memory | 611192 kb |
| Host | smart-515017d5-e22d-4eda-ad45-6492b3b19cb8 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +do_random=1 +sw_build_device=sim_dv +sw_images=pwrmgr_random_sleep_all_wake_ups:1:new_rules,te st_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n tb_random_seed=3624116927 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_pwrmgr_deep_sleep_all_wake_ups_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_pwrmgr_random_sleep_all_wake_ups.3624116927 |
| Directory | /workspace/2.chip_sw_pwrmgr_random_sleep_all_wake_ups/latest |
| Test location | /workspace/coverage/default/2.chip_sw_pwrmgr_random_sleep_power_glitch_reset.1613244398 |
| Short name | T1018 |
| Test name | |
| Test status | |
| Simulation time | 36987346729 ps |
| CPU time | 3199.79 seconds |
| Started | Aug 12 07:27:05 PM PDT 24 |
| Finished | Aug 12 08:20:26 PM PDT 24 |
| Peak memory | 612468 kb |
| Host | smart-5269cdf3-372d-4c31-bcda-4daa0edb9c00 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_test_timeout_ns=24_000_000 +sw_build_device=sim_dv +sw_images=pwrmgr_random_sleep_power _glitch_reset_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1613244398 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_random_power_glit ch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_pwrmgr_random_s leep_power_glitch_reset.1613244398 |
| Directory | /workspace/2.chip_sw_pwrmgr_random_sleep_power_glitch_reset/latest |
| Test location | /workspace/coverage/default/2.chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up.634656354 |
| Short name | T384 |
| Test name | |
| Test status | |
| Simulation time | 5613194848 ps |
| CPU time | 410.9 seconds |
| Started | Aug 12 07:28:53 PM PDT 24 |
| Finished | Aug 12 07:35:45 PM PDT 24 |
| Peak memory | 611688 kb |
| Host | smart-e2fde1ab-a0e1-4fa8-b9fe-094754b18a48 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +do_random=1 +sw_build_device=sim_dv +sw_images=pwrmgr_sensor_ctrl_deep_sleep_wake_up:1:new_rul es,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t cl +ntb_random_seed=634656354 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_pwrmgr_sensor_ctrl_deep_sl eep_wake_up.634656354 |
| Directory | /workspace/2.chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up/latest |
| Test location | /workspace/coverage/default/2.chip_sw_pwrmgr_sleep_disabled.1629209523 |
| Short name | T1201 |
| Test name | |
| Test status | |
| Simulation time | 3266532700 ps |
| CPU time | 337.69 seconds |
| Started | Aug 12 07:25:51 PM PDT 24 |
| Finished | Aug 12 07:31:29 PM PDT 24 |
| Peak memory | 610236 kb |
| Host | smart-a149ce71-7b6e-4bb7-b8fc-0e3ab5da9328 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_sleep_disabled_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1629209523 -assert nopostproc +UVM_ TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_ log /dev/null -cm_name 2.chip_sw_pwrmgr_sleep_disabled.1629209523 |
| Directory | /workspace/2.chip_sw_pwrmgr_sleep_disabled/latest |
| Test location | /workspace/coverage/default/2.chip_sw_pwrmgr_sleep_power_glitch_reset.112691358 |
| Short name | T994 |
| Test name | |
| Test status | |
| Simulation time | 5186238484 ps |
| CPU time | 593.07 seconds |
| Started | Aug 12 07:24:58 PM PDT 24 |
| Finished | Aug 12 07:34:51 PM PDT 24 |
| Peak memory | 616996 kb |
| Host | smart-134845bd-16fb-4608-9b3d-51ffd7d01164 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=pwrmgr_sleep_power_glitch_test:1:new_rules,test_rom:0 +c dc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_s eed=112691358 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_main_power_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_pwrmgr_sleep_power_glitch_reset.112691358 |
| Directory | /workspace/2.chip_sw_pwrmgr_sleep_power_glitch_reset/latest |
| Test location | /workspace/coverage/default/2.chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup.3365596868 |
| Short name | T141 |
| Test name | |
| Test status | |
| Simulation time | 5782618220 ps |
| CPU time | 560.59 seconds |
| Started | Aug 12 07:27:46 PM PDT 24 |
| Finished | Aug 12 07:37:07 PM PDT 24 |
| Peak memory | 609464 kb |
| Host | smart-ef25d50b-aed5-4dbe-bbbf-f8584e9b898f |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=8_000_000 +sw_build_device=sim_dv +sw_images=sensor_ctrl_wakeup_test:1:new_rules,test_rom:0 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33655968 68 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac e/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup.3365596868 |
| Directory | /workspace/2.chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup/latest |
| Test location | /workspace/coverage/default/2.chip_sw_pwrmgr_sleep_wake_5_bug.2072706517 |
| Short name | T131 |
| Test name | |
| Test status | |
| Simulation time | 5939863640 ps |
| CPU time | 546.54 seconds |
| Started | Aug 12 07:28:59 PM PDT 24 |
| Finished | Aug 12 07:38:06 PM PDT 24 |
| Peak memory | 611212 kb |
| Host | smart-24c20b23-2bc9-41c3-8c68-16d7121a7acd |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +do_random=1 +sw_build_device=sim_dv +sw_images=pwrmgr_sleep_wake_5_bug_test:1:new_rules,test_r om:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r andom_seed=2072706517 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_pwrmgr_sleep_wake_5_bug.2072706517 |
| Directory | /workspace/2.chip_sw_pwrmgr_sleep_wake_5_bug/latest |
| Test location | /workspace/coverage/default/2.chip_sw_pwrmgr_smoketest.4032911624 |
| Short name | T112 |
| Test name | |
| Test status | |
| Simulation time | 4929293402 ps |
| CPU time | 475.8 seconds |
| Started | Aug 12 07:30:40 PM PDT 24 |
| Finished | Aug 12 07:38:36 PM PDT 24 |
| Peak memory | 610844 kb |
| Host | smart-4c9de6d7-2ffb-4151-86ab-3a1654acc33b |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=10000000 +sw_build_device=sim_dv +sw_images=pwrmgr_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4032911624 -asse rt nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera ge/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_pwrmgr_smoketest.4032911624 |
| Directory | /workspace/2.chip_sw_pwrmgr_smoketest/latest |
| Test location | /workspace/coverage/default/2.chip_sw_pwrmgr_sysrst_ctrl_reset.3663757886 |
| Short name | T258 |
| Test name | |
| Test status | |
| Simulation time | 6282078634 ps |
| CPU time | 1000.12 seconds |
| Started | Aug 12 07:24:25 PM PDT 24 |
| Finished | Aug 12 07:41:06 PM PDT 24 |
| Peak memory | 611280 kb |
| Host | smart-141bef45-555c-4e49-9951-f6c22c7b858d |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_sysrst_ctrl_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3663757886 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sysrst_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_pwrmgr_sysrst_ctrl_reset.3663757886 |
| Directory | /workspace/2.chip_sw_pwrmgr_sysrst_ctrl_reset/latest |
| Test location | /workspace/coverage/default/2.chip_sw_pwrmgr_usb_clk_disabled_when_active.227498537 |
| Short name | T1358 |
| Test name | |
| Test status | |
| Simulation time | 4257141480 ps |
| CPU time | 783.7 seconds |
| Started | Aug 12 07:24:48 PM PDT 24 |
| Finished | Aug 12 07:37:52 PM PDT 24 |
| Peak memory | 609796 kb |
| Host | smart-1c1749e2-10a0-453b-a9e6-1e5a395c31e6 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_usb_clk_disabled_when_active_test:1:new_rules,test_rom:0 +cdc_instrumentation_enable d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=227498537 -assert nop ostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def ault.vdb -cm_log /dev/null -cm_name 2.chip_sw_pwrmgr_usb_clk_disabled_when_active.227498537 |
| Directory | /workspace/2.chip_sw_pwrmgr_usb_clk_disabled_when_active/latest |
| Test location | /workspace/coverage/default/2.chip_sw_pwrmgr_usbdev_smoketest.3001697472 |
| Short name | T1429 |
| Test name | |
| Test status | |
| Simulation time | 5094841094 ps |
| CPU time | 532.89 seconds |
| Started | Aug 12 07:29:33 PM PDT 24 |
| Finished | Aug 12 07:38:26 PM PDT 24 |
| Peak memory | 609932 kb |
| Host | smart-570881cc-d2f3-4021-9d2c-ecc4b3f73f30 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_usbdev_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3001697472 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_pwrmgr_usbdev_smoketest.3001697472 |
| Directory | /workspace/2.chip_sw_pwrmgr_usbdev_smoketest/latest |
| Test location | /workspace/coverage/default/2.chip_sw_pwrmgr_wdog_reset.416109710 |
| Short name | T1266 |
| Test name | |
| Test status | |
| Simulation time | 4897473110 ps |
| CPU time | 566.83 seconds |
| Started | Aug 12 07:26:05 PM PDT 24 |
| Finished | Aug 12 07:35:32 PM PDT 24 |
| Peak memory | 610828 kb |
| Host | smart-adbb1655-aa48-44c1-89e6-98c7dd60de25 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=pwrmgr_wdog_reset_reqs_test:1:new_rules,test_rom:0 +cdc_inst rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=416 109710 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work space/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_pwrmgr_wdog_reset.416109710 |
| Directory | /workspace/2.chip_sw_pwrmgr_wdog_reset/latest |
| Test location | /workspace/coverage/default/2.chip_sw_rom_ctrl_integrity_check.1872804848 |
| Short name | T1214 |
| Test name | |
| Test status | |
| Simulation time | 9123581980 ps |
| CPU time | 530.97 seconds |
| Started | Aug 12 07:28:34 PM PDT 24 |
| Finished | Aug 12 07:37:25 PM PDT 24 |
| Peak memory | 610612 kb |
| Host | smart-76ac6719-eadb-43af-abd1-32dac980dcdb |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=rom_ctrl_integrity_check_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1872804848 -assert nopostproc +U VM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rom_ctrl_integrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co verage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_rom_ctrl_integrity_check.1872804848 |
| Directory | /workspace/2.chip_sw_rom_ctrl_integrity_check/latest |
| Test location | /workspace/coverage/default/2.chip_sw_rstmgr_alert_info.255193483 |
| Short name | T339 |
| Test name | |
| Test status | |
| Simulation time | 12539086910 ps |
| CPU time | 1605.18 seconds |
| Started | Aug 12 07:28:03 PM PDT 24 |
| Finished | Aug 12 07:54:49 PM PDT 24 |
| Peak memory | 611328 kb |
| Host | smart-6cb66fe6-a846-496b-9274-dd0480057983 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=30_000_000 +en_scb_tl_err_chk=0 +sw_build_device=sim_dv +sw_images=rstmgr_alert_info_test:1:new_rules,test _rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb _random_seed=255193483 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_rstmgr_alert_info.255193483 |
| Directory | /workspace/2.chip_sw_rstmgr_alert_info/latest |
| Test location | /workspace/coverage/default/2.chip_sw_rstmgr_cpu_info.614645509 |
| Short name | T266 |
| Test name | |
| Test status | |
| Simulation time | 6213197560 ps |
| CPU time | 558.75 seconds |
| Started | Aug 12 07:26:13 PM PDT 24 |
| Finished | Aug 12 07:35:32 PM PDT 24 |
| Peak memory | 610884 kb |
| Host | smart-7faf3c30-b80f-4df7-a731-9e588781c6c1 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=rstmgr_cpu_info_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=614645509 -assert nopostproc +UVM_TESTNAM E=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 2.chip_sw_rstmgr_cpu_info.614645509 |
| Directory | /workspace/2.chip_sw_rstmgr_cpu_info/latest |
| Test location | /workspace/coverage/default/2.chip_sw_rstmgr_rst_cnsty_escalation.3806931854 |
| Short name | T1092 |
| Test name | |
| Test status | |
| Simulation time | 5449155484 ps |
| CPU time | 795.26 seconds |
| Started | Aug 12 07:22:29 PM PDT 24 |
| Finished | Aug 12 07:35:45 PM PDT 24 |
| Peak memory | 642072 kb |
| Host | smart-79aab153-bfe3-41ab-a238-6b43d716a54d |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 3806931854 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rstmgr_cnsty_fault_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_rstmgr_rst_cnsty_escalation.3806931854 |
| Directory | /workspace/2.chip_sw_rstmgr_rst_cnsty_escalation/latest |
| Test location | /workspace/coverage/default/2.chip_sw_rstmgr_smoketest.4101203951 |
| Short name | T1248 |
| Test name | |
| Test status | |
| Simulation time | 2544559000 ps |
| CPU time | 317.49 seconds |
| Started | Aug 12 07:31:03 PM PDT 24 |
| Finished | Aug 12 07:36:21 PM PDT 24 |
| Peak memory | 609796 kb |
| Host | smart-ba2b519b-f8bf-4e2b-9bb7-e18bc7782156 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=rstmgr_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4101203951 -assert nopostproc +UVM_TESTNAME=c hip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n ull -cm_name 2.chip_sw_rstmgr_smoketest.4101203951 |
| Directory | /workspace/2.chip_sw_rstmgr_smoketest/latest |
| Test location | /workspace/coverage/default/2.chip_sw_rstmgr_sw_req.2335161227 |
| Short name | T1035 |
| Test name | |
| Test status | |
| Simulation time | 4153222248 ps |
| CPU time | 632.98 seconds |
| Started | Aug 12 07:26:19 PM PDT 24 |
| Finished | Aug 12 07:36:52 PM PDT 24 |
| Peak memory | 609764 kb |
| Host | smart-bdf9881f-c562-4d35-baed-8e91acc3336c |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=rstmgr_sw_req_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2335161227 -assert nopostproc +UVM_TESTNAME =chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 2.chip_sw_rstmgr_sw_req.2335161227 |
| Directory | /workspace/2.chip_sw_rstmgr_sw_req/latest |
| Test location | /workspace/coverage/default/2.chip_sw_rstmgr_sw_rst.3957566683 |
| Short name | T1158 |
| Test name | |
| Test status | |
| Simulation time | 2927785224 ps |
| CPU time | 185.99 seconds |
| Started | Aug 12 07:24:38 PM PDT 24 |
| Finished | Aug 12 07:27:44 PM PDT 24 |
| Peak memory | 609760 kb |
| Host | smart-1d26df9a-fa1d-45b6-95e5-fe661b3ddb9b |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=rstmgr_sw_rst_ctrl_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3957566683 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_rstmgr_sw_rst.3957566683 |
| Directory | /workspace/2.chip_sw_rstmgr_sw_rst/latest |
| Test location | /workspace/coverage/default/2.chip_sw_rv_core_ibex_address_translation.1099213050 |
| Short name | T189 |
| Test name | |
| Test status | |
| Simulation time | 2795763120 ps |
| CPU time | 355.51 seconds |
| Started | Aug 12 07:28:50 PM PDT 24 |
| Finished | Aug 12 07:34:45 PM PDT 24 |
| Peak memory | 609124 kb |
| Host | smart-d73d2af0-ad42-4d0b-8963-24744d66bf40 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=7_000_000 +sw_build_device=sim_dv +sw_images=rv_core_ibex_address_translation_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random _seed=1099213050 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_rv_core_ibex_address_translation.1099213050 |
| Directory | /workspace/2.chip_sw_rv_core_ibex_address_translation/latest |
| Test location | /workspace/coverage/default/2.chip_sw_rv_core_ibex_icache_invalidate.113872289 |
| Short name | T192 |
| Test name | |
| Test status | |
| Simulation time | 2791007718 ps |
| CPU time | 299.08 seconds |
| Started | Aug 12 07:29:19 PM PDT 24 |
| Finished | Aug 12 07:34:19 PM PDT 24 |
| Peak memory | 609920 kb |
| Host | smart-b0277fce-5db9-4efc-8d20-574a76657f4e |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=rv_core_ibex_icache_invalidate_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=113872289 -assert nopostpr oc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rv_core_ibex_icache_invalidate_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_rv_core_ibex_icache_invalidate.113872289 |
| Directory | /workspace/2.chip_sw_rv_core_ibex_icache_invalidate/latest |
| Test location | /workspace/coverage/default/2.chip_sw_rv_core_ibex_nmi_irq.1477407991 |
| Short name | T549 |
| Test name | |
| Test status | |
| Simulation time | 4612853256 ps |
| CPU time | 845.09 seconds |
| Started | Aug 12 07:25:41 PM PDT 24 |
| Finished | Aug 12 07:39:46 PM PDT 24 |
| Peak memory | 610560 kb |
| Host | smart-37bef21a-84e3-4231-90bf-d9ef85d65d44 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=10_000_000 +sw_build_device=sim_dv +sw_images=rv_core_ibex_nmi_irq_test:1:new_rules,test_rom:0 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14774 07991 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_rv_core_ibex_nmi_irq.1477407991 |
| Directory | /workspace/2.chip_sw_rv_core_ibex_nmi_irq/latest |
| Test location | /workspace/coverage/default/2.chip_sw_rv_core_ibex_rnd.1925901424 |
| Short name | T433 |
| Test name | |
| Test status | |
| Simulation time | 5879662506 ps |
| CPU time | 1099.26 seconds |
| Started | Aug 12 07:26:03 PM PDT 24 |
| Finished | Aug 12 07:44:22 PM PDT 24 |
| Peak memory | 610400 kb |
| Host | smart-0e9b5680-a29a-43ea-af87-210b0a08df35 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=20_000_000 +rng_srate_value_max=32 +sw_build_device=sim_dv +sw_images=rv_core_ibex_rnd_test:1:new_rules,te st_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n tb_random_seed=1925901424 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_rv_core_ibex_rnd.1925901424 |
| Directory | /workspace/2.chip_sw_rv_core_ibex_rnd/latest |
| Test location | /workspace/coverage/default/2.chip_sw_rv_dm_access_after_escalation_reset.2380892364 |
| Short name | T751 |
| Test name | |
| Test status | |
| Simulation time | 5862027110 ps |
| CPU time | 508.1 seconds |
| Started | Aug 12 07:29:49 PM PDT 24 |
| Finished | Aug 12 07:38:18 PM PDT 24 |
| Peak memory | 624708 kb |
| Host | smart-99f8ba9f-bcd7-49c7-a5db-0a5ebc66d898 |
| User | root |
| Command | /workspace/default/simv +use_jtag_dmi=1 +sw_build_device=sim_dv +sw_images=alert_handler_escalation_test:1:new_rules,test_rom:0 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2380892364 -asse rt nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rv_dm_access_after_escalation_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_rv_dm_access_after_escalation_reset.2380892364 |
| Directory | /workspace/2.chip_sw_rv_dm_access_after_escalation_reset/latest |
| Test location | /workspace/coverage/default/2.chip_sw_rv_dm_access_after_wakeup.1427738124 |
| Short name | T438 |
| Test name | |
| Test status | |
| Simulation time | 5727293572 ps |
| CPU time | 436.86 seconds |
| Started | Aug 12 07:29:23 PM PDT 24 |
| Finished | Aug 12 07:36:40 PM PDT 24 |
| Peak memory | 621388 kb |
| Host | smart-99e211a3-1a2a-4457-9afa-1164bde3843d |
| User | root |
| Command | /workspace/default/simv +use_jtag_dmi=1 +sw_build_device=sim_dv +sw_images=rv_dm_access_after_wakeup_rma:1:new_rules,test_rom:0 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1427738124 -asse rt nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rv_dm_access_after_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_rv_dm_access_after_wakeup.1427738124 |
| Directory | /workspace/2.chip_sw_rv_dm_access_after_wakeup/latest |
| Test location | /workspace/coverage/default/2.chip_sw_rv_dm_ndm_reset_req_when_cpu_halted.3810546864 |
| Short name | T1404 |
| Test name | |
| Test status | |
| Simulation time | 4575621506 ps |
| CPU time | 442.61 seconds |
| Started | Aug 12 07:28:49 PM PDT 24 |
| Finished | Aug 12 07:36:11 PM PDT 24 |
| Peak memory | 619384 kb |
| Host | smart-0afa518a-ff2b-4abf-b1b2-43da3ef8c0fe |
| User | root |
| Command | /workspace/default/simv +use_jtag_dmi=1 +sw_build_device=sim_dv +sw_images=rv_dm_ndm_reset_req_when_cpu_halted_rma:1:new_rules,test_rom:0 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=381054 6864 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rv_dm_ndm_reset_when_cpu_halted_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_rv_dm_ndm_reset_req_when_cpu_halted.3810546864 |
| Directory | /workspace/2.chip_sw_rv_dm_ndm_reset_req_when_cpu_halted/latest |
| Test location | /workspace/coverage/default/2.chip_sw_rv_plic_smoketest.2249331755 |
| Short name | T969 |
| Test name | |
| Test status | |
| Simulation time | 2802883548 ps |
| CPU time | 249.09 seconds |
| Started | Aug 12 07:31:45 PM PDT 24 |
| Finished | Aug 12 07:35:54 PM PDT 24 |
| Peak memory | 608800 kb |
| Host | smart-43cba4e5-48a7-472b-8608-7948b5e8339a |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=rv_plic_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2249331755 -assert nopostproc +UVM_TESTNAME= chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/ null -cm_name 2.chip_sw_rv_plic_smoketest.2249331755 |
| Directory | /workspace/2.chip_sw_rv_plic_smoketest/latest |
| Test location | /workspace/coverage/default/2.chip_sw_rv_timer_irq.3644223153 |
| Short name | T255 |
| Test name | |
| Test status | |
| Simulation time | 3399180584 ps |
| CPU time | 329.83 seconds |
| Started | Aug 12 07:24:48 PM PDT 24 |
| Finished | Aug 12 07:30:18 PM PDT 24 |
| Peak memory | 609720 kb |
| Host | smart-f29106d4-6ec1-4bc8-99d2-7498e9b32c98 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=rv_timer_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3644223153 -assert nopostproc +UVM_TESTNAME =chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 2.chip_sw_rv_timer_irq.3644223153 |
| Directory | /workspace/2.chip_sw_rv_timer_irq/latest |
| Test location | /workspace/coverage/default/2.chip_sw_rv_timer_smoketest.3172567169 |
| Short name | T1121 |
| Test name | |
| Test status | |
| Simulation time | 2806679600 ps |
| CPU time | 257 seconds |
| Started | Aug 12 07:30:28 PM PDT 24 |
| Finished | Aug 12 07:34:45 PM PDT 24 |
| Peak memory | 608776 kb |
| Host | smart-f902fbf6-61d1-494c-a464-75446475e5a8 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=rv_timer_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3172567169 -assert nopostproc +UVM_TESTNAME =chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 2.chip_sw_rv_timer_smoketest.3172567169 |
| Directory | /workspace/2.chip_sw_rv_timer_smoketest/latest |
| Test location | /workspace/coverage/default/2.chip_sw_sensor_ctrl_status.2792602098 |
| Short name | T1246 |
| Test name | |
| Test status | |
| Simulation time | 2953228306 ps |
| CPU time | 327.96 seconds |
| Started | Aug 12 07:30:38 PM PDT 24 |
| Finished | Aug 12 07:36:07 PM PDT 24 |
| Peak memory | 611112 kb |
| Host | smart-794a5e56-b423-4f54-a8fe-740cdfb40ef6 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=40_000_000 +sw_build_device=sim_dv +sw_images=sensor_ctrl_status_test:1:new_rules,test_rom:0 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2792602 098 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sensor_ctrl_status_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_sensor_ctrl_status.2792602098 |
| Directory | /workspace/2.chip_sw_sensor_ctrl_status/latest |
| Test location | /workspace/coverage/default/2.chip_sw_sleep_pwm_pulses.1525407819 |
| Short name | T1348 |
| Test name | |
| Test status | |
| Simulation time | 9014139674 ps |
| CPU time | 1287.33 seconds |
| Started | Aug 12 07:22:36 PM PDT 24 |
| Finished | Aug 12 07:44:04 PM PDT 24 |
| Peak memory | 611272 kb |
| Host | smart-86d8ddbd-34a4-4043-9365-aeca4652be76 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=sleep_pwm_pulses_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1525407819 -assert nopostproc +UVM_TESTN AME=chip_base_test +UVM_TEST_SEQ=chip_sw_pwm_pulses_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm _log /dev/null -cm_name 2.chip_sw_sleep_pwm_pulses.1525407819 |
| Directory | /workspace/2.chip_sw_sleep_pwm_pulses/latest |
| Test location | /workspace/coverage/default/2.chip_sw_sleep_sram_ret_contents_no_scramble.4267851868 |
| Short name | T1353 |
| Test name | |
| Test status | |
| Simulation time | 9111102730 ps |
| CPU time | 762.09 seconds |
| Started | Aug 12 07:30:40 PM PDT 24 |
| Finished | Aug 12 07:43:22 PM PDT 24 |
| Peak memory | 611052 kb |
| Host | smart-fe8fd355-f1f0-45a3-a710-4dcce95e00dd |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=20_000_000 +en_scb_tl_err_chk=0 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=sram _ctrl_sleep_sram_ret_contents_no_scramble_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4267851868 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_S EQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_sl eep_sram_ret_contents_no_scramble.4267851868 |
| Directory | /workspace/2.chip_sw_sleep_sram_ret_contents_no_scramble/latest |
| Test location | /workspace/coverage/default/2.chip_sw_sleep_sram_ret_contents_scramble.2747639470 |
| Short name | T1133 |
| Test name | |
| Test status | |
| Simulation time | 8620690254 ps |
| CPU time | 656.07 seconds |
| Started | Aug 12 07:30:21 PM PDT 24 |
| Finished | Aug 12 07:41:18 PM PDT 24 |
| Peak memory | 610804 kb |
| Host | smart-3723a6fd-3cb3-484d-ac69-d6e48fc83b44 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=20_000_000 +en_scb_tl_err_chk=0 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=sram _ctrl_sleep_sram_ret_contents_scramble_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2747639470 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ= chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_sleep _sram_ret_contents_scramble.2747639470 |
| Directory | /workspace/2.chip_sw_sleep_sram_ret_contents_scramble/latest |
| Test location | /workspace/coverage/default/2.chip_sw_spi_device_pass_through.1045353298 |
| Short name | T14 |
| Test name | |
| Test status | |
| Simulation time | 6877377754 ps |
| CPU time | 686.52 seconds |
| Started | Aug 12 07:24:41 PM PDT 24 |
| Finished | Aug 12 07:36:08 PM PDT 24 |
| Peak memory | 625228 kb |
| Host | smart-47d0e717-bc6c-4ba4-9945-e5a236873f90 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=spi_passthrough_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1045353298 -assert nopostproc +UVM_TESTNA ME=chip_base_test +UVM_TEST_SEQ=chip_sw_spi_passthrough_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_spi_device_pass_through.1045353298 |
| Directory | /workspace/2.chip_sw_spi_device_pass_through/latest |
| Test location | /workspace/coverage/default/2.chip_sw_spi_device_pass_through_collision.1851248821 |
| Short name | T100 |
| Test name | |
| Test status | |
| Simulation time | 4984784906 ps |
| CPU time | 561.43 seconds |
| Started | Aug 12 07:25:08 PM PDT 24 |
| Finished | Aug 12 07:34:30 PM PDT 24 |
| Peak memory | 625260 kb |
| Host | smart-17159622-bb6e-4616-a4a0-946a7d57e82b |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=spi_passthrough_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1851248821 -assert nopostproc +UVM_TESTNA ME=chip_base_test +UVM_TEST_SEQ=chip_sw_spi_passthrough_collision_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/d efault.vdb -cm_log /dev/null -cm_name 2.chip_sw_spi_device_pass_through_collision.1851248821 |
| Directory | /workspace/2.chip_sw_spi_device_pass_through_collision/latest |
| Test location | /workspace/coverage/default/2.chip_sw_spi_device_pinmux_sleep_retention.2805861394 |
| Short name | T63 |
| Test name | |
| Test status | |
| Simulation time | 3493222241 ps |
| CPU time | 356.94 seconds |
| Started | Aug 12 07:24:37 PM PDT 24 |
| Finished | Aug 12 07:30:35 PM PDT 24 |
| Peak memory | 619484 kb |
| Host | smart-bcd478f7-9a56-435d-be1e-201669de09dd |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=spi_device_sleep_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2805861394 -assert nopostproc +UVM_TESTN AME=chip_base_test +UVM_TEST_SEQ=chip_sw_spi_device_pinmux_sleep_retention_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/c overage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_spi_device_pinmux_sleep_retention.2805861394 |
| Directory | /workspace/2.chip_sw_spi_device_pinmux_sleep_retention/latest |
| Test location | /workspace/coverage/default/2.chip_sw_spi_device_tpm.3190843974 |
| Short name | T43 |
| Test name | |
| Test status | |
| Simulation time | 3280579066 ps |
| CPU time | 401.03 seconds |
| Started | Aug 12 07:24:09 PM PDT 24 |
| Finished | Aug 12 07:30:50 PM PDT 24 |
| Peak memory | 619884 kb |
| Host | smart-374ed541-ba49-4887-8fd7-bd195dc94125 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=spi_device_tpm_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3190843974 -assert nopostproc +UVM_T ESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_spi_device_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default .vdb -cm_log /dev/null -cm_name 2.chip_sw_spi_device_tpm.3190843974 |
| Directory | /workspace/2.chip_sw_spi_device_tpm/latest |
| Test location | /workspace/coverage/default/2.chip_sw_spi_host_tx_rx.2353492646 |
| Short name | T36 |
| Test name | |
| Test status | |
| Simulation time | 3150860784 ps |
| CPU time | 323.78 seconds |
| Started | Aug 12 07:23:33 PM PDT 24 |
| Finished | Aug 12 07:28:57 PM PDT 24 |
| Peak memory | 610620 kb |
| Host | smart-f3109330-3df6-4ce1-a34a-0d573a94c011 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=spi_host_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2353492646 -assert nopostproc +UVM_TESTNAM E=chip_base_test +UVM_TEST_SEQ=chip_sw_spi_host_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb - cm_log /dev/null -cm_name 2.chip_sw_spi_host_tx_rx.2353492646 |
| Directory | /workspace/2.chip_sw_spi_host_tx_rx/latest |
| Test location | /workspace/coverage/default/2.chip_sw_sram_ctrl_execution_main.1164213170 |
| Short name | T190 |
| Test name | |
| Test status | |
| Simulation time | 7473020227 ps |
| CPU time | 630.2 seconds |
| Started | Aug 12 07:29:21 PM PDT 24 |
| Finished | Aug 12 07:39:51 PM PDT 24 |
| Peak memory | 611044 kb |
| Host | smart-86801b86-ea0b-4f60-8eaa-20df6a76ab94 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=sram_ctrl_execution_main_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1164213170 -assert nopostproc +U VM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sram_ctrl_execution_main_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co verage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_sram_ctrl_execution_main.1164213170 |
| Directory | /workspace/2.chip_sw_sram_ctrl_execution_main/latest |
| Test location | /workspace/coverage/default/2.chip_sw_sram_ctrl_scrambled_access_jitter_en.3725012871 |
| Short name | T1272 |
| Test name | |
| Test status | |
| Simulation time | 4892217489 ps |
| CPU time | 711.36 seconds |
| Started | Aug 12 07:27:27 PM PDT 24 |
| Finished | Aug 12 07:39:19 PM PDT 24 |
| Peak memory | 611580 kb |
| Host | smart-d64b946d-e686-49ff-a0e4-8b435bc370df |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=12_000_000 +bypass_alert_ready_to_end_check=1 +en_jitter=1 +en_scb_tl_err_chk=0 +sw_build_device=sim_dv +s w_images=sram_ctrl_scrambled_access_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3725012871 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chi p_sw_sram_ctrl_scrambled_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n ame 2.chip_sw_sram_ctrl_scrambled_access_jitter_en.3725012871 |
| Directory | /workspace/2.chip_sw_sram_ctrl_scrambled_access_jitter_en/latest |
| Test location | /workspace/coverage/default/2.chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq.4291235230 |
| Short name | T187 |
| Test name | |
| Test status | |
| Simulation time | 4246886373 ps |
| CPU time | 547.07 seconds |
| Started | Aug 12 07:29:03 PM PDT 24 |
| Finished | Aug 12 07:38:11 PM PDT 24 |
| Peak memory | 611348 kb |
| Host | smart-6f6563a2-370c-49db-824e-d201d129e837 |
| User | root |
| Command | /workspace/default/simv +mem_sel=main +sw_test_timeout_ns=12_000_000 +bypass_alert_ready_to_end_check=1 +en_jitter=1 +en_scb_tl_err_chk=0 +cal_sys_clk _70mhz=1 +sw_build_device=sim_dv +sw_images=sram_ctrl_scrambled_access_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4291235230 -assert nopostproc +UVM_TESTNA ME=chip_base_test +UVM_TEST_SEQ=chip_sw_sram_ctrl_scrambled_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/ default.vdb -cm_log /dev/null -cm_name 2.chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq.4291235230 |
| Directory | /workspace/2.chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq/latest |
| Test location | /workspace/coverage/default/2.chip_sw_sram_ctrl_smoketest.3181177689 |
| Short name | T1072 |
| Test name | |
| Test status | |
| Simulation time | 2517008210 ps |
| CPU time | 270.13 seconds |
| Started | Aug 12 07:30:16 PM PDT 24 |
| Finished | Aug 12 07:34:46 PM PDT 24 |
| Peak memory | 609868 kb |
| Host | smart-b5f9fffb-6f55-4201-b6e7-cfcaa49fab78 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=sram_ctrl_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3181177689 -assert nopostproc +UVM_TESTNAM E=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 2.chip_sw_sram_ctrl_smoketest.3181177689 |
| Directory | /workspace/2.chip_sw_sram_ctrl_smoketest/latest |
| Test location | /workspace/coverage/default/2.chip_sw_sysrst_ctrl_ec_rst_l.2655533005 |
| Short name | T428 |
| Test name | |
| Test status | |
| Simulation time | 20322925756 ps |
| CPU time | 2829.16 seconds |
| Started | Aug 12 07:24:26 PM PDT 24 |
| Finished | Aug 12 08:11:36 PM PDT 24 |
| Peak memory | 611220 kb |
| Host | smart-8f8f7562-5dc9-4bef-88bd-d141751289d1 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=sysrst_ctrl_ec_rst_l_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2655533005 -assert nopostproc +UVM_T ESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sysrst_ctrl_ec_rst_l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/d efault.vdb -cm_log /dev/null -cm_name 2.chip_sw_sysrst_ctrl_ec_rst_l.2655533005 |
| Directory | /workspace/2.chip_sw_sysrst_ctrl_ec_rst_l/latest |
| Test location | /workspace/coverage/default/2.chip_sw_sysrst_ctrl_in_irq.2981641008 |
| Short name | T217 |
| Test name | |
| Test status | |
| Simulation time | 4438258723 ps |
| CPU time | 624.83 seconds |
| Started | Aug 12 07:24:26 PM PDT 24 |
| Finished | Aug 12 07:34:54 PM PDT 24 |
| Peak memory | 614196 kb |
| Host | smart-0050413a-14f2-41a1-a938-b20a6cb4f18a |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=sysrst_ctrl_in_irq_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2981641008 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sysrst_ctrl_in_irq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau lt.vdb -cm_log /dev/null -cm_name 2.chip_sw_sysrst_ctrl_in_irq.2981641008 |
| Directory | /workspace/2.chip_sw_sysrst_ctrl_in_irq/latest |
| Test location | /workspace/coverage/default/2.chip_sw_sysrst_ctrl_inputs.1094327065 |
| Short name | T214 |
| Test name | |
| Test status | |
| Simulation time | 3661120066 ps |
| CPU time | 325.32 seconds |
| Started | Aug 12 07:25:35 PM PDT 24 |
| Finished | Aug 12 07:31:01 PM PDT 24 |
| Peak memory | 613796 kb |
| Host | smart-f0e3f912-ad2b-47e2-a2f0-5a3cd4062dfe |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=sysrst_ctrl_inputs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1094327065 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sysrst_ctrl_inputs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau lt.vdb -cm_log /dev/null -cm_name 2.chip_sw_sysrst_ctrl_inputs.1094327065 |
| Directory | /workspace/2.chip_sw_sysrst_ctrl_inputs/latest |
| Test location | /workspace/coverage/default/2.chip_sw_sysrst_ctrl_outputs.1314012200 |
| Short name | T211 |
| Test name | |
| Test status | |
| Simulation time | 3219865432 ps |
| CPU time | 348.76 seconds |
| Started | Aug 12 07:29:00 PM PDT 24 |
| Finished | Aug 12 07:34:49 PM PDT 24 |
| Peak memory | 609684 kb |
| Host | smart-c17c11c1-8797-458f-836d-9fb4d655c390 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=sysrst_ctrl_outputs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1314012200 -assert nopostproc +UVM_TE STNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sysrst_ctrl_outputs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def ault.vdb -cm_log /dev/null -cm_name 2.chip_sw_sysrst_ctrl_outputs.1314012200 |
| Directory | /workspace/2.chip_sw_sysrst_ctrl_outputs/latest |
| Test location | /workspace/coverage/default/2.chip_sw_sysrst_ctrl_reset.335414872 |
| Short name | T213 |
| Test name | |
| Test status | |
| Simulation time | 22024051450 ps |
| CPU time | 1763.46 seconds |
| Started | Aug 12 07:25:55 PM PDT 24 |
| Finished | Aug 12 07:55:19 PM PDT 24 |
| Peak memory | 615060 kb |
| Host | smart-f0dedf6e-2eae-4c4b-a180-e31c3db660dc |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=36_000_000 +sw_build_device=sim_dv +sw_images=sysrst_ctrl_reset_test:1:new_rules,test_rom:0 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33541487 2 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sysrst_ctrl_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_sysrst_ctrl_reset.335414872 |
| Directory | /workspace/2.chip_sw_sysrst_ctrl_reset/latest |
| Test location | /workspace/coverage/default/2.chip_sw_sysrst_ctrl_ulp_z3_wakeup.1144876688 |
| Short name | T40 |
| Test name | |
| Test status | |
| Simulation time | 6176172000 ps |
| CPU time | 397.09 seconds |
| Started | Aug 12 07:26:08 PM PDT 24 |
| Finished | Aug 12 07:32:45 PM PDT 24 |
| Peak memory | 611216 kb |
| Host | smart-658f5227-2971-4e3e-a6b6-4016bf45ac8f |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=sysrst_ctrl_ulp_z3_wakeup_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1144876688 -assert nopostproc + UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sysrst_ctrl_ulp_z3_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/ coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_sysrst_ctrl_ulp_z3_wakeup.1144876688 |
| Directory | /workspace/2.chip_sw_sysrst_ctrl_ulp_z3_wakeup/latest |
| Test location | /workspace/coverage/default/2.chip_sw_uart_rand_baudrate.2670490312 |
| Short name | T1399 |
| Test name | |
| Test status | |
| Simulation time | 13694585244 ps |
| CPU time | 2280.84 seconds |
| Started | Aug 12 07:23:41 PM PDT 24 |
| Finished | Aug 12 08:01:42 PM PDT 24 |
| Peak memory | 624976 kb |
| Host | smart-ebd72653-7596-4fe1-85a7-4be127a9603e |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random _seed=2670490312 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_uart_rand_baudrate.2670490312 |
| Directory | /workspace/2.chip_sw_uart_rand_baudrate/latest |
| Test location | /workspace/coverage/default/2.chip_sw_uart_smoketest.2284783510 |
| Short name | T1040 |
| Test name | |
| Test status | |
| Simulation time | 2341593960 ps |
| CPU time | 378.71 seconds |
| Started | Aug 12 07:30:23 PM PDT 24 |
| Finished | Aug 12 07:36:42 PM PDT 24 |
| Peak memory | 610324 kb |
| Host | smart-db3f2f64-ded8-41a0-9ab2-e322fa6ff258 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=uart_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2284783510 -assert nopostproc +UVM_TESTNAME=chi p_base_test +UVM_TEST_SEQ=chip_sw_uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 2.chip_sw_uart_smoketest.2284783510 |
| Directory | /workspace/2.chip_sw_uart_smoketest/latest |
| Test location | /workspace/coverage/default/2.chip_sw_uart_tx_rx.368777705 |
| Short name | T1148 |
| Test name | |
| Test status | |
| Simulation time | 3926574520 ps |
| CPU time | 714.47 seconds |
| Started | Aug 12 07:24:36 PM PDT 24 |
| Finished | Aug 12 07:36:31 PM PDT 24 |
| Peak memory | 624340 kb |
| Host | smart-2d5e8bad-c836-44e7-85aa-9edb21e4e3ee |
| User | root |
| Command | /workspace/default/simv +uart_idx=0 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=368777705 -as sert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac e/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_uart_tx_rx.368777705 |
| Directory | /workspace/2.chip_sw_uart_tx_rx/latest |
| Test location | /workspace/coverage/default/2.chip_sw_uart_tx_rx_alt_clk_freq.867882086 |
| Short name | T1376 |
| Test name | |
| Test status | |
| Simulation time | 9056173898 ps |
| CPU time | 1877.46 seconds |
| Started | Aug 12 07:23:27 PM PDT 24 |
| Finished | Aug 12 07:54:45 PM PDT 24 |
| Peak memory | 619368 kb |
| Host | smart-051199dd-0ebb-4a08-b00b-842d7e31c9f4 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=80_000_000 +chip_clock_source=ChipClockSourceExternal96Mhz +calibrate_usb_clk=1 +sw_build_device=sim_dv +s w_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=867882086 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_ba udrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_uart_tx_rx_ alt_clk_freq.867882086 |
| Directory | /workspace/2.chip_sw_uart_tx_rx_alt_clk_freq/latest |
| Test location | /workspace/coverage/default/2.chip_sw_uart_tx_rx_alt_clk_freq_low_speed.4087763150 |
| Short name | T1411 |
| Test name | |
| Test status | |
| Simulation time | 4569586804 ps |
| CPU time | 560.63 seconds |
| Started | Aug 12 07:23:46 PM PDT 24 |
| Finished | Aug 12 07:33:08 PM PDT 24 |
| Peak memory | 624000 kb |
| Host | smart-6be6c7ab-e1ec-4a68-b800-60a6fbf3f613 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +chip_clock_source=ChipClockSourceExternal48Mhz +sw_build_device=sim_dv +s w_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4087763150 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_b audrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_uart_tx_rx _alt_clk_freq_low_speed.4087763150 |
| Directory | /workspace/2.chip_sw_uart_tx_rx_alt_clk_freq_low_speed/latest |
| Test location | /workspace/coverage/default/2.chip_sw_uart_tx_rx_bootstrap.3497668146 |
| Short name | T210 |
| Test name | |
| Test status | |
| Simulation time | 78946463924 ps |
| CPU time | 13719.6 seconds |
| Started | Aug 12 07:21:58 PM PDT 24 |
| Finished | Aug 12 11:10:39 PM PDT 24 |
| Peak memory | 636492 kb |
| Host | smart-6e6a66d7-8549-4643-abef-3817d65fb0ff |
| User | root |
| Command | /workspace/default/simv +use_spi_load_bootstrap=1 +calibrate_usb_clk=1 +test_timeout_ns=160_000_000 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test :1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=3497668146 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_uart_tx_rx_bootstrap.3497668146 |
| Directory | /workspace/2.chip_sw_uart_tx_rx_bootstrap/latest |
| Test location | /workspace/coverage/default/2.chip_sw_uart_tx_rx_idx1.1668734251 |
| Short name | T1019 |
| Test name | |
| Test status | |
| Simulation time | 4488436514 ps |
| CPU time | 681.27 seconds |
| Started | Aug 12 07:23:56 PM PDT 24 |
| Finished | Aug 12 07:35:18 PM PDT 24 |
| Peak memory | 624328 kb |
| Host | smart-c209864b-faf1-423a-8721-9454739f1f29 |
| User | root |
| Command | /workspace/default/simv +uart_idx=1 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1668734251 -a ssert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ce/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_uart_tx_rx_idx1.1668734251 |
| Directory | /workspace/2.chip_sw_uart_tx_rx_idx1/latest |
| Test location | /workspace/coverage/default/2.chip_sw_uart_tx_rx_idx2.2011661971 |
| Short name | T160 |
| Test name | |
| Test status | |
| Simulation time | 4484440334 ps |
| CPU time | 624.8 seconds |
| Started | Aug 12 07:22:12 PM PDT 24 |
| Finished | Aug 12 07:32:37 PM PDT 24 |
| Peak memory | 624560 kb |
| Host | smart-0352729a-cdbd-4d2f-8fe8-3ad8c5c4218a |
| User | root |
| Command | /workspace/default/simv +uart_idx=2 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2011661971 -a ssert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ce/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_uart_tx_rx_idx2.2011661971 |
| Directory | /workspace/2.chip_sw_uart_tx_rx_idx2/latest |
| Test location | /workspace/coverage/default/2.chip_sw_uart_tx_rx_idx3.765479809 |
| Short name | T1122 |
| Test name | |
| Test status | |
| Simulation time | 4821768010 ps |
| CPU time | 666.64 seconds |
| Started | Aug 12 07:22:53 PM PDT 24 |
| Finished | Aug 12 07:34:01 PM PDT 24 |
| Peak memory | 624588 kb |
| Host | smart-c4901105-beae-4221-aab4-8634da5b9335 |
| User | root |
| Command | /workspace/default/simv +uart_idx=3 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=765479809 -as sert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac e/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_uart_tx_rx_idx3.765479809 |
| Directory | /workspace/2.chip_sw_uart_tx_rx_idx3/latest |
| Test location | /workspace/coverage/default/2.chip_tap_straps_dev.3604668698 |
| Short name | T76 |
| Test name | |
| Test status | |
| Simulation time | 6973548372 ps |
| CPU time | 716.88 seconds |
| Started | Aug 12 07:28:04 PM PDT 24 |
| Finished | Aug 12 07:40:01 PM PDT 24 |
| Peak memory | 624992 kb |
| Host | smart-8bad6446-6dd4-41aa-a19c-a8da94b87a02 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStDev +create_jtag_riscv_map=1 +sw_build_device=sim_dv +sw_images=example_test_from_rom:0:test_in_rom: new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=3604668698 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_tap_straps_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_tap_straps_dev.3604668698 |
| Directory | /workspace/2.chip_tap_straps_dev/latest |
| Test location | /workspace/coverage/default/2.chip_tap_straps_prod.1672599320 |
| Short name | T1149 |
| Test name | |
| Test status | |
| Simulation time | 8332506154 ps |
| CPU time | 844.03 seconds |
| Started | Aug 12 07:28:46 PM PDT 24 |
| Finished | Aug 12 07:42:50 PM PDT 24 |
| Peak memory | 625044 kb |
| Host | smart-ef62bd44-5f7d-4ef3-80e6-91a28a52cddb |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStProd +create_jtag_riscv_map=1 +sw_build_device=sim_dv +sw_images=example_test_from_rom:0:test_in_rom :new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1672599320 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_tap_straps_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_tap_straps_prod.1672599320 |
| Directory | /workspace/2.chip_tap_straps_prod/latest |
| Test location | /workspace/coverage/default/2.chip_tap_straps_rma.3194581830 |
| Short name | T72 |
| Test name | |
| Test status | |
| Simulation time | 8104988702 ps |
| CPU time | 683.21 seconds |
| Started | Aug 12 07:29:07 PM PDT 24 |
| Finished | Aug 12 07:40:30 PM PDT 24 |
| Peak memory | 631900 kb |
| Host | smart-7c6ddeed-c08a-4abe-a462-3956f2078fec |
| User | root |
| Command | /workspace/default/simv +create_jtag_riscv_map=1 +sw_build_device=sim_dv +sw_images=example_test_from_rom:0:test_in_rom:new_rules +cdc_instrumentation _enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3194581830 -as sert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_tap_straps_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/c overage/default.vdb -cm_log /dev/null -cm_name 2.chip_tap_straps_rma.3194581830 |
| Directory | /workspace/2.chip_tap_straps_rma/latest |
| Test location | /workspace/coverage/default/2.rom_e2e_asm_init_dev.3077300113 |
| Short name | T1096 |
| Test name | |
| Test status | |
| Simulation time | 15059928574 ps |
| CPU time | 3346.03 seconds |
| Started | Aug 12 07:34:02 PM PDT 24 |
| Finished | Aug 12 08:29:49 PM PDT 24 |
| Peak memory | 610496 kb |
| Host | smart-0a398bee-b403-4936-99b8-8c3d7b515e66 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeCustom +sw_test_timeout_ns=20000000 +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_prod _key_0:1:ot_flash_binary,otp_img_e2e_bootstrap_entry_dev:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3077300113 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_S EQ=chip_sw_rom_e2e_asm_init_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_e2e_asm_init_dev.3077300113 |
| Directory | /workspace/2.rom_e2e_asm_init_dev/latest |
| Test location | /workspace/coverage/default/2.rom_e2e_asm_init_prod.227441496 |
| Short name | T386 |
| Test name | |
| Test status | |
| Simulation time | 15727392880 ps |
| CPU time | 3274.69 seconds |
| Started | Aug 12 07:36:27 PM PDT 24 |
| Finished | Aug 12 08:31:04 PM PDT 24 |
| Peak memory | 610680 kb |
| Host | smart-d18a32a1-4cff-4b7f-bbbb-622b952e6564 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeCustom +sw_test_timeout_ns=20000000 +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_prod _key_0:1:ot_flash_binary,otp_img_e2e_bootstrap_entry_prod:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=227441496 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_S EQ=chip_sw_rom_e2e_asm_init_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_e2e_asm_init_prod.227441496 |
| Directory | /workspace/2.rom_e2e_asm_init_prod/latest |
| Test location | /workspace/coverage/default/2.rom_e2e_asm_init_prod_end.2178868521 |
| Short name | T1363 |
| Test name | |
| Test status | |
| Simulation time | 15457651214 ps |
| CPU time | 3790.89 seconds |
| Started | Aug 12 07:34:49 PM PDT 24 |
| Finished | Aug 12 08:38:02 PM PDT 24 |
| Peak memory | 610680 kb |
| Host | smart-c6b949b2-5954-43c8-adef-7058897f1d3b |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeCustom +sw_test_timeout_ns=20000000 +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_prod _key_0:1:ot_flash_binary,otp_img_e2e_bootstrap_entry_prod_end:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2178868521 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_T EST_SEQ=chip_sw_rom_e2e_asm_init_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 2.rom_e2e_asm_init_prod_end.2178868521 |
| Directory | /workspace/2.rom_e2e_asm_init_prod_end/latest |
| Test location | /workspace/coverage/default/2.rom_e2e_asm_init_rma.2746423595 |
| Short name | T1034 |
| Test name | |
| Test status | |
| Simulation time | 14810367843 ps |
| CPU time | 3893.41 seconds |
| Started | Aug 12 07:36:20 PM PDT 24 |
| Finished | Aug 12 08:41:14 PM PDT 24 |
| Peak memory | 610724 kb |
| Host | smart-dd6212b2-904f-4342-85fa-e4bc97bfeae8 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeCustom +sw_test_timeout_ns=20000000 +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_prod _key_0:1:ot_flash_binary,otp_img_e2e_bootstrap_entry_rma:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2746423595 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_S EQ=chip_sw_rom_e2e_asm_init_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_e2e_asm_init_rma.2746423595 |
| Directory | /workspace/2.rom_e2e_asm_init_rma/latest |
| Test location | /workspace/coverage/default/2.rom_e2e_asm_init_test_unlocked0.2625554458 |
| Short name | T1094 |
| Test name | |
| Test status | |
| Simulation time | 11373745946 ps |
| CPU time | 2713.11 seconds |
| Started | Aug 12 07:34:31 PM PDT 24 |
| Finished | Aug 12 08:19:45 PM PDT 24 |
| Peak memory | 610740 kb |
| Host | smart-dd425844-4e19-43a3-8a67-4b35c443ed6b |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeCustom +sw_test_timeout_ns=410_000_000 +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_p rod_key_0:1:ot_flash_binary,otp_img_e2e_bootstrap_entry_test_unlocked0:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY =UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2625554458 -assert nopostproc +UVM_TESTNAME=chip_base_te st +UVM_TEST_SEQ=chip_sw_rom_e2e_asm_init_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/ null -cm_name 2.rom_e2e_asm_init_test_unlocked0.2625554458 |
| Directory | /workspace/2.rom_e2e_asm_init_test_unlocked0/latest |
| Test location | /workspace/coverage/default/2.rom_e2e_keymgr_init_rom_ext_invalid_meas.3407835346 |
| Short name | T1043 |
| Test name | |
| Test status | |
| Simulation time | 14497903600 ps |
| CPU time | 2803.98 seconds |
| Started | Aug 12 07:34:22 PM PDT 24 |
| Finished | Aug 12 08:21:06 PM PDT 24 |
| Peak memory | 610424 kb |
| Host | smart-437e1f36-87dd-4eec-8b42-53773a316d8b |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=40_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=rom_e2e_keymgr_init_otp_invalid _meas:1:new_rules,otp_img_keymgr_otp_invalid_meas:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3407835346 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip _sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_e2e_keymgr_in it_rom_ext_invalid_meas.3407835346 |
| Directory | /workspace/2.rom_e2e_keymgr_init_rom_ext_invalid_meas/latest |
| Test location | /workspace/coverage/default/2.rom_e2e_keymgr_init_rom_ext_meas.3614198895 |
| Short name | T1361 |
| Test name | |
| Test status | |
| Simulation time | 15429953012 ps |
| CPU time | 4163.19 seconds |
| Started | Aug 12 07:36:38 PM PDT 24 |
| Finished | Aug 12 08:46:02 PM PDT 24 |
| Peak memory | 610668 kb |
| Host | smart-a7333c5a-1a89-4966-8d07-330965293174 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=40_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=rom_e2e_keymgr_init_otp_meas:1: new_rules,otp_img_keymgr_otp_meas:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3614198895 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_e2e_keymgr_init_rom_ext_meas.3614198895 |
| Directory | /workspace/2.rom_e2e_keymgr_init_rom_ext_meas/latest |
| Test location | /workspace/coverage/default/2.rom_e2e_keymgr_init_rom_ext_no_meas.2861054469 |
| Short name | T1027 |
| Test name | |
| Test status | |
| Simulation time | 14858141700 ps |
| CPU time | 3254.62 seconds |
| Started | Aug 12 07:36:34 PM PDT 24 |
| Finished | Aug 12 08:30:49 PM PDT 24 |
| Peak memory | 610372 kb |
| Host | smart-94e626fa-4ad7-490d-9ec1-933e0312f934 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=40_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=rom_e2e_keymgr_init_otp_no_meas :1:new_rules,otp_img_keymgr_otp_no_meas:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2861054469 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_e2e_keymgr_init_rom_ext _no_meas.2861054469 |
| Directory | /workspace/2.rom_e2e_keymgr_init_rom_ext_no_meas/latest |
| Test location | /workspace/coverage/default/2.rom_e2e_self_hash.1200472933 |
| Short name | T1007 |
| Test name | |
| Test status | |
| Simulation time | 26194065312 ps |
| CPU time | 5687.9 seconds |
| Started | Aug 12 07:34:09 PM PDT 24 |
| Finished | Aug 12 09:08:57 PM PDT 24 |
| Peak memory | 610644 kb |
| Host | smart-684e4748-bb15-4e7d-b671-f58a1cc5cf99 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=200_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=rom_e2e_self_hash_test:1:new_r ules,otp_img_sigverify_spx_prod:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1200472933 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_e2e_self_hash.1200472933 |
| Directory | /workspace/2.rom_e2e_self_hash/latest |
| Test location | /workspace/coverage/default/2.rom_e2e_shutdown_exception_c.2591289777 |
| Short name | T1351 |
| Test name | |
| Test status | |
| Simulation time | 14590761080 ps |
| CPU time | 4168.26 seconds |
| Started | Aug 12 07:36:35 PM PDT 24 |
| Finished | Aug 12 08:46:04 PM PDT 24 |
| Peak memory | 611440 kb |
| Host | smart-dda23d3e-a604-4628-be79-87f7a090a873 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=40000000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=rom_e2e_shutdown_exception_c:1:ne w_rules,otp_img_secret2_locked_rma:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2591289777 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rom_e2e_shu tdown_exception_c_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_e2e_ shutdown_exception_c.2591289777 |
| Directory | /workspace/2.rom_e2e_shutdown_exception_c/latest |
| Test location | /workspace/coverage/default/2.rom_e2e_shutdown_output.2616269940 |
| Short name | T381 |
| Test name | |
| Test status | |
| Simulation time | 25206115554 ps |
| CPU time | 2916.89 seconds |
| Started | Aug 12 07:33:58 PM PDT 24 |
| Finished | Aug 12 08:22:35 PM PDT 24 |
| Peak memory | 611744 kb |
| Host | smart-6437a081-a944-4046-a380-20c9c6d7535f |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=20000000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_unsigned:1:ot_f lash_binary,otp_img_shutdown_output_test_unlocked0:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2616269940 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chi p_sw_rom_e2e_shutdown_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_e2e_shutdown_output.2616269940 |
| Directory | /workspace/2.rom_e2e_shutdown_output/latest |
| Test location | /workspace/coverage/default/2.rom_e2e_smoke.3407036093 |
| Short name | T1373 |
| Test name | |
| Test status | |
| Simulation time | 14577029448 ps |
| CPU time | 3962.46 seconds |
| Started | Aug 12 07:34:33 PM PDT 24 |
| Finished | Aug 12 08:40:36 PM PDT 24 |
| Peak memory | 610476 kb |
| Host | smart-15ff8dfd-b01d-4d32-b979-5c74df61fb2c |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=40000000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=rom_e2e_smoke:1:new_rules,otp_img _secret2_locked_rma:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_to p/hw/dv/tools/sim.tcl +ntb_random_seed=3407036093 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_e2e_smoke.3407036093 |
| Directory | /workspace/2.rom_e2e_smoke/latest |
| Test location | /workspace/coverage/default/2.rom_e2e_static_critical.2677770068 |
| Short name | T1102 |
| Test name | |
| Test status | |
| Simulation time | 17008463608 ps |
| CPU time | 3495.2 seconds |
| Started | Aug 12 07:34:53 PM PDT 24 |
| Finished | Aug 12 08:33:08 PM PDT 24 |
| Peak memory | 610568 kb |
| Host | smart-82d225f8-ac50-45b3-ac4d-febcbfcd9f9d |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=40000000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=rom_e2e_static_critical:1:new_rul es,otp_img_secret2_locked_rma:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2677770068 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_e2e_static_critical.2677770068 |
| Directory | /workspace/2.rom_e2e_static_critical/latest |
| Test location | /workspace/coverage/default/2.rom_keymgr_functest.2953870154 |
| Short name | T1188 |
| Test name | |
| Test status | |
| Simulation time | 4130216530 ps |
| CPU time | 539.13 seconds |
| Started | Aug 12 07:30:55 PM PDT 24 |
| Finished | Aug 12 07:39:55 PM PDT 24 |
| Peak memory | 610516 kb |
| Host | smart-6600a0ba-f847-4a6f-822a-98fb197a8d2b |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=10_000_000 +sw_build_device=sim_dv +sw_images=keymgr_functest:1:new_rules,test_rom:0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2953870154 -ass ert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 2.rom_keymgr_functest.2953870154 |
| Directory | /workspace/2.rom_keymgr_functest/latest |
| Test location | /workspace/coverage/default/2.rom_raw_unlock.1428836117 |
| Short name | T787 |
| Test name | |
| Test status | |
| Simulation time | 5438389766 ps |
| CPU time | 231.94 seconds |
| Started | Aug 12 07:29:38 PM PDT 24 |
| Finished | Aug 12 07:33:30 PM PDT 24 |
| Peak memory | 624124 kb |
| Host | smart-a7fcd059-9f7c-4528-b8c5-de43512f47d8 |
| User | root |
| Command | /workspace/default/simv +do_creator_sw_cfg_ast_cfg=0 +sw_test_timeout_ns=200_000_000 +use_otp_image=OtpTypeLcStRaw +chip_clock_source=ChipClockSourceE xternal48Mhz +rom_prod_mode=1 +use_jtag_dmi=1 +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_test_key_0:1:ot_flash_binary,mask_ro m:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=1428836117 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_raw_unlock_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_raw_unlock.1428836117 |
| Directory | /workspace/2.rom_raw_unlock/latest |
| Test location | /workspace/coverage/default/2.rom_volatile_raw_unlock.1335299217 |
| Short name | T279 |
| Test name | |
| Test status | |
| Simulation time | 2676550202 ps |
| CPU time | 106.21 seconds |
| Started | Aug 12 07:29:49 PM PDT 24 |
| Finished | Aug 12 07:31:36 PM PDT 24 |
| Peak memory | 617232 kb |
| Host | smart-75dc5a4e-74ec-49dc-bf32-afc7c1d775e3 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=200_000_000 +use_otp_image=OtpTypeLcStRaw +chip_clock_source=ChipClockSourceExternal48Mhz +rom_prod_mode=1 +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_test_key_0:1:ot_flash_binary,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1335299217 -assert nopostproc +UVM_ TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_volatile_raw_unlock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag e/default.vdb -cm_log /dev/null -cm_name 2.rom_volatile_raw_unlock.1335299217 |
| Directory | /workspace/2.rom_volatile_raw_unlock/latest |
| Test location | /workspace/coverage/default/21.chip_sw_alert_handler_lpg_sleep_mode_alerts.2229556862 |
| Short name | T1147 |
| Test name | |
| Test status | |
| Simulation time | 3387562208 ps |
| CPU time | 389.33 seconds |
| Started | Aug 12 07:35:04 PM PDT 24 |
| Finished | Aug 12 07:41:33 PM PDT 24 |
| Peak memory | 619356 kb |
| Host | smart-6413ab68-ecdb-4538-9eee-a1d2c1e52321 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2229556862 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.chip_ sw_alert_handler_lpg_sleep_mode_alerts.2229556862 |
| Directory | /workspace/21.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/22.chip_sw_alert_handler_lpg_sleep_mode_alerts.1953753624 |
| Short name | T327 |
| Test name | |
| Test status | |
| Simulation time | 4166470132 ps |
| CPU time | 449.65 seconds |
| Started | Aug 12 07:36:00 PM PDT 24 |
| Finished | Aug 12 07:43:30 PM PDT 24 |
| Peak memory | 649572 kb |
| Host | smart-408ed1ae-1d9d-4281-af13-bd65064a5a9a |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1953753624 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.chip_ sw_alert_handler_lpg_sleep_mode_alerts.1953753624 |
| Directory | /workspace/22.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/24.chip_sw_all_escalation_resets.2633403767 |
| Short name | T413 |
| Test name | |
| Test status | |
| Simulation time | 5097202220 ps |
| CPU time | 668.66 seconds |
| Started | Aug 12 07:36:11 PM PDT 24 |
| Finished | Aug 12 07:47:20 PM PDT 24 |
| Peak memory | 650468 kb |
| Host | smart-718dd1e2-387a-4832-a9dc-d10293e0089f |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 2633403767 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.chip_sw_all_escalation_resets.2633403767 |
| Directory | /workspace/24.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/25.chip_sw_alert_handler_lpg_sleep_mode_alerts.1524824876 |
| Short name | T310 |
| Test name | |
| Test status | |
| Simulation time | 4311351200 ps |
| CPU time | 415.84 seconds |
| Started | Aug 12 07:35:20 PM PDT 24 |
| Finished | Aug 12 07:42:16 PM PDT 24 |
| Peak memory | 649684 kb |
| Host | smart-8cd9da09-09a8-4609-af71-5854e1ef51a1 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1524824876 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.chip_ sw_alert_handler_lpg_sleep_mode_alerts.1524824876 |
| Directory | /workspace/25.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/27.chip_sw_all_escalation_resets.2997510202 |
| Short name | T844 |
| Test name | |
| Test status | |
| Simulation time | 5883341960 ps |
| CPU time | 636.47 seconds |
| Started | Aug 12 07:36:01 PM PDT 24 |
| Finished | Aug 12 07:46:37 PM PDT 24 |
| Peak memory | 650596 kb |
| Host | smart-c6a0878e-7b96-4a6f-b2c9-d48c7c3d7bda |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 2997510202 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.chip_sw_all_escalation_resets.2997510202 |
| Directory | /workspace/27.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/28.chip_sw_alert_handler_lpg_sleep_mode_alerts.3873583052 |
| Short name | T799 |
| Test name | |
| Test status | |
| Simulation time | 3763814360 ps |
| CPU time | 359.64 seconds |
| Started | Aug 12 07:36:48 PM PDT 24 |
| Finished | Aug 12 07:42:48 PM PDT 24 |
| Peak memory | 647632 kb |
| Host | smart-9023156e-215e-4caa-bc7b-b5e585543600 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3873583052 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.chip_ sw_alert_handler_lpg_sleep_mode_alerts.3873583052 |
| Directory | /workspace/28.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/28.chip_sw_all_escalation_resets.1909355831 |
| Short name | T837 |
| Test name | |
| Test status | |
| Simulation time | 5042349774 ps |
| CPU time | 675.26 seconds |
| Started | Aug 12 07:35:48 PM PDT 24 |
| Finished | Aug 12 07:47:04 PM PDT 24 |
| Peak memory | 650660 kb |
| Host | smart-72c6b949-7978-4043-a988-0a3f894aa21e |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 1909355831 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.chip_sw_all_escalation_resets.1909355831 |
| Directory | /workspace/28.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/3.chip_sw_aon_timer_sleep_wdog_sleep_pause.2072711161 |
| Short name | T1424 |
| Test name | |
| Test status | |
| Simulation time | 6552873716 ps |
| CPU time | 705.6 seconds |
| Started | Aug 12 07:30:35 PM PDT 24 |
| Finished | Aug 12 07:42:21 PM PDT 24 |
| Peak memory | 609608 kb |
| Host | smart-8f7b01a1-4f0f-449c-b29b-809083b43627 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=aon_timer_sleep_wdog_sleep_pause_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=2072711161 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.chip_sw_aon_timer_sleep_wdog_sleep_pause.2072711161 |
| Directory | /workspace/3.chip_sw_aon_timer_sleep_wdog_sleep_pause/latest |
| Test location | /workspace/coverage/default/3.chip_sw_csrng_edn_concurrency.1583373695 |
| Short name | T1006 |
| Test name | |
| Test status | |
| Simulation time | 21992872482 ps |
| CPU time | 4855.71 seconds |
| Started | Aug 12 07:37:27 PM PDT 24 |
| Finished | Aug 12 08:58:23 PM PDT 24 |
| Peak memory | 610784 kb |
| Host | smart-f6b5e415-e06f-4c5f-baa9-e04aa031ae02 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=140_000_000 +rng_srate_value_min=15 +rng_srate_value_max=20 +sw_build_device=sim_dv +sw_images=csrng_edn_c oncurrency_test:1:new_rules,test_rom:0 +accelerate_cold_power_up_time=3 +accelerate_regulators_power_up_time=2 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1583373695 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd b -cm_log /dev/null -cm_name 3.chip_sw_csrng_edn_concurrency.1583373695 |
| Directory | /workspace/3.chip_sw_csrng_edn_concurrency/latest |
| Test location | /workspace/coverage/default/3.chip_sw_data_integrity_escalation.3173574445 |
| Short name | T291 |
| Test name | |
| Test status | |
| Simulation time | 5912262974 ps |
| CPU time | 602.92 seconds |
| Started | Aug 12 07:36:11 PM PDT 24 |
| Finished | Aug 12 07:46:14 PM PDT 24 |
| Peak memory | 611176 kb |
| Host | smart-579f1a91-8c8f-4ac2-ad17-7292b8ef983c |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=data_integrity_escalation_reset_test:1:new_rules,test_ro m:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=3173574445 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_data_integrity_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.chip_sw_data_integrity_escalation.3173574445 |
| Directory | /workspace/3.chip_sw_data_integrity_escalation/latest |
| Test location | /workspace/coverage/default/3.chip_sw_lc_ctrl_transition.2288776500 |
| Short name | T1047 |
| Test name | |
| Test status | |
| Simulation time | 6855405336 ps |
| CPU time | 447.31 seconds |
| Started | Aug 12 07:33:30 PM PDT 24 |
| Finished | Aug 12 07:40:58 PM PDT 24 |
| Peak memory | 622852 kb |
| Host | smart-54bb40d5-993c-41e7-9601-d30fa99a60c6 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=lc_ctrl_transition_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2288776500 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_transition_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau lt.vdb -cm_log /dev/null -cm_name 3.chip_sw_lc_ctrl_transition.2288776500 |
| Directory | /workspace/3.chip_sw_lc_ctrl_transition/latest |
| Test location | /workspace/coverage/default/3.chip_sw_sensor_ctrl_alert.2020802900 |
| Short name | T147 |
| Test name | |
| Test status | |
| Simulation time | 7217301330 ps |
| CPU time | 996.8 seconds |
| Started | Aug 12 07:31:53 PM PDT 24 |
| Finished | Aug 12 07:48:30 PM PDT 24 |
| Peak memory | 609632 kb |
| Host | smart-b562f7b9-1ca0-4938-988a-9192ba482eca |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=40_000_000 +sw_build_device=sim_dv +sw_images=sensor_ctrl_alert_test:1:new_rules,test_rom:0 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20208029 00 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac e/coverage/default.vdb -cm_log /dev/null -cm_name 3.chip_sw_sensor_ctrl_alert.2020802900 |
| Directory | /workspace/3.chip_sw_sensor_ctrl_alert/latest |
| Test location | /workspace/coverage/default/3.chip_sw_uart_rand_baudrate.1895440101 |
| Short name | T369 |
| Test name | |
| Test status | |
| Simulation time | 8034350976 ps |
| CPU time | 1503.75 seconds |
| Started | Aug 12 07:31:22 PM PDT 24 |
| Finished | Aug 12 07:56:26 PM PDT 24 |
| Peak memory | 623900 kb |
| Host | smart-c395c2c0-ba61-45be-bdcf-8e7a492398a5 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random _seed=1895440101 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.chip_sw_uart_rand_baudrate.1895440101 |
| Directory | /workspace/3.chip_sw_uart_rand_baudrate/latest |
| Test location | /workspace/coverage/default/3.chip_sw_uart_tx_rx.4205057994 |
| Short name | T1181 |
| Test name | |
| Test status | |
| Simulation time | 4413657600 ps |
| CPU time | 641.74 seconds |
| Started | Aug 12 07:36:35 PM PDT 24 |
| Finished | Aug 12 07:47:17 PM PDT 24 |
| Peak memory | 624264 kb |
| Host | smart-40a34a62-70ce-44d0-976b-493d8f62672b |
| User | root |
| Command | /workspace/default/simv +uart_idx=0 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4205057994 -a ssert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ce/coverage/default.vdb -cm_log /dev/null -cm_name 3.chip_sw_uart_tx_rx.4205057994 |
| Directory | /workspace/3.chip_sw_uart_tx_rx/latest |
| Test location | /workspace/coverage/default/3.chip_sw_uart_tx_rx_alt_clk_freq_low_speed.965624618 |
| Short name | T1167 |
| Test name | |
| Test status | |
| Simulation time | 14273200244 ps |
| CPU time | 2050.48 seconds |
| Started | Aug 12 07:33:32 PM PDT 24 |
| Finished | Aug 12 08:07:43 PM PDT 24 |
| Peak memory | 624068 kb |
| Host | smart-27658986-1531-4acc-85c5-ff2dc8f99c5b |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +chip_clock_source=ChipClockSourceExternal48Mhz +sw_build_device=sim_dv +s w_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=965624618 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_ba udrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.chip_sw_uart_tx_rx_ alt_clk_freq_low_speed.965624618 |
| Directory | /workspace/3.chip_sw_uart_tx_rx_alt_clk_freq_low_speed/latest |
| Test location | /workspace/coverage/default/3.chip_sw_uart_tx_rx_idx1.930054790 |
| Short name | T1138 |
| Test name | |
| Test status | |
| Simulation time | 4081852358 ps |
| CPU time | 670.98 seconds |
| Started | Aug 12 07:37:17 PM PDT 24 |
| Finished | Aug 12 07:48:28 PM PDT 24 |
| Peak memory | 624272 kb |
| Host | smart-d1e0c3cd-4385-46f4-aeca-ab66f3c325d7 |
| User | root |
| Command | /workspace/default/simv +uart_idx=1 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=930054790 -as sert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac e/coverage/default.vdb -cm_log /dev/null -cm_name 3.chip_sw_uart_tx_rx_idx1.930054790 |
| Directory | /workspace/3.chip_sw_uart_tx_rx_idx1/latest |
| Test location | /workspace/coverage/default/3.chip_sw_uart_tx_rx_idx3.4003229584 |
| Short name | T1231 |
| Test name | |
| Test status | |
| Simulation time | 5203411284 ps |
| CPU time | 734.66 seconds |
| Started | Aug 12 07:31:25 PM PDT 24 |
| Finished | Aug 12 07:43:40 PM PDT 24 |
| Peak memory | 624552 kb |
| Host | smart-778c4565-bd30-4a3e-a179-b1dd7fcb3261 |
| User | root |
| Command | /workspace/default/simv +uart_idx=3 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4003229584 -a ssert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ce/coverage/default.vdb -cm_log /dev/null -cm_name 3.chip_sw_uart_tx_rx_idx3.4003229584 |
| Directory | /workspace/3.chip_sw_uart_tx_rx_idx3/latest |
| Test location | /workspace/coverage/default/3.chip_tap_straps_dev.1062495877 |
| Short name | T752 |
| Test name | |
| Test status | |
| Simulation time | 15765120117 ps |
| CPU time | 1610.93 seconds |
| Started | Aug 12 07:31:29 PM PDT 24 |
| Finished | Aug 12 07:58:20 PM PDT 24 |
| Peak memory | 625012 kb |
| Host | smart-f6287a8f-4425-4f3d-8f9c-31e50ee8255f |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStDev +create_jtag_riscv_map=1 +sw_build_device=sim_dv +sw_images=example_test_from_rom:0:test_in_rom: new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=1062495877 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_tap_straps_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.chip_tap_straps_dev.1062495877 |
| Directory | /workspace/3.chip_tap_straps_dev/latest |
| Test location | /workspace/coverage/default/3.chip_tap_straps_prod.2127040424 |
| Short name | T1199 |
| Test name | |
| Test status | |
| Simulation time | 12179083991 ps |
| CPU time | 1135.47 seconds |
| Started | Aug 12 07:33:02 PM PDT 24 |
| Finished | Aug 12 07:51:58 PM PDT 24 |
| Peak memory | 621484 kb |
| Host | smart-e2d29ca9-9706-45bd-9348-4a63f80671b5 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStProd +create_jtag_riscv_map=1 +sw_build_device=sim_dv +sw_images=example_test_from_rom:0:test_in_rom :new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2127040424 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_tap_straps_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.chip_tap_straps_prod.2127040424 |
| Directory | /workspace/3.chip_tap_straps_prod/latest |
| Test location | /workspace/coverage/default/3.chip_tap_straps_rma.1871504551 |
| Short name | T1291 |
| Test name | |
| Test status | |
| Simulation time | 6734813045 ps |
| CPU time | 628.77 seconds |
| Started | Aug 12 07:31:02 PM PDT 24 |
| Finished | Aug 12 07:41:31 PM PDT 24 |
| Peak memory | 625032 kb |
| Host | smart-cc5159ef-8072-4426-b9dc-b9184beb11b0 |
| User | root |
| Command | /workspace/default/simv +create_jtag_riscv_map=1 +sw_build_device=sim_dv +sw_images=example_test_from_rom:0:test_in_rom:new_rules +cdc_instrumentation _enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1871504551 -as sert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_tap_straps_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/c overage/default.vdb -cm_log /dev/null -cm_name 3.chip_tap_straps_rma.1871504551 |
| Directory | /workspace/3.chip_tap_straps_rma/latest |
| Test location | /workspace/coverage/default/3.chip_tap_straps_testunlock0.954078130 |
| Short name | T1370 |
| Test name | |
| Test status | |
| Simulation time | 3759102147 ps |
| CPU time | 251.41 seconds |
| Started | Aug 12 07:31:58 PM PDT 24 |
| Finished | Aug 12 07:36:09 PM PDT 24 |
| Peak memory | 633568 kb |
| Host | smart-5d7978a3-28ad-43cb-a4f7-c8b4f4edc295 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStTestUnlocked0 +create_jtag_riscv_map=1 +sw_build_device=sim_dv +sw_images=example_test_from_rom:0:te st_in_rom:new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=954078130 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_tap_straps_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.chip_tap_straps_testunlock0.954078130 |
| Directory | /workspace/3.chip_tap_straps_testunlock0/latest |
| Test location | /workspace/coverage/default/30.chip_sw_alert_handler_lpg_sleep_mode_alerts.2745953265 |
| Short name | T851 |
| Test name | |
| Test status | |
| Simulation time | 4062165820 ps |
| CPU time | 422.12 seconds |
| Started | Aug 12 07:36:31 PM PDT 24 |
| Finished | Aug 12 07:43:33 PM PDT 24 |
| Peak memory | 649328 kb |
| Host | smart-388afde5-51c9-4b34-9305-86e03f9fd1cf |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2745953265 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.chip_ sw_alert_handler_lpg_sleep_mode_alerts.2745953265 |
| Directory | /workspace/30.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/30.chip_sw_all_escalation_resets.595579117 |
| Short name | T265 |
| Test name | |
| Test status | |
| Simulation time | 5244877174 ps |
| CPU time | 480.21 seconds |
| Started | Aug 12 07:36:40 PM PDT 24 |
| Finished | Aug 12 07:44:40 PM PDT 24 |
| Peak memory | 649000 kb |
| Host | smart-07775a76-f5c9-4eb5-8fdf-92e82cc3cc72 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 595579117 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.chip_sw_all_escalation_resets.595579117 |
| Directory | /workspace/30.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/31.chip_sw_alert_handler_lpg_sleep_mode_alerts.2858635684 |
| Short name | T1283 |
| Test name | |
| Test status | |
| Simulation time | 4306447512 ps |
| CPU time | 540.98 seconds |
| Started | Aug 12 07:36:25 PM PDT 24 |
| Finished | Aug 12 07:45:26 PM PDT 24 |
| Peak memory | 649620 kb |
| Host | smart-64353abd-72ea-4529-8fcf-f4ef5cfb4659 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2858635684 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.chip_ sw_alert_handler_lpg_sleep_mode_alerts.2858635684 |
| Directory | /workspace/31.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/32.chip_sw_alert_handler_lpg_sleep_mode_alerts.4183460945 |
| Short name | T323 |
| Test name | |
| Test status | |
| Simulation time | 4209100288 ps |
| CPU time | 400.52 seconds |
| Started | Aug 12 07:37:45 PM PDT 24 |
| Finished | Aug 12 07:44:26 PM PDT 24 |
| Peak memory | 649504 kb |
| Host | smart-da8a9f44-47ac-48ce-bcd8-3957c23a39c6 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4183460945 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.chip_ sw_alert_handler_lpg_sleep_mode_alerts.4183460945 |
| Directory | /workspace/32.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/33.chip_sw_alert_handler_lpg_sleep_mode_alerts.4146005305 |
| Short name | T883 |
| Test name | |
| Test status | |
| Simulation time | 3929546300 ps |
| CPU time | 436.67 seconds |
| Started | Aug 12 07:36:52 PM PDT 24 |
| Finished | Aug 12 07:44:09 PM PDT 24 |
| Peak memory | 649376 kb |
| Host | smart-9099703d-5fbe-499b-a9cb-072203945ef5 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4146005305 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.chip_ sw_alert_handler_lpg_sleep_mode_alerts.4146005305 |
| Directory | /workspace/33.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/34.chip_sw_alert_handler_lpg_sleep_mode_alerts.811728927 |
| Short name | T414 |
| Test name | |
| Test status | |
| Simulation time | 4347719304 ps |
| CPU time | 371.52 seconds |
| Started | Aug 12 07:36:39 PM PDT 24 |
| Finished | Aug 12 07:42:51 PM PDT 24 |
| Peak memory | 649604 kb |
| Host | smart-409ed3aa-301b-490e-a3cd-d8f34f3e2155 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=811728927 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all _escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.chip_s w_alert_handler_lpg_sleep_mode_alerts.811728927 |
| Directory | /workspace/34.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/34.chip_sw_all_escalation_resets.2529960778 |
| Short name | T1254 |
| Test name | |
| Test status | |
| Simulation time | 5951223950 ps |
| CPU time | 772.52 seconds |
| Started | Aug 12 07:36:19 PM PDT 24 |
| Finished | Aug 12 07:49:12 PM PDT 24 |
| Peak memory | 650240 kb |
| Host | smart-670fae69-4c5f-4c4b-95dd-ac9022eef095 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 2529960778 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.chip_sw_all_escalation_resets.2529960778 |
| Directory | /workspace/34.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/35.chip_sw_all_escalation_resets.1226000310 |
| Short name | T827 |
| Test name | |
| Test status | |
| Simulation time | 4952291512 ps |
| CPU time | 765.91 seconds |
| Started | Aug 12 07:36:28 PM PDT 24 |
| Finished | Aug 12 07:49:14 PM PDT 24 |
| Peak memory | 650256 kb |
| Host | smart-80354e1a-59c0-414d-86da-70c4d2041269 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 1226000310 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.chip_sw_all_escalation_resets.1226000310 |
| Directory | /workspace/35.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/36.chip_sw_alert_handler_lpg_sleep_mode_alerts.2282723834 |
| Short name | T808 |
| Test name | |
| Test status | |
| Simulation time | 3996311720 ps |
| CPU time | 393.78 seconds |
| Started | Aug 12 07:36:49 PM PDT 24 |
| Finished | Aug 12 07:43:22 PM PDT 24 |
| Peak memory | 649292 kb |
| Host | smart-bcb9ed06-eb0c-41fb-a3b8-461b5191c6ad |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2282723834 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.chip_ sw_alert_handler_lpg_sleep_mode_alerts.2282723834 |
| Directory | /workspace/36.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/36.chip_sw_all_escalation_resets.1842101890 |
| Short name | T829 |
| Test name | |
| Test status | |
| Simulation time | 6138893632 ps |
| CPU time | 582.88 seconds |
| Started | Aug 12 07:35:49 PM PDT 24 |
| Finished | Aug 12 07:45:32 PM PDT 24 |
| Peak memory | 650896 kb |
| Host | smart-9a27e5f2-7a72-4ce0-9157-53c3ee8438e8 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 1842101890 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.chip_sw_all_escalation_resets.1842101890 |
| Directory | /workspace/36.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/37.chip_sw_alert_handler_lpg_sleep_mode_alerts.4174016308 |
| Short name | T1030 |
| Test name | |
| Test status | |
| Simulation time | 3470731740 ps |
| CPU time | 345.97 seconds |
| Started | Aug 12 07:36:08 PM PDT 24 |
| Finished | Aug 12 07:41:54 PM PDT 24 |
| Peak memory | 649284 kb |
| Host | smart-f37fbc96-1c08-4403-ab97-6a673b05afec |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4174016308 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.chip_ sw_alert_handler_lpg_sleep_mode_alerts.4174016308 |
| Directory | /workspace/37.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/37.chip_sw_all_escalation_resets.3991587903 |
| Short name | T889 |
| Test name | |
| Test status | |
| Simulation time | 5098624340 ps |
| CPU time | 640.44 seconds |
| Started | Aug 12 07:36:27 PM PDT 24 |
| Finished | Aug 12 07:47:07 PM PDT 24 |
| Peak memory | 650160 kb |
| Host | smart-150a803b-4722-4911-a4ee-4a1a8933d739 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 3991587903 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.chip_sw_all_escalation_resets.3991587903 |
| Directory | /workspace/37.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/39.chip_sw_alert_handler_lpg_sleep_mode_alerts.6471484 |
| Short name | T401 |
| Test name | |
| Test status | |
| Simulation time | 3867477120 ps |
| CPU time | 355.12 seconds |
| Started | Aug 12 07:36:16 PM PDT 24 |
| Finished | Aug 12 07:42:12 PM PDT 24 |
| Peak memory | 649424 kb |
| Host | smart-43dfcc1d-397f-4674-9624-1754163eaa04 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=6471484 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_e scalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.chip_sw_ alert_handler_lpg_sleep_mode_alerts.6471484 |
| Directory | /workspace/39.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/39.chip_sw_all_escalation_resets.603797301 |
| Short name | T874 |
| Test name | |
| Test status | |
| Simulation time | 4792326146 ps |
| CPU time | 502.29 seconds |
| Started | Aug 12 07:37:01 PM PDT 24 |
| Finished | Aug 12 07:45:23 PM PDT 24 |
| Peak memory | 650284 kb |
| Host | smart-70874bc1-4be2-4aa9-9003-a76220d4afd4 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 603797301 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.chip_sw_all_escalation_resets.603797301 |
| Directory | /workspace/39.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/4.chip_sw_alert_handler_lpg_sleep_mode_alerts.1955557391 |
| Short name | T832 |
| Test name | |
| Test status | |
| Simulation time | 4682309368 ps |
| CPU time | 405.53 seconds |
| Started | Aug 12 07:32:14 PM PDT 24 |
| Finished | Aug 12 07:39:00 PM PDT 24 |
| Peak memory | 649980 kb |
| Host | smart-9f407f2d-8040-4b0e-b6e0-26acd3670b0b |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1955557391 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.chip_s w_alert_handler_lpg_sleep_mode_alerts.1955557391 |
| Directory | /workspace/4.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/4.chip_sw_aon_timer_sleep_wdog_sleep_pause.4010866943 |
| Short name | T1345 |
| Test name | |
| Test status | |
| Simulation time | 6492440728 ps |
| CPU time | 412.23 seconds |
| Started | Aug 12 07:32:29 PM PDT 24 |
| Finished | Aug 12 07:39:22 PM PDT 24 |
| Peak memory | 609816 kb |
| Host | smart-aa236503-a805-41a2-a6c0-b1dd13725876 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=aon_timer_sleep_wdog_sleep_pause_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=4010866943 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.chip_sw_aon_timer_sleep_wdog_sleep_pause.4010866943 |
| Directory | /workspace/4.chip_sw_aon_timer_sleep_wdog_sleep_pause/latest |
| Test location | /workspace/coverage/default/4.chip_sw_csrng_edn_concurrency.2262058337 |
| Short name | T1195 |
| Test name | |
| Test status | |
| Simulation time | 20537112328 ps |
| CPU time | 5220.96 seconds |
| Started | Aug 12 07:32:17 PM PDT 24 |
| Finished | Aug 12 08:59:19 PM PDT 24 |
| Peak memory | 610840 kb |
| Host | smart-f96ab644-7e34-463b-841a-3e1db79c0d63 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=140_000_000 +rng_srate_value_min=15 +rng_srate_value_max=20 +sw_build_device=sim_dv +sw_images=csrng_edn_c oncurrency_test:1:new_rules,test_rom:0 +accelerate_cold_power_up_time=3 +accelerate_regulators_power_up_time=2 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2262058337 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd b -cm_log /dev/null -cm_name 4.chip_sw_csrng_edn_concurrency.2262058337 |
| Directory | /workspace/4.chip_sw_csrng_edn_concurrency/latest |
| Test location | /workspace/coverage/default/4.chip_sw_data_integrity_escalation.2354040587 |
| Short name | T245 |
| Test name | |
| Test status | |
| Simulation time | 4729569896 ps |
| CPU time | 757.14 seconds |
| Started | Aug 12 07:33:06 PM PDT 24 |
| Finished | Aug 12 07:45:44 PM PDT 24 |
| Peak memory | 611244 kb |
| Host | smart-b3eb7906-0541-4bf2-b585-a3d4cee83833 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=data_integrity_escalation_reset_test:1:new_rules,test_ro m:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=2354040587 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_data_integrity_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.chip_sw_data_integrity_escalation.2354040587 |
| Directory | /workspace/4.chip_sw_data_integrity_escalation/latest |
| Test location | /workspace/coverage/default/4.chip_sw_lc_ctrl_transition.4223299371 |
| Short name | T436 |
| Test name | |
| Test status | |
| Simulation time | 8619144364 ps |
| CPU time | 848.62 seconds |
| Started | Aug 12 07:31:12 PM PDT 24 |
| Finished | Aug 12 07:45:21 PM PDT 24 |
| Peak memory | 625192 kb |
| Host | smart-689718fd-d9cd-4245-a6c3-6d4d3b1bd097 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=lc_ctrl_transition_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4223299371 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_transition_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau lt.vdb -cm_log /dev/null -cm_name 4.chip_sw_lc_ctrl_transition.4223299371 |
| Directory | /workspace/4.chip_sw_lc_ctrl_transition/latest |
| Test location | /workspace/coverage/default/4.chip_sw_sensor_ctrl_alert.2007770229 |
| Short name | T148 |
| Test name | |
| Test status | |
| Simulation time | 5101967896 ps |
| CPU time | 660.24 seconds |
| Started | Aug 12 07:31:27 PM PDT 24 |
| Finished | Aug 12 07:42:27 PM PDT 24 |
| Peak memory | 610768 kb |
| Host | smart-5981a7a0-908e-4983-83d0-41446a559820 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=40_000_000 +sw_build_device=sim_dv +sw_images=sensor_ctrl_alert_test:1:new_rules,test_rom:0 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20077702 29 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac e/coverage/default.vdb -cm_log /dev/null -cm_name 4.chip_sw_sensor_ctrl_alert.2007770229 |
| Directory | /workspace/4.chip_sw_sensor_ctrl_alert/latest |
| Test location | /workspace/coverage/default/4.chip_sw_uart_rand_baudrate.2410375505 |
| Short name | T430 |
| Test name | |
| Test status | |
| Simulation time | 3619830000 ps |
| CPU time | 482.97 seconds |
| Started | Aug 12 07:31:37 PM PDT 24 |
| Finished | Aug 12 07:39:41 PM PDT 24 |
| Peak memory | 625044 kb |
| Host | smart-7205b92b-5e78-4244-a99e-c2e4b019fd3e |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random _seed=2410375505 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.chip_sw_uart_rand_baudrate.2410375505 |
| Directory | /workspace/4.chip_sw_uart_rand_baudrate/latest |
| Test location | /workspace/coverage/default/4.chip_sw_uart_tx_rx.3937014701 |
| Short name | T223 |
| Test name | |
| Test status | |
| Simulation time | 4571484132 ps |
| CPU time | 587.29 seconds |
| Started | Aug 12 07:31:19 PM PDT 24 |
| Finished | Aug 12 07:41:07 PM PDT 24 |
| Peak memory | 624288 kb |
| Host | smart-ecc1ea4e-b771-4b71-84f5-ee9e7f83f0cd |
| User | root |
| Command | /workspace/default/simv +uart_idx=0 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3937014701 -a ssert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ce/coverage/default.vdb -cm_log /dev/null -cm_name 4.chip_sw_uart_tx_rx.3937014701 |
| Directory | /workspace/4.chip_sw_uart_tx_rx/latest |
| Test location | /workspace/coverage/default/4.chip_sw_uart_tx_rx_alt_clk_freq.2119089157 |
| Short name | T449 |
| Test name | |
| Test status | |
| Simulation time | 3777440409 ps |
| CPU time | 659.83 seconds |
| Started | Aug 12 07:31:26 PM PDT 24 |
| Finished | Aug 12 07:42:26 PM PDT 24 |
| Peak memory | 624000 kb |
| Host | smart-e830fe38-0d59-4763-a546-cdbb8bbf4458 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=80_000_000 +chip_clock_source=ChipClockSourceExternal96Mhz +calibrate_usb_clk=1 +sw_build_device=sim_dv +s w_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2119089157 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_b audrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.chip_sw_uart_tx_rx _alt_clk_freq.2119089157 |
| Directory | /workspace/4.chip_sw_uart_tx_rx_alt_clk_freq/latest |
| Test location | /workspace/coverage/default/4.chip_sw_uart_tx_rx_idx1.2130977729 |
| Short name | T345 |
| Test name | |
| Test status | |
| Simulation time | 4701146310 ps |
| CPU time | 740.04 seconds |
| Started | Aug 12 07:34:04 PM PDT 24 |
| Finished | Aug 12 07:46:25 PM PDT 24 |
| Peak memory | 624288 kb |
| Host | smart-5f1ae77e-af14-4000-9a49-5498a7220575 |
| User | root |
| Command | /workspace/default/simv +uart_idx=1 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2130977729 -a ssert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ce/coverage/default.vdb -cm_log /dev/null -cm_name 4.chip_sw_uart_tx_rx_idx1.2130977729 |
| Directory | /workspace/4.chip_sw_uart_tx_rx_idx1/latest |
| Test location | /workspace/coverage/default/4.chip_sw_uart_tx_rx_idx2.2880394355 |
| Short name | T161 |
| Test name | |
| Test status | |
| Simulation time | 4077409304 ps |
| CPU time | 588.97 seconds |
| Started | Aug 12 07:31:03 PM PDT 24 |
| Finished | Aug 12 07:40:53 PM PDT 24 |
| Peak memory | 624316 kb |
| Host | smart-c732ff1f-8581-4c66-8a27-d5a423e0c183 |
| User | root |
| Command | /workspace/default/simv +uart_idx=2 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2880394355 -a ssert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ce/coverage/default.vdb -cm_log /dev/null -cm_name 4.chip_sw_uart_tx_rx_idx2.2880394355 |
| Directory | /workspace/4.chip_sw_uart_tx_rx_idx2/latest |
| Test location | /workspace/coverage/default/4.chip_sw_uart_tx_rx_idx3.1997734197 |
| Short name | T15 |
| Test name | |
| Test status | |
| Simulation time | 4413693088 ps |
| CPU time | 704.21 seconds |
| Started | Aug 12 07:32:09 PM PDT 24 |
| Finished | Aug 12 07:43:53 PM PDT 24 |
| Peak memory | 624280 kb |
| Host | smart-1f50847c-71f7-43d9-a689-5d2693348e2a |
| User | root |
| Command | /workspace/default/simv +uart_idx=3 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1997734197 -a ssert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ce/coverage/default.vdb -cm_log /dev/null -cm_name 4.chip_sw_uart_tx_rx_idx3.1997734197 |
| Directory | /workspace/4.chip_sw_uart_tx_rx_idx3/latest |
| Test location | /workspace/coverage/default/4.chip_tap_straps_dev.3495878347 |
| Short name | T753 |
| Test name | |
| Test status | |
| Simulation time | 11015270659 ps |
| CPU time | 1092.19 seconds |
| Started | Aug 12 07:31:25 PM PDT 24 |
| Finished | Aug 12 07:49:38 PM PDT 24 |
| Peak memory | 625004 kb |
| Host | smart-7318f607-3e34-49ee-9c5f-e719b9b11955 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStDev +create_jtag_riscv_map=1 +sw_build_device=sim_dv +sw_images=example_test_from_rom:0:test_in_rom: new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=3495878347 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_tap_straps_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.chip_tap_straps_dev.3495878347 |
| Directory | /workspace/4.chip_tap_straps_dev/latest |
| Test location | /workspace/coverage/default/4.chip_tap_straps_prod.2434057310 |
| Short name | T1016 |
| Test name | |
| Test status | |
| Simulation time | 9814176828 ps |
| CPU time | 1004.31 seconds |
| Started | Aug 12 07:32:07 PM PDT 24 |
| Finished | Aug 12 07:48:51 PM PDT 24 |
| Peak memory | 624988 kb |
| Host | smart-bc88e05f-c283-404b-83e9-d0df218514aa |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStProd +create_jtag_riscv_map=1 +sw_build_device=sim_dv +sw_images=example_test_from_rom:0:test_in_rom :new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2434057310 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_tap_straps_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.chip_tap_straps_prod.2434057310 |
| Directory | /workspace/4.chip_tap_straps_prod/latest |
| Test location | /workspace/coverage/default/4.chip_tap_straps_rma.3863144760 |
| Short name | T1306 |
| Test name | |
| Test status | |
| Simulation time | 6116941639 ps |
| CPU time | 630.8 seconds |
| Started | Aug 12 07:31:16 PM PDT 24 |
| Finished | Aug 12 07:41:47 PM PDT 24 |
| Peak memory | 625016 kb |
| Host | smart-e1293806-f7c2-4daf-842b-c266c69c7c0c |
| User | root |
| Command | /workspace/default/simv +create_jtag_riscv_map=1 +sw_build_device=sim_dv +sw_images=example_test_from_rom:0:test_in_rom:new_rules +cdc_instrumentation _enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3863144760 -as sert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_tap_straps_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/c overage/default.vdb -cm_log /dev/null -cm_name 4.chip_tap_straps_rma.3863144760 |
| Directory | /workspace/4.chip_tap_straps_rma/latest |
| Test location | /workspace/coverage/default/4.chip_tap_straps_testunlock0.854705117 |
| Short name | T68 |
| Test name | |
| Test status | |
| Simulation time | 3337223640 ps |
| CPU time | 233.48 seconds |
| Started | Aug 12 07:31:17 PM PDT 24 |
| Finished | Aug 12 07:35:10 PM PDT 24 |
| Peak memory | 624068 kb |
| Host | smart-f13b702f-a911-4957-94ae-fbd6d74acb9c |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStTestUnlocked0 +create_jtag_riscv_map=1 +sw_build_device=sim_dv +sw_images=example_test_from_rom:0:te st_in_rom:new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=854705117 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_tap_straps_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.chip_tap_straps_testunlock0.854705117 |
| Directory | /workspace/4.chip_tap_straps_testunlock0/latest |
| Test location | /workspace/coverage/default/40.chip_sw_all_escalation_resets.845231593 |
| Short name | T798 |
| Test name | |
| Test status | |
| Simulation time | 5490795790 ps |
| CPU time | 676.37 seconds |
| Started | Aug 12 07:37:35 PM PDT 24 |
| Finished | Aug 12 07:48:51 PM PDT 24 |
| Peak memory | 650544 kb |
| Host | smart-02fa2f58-6483-4783-b433-64e35ac4de78 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 845231593 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.chip_sw_all_escalation_resets.845231593 |
| Directory | /workspace/40.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/41.chip_sw_alert_handler_lpg_sleep_mode_alerts.148653854 |
| Short name | T277 |
| Test name | |
| Test status | |
| Simulation time | 3772957896 ps |
| CPU time | 381.6 seconds |
| Started | Aug 12 07:37:10 PM PDT 24 |
| Finished | Aug 12 07:43:32 PM PDT 24 |
| Peak memory | 649380 kb |
| Host | smart-338809cd-0760-4908-9386-77ec666fdcd4 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=148653854 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all _escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.chip_s w_alert_handler_lpg_sleep_mode_alerts.148653854 |
| Directory | /workspace/41.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/42.chip_sw_alert_handler_lpg_sleep_mode_alerts.970408908 |
| Short name | T794 |
| Test name | |
| Test status | |
| Simulation time | 3070335446 ps |
| CPU time | 400.52 seconds |
| Started | Aug 12 07:37:29 PM PDT 24 |
| Finished | Aug 12 07:44:10 PM PDT 24 |
| Peak memory | 649180 kb |
| Host | smart-c26b8c75-b5f7-4c69-ad21-a33372dd38fc |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=970408908 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all _escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.chip_s w_alert_handler_lpg_sleep_mode_alerts.970408908 |
| Directory | /workspace/42.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/42.chip_sw_all_escalation_resets.3160583877 |
| Short name | T842 |
| Test name | |
| Test status | |
| Simulation time | 4865909004 ps |
| CPU time | 647.12 seconds |
| Started | Aug 12 07:37:36 PM PDT 24 |
| Finished | Aug 12 07:48:24 PM PDT 24 |
| Peak memory | 650520 kb |
| Host | smart-54c72fe0-51c6-47fa-8846-449c140267af |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 3160583877 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.chip_sw_all_escalation_resets.3160583877 |
| Directory | /workspace/42.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/43.chip_sw_all_escalation_resets.1668787169 |
| Short name | T88 |
| Test name | |
| Test status | |
| Simulation time | 4577503918 ps |
| CPU time | 653.13 seconds |
| Started | Aug 12 07:37:32 PM PDT 24 |
| Finished | Aug 12 07:48:25 PM PDT 24 |
| Peak memory | 651244 kb |
| Host | smart-8db82df0-6bfd-4b50-8b9c-4852ca308b61 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 1668787169 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.chip_sw_all_escalation_resets.1668787169 |
| Directory | /workspace/43.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/44.chip_sw_alert_handler_lpg_sleep_mode_alerts.1689214310 |
| Short name | T830 |
| Test name | |
| Test status | |
| Simulation time | 4306031284 ps |
| CPU time | 400.8 seconds |
| Started | Aug 12 07:37:36 PM PDT 24 |
| Finished | Aug 12 07:44:17 PM PDT 24 |
| Peak memory | 649652 kb |
| Host | smart-afe4a176-2e4b-47b9-bd0d-2f1f8fe73761 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1689214310 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.chip_ sw_alert_handler_lpg_sleep_mode_alerts.1689214310 |
| Directory | /workspace/44.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/45.chip_sw_alert_handler_lpg_sleep_mode_alerts.3786207802 |
| Short name | T284 |
| Test name | |
| Test status | |
| Simulation time | 3740250356 ps |
| CPU time | 310.07 seconds |
| Started | Aug 12 07:38:59 PM PDT 24 |
| Finished | Aug 12 07:44:10 PM PDT 24 |
| Peak memory | 649372 kb |
| Host | smart-1a2aeb9a-0d67-48a4-a3ad-82f01cf369c8 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3786207802 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.chip_ sw_alert_handler_lpg_sleep_mode_alerts.3786207802 |
| Directory | /workspace/45.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/45.chip_sw_all_escalation_resets.1015115262 |
| Short name | T364 |
| Test name | |
| Test status | |
| Simulation time | 4165590540 ps |
| CPU time | 548.39 seconds |
| Started | Aug 12 07:37:47 PM PDT 24 |
| Finished | Aug 12 07:46:55 PM PDT 24 |
| Peak memory | 649996 kb |
| Host | smart-d5938e92-1a77-4087-8612-be86359a658e |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 1015115262 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.chip_sw_all_escalation_resets.1015115262 |
| Directory | /workspace/45.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/46.chip_sw_all_escalation_resets.3417087114 |
| Short name | T448 |
| Test name | |
| Test status | |
| Simulation time | 4994937440 ps |
| CPU time | 527.75 seconds |
| Started | Aug 12 07:37:25 PM PDT 24 |
| Finished | Aug 12 07:46:13 PM PDT 24 |
| Peak memory | 650312 kb |
| Host | smart-f0355e96-ab75-41ea-bfba-a6ac5c601a1e |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 3417087114 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.chip_sw_all_escalation_resets.3417087114 |
| Directory | /workspace/46.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/47.chip_sw_all_escalation_resets.3347325678 |
| Short name | T850 |
| Test name | |
| Test status | |
| Simulation time | 4663392910 ps |
| CPU time | 464.12 seconds |
| Started | Aug 12 07:37:35 PM PDT 24 |
| Finished | Aug 12 07:45:19 PM PDT 24 |
| Peak memory | 650556 kb |
| Host | smart-e3cc59d1-0514-4f2d-95fe-a4772fa2fda5 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 3347325678 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.chip_sw_all_escalation_resets.3347325678 |
| Directory | /workspace/47.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/48.chip_sw_alert_handler_lpg_sleep_mode_alerts.3388502403 |
| Short name | T1013 |
| Test name | |
| Test status | |
| Simulation time | 4078822088 ps |
| CPU time | 387.62 seconds |
| Started | Aug 12 07:37:51 PM PDT 24 |
| Finished | Aug 12 07:44:19 PM PDT 24 |
| Peak memory | 619376 kb |
| Host | smart-74e6620c-4efe-4dbc-9e62-408ba490a763 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3388502403 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.chip_ sw_alert_handler_lpg_sleep_mode_alerts.3388502403 |
| Directory | /workspace/48.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/49.chip_sw_alert_handler_lpg_sleep_mode_alerts.2824085505 |
| Short name | T1362 |
| Test name | |
| Test status | |
| Simulation time | 3651922348 ps |
| CPU time | 482.18 seconds |
| Started | Aug 12 07:37:57 PM PDT 24 |
| Finished | Aug 12 07:46:00 PM PDT 24 |
| Peak memory | 649396 kb |
| Host | smart-026ec765-0437-43cf-950a-6c9a75cb1365 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2824085505 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.chip_ sw_alert_handler_lpg_sleep_mode_alerts.2824085505 |
| Directory | /workspace/49.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/5.chip_sw_alert_handler_lpg_sleep_mode_alerts.2657127944 |
| Short name | T878 |
| Test name | |
| Test status | |
| Simulation time | 3459676568 ps |
| CPU time | 316.86 seconds |
| Started | Aug 12 07:32:32 PM PDT 24 |
| Finished | Aug 12 07:37:49 PM PDT 24 |
| Peak memory | 649056 kb |
| Host | smart-883fbb80-f113-494d-bd4e-6e6bc275fd90 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2657127944 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.chip_s w_alert_handler_lpg_sleep_mode_alerts.2657127944 |
| Directory | /workspace/5.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/5.chip_sw_csrng_edn_concurrency.1283328091 |
| Short name | T1253 |
| Test name | |
| Test status | |
| Simulation time | 21675752408 ps |
| CPU time | 4774.41 seconds |
| Started | Aug 12 07:33:37 PM PDT 24 |
| Finished | Aug 12 08:53:12 PM PDT 24 |
| Peak memory | 610784 kb |
| Host | smart-b3c1166a-0d3f-4d09-bff0-0f04e97cbdc0 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=140_000_000 +rng_srate_value_min=15 +rng_srate_value_max=20 +sw_build_device=sim_dv +sw_images=csrng_edn_c oncurrency_test:1:new_rules,test_rom:0 +accelerate_cold_power_up_time=3 +accelerate_regulators_power_up_time=2 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1283328091 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd b -cm_log /dev/null -cm_name 5.chip_sw_csrng_edn_concurrency.1283328091 |
| Directory | /workspace/5.chip_sw_csrng_edn_concurrency/latest |
| Test location | /workspace/coverage/default/5.chip_sw_data_integrity_escalation.1228422071 |
| Short name | T1368 |
| Test name | |
| Test status | |
| Simulation time | 6612492192 ps |
| CPU time | 914.91 seconds |
| Started | Aug 12 07:32:28 PM PDT 24 |
| Finished | Aug 12 07:47:43 PM PDT 24 |
| Peak memory | 611556 kb |
| Host | smart-4b8f33f5-ba4c-4dd0-ba29-8f5a8ce5c1a6 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=data_integrity_escalation_reset_test:1:new_rules,test_ro m:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=1228422071 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_data_integrity_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.chip_sw_data_integrity_escalation.1228422071 |
| Directory | /workspace/5.chip_sw_data_integrity_escalation/latest |
| Test location | /workspace/coverage/default/5.chip_sw_lc_ctrl_transition.2553192451 |
| Short name | T197 |
| Test name | |
| Test status | |
| Simulation time | 8718454904 ps |
| CPU time | 917.69 seconds |
| Started | Aug 12 07:33:13 PM PDT 24 |
| Finished | Aug 12 07:48:31 PM PDT 24 |
| Peak memory | 621536 kb |
| Host | smart-94668b94-4779-420a-8289-d2bdb02596fe |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=lc_ctrl_transition_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2553192451 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_transition_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau lt.vdb -cm_log /dev/null -cm_name 5.chip_sw_lc_ctrl_transition.2553192451 |
| Directory | /workspace/5.chip_sw_lc_ctrl_transition/latest |
| Test location | /workspace/coverage/default/5.chip_sw_uart_rand_baudrate.905322076 |
| Short name | T426 |
| Test name | |
| Test status | |
| Simulation time | 8555210820 ps |
| CPU time | 1449.7 seconds |
| Started | Aug 12 07:32:03 PM PDT 24 |
| Finished | Aug 12 07:56:13 PM PDT 24 |
| Peak memory | 623872 kb |
| Host | smart-4a3cc8bf-f930-4a77-8355-6d9084b5e566 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random _seed=905322076 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.chip_sw_uart_rand_baudrate.905322076 |
| Directory | /workspace/5.chip_sw_uart_rand_baudrate/latest |
| Test location | /workspace/coverage/default/51.chip_sw_alert_handler_lpg_sleep_mode_alerts.2381461323 |
| Short name | T1193 |
| Test name | |
| Test status | |
| Simulation time | 3277354146 ps |
| CPU time | 312.97 seconds |
| Started | Aug 12 07:38:54 PM PDT 24 |
| Finished | Aug 12 07:44:07 PM PDT 24 |
| Peak memory | 649100 kb |
| Host | smart-1f057f49-d26a-4504-8e9f-201ab1388531 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2381461323 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 51.chip_ sw_alert_handler_lpg_sleep_mode_alerts.2381461323 |
| Directory | /workspace/51.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/51.chip_sw_all_escalation_resets.3542737375 |
| Short name | T328 |
| Test name | |
| Test status | |
| Simulation time | 3923108456 ps |
| CPU time | 424.22 seconds |
| Started | Aug 12 07:37:37 PM PDT 24 |
| Finished | Aug 12 07:44:42 PM PDT 24 |
| Peak memory | 650252 kb |
| Host | smart-2313e3fd-66ef-4585-917e-25ecb0e3dae3 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 3542737375 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 51.chip_sw_all_escalation_resets.3542737375 |
| Directory | /workspace/51.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/53.chip_sw_alert_handler_lpg_sleep_mode_alerts.436485277 |
| Short name | T249 |
| Test name | |
| Test status | |
| Simulation time | 3540541752 ps |
| CPU time | 323.33 seconds |
| Started | Aug 12 07:39:01 PM PDT 24 |
| Finished | Aug 12 07:44:25 PM PDT 24 |
| Peak memory | 649336 kb |
| Host | smart-83b275d7-fb28-4bf9-b216-9510f7ccb559 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=436485277 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all _escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 53.chip_s w_alert_handler_lpg_sleep_mode_alerts.436485277 |
| Directory | /workspace/53.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/53.chip_sw_all_escalation_resets.3682488570 |
| Short name | T1398 |
| Test name | |
| Test status | |
| Simulation time | 5804495060 ps |
| CPU time | 759.61 seconds |
| Started | Aug 12 07:39:36 PM PDT 24 |
| Finished | Aug 12 07:52:16 PM PDT 24 |
| Peak memory | 650532 kb |
| Host | smart-870c1fc8-4931-4356-b224-863467ba428b |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 3682488570 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 53.chip_sw_all_escalation_resets.3682488570 |
| Directory | /workspace/53.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/54.chip_sw_all_escalation_resets.2103716251 |
| Short name | T372 |
| Test name | |
| Test status | |
| Simulation time | 4296468086 ps |
| CPU time | 623.65 seconds |
| Started | Aug 12 07:39:39 PM PDT 24 |
| Finished | Aug 12 07:50:03 PM PDT 24 |
| Peak memory | 650384 kb |
| Host | smart-2a67c079-e43a-466f-b229-72122356eab5 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 2103716251 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 54.chip_sw_all_escalation_resets.2103716251 |
| Directory | /workspace/54.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/55.chip_sw_all_escalation_resets.972484850 |
| Short name | T89 |
| Test name | |
| Test status | |
| Simulation time | 4803947240 ps |
| CPU time | 581.33 seconds |
| Started | Aug 12 07:41:56 PM PDT 24 |
| Finished | Aug 12 07:51:38 PM PDT 24 |
| Peak memory | 651128 kb |
| Host | smart-1b6a08c7-e256-42bb-9aa8-0d718425733f |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 972484850 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 55.chip_sw_all_escalation_resets.972484850 |
| Directory | /workspace/55.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/56.chip_sw_alert_handler_lpg_sleep_mode_alerts.86749870 |
| Short name | T816 |
| Test name | |
| Test status | |
| Simulation time | 3711532988 ps |
| CPU time | 339.94 seconds |
| Started | Aug 12 07:37:48 PM PDT 24 |
| Finished | Aug 12 07:43:28 PM PDT 24 |
| Peak memory | 649108 kb |
| Host | smart-540e473e-0967-46f5-a685-78149ee371cd |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86749870 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_ escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 56.chip_sw _alert_handler_lpg_sleep_mode_alerts.86749870 |
| Directory | /workspace/56.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/57.chip_sw_alert_handler_lpg_sleep_mode_alerts.3579721183 |
| Short name | T296 |
| Test name | |
| Test status | |
| Simulation time | 3203982492 ps |
| CPU time | 394.99 seconds |
| Started | Aug 12 07:38:36 PM PDT 24 |
| Finished | Aug 12 07:45:11 PM PDT 24 |
| Peak memory | 649404 kb |
| Host | smart-81f2f92d-16a4-486a-8c74-a7b97f39111c |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3579721183 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 57.chip_ sw_alert_handler_lpg_sleep_mode_alerts.3579721183 |
| Directory | /workspace/57.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/58.chip_sw_alert_handler_lpg_sleep_mode_alerts.1151946945 |
| Short name | T867 |
| Test name | |
| Test status | |
| Simulation time | 2941987040 ps |
| CPU time | 408.38 seconds |
| Started | Aug 12 07:38:27 PM PDT 24 |
| Finished | Aug 12 07:45:15 PM PDT 24 |
| Peak memory | 649052 kb |
| Host | smart-86a29db5-c8ac-4f0e-a6b4-082a4d33c90b |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1151946945 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 58.chip_ sw_alert_handler_lpg_sleep_mode_alerts.1151946945 |
| Directory | /workspace/58.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/58.chip_sw_all_escalation_resets.1365585513 |
| Short name | T891 |
| Test name | |
| Test status | |
| Simulation time | 5774823872 ps |
| CPU time | 520.07 seconds |
| Started | Aug 12 07:38:42 PM PDT 24 |
| Finished | Aug 12 07:47:23 PM PDT 24 |
| Peak memory | 650184 kb |
| Host | smart-b0e5ce43-fc93-41d4-a605-17fb47c6ac5f |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 1365585513 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 58.chip_sw_all_escalation_resets.1365585513 |
| Directory | /workspace/58.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/59.chip_sw_alert_handler_lpg_sleep_mode_alerts.1989467146 |
| Short name | T299 |
| Test name | |
| Test status | |
| Simulation time | 3406171354 ps |
| CPU time | 387.7 seconds |
| Started | Aug 12 07:42:43 PM PDT 24 |
| Finished | Aug 12 07:49:10 PM PDT 24 |
| Peak memory | 649048 kb |
| Host | smart-871ad187-f1e1-4be7-aa51-4e8d2e9a330a |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1989467146 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 59.chip_ sw_alert_handler_lpg_sleep_mode_alerts.1989467146 |
| Directory | /workspace/59.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/6.chip_sw_alert_handler_lpg_sleep_mode_alerts.2179113094 |
| Short name | T870 |
| Test name | |
| Test status | |
| Simulation time | 3786747600 ps |
| CPU time | 389.58 seconds |
| Started | Aug 12 07:32:28 PM PDT 24 |
| Finished | Aug 12 07:38:58 PM PDT 24 |
| Peak memory | 649056 kb |
| Host | smart-1474d0f9-91a2-41c9-9c3f-02a16b241813 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2179113094 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.chip_s w_alert_handler_lpg_sleep_mode_alerts.2179113094 |
| Directory | /workspace/6.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/6.chip_sw_all_escalation_resets.742716021 |
| Short name | T91 |
| Test name | |
| Test status | |
| Simulation time | 4348747298 ps |
| CPU time | 665.14 seconds |
| Started | Aug 12 07:33:09 PM PDT 24 |
| Finished | Aug 12 07:44:14 PM PDT 24 |
| Peak memory | 651120 kb |
| Host | smart-e99d03df-5378-4d29-b7d8-72fa162a5af6 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 742716021 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.chip_sw_all_escalation_resets.742716021 |
| Directory | /workspace/6.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/6.chip_sw_csrng_edn_concurrency.3699952303 |
| Short name | T262 |
| Test name | |
| Test status | |
| Simulation time | 16771717440 ps |
| CPU time | 3285.08 seconds |
| Started | Aug 12 07:32:54 PM PDT 24 |
| Finished | Aug 12 08:27:40 PM PDT 24 |
| Peak memory | 610804 kb |
| Host | smart-8355dbf2-b647-478e-826d-f3e0d4d3366a |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=140_000_000 +rng_srate_value_min=15 +rng_srate_value_max=20 +sw_build_device=sim_dv +sw_images=csrng_edn_c oncurrency_test:1:new_rules,test_rom:0 +accelerate_cold_power_up_time=3 +accelerate_regulators_power_up_time=2 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3699952303 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd b -cm_log /dev/null -cm_name 6.chip_sw_csrng_edn_concurrency.3699952303 |
| Directory | /workspace/6.chip_sw_csrng_edn_concurrency/latest |
| Test location | /workspace/coverage/default/6.chip_sw_lc_ctrl_transition.2122054096 |
| Short name | T1076 |
| Test name | |
| Test status | |
| Simulation time | 10002318967 ps |
| CPU time | 886.07 seconds |
| Started | Aug 12 07:35:42 PM PDT 24 |
| Finished | Aug 12 07:50:28 PM PDT 24 |
| Peak memory | 625144 kb |
| Host | smart-41a3c6d3-33b4-48d1-a91a-5973a20d72af |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=lc_ctrl_transition_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2122054096 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_transition_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau lt.vdb -cm_log /dev/null -cm_name 6.chip_sw_lc_ctrl_transition.2122054096 |
| Directory | /workspace/6.chip_sw_lc_ctrl_transition/latest |
| Test location | /workspace/coverage/default/6.chip_sw_uart_rand_baudrate.305000919 |
| Short name | T358 |
| Test name | |
| Test status | |
| Simulation time | 8565551760 ps |
| CPU time | 1596.86 seconds |
| Started | Aug 12 07:33:40 PM PDT 24 |
| Finished | Aug 12 08:00:17 PM PDT 24 |
| Peak memory | 625080 kb |
| Host | smart-452732f4-4ba0-4364-94a4-c74ee0b1bbe3 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random _seed=305000919 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.chip_sw_uart_rand_baudrate.305000919 |
| Directory | /workspace/6.chip_sw_uart_rand_baudrate/latest |
| Test location | /workspace/coverage/default/60.chip_sw_alert_handler_lpg_sleep_mode_alerts.589726590 |
| Short name | T849 |
| Test name | |
| Test status | |
| Simulation time | 3757409816 ps |
| CPU time | 390.07 seconds |
| Started | Aug 12 07:39:14 PM PDT 24 |
| Finished | Aug 12 07:45:45 PM PDT 24 |
| Peak memory | 649360 kb |
| Host | smart-630bb70b-fc06-47e8-a8f4-5035ee4d2ae7 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=589726590 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all _escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 60.chip_s w_alert_handler_lpg_sleep_mode_alerts.589726590 |
| Directory | /workspace/60.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/61.chip_sw_alert_handler_lpg_sleep_mode_alerts.3453560569 |
| Short name | T337 |
| Test name | |
| Test status | |
| Simulation time | 3884418494 ps |
| CPU time | 385.2 seconds |
| Started | Aug 12 07:39:41 PM PDT 24 |
| Finished | Aug 12 07:46:06 PM PDT 24 |
| Peak memory | 649296 kb |
| Host | smart-506d8546-bbd5-4abd-9413-5c3e62f488b0 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3453560569 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 61.chip_ sw_alert_handler_lpg_sleep_mode_alerts.3453560569 |
| Directory | /workspace/61.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/61.chip_sw_all_escalation_resets.1523376435 |
| Short name | T1330 |
| Test name | |
| Test status | |
| Simulation time | 4691149080 ps |
| CPU time | 757.7 seconds |
| Started | Aug 12 07:39:39 PM PDT 24 |
| Finished | Aug 12 07:52:17 PM PDT 24 |
| Peak memory | 617288 kb |
| Host | smart-33e63c4f-ab7e-49f1-ae26-41fdb39fc603 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 1523376435 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 61.chip_sw_all_escalation_resets.1523376435 |
| Directory | /workspace/61.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/62.chip_sw_alert_handler_lpg_sleep_mode_alerts.3558396586 |
| Short name | T823 |
| Test name | |
| Test status | |
| Simulation time | 4141082504 ps |
| CPU time | 393.94 seconds |
| Started | Aug 12 07:38:24 PM PDT 24 |
| Finished | Aug 12 07:44:58 PM PDT 24 |
| Peak memory | 649328 kb |
| Host | smart-cc80d7e3-d803-448d-8830-751fbf613d88 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3558396586 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 62.chip_ sw_alert_handler_lpg_sleep_mode_alerts.3558396586 |
| Directory | /workspace/62.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/62.chip_sw_all_escalation_resets.778575803 |
| Short name | T871 |
| Test name | |
| Test status | |
| Simulation time | 4460040260 ps |
| CPU time | 601.34 seconds |
| Started | Aug 12 07:38:04 PM PDT 24 |
| Finished | Aug 12 07:48:06 PM PDT 24 |
| Peak memory | 650456 kb |
| Host | smart-aabff15a-7c79-4748-8bf6-72fe4984a667 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 778575803 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 62.chip_sw_all_escalation_resets.778575803 |
| Directory | /workspace/62.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/63.chip_sw_alert_handler_lpg_sleep_mode_alerts.1241591598 |
| Short name | T219 |
| Test name | |
| Test status | |
| Simulation time | 3490573806 ps |
| CPU time | 422.52 seconds |
| Started | Aug 12 07:38:49 PM PDT 24 |
| Finished | Aug 12 07:45:52 PM PDT 24 |
| Peak memory | 649400 kb |
| Host | smart-fcf177c6-ab8b-45b8-929f-507b4fd8155e |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1241591598 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 63.chip_ sw_alert_handler_lpg_sleep_mode_alerts.1241591598 |
| Directory | /workspace/63.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/64.chip_sw_alert_handler_lpg_sleep_mode_alerts.3647156169 |
| Short name | T1298 |
| Test name | |
| Test status | |
| Simulation time | 4052918420 ps |
| CPU time | 400.43 seconds |
| Started | Aug 12 07:40:20 PM PDT 24 |
| Finished | Aug 12 07:47:00 PM PDT 24 |
| Peak memory | 649332 kb |
| Host | smart-3b6d4dc7-2df6-40a6-8078-c9ab15fbcbcb |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3647156169 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 64.chip_ sw_alert_handler_lpg_sleep_mode_alerts.3647156169 |
| Directory | /workspace/64.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/64.chip_sw_all_escalation_resets.3070655534 |
| Short name | T321 |
| Test name | |
| Test status | |
| Simulation time | 4048327228 ps |
| CPU time | 478.68 seconds |
| Started | Aug 12 07:38:44 PM PDT 24 |
| Finished | Aug 12 07:46:43 PM PDT 24 |
| Peak memory | 650488 kb |
| Host | smart-b7f5eb4c-b19a-4dbb-a661-9f9f3e93cbd0 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 3070655534 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 64.chip_sw_all_escalation_resets.3070655534 |
| Directory | /workspace/64.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/65.chip_sw_alert_handler_lpg_sleep_mode_alerts.1930972957 |
| Short name | T840 |
| Test name | |
| Test status | |
| Simulation time | 3707702906 ps |
| CPU time | 355.24 seconds |
| Started | Aug 12 07:39:47 PM PDT 24 |
| Finished | Aug 12 07:45:42 PM PDT 24 |
| Peak memory | 649208 kb |
| Host | smart-68becfd6-5b5c-4961-b4ac-bd06e4effd94 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1930972957 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 65.chip_ sw_alert_handler_lpg_sleep_mode_alerts.1930972957 |
| Directory | /workspace/65.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/65.chip_sw_all_escalation_resets.2101857472 |
| Short name | T853 |
| Test name | |
| Test status | |
| Simulation time | 5324573680 ps |
| CPU time | 572.24 seconds |
| Started | Aug 12 07:40:34 PM PDT 24 |
| Finished | Aug 12 07:50:06 PM PDT 24 |
| Peak memory | 650768 kb |
| Host | smart-1ad96fd0-270e-4fa7-95aa-6427aff5b1c3 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 2101857472 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 65.chip_sw_all_escalation_resets.2101857472 |
| Directory | /workspace/65.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/66.chip_sw_all_escalation_resets.1023343551 |
| Short name | T1354 |
| Test name | |
| Test status | |
| Simulation time | 4934024568 ps |
| CPU time | 527.04 seconds |
| Started | Aug 12 07:40:12 PM PDT 24 |
| Finished | Aug 12 07:48:59 PM PDT 24 |
| Peak memory | 617252 kb |
| Host | smart-afaf6567-c900-4260-951c-26e8e9e86cdc |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 1023343551 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 66.chip_sw_all_escalation_resets.1023343551 |
| Directory | /workspace/66.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/67.chip_sw_alert_handler_lpg_sleep_mode_alerts.3546386535 |
| Short name | T866 |
| Test name | |
| Test status | |
| Simulation time | 4056981340 ps |
| CPU time | 375.94 seconds |
| Started | Aug 12 07:41:33 PM PDT 24 |
| Finished | Aug 12 07:47:49 PM PDT 24 |
| Peak memory | 649336 kb |
| Host | smart-552f1fcb-67e9-40ab-8d48-7f34fe733d28 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3546386535 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 67.chip_ sw_alert_handler_lpg_sleep_mode_alerts.3546386535 |
| Directory | /workspace/67.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/67.chip_sw_all_escalation_resets.1825387949 |
| Short name | T303 |
| Test name | |
| Test status | |
| Simulation time | 4901621208 ps |
| CPU time | 634.25 seconds |
| Started | Aug 12 07:39:14 PM PDT 24 |
| Finished | Aug 12 07:49:48 PM PDT 24 |
| Peak memory | 650444 kb |
| Host | smart-4bf4ef21-f751-4ca1-aaab-45a837dee0ad |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 1825387949 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 67.chip_sw_all_escalation_resets.1825387949 |
| Directory | /workspace/67.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/68.chip_sw_alert_handler_lpg_sleep_mode_alerts.1502136899 |
| Short name | T389 |
| Test name | |
| Test status | |
| Simulation time | 3932670680 ps |
| CPU time | 287.08 seconds |
| Started | Aug 12 07:40:24 PM PDT 24 |
| Finished | Aug 12 07:45:11 PM PDT 24 |
| Peak memory | 649336 kb |
| Host | smart-a889fce1-cc02-4d8b-9742-8ddec50bbe25 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1502136899 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 68.chip_ sw_alert_handler_lpg_sleep_mode_alerts.1502136899 |
| Directory | /workspace/68.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/68.chip_sw_all_escalation_resets.629618272 |
| Short name | T819 |
| Test name | |
| Test status | |
| Simulation time | 5196267480 ps |
| CPU time | 593.29 seconds |
| Started | Aug 12 07:38:56 PM PDT 24 |
| Finished | Aug 12 07:48:49 PM PDT 24 |
| Peak memory | 650500 kb |
| Host | smart-57ce35d5-2031-46c6-9bbf-812b2dd45dc2 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 629618272 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 68.chip_sw_all_escalation_resets.629618272 |
| Directory | /workspace/68.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/69.chip_sw_alert_handler_lpg_sleep_mode_alerts.2043998652 |
| Short name | T890 |
| Test name | |
| Test status | |
| Simulation time | 3953699900 ps |
| CPU time | 331.61 seconds |
| Started | Aug 12 07:40:06 PM PDT 24 |
| Finished | Aug 12 07:45:38 PM PDT 24 |
| Peak memory | 648952 kb |
| Host | smart-aa446d7b-50c0-45c9-b296-7b673a477249 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2043998652 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 69.chip_ sw_alert_handler_lpg_sleep_mode_alerts.2043998652 |
| Directory | /workspace/69.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/7.chip_sw_alert_handler_lpg_sleep_mode_alerts.2818163815 |
| Short name | T1226 |
| Test name | |
| Test status | |
| Simulation time | 4129985064 ps |
| CPU time | 505.78 seconds |
| Started | Aug 12 07:33:37 PM PDT 24 |
| Finished | Aug 12 07:42:03 PM PDT 24 |
| Peak memory | 649288 kb |
| Host | smart-8902f814-ad93-4d18-809d-b33c42e70a44 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2818163815 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.chip_s w_alert_handler_lpg_sleep_mode_alerts.2818163815 |
| Directory | /workspace/7.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/7.chip_sw_csrng_edn_concurrency.2247244093 |
| Short name | T1392 |
| Test name | |
| Test status | |
| Simulation time | 20680413340 ps |
| CPU time | 4558.13 seconds |
| Started | Aug 12 07:33:20 PM PDT 24 |
| Finished | Aug 12 08:49:18 PM PDT 24 |
| Peak memory | 610604 kb |
| Host | smart-0a1b7c63-23e1-43bc-930b-f7fb3bbbe42d |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=140_000_000 +rng_srate_value_min=15 +rng_srate_value_max=20 +sw_build_device=sim_dv +sw_images=csrng_edn_c oncurrency_test:1:new_rules,test_rom:0 +accelerate_cold_power_up_time=3 +accelerate_regulators_power_up_time=2 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2247244093 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd b -cm_log /dev/null -cm_name 7.chip_sw_csrng_edn_concurrency.2247244093 |
| Directory | /workspace/7.chip_sw_csrng_edn_concurrency/latest |
| Test location | /workspace/coverage/default/7.chip_sw_lc_ctrl_transition.3464655684 |
| Short name | T996 |
| Test name | |
| Test status | |
| Simulation time | 7791306453 ps |
| CPU time | 641.87 seconds |
| Started | Aug 12 07:32:42 PM PDT 24 |
| Finished | Aug 12 07:43:24 PM PDT 24 |
| Peak memory | 625176 kb |
| Host | smart-c24e364e-9e36-4a84-8c8a-e26be3ad55c0 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=lc_ctrl_transition_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3464655684 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_transition_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau lt.vdb -cm_log /dev/null -cm_name 7.chip_sw_lc_ctrl_transition.3464655684 |
| Directory | /workspace/7.chip_sw_lc_ctrl_transition/latest |
| Test location | /workspace/coverage/default/7.chip_sw_uart_rand_baudrate.1930066054 |
| Short name | T1037 |
| Test name | |
| Test status | |
| Simulation time | 4061248320 ps |
| CPU time | 695.96 seconds |
| Started | Aug 12 07:32:20 PM PDT 24 |
| Finished | Aug 12 07:43:57 PM PDT 24 |
| Peak memory | 623872 kb |
| Host | smart-063c3ccd-e73f-4323-8fac-7bd01a55931c |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random _seed=1930066054 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.chip_sw_uart_rand_baudrate.1930066054 |
| Directory | /workspace/7.chip_sw_uart_rand_baudrate/latest |
| Test location | /workspace/coverage/default/70.chip_sw_alert_handler_lpg_sleep_mode_alerts.2911403708 |
| Short name | T813 |
| Test name | |
| Test status | |
| Simulation time | 3768262460 ps |
| CPU time | 541.16 seconds |
| Started | Aug 12 07:39:59 PM PDT 24 |
| Finished | Aug 12 07:49:01 PM PDT 24 |
| Peak memory | 649408 kb |
| Host | smart-93ba968b-4963-4c35-aec0-c9ec02064e0a |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2911403708 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 70.chip_ sw_alert_handler_lpg_sleep_mode_alerts.2911403708 |
| Directory | /workspace/70.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/71.chip_sw_alert_handler_lpg_sleep_mode_alerts.1962433762 |
| Short name | T326 |
| Test name | |
| Test status | |
| Simulation time | 3114281076 ps |
| CPU time | 347.68 seconds |
| Started | Aug 12 07:39:16 PM PDT 24 |
| Finished | Aug 12 07:45:04 PM PDT 24 |
| Peak memory | 649544 kb |
| Host | smart-c6a70049-03db-4cb6-9bb3-94f60e4ff7a7 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1962433762 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 71.chip_ sw_alert_handler_lpg_sleep_mode_alerts.1962433762 |
| Directory | /workspace/71.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/71.chip_sw_all_escalation_resets.4096047670 |
| Short name | T877 |
| Test name | |
| Test status | |
| Simulation time | 5982570916 ps |
| CPU time | 476.32 seconds |
| Started | Aug 12 07:39:23 PM PDT 24 |
| Finished | Aug 12 07:47:19 PM PDT 24 |
| Peak memory | 650324 kb |
| Host | smart-80b461bc-bf73-47fc-b4c0-b3e0d17f01f3 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 4096047670 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 71.chip_sw_all_escalation_resets.4096047670 |
| Directory | /workspace/71.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/72.chip_sw_alert_handler_lpg_sleep_mode_alerts.1696037911 |
| Short name | T1431 |
| Test name | |
| Test status | |
| Simulation time | 3160233960 ps |
| CPU time | 359.43 seconds |
| Started | Aug 12 07:39:27 PM PDT 24 |
| Finished | Aug 12 07:45:27 PM PDT 24 |
| Peak memory | 649400 kb |
| Host | smart-c44da9b3-21e0-4feb-a0be-d2f7fb102ace |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1696037911 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 72.chip_ sw_alert_handler_lpg_sleep_mode_alerts.1696037911 |
| Directory | /workspace/72.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/72.chip_sw_all_escalation_resets.1972239953 |
| Short name | T1359 |
| Test name | |
| Test status | |
| Simulation time | 4619324528 ps |
| CPU time | 600.61 seconds |
| Started | Aug 12 07:39:41 PM PDT 24 |
| Finished | Aug 12 07:49:42 PM PDT 24 |
| Peak memory | 650720 kb |
| Host | smart-1851d60a-514b-4047-868b-21d20fd6bcef |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 1972239953 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 72.chip_sw_all_escalation_resets.1972239953 |
| Directory | /workspace/72.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/73.chip_sw_all_escalation_resets.1497976255 |
| Short name | T820 |
| Test name | |
| Test status | |
| Simulation time | 5363224760 ps |
| CPU time | 508.9 seconds |
| Started | Aug 12 07:40:58 PM PDT 24 |
| Finished | Aug 12 07:49:28 PM PDT 24 |
| Peak memory | 650176 kb |
| Host | smart-2b7de8a2-8bba-4420-bdf1-ee1cffe51284 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 1497976255 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 73.chip_sw_all_escalation_resets.1497976255 |
| Directory | /workspace/73.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/74.chip_sw_all_escalation_resets.889968404 |
| Short name | T876 |
| Test name | |
| Test status | |
| Simulation time | 4341963120 ps |
| CPU time | 597.94 seconds |
| Started | Aug 12 07:39:49 PM PDT 24 |
| Finished | Aug 12 07:49:47 PM PDT 24 |
| Peak memory | 650484 kb |
| Host | smart-8e5e37d7-3d32-4735-8226-c664d493664b |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 889968404 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 74.chip_sw_all_escalation_resets.889968404 |
| Directory | /workspace/74.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/75.chip_sw_all_escalation_resets.3850410967 |
| Short name | T271 |
| Test name | |
| Test status | |
| Simulation time | 4952295370 ps |
| CPU time | 650.66 seconds |
| Started | Aug 12 07:41:01 PM PDT 24 |
| Finished | Aug 12 07:51:52 PM PDT 24 |
| Peak memory | 650592 kb |
| Host | smart-c2f9503f-0b89-4916-b852-fa2d773461f7 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 3850410967 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 75.chip_sw_all_escalation_resets.3850410967 |
| Directory | /workspace/75.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/76.chip_sw_all_escalation_resets.3093623095 |
| Short name | T325 |
| Test name | |
| Test status | |
| Simulation time | 4779574994 ps |
| CPU time | 536.15 seconds |
| Started | Aug 12 07:40:49 PM PDT 24 |
| Finished | Aug 12 07:49:45 PM PDT 24 |
| Peak memory | 650848 kb |
| Host | smart-73478a47-e5da-416d-8fb9-e55c48b4fa2a |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 3093623095 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 76.chip_sw_all_escalation_resets.3093623095 |
| Directory | /workspace/76.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/77.chip_sw_all_escalation_resets.567575223 |
| Short name | T1179 |
| Test name | |
| Test status | |
| Simulation time | 5200196304 ps |
| CPU time | 604.22 seconds |
| Started | Aug 12 07:40:57 PM PDT 24 |
| Finished | Aug 12 07:51:02 PM PDT 24 |
| Peak memory | 650580 kb |
| Host | smart-f8253984-87a0-4d47-8362-2c19e712759c |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 567575223 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 77.chip_sw_all_escalation_resets.567575223 |
| Directory | /workspace/77.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/78.chip_sw_alert_handler_lpg_sleep_mode_alerts.687527536 |
| Short name | T857 |
| Test name | |
| Test status | |
| Simulation time | 3365578398 ps |
| CPU time | 418.47 seconds |
| Started | Aug 12 07:40:29 PM PDT 24 |
| Finished | Aug 12 07:47:28 PM PDT 24 |
| Peak memory | 649080 kb |
| Host | smart-0d0cb8ca-291f-4015-b9e3-da43cd8e7b47 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=687527536 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all _escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 78.chip_s w_alert_handler_lpg_sleep_mode_alerts.687527536 |
| Directory | /workspace/78.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/78.chip_sw_all_escalation_resets.1999088114 |
| Short name | T247 |
| Test name | |
| Test status | |
| Simulation time | 6036999280 ps |
| CPU time | 567.8 seconds |
| Started | Aug 12 07:43:50 PM PDT 24 |
| Finished | Aug 12 07:53:17 PM PDT 24 |
| Peak memory | 650752 kb |
| Host | smart-4d0ce05e-21b2-4d2a-8204-b8011c15fbb6 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 1999088114 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 78.chip_sw_all_escalation_resets.1999088114 |
| Directory | /workspace/78.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/79.chip_sw_all_escalation_resets.2307977528 |
| Short name | T801 |
| Test name | |
| Test status | |
| Simulation time | 5195387996 ps |
| CPU time | 620.65 seconds |
| Started | Aug 12 07:42:59 PM PDT 24 |
| Finished | Aug 12 07:53:20 PM PDT 24 |
| Peak memory | 650340 kb |
| Host | smart-fa7abb4b-4a06-4d61-870f-af861a25e751 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 2307977528 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 79.chip_sw_all_escalation_resets.2307977528 |
| Directory | /workspace/79.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/8.chip_sw_alert_handler_lpg_sleep_mode_alerts.631434779 |
| Short name | T324 |
| Test name | |
| Test status | |
| Simulation time | 3721403518 ps |
| CPU time | 414.46 seconds |
| Started | Aug 12 07:34:49 PM PDT 24 |
| Finished | Aug 12 07:41:44 PM PDT 24 |
| Peak memory | 649544 kb |
| Host | smart-6fffa1e7-a612-41de-b621-63cb0181c94b |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=631434779 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all _escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.chip_sw _alert_handler_lpg_sleep_mode_alerts.631434779 |
| Directory | /workspace/8.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/8.chip_sw_all_escalation_resets.2768277144 |
| Short name | T868 |
| Test name | |
| Test status | |
| Simulation time | 5334787562 ps |
| CPU time | 737.45 seconds |
| Started | Aug 12 07:35:23 PM PDT 24 |
| Finished | Aug 12 07:47:41 PM PDT 24 |
| Peak memory | 650528 kb |
| Host | smart-4e6d76a8-d207-44f5-a30f-e6c4d6baf42e |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 2768277144 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.chip_sw_all_escalation_resets.2768277144 |
| Directory | /workspace/8.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/8.chip_sw_csrng_edn_concurrency.162840415 |
| Short name | T745 |
| Test name | |
| Test status | |
| Simulation time | 34132483416 ps |
| CPU time | 6724.55 seconds |
| Started | Aug 12 07:33:26 PM PDT 24 |
| Finished | Aug 12 09:25:32 PM PDT 24 |
| Peak memory | 610784 kb |
| Host | smart-f91bc9cc-2456-45c1-a4e8-1c7d3915dc71 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=140_000_000 +rng_srate_value_min=15 +rng_srate_value_max=20 +sw_build_device=sim_dv +sw_images=csrng_edn_c oncurrency_test:1:new_rules,test_rom:0 +accelerate_cold_power_up_time=3 +accelerate_regulators_power_up_time=2 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=162840415 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.chip_sw_csrng_edn_concurrency.162840415 |
| Directory | /workspace/8.chip_sw_csrng_edn_concurrency/latest |
| Test location | /workspace/coverage/default/8.chip_sw_lc_ctrl_transition.2241364220 |
| Short name | T1342 |
| Test name | |
| Test status | |
| Simulation time | 7176982609 ps |
| CPU time | 558.74 seconds |
| Started | Aug 12 07:32:56 PM PDT 24 |
| Finished | Aug 12 07:42:15 PM PDT 24 |
| Peak memory | 622880 kb |
| Host | smart-0f17ca80-16d1-4d95-8df4-9966de14d9ac |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=lc_ctrl_transition_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2241364220 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_transition_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau lt.vdb -cm_log /dev/null -cm_name 8.chip_sw_lc_ctrl_transition.2241364220 |
| Directory | /workspace/8.chip_sw_lc_ctrl_transition/latest |
| Test location | /workspace/coverage/default/8.chip_sw_uart_rand_baudrate.2047912864 |
| Short name | T1233 |
| Test name | |
| Test status | |
| Simulation time | 3048426708 ps |
| CPU time | 483.84 seconds |
| Started | Aug 12 07:35:01 PM PDT 24 |
| Finished | Aug 12 07:43:06 PM PDT 24 |
| Peak memory | 623904 kb |
| Host | smart-1db41c86-e3b5-4944-98c4-30029ae535c9 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random _seed=2047912864 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.chip_sw_uart_rand_baudrate.2047912864 |
| Directory | /workspace/8.chip_sw_uart_rand_baudrate/latest |
| Test location | /workspace/coverage/default/80.chip_sw_alert_handler_lpg_sleep_mode_alerts.2080295033 |
| Short name | T855 |
| Test name | |
| Test status | |
| Simulation time | 3597623110 ps |
| CPU time | 322.57 seconds |
| Started | Aug 12 07:41:57 PM PDT 24 |
| Finished | Aug 12 07:47:20 PM PDT 24 |
| Peak memory | 649572 kb |
| Host | smart-899d35fd-74ea-4361-b571-13d389e2ce2a |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2080295033 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 80.chip_ sw_alert_handler_lpg_sleep_mode_alerts.2080295033 |
| Directory | /workspace/80.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/80.chip_sw_all_escalation_resets.832547445 |
| Short name | T1222 |
| Test name | |
| Test status | |
| Simulation time | 5795138026 ps |
| CPU time | 575.69 seconds |
| Started | Aug 12 07:43:38 PM PDT 24 |
| Finished | Aug 12 07:53:14 PM PDT 24 |
| Peak memory | 650540 kb |
| Host | smart-160c3f5b-a977-4fe7-b0a7-eca620aac0ac |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 832547445 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 80.chip_sw_all_escalation_resets.832547445 |
| Directory | /workspace/80.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/81.chip_sw_alert_handler_lpg_sleep_mode_alerts.3399784460 |
| Short name | T887 |
| Test name | |
| Test status | |
| Simulation time | 4212462376 ps |
| CPU time | 303.15 seconds |
| Started | Aug 12 07:43:54 PM PDT 24 |
| Finished | Aug 12 07:48:57 PM PDT 24 |
| Peak memory | 649360 kb |
| Host | smart-b4d0f705-a23a-4cf3-94b2-2c280cf50831 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3399784460 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 81.chip_ sw_alert_handler_lpg_sleep_mode_alerts.3399784460 |
| Directory | /workspace/81.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/82.chip_sw_alert_handler_lpg_sleep_mode_alerts.815370230 |
| Short name | T444 |
| Test name | |
| Test status | |
| Simulation time | 4218162900 ps |
| CPU time | 407.3 seconds |
| Started | Aug 12 07:40:54 PM PDT 24 |
| Finished | Aug 12 07:47:41 PM PDT 24 |
| Peak memory | 649420 kb |
| Host | smart-8abd1528-e430-471a-8981-55529f9594c2 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=815370230 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all _escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 82.chip_s w_alert_handler_lpg_sleep_mode_alerts.815370230 |
| Directory | /workspace/82.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/82.chip_sw_all_escalation_resets.3629286366 |
| Short name | T885 |
| Test name | |
| Test status | |
| Simulation time | 5819155382 ps |
| CPU time | 529.2 seconds |
| Started | Aug 12 07:44:12 PM PDT 24 |
| Finished | Aug 12 07:53:01 PM PDT 24 |
| Peak memory | 650576 kb |
| Host | smart-a7a6a829-760c-4f68-b63e-d18dca96b4c7 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 3629286366 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 82.chip_sw_all_escalation_resets.3629286366 |
| Directory | /workspace/82.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/83.chip_sw_alert_handler_lpg_sleep_mode_alerts.1885022241 |
| Short name | T856 |
| Test name | |
| Test status | |
| Simulation time | 3751859266 ps |
| CPU time | 424.55 seconds |
| Started | Aug 12 07:41:20 PM PDT 24 |
| Finished | Aug 12 07:48:25 PM PDT 24 |
| Peak memory | 649632 kb |
| Host | smart-b2feab26-b2e3-469b-bde9-6a2788b41f66 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1885022241 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 83.chip_ sw_alert_handler_lpg_sleep_mode_alerts.1885022241 |
| Directory | /workspace/83.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/83.chip_sw_all_escalation_resets.435848577 |
| Short name | T863 |
| Test name | |
| Test status | |
| Simulation time | 6071085900 ps |
| CPU time | 580.99 seconds |
| Started | Aug 12 07:40:38 PM PDT 24 |
| Finished | Aug 12 07:50:20 PM PDT 24 |
| Peak memory | 650240 kb |
| Host | smart-dba101f2-0d62-41b9-9e65-119d074ab376 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 435848577 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 83.chip_sw_all_escalation_resets.435848577 |
| Directory | /workspace/83.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/84.chip_sw_all_escalation_resets.664175777 |
| Short name | T1299 |
| Test name | |
| Test status | |
| Simulation time | 4994888700 ps |
| CPU time | 622.35 seconds |
| Started | Aug 12 07:43:19 PM PDT 24 |
| Finished | Aug 12 07:53:42 PM PDT 24 |
| Peak memory | 650156 kb |
| Host | smart-0fb5ed3d-9417-43d4-b269-3d9ea1fe9b30 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 664175777 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 84.chip_sw_all_escalation_resets.664175777 |
| Directory | /workspace/84.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/85.chip_sw_alert_handler_lpg_sleep_mode_alerts.3078001705 |
| Short name | T225 |
| Test name | |
| Test status | |
| Simulation time | 4332683606 ps |
| CPU time | 362.25 seconds |
| Started | Aug 12 07:41:20 PM PDT 24 |
| Finished | Aug 12 07:47:23 PM PDT 24 |
| Peak memory | 649356 kb |
| Host | smart-7864eb34-6511-4055-b6fe-54c72135e8af |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3078001705 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 85.chip_ sw_alert_handler_lpg_sleep_mode_alerts.3078001705 |
| Directory | /workspace/85.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/85.chip_sw_all_escalation_resets.17382969 |
| Short name | T882 |
| Test name | |
| Test status | |
| Simulation time | 5028989244 ps |
| CPU time | 785.4 seconds |
| Started | Aug 12 07:41:44 PM PDT 24 |
| Finished | Aug 12 07:54:50 PM PDT 24 |
| Peak memory | 650392 kb |
| Host | smart-8f2d4d0b-fae3-41ac-9eb6-b97be27a09ac |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 17382969 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 85.chip_sw_all_escalation_resets.17382969 |
| Directory | /workspace/85.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/86.chip_sw_alert_handler_lpg_sleep_mode_alerts.649576836 |
| Short name | T1432 |
| Test name | |
| Test status | |
| Simulation time | 3645405464 ps |
| CPU time | 360.09 seconds |
| Started | Aug 12 07:41:25 PM PDT 24 |
| Finished | Aug 12 07:47:26 PM PDT 24 |
| Peak memory | 649300 kb |
| Host | smart-69e9a1e5-272e-4562-962d-f224e2edc47a |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=649576836 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all _escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 86.chip_s w_alert_handler_lpg_sleep_mode_alerts.649576836 |
| Directory | /workspace/86.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/86.chip_sw_all_escalation_resets.3017381427 |
| Short name | T90 |
| Test name | |
| Test status | |
| Simulation time | 5559044756 ps |
| CPU time | 582.13 seconds |
| Started | Aug 12 07:41:28 PM PDT 24 |
| Finished | Aug 12 07:51:10 PM PDT 24 |
| Peak memory | 651120 kb |
| Host | smart-10b5242f-b980-4dc4-9837-a3ca2c40628e |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 3017381427 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 86.chip_sw_all_escalation_resets.3017381427 |
| Directory | /workspace/86.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/87.chip_sw_alert_handler_lpg_sleep_mode_alerts.805806031 |
| Short name | T839 |
| Test name | |
| Test status | |
| Simulation time | 3734348424 ps |
| CPU time | 309.95 seconds |
| Started | Aug 12 07:42:24 PM PDT 24 |
| Finished | Aug 12 07:47:35 PM PDT 24 |
| Peak memory | 649416 kb |
| Host | smart-6cf55154-fd6b-48d8-a347-f61502b0b3e7 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=805806031 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all _escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 87.chip_s w_alert_handler_lpg_sleep_mode_alerts.805806031 |
| Directory | /workspace/87.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/87.chip_sw_all_escalation_resets.3925774675 |
| Short name | T861 |
| Test name | |
| Test status | |
| Simulation time | 5083101406 ps |
| CPU time | 653.67 seconds |
| Started | Aug 12 07:41:29 PM PDT 24 |
| Finished | Aug 12 07:52:23 PM PDT 24 |
| Peak memory | 650332 kb |
| Host | smart-eee8058e-bc82-4da4-b40d-284b951051dc |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 3925774675 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 87.chip_sw_all_escalation_resets.3925774675 |
| Directory | /workspace/87.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/88.chip_sw_alert_handler_lpg_sleep_mode_alerts.2657336068 |
| Short name | T824 |
| Test name | |
| Test status | |
| Simulation time | 3698119400 ps |
| CPU time | 260.93 seconds |
| Started | Aug 12 07:41:11 PM PDT 24 |
| Finished | Aug 12 07:45:32 PM PDT 24 |
| Peak memory | 649308 kb |
| Host | smart-7a33fbb7-567e-4517-96b0-0a75a096d88a |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2657336068 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 88.chip_ sw_alert_handler_lpg_sleep_mode_alerts.2657336068 |
| Directory | /workspace/88.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/88.chip_sw_all_escalation_resets.2444831063 |
| Short name | T311 |
| Test name | |
| Test status | |
| Simulation time | 5511758720 ps |
| CPU time | 547.68 seconds |
| Started | Aug 12 07:40:55 PM PDT 24 |
| Finished | Aug 12 07:50:03 PM PDT 24 |
| Peak memory | 650968 kb |
| Host | smart-fcbac641-eaac-4d75-8527-aecd5c127261 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 2444831063 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 88.chip_sw_all_escalation_resets.2444831063 |
| Directory | /workspace/88.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/89.chip_sw_alert_handler_lpg_sleep_mode_alerts.978987234 |
| Short name | T273 |
| Test name | |
| Test status | |
| Simulation time | 4119462386 ps |
| CPU time | 317.94 seconds |
| Started | Aug 12 07:43:34 PM PDT 24 |
| Finished | Aug 12 07:48:52 PM PDT 24 |
| Peak memory | 649376 kb |
| Host | smart-51edf519-8a6c-4e7e-b67b-500d69d18ad7 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=978987234 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all _escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 89.chip_s w_alert_handler_lpg_sleep_mode_alerts.978987234 |
| Directory | /workspace/89.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/89.chip_sw_all_escalation_resets.558950381 |
| Short name | T297 |
| Test name | |
| Test status | |
| Simulation time | 4406149032 ps |
| CPU time | 576.86 seconds |
| Started | Aug 12 07:42:21 PM PDT 24 |
| Finished | Aug 12 07:51:58 PM PDT 24 |
| Peak memory | 650352 kb |
| Host | smart-7f08324f-f592-4300-a5fe-5fcd8574a17a |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 558950381 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 89.chip_sw_all_escalation_resets.558950381 |
| Directory | /workspace/89.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/9.chip_sw_alert_handler_lpg_sleep_mode_alerts.2381756138 |
| Short name | T431 |
| Test name | |
| Test status | |
| Simulation time | 3355071416 ps |
| CPU time | 370.5 seconds |
| Started | Aug 12 07:36:10 PM PDT 24 |
| Finished | Aug 12 07:42:21 PM PDT 24 |
| Peak memory | 649640 kb |
| Host | smart-395f3b8d-ec8f-4411-9255-52be533a9272 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2381756138 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.chip_s w_alert_handler_lpg_sleep_mode_alerts.2381756138 |
| Directory | /workspace/9.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/9.chip_sw_all_escalation_resets.4229040617 |
| Short name | T802 |
| Test name | |
| Test status | |
| Simulation time | 5288342120 ps |
| CPU time | 882.68 seconds |
| Started | Aug 12 07:33:45 PM PDT 24 |
| Finished | Aug 12 07:48:28 PM PDT 24 |
| Peak memory | 650200 kb |
| Host | smart-5ac850c4-3b74-49aa-826a-948e6fa63fd7 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 4229040617 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.chip_sw_all_escalation_resets.4229040617 |
| Directory | /workspace/9.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/9.chip_sw_csrng_edn_concurrency.1515135179 |
| Short name | T1134 |
| Test name | |
| Test status | |
| Simulation time | 15162767944 ps |
| CPU time | 2947.41 seconds |
| Started | Aug 12 07:34:09 PM PDT 24 |
| Finished | Aug 12 08:23:17 PM PDT 24 |
| Peak memory | 610812 kb |
| Host | smart-fe20bbc2-950f-40f2-a96e-1612aa84771b |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=140_000_000 +rng_srate_value_min=15 +rng_srate_value_max=20 +sw_build_device=sim_dv +sw_images=csrng_edn_c oncurrency_test:1:new_rules,test_rom:0 +accelerate_cold_power_up_time=3 +accelerate_regulators_power_up_time=2 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1515135179 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd b -cm_log /dev/null -cm_name 9.chip_sw_csrng_edn_concurrency.1515135179 |
| Directory | /workspace/9.chip_sw_csrng_edn_concurrency/latest |
| Test location | /workspace/coverage/default/9.chip_sw_lc_ctrl_transition.473117019 |
| Short name | T1086 |
| Test name | |
| Test status | |
| Simulation time | 8951454637 ps |
| CPU time | 695.08 seconds |
| Started | Aug 12 07:36:34 PM PDT 24 |
| Finished | Aug 12 07:48:09 PM PDT 24 |
| Peak memory | 622868 kb |
| Host | smart-ea8ce843-c5fb-4dd1-b448-f3b20e8f9d1b |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=lc_ctrl_transition_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=473117019 -assert nopostproc +UVM_TEST NAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_transition_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul t.vdb -cm_log /dev/null -cm_name 9.chip_sw_lc_ctrl_transition.473117019 |
| Directory | /workspace/9.chip_sw_lc_ctrl_transition/latest |
| Test location | /workspace/coverage/default/9.chip_sw_uart_rand_baudrate.2866487791 |
| Short name | T1223 |
| Test name | |
| Test status | |
| Simulation time | 13218703240 ps |
| CPU time | 2121.33 seconds |
| Started | Aug 12 07:32:57 PM PDT 24 |
| Finished | Aug 12 08:08:19 PM PDT 24 |
| Peak memory | 624996 kb |
| Host | smart-1f665f4b-b8a7-4ccf-a215-637d32df1863 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random _seed=2866487791 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.chip_sw_uart_rand_baudrate.2866487791 |
| Directory | /workspace/9.chip_sw_uart_rand_baudrate/latest |
| Test location | /workspace/coverage/default/90.chip_sw_all_escalation_resets.3137992217 |
| Short name | T860 |
| Test name | |
| Test status | |
| Simulation time | 5624644664 ps |
| CPU time | 643.82 seconds |
| Started | Aug 12 07:40:57 PM PDT 24 |
| Finished | Aug 12 07:51:41 PM PDT 24 |
| Peak memory | 650320 kb |
| Host | smart-bb67a7fe-6a59-4bc8-8bfb-c07a0ebfc12d |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 3137992217 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 90.chip_sw_all_escalation_resets.3137992217 |
| Directory | /workspace/90.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/91.chip_sw_all_escalation_resets.1506525926 |
| Short name | T102 |
| Test name | |
| Test status | |
| Simulation time | 4538962232 ps |
| CPU time | 586.27 seconds |
| Started | Aug 12 07:43:27 PM PDT 24 |
| Finished | Aug 12 07:53:13 PM PDT 24 |
| Peak memory | 650344 kb |
| Host | smart-b17b33a9-0ce9-4948-9368-78c6a29d6954 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 1506525926 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 91.chip_sw_all_escalation_resets.1506525926 |
| Directory | /workspace/91.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/92.chip_sw_all_escalation_resets.435109366 |
| Short name | T814 |
| Test name | |
| Test status | |
| Simulation time | 5348868264 ps |
| CPU time | 621.33 seconds |
| Started | Aug 12 07:41:42 PM PDT 24 |
| Finished | Aug 12 07:52:03 PM PDT 24 |
| Peak memory | 650520 kb |
| Host | smart-f4f4af66-38d7-48fb-b681-cda779ac7250 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 435109366 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 92.chip_sw_all_escalation_resets.435109366 |
| Directory | /workspace/92.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/93.chip_sw_all_escalation_resets.4003833228 |
| Short name | T95 |
| Test name | |
| Test status | |
| Simulation time | 5526257196 ps |
| CPU time | 546.02 seconds |
| Started | Aug 12 07:41:19 PM PDT 24 |
| Finished | Aug 12 07:50:25 PM PDT 24 |
| Peak memory | 651248 kb |
| Host | smart-9a3b3bde-6e73-41b1-9e3d-f8c742918c34 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 4003833228 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 93.chip_sw_all_escalation_resets.4003833228 |
| Directory | /workspace/93.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/95.chip_sw_all_escalation_resets.2319281353 |
| Short name | T1026 |
| Test name | |
| Test status | |
| Simulation time | 4880743396 ps |
| CPU time | 447.48 seconds |
| Started | Aug 12 07:42:05 PM PDT 24 |
| Finished | Aug 12 07:49:32 PM PDT 24 |
| Peak memory | 620328 kb |
| Host | smart-deae07f0-b48d-494c-9e67-50f65b962fd9 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 2319281353 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 95.chip_sw_all_escalation_resets.2319281353 |
| Directory | /workspace/95.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/96.chip_sw_all_escalation_resets.1890108360 |
| Short name | T179 |
| Test name | |
| Test status | |
| Simulation time | 6467654460 ps |
| CPU time | 695.44 seconds |
| Started | Aug 12 07:41:05 PM PDT 24 |
| Finished | Aug 12 07:52:41 PM PDT 24 |
| Peak memory | 620124 kb |
| Host | smart-a05e95cc-bfc1-4afc-9c3f-cff05279967b |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 1890108360 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 96.chip_sw_all_escalation_resets.1890108360 |
| Directory | /workspace/96.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/98.chip_sw_all_escalation_resets.1253977176 |
| Short name | T838 |
| Test name | |
| Test status | |
| Simulation time | 5509755330 ps |
| CPU time | 469.31 seconds |
| Started | Aug 12 07:42:09 PM PDT 24 |
| Finished | Aug 12 07:49:58 PM PDT 24 |
| Peak memory | 650196 kb |
| Host | smart-34428090-95e9-453f-b1f4-4b095824c933 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 1253977176 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 98.chip_sw_all_escalation_resets.1253977176 |
| Directory | /workspace/98.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/99.chip_sw_all_escalation_resets.2616100611 |
| Short name | T250 |
| Test name | |
| Test status | |
| Simulation time | 5151825008 ps |
| CPU time | 531.6 seconds |
| Started | Aug 12 07:41:40 PM PDT 24 |
| Finished | Aug 12 07:50:32 PM PDT 24 |
| Peak memory | 650448 kb |
| Host | smart-0bac3924-f0fb-44ee-8a5f-9d37eed6cbcc |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 2616100611 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 99.chip_sw_all_escalation_resets.2616100611 |
| Directory | /workspace/99.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/pad_ctrl_test_mode/1.chip_padctrl_attributes.1013253395 |
| Short name | T202 |
| Test name | |
| Test status | |
| Simulation time | 4909373269 ps |
| CPU time | 249.44 seconds |
| Started | Aug 12 07:34:59 PM PDT 24 |
| Finished | Aug 12 07:39:09 PM PDT 24 |
| Peak memory | 655536 kb |
| Host | smart-535beaad-688b-4c21-a80b-137a0639085f |
| User | root |
| Command | /workspace/pad_ctrl_test_mode/simv +use_otp_image=OtpTypeLcStProd +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1013253395 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TE ST_SEQ=chip_padctrl_attributes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/pad_ctrl_test_mode.vdb -cm_log /dev/ null -cm_name 1.chip_padctrl_attributes.1013253395 |
| Directory | /workspace/1.chip_padctrl_attributes/latest |
| Test location | /workspace/coverage/pad_ctrl_test_mode/2.chip_padctrl_attributes.4134806719 |
| Short name | T204 |
| Test name | |
| Test status | |
| Simulation time | 5051701810 ps |
| CPU time | 322.4 seconds |
| Started | Aug 12 07:35:14 PM PDT 24 |
| Finished | Aug 12 07:40:37 PM PDT 24 |
| Peak memory | 656448 kb |
| Host | smart-d024a808-0a66-4ccf-96d0-54676e337bb6 |
| User | root |
| Command | /workspace/pad_ctrl_test_mode/simv +use_otp_image=OtpTypeLcStProd +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4134806719 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TE ST_SEQ=chip_padctrl_attributes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/pad_ctrl_test_mode.vdb -cm_log /dev/ null -cm_name 2.chip_padctrl_attributes.4134806719 |
| Directory | /workspace/2.chip_padctrl_attributes/latest |
| Test location | /workspace/coverage/pad_ctrl_test_mode/3.chip_padctrl_attributes.2746960665 |
| Short name | T200 |
| Test name | |
| Test status | |
| Simulation time | 5487576795 ps |
| CPU time | 339.73 seconds |
| Started | Aug 12 07:35:22 PM PDT 24 |
| Finished | Aug 12 07:41:02 PM PDT 24 |
| Peak memory | 653420 kb |
| Host | smart-e2b8f0e8-c417-4d81-8566-ba249d1db4a8 |
| User | root |
| Command | /workspace/pad_ctrl_test_mode/simv +use_otp_image=OtpTypeLcStProd +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2746960665 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TE ST_SEQ=chip_padctrl_attributes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/pad_ctrl_test_mode.vdb -cm_log /dev/ null -cm_name 3.chip_padctrl_attributes.2746960665 |
| Directory | /workspace/3.chip_padctrl_attributes/latest |
| Test location | /workspace/coverage/pad_ctrl_test_mode/4.chip_padctrl_attributes.2828813347 |
| Short name | T32 |
| Test name | |
| Test status | |
| Simulation time | 5058078686 ps |
| CPU time | 259.4 seconds |
| Started | Aug 12 07:35:14 PM PDT 24 |
| Finished | Aug 12 07:39:33 PM PDT 24 |
| Peak memory | 657648 kb |
| Host | smart-ee9b2853-bd3a-46c2-b941-b55b4b29b41c |
| User | root |
| Command | /workspace/pad_ctrl_test_mode/simv +use_otp_image=OtpTypeLcStProd +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2828813347 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TE ST_SEQ=chip_padctrl_attributes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/pad_ctrl_test_mode.vdb -cm_log /dev/ null -cm_name 4.chip_padctrl_attributes.2828813347 |
| Directory | /workspace/4.chip_padctrl_attributes/latest |
| Test location | /workspace/coverage/pad_ctrl_test_mode/5.chip_padctrl_attributes.1817662295 |
| Short name | T199 |
| Test name | |
| Test status | |
| Simulation time | 4887336288 ps |
| CPU time | 260.86 seconds |
| Started | Aug 12 07:35:23 PM PDT 24 |
| Finished | Aug 12 07:39:44 PM PDT 24 |
| Peak memory | 649476 kb |
| Host | smart-497f45a0-53ba-4c4a-976d-d18dba12ee04 |
| User | root |
| Command | /workspace/pad_ctrl_test_mode/simv +use_otp_image=OtpTypeLcStProd +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1817662295 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TE ST_SEQ=chip_padctrl_attributes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/pad_ctrl_test_mode.vdb -cm_log /dev/ null -cm_name 5.chip_padctrl_attributes.1817662295 |
| Directory | /workspace/5.chip_padctrl_attributes/latest |
| Test location | /workspace/coverage/pad_ctrl_test_mode/6.chip_padctrl_attributes.4212134968 |
| Short name | T34 |
| Test name | |
| Test status | |
| Simulation time | 5282492644 ps |
| CPU time | 310.61 seconds |
| Started | Aug 12 07:35:26 PM PDT 24 |
| Finished | Aug 12 07:40:37 PM PDT 24 |
| Peak memory | 656548 kb |
| Host | smart-a58ac6cc-de4b-4984-9a75-13919de7cf4d |
| User | root |
| Command | /workspace/pad_ctrl_test_mode/simv +use_otp_image=OtpTypeLcStProd +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4212134968 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TE ST_SEQ=chip_padctrl_attributes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/pad_ctrl_test_mode.vdb -cm_log /dev/ null -cm_name 6.chip_padctrl_attributes.4212134968 |
| Directory | /workspace/6.chip_padctrl_attributes/latest |
| Test location | /workspace/coverage/pad_ctrl_test_mode/7.chip_padctrl_attributes.68185628 |
| Short name | T33 |
| Test name | |
| Test status | |
| Simulation time | 3903315240 ps |
| CPU time | 251.91 seconds |
| Started | Aug 12 07:35:17 PM PDT 24 |
| Finished | Aug 12 07:39:29 PM PDT 24 |
| Peak memory | 641288 kb |
| Host | smart-2245bed7-920a-4381-b9c6-bfc27592a2c9 |
| User | root |
| Command | /workspace/pad_ctrl_test_mode/simv +use_otp_image=OtpTypeLcStProd +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=68185628 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST _SEQ=chip_padctrl_attributes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/pad_ctrl_test_mode.vdb -cm_log /dev/nu ll -cm_name 7.chip_padctrl_attributes.68185628 |
| Directory | /workspace/7.chip_padctrl_attributes/latest |
| Test location | /workspace/coverage/pad_ctrl_test_mode/9.chip_padctrl_attributes.3468217769 |
| Short name | T201 |
| Test name | |
| Test status | |
| Simulation time | 3859695675 ps |
| CPU time | 234.44 seconds |
| Started | Aug 12 07:35:15 PM PDT 24 |
| Finished | Aug 12 07:39:10 PM PDT 24 |
| Peak memory | 642656 kb |
| Host | smart-c3061a3f-31fb-4208-9424-ca47dec09774 |
| User | root |
| Command | /workspace/pad_ctrl_test_mode/simv +use_otp_image=OtpTypeLcStProd +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3468217769 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TE ST_SEQ=chip_padctrl_attributes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/pad_ctrl_test_mode.vdb -cm_log /dev/ null -cm_name 9.chip_padctrl_attributes.3468217769 |
| Directory | /workspace/9.chip_padctrl_attributes/latest |
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