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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
96.03 95.47 93.71 95.35 94.54 97.53 99.57


Total test records in report: 2943
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T1108 /workspace/coverage/default/1.chip_sw_clkmgr_off_kmac_trans.1167884004 Aug 12 07:19:21 PM PDT 24 Aug 12 07:30:51 PM PDT 24 5240759634 ps
T1109 /workspace/coverage/default/10.chip_sw_uart_rand_baudrate.630797166 Aug 12 07:33:48 PM PDT 24 Aug 12 08:15:12 PM PDT 24 13259040362 ps
T1110 /workspace/coverage/default/1.chip_sw_uart_tx_rx.1512035725 Aug 12 07:10:28 PM PDT 24 Aug 12 07:20:39 PM PDT 24 3910587880 ps
T856 /workspace/coverage/default/83.chip_sw_alert_handler_lpg_sleep_mode_alerts.1885022241 Aug 12 07:41:20 PM PDT 24 Aug 12 07:48:25 PM PDT 24 3751859266 ps
T1111 /workspace/coverage/default/2.chip_sw_otp_ctrl_lc_signals_dev.1473476485 Aug 12 07:26:26 PM PDT 24 Aug 12 07:48:59 PM PDT 24 10037853016 ps
T1112 /workspace/coverage/default/0.chip_sw_hmac_enc_idle.2320369806 Aug 12 07:08:49 PM PDT 24 Aug 12 07:13:30 PM PDT 24 2654972568 ps
T1113 /workspace/coverage/default/2.chip_sw_flash_ctrl_idle_low_power.3912657523 Aug 12 07:24:38 PM PDT 24 Aug 12 07:30:51 PM PDT 24 3725341136 ps
T817 /workspace/coverage/default/18.chip_sw_alert_handler_lpg_sleep_mode_alerts.1412368083 Aug 12 07:34:52 PM PDT 24 Aug 12 07:42:50 PM PDT 24 3840659314 ps
T82 /workspace/coverage/default/2.chip_jtag_csr_rw.2344203753 Aug 12 07:21:06 PM PDT 24 Aug 12 07:46:09 PM PDT 24 10641127888 ps
T872 /workspace/coverage/default/23.chip_sw_alert_handler_lpg_sleep_mode_alerts.3504371874 Aug 12 07:35:51 PM PDT 24 Aug 12 07:42:01 PM PDT 24 3717871430 ps
T1114 /workspace/coverage/default/2.chip_sw_otbn_smoketest.351911009 Aug 12 07:33:07 PM PDT 24 Aug 12 07:55:06 PM PDT 24 8077665334 ps
T1115 /workspace/coverage/default/1.chip_sw_pwrmgr_sysrst_ctrl_reset.3802739301 Aug 12 07:12:13 PM PDT 24 Aug 12 07:39:45 PM PDT 24 6897293175 ps
T29 /workspace/coverage/default/0.chip_sw_gpio.1539317068 Aug 12 07:08:08 PM PDT 24 Aug 12 07:15:53 PM PDT 24 4456735704 ps
T293 /workspace/coverage/default/0.chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq.3752944996 Aug 12 07:10:41 PM PDT 24 Aug 12 07:20:00 PM PDT 24 4848717284 ps
T1116 /workspace/coverage/default/29.chip_sw_alert_handler_lpg_sleep_mode_alerts.811831372 Aug 12 07:36:00 PM PDT 24 Aug 12 07:43:20 PM PDT 24 4287350150 ps
T1117 /workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_bad_dev.2721788600 Aug 12 07:14:43 PM PDT 24 Aug 12 08:57:50 PM PDT 24 23544462968 ps
T1118 /workspace/coverage/default/1.chip_sw_otbn_smoketest.1145763333 Aug 12 07:21:43 PM PDT 24 Aug 12 07:57:55 PM PDT 24 9768018232 ps
T863 /workspace/coverage/default/83.chip_sw_all_escalation_resets.435848577 Aug 12 07:40:38 PM PDT 24 Aug 12 07:50:20 PM PDT 24 6071085900 ps
T373 /workspace/coverage/default/0.chip_sw_adc_ctrl_sleep_debug_cable_wakeup.234286053 Aug 12 07:12:04 PM PDT 24 Aug 12 07:22:28 PM PDT 24 19339638072 ps
T1119 /workspace/coverage/default/2.chip_sw_clkmgr_off_peri.3206897048 Aug 12 07:32:31 PM PDT 24 Aug 12 07:50:57 PM PDT 24 9705920748 ps
T1120 /workspace/coverage/default/0.chip_sw_rv_timer_irq.940421844 Aug 12 07:07:23 PM PDT 24 Aug 12 07:10:55 PM PDT 24 2976969208 ps
T1121 /workspace/coverage/default/2.chip_sw_rv_timer_smoketest.3172567169 Aug 12 07:30:28 PM PDT 24 Aug 12 07:34:45 PM PDT 24 2806679600 ps
T1122 /workspace/coverage/default/2.chip_sw_uart_tx_rx_idx3.765479809 Aug 12 07:22:53 PM PDT 24 Aug 12 07:34:01 PM PDT 24 4821768010 ps
T1123 /workspace/coverage/default/0.chip_sw_hmac_multistream.1654427937 Aug 12 07:09:58 PM PDT 24 Aug 12 07:45:11 PM PDT 24 7945239104 ps
T1124 /workspace/coverage/default/0.chip_sw_clkmgr_off_peri.2983700591 Aug 12 07:09:25 PM PDT 24 Aug 12 07:36:43 PM PDT 24 10258936088 ps
T1125 /workspace/coverage/default/0.chip_sw_uart_rand_baudrate.1197231634 Aug 12 07:07:33 PM PDT 24 Aug 12 07:15:41 PM PDT 24 4585219640 ps
T69 /workspace/coverage/default/0.chip_tap_straps_testunlock0.298918504 Aug 12 07:08:57 PM PDT 24 Aug 12 07:12:47 PM PDT 24 4348384476 ps
T335 /workspace/coverage/default/2.chip_sw_i2c_host_tx_rx.503302938 Aug 12 07:26:30 PM PDT 24 Aug 12 07:37:22 PM PDT 24 4224910158 ps
T1126 /workspace/coverage/default/2.chip_sw_otp_ctrl_smoketest.3860749201 Aug 12 07:33:00 PM PDT 24 Aug 12 07:37:11 PM PDT 24 2287876392 ps
T1127 /workspace/coverage/default/2.chip_sw_alert_handler_escalation.1109806612 Aug 12 07:27:09 PM PDT 24 Aug 12 07:36:13 PM PDT 24 5091247330 ps
T172 /workspace/coverage/default/0.chip_sw_otp_ctrl_vendor_test_csr_access.1558890160 Aug 12 07:07:46 PM PDT 24 Aug 12 07:12:26 PM PDT 24 3156364704 ps
T1128 /workspace/coverage/default/1.chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq.426065184 Aug 12 07:21:23 PM PDT 24 Aug 12 08:24:50 PM PDT 24 24799304421 ps
T1129 /workspace/coverage/default/1.chip_sw_rstmgr_smoketest.1621304745 Aug 12 07:23:00 PM PDT 24 Aug 12 07:26:27 PM PDT 24 2628181750 ps
T1130 /workspace/coverage/default/0.chip_sw_pwrmgr_usb_clk_disabled_when_active.2451043318 Aug 12 07:09:22 PM PDT 24 Aug 12 07:19:20 PM PDT 24 5802374972 ps
T1131 /workspace/coverage/default/13.chip_sw_lc_ctrl_transition.68896579 Aug 12 07:35:13 PM PDT 24 Aug 12 07:43:09 PM PDT 24 7232155980 ps
T1132 /workspace/coverage/default/2.chip_sw_pwrmgr_random_sleep_all_reset_reqs.96450551 Aug 12 07:26:56 PM PDT 24 Aug 12 08:00:46 PM PDT 24 23598993741 ps
T103 /workspace/coverage/default/2.chip_sw_sleep_pin_wake.94415958 Aug 12 07:23:13 PM PDT 24 Aug 12 07:28:36 PM PDT 24 3438000920 ps
T43 /workspace/coverage/default/2.chip_sw_spi_device_tpm.3190843974 Aug 12 07:24:09 PM PDT 24 Aug 12 07:30:50 PM PDT 24 3280579066 ps
T434 /workspace/coverage/default/1.chip_sw_edn_boot_mode.2461927651 Aug 12 07:16:54 PM PDT 24 Aug 12 07:27:49 PM PDT 24 2765678586 ps
T435 /workspace/coverage/default/1.chip_sw_entropy_src_ast_rng_req.260451242 Aug 12 07:15:54 PM PDT 24 Aug 12 07:20:22 PM PDT 24 3041094130 ps
T436 /workspace/coverage/default/4.chip_sw_lc_ctrl_transition.4223299371 Aug 12 07:31:12 PM PDT 24 Aug 12 07:45:21 PM PDT 24 8619144364 ps
T437 /workspace/coverage/default/1.chip_sw_rv_dm_access_after_wakeup.2471459406 Aug 12 07:19:23 PM PDT 24 Aug 12 07:26:30 PM PDT 24 5521637700 ps
T166 /workspace/coverage/default/1.rom_raw_unlock.1794385683 Aug 12 07:22:26 PM PDT 24 Aug 12 07:26:42 PM PDT 24 5090731932 ps
T438 /workspace/coverage/default/2.chip_sw_rv_dm_access_after_wakeup.1427738124 Aug 12 07:29:23 PM PDT 24 Aug 12 07:36:40 PM PDT 24 5727293572 ps
T77 /workspace/coverage/default/0.chip_sw_usbdev_aon_pullup.3287732479 Aug 12 07:07:29 PM PDT 24 Aug 12 07:16:30 PM PDT 24 4017651996 ps
T439 /workspace/coverage/default/1.rom_e2e_keymgr_init_rom_ext_invalid_meas.170210548 Aug 12 07:25:59 PM PDT 24 Aug 12 08:19:07 PM PDT 24 15120866740 ps
T236 /workspace/coverage/default/0.chip_sw_lc_walkthrough_dev.691697036 Aug 12 07:09:45 PM PDT 24 Aug 12 08:43:42 PM PDT 24 47251115000 ps
T1133 /workspace/coverage/default/2.chip_sw_sleep_sram_ret_contents_scramble.2747639470 Aug 12 07:30:21 PM PDT 24 Aug 12 07:41:18 PM PDT 24 8620690254 ps
T1134 /workspace/coverage/default/9.chip_sw_csrng_edn_concurrency.1515135179 Aug 12 07:34:09 PM PDT 24 Aug 12 08:23:17 PM PDT 24 15162767944 ps
T1135 /workspace/coverage/default/2.chip_sw_flash_ctrl_access.1646248946 Aug 12 07:25:05 PM PDT 24 Aug 12 07:41:48 PM PDT 24 5477003224 ps
T1136 /workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_fast_dev.1239300172 Aug 12 07:11:59 PM PDT 24 Aug 12 07:22:28 PM PDT 24 3891569390 ps
T1137 /workspace/coverage/default/1.chip_sw_entropy_src_smoketest.421419099 Aug 12 07:21:41 PM PDT 24 Aug 12 07:30:59 PM PDT 24 4061324620 ps
T62 /workspace/coverage/default/1.chip_sw_spi_device_pinmux_sleep_retention.545839058 Aug 12 07:11:10 PM PDT 24 Aug 12 07:15:52 PM PDT 24 3404905536 ps
T167 /workspace/coverage/default/0.chip_plic_all_irqs_10.3462509024 Aug 12 07:09:07 PM PDT 24 Aug 12 07:19:29 PM PDT 24 4726833592 ps
T1138 /workspace/coverage/default/3.chip_sw_uart_tx_rx_idx1.930054790 Aug 12 07:37:17 PM PDT 24 Aug 12 07:48:28 PM PDT 24 4081852358 ps
T1139 /workspace/coverage/default/1.chip_sw_clkmgr_off_peri.228545718 Aug 12 07:18:15 PM PDT 24 Aug 12 07:44:23 PM PDT 24 9131232560 ps
T1140 /workspace/coverage/default/1.chip_sw_flash_crash_alert.3754233648 Aug 12 07:19:59 PM PDT 24 Aug 12 07:33:36 PM PDT 24 4905456200 ps
T104 /workspace/coverage/default/1.chip_sw_sleep_pin_wake.3832316538 Aug 12 07:11:08 PM PDT 24 Aug 12 07:14:37 PM PDT 24 3468751640 ps
T1141 /workspace/coverage/default/0.chip_sw_flash_ctrl_access_jitter_en.1454696073 Aug 12 07:07:41 PM PDT 24 Aug 12 07:26:38 PM PDT 24 6140877084 ps
T412 /workspace/coverage/default/7.chip_sw_all_escalation_resets.2689390212 Aug 12 07:32:38 PM PDT 24 Aug 12 07:43:22 PM PDT 24 5829951892 ps
T1142 /workspace/coverage/default/1.chip_sw_aon_timer_irq.2536294721 Aug 12 07:13:14 PM PDT 24 Aug 12 07:18:26 PM PDT 24 3055770730 ps
T1143 /workspace/coverage/default/1.chip_sw_aes_masking_off.1904912036 Aug 12 07:15:35 PM PDT 24 Aug 12 07:21:14 PM PDT 24 2896278547 ps
T1144 /workspace/coverage/default/12.chip_sw_all_escalation_resets.1873385429 Aug 12 07:34:19 PM PDT 24 Aug 12 07:45:13 PM PDT 24 6035114500 ps
T1145 /workspace/coverage/default/2.chip_sw_keymgr_key_derivation.1685656403 Aug 12 07:27:42 PM PDT 24 Aug 12 07:51:58 PM PDT 24 8594793816 ps
T889 /workspace/coverage/default/37.chip_sw_all_escalation_resets.3991587903 Aug 12 07:36:27 PM PDT 24 Aug 12 07:47:07 PM PDT 24 5098624340 ps
T332 /workspace/coverage/default/2.chip_plic_all_irqs_0.2659487159 Aug 12 07:27:34 PM PDT 24 Aug 12 07:51:00 PM PDT 24 6025805950 ps
T25 /workspace/coverage/default/0.chip_sw_usbdev_pincfg.2740337546 Aug 12 07:07:49 PM PDT 24 Aug 12 09:08:10 PM PDT 24 31752535590 ps
T1146 /workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0.3206839348 Aug 12 07:10:03 PM PDT 24 Aug 12 07:20:02 PM PDT 24 3820382360 ps
T147 /workspace/coverage/default/3.chip_sw_sensor_ctrl_alert.2020802900 Aug 12 07:31:53 PM PDT 24 Aug 12 07:48:30 PM PDT 24 7217301330 ps
T1147 /workspace/coverage/default/21.chip_sw_alert_handler_lpg_sleep_mode_alerts.2229556862 Aug 12 07:35:04 PM PDT 24 Aug 12 07:41:33 PM PDT 24 3387562208 ps
T1148 /workspace/coverage/default/2.chip_sw_uart_tx_rx.368777705 Aug 12 07:24:36 PM PDT 24 Aug 12 07:36:31 PM PDT 24 3926574520 ps
T1149 /workspace/coverage/default/2.chip_tap_straps_prod.1672599320 Aug 12 07:28:46 PM PDT 24 Aug 12 07:42:50 PM PDT 24 8332506154 ps
T1150 /workspace/coverage/default/2.chip_sw_lc_ctrl_otp_hw_cfg0.3127362545 Aug 12 07:23:43 PM PDT 24 Aug 12 07:29:56 PM PDT 24 3150608032 ps
T253 /workspace/coverage/default/0.chip_sw_power_sleep_load.2627763225 Aug 12 07:13:32 PM PDT 24 Aug 12 07:20:23 PM PDT 24 4622572440 ps
T180 /workspace/coverage/default/1.chip_sw_lc_ctrl_program_error.1321739935 Aug 12 07:23:32 PM PDT 24 Aug 12 07:33:52 PM PDT 24 4333465032 ps
T413 /workspace/coverage/default/24.chip_sw_all_escalation_resets.2633403767 Aug 12 07:36:11 PM PDT 24 Aug 12 07:47:20 PM PDT 24 5097202220 ps
T1151 /workspace/coverage/default/2.chip_sw_pwrmgr_deep_sleep_power_glitch_reset.2314764801 Aug 12 07:25:14 PM PDT 24 Aug 12 07:32:29 PM PDT 24 6416130286 ps
T1152 /workspace/coverage/default/1.chip_sw_otp_ctrl_ecc_error_vendor_test.2800194275 Aug 12 07:14:13 PM PDT 24 Aug 12 07:18:45 PM PDT 24 2514499732 ps
T1153 /workspace/coverage/default/0.rom_e2e_self_hash.2332419586 Aug 12 07:18:45 PM PDT 24 Aug 12 08:55:53 PM PDT 24 25478980752 ps
T1154 /workspace/coverage/default/0.chip_sw_example_manufacturer.3283601336 Aug 12 07:09:56 PM PDT 24 Aug 12 07:13:58 PM PDT 24 2807767260 ps
T769 /workspace/coverage/default/1.chip_sw_plic_sw_irq.3025711272 Aug 12 07:17:30 PM PDT 24 Aug 12 07:21:32 PM PDT 24 3229794984 ps
T1155 /workspace/coverage/default/0.chip_sw_keymgr_key_derivation.3874641605 Aug 12 07:09:41 PM PDT 24 Aug 12 07:41:26 PM PDT 24 9798033024 ps
T1156 /workspace/coverage/default/0.chip_sw_pwrmgr_deep_sleep_power_glitch_reset.3624023200 Aug 12 07:09:43 PM PDT 24 Aug 12 07:16:08 PM PDT 24 6890736250 ps
T1157 /workspace/coverage/default/0.chip_sw_entropy_src_ast_rng_req.1578453309 Aug 12 07:10:15 PM PDT 24 Aug 12 07:13:01 PM PDT 24 2521382248 ps
T864 /workspace/coverage/default/20.chip_sw_all_escalation_resets.4177882647 Aug 12 07:35:09 PM PDT 24 Aug 12 07:46:39 PM PDT 24 5879052856 ps
T1158 /workspace/coverage/default/2.chip_sw_rstmgr_sw_rst.3957566683 Aug 12 07:24:38 PM PDT 24 Aug 12 07:27:44 PM PDT 24 2927785224 ps
T338 /workspace/coverage/default/0.chip_sw_rstmgr_alert_info.113056957 Aug 12 07:09:06 PM PDT 24 Aug 12 07:45:37 PM PDT 24 12918998358 ps
T1159 /workspace/coverage/default/1.chip_sw_ast_clk_outputs.2637393388 Aug 12 07:20:03 PM PDT 24 Aug 12 07:37:43 PM PDT 24 7374527440 ps
T1160 /workspace/coverage/default/2.chip_sw_csrng_edn_concurrency.3635553404 Aug 12 07:26:48 PM PDT 24 Aug 12 09:11:31 PM PDT 24 28143041816 ps
T323 /workspace/coverage/default/32.chip_sw_alert_handler_lpg_sleep_mode_alerts.4183460945 Aug 12 07:37:45 PM PDT 24 Aug 12 07:44:26 PM PDT 24 4209100288 ps
T1161 /workspace/coverage/default/2.chip_sw_csrng_kat_test.1126601228 Aug 12 07:30:54 PM PDT 24 Aug 12 07:35:36 PM PDT 24 3272732488 ps
T1162 /workspace/coverage/default/11.chip_sw_lc_ctrl_transition.2081969786 Aug 12 07:34:32 PM PDT 24 Aug 12 07:50:28 PM PDT 24 11814563537 ps
T1163 /workspace/coverage/default/1.chip_sw_hmac_enc_jitter_en.1224537145 Aug 12 07:18:51 PM PDT 24 Aug 12 07:24:05 PM PDT 24 2833244237 ps
T824 /workspace/coverage/default/88.chip_sw_alert_handler_lpg_sleep_mode_alerts.2657336068 Aug 12 07:41:11 PM PDT 24 Aug 12 07:45:32 PM PDT 24 3698119400 ps
T1164 /workspace/coverage/default/0.chip_sw_flash_ctrl_access.3781987272 Aug 12 07:06:34 PM PDT 24 Aug 12 07:25:04 PM PDT 24 4961981208 ps
T1165 /workspace/coverage/default/1.chip_sw_kmac_mode_kmac.3116635317 Aug 12 07:17:49 PM PDT 24 Aug 12 07:23:08 PM PDT 24 2501597180 ps
T848 /workspace/coverage/default/14.chip_sw_alert_handler_lpg_sleep_mode_alerts.3864259607 Aug 12 07:35:26 PM PDT 24 Aug 12 07:42:52 PM PDT 24 4040822640 ps
T1166 /workspace/coverage/default/0.chip_sw_otbn_randomness.2862222033 Aug 12 07:08:11 PM PDT 24 Aug 12 07:25:28 PM PDT 24 5975826040 ps
T1167 /workspace/coverage/default/3.chip_sw_uart_tx_rx_alt_clk_freq_low_speed.965624618 Aug 12 07:33:32 PM PDT 24 Aug 12 08:07:43 PM PDT 24 14273200244 ps
T893 /workspace/coverage/default/94.chip_sw_all_escalation_resets.2606893093 Aug 12 07:43:11 PM PDT 24 Aug 12 07:52:36 PM PDT 24 5165048004 ps
T1168 /workspace/coverage/default/2.chip_sw_aes_enc_jitter_en.736205875 Aug 12 07:26:59 PM PDT 24 Aug 12 07:31:52 PM PDT 24 3202667743 ps
T247 /workspace/coverage/default/78.chip_sw_all_escalation_resets.1999088114 Aug 12 07:43:50 PM PDT 24 Aug 12 07:53:17 PM PDT 24 6036999280 ps
T400 /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_bad_b_good_prod.222270833 Aug 12 07:16:01 PM PDT 24 Aug 12 09:12:54 PM PDT 24 24210150940 ps
T105 /workspace/coverage/default/2.chip_sw_pwrmgr_random_sleep_all_wake_ups.3624116927 Aug 12 07:28:20 PM PDT 24 Aug 12 07:48:01 PM PDT 24 23252439916 ps
T1169 /workspace/coverage/default/2.chip_sw_kmac_idle.1016103869 Aug 12 07:28:02 PM PDT 24 Aug 12 07:33:13 PM PDT 24 2656196518 ps
T1170 /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_good_prod.4100247848 Aug 12 07:13:59 PM PDT 24 Aug 12 08:21:35 PM PDT 24 16090124650 ps
T1171 /workspace/coverage/default/0.chip_sw_uart_tx_rx_idx2.1195383115 Aug 12 07:11:24 PM PDT 24 Aug 12 07:22:28 PM PDT 24 4312629028 ps
T1172 /workspace/coverage/default/1.chip_sw_uart_rand_baudrate.4032261570 Aug 12 07:14:40 PM PDT 24 Aug 12 07:25:36 PM PDT 24 4688258000 ps
T1173 /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_bad_b_good_dev.4148341712 Aug 12 07:18:14 PM PDT 24 Aug 12 08:50:36 PM PDT 24 24581666590 ps
T1174 /workspace/coverage/default/0.chip_sw_otbn_ecdsa_op_irq_jitter_en.3759241691 Aug 12 07:10:37 PM PDT 24 Aug 12 08:14:12 PM PDT 24 19177043297 ps
T375 /workspace/coverage/default/0.chip_sw_flash_ctrl_ops_jitter_en_reduced_freq.3502339360 Aug 12 07:10:31 PM PDT 24 Aug 12 07:21:30 PM PDT 24 4696486073 ps
T1175 /workspace/coverage/default/1.chip_sw_example_concurrency.575923964 Aug 12 07:11:08 PM PDT 24 Aug 12 07:14:11 PM PDT 24 2494355840 ps
T114 /workspace/coverage/default/0.chip_rv_dm_ndm_reset_req.1248138942 Aug 12 07:09:47 PM PDT 24 Aug 12 07:15:42 PM PDT 24 3912540856 ps
T442 /workspace/coverage/default/2.chip_sw_alert_handler_lpg_sleep_mode_alerts.3585752486 Aug 12 07:28:52 PM PDT 24 Aug 12 07:35:04 PM PDT 24 3652744040 ps
T443 /workspace/coverage/default/2.chip_sw_pwrmgr_full_aon_reset.301722538 Aug 12 07:24:08 PM PDT 24 Aug 12 07:34:10 PM PDT 24 6574322320 ps
T444 /workspace/coverage/default/82.chip_sw_alert_handler_lpg_sleep_mode_alerts.815370230 Aug 12 07:40:54 PM PDT 24 Aug 12 07:47:41 PM PDT 24 4218162900 ps
T47 /workspace/coverage/default/2.chip_sw_power_virus.4229923332 Aug 12 07:33:46 PM PDT 24 Aug 12 07:56:52 PM PDT 24 5271624480 ps
T445 /workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0.646267175 Aug 12 07:18:12 PM PDT 24 Aug 12 07:29:54 PM PDT 24 4525293538 ps
T446 /workspace/coverage/default/2.chip_sw_example_concurrency.1158998636 Aug 12 07:22:37 PM PDT 24 Aug 12 07:27:13 PM PDT 24 2836486480 ps
T447 /workspace/coverage/default/2.chip_sw_aes_enc_jitter_en_reduced_freq.701223868 Aug 12 07:28:48 PM PDT 24 Aug 12 07:33:06 PM PDT 24 2803948987 ps
T448 /workspace/coverage/default/46.chip_sw_all_escalation_resets.3417087114 Aug 12 07:37:25 PM PDT 24 Aug 12 07:46:13 PM PDT 24 4994937440 ps
T449 /workspace/coverage/default/4.chip_sw_uart_tx_rx_alt_clk_freq.2119089157 Aug 12 07:31:26 PM PDT 24 Aug 12 07:42:26 PM PDT 24 3777440409 ps
T74 /workspace/coverage/default/0.chip_tap_straps_rma.327044024 Aug 12 07:10:33 PM PDT 24 Aug 12 07:12:56 PM PDT 24 2846209983 ps
T887 /workspace/coverage/default/81.chip_sw_alert_handler_lpg_sleep_mode_alerts.3399784460 Aug 12 07:43:54 PM PDT 24 Aug 12 07:48:57 PM PDT 24 4212462376 ps
T1176 /workspace/coverage/default/1.rom_e2e_asm_init_test_unlocked0.4044673082 Aug 12 07:27:28 PM PDT 24 Aug 12 08:12:23 PM PDT 24 11406712418 ps
T1177 /workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_fast_rma.469196153 Aug 12 07:18:44 PM PDT 24 Aug 12 07:30:02 PM PDT 24 4116491742 ps
T265 /workspace/coverage/default/30.chip_sw_all_escalation_resets.595579117 Aug 12 07:36:40 PM PDT 24 Aug 12 07:44:40 PM PDT 24 5244877174 ps
T868 /workspace/coverage/default/8.chip_sw_all_escalation_resets.2768277144 Aug 12 07:35:23 PM PDT 24 Aug 12 07:47:41 PM PDT 24 5334787562 ps
T1178 /workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_fast_dev.3804891791 Aug 12 07:22:34 PM PDT 24 Aug 12 07:33:05 PM PDT 24 4352450176 ps
T1179 /workspace/coverage/default/77.chip_sw_all_escalation_resets.567575223 Aug 12 07:40:57 PM PDT 24 Aug 12 07:51:02 PM PDT 24 5200196304 ps
T56 /workspace/coverage/default/1.chip_jtag_csr_rw.2410091547 Aug 12 07:11:39 PM PDT 24 Aug 12 07:27:50 PM PDT 24 9283595196 ps
T348 /workspace/coverage/default/0.chip_sw_i2c_device_tx_rx.2102815154 Aug 12 07:08:57 PM PDT 24 Aug 12 07:21:55 PM PDT 24 4402710420 ps
T884 /workspace/coverage/default/31.chip_sw_all_escalation_resets.3726609492 Aug 12 07:37:01 PM PDT 24 Aug 12 07:44:29 PM PDT 24 4302936728 ps
T1180 /workspace/coverage/default/2.chip_sw_alert_handler_lpg_clkoff.964791681 Aug 12 07:31:14 PM PDT 24 Aug 12 07:45:41 PM PDT 24 5757884962 ps
T63 /workspace/coverage/default/2.chip_sw_spi_device_pinmux_sleep_retention.2805861394 Aug 12 07:24:37 PM PDT 24 Aug 12 07:30:35 PM PDT 24 3493222241 ps
T1181 /workspace/coverage/default/3.chip_sw_uart_tx_rx.4205057994 Aug 12 07:36:35 PM PDT 24 Aug 12 07:47:17 PM PDT 24 4413657600 ps
T1182 /workspace/coverage/default/11.chip_sw_uart_rand_baudrate.3042532924 Aug 12 07:34:21 PM PDT 24 Aug 12 07:41:41 PM PDT 24 4036736256 ps
T1183 /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0.3025139695 Aug 12 07:18:36 PM PDT 24 Aug 12 08:04:02 PM PDT 24 11726213296 ps
T1184 /workspace/coverage/default/0.rom_e2e_asm_init_prod_end.570159148 Aug 12 07:16:27 PM PDT 24 Aug 12 08:12:07 PM PDT 24 15399108682 ps
T1185 /workspace/coverage/default/2.chip_sw_aes_entropy.2631513817 Aug 12 07:26:40 PM PDT 24 Aug 12 07:30:19 PM PDT 24 3073729538 ps
T1186 /workspace/coverage/default/1.chip_sw_pwrmgr_main_power_glitch_reset.4036117616 Aug 12 07:13:36 PM PDT 24 Aug 12 07:18:18 PM PDT 24 3513054961 ps
T1187 /workspace/coverage/default/0.chip_sw_otbn_smoketest.3554904853 Aug 12 07:13:09 PM PDT 24 Aug 12 07:56:08 PM PDT 24 9644935484 ps
T1188 /workspace/coverage/default/2.rom_keymgr_functest.2953870154 Aug 12 07:30:55 PM PDT 24 Aug 12 07:39:55 PM PDT 24 4130216530 ps
T1189 /workspace/coverage/default/2.chip_sw_clkmgr_reset_frequency.1840481105 Aug 12 07:28:15 PM PDT 24 Aug 12 07:35:04 PM PDT 24 3608487520 ps
T1190 /workspace/coverage/default/1.chip_tap_straps_testunlock0.1077985906 Aug 12 07:19:44 PM PDT 24 Aug 12 07:27:37 PM PDT 24 5756487414 ps
T849 /workspace/coverage/default/60.chip_sw_alert_handler_lpg_sleep_mode_alerts.589726590 Aug 12 07:39:14 PM PDT 24 Aug 12 07:45:45 PM PDT 24 3757409816 ps
T106 /workspace/coverage/default/0.chip_sw_pwrmgr_random_sleep_all_wake_ups.1939954335 Aug 12 07:12:32 PM PDT 24 Aug 12 07:37:41 PM PDT 24 24590211160 ps
T1191 /workspace/coverage/default/1.chip_sw_edn_kat.185632930 Aug 12 07:16:44 PM PDT 24 Aug 12 07:26:14 PM PDT 24 3390098652 ps
T1192 /workspace/coverage/default/0.rom_e2e_asm_init_prod.2776196547 Aug 12 07:15:14 PM PDT 24 Aug 12 08:13:43 PM PDT 24 15482827290 ps
T1193 /workspace/coverage/default/51.chip_sw_alert_handler_lpg_sleep_mode_alerts.2381461323 Aug 12 07:38:54 PM PDT 24 Aug 12 07:44:07 PM PDT 24 3277354146 ps
T384 /workspace/coverage/default/2.chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up.634656354 Aug 12 07:28:53 PM PDT 24 Aug 12 07:35:45 PM PDT 24 5613194848 ps
T1194 /workspace/coverage/default/1.chip_sw_clkmgr_jitter_frequency.636013168 Aug 12 07:18:55 PM PDT 24 Aug 12 07:26:57 PM PDT 24 4151517184 ps
T1195 /workspace/coverage/default/4.chip_sw_csrng_edn_concurrency.2262058337 Aug 12 07:32:17 PM PDT 24 Aug 12 08:59:19 PM PDT 24 20537112328 ps
T1196 /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_bad_prod.798595803 Aug 12 07:17:40 PM PDT 24 Aug 12 08:27:19 PM PDT 24 14989051488 ps
T1197 /workspace/coverage/default/0.chip_sw_pwrmgr_sysrst_ctrl_reset.1082210125 Aug 12 07:10:53 PM PDT 24 Aug 12 07:35:50 PM PDT 24 7739680264 ps
T347 /workspace/coverage/default/0.chip_sw_i2c_host_tx_rx_idx2.9738947 Aug 12 07:08:28 PM PDT 24 Aug 12 07:22:09 PM PDT 24 4565537430 ps
T60 /workspace/coverage/default/1.chip_sw_sleep_pin_retention.3135548842 Aug 12 07:13:06 PM PDT 24 Aug 12 07:18:44 PM PDT 24 4445147882 ps
T208 /workspace/coverage/default/0.chip_jtag_csr_rw.2142854021 Aug 12 07:01:12 PM PDT 24 Aug 12 07:23:03 PM PDT 24 11893247711 ps
T181 /workspace/coverage/default/2.chip_sw_lc_ctrl_program_error.1486445708 Aug 12 07:27:46 PM PDT 24 Aug 12 07:35:38 PM PDT 24 4250367044 ps
T1198 /workspace/coverage/default/1.chip_sw_flash_ctrl_idle_low_power.1228700373 Aug 12 07:17:36 PM PDT 24 Aug 12 07:24:37 PM PDT 24 3526281930 ps
T1199 /workspace/coverage/default/3.chip_tap_straps_prod.2127040424 Aug 12 07:33:02 PM PDT 24 Aug 12 07:51:58 PM PDT 24 12179083991 ps
T366 /workspace/coverage/default/0.chip_sw_flash_ctrl_ops_jitter_en.4153806058 Aug 12 07:08:37 PM PDT 24 Aug 12 07:19:51 PM PDT 24 4730061423 ps
T91 /workspace/coverage/default/6.chip_sw_all_escalation_resets.742716021 Aug 12 07:33:09 PM PDT 24 Aug 12 07:44:14 PM PDT 24 4348747298 ps
T1200 /workspace/coverage/default/0.chip_sw_uart_tx_rx_bootstrap.612929844 Aug 12 07:08:35 PM PDT 24 Aug 12 10:53:17 PM PDT 24 79132576321 ps
T1201 /workspace/coverage/default/2.chip_sw_pwrmgr_sleep_disabled.1629209523 Aug 12 07:25:51 PM PDT 24 Aug 12 07:31:29 PM PDT 24 3266532700 ps
T190 /workspace/coverage/default/2.chip_sw_sram_ctrl_execution_main.1164213170 Aug 12 07:29:21 PM PDT 24 Aug 12 07:39:51 PM PDT 24 7473020227 ps
T1202 /workspace/coverage/default/2.chip_sw_aon_timer_wdog_lc_escalate.3512969928 Aug 12 07:26:57 PM PDT 24 Aug 12 07:36:52 PM PDT 24 4457438954 ps
T1203 /workspace/coverage/default/2.chip_sw_pwrmgr_deep_sleep_all_reset_reqs.4038850230 Aug 12 07:26:39 PM PDT 24 Aug 12 07:51:40 PM PDT 24 15429514185 ps
T1204 /workspace/coverage/default/0.chip_sw_uart_tx_rx_idx3.1121457281 Aug 12 07:08:15 PM PDT 24 Aug 12 07:19:50 PM PDT 24 4044142024 ps
T1205 /workspace/coverage/default/1.chip_sw_sleep_sram_ret_contents_scramble.4067357617 Aug 12 07:19:52 PM PDT 24 Aug 12 07:30:42 PM PDT 24 7590284088 ps
T1206 /workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0.2387407870 Aug 12 07:18:05 PM PDT 24 Aug 12 08:09:20 PM PDT 24 10995392732 ps
T1207 /workspace/coverage/default/2.chip_sw_csrng_smoketest.3823227239 Aug 12 07:32:35 PM PDT 24 Aug 12 07:37:23 PM PDT 24 2943146572 ps
T1208 /workspace/coverage/default/0.chip_sw_edn_kat.2649889833 Aug 12 07:11:22 PM PDT 24 Aug 12 07:21:43 PM PDT 24 3543966348 ps
T237 /workspace/coverage/default/2.chip_sw_flash_init_reduced_freq.3783374563 Aug 12 07:28:47 PM PDT 24 Aug 12 08:00:58 PM PDT 24 19226585774 ps
T36 /workspace/coverage/default/2.chip_sw_spi_host_tx_rx.2353492646 Aug 12 07:23:33 PM PDT 24 Aug 12 07:28:57 PM PDT 24 3150860784 ps
T821 /workspace/coverage/default/48.chip_sw_all_escalation_resets.4164451415 Aug 12 07:38:07 PM PDT 24 Aug 12 07:49:08 PM PDT 24 5055942528 ps
T153 /workspace/coverage/default/2.chip_sw_ast_clk_rst_inputs.2545246231 Aug 12 07:30:35 PM PDT 24 Aug 12 07:57:57 PM PDT 24 16334346526 ps
T847 /workspace/coverage/default/63.chip_sw_all_escalation_resets.511706914 Aug 12 07:40:19 PM PDT 24 Aug 12 07:53:18 PM PDT 24 5621211832 ps
T1209 /workspace/coverage/default/0.chip_sw_uart_tx_rx_alt_clk_freq.1236189096 Aug 12 07:08:09 PM PDT 24 Aug 12 07:40:47 PM PDT 24 8664465048 ps
T1210 /workspace/coverage/default/0.chip_sw_csrng_fuse_en_sw_app_read_test.2065099475 Aug 12 07:08:39 PM PDT 24 Aug 12 07:15:10 PM PDT 24 3700599086 ps
T1211 /workspace/coverage/default/2.chip_sw_keymgr_sideload_kmac.3853140584 Aug 12 07:26:45 PM PDT 24 Aug 12 08:02:05 PM PDT 24 12969323456 ps
T1212 /workspace/coverage/default/0.chip_sw_entropy_src_kat_test.3773602220 Aug 12 07:10:16 PM PDT 24 Aug 12 07:14:25 PM PDT 24 2172060052 ps
T324 /workspace/coverage/default/8.chip_sw_alert_handler_lpg_sleep_mode_alerts.631434779 Aug 12 07:34:49 PM PDT 24 Aug 12 07:41:44 PM PDT 24 3721403518 ps
T1213 /workspace/coverage/default/0.chip_sw_otp_ctrl_lc_signals_prod.1330497792 Aug 12 07:07:04 PM PDT 24 Aug 12 07:31:16 PM PDT 24 7939658168 ps
T191 /workspace/coverage/default/1.chip_sw_sram_ctrl_execution_main.3065847493 Aug 12 07:18:23 PM PDT 24 Aug 12 07:31:55 PM PDT 24 6589716089 ps
T866 /workspace/coverage/default/67.chip_sw_alert_handler_lpg_sleep_mode_alerts.3546386535 Aug 12 07:41:33 PM PDT 24 Aug 12 07:47:49 PM PDT 24 4056981340 ps
T837 /workspace/coverage/default/28.chip_sw_all_escalation_resets.1909355831 Aug 12 07:35:48 PM PDT 24 Aug 12 07:47:04 PM PDT 24 5042349774 ps
T1214 /workspace/coverage/default/2.chip_sw_rom_ctrl_integrity_check.1872804848 Aug 12 07:28:34 PM PDT 24 Aug 12 07:37:25 PM PDT 24 9123581980 ps
T1215 /workspace/coverage/default/0.chip_sw_alert_handler_ping_timeout.1841181001 Aug 12 07:09:58 PM PDT 24 Aug 12 07:16:53 PM PDT 24 4050858600 ps
T1216 /workspace/coverage/default/1.chip_sw_sleep_sram_ret_contents_no_scramble.4144369802 Aug 12 07:17:30 PM PDT 24 Aug 12 07:26:25 PM PDT 24 8222354566 ps
T1217 /workspace/coverage/default/2.chip_sw_clkmgr_off_kmac_trans.3934517374 Aug 12 07:28:39 PM PDT 24 Aug 12 07:39:03 PM PDT 24 4393587910 ps
T1218 /workspace/coverage/default/0.chip_sw_otp_ctrl_dai_lock.1310434961 Aug 12 07:11:52 PM PDT 24 Aug 12 08:51:31 PM PDT 24 27963674512 ps
T1219 /workspace/coverage/default/0.chip_sw_alert_handler_lpg_reset_toggle.3456861873 Aug 12 07:10:38 PM PDT 24 Aug 12 07:45:27 PM PDT 24 8213459432 ps
T1220 /workspace/coverage/default/1.chip_tap_straps_prod.2536571639 Aug 12 07:18:42 PM PDT 24 Aug 12 07:20:58 PM PDT 24 3128628219 ps
T1221 /workspace/coverage/default/0.chip_sw_keymgr_key_derivation_prod.3307361517 Aug 12 07:11:22 PM PDT 24 Aug 12 07:33:47 PM PDT 24 7319371408 ps
T1222 /workspace/coverage/default/80.chip_sw_all_escalation_resets.832547445 Aug 12 07:43:38 PM PDT 24 Aug 12 07:53:14 PM PDT 24 5795138026 ps
T416 /workspace/coverage/default/1.chip_rv_dm_ndm_reset_req.3077991016 Aug 12 07:19:56 PM PDT 24 Aug 12 07:26:05 PM PDT 24 3837972928 ps
T1223 /workspace/coverage/default/9.chip_sw_uart_rand_baudrate.2866487791 Aug 12 07:32:57 PM PDT 24 Aug 12 08:08:19 PM PDT 24 13218703240 ps
T1224 /workspace/coverage/default/0.chip_sw_pwrmgr_normal_sleep_por_reset.293121710 Aug 12 07:08:50 PM PDT 24 Aug 12 07:19:16 PM PDT 24 6945607668 ps
T1225 /workspace/coverage/default/0.chip_sw_pwrmgr_main_power_glitch_reset.1238189012 Aug 12 07:07:57 PM PDT 24 Aug 12 07:17:28 PM PDT 24 3519857170 ps
T168 /workspace/coverage/default/1.chip_plic_all_irqs_10.153131605 Aug 12 07:17:25 PM PDT 24 Aug 12 07:28:27 PM PDT 24 4165424072 ps
T750 /workspace/coverage/default/1.chip_sw_rv_dm_access_after_escalation_reset.3754147483 Aug 12 07:20:12 PM PDT 24 Aug 12 07:31:16 PM PDT 24 6561452413 ps
T1226 /workspace/coverage/default/7.chip_sw_alert_handler_lpg_sleep_mode_alerts.2818163815 Aug 12 07:33:37 PM PDT 24 Aug 12 07:42:03 PM PDT 24 4129985064 ps
T753 /workspace/coverage/default/4.chip_tap_straps_dev.3495878347 Aug 12 07:31:25 PM PDT 24 Aug 12 07:49:38 PM PDT 24 11015270659 ps
T757 /workspace/coverage/default/0.chip_sw_lc_ctrl_raw_to_scrap.3140780362 Aug 12 07:08:52 PM PDT 24 Aug 12 07:11:12 PM PDT 24 3150194928 ps
T1227 /workspace/coverage/default/1.chip_sw_uart_tx_rx_alt_clk_freq.3292004530 Aug 12 07:14:37 PM PDT 24 Aug 12 07:57:49 PM PDT 24 12633595389 ps
T1228 /workspace/coverage/default/2.chip_sw_clkmgr_off_aes_trans.3404093389 Aug 12 07:32:33 PM PDT 24 Aug 12 07:43:31 PM PDT 24 5973514300 ps
T1229 /workspace/coverage/default/2.chip_sw_clkmgr_off_otbn_trans.3821553672 Aug 12 07:27:33 PM PDT 24 Aug 12 07:38:59 PM PDT 24 4099200976 ps
T842 /workspace/coverage/default/42.chip_sw_all_escalation_resets.3160583877 Aug 12 07:37:36 PM PDT 24 Aug 12 07:48:24 PM PDT 24 4865909004 ps
T343 /workspace/coverage/default/0.chip_sw_entropy_src_csrng.2156660045 Aug 12 07:10:30 PM PDT 24 Aug 12 07:35:33 PM PDT 24 6223189276 ps
T1230 /workspace/coverage/default/0.chip_sw_rv_core_ibex_rnd.4082428783 Aug 12 07:08:09 PM PDT 24 Aug 12 07:27:18 PM PDT 24 5245279096 ps
T1231 /workspace/coverage/default/3.chip_sw_uart_tx_rx_idx3.4003229584 Aug 12 07:31:25 PM PDT 24 Aug 12 07:43:40 PM PDT 24 5203411284 ps
T455 /workspace/coverage/default/0.rom_e2e_jtag_inject_test_unlocked0.875300134 Aug 12 07:13:53 PM PDT 24 Aug 12 08:01:02 PM PDT 24 27075520619 ps
T352 /workspace/coverage/default/0.chip_sw_pwrmgr_lowpower_cancel.2675949168 Aug 12 07:08:55 PM PDT 24 Aug 12 07:15:37 PM PDT 24 3496518848 ps
T325 /workspace/coverage/default/76.chip_sw_all_escalation_resets.3093623095 Aug 12 07:40:49 PM PDT 24 Aug 12 07:49:45 PM PDT 24 4779574994 ps
T266 /workspace/coverage/default/2.chip_sw_rstmgr_cpu_info.614645509 Aug 12 07:26:13 PM PDT 24 Aug 12 07:35:32 PM PDT 24 6213197560 ps
T1232 /workspace/coverage/default/0.chip_sw_otp_ctrl_lc_signals_rma.362172907 Aug 12 07:07:09 PM PDT 24 Aug 12 07:27:13 PM PDT 24 7936326496 ps
T417 /workspace/coverage/default/2.chip_sw_pwrmgr_normal_sleep_all_wake_ups.518007180 Aug 12 07:28:28 PM PDT 24 Aug 12 07:37:19 PM PDT 24 7848253968 ps
T1233 /workspace/coverage/default/8.chip_sw_uart_rand_baudrate.2047912864 Aug 12 07:35:01 PM PDT 24 Aug 12 07:43:06 PM PDT 24 3048426708 ps
T758 /workspace/coverage/default/1.chip_sw_lc_ctrl_volatile_raw_unlock.61223212 Aug 12 07:13:43 PM PDT 24 Aug 12 07:15:30 PM PDT 24 2818264847 ps
T1234 /workspace/coverage/default/1.chip_sw_flash_ctrl_access_jitter_en_reduced_freq.2907258395 Aug 12 07:20:45 PM PDT 24 Aug 12 07:41:36 PM PDT 24 7129557354 ps
T1235 /workspace/coverage/default/2.chip_sw_flash_ctrl_access_jitter_en.862982122 Aug 12 07:23:16 PM PDT 24 Aug 12 07:42:42 PM PDT 24 6124136750 ps
T1236 /workspace/coverage/default/2.chip_sw_example_flash.3478820643 Aug 12 07:21:08 PM PDT 24 Aug 12 07:26:19 PM PDT 24 3339833800 ps
T1237 /workspace/coverage/default/1.chip_sw_flash_init_reduced_freq.4280015958 Aug 12 07:19:54 PM PDT 24 Aug 12 07:57:01 PM PDT 24 24999240461 ps
T1238 /workspace/coverage/default/2.chip_sw_kmac_entropy.539880524 Aug 12 07:24:59 PM PDT 24 Aug 12 07:28:09 PM PDT 24 2712682300 ps
T205 /workspace/coverage/default/0.chip_sw_spi_device_pass_through_collision.831231071 Aug 12 07:08:15 PM PDT 24 Aug 12 07:17:50 PM PDT 24 4790191807 ps
T835 /workspace/coverage/default/66.chip_sw_alert_handler_lpg_sleep_mode_alerts.4117349826 Aug 12 07:39:50 PM PDT 24 Aug 12 07:47:00 PM PDT 24 3294505604 ps
T839 /workspace/coverage/default/87.chip_sw_alert_handler_lpg_sleep_mode_alerts.805806031 Aug 12 07:42:24 PM PDT 24 Aug 12 07:47:35 PM PDT 24 3734348424 ps
T890 /workspace/coverage/default/69.chip_sw_alert_handler_lpg_sleep_mode_alerts.2043998652 Aug 12 07:40:06 PM PDT 24 Aug 12 07:45:38 PM PDT 24 3953699900 ps
T209 /workspace/coverage/default/2.chip_jtag_mem_access.415506481 Aug 12 07:21:12 PM PDT 24 Aug 12 07:43:26 PM PDT 24 13497979475 ps
T92 /workspace/coverage/default/15.chip_sw_all_escalation_resets.1403818054 Aug 12 07:34:26 PM PDT 24 Aug 12 07:44:54 PM PDT 24 5414658896 ps
T267 /workspace/coverage/default/0.chip_sw_rstmgr_cpu_info.1432576761 Aug 12 07:07:14 PM PDT 24 Aug 12 07:16:54 PM PDT 24 5575715528 ps
T1239 /workspace/coverage/default/18.chip_sw_uart_rand_baudrate.2239322661 Aug 12 07:38:58 PM PDT 24 Aug 12 08:04:41 PM PDT 24 8585220120 ps
T423 /workspace/coverage/default/0.chip_sw_pwrmgr_normal_sleep_all_wake_ups.305738203 Aug 12 07:12:24 PM PDT 24 Aug 12 07:18:41 PM PDT 24 7401921728 ps
T148 /workspace/coverage/default/4.chip_sw_sensor_ctrl_alert.2007770229 Aug 12 07:31:27 PM PDT 24 Aug 12 07:42:27 PM PDT 24 5101967896 ps
T1240 /workspace/coverage/default/1.chip_sw_pwrmgr_random_sleep_power_glitch_reset.390041061 Aug 12 07:16:04 PM PDT 24 Aug 12 08:06:30 PM PDT 24 30992483789 ps
T1241 /workspace/coverage/default/1.chip_sw_aes_idle.802224307 Aug 12 07:15:04 PM PDT 24 Aug 12 07:20:46 PM PDT 24 3560736888 ps
T1242 /workspace/coverage/default/1.chip_sw_pwrmgr_sleep_power_glitch_reset.1935380857 Aug 12 07:14:51 PM PDT 24 Aug 12 07:23:47 PM PDT 24 4851020908 ps
T1243 /workspace/coverage/default/0.chip_sw_kmac_smoketest.3009205721 Aug 12 07:13:19 PM PDT 24 Aug 12 07:18:13 PM PDT 24 2530461392 ps
T268 /workspace/coverage/default/0.chip_sw_all_escalation_resets.3335347842 Aug 12 07:08:18 PM PDT 24 Aug 12 07:18:47 PM PDT 24 6087143336 ps
T1244 /workspace/coverage/default/2.chip_sw_kmac_smoketest.734381056 Aug 12 07:31:47 PM PDT 24 Aug 12 07:37:05 PM PDT 24 2591317360 ps
T1245 /workspace/coverage/default/2.chip_sw_aes_smoketest.2792956551 Aug 12 07:29:44 PM PDT 24 Aug 12 07:34:52 PM PDT 24 3212907700 ps
T1246 /workspace/coverage/default/2.chip_sw_sensor_ctrl_status.2792602098 Aug 12 07:30:38 PM PDT 24 Aug 12 07:36:07 PM PDT 24 2953228306 ps
T1247 /workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0.1631099847 Aug 12 07:09:07 PM PDT 24 Aug 12 07:21:02 PM PDT 24 5213156480 ps
T1248 /workspace/coverage/default/2.chip_sw_rstmgr_smoketest.4101203951 Aug 12 07:31:03 PM PDT 24 Aug 12 07:36:21 PM PDT 24 2544559000 ps
T314 /workspace/coverage/default/0.chip_sw_sram_ctrl_execution_main.2937206047 Aug 12 07:12:11 PM PDT 24 Aug 12 07:22:07 PM PDT 24 6644681171 ps
T1249 /workspace/coverage/default/0.chip_sw_kmac_mode_kmac.3740302482 Aug 12 07:08:19 PM PDT 24 Aug 12 07:12:31 PM PDT 24 3070005344 ps
T1250 /workspace/coverage/default/1.chip_tap_straps_rma.3721147584 Aug 12 07:19:50 PM PDT 24 Aug 12 07:28:10 PM PDT 24 5648389925 ps
T1251 /workspace/coverage/default/1.rom_e2e_asm_init_rma.1662054423 Aug 12 07:26:21 PM PDT 24 Aug 12 08:28:36 PM PDT 24 15190602464 ps
T1252 /workspace/coverage/default/0.chip_sw_edn_sw_mode.1565238666 Aug 12 07:08:09 PM PDT 24 Aug 12 07:42:01 PM PDT 24 8518886476 ps
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