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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
96.03 95.47 93.71 95.35 94.54 97.53 99.57


Total test records in report: 2943
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T1253 /workspace/coverage/default/5.chip_sw_csrng_edn_concurrency.1283328091 Aug 12 07:33:37 PM PDT 24 Aug 12 08:53:12 PM PDT 24 21675752408 ps
T1254 /workspace/coverage/default/34.chip_sw_all_escalation_resets.2529960778 Aug 12 07:36:19 PM PDT 24 Aug 12 07:49:12 PM PDT 24 5951223950 ps
T1255 /workspace/coverage/default/0.chip_sw_hmac_enc.1134262901 Aug 12 07:10:57 PM PDT 24 Aug 12 07:16:13 PM PDT 24 3404260776 ps
T881 /workspace/coverage/default/38.chip_sw_alert_handler_lpg_sleep_mode_alerts.2189940270 Aug 12 07:36:51 PM PDT 24 Aug 12 07:42:53 PM PDT 24 4007352036 ps
T1256 /workspace/coverage/default/0.chip_sw_sysrst_ctrl_inputs.2619408583 Aug 12 07:07:59 PM PDT 24 Aug 12 07:12:58 PM PDT 24 3174752490 ps
T1257 /workspace/coverage/default/0.chip_sw_clkmgr_jitter.4012102949 Aug 12 07:11:14 PM PDT 24 Aug 12 07:14:39 PM PDT 24 2461362778 ps
T143 /workspace/coverage/default/0.chip_sw_sensor_ctrl_alert.3779340327 Aug 12 07:08:28 PM PDT 24 Aug 12 07:21:26 PM PDT 24 6549167500 ps
T1258 /workspace/coverage/default/0.chip_sw_pwrmgr_wdog_reset.2801605593 Aug 12 07:09:17 PM PDT 24 Aug 12 07:20:01 PM PDT 24 5987775872 ps
T1259 /workspace/coverage/default/0.chip_sw_clkmgr_smoketest.2972747711 Aug 12 07:10:15 PM PDT 24 Aug 12 07:14:15 PM PDT 24 2355819408 ps
T61 /workspace/coverage/default/0.chip_sw_sleep_pin_retention.740349720 Aug 12 07:09:46 PM PDT 24 Aug 12 07:15:25 PM PDT 24 2780154152 ps
T1260 /workspace/coverage/default/1.chip_sw_flash_ctrl_ops.2079587124 Aug 12 07:13:36 PM PDT 24 Aug 12 07:24:16 PM PDT 24 3371615396 ps
T1261 /workspace/coverage/default/0.chip_sw_aes_masking_off.2134093322 Aug 12 07:10:36 PM PDT 24 Aug 12 07:15:53 PM PDT 24 2242865343 ps
T548 /workspace/coverage/default/1.chip_sw_rv_core_ibex_nmi_irq.743519422 Aug 12 07:14:11 PM PDT 24 Aug 12 07:26:59 PM PDT 24 4566196162 ps
T1262 /workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0.1720846569 Aug 12 07:27:30 PM PDT 24 Aug 12 07:42:01 PM PDT 24 4424450898 ps
T1263 /workspace/coverage/default/1.chip_sw_uart_tx_rx_idx3.165445301 Aug 12 07:13:09 PM PDT 24 Aug 12 07:24:18 PM PDT 24 4405290312 ps
T1264 /workspace/coverage/default/1.chip_sw_hmac_oneshot.3932098472 Aug 12 07:18:39 PM PDT 24 Aug 12 07:23:51 PM PDT 24 2935145046 ps
T206 /workspace/coverage/default/1.chip_sw_spi_device_pass_through_collision.1205541086 Aug 12 07:12:43 PM PDT 24 Aug 12 07:21:41 PM PDT 24 4522105691 ps
T880 /workspace/coverage/default/1.chip_sw_all_escalation_resets.3919412107 Aug 12 07:11:46 PM PDT 24 Aug 12 07:22:51 PM PDT 24 6105933464 ps
T1265 /workspace/coverage/default/2.chip_sw_otbn_ecdsa_op_irq.1177425861 Aug 12 07:26:01 PM PDT 24 Aug 12 08:20:21 PM PDT 24 16597918848 ps
T811 /workspace/coverage/default/16.chip_sw_all_escalation_resets.221382246 Aug 12 07:35:00 PM PDT 24 Aug 12 07:48:04 PM PDT 24 4696555888 ps
T1266 /workspace/coverage/default/2.chip_sw_pwrmgr_wdog_reset.416109710 Aug 12 07:26:05 PM PDT 24 Aug 12 07:35:32 PM PDT 24 4897473110 ps
T192 /workspace/coverage/default/2.chip_sw_rv_core_ibex_icache_invalidate.113872289 Aug 12 07:29:19 PM PDT 24 Aug 12 07:34:19 PM PDT 24 2791007718 ps
T851 /workspace/coverage/default/30.chip_sw_alert_handler_lpg_sleep_mode_alerts.2745953265 Aug 12 07:36:31 PM PDT 24 Aug 12 07:43:33 PM PDT 24 4062165820 ps
T1267 /workspace/coverage/default/0.chip_sw_example_flash.3340727243 Aug 12 07:06:36 PM PDT 24 Aug 12 07:09:33 PM PDT 24 2321084856 ps
T1268 /workspace/coverage/default/1.chip_sw_lc_walkthrough_prod.1603514499 Aug 12 07:11:48 PM PDT 24 Aug 12 08:43:03 PM PDT 24 50778284388 ps
T1269 /workspace/coverage/default/1.chip_sw_exit_test_unlocked_bootstrap.188763782 Aug 12 07:12:16 PM PDT 24 Aug 12 09:59:39 PM PDT 24 57777119448 ps
T1270 /workspace/coverage/default/0.chip_sw_data_integrity_escalation.942006967 Aug 12 07:07:00 PM PDT 24 Aug 12 07:22:19 PM PDT 24 6693079100 ps
T424 /workspace/coverage/default/2.chip_sw_pwrmgr_deep_sleep_all_wake_ups.252681928 Aug 12 07:28:52 PM PDT 24 Aug 12 07:55:00 PM PDT 24 21704359804 ps
T1271 /workspace/coverage/default/1.chip_sw_otp_ctrl_lc_signals_dev.382316737 Aug 12 07:14:52 PM PDT 24 Aug 12 07:36:23 PM PDT 24 8330810350 ps
T801 /workspace/coverage/default/79.chip_sw_all_escalation_resets.2307977528 Aug 12 07:42:59 PM PDT 24 Aug 12 07:53:20 PM PDT 24 5195387996 ps
T1272 /workspace/coverage/default/2.chip_sw_sram_ctrl_scrambled_access_jitter_en.3725012871 Aug 12 07:27:27 PM PDT 24 Aug 12 07:39:19 PM PDT 24 4892217489 ps
T154 /workspace/coverage/default/1.chip_sw_ast_clk_rst_inputs.983085207 Aug 12 07:22:54 PM PDT 24 Aug 12 08:34:25 PM PDT 24 26578121599 ps
T1273 /workspace/coverage/default/1.chip_sw_sram_ctrl_scrambled_access.3404487091 Aug 12 07:18:11 PM PDT 24 Aug 12 07:29:09 PM PDT 24 5377612060 ps
T370 /workspace/coverage/default/2.chip_sw_i2c_host_tx_rx_idx2.3556201720 Aug 12 07:24:13 PM PDT 24 Aug 12 07:39:00 PM PDT 24 4640574428 ps
T1274 /workspace/coverage/default/2.chip_sw_clkmgr_jitter.1105701401 Aug 12 07:28:56 PM PDT 24 Aug 12 07:32:48 PM PDT 24 2193071826 ps
T1275 /workspace/coverage/default/1.chip_sw_clkmgr_reset_frequency.3600492394 Aug 12 07:18:29 PM PDT 24 Aug 12 07:28:00 PM PDT 24 3452619832 ps
T1276 /workspace/coverage/default/1.chip_sw_edn_auto_mode.2470342516 Aug 12 07:14:58 PM PDT 24 Aug 12 07:34:44 PM PDT 24 4833855788 ps
T144 /workspace/coverage/default/1.chip_sw_sensor_ctrl_alert.1011792792 Aug 12 07:19:22 PM PDT 24 Aug 12 07:29:41 PM PDT 24 5423150490 ps
T1277 /workspace/coverage/default/1.chip_sw_power_idle_load.4279759986 Aug 12 07:21:18 PM PDT 24 Aug 12 07:32:07 PM PDT 24 4508368322 ps
T1278 /workspace/coverage/default/0.rom_e2e_sigverify_always_a_nothing_b_bad_rma.2010903573 Aug 12 07:17:25 PM PDT 24 Aug 12 08:31:58 PM PDT 24 13597909992 ps
T1279 /workspace/coverage/default/0.rom_e2e_shutdown_output.1419561364 Aug 12 07:12:56 PM PDT 24 Aug 12 08:18:42 PM PDT 24 25622408625 ps
T1280 /workspace/coverage/default/2.chip_sw_csrng_fuse_en_sw_app_read_test.3896904289 Aug 12 07:26:45 PM PDT 24 Aug 12 07:33:11 PM PDT 24 4776002664 ps
T1281 /workspace/coverage/default/2.chip_sw_plic_sw_irq.1766290283 Aug 12 07:30:18 PM PDT 24 Aug 12 07:35:12 PM PDT 24 2901515000 ps
T1282 /workspace/coverage/default/1.rom_volatile_raw_unlock.1218249743 Aug 12 07:22:25 PM PDT 24 Aug 12 07:24:28 PM PDT 24 2217400113 ps
T1283 /workspace/coverage/default/31.chip_sw_alert_handler_lpg_sleep_mode_alerts.2858635684 Aug 12 07:36:25 PM PDT 24 Aug 12 07:45:26 PM PDT 24 4306447512 ps
T1284 /workspace/coverage/default/1.chip_sw_csrng_lc_hw_debug_en_test.3306833614 Aug 12 07:15:34 PM PDT 24 Aug 12 07:27:21 PM PDT 24 6094638039 ps
T549 /workspace/coverage/default/2.chip_sw_rv_core_ibex_nmi_irq.1477407991 Aug 12 07:25:41 PM PDT 24 Aug 12 07:39:46 PM PDT 24 4612853256 ps
T37 /workspace/coverage/default/0.chip_sw_spi_host_tx_rx.3708502036 Aug 12 07:08:44 PM PDT 24 Aug 12 07:12:37 PM PDT 24 2648070632 ps
T93 /workspace/coverage/default/17.chip_sw_all_escalation_resets.280208058 Aug 12 07:37:10 PM PDT 24 Aug 12 07:47:59 PM PDT 24 4919575164 ps
T44 /workspace/coverage/default/1.chip_sw_spi_device_tpm.1127124642 Aug 12 07:14:01 PM PDT 24 Aug 12 07:19:22 PM PDT 24 3703815014 ps
T64 /workspace/coverage/default/0.chip_sw_spi_device_pinmux_sleep_retention.2094100465 Aug 12 07:06:48 PM PDT 24 Aug 12 07:11:58 PM PDT 24 3684975818 ps
T1285 /workspace/coverage/default/1.chip_sw_uart_tx_rx_alt_clk_freq_low_speed.1563744313 Aug 12 07:12:52 PM PDT 24 Aug 12 07:21:11 PM PDT 24 4007034610 ps
T425 /workspace/coverage/default/0.chip_sw_pwrmgr_deep_sleep_all_wake_ups.162783921 Aug 12 07:14:28 PM PDT 24 Aug 12 07:46:52 PM PDT 24 23777012840 ps
T1286 /workspace/coverage/default/0.chip_sw_flash_scrambling_smoketest.1513435390 Aug 12 07:15:44 PM PDT 24 Aug 12 07:19:07 PM PDT 24 2305026176 ps
T193 /workspace/coverage/default/1.chip_sw_rv_core_ibex_address_translation.1393151788 Aug 12 07:21:14 PM PDT 24 Aug 12 07:26:54 PM PDT 24 3633352052 ps
T1287 /workspace/coverage/default/0.chip_sw_i2c_host_tx_rx.491780603 Aug 12 07:07:46 PM PDT 24 Aug 12 07:21:44 PM PDT 24 5593480800 ps
T1288 /workspace/coverage/default/1.chip_sw_otp_ctrl_smoketest.1069550675 Aug 12 07:22:09 PM PDT 24 Aug 12 07:25:53 PM PDT 24 2455889780 ps
T1289 /workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_fast_dev.2404504959 Aug 12 07:27:42 PM PDT 24 Aug 12 07:39:25 PM PDT 24 3859095768 ps
T1290 /workspace/coverage/default/0.chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq.4072956552 Aug 12 07:09:59 PM PDT 24 Aug 12 08:17:45 PM PDT 24 24356626232 ps
T840 /workspace/coverage/default/65.chip_sw_alert_handler_lpg_sleep_mode_alerts.1930972957 Aug 12 07:39:47 PM PDT 24 Aug 12 07:45:42 PM PDT 24 3707702906 ps
T1291 /workspace/coverage/default/3.chip_tap_straps_rma.1871504551 Aug 12 07:31:02 PM PDT 24 Aug 12 07:41:31 PM PDT 24 6734813045 ps
T1292 /workspace/coverage/default/0.chip_sw_kmac_idle.815343624 Aug 12 07:12:57 PM PDT 24 Aug 12 07:17:02 PM PDT 24 2522531238 ps
T751 /workspace/coverage/default/2.chip_sw_rv_dm_access_after_escalation_reset.2380892364 Aug 12 07:29:49 PM PDT 24 Aug 12 07:38:18 PM PDT 24 5862027110 ps
T1293 /workspace/coverage/default/0.chip_sw_clkmgr_sleep_frequency.801964356 Aug 12 07:15:12 PM PDT 24 Aug 12 07:29:37 PM PDT 24 4476271728 ps
T30 /workspace/coverage/default/1.chip_sw_gpio.281634324 Aug 12 07:13:06 PM PDT 24 Aug 12 07:20:46 PM PDT 24 3980195395 ps
T1294 /workspace/coverage/default/0.chip_sw_aon_timer_wdog_bite_reset.2917011286 Aug 12 07:09:07 PM PDT 24 Aug 12 07:20:59 PM PDT 24 8968283296 ps
T1295 /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_good_test_unlocked0.3489286305 Aug 12 07:16:27 PM PDT 24 Aug 12 08:06:18 PM PDT 24 11129125872 ps
T1296 /workspace/coverage/default/1.chip_sw_example_flash.2117251555 Aug 12 07:13:11 PM PDT 24 Aug 12 07:16:47 PM PDT 24 3012526680 ps
T45 /workspace/coverage/default/0.chip_sw_spi_device_tpm.1115531442 Aug 12 07:06:36 PM PDT 24 Aug 12 07:11:48 PM PDT 24 3912507210 ps
T1297 /workspace/coverage/default/1.chip_sw_uart_tx_rx_idx1.3448390961 Aug 12 07:11:44 PM PDT 24 Aug 12 07:20:33 PM PDT 24 4221809176 ps
T1298 /workspace/coverage/default/64.chip_sw_alert_handler_lpg_sleep_mode_alerts.3647156169 Aug 12 07:40:20 PM PDT 24 Aug 12 07:47:00 PM PDT 24 4052918420 ps
T1299 /workspace/coverage/default/84.chip_sw_all_escalation_resets.664175777 Aug 12 07:43:19 PM PDT 24 Aug 12 07:53:42 PM PDT 24 4994888700 ps
T1300 /workspace/coverage/default/1.chip_sw_hmac_multistream.507636728 Aug 12 07:17:48 PM PDT 24 Aug 12 07:47:31 PM PDT 24 7437458104 ps
T1301 /workspace/coverage/default/2.chip_sw_keymgr_key_derivation_jitter_en_reduced_freq.1460205411 Aug 12 07:29:48 PM PDT 24 Aug 12 07:53:52 PM PDT 24 8739061369 ps
T1302 /workspace/coverage/default/0.chip_sw_example_concurrency.3650581348 Aug 12 07:08:31 PM PDT 24 Aug 12 07:13:40 PM PDT 24 2812509720 ps
T94 /workspace/coverage/default/10.chip_sw_alert_handler_lpg_sleep_mode_alerts.3702617695 Aug 12 07:33:54 PM PDT 24 Aug 12 07:40:45 PM PDT 24 3649861840 ps
T230 /workspace/coverage/default/0.chip_sw_keymgr_sideload_aes.3086000044 Aug 12 07:09:07 PM PDT 24 Aug 12 07:51:13 PM PDT 24 11393019634 ps
T818 /workspace/coverage/default/40.chip_sw_alert_handler_lpg_sleep_mode_alerts.617270327 Aug 12 07:37:09 PM PDT 24 Aug 12 07:44:06 PM PDT 24 4438201362 ps
T298 /workspace/coverage/default/50.chip_sw_all_escalation_resets.4039793404 Aug 12 07:38:45 PM PDT 24 Aug 12 07:46:42 PM PDT 24 4310603144 ps
T1303 /workspace/coverage/default/1.chip_tap_straps_dev.3240493452 Aug 12 07:20:59 PM PDT 24 Aug 12 07:44:09 PM PDT 24 15223597111 ps
T1304 /workspace/coverage/default/1.chip_sw_clkmgr_sleep_frequency.2990090239 Aug 12 07:19:49 PM PDT 24 Aug 12 07:33:25 PM PDT 24 4901282352 ps
T1305 /workspace/coverage/default/0.chip_sw_flash_ctrl_idle_low_power.2080915550 Aug 12 07:09:41 PM PDT 24 Aug 12 07:16:49 PM PDT 24 2854573856 ps
T1306 /workspace/coverage/default/4.chip_tap_straps_rma.3863144760 Aug 12 07:31:16 PM PDT 24 Aug 12 07:41:47 PM PDT 24 6116941639 ps
T231 /workspace/coverage/default/1.chip_sw_keymgr_sideload_aes.830917036 Aug 12 07:16:50 PM PDT 24 Aug 12 07:54:59 PM PDT 24 10083829462 ps
T1307 /workspace/coverage/default/1.chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz.1319314502 Aug 12 07:14:48 PM PDT 24 Aug 12 07:16:38 PM PDT 24 2222850455 ps
T1308 /workspace/coverage/default/0.chip_sw_rstmgr_rst_cnsty_escalation.4242507797 Aug 12 07:06:45 PM PDT 24 Aug 12 07:17:54 PM PDT 24 6504961240 ps
T786 /workspace/coverage/default/0.rom_raw_unlock.3070481139 Aug 12 07:11:07 PM PDT 24 Aug 12 07:15:11 PM PDT 24 4984047136 ps
T1309 /workspace/coverage/default/2.chip_sw_power_sleep_load.3281921758 Aug 12 07:28:58 PM PDT 24 Aug 12 07:39:59 PM PDT 24 10759534372 ps
T1310 /workspace/coverage/default/0.rom_e2e_sigverify_always_a_nothing_b_bad_prod.2245639801 Aug 12 07:17:51 PM PDT 24 Aug 12 08:25:30 PM PDT 24 15527628567 ps
T1311 /workspace/coverage/default/2.chip_sw_otp_ctrl_lc_signals_rma.622505372 Aug 12 07:25:07 PM PDT 24 Aug 12 07:47:55 PM PDT 24 7022601760 ps
T376 /workspace/coverage/default/1.chip_sw_flash_ctrl_ops_jitter_en.3662056843 Aug 12 07:14:01 PM PDT 24 Aug 12 07:26:58 PM PDT 24 4303298820 ps
T1312 /workspace/coverage/default/2.chip_sw_aes_masking_off.3125828568 Aug 12 07:25:50 PM PDT 24 Aug 12 07:30:26 PM PDT 24 2761064166 ps
T1313 /workspace/coverage/default/2.chip_sw_adc_ctrl_sleep_debug_cable_wakeup.337848380 Aug 12 07:25:35 PM PDT 24 Aug 12 07:35:44 PM PDT 24 19794443608 ps
T179 /workspace/coverage/default/96.chip_sw_all_escalation_resets.1890108360 Aug 12 07:41:05 PM PDT 24 Aug 12 07:52:41 PM PDT 24 6467654460 ps
T1314 /workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_lc.1760662928 Aug 12 07:28:36 PM PDT 24 Aug 12 07:40:23 PM PDT 24 12210660837 ps
T1315 /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0.2452708162 Aug 12 07:16:00 PM PDT 24 Aug 12 08:36:50 PM PDT 24 18654171848 ps
T833 /workspace/coverage/default/55.chip_sw_alert_handler_lpg_sleep_mode_alerts.1365295415 Aug 12 07:42:34 PM PDT 24 Aug 12 07:50:52 PM PDT 24 3942330680 ps
T1316 /workspace/coverage/default/1.chip_sw_pwrmgr_usbdev_smoketest.3060695982 Aug 12 07:21:43 PM PDT 24 Aug 12 07:32:01 PM PDT 24 6261963008 ps
T803 /workspace/coverage/default/52.chip_sw_all_escalation_resets.2343681360 Aug 12 07:38:04 PM PDT 24 Aug 12 07:48:00 PM PDT 24 6182075080 ps
T1317 /workspace/coverage/default/0.chip_sw_aon_timer_sleep_wdog_sleep_pause.3955929779 Aug 12 07:08:50 PM PDT 24 Aug 12 07:16:56 PM PDT 24 7398556604 ps
T1318 /workspace/coverage/default/1.chip_sw_aon_timer_wdog_bite_reset.1006242207 Aug 12 07:14:17 PM PDT 24 Aug 12 07:27:48 PM PDT 24 9526891138 ps
T380 /workspace/coverage/default/2.chip_sw_hmac_enc.3603418451 Aug 12 07:26:38 PM PDT 24 Aug 12 07:31:19 PM PDT 24 2908455128 ps
T1319 /workspace/coverage/default/2.chip_sw_clkmgr_sleep_frequency.3439944174 Aug 12 07:28:37 PM PDT 24 Aug 12 07:37:15 PM PDT 24 4946828744 ps
T1320 /workspace/coverage/default/1.chip_sw_inject_scramble_seed.3432844813 Aug 12 07:15:56 PM PDT 24 Aug 12 10:12:03 PM PDT 24 64579908355 ps
T1321 /workspace/coverage/default/1.rom_e2e_shutdown_exception_c.3339128272 Aug 12 07:27:06 PM PDT 24 Aug 12 08:45:15 PM PDT 24 14284411575 ps
T1322 /workspace/coverage/default/1.chip_sw_sysrst_ctrl_ec_rst_l.3623497900 Aug 12 07:15:16 PM PDT 24 Aug 12 08:05:54 PM PDT 24 20875075724 ps
T1323 /workspace/coverage/default/2.chip_sw_kmac_mode_cshake.3423318756 Aug 12 07:26:56 PM PDT 24 Aug 12 07:32:20 PM PDT 24 2642219408 ps
T78 /workspace/coverage/default/0.chip_sw_usbdev_pullup.2225010098 Aug 12 07:07:42 PM PDT 24 Aug 12 07:12:21 PM PDT 24 2966625564 ps
T1324 /workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_slow_rma.1777067890 Aug 12 07:11:03 PM PDT 24 Aug 12 07:22:19 PM PDT 24 5062385744 ps
T232 /workspace/coverage/default/2.chip_sw_keymgr_sideload_aes.2564860818 Aug 12 07:28:09 PM PDT 24 Aug 12 08:10:55 PM PDT 24 13125542920 ps
T1325 /workspace/coverage/default/2.chip_sw_alert_handler_lpg_sleep_mode_pings.145544820 Aug 12 07:27:22 PM PDT 24 Aug 12 07:46:49 PM PDT 24 11368410584 ps
T1326 /workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_slow_dev.931593981 Aug 12 07:28:45 PM PDT 24 Aug 12 07:38:23 PM PDT 24 5327874700 ps
T1327 /workspace/coverage/default/0.chip_sw_otp_ctrl_lc_signals_test_unlocked0.3413726122 Aug 12 07:11:24 PM PDT 24 Aug 12 07:25:50 PM PDT 24 4506285330 ps
T1328 /workspace/coverage/default/0.chip_sw_inject_scramble_seed.954042225 Aug 12 07:07:14 PM PDT 24 Aug 12 10:13:25 PM PDT 24 65460538714 ps
T1329 /workspace/coverage/default/1.chip_sw_example_manufacturer.233773787 Aug 12 07:15:12 PM PDT 24 Aug 12 07:18:34 PM PDT 24 2859212836 ps
T1330 /workspace/coverage/default/61.chip_sw_all_escalation_resets.1523376435 Aug 12 07:39:39 PM PDT 24 Aug 12 07:52:17 PM PDT 24 4691149080 ps
T1331 /workspace/coverage/default/1.chip_sw_flash_ctrl_mem_protection.1192441920 Aug 12 07:22:11 PM PDT 24 Aug 12 07:40:24 PM PDT 24 5600594500 ps
T1332 /workspace/coverage/default/2.chip_sw_hmac_enc_jitter_en.1965082818 Aug 12 07:26:21 PM PDT 24 Aug 12 07:30:04 PM PDT 24 3370104361 ps
T1333 /workspace/coverage/default/2.chip_sw_kmac_mode_kmac.846376217 Aug 12 07:27:03 PM PDT 24 Aug 12 07:33:06 PM PDT 24 3725602344 ps
T1334 /workspace/coverage/default/1.chip_sw_kmac_mode_cshake.729562282 Aug 12 07:16:44 PM PDT 24 Aug 12 07:21:08 PM PDT 24 2823196104 ps
T1335 /workspace/coverage/default/0.chip_sw_aon_timer_irq.235082926 Aug 12 07:07:52 PM PDT 24 Aug 12 07:15:48 PM PDT 24 3642076952 ps
T1336 /workspace/coverage/default/1.chip_sw_alert_handler_lpg_sleep_mode_alerts.1836200016 Aug 12 07:15:21 PM PDT 24 Aug 12 07:23:09 PM PDT 24 3733705098 ps
T115 /workspace/coverage/default/2.chip_rv_dm_ndm_reset_req.3553312366 Aug 12 07:28:51 PM PDT 24 Aug 12 07:34:43 PM PDT 24 4300973544 ps
T1337 /workspace/coverage/default/0.chip_sw_alert_handler_ping_ok.669139867 Aug 12 07:10:47 PM PDT 24 Aug 12 07:40:26 PM PDT 24 8362997766 ps
T1338 /workspace/coverage/default/1.chip_sw_csrng_edn_concurrency.3636817506 Aug 12 07:15:46 PM PDT 24 Aug 12 09:01:46 PM PDT 24 31516191912 ps
T832 /workspace/coverage/default/4.chip_sw_alert_handler_lpg_sleep_mode_alerts.1955557391 Aug 12 07:32:14 PM PDT 24 Aug 12 07:39:00 PM PDT 24 4682309368 ps
T882 /workspace/coverage/default/85.chip_sw_all_escalation_resets.17382969 Aug 12 07:41:44 PM PDT 24 Aug 12 07:54:50 PM PDT 24 5028989244 ps
T196 /workspace/coverage/default/2.chip_sw_flash_rma_unlocked.2053106821 Aug 12 07:23:16 PM PDT 24 Aug 12 08:51:11 PM PDT 24 42913878789 ps
T1339 /workspace/coverage/default/0.chip_sw_alert_handler_escalation.2820513669 Aug 12 07:10:34 PM PDT 24 Aug 12 07:20:48 PM PDT 24 4739519790 ps
T1340 /workspace/coverage/default/0.chip_sw_flash_ctrl_clock_freqs.3533475439 Aug 12 07:06:11 PM PDT 24 Aug 12 07:23:06 PM PDT 24 5633685460 ps
T1341 /workspace/coverage/default/0.chip_sw_flash_ctrl_mem_protection.1272396235 Aug 12 07:13:03 PM PDT 24 Aug 12 07:30:56 PM PDT 24 5485950218 ps
T1342 /workspace/coverage/default/8.chip_sw_lc_ctrl_transition.2241364220 Aug 12 07:32:56 PM PDT 24 Aug 12 07:42:15 PM PDT 24 7176982609 ps
T1343 /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_good_rma.4245300158 Aug 12 07:15:46 PM PDT 24 Aug 12 08:33:33 PM PDT 24 14990652400 ps
T1344 /workspace/coverage/default/0.chip_sw_pwrmgr_random_sleep_power_glitch_reset.1373587455 Aug 12 07:08:33 PM PDT 24 Aug 12 08:00:18 PM PDT 24 37877649760 ps
T1345 /workspace/coverage/default/4.chip_sw_aon_timer_sleep_wdog_sleep_pause.4010866943 Aug 12 07:32:29 PM PDT 24 Aug 12 07:39:22 PM PDT 24 6492440728 ps
T1346 /workspace/coverage/default/1.chip_sw_aes_enc_jitter_en.2705105696 Aug 12 07:17:39 PM PDT 24 Aug 12 07:22:14 PM PDT 24 2541540061 ps
T850 /workspace/coverage/default/47.chip_sw_all_escalation_resets.3347325678 Aug 12 07:37:35 PM PDT 24 Aug 12 07:45:19 PM PDT 24 4663392910 ps
T1347 /workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_slow_rma.2432551377 Aug 12 07:19:06 PM PDT 24 Aug 12 07:30:27 PM PDT 24 5092961442 ps
T1348 /workspace/coverage/default/2.chip_sw_sleep_pwm_pulses.1525407819 Aug 12 07:22:36 PM PDT 24 Aug 12 07:44:04 PM PDT 24 9014139674 ps
T116 /workspace/coverage/default/0.chip_sw_sleep_pin_wake.603300908 Aug 12 07:11:33 PM PDT 24 Aug 12 07:19:00 PM PDT 24 4779724792 ps
T428 /workspace/coverage/default/2.chip_sw_sysrst_ctrl_ec_rst_l.2655533005 Aug 12 07:24:26 PM PDT 24 Aug 12 08:11:36 PM PDT 24 20322925756 ps
T326 /workspace/coverage/default/71.chip_sw_alert_handler_lpg_sleep_mode_alerts.1962433762 Aug 12 07:39:16 PM PDT 24 Aug 12 07:45:04 PM PDT 24 3114281076 ps
T429 /workspace/coverage/default/0.chip_sw_power_idle_load.1664236995 Aug 12 07:09:44 PM PDT 24 Aug 12 07:22:41 PM PDT 24 4616192750 ps
T430 /workspace/coverage/default/4.chip_sw_uart_rand_baudrate.2410375505 Aug 12 07:31:37 PM PDT 24 Aug 12 07:39:41 PM PDT 24 3619830000 ps
T431 /workspace/coverage/default/9.chip_sw_alert_handler_lpg_sleep_mode_alerts.2381756138 Aug 12 07:36:10 PM PDT 24 Aug 12 07:42:21 PM PDT 24 3355071416 ps
T432 /workspace/coverage/default/0.chip_sw_clkmgr_off_aes_trans.1318788889 Aug 12 07:08:16 PM PDT 24 Aug 12 07:15:15 PM PDT 24 4495197200 ps
T336 /workspace/coverage/default/1.chip_plic_all_irqs_0.1052720482 Aug 12 07:19:20 PM PDT 24 Aug 12 07:45:22 PM PDT 24 6022512628 ps
T433 /workspace/coverage/default/2.chip_sw_rv_core_ibex_rnd.1925901424 Aug 12 07:26:03 PM PDT 24 Aug 12 07:44:22 PM PDT 24 5879662506 ps
T339 /workspace/coverage/default/2.chip_sw_rstmgr_alert_info.255193483 Aug 12 07:28:03 PM PDT 24 Aug 12 07:54:49 PM PDT 24 12539086910 ps
T1349 /workspace/coverage/default/2.chip_sw_flash_ctrl_lc_rw_en.1255317191 Aug 12 07:23:33 PM PDT 24 Aug 12 07:29:33 PM PDT 24 4069585420 ps
T207 /workspace/coverage/default/1.chip_sw_power_virus.2647493437 Aug 12 07:24:38 PM PDT 24 Aug 12 07:49:39 PM PDT 24 5959241992 ps
T873 /workspace/coverage/default/29.chip_sw_all_escalation_resets.3356117173 Aug 12 07:36:54 PM PDT 24 Aug 12 07:47:55 PM PDT 24 5577614782 ps
T1350 /workspace/coverage/default/1.chip_sival_flash_info_access.3985913058 Aug 12 07:13:37 PM PDT 24 Aug 12 07:18:38 PM PDT 24 3667385954 ps
T819 /workspace/coverage/default/68.chip_sw_all_escalation_resets.629618272 Aug 12 07:38:56 PM PDT 24 Aug 12 07:48:49 PM PDT 24 5196267480 ps
T1351 /workspace/coverage/default/2.rom_e2e_shutdown_exception_c.2591289777 Aug 12 07:36:35 PM PDT 24 Aug 12 08:46:04 PM PDT 24 14590761080 ps
T1352 /workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_fast_rma.528106856 Aug 12 07:30:07 PM PDT 24 Aug 12 07:41:29 PM PDT 24 4265250402 ps
T95 /workspace/coverage/default/93.chip_sw_all_escalation_resets.4003833228 Aug 12 07:41:19 PM PDT 24 Aug 12 07:50:25 PM PDT 24 5526257196 ps
T1353 /workspace/coverage/default/2.chip_sw_sleep_sram_ret_contents_no_scramble.4267851868 Aug 12 07:30:40 PM PDT 24 Aug 12 07:43:22 PM PDT 24 9111102730 ps
T299 /workspace/coverage/default/59.chip_sw_alert_handler_lpg_sleep_mode_alerts.1989467146 Aug 12 07:42:43 PM PDT 24 Aug 12 07:49:10 PM PDT 24 3406171354 ps
T304 /workspace/coverage/default/0.chip_sw_rv_core_ibex_address_translation.1143902151 Aug 12 07:08:40 PM PDT 24 Aug 12 07:13:16 PM PDT 24 2809892336 ps
T1354 /workspace/coverage/default/66.chip_sw_all_escalation_resets.1023343551 Aug 12 07:40:12 PM PDT 24 Aug 12 07:48:59 PM PDT 24 4934024568 ps
T1355 /workspace/coverage/default/0.rom_e2e_keymgr_init_rom_ext_meas.1578550169 Aug 12 07:17:09 PM PDT 24 Aug 12 08:18:36 PM PDT 24 15237898370 ps
T1356 /workspace/coverage/default/0.rom_e2e_static_critical.684261364 Aug 12 07:15:30 PM PDT 24 Aug 12 08:20:56 PM PDT 24 17523807250 ps
T1357 /workspace/coverage/default/0.rom_volatile_raw_unlock.4004541499 Aug 12 07:10:54 PM PDT 24 Aug 12 07:12:39 PM PDT 24 2435550397 ps
T1358 /workspace/coverage/default/2.chip_sw_pwrmgr_usb_clk_disabled_when_active.227498537 Aug 12 07:24:48 PM PDT 24 Aug 12 07:37:52 PM PDT 24 4257141480 ps
T875 /workspace/coverage/default/60.chip_sw_all_escalation_resets.3799736104 Aug 12 07:38:54 PM PDT 24 Aug 12 07:47:13 PM PDT 24 5012937160 ps
T234 /workspace/coverage/default/0.chip_sw_keymgr_sideload_otbn.819710992 Aug 12 07:11:09 PM PDT 24 Aug 12 08:17:18 PM PDT 24 16108129200 ps
T843 /workspace/coverage/default/26.chip_sw_all_escalation_resets.3702520546 Aug 12 07:35:07 PM PDT 24 Aug 12 07:45:35 PM PDT 24 5443862018 ps
T327 /workspace/coverage/default/22.chip_sw_alert_handler_lpg_sleep_mode_alerts.1953753624 Aug 12 07:36:00 PM PDT 24 Aug 12 07:43:30 PM PDT 24 4166470132 ps
T1359 /workspace/coverage/default/72.chip_sw_all_escalation_resets.1972239953 Aug 12 07:39:41 PM PDT 24 Aug 12 07:49:42 PM PDT 24 4619324528 ps
T1360 /workspace/coverage/default/0.chip_sw_aon_timer_smoketest.3965759622 Aug 12 07:14:02 PM PDT 24 Aug 12 07:19:16 PM PDT 24 3521244812 ps
T1361 /workspace/coverage/default/2.rom_e2e_keymgr_init_rom_ext_meas.3614198895 Aug 12 07:36:38 PM PDT 24 Aug 12 08:46:02 PM PDT 24 15429953012 ps
T820 /workspace/coverage/default/73.chip_sw_all_escalation_resets.1497976255 Aug 12 07:40:58 PM PDT 24 Aug 12 07:49:28 PM PDT 24 5363224760 ps
T1362 /workspace/coverage/default/49.chip_sw_alert_handler_lpg_sleep_mode_alerts.2824085505 Aug 12 07:37:57 PM PDT 24 Aug 12 07:46:00 PM PDT 24 3651922348 ps
T965 /workspace/coverage/default/1.chip_jtag_mem_access.794671467 Aug 12 07:11:49 PM PDT 24 Aug 12 07:38:10 PM PDT 24 13937606243 ps
T874 /workspace/coverage/default/39.chip_sw_all_escalation_resets.603797301 Aug 12 07:37:01 PM PDT 24 Aug 12 07:45:23 PM PDT 24 4792326146 ps
T1363 /workspace/coverage/default/2.rom_e2e_asm_init_prod_end.2178868521 Aug 12 07:34:49 PM PDT 24 Aug 12 08:38:02 PM PDT 24 15457651214 ps
T1364 /workspace/coverage/default/0.chip_sw_clkmgr_off_hmac_trans.3216750582 Aug 12 07:10:36 PM PDT 24 Aug 12 07:18:28 PM PDT 24 3936826336 ps
T1365 /workspace/coverage/default/1.chip_sw_alert_handler_lpg_clkoff.150731717 Aug 12 07:15:03 PM PDT 24 Aug 12 07:46:17 PM PDT 24 8467500216 ps
T1366 /workspace/coverage/default/1.chip_sw_aes_enc_jitter_en_reduced_freq.2681097463 Aug 12 07:20:47 PM PDT 24 Aug 12 07:25:32 PM PDT 24 3343346336 ps
T1367 /workspace/coverage/default/1.chip_sw_uart_smoketest.3565764948 Aug 12 07:22:44 PM PDT 24 Aug 12 07:26:27 PM PDT 24 2477077600 ps
T1368 /workspace/coverage/default/5.chip_sw_data_integrity_escalation.1228422071 Aug 12 07:32:28 PM PDT 24 Aug 12 07:47:43 PM PDT 24 6612492192 ps
T1369 /workspace/coverage/default/2.chip_sw_keymgr_key_derivation_jitter_en.3231707200 Aug 12 07:27:09 PM PDT 24 Aug 12 07:48:36 PM PDT 24 6575395788 ps
T1370 /workspace/coverage/default/3.chip_tap_straps_testunlock0.954078130 Aug 12 07:31:58 PM PDT 24 Aug 12 07:36:09 PM PDT 24 3759102147 ps
T834 /workspace/coverage/default/20.chip_sw_alert_handler_lpg_sleep_mode_alerts.2122907687 Aug 12 07:35:17 PM PDT 24 Aug 12 07:42:03 PM PDT 24 4227680130 ps
T1371 /workspace/coverage/default/2.chip_sw_hmac_multistream.297416262 Aug 12 07:26:37 PM PDT 24 Aug 12 07:53:25 PM PDT 24 7414337880 ps
T1372 /workspace/coverage/default/0.rom_e2e_jtag_inject_dev.3379741155 Aug 12 07:11:34 PM PDT 24 Aug 12 07:50:45 PM PDT 24 26250717557 ps
T1373 /workspace/coverage/default/2.rom_e2e_smoke.3407036093 Aug 12 07:34:33 PM PDT 24 Aug 12 08:40:36 PM PDT 24 14577029448 ps
T1374 /workspace/coverage/default/2.chip_sw_lc_walkthrough_rma.668162748 Aug 12 07:24:13 PM PDT 24 Aug 12 08:51:14 PM PDT 24 48163024504 ps
T1375 /workspace/coverage/default/0.chip_sw_clkmgr_jitter_frequency.3704453335 Aug 12 07:09:15 PM PDT 24 Aug 12 07:16:25 PM PDT 24 3699611026 ps
T1376 /workspace/coverage/default/2.chip_sw_uart_tx_rx_alt_clk_freq.867882086 Aug 12 07:23:27 PM PDT 24 Aug 12 07:54:45 PM PDT 24 9056173898 ps
T1377 /workspace/coverage/default/1.rom_e2e_self_hash.2085071555 Aug 12 07:27:38 PM PDT 24 Aug 12 09:08:06 PM PDT 24 26402207870 ps
T1378 /workspace/coverage/default/2.chip_sw_lc_ctrl_volatile_raw_unlock.1328339447 Aug 12 07:24:59 PM PDT 24 Aug 12 07:26:33 PM PDT 24 2470889628 ps
T1379 /workspace/coverage/default/13.chip_sw_uart_rand_baudrate.1239607565 Aug 12 07:35:04 PM PDT 24 Aug 12 07:46:44 PM PDT 24 4753269710 ps
T1380 /workspace/coverage/default/1.chip_sw_aes_entropy.400744472 Aug 12 07:17:52 PM PDT 24 Aug 12 07:21:25 PM PDT 24 2810245000 ps
T269 /workspace/coverage/default/1.chip_sw_rstmgr_cpu_info.4171653278 Aug 12 07:13:54 PM PDT 24 Aug 12 07:24:07 PM PDT 24 6234461384 ps
T1381 /workspace/coverage/default/0.chip_sw_usbdev_vbus.1420624030 Aug 12 07:08:44 PM PDT 24 Aug 12 07:14:54 PM PDT 24 3481648728 ps
T1382 /workspace/coverage/default/2.chip_sw_keymgr_key_derivation_prod.1959203569 Aug 12 07:27:13 PM PDT 24 Aug 12 07:59:12 PM PDT 24 9759460904 ps
T1383 /workspace/coverage/default/1.chip_sw_edn_entropy_reqs.1870057338 Aug 12 07:16:03 PM PDT 24 Aug 12 07:39:29 PM PDT 24 6815261682 ps
T1384 /workspace/coverage/default/2.chip_sw_aon_timer_smoketest.2371848115 Aug 12 07:32:51 PM PDT 24 Aug 12 07:39:00 PM PDT 24 3119707670 ps
T1385 /workspace/coverage/default/0.rom_e2e_asm_init_dev.3700068249 Aug 12 07:15:15 PM PDT 24 Aug 12 08:17:11 PM PDT 24 15072799096 ps
T1386 /workspace/coverage/default/0.chip_sw_uart_tx_rx_idx1.284614861 Aug 12 07:10:21 PM PDT 24 Aug 12 07:22:43 PM PDT 24 4753393828 ps
T1387 /workspace/coverage/default/0.chip_sw_hmac_smoketest.2164602813 Aug 12 07:12:13 PM PDT 24 Aug 12 07:18:22 PM PDT 24 3092180816 ps
T1388 /workspace/coverage/default/0.chip_sw_i2c_host_tx_rx_idx1.3910513828 Aug 12 07:07:06 PM PDT 24 Aug 12 07:20:52 PM PDT 24 5769805640 ps
T812 /workspace/coverage/default/46.chip_sw_alert_handler_lpg_sleep_mode_alerts.426845132 Aug 12 07:38:01 PM PDT 24 Aug 12 07:44:29 PM PDT 24 4386208914 ps
T1389 /workspace/coverage/default/1.chip_sw_kmac_mode_kmac_jitter_en.3512695069 Aug 12 07:20:47 PM PDT 24 Aug 12 07:26:01 PM PDT 24 3386858981 ps
T159 /workspace/coverage/default/0.chip_sw_usbdev_setuprx.2651881589 Aug 12 07:07:22 PM PDT 24 Aug 12 07:15:32 PM PDT 24 4023933000 ps
T305 /workspace/coverage/default/1.chip_sw_rv_core_ibex_icache_invalidate.2148984447 Aug 12 07:21:12 PM PDT 24 Aug 12 07:24:45 PM PDT 24 2571235021 ps
T1390 /workspace/coverage/default/1.chip_sw_kmac_smoketest.1322723201 Aug 12 07:23:14 PM PDT 24 Aug 12 07:29:04 PM PDT 24 2376572448 ps
T1391 /workspace/coverage/default/0.chip_sw_sysrst_ctrl_reset.2521651991 Aug 12 07:09:10 PM PDT 24 Aug 12 07:40:21 PM PDT 24 22034899916 ps
T1392 /workspace/coverage/default/7.chip_sw_csrng_edn_concurrency.2247244093 Aug 12 07:33:20 PM PDT 24 Aug 12 08:49:18 PM PDT 24 20680413340 ps
T1393 /workspace/coverage/default/0.chip_sw_usb_ast_clk_calib.2663441444 Aug 12 07:07:54 PM PDT 24 Aug 12 07:12:50 PM PDT 24 3128204017 ps
T1394 /workspace/coverage/default/0.chip_sw_usbdev_dpi.81015872 Aug 12 07:10:01 PM PDT 24 Aug 12 07:59:17 PM PDT 24 11798617456 ps
T306 /workspace/coverage/default/0.chip_sw_rv_core_ibex_icache_invalidate.3752582919 Aug 12 07:12:14 PM PDT 24 Aug 12 07:15:59 PM PDT 24 2661455252 ps
T1395 /workspace/coverage/default/0.chip_sw_keymgr_key_derivation_jitter_en_reduced_freq.1957610832 Aug 12 07:11:36 PM PDT 24 Aug 12 07:49:07 PM PDT 24 12885796705 ps
T1396 /workspace/coverage/default/2.chip_sw_aes_enc.1129437138 Aug 12 07:27:08 PM PDT 24 Aug 12 07:31:23 PM PDT 24 2514500952 ps
T38 /workspace/coverage/default/1.chip_sw_spi_host_tx_rx.3358337367 Aug 12 07:15:57 PM PDT 24 Aug 12 07:21:16 PM PDT 24 3121782806 ps
T869 /workspace/coverage/default/43.chip_sw_alert_handler_lpg_sleep_mode_alerts.1852525247 Aug 12 07:37:37 PM PDT 24 Aug 12 07:45:33 PM PDT 24 3943667664 ps
T1397 /workspace/coverage/default/2.chip_sw_clkmgr_jitter_reduced_freq.2105313252 Aug 12 07:29:57 PM PDT 24 Aug 12 07:33:22 PM PDT 24 2718406217 ps
T1398 /workspace/coverage/default/53.chip_sw_all_escalation_resets.3682488570 Aug 12 07:39:36 PM PDT 24 Aug 12 07:52:16 PM PDT 24 5804495060 ps
T1399 /workspace/coverage/default/2.chip_sw_uart_rand_baudrate.2670490312 Aug 12 07:23:41 PM PDT 24 Aug 12 08:01:42 PM PDT 24 13694585244 ps
T1400 /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_bad_rma.3129622258 Aug 12 07:18:33 PM PDT 24 Aug 12 08:22:14 PM PDT 24 15214476212 ps
T333 /workspace/coverage/default/1.chip_plic_all_irqs_20.4042733154 Aug 12 07:19:13 PM PDT 24 Aug 12 07:32:15 PM PDT 24 5042246612 ps
T1401 /workspace/coverage/default/1.chip_sw_alert_handler_lpg_reset_toggle.4267077400 Aug 12 07:16:29 PM PDT 24 Aug 12 07:46:15 PM PDT 24 7670676634 ps
T1402 /workspace/coverage/default/1.chip_sw_csrng_kat_test.1444429645 Aug 12 07:15:19 PM PDT 24 Aug 12 07:19:06 PM PDT 24 2469923080 ps
T1403 /workspace/coverage/default/0.chip_sw_csrng_lc_hw_debug_en_test.2521689046 Aug 12 07:12:28 PM PDT 24 Aug 12 07:23:27 PM PDT 24 5150092212 ps
T169 /workspace/coverage/default/2.chip_plic_all_irqs_10.1800568370 Aug 12 07:32:21 PM PDT 24 Aug 12 07:41:29 PM PDT 24 3708427384 ps
T1404 /workspace/coverage/default/2.chip_sw_rv_dm_ndm_reset_req_when_cpu_halted.3810546864 Aug 12 07:28:49 PM PDT 24 Aug 12 07:36:11 PM PDT 24 4575621506 ps
T1405 /workspace/coverage/default/1.chip_sw_uart_tx_rx_idx2.2332140275 Aug 12 07:13:00 PM PDT 24 Aug 12 07:24:29 PM PDT 24 5077565038 ps
T1406 /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_good_prod_end.4067331575 Aug 12 07:16:03 PM PDT 24 Aug 12 08:22:19 PM PDT 24 15698001230 ps
T340 /workspace/coverage/default/1.chip_sw_rstmgr_alert_info.71347751 Aug 12 07:15:25 PM PDT 24 Aug 12 07:50:14 PM PDT 24 14719137500 ps
T1407 /workspace/coverage/default/1.chip_sw_i2c_host_tx_rx.2242070072 Aug 12 07:13:54 PM PDT 24 Aug 12 07:29:33 PM PDT 24 4942887094 ps
T1408 /workspace/coverage/default/2.chip_sw_pwrmgr_deep_sleep_por_reset.2198115474 Aug 12 07:27:15 PM PDT 24 Aug 12 07:38:28 PM PDT 24 7447959438 ps
T1409 /workspace/coverage/default/0.chip_sw_otp_ctrl_smoketest.1848731156 Aug 12 07:14:05 PM PDT 24 Aug 12 07:19:38 PM PDT 24 2815955628 ps
T1410 /workspace/coverage/default/0.chip_sw_flash_ctrl_access_jitter_en_reduced_freq.331025045 Aug 12 07:08:47 PM PDT 24 Aug 12 07:24:05 PM PDT 24 7233855851 ps
T1411 /workspace/coverage/default/2.chip_sw_uart_tx_rx_alt_clk_freq_low_speed.4087763150 Aug 12 07:23:46 PM PDT 24 Aug 12 07:33:08 PM PDT 24 4569586804 ps
T744 /workspace/coverage/default/0.chip_sw_edn_boot_mode.2540244259 Aug 12 07:09:07 PM PDT 24 Aug 12 07:20:00 PM PDT 24 2833339138 ps
T270 /workspace/coverage/default/23.chip_sw_all_escalation_resets.2171993644 Aug 12 07:35:08 PM PDT 24 Aug 12 07:44:54 PM PDT 24 4880042188 ps
T1412 /workspace/coverage/default/0.rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0.1897831329 Aug 12 07:17:22 PM PDT 24 Aug 12 08:03:40 PM PDT 24 11405665727 ps
T1413 /workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0.1447101509 Aug 12 07:17:31 PM PDT 24 Aug 12 08:51:49 PM PDT 24 17820211320 ps
T1414 /workspace/coverage/default/0.chip_sw_edn_auto_mode.2953382009 Aug 12 07:10:41 PM PDT 24 Aug 12 07:32:13 PM PDT 24 4841879780 ps
T1415 /workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_nothing_dev.2715893091 Aug 12 07:11:28 PM PDT 24 Aug 12 08:09:11 PM PDT 24 14447221304 ps
T1416 /workspace/coverage/default/2.chip_sw_alert_handler_reverse_ping_in_deep_sleep.3962616748 Aug 12 07:27:14 PM PDT 24 Aug 12 11:08:29 PM PDT 24 255356788230 ps
T1417 /workspace/coverage/default/0.chip_sw_sysrst_ctrl_in_irq.3326297015 Aug 12 07:08:34 PM PDT 24 Aug 12 07:21:35 PM PDT 24 5505408030 ps
T377 /workspace/coverage/default/2.chip_sw_flash_ctrl_ops.1643896881 Aug 12 07:26:43 PM PDT 24 Aug 12 07:37:55 PM PDT 24 4570272730 ps
T1418 /workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_fast_rma.3345033908 Aug 12 07:09:47 PM PDT 24 Aug 12 07:19:26 PM PDT 24 3998921556 ps
T1419 /workspace/coverage/default/44.chip_sw_all_escalation_resets.247171187 Aug 12 07:36:42 PM PDT 24 Aug 12 07:46:37 PM PDT 24 5616109728 ps
T1420 /workspace/coverage/default/1.chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq.3234306580 Aug 12 07:21:26 PM PDT 24 Aug 12 07:31:11 PM PDT 24 4290680615 ps
T1421 /workspace/coverage/default/1.chip_sw_pwrmgr_smoketest.135636995 Aug 12 07:21:40 PM PDT 24 Aug 12 07:31:01 PM PDT 24 6130195538 ps
T1422 /workspace/coverage/default/1.rom_e2e_asm_init_prod.1253872839 Aug 12 07:26:21 PM PDT 24 Aug 12 08:29:59 PM PDT 24 15776832335 ps
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