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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
96.20 95.54 94.20 95.34 95.05 97.53 99.52


Total test records in report: 2943
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T970 /workspace/coverage/default/1.chip_sw_clkmgr_jitter_frequency.2926017525 Aug 13 07:18:44 PM PDT 24 Aug 13 07:24:31 PM PDT 24 3410795516 ps
T148 /workspace/coverage/default/2.chip_sw_sensor_ctrl_status.2527395405 Aug 13 07:28:12 PM PDT 24 Aug 13 07:33:28 PM PDT 24 2827347844 ps
T119 /workspace/coverage/default/0.chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq.3135498550 Aug 13 07:11:51 PM PDT 24 Aug 13 07:21:12 PM PDT 24 4780006739 ps
T190 /workspace/coverage/default/0.chip_sw_flash_rma_unlocked.1912031896 Aug 13 07:13:53 PM PDT 24 Aug 13 08:31:22 PM PDT 24 43479315067 ps
T971 /workspace/coverage/default/1.chip_sw_hmac_enc_idle.1380637916 Aug 13 07:17:48 PM PDT 24 Aug 13 07:22:30 PM PDT 24 2632117750 ps
T972 /workspace/coverage/default/0.chip_sw_example_rom.2339520577 Aug 13 07:08:57 PM PDT 24 Aug 13 07:11:07 PM PDT 24 2809286824 ps
T69 /workspace/coverage/default/0.chip_sw_usbdev_pullup.1642289554 Aug 13 07:10:32 PM PDT 24 Aug 13 07:16:00 PM PDT 24 3129063940 ps
T124 /workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0.1635477154 Aug 13 07:28:44 PM PDT 24 Aug 13 07:38:41 PM PDT 24 3965683116 ps
T352 /workspace/coverage/default/0.chip_sw_flash_ctrl_ops_jitter_en.2536306144 Aug 13 07:09:04 PM PDT 24 Aug 13 07:18:39 PM PDT 24 4249531793 ps
T223 /workspace/coverage/default/70.chip_sw_alert_handler_lpg_sleep_mode_alerts.482492687 Aug 13 07:40:11 PM PDT 24 Aug 13 07:46:10 PM PDT 24 3010391202 ps
T973 /workspace/coverage/default/2.chip_sw_pwrmgr_wdog_reset.3205051557 Aug 13 07:27:55 PM PDT 24 Aug 13 07:36:54 PM PDT 24 5370133872 ps
T974 /workspace/coverage/default/1.chip_sw_kmac_mode_kmac_jitter_en.692099233 Aug 13 07:18:35 PM PDT 24 Aug 13 07:23:21 PM PDT 24 2666315619 ps
T24 /workspace/coverage/default/2.chip_sw_gpio_smoketest.1140938762 Aug 13 07:32:27 PM PDT 24 Aug 13 07:36:14 PM PDT 24 3192894223 ps
T22 /workspace/coverage/default/2.chip_sw_sysrst_ctrl_ec_rst_l.3902165265 Aug 13 07:25:45 PM PDT 24 Aug 13 08:15:43 PM PDT 24 20576051958 ps
T975 /workspace/coverage/default/0.chip_sw_flash_ctrl_access.1663098514 Aug 13 07:09:52 PM PDT 24 Aug 13 07:28:43 PM PDT 24 5759738548 ps
T181 /workspace/coverage/default/0.chip_sw_lc_ctrl_raw_to_scrap.1114096698 Aug 13 07:09:35 PM PDT 24 Aug 13 07:12:12 PM PDT 24 2538940949 ps
T976 /workspace/coverage/default/0.rom_e2e_asm_init_test_unlocked0.1218046398 Aug 13 07:18:36 PM PDT 24 Aug 13 08:08:55 PM PDT 24 11586264336 ps
T977 /workspace/coverage/default/2.chip_sw_pwrmgr_main_power_glitch_reset.1043088350 Aug 13 07:28:11 PM PDT 24 Aug 13 07:36:03 PM PDT 24 4723803624 ps
T324 /workspace/coverage/default/1.chip_sw_pwrmgr_random_sleep_all_reset_reqs.3826781218 Aug 13 07:17:07 PM PDT 24 Aug 13 07:46:55 PM PDT 24 20721425852 ps
T978 /workspace/coverage/default/1.chip_sw_flash_ctrl_access_jitter_en_reduced_freq.3894693932 Aug 13 07:22:19 PM PDT 24 Aug 13 07:39:39 PM PDT 24 7110325433 ps
T421 /workspace/coverage/default/0.chip_sw_usb_ast_clk_calib.1658167344 Aug 13 07:12:42 PM PDT 24 Aug 13 07:18:06 PM PDT 24 3168705863 ps
T58 /workspace/coverage/default/1.chip_sw_pwrmgr_deep_sleep_all_wake_ups.313843814 Aug 13 07:19:59 PM PDT 24 Aug 13 07:54:33 PM PDT 24 22201682392 ps
T788 /workspace/coverage/default/15.chip_sw_all_escalation_resets.1649706436 Aug 13 07:34:14 PM PDT 24 Aug 13 07:47:41 PM PDT 24 5976829456 ps
T373 /workspace/coverage/default/1.chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up.2186406926 Aug 13 07:20:08 PM PDT 24 Aug 13 07:27:11 PM PDT 24 5035377012 ps
T979 /workspace/coverage/default/1.chip_sw_csrng_edn_concurrency.2806487825 Aug 13 07:18:01 PM PDT 24 Aug 13 08:42:08 PM PDT 24 23506357090 ps
T420 /workspace/coverage/default/0.chip_sw_pwrmgr_usbdev_smoketest.3894125588 Aug 13 07:12:18 PM PDT 24 Aug 13 07:18:38 PM PDT 24 5140106300 ps
T980 /workspace/coverage/default/2.chip_sw_aon_timer_wdog_lc_escalate.861721257 Aug 13 07:26:49 PM PDT 24 Aug 13 07:37:31 PM PDT 24 5741655440 ps
T981 /workspace/coverage/default/2.chip_sw_pwrmgr_sysrst_ctrl_reset.1197486243 Aug 13 07:25:10 PM PDT 24 Aug 13 07:43:36 PM PDT 24 6906942776 ps
T376 /workspace/coverage/default/42.chip_sw_all_escalation_resets.4074531658 Aug 13 07:37:09 PM PDT 24 Aug 13 07:47:34 PM PDT 24 4597580158 ps
T381 /workspace/coverage/default/9.chip_sw_alert_handler_lpg_sleep_mode_alerts.4064309735 Aug 13 07:34:17 PM PDT 24 Aug 13 07:41:19 PM PDT 24 4472642964 ps
T382 /workspace/coverage/default/1.chip_sw_flash_ctrl_access_jitter_en.1440246831 Aug 13 07:14:46 PM PDT 24 Aug 13 07:32:47 PM PDT 24 5903342739 ps
T135 /workspace/coverage/default/1.chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup.2022832204 Aug 13 07:20:48 PM PDT 24 Aug 13 07:31:02 PM PDT 24 4842348544 ps
T162 /workspace/coverage/default/2.chip_sw_alert_handler_reverse_ping_in_deep_sleep.3998523109 Aug 13 07:28:04 PM PDT 24 Aug 13 11:04:46 PM PDT 24 256445869774 ps
T383 /workspace/coverage/default/0.chip_sw_csrng_smoketest.3280446484 Aug 13 07:11:39 PM PDT 24 Aug 13 07:14:45 PM PDT 24 2959456336 ps
T384 /workspace/coverage/default/97.chip_sw_all_escalation_resets.2591319193 Aug 13 07:41:51 PM PDT 24 Aug 13 07:51:35 PM PDT 24 4930295160 ps
T365 /workspace/coverage/default/1.chip_sw_uart_tx_rx_idx3.1986510818 Aug 13 07:12:26 PM PDT 24 Aug 13 07:22:59 PM PDT 24 4220027928 ps
T385 /workspace/coverage/default/1.chip_sw_otp_ctrl_lc_signals_prod.4143818630 Aug 13 07:15:23 PM PDT 24 Aug 13 07:36:59 PM PDT 24 7527436884 ps
T386 /workspace/coverage/default/0.chip_sw_aes_idle.1750582516 Aug 13 07:10:25 PM PDT 24 Aug 13 07:16:22 PM PDT 24 3143590400 ps
T281 /workspace/coverage/default/2.chip_sw_rom_ctrl_integrity_check.169395788 Aug 13 07:28:08 PM PDT 24 Aug 13 07:38:13 PM PDT 24 8509131855 ps
T982 /workspace/coverage/default/1.chip_sw_kmac_mode_kmac_jitter_en_reduced_freq.1643977934 Aug 13 07:21:07 PM PDT 24 Aug 13 07:26:05 PM PDT 24 3530767390 ps
T422 /workspace/coverage/default/1.chip_sw_kmac_app_rom.2624332644 Aug 13 07:17:49 PM PDT 24 Aug 13 07:20:32 PM PDT 24 2060648920 ps
T983 /workspace/coverage/default/1.chip_sw_aes_enc.3652087894 Aug 13 07:17:05 PM PDT 24 Aug 13 07:22:51 PM PDT 24 3399135680 ps
T64 /workspace/coverage/default/2.chip_tap_straps_rma.3269465680 Aug 13 07:29:13 PM PDT 24 Aug 13 07:34:55 PM PDT 24 3902582394 ps
T336 /workspace/coverage/default/0.chip_sw_uart_tx_rx_idx2.2604464167 Aug 13 07:10:42 PM PDT 24 Aug 13 07:22:34 PM PDT 24 3939554240 ps
T339 /workspace/coverage/default/19.chip_sw_uart_rand_baudrate.3580281725 Aug 13 07:35:18 PM PDT 24 Aug 13 07:59:49 PM PDT 24 8109426744 ps
T984 /workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_nothing_prod_end.3560517141 Aug 13 07:18:37 PM PDT 24 Aug 13 08:26:36 PM PDT 24 15233971320 ps
T186 /workspace/coverage/default/2.chip_sw_rv_core_ibex_icache_invalidate.277009350 Aug 13 07:28:59 PM PDT 24 Aug 13 07:32:25 PM PDT 24 2678214362 ps
T304 /workspace/coverage/default/0.chip_sw_lc_ctrl_volatile_raw_unlock.520596336 Aug 13 07:10:15 PM PDT 24 Aug 13 07:12:12 PM PDT 24 2513061555 ps
T305 /workspace/coverage/default/2.chip_sw_lc_walkthrough_prodend.4243150392 Aug 13 07:25:06 PM PDT 24 Aug 13 07:40:07 PM PDT 24 10577046100 ps
T241 /workspace/coverage/default/0.chip_sw_flash_init_reduced_freq.1988946607 Aug 13 07:11:55 PM PDT 24 Aug 13 07:53:34 PM PDT 24 21524222495 ps
T306 /workspace/coverage/default/2.chip_sw_kmac_entropy.2640414486 Aug 13 07:26:12 PM PDT 24 Aug 13 07:32:27 PM PDT 24 3806008164 ps
T307 /workspace/coverage/default/17.chip_sw_all_escalation_resets.3908945824 Aug 13 07:36:08 PM PDT 24 Aug 13 07:48:53 PM PDT 24 4980267814 ps
T308 /workspace/coverage/default/0.chip_sw_flash_ctrl_clock_freqs.1358570221 Aug 13 07:11:06 PM PDT 24 Aug 13 07:29:54 PM PDT 24 5067871893 ps
T309 /workspace/coverage/default/1.chip_sw_lc_walkthrough_prodend.3955902114 Aug 13 07:15:35 PM PDT 24 Aug 13 07:32:53 PM PDT 24 8781059228 ps
T310 /workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_bad_rma.2910400193 Aug 13 07:17:41 PM PDT 24 Aug 13 08:45:16 PM PDT 24 22129036296 ps
T311 /workspace/coverage/default/0.chip_sw_pwrmgr_main_power_glitch_reset.787901694 Aug 13 07:11:43 PM PDT 24 Aug 13 07:19:14 PM PDT 24 4168376500 ps
T789 /workspace/coverage/default/44.chip_sw_all_escalation_resets.1306601336 Aug 13 07:39:07 PM PDT 24 Aug 13 07:49:22 PM PDT 24 4808047042 ps
T985 /workspace/coverage/default/1.chip_sw_flash_ctrl_access.3939358003 Aug 13 07:16:13 PM PDT 24 Aug 13 07:31:47 PM PDT 24 5100863010 ps
T182 /workspace/coverage/default/2.chip_sw_lc_ctrl_rand_to_scrap.1863080145 Aug 13 07:25:23 PM PDT 24 Aug 13 07:29:59 PM PDT 24 4231384309 ps
T986 /workspace/coverage/default/2.chip_sw_aes_enc.107198388 Aug 13 07:27:24 PM PDT 24 Aug 13 07:31:24 PM PDT 24 2488458944 ps
T987 /workspace/coverage/default/1.chip_sw_kmac_idle.2113240739 Aug 13 07:19:13 PM PDT 24 Aug 13 07:23:06 PM PDT 24 2543534224 ps
T800 /workspace/coverage/default/95.chip_sw_all_escalation_resets.4149275417 Aug 13 07:41:25 PM PDT 24 Aug 13 07:51:55 PM PDT 24 4730242994 ps
T795 /workspace/coverage/default/74.chip_sw_alert_handler_lpg_sleep_mode_alerts.3346244624 Aug 13 07:40:23 PM PDT 24 Aug 13 07:47:36 PM PDT 24 3287143424 ps
T290 /workspace/coverage/default/1.chip_sw_otbn_mem_scramble.2447391163 Aug 13 07:14:58 PM PDT 24 Aug 13 07:23:54 PM PDT 24 4118519780 ps
T988 /workspace/coverage/default/4.chip_sw_aon_timer_sleep_wdog_sleep_pause.1040862007 Aug 13 07:31:47 PM PDT 24 Aug 13 07:41:01 PM PDT 24 7022051950 ps
T221 /workspace/coverage/default/28.chip_sw_all_escalation_resets.1663632446 Aug 13 07:38:49 PM PDT 24 Aug 13 07:48:03 PM PDT 24 5071674688 ps
T989 /workspace/coverage/default/2.chip_sw_aes_enc_jitter_en_reduced_freq.4054872197 Aug 13 07:32:17 PM PDT 24 Aug 13 07:37:58 PM PDT 24 2845595513 ps
T990 /workspace/coverage/default/2.chip_sw_example_flash.1581459024 Aug 13 07:21:54 PM PDT 24 Aug 13 07:25:57 PM PDT 24 3052317614 ps
T991 /workspace/coverage/default/0.chip_sw_otp_ctrl_lc_signals_test_unlocked0.1875653270 Aug 13 07:09:05 PM PDT 24 Aug 13 07:20:14 PM PDT 24 5151767394 ps
T992 /workspace/coverage/default/0.chip_sw_pwrmgr_b2b_sleep_reset_req.1160169906 Aug 13 07:16:57 PM PDT 24 Aug 13 07:55:50 PM PDT 24 21122654530 ps
T993 /workspace/coverage/default/1.chip_sw_clkmgr_off_aes_trans.4209642114 Aug 13 07:20:11 PM PDT 24 Aug 13 07:29:35 PM PDT 24 4247399340 ps
T994 /workspace/coverage/default/3.chip_sw_uart_tx_rx_alt_clk_freq_low_speed.4072188381 Aug 13 07:32:20 PM PDT 24 Aug 13 07:41:25 PM PDT 24 4042432634 ps
T65 /workspace/coverage/default/4.chip_tap_straps_testunlock0.4003642873 Aug 13 07:34:24 PM PDT 24 Aug 13 07:39:02 PM PDT 24 3439631037 ps
T995 /workspace/coverage/default/0.chip_sw_kmac_mode_cshake.3120819251 Aug 13 07:09:34 PM PDT 24 Aug 13 07:14:13 PM PDT 24 3622805102 ps
T794 /workspace/coverage/default/78.chip_sw_alert_handler_lpg_sleep_mode_alerts.3205207432 Aug 13 07:41:17 PM PDT 24 Aug 13 07:46:00 PM PDT 24 3545231490 ps
T996 /workspace/coverage/default/57.chip_sw_alert_handler_lpg_sleep_mode_alerts.1167913198 Aug 13 07:40:00 PM PDT 24 Aug 13 07:46:33 PM PDT 24 3632332084 ps
T997 /workspace/coverage/default/0.rom_e2e_self_hash.2942807354 Aug 13 07:22:45 PM PDT 24 Aug 13 09:12:14 PM PDT 24 26230287744 ps
T798 /workspace/coverage/default/77.chip_sw_all_escalation_resets.636349404 Aug 13 07:40:35 PM PDT 24 Aug 13 07:49:46 PM PDT 24 4386700760 ps
T998 /workspace/coverage/default/2.chip_sw_example_concurrency.4197275431 Aug 13 07:26:57 PM PDT 24 Aug 13 07:31:10 PM PDT 24 3100754214 ps
T187 /workspace/coverage/default/1.chip_sw_sram_ctrl_execution_main.3559983243 Aug 13 07:18:11 PM PDT 24 Aug 13 07:33:36 PM PDT 24 9422385159 ps
T75 /workspace/coverage/default/0.chip_jtag_mem_access.3705459394 Aug 13 07:02:58 PM PDT 24 Aug 13 07:30:58 PM PDT 24 13389976140 ps
T999 /workspace/coverage/default/1.rom_e2e_asm_init_test_unlocked0.1624991080 Aug 13 07:26:02 PM PDT 24 Aug 13 08:14:21 PM PDT 24 10911537469 ps
T1000 /workspace/coverage/default/12.chip_sw_lc_ctrl_transition.2367171384 Aug 13 07:34:02 PM PDT 24 Aug 13 07:47:47 PM PDT 24 11596716251 ps
T1001 /workspace/coverage/default/1.chip_sw_clkmgr_sleep_frequency.3492273517 Aug 13 07:19:42 PM PDT 24 Aug 13 07:30:01 PM PDT 24 4231937806 ps
T799 /workspace/coverage/default/74.chip_sw_all_escalation_resets.2131336027 Aug 13 07:39:49 PM PDT 24 Aug 13 07:51:04 PM PDT 24 4467050630 ps
T1002 /workspace/coverage/default/2.chip_sw_uart_tx_rx_idx2.1970327285 Aug 13 07:24:34 PM PDT 24 Aug 13 07:36:33 PM PDT 24 4253689964 ps
T1003 /workspace/coverage/default/0.rom_keymgr_functest.3846739878 Aug 13 07:10:53 PM PDT 24 Aug 13 07:18:04 PM PDT 24 4609362338 ps
T1004 /workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_slow_rma.3253800673 Aug 13 07:32:41 PM PDT 24 Aug 13 07:44:12 PM PDT 24 5089390636 ps
T1005 /workspace/coverage/default/0.chip_sw_alert_handler_escalation.4041577951 Aug 13 07:11:31 PM PDT 24 Aug 13 07:23:18 PM PDT 24 5560957596 ps
T322 /workspace/coverage/default/8.chip_sw_alert_handler_lpg_sleep_mode_alerts.2925217182 Aug 13 07:34:12 PM PDT 24 Aug 13 07:41:06 PM PDT 24 3070756352 ps
T1006 /workspace/coverage/default/0.chip_sw_clkmgr_jitter_frequency.455239240 Aug 13 07:13:08 PM PDT 24 Aug 13 07:20:59 PM PDT 24 3944260030 ps
T374 /workspace/coverage/default/0.chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up.3547244380 Aug 13 07:12:35 PM PDT 24 Aug 13 07:18:54 PM PDT 24 4878494238 ps
T237 /workspace/coverage/default/0.chip_sw_keymgr_sideload_otbn.568915840 Aug 13 07:11:20 PM PDT 24 Aug 13 08:21:58 PM PDT 24 16769054744 ps
T1007 /workspace/coverage/default/1.chip_sw_uart_tx_rx_alt_clk_freq.503927152 Aug 13 07:12:36 PM PDT 24 Aug 13 07:24:28 PM PDT 24 4461587348 ps
T366 /workspace/coverage/default/3.chip_sw_uart_tx_rx_idx3.2619886452 Aug 13 07:33:28 PM PDT 24 Aug 13 07:41:40 PM PDT 24 4837860828 ps
T724 /workspace/coverage/default/28.chip_sw_alert_handler_lpg_sleep_mode_alerts.3284459955 Aug 13 07:35:46 PM PDT 24 Aug 13 07:41:59 PM PDT 24 3269652680 ps
T86 /workspace/coverage/default/21.chip_sw_all_escalation_resets.1280022266 Aug 13 07:36:29 PM PDT 24 Aug 13 07:47:50 PM PDT 24 4336505088 ps
T1008 /workspace/coverage/default/2.chip_sw_pwrmgr_sleep_wake_5_bug.4088505549 Aug 13 07:30:19 PM PDT 24 Aug 13 07:40:06 PM PDT 24 5904310616 ps
T1009 /workspace/coverage/default/2.chip_sw_ast_clk_outputs.2412667517 Aug 13 07:33:07 PM PDT 24 Aug 13 07:50:39 PM PDT 24 8471312548 ps
T1010 /workspace/coverage/default/2.chip_sw_kmac_mode_kmac_jitter_en.3034438809 Aug 13 07:28:03 PM PDT 24 Aug 13 07:33:44 PM PDT 24 2936548368 ps
T805 /workspace/coverage/default/79.chip_sw_alert_handler_lpg_sleep_mode_alerts.3689502445 Aug 13 07:42:00 PM PDT 24 Aug 13 07:48:00 PM PDT 24 4068336758 ps
T258 /workspace/coverage/default/1.chip_sw_rv_timer_smoketest.934044074 Aug 13 07:22:46 PM PDT 24 Aug 13 07:26:52 PM PDT 24 2305874324 ps
T1011 /workspace/coverage/default/1.rom_e2e_static_critical.596156526 Aug 13 07:26:58 PM PDT 24 Aug 13 08:35:12 PM PDT 24 17568982444 ps
T10 /workspace/coverage/default/1.chip_sw_sleep_pin_mio_dio_val.399825295 Aug 13 07:14:50 PM PDT 24 Aug 13 07:19:33 PM PDT 24 2900174877 ps
T1012 /workspace/coverage/default/1.chip_sw_aon_timer_wdog_bite_reset.1076602893 Aug 13 07:18:44 PM PDT 24 Aug 13 07:34:12 PM PDT 24 8682225688 ps
T1013 /workspace/coverage/default/1.chip_sw_hmac_multistream.2942278301 Aug 13 07:17:32 PM PDT 24 Aug 13 07:46:09 PM PDT 24 6987738912 ps
T1014 /workspace/coverage/default/1.chip_sw_otp_ctrl_lc_signals_dev.2886220222 Aug 13 07:15:06 PM PDT 24 Aug 13 07:35:23 PM PDT 24 8457270834 ps
T1015 /workspace/coverage/default/2.chip_sw_uart_rand_baudrate.2249792964 Aug 13 07:23:07 PM PDT 24 Aug 13 07:32:48 PM PDT 24 3973040802 ps
T222 /workspace/coverage/default/2.chip_sw_alert_handler_lpg_reset_toggle.4201431286 Aug 13 07:28:51 PM PDT 24 Aug 13 07:56:15 PM PDT 24 7322875126 ps
T1016 /workspace/coverage/default/0.chip_sw_flash_crash_alert.510878610 Aug 13 07:12:36 PM PDT 24 Aug 13 07:26:23 PM PDT 24 5271511614 ps
T1017 /workspace/coverage/default/0.rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0.1543149323 Aug 13 07:21:23 PM PDT 24 Aug 13 08:11:51 PM PDT 24 10661470138 ps
T1018 /workspace/coverage/default/1.chip_sw_aes_enc_jitter_en_reduced_freq.2280545879 Aug 13 07:21:49 PM PDT 24 Aug 13 07:26:04 PM PDT 24 2770039015 ps
T1019 /workspace/coverage/default/2.rom_keymgr_functest.3266342343 Aug 13 07:31:07 PM PDT 24 Aug 13 07:38:59 PM PDT 24 4523381944 ps
T1020 /workspace/coverage/default/1.chip_sw_uart_tx_rx_idx2.4245166207 Aug 13 07:16:06 PM PDT 24 Aug 13 07:26:05 PM PDT 24 4515885224 ps
T796 /workspace/coverage/default/67.chip_sw_all_escalation_resets.1205670536 Aug 13 07:40:28 PM PDT 24 Aug 13 07:49:33 PM PDT 24 6441321522 ps
T1021 /workspace/coverage/default/0.chip_sw_rv_core_ibex_rnd.3330554334 Aug 13 07:11:28 PM PDT 24 Aug 13 07:29:54 PM PDT 24 5393228870 ps
T1022 /workspace/coverage/default/0.chip_sw_flash_ctrl_write_clear.3515269809 Aug 13 07:14:55 PM PDT 24 Aug 13 07:21:09 PM PDT 24 3199251678 ps
T1023 /workspace/coverage/default/1.chip_sw_alert_handler_escalation.2812274646 Aug 13 07:16:22 PM PDT 24 Aug 13 07:25:04 PM PDT 24 4888886206 ps
T23 /workspace/coverage/default/0.chip_sw_usbdev_pincfg.719634895 Aug 13 07:11:56 PM PDT 24 Aug 13 09:07:02 PM PDT 24 31507363216 ps
T1024 /workspace/coverage/default/5.chip_sw_csrng_edn_concurrency.1088309007 Aug 13 07:34:29 PM PDT 24 Aug 13 08:31:50 PM PDT 24 16997201800 ps
T47 /workspace/coverage/default/0.chip_sw_alert_test.3165483738 Aug 13 07:09:59 PM PDT 24 Aug 13 07:14:47 PM PDT 24 3169782200 ps
T1025 /workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0.969349058 Aug 13 07:18:47 PM PDT 24 Aug 13 07:30:29 PM PDT 24 3981752600 ps
T25 /workspace/coverage/default/2.chip_sw_gpio.3368522160 Aug 13 07:24:06 PM PDT 24 Aug 13 07:34:35 PM PDT 24 3876589268 ps
T786 /workspace/coverage/default/32.chip_sw_all_escalation_resets.1841777264 Aug 13 07:35:41 PM PDT 24 Aug 13 07:48:32 PM PDT 24 5286692648 ps
T1026 /workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0.1825248749 Aug 13 07:32:37 PM PDT 24 Aug 13 07:44:30 PM PDT 24 4116956900 ps
T156 /workspace/coverage/default/0.chip_sw_otbn_ecdsa_op_irq.3105168592 Aug 13 07:10:51 PM PDT 24 Aug 13 08:12:01 PM PDT 24 17783851436 ps
T1027 /workspace/coverage/default/0.chip_sw_hmac_oneshot.1320371491 Aug 13 07:11:25 PM PDT 24 Aug 13 07:18:02 PM PDT 24 3530891624 ps
T1028 /workspace/coverage/default/0.chip_sw_entropy_src_smoketest.2286668703 Aug 13 07:14:34 PM PDT 24 Aug 13 07:22:05 PM PDT 24 2916593432 ps
T1029 /workspace/coverage/default/2.chip_sw_clkmgr_sleep_frequency.2521909787 Aug 13 07:32:21 PM PDT 24 Aug 13 07:45:13 PM PDT 24 5157697820 ps
T1030 /workspace/coverage/default/4.chip_sw_lc_ctrl_transition.1295418833 Aug 13 07:32:42 PM PDT 24 Aug 13 07:49:49 PM PDT 24 9109061942 ps
T1031 /workspace/coverage/default/1.rom_e2e_keymgr_init_rom_ext_meas.2388944306 Aug 13 07:27:21 PM PDT 24 Aug 13 08:22:57 PM PDT 24 14984140550 ps
T120 /workspace/coverage/default/0.chip_sw_sram_ctrl_scrambled_access_jitter_en.2147299548 Aug 13 07:10:29 PM PDT 24 Aug 13 07:18:25 PM PDT 24 5365251409 ps
T1032 /workspace/coverage/default/1.rom_keymgr_functest.3663986329 Aug 13 07:22:04 PM PDT 24 Aug 13 07:34:20 PM PDT 24 4643950320 ps
T834 /workspace/coverage/default/56.chip_sw_all_escalation_resets.1008282019 Aug 13 07:42:09 PM PDT 24 Aug 13 07:51:19 PM PDT 24 5160308484 ps
T136 /workspace/coverage/default/0.chip_sw_sensor_ctrl_alert.2523229249 Aug 13 07:10:27 PM PDT 24 Aug 13 07:19:22 PM PDT 24 6209591296 ps
T242 /workspace/coverage/default/0.chip_sw_lc_walkthrough_dev.630080962 Aug 13 07:09:52 PM PDT 24 Aug 13 08:34:11 PM PDT 24 46603760665 ps
T353 /workspace/coverage/default/1.chip_sw_flash_ctrl_ops_jitter_en.1797879117 Aug 13 07:13:39 PM PDT 24 Aug 13 07:23:20 PM PDT 24 3932449843 ps
T1033 /workspace/coverage/default/0.chip_sw_aes_masking_off.2668602734 Aug 13 07:09:18 PM PDT 24 Aug 13 07:15:04 PM PDT 24 2726646602 ps
T1034 /workspace/coverage/default/12.chip_sw_uart_rand_baudrate.3354800401 Aug 13 07:35:20 PM PDT 24 Aug 13 07:59:49 PM PDT 24 8386771900 ps
T859 /workspace/coverage/default/50.chip_sw_alert_handler_lpg_sleep_mode_alerts.930673652 Aug 13 07:37:37 PM PDT 24 Aug 13 07:44:36 PM PDT 24 4312895140 ps
T1035 /workspace/coverage/default/2.chip_sw_kmac_app_rom.1297804926 Aug 13 07:29:07 PM PDT 24 Aug 13 07:34:24 PM PDT 24 2875159618 ps
T1036 /workspace/coverage/default/9.chip_sw_uart_rand_baudrate.4075188570 Aug 13 07:33:17 PM PDT 24 Aug 13 08:16:48 PM PDT 24 12920596804 ps
T797 /workspace/coverage/default/72.chip_sw_alert_handler_lpg_sleep_mode_alerts.2542106179 Aug 13 07:42:00 PM PDT 24 Aug 13 07:49:16 PM PDT 24 4032292870 ps
T1037 /workspace/coverage/default/9.chip_sw_csrng_edn_concurrency.1162880603 Aug 13 07:35:01 PM PDT 24 Aug 13 08:31:47 PM PDT 24 15599254600 ps
T1038 /workspace/coverage/default/2.chip_sw_flash_crash_alert.661535036 Aug 13 07:29:56 PM PDT 24 Aug 13 07:41:35 PM PDT 24 5255341918 ps
T80 /workspace/coverage/default/0.chip_sw_alert_handler_entropy.4264546333 Aug 13 07:12:47 PM PDT 24 Aug 13 07:20:22 PM PDT 24 4268574959 ps
T1039 /workspace/coverage/default/2.chip_sw_inject_scramble_seed.3576065741 Aug 13 07:26:55 PM PDT 24 Aug 13 10:54:14 PM PDT 24 63523167434 ps
T549 /workspace/coverage/default/0.chip_sw_pwrmgr_all_reset_reqs.2358839119 Aug 13 07:10:03 PM PDT 24 Aug 13 07:36:13 PM PDT 24 12007848767 ps
T793 /workspace/coverage/default/65.chip_sw_all_escalation_resets.1450165306 Aug 13 07:39:13 PM PDT 24 Aug 13 07:48:19 PM PDT 24 5594275784 ps
T1040 /workspace/coverage/default/2.rom_e2e_asm_init_rma.971536271 Aug 13 07:37:25 PM PDT 24 Aug 13 08:38:53 PM PDT 24 15091866803 ps
T1041 /workspace/coverage/default/2.chip_sw_flash_ctrl_write_clear.1484245253 Aug 13 07:31:11 PM PDT 24 Aug 13 07:37:57 PM PDT 24 3030761900 ps
T1042 /workspace/coverage/default/3.chip_sw_lc_ctrl_transition.644881728 Aug 13 07:32:30 PM PDT 24 Aug 13 07:40:31 PM PDT 24 6557076898 ps
T1043 /workspace/coverage/default/0.chip_sw_kmac_mode_kmac_jitter_en_reduced_freq.3539671539 Aug 13 07:15:16 PM PDT 24 Aug 13 07:21:23 PM PDT 24 2804075132 ps
T1044 /workspace/coverage/default/2.chip_sw_pwrmgr_smoketest.1537624552 Aug 13 07:32:12 PM PDT 24 Aug 13 07:37:30 PM PDT 24 5028580124 ps
T195 /workspace/coverage/default/1.chip_sw_csrng_fuse_en_sw_app_read_test.3634825570 Aug 13 07:18:31 PM PDT 24 Aug 13 07:25:11 PM PDT 24 3420925038 ps
T735 /workspace/coverage/default/2.chip_sw_rv_dm_access_after_escalation_reset.3380157806 Aug 13 07:29:30 PM PDT 24 Aug 13 07:40:29 PM PDT 24 6188592258 ps
T1045 /workspace/coverage/default/1.chip_sw_rv_dm_access_after_wakeup.1184650957 Aug 13 07:21:31 PM PDT 24 Aug 13 07:31:07 PM PDT 24 5558166260 ps
T97 /workspace/coverage/default/1.chip_sw_pwrmgr_normal_sleep_all_wake_ups.3302262098 Aug 13 07:20:27 PM PDT 24 Aug 13 07:27:31 PM PDT 24 7315868744 ps
T1046 /workspace/coverage/default/2.chip_sw_hmac_smoketest.1977624056 Aug 13 07:32:01 PM PDT 24 Aug 13 07:38:54 PM PDT 24 3117242872 ps
T98 /workspace/coverage/default/2.chip_sw_pwrmgr_random_sleep_all_wake_ups.2529281150 Aug 13 07:31:18 PM PDT 24 Aug 13 07:59:35 PM PDT 24 25710360760 ps
T149 /workspace/coverage/default/0.chip_sw_pwrmgr_full_aon_reset.1388438146 Aug 13 07:08:27 PM PDT 24 Aug 13 07:16:01 PM PDT 24 8089823072 ps
T99 /workspace/coverage/default/1.chip_sw_sleep_pin_wake.483945319 Aug 13 07:12:23 PM PDT 24 Aug 13 07:17:22 PM PDT 24 3673103544 ps
T100 /workspace/coverage/default/2.chip_sw_pwrmgr_normal_sleep_all_wake_ups.52834278 Aug 13 07:29:58 PM PDT 24 Aug 13 07:37:03 PM PDT 24 7580166984 ps
T784 /workspace/coverage/default/60.chip_sw_alert_handler_lpg_sleep_mode_alerts.1996418968 Aug 13 07:39:39 PM PDT 24 Aug 13 07:46:22 PM PDT 24 3816499320 ps
T857 /workspace/coverage/default/44.chip_sw_alert_handler_lpg_sleep_mode_alerts.1806818948 Aug 13 07:37:10 PM PDT 24 Aug 13 07:43:52 PM PDT 24 3367975404 ps
T1047 /workspace/coverage/default/2.chip_sw_otbn_ecdsa_op_irq_jitter_en.1520836538 Aug 13 07:28:05 PM PDT 24 Aug 13 08:23:44 PM PDT 24 18070518776 ps
T1048 /workspace/coverage/default/2.chip_sw_kmac_mode_kmac_jitter_en_reduced_freq.2626296294 Aug 13 07:31:14 PM PDT 24 Aug 13 07:36:06 PM PDT 24 3261425406 ps
T1049 /workspace/coverage/default/1.chip_sw_clkmgr_off_peri.343408047 Aug 13 07:18:01 PM PDT 24 Aug 13 07:39:05 PM PDT 24 8156460638 ps
T1050 /workspace/coverage/default/20.chip_sw_all_escalation_resets.232845337 Aug 13 07:34:52 PM PDT 24 Aug 13 07:45:16 PM PDT 24 4265562192 ps
T1051 /workspace/coverage/default/0.rom_e2e_asm_init_prod.746766819 Aug 13 07:20:25 PM PDT 24 Aug 13 08:41:34 PM PDT 24 15550492267 ps
T70 /workspace/coverage/default/0.chip_sw_usbdev_aon_pullup.3896349886 Aug 13 07:08:32 PM PDT 24 Aug 13 07:15:46 PM PDT 24 4342479300 ps
T1052 /workspace/coverage/default/4.chip_sw_uart_tx_rx_idx2.4177583722 Aug 13 07:31:31 PM PDT 24 Aug 13 07:45:13 PM PDT 24 4027743256 ps
T1053 /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_good_prod.962581447 Aug 13 07:18:50 PM PDT 24 Aug 13 08:27:59 PM PDT 24 15421756540 ps
T806 /workspace/coverage/default/38.chip_sw_alert_handler_lpg_sleep_mode_alerts.314517503 Aug 13 07:36:14 PM PDT 24 Aug 13 07:43:30 PM PDT 24 4051205808 ps
T1054 /workspace/coverage/default/2.chip_sw_otbn_ecdsa_op_irq.2135949657 Aug 13 07:27:33 PM PDT 24 Aug 13 08:16:33 PM PDT 24 16863198522 ps
T1055 /workspace/coverage/default/0.chip_sw_kmac_mode_kmac_jitter_en.3233563242 Aug 13 07:10:10 PM PDT 24 Aug 13 07:14:50 PM PDT 24 2934190520 ps
T853 /workspace/coverage/default/24.chip_sw_all_escalation_resets.75681393 Aug 13 07:34:59 PM PDT 24 Aug 13 07:45:01 PM PDT 24 5137793152 ps
T81 /workspace/coverage/default/1.chip_sw_alert_handler_lpg_sleep_mode_pings.668773397 Aug 13 07:18:18 PM PDT 24 Aug 13 07:40:42 PM PDT 24 12595202376 ps
T1056 /workspace/coverage/default/1.chip_sw_sysrst_ctrl_ec_rst_l.2849340199 Aug 13 07:16:01 PM PDT 24 Aug 13 08:08:05 PM PDT 24 20758933708 ps
T739 /workspace/coverage/default/4.chip_sw_all_escalation_resets.122935670 Aug 13 07:34:09 PM PDT 24 Aug 13 07:46:06 PM PDT 24 4530102040 ps
T291 /workspace/coverage/default/1.chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq.2432743505 Aug 13 07:21:29 PM PDT 24 Aug 13 07:32:50 PM PDT 24 5632260246 ps
T1057 /workspace/coverage/default/2.chip_sw_lc_walkthrough_testunlocks.3740549905 Aug 13 07:25:25 PM PDT 24 Aug 13 08:02:35 PM PDT 24 34864447064 ps
T1058 /workspace/coverage/default/1.chip_sw_lc_walkthrough_dev.526557971 Aug 13 07:14:38 PM PDT 24 Aug 13 08:41:19 PM PDT 24 48445359162 ps
T1059 /workspace/coverage/default/0.chip_sw_lc_ctrl_transition.826196953 Aug 13 07:09:03 PM PDT 24 Aug 13 07:17:13 PM PDT 24 4954438953 ps
T1060 /workspace/coverage/default/12.chip_sw_alert_handler_lpg_sleep_mode_alerts.2123834069 Aug 13 07:33:37 PM PDT 24 Aug 13 07:41:51 PM PDT 24 3887546396 ps
T1061 /workspace/coverage/default/0.chip_sw_coremark.1566844186 Aug 13 07:11:36 PM PDT 24 Aug 13 11:22:41 PM PDT 24 72257685352 ps
T738 /workspace/coverage/default/2.chip_sw_lc_ctrl_volatile_raw_unlock.2283343674 Aug 13 07:24:15 PM PDT 24 Aug 13 07:26:02 PM PDT 24 2535413894 ps
T101 /workspace/coverage/default/0.chip_sw_pwrmgr_normal_sleep_all_wake_ups.4171051529 Aug 13 07:14:31 PM PDT 24 Aug 13 07:22:12 PM PDT 24 7715936952 ps
T173 /workspace/coverage/default/2.chip_sw_lc_ctrl_program_error.514166388 Aug 13 07:29:59 PM PDT 24 Aug 13 07:38:37 PM PDT 24 4327056214 ps
T1062 /workspace/coverage/default/1.chip_sw_otbn_randomness.2502827731 Aug 13 07:16:47 PM PDT 24 Aug 13 07:33:39 PM PDT 24 5560280682 ps
T1063 /workspace/coverage/default/2.rom_e2e_shutdown_output.2166433628 Aug 13 07:35:48 PM PDT 24 Aug 13 08:25:57 PM PDT 24 25813720973 ps
T1064 /workspace/coverage/default/29.chip_sw_all_escalation_resets.102302494 Aug 13 07:36:44 PM PDT 24 Aug 13 07:48:28 PM PDT 24 5654937270 ps
T722 /workspace/coverage/default/0.chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq.3388433656 Aug 13 07:13:55 PM PDT 24 Aug 13 08:12:52 PM PDT 24 25573099326 ps
T803 /workspace/coverage/default/26.chip_sw_alert_handler_lpg_sleep_mode_alerts.3892839871 Aug 13 07:38:01 PM PDT 24 Aug 13 07:44:49 PM PDT 24 3561103512 ps
T1065 /workspace/coverage/default/2.rom_e2e_asm_init_prod.1892180366 Aug 13 07:37:35 PM PDT 24 Aug 13 08:38:00 PM PDT 24 15988388900 ps
T1066 /workspace/coverage/default/38.chip_sw_all_escalation_resets.1440032379 Aug 13 07:40:18 PM PDT 24 Aug 13 07:50:02 PM PDT 24 5833388164 ps
T1067 /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_bad_prod.76070130 Aug 13 07:18:14 PM PDT 24 Aug 13 08:24:06 PM PDT 24 16070511996 ps
T1068 /workspace/coverage/default/1.chip_sw_pwrmgr_deep_sleep_por_reset.199885069 Aug 13 07:17:20 PM PDT 24 Aug 13 07:31:22 PM PDT 24 9837060804 ps
T1069 /workspace/coverage/default/0.chip_sw_alert_handler_lpg_reset_toggle.2978609967 Aug 13 07:10:01 PM PDT 24 Aug 13 07:38:58 PM PDT 24 7881291528 ps
T292 /workspace/coverage/default/2.chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq.2688565999 Aug 13 07:29:50 PM PDT 24 Aug 13 07:40:16 PM PDT 24 4918250437 ps
T818 /workspace/coverage/default/66.chip_sw_all_escalation_resets.4177575432 Aug 13 07:39:28 PM PDT 24 Aug 13 07:51:12 PM PDT 24 5517004164 ps
T1070 /workspace/coverage/default/2.chip_sw_csrng_kat_test.3072464420 Aug 13 07:27:53 PM PDT 24 Aug 13 07:31:13 PM PDT 24 2937094820 ps
T217 /workspace/coverage/default/0.chip_sw_sysrst_ctrl_in_irq.836202391 Aug 13 07:10:56 PM PDT 24 Aug 13 07:20:26 PM PDT 24 4714479666 ps
T402 /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_bad_b_good_prod.4197272829 Aug 13 07:18:52 PM PDT 24 Aug 13 08:52:17 PM PDT 24 23976352456 ps
T1071 /workspace/coverage/default/0.chip_sw_otp_ctrl_dai_lock.3667940200 Aug 13 07:09:56 PM PDT 24 Aug 13 08:43:20 PM PDT 24 27460005204 ps
T814 /workspace/coverage/default/57.chip_sw_all_escalation_resets.1627847608 Aug 13 07:39:15 PM PDT 24 Aug 13 07:50:06 PM PDT 24 5234885360 ps
T1072 /workspace/coverage/default/0.chip_tap_straps_prod.2494144085 Aug 13 07:14:36 PM PDT 24 Aug 13 07:16:57 PM PDT 24 2436698014 ps
T792 /workspace/coverage/default/3.chip_sw_alert_handler_lpg_sleep_mode_alerts.3451782364 Aug 13 07:31:51 PM PDT 24 Aug 13 07:39:56 PM PDT 24 4350681600 ps
T1073 /workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0.2681057385 Aug 13 07:20:07 PM PDT 24 Aug 13 08:47:53 PM PDT 24 18040822033 ps
T1074 /workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_slow_dev.1278205055 Aug 13 07:12:43 PM PDT 24 Aug 13 07:26:38 PM PDT 24 4748181406 ps
T1075 /workspace/coverage/default/0.chip_sw_edn_kat.2790792713 Aug 13 07:10:59 PM PDT 24 Aug 13 07:22:36 PM PDT 24 3181943560 ps
T1076 /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_good_test_unlocked0.854495801 Aug 13 07:17:12 PM PDT 24 Aug 13 08:02:38 PM PDT 24 11344489476 ps
T1077 /workspace/coverage/default/0.chip_sw_otp_ctrl_lc_signals_rma.939520753 Aug 13 07:13:04 PM PDT 24 Aug 13 07:42:00 PM PDT 24 8626870300 ps
T1078 /workspace/coverage/default/0.chip_sw_otp_ctrl_lc_signals_prod.4112545995 Aug 13 07:11:40 PM PDT 24 Aug 13 07:36:58 PM PDT 24 7584674588 ps
T1079 /workspace/coverage/default/0.chip_sw_aes_enc.81592331 Aug 13 07:08:42 PM PDT 24 Aug 13 07:12:57 PM PDT 24 2778699080 ps
T1080 /workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_fast_rma.2969114372 Aug 13 07:30:40 PM PDT 24 Aug 13 07:42:19 PM PDT 24 4060440658 ps
T1081 /workspace/coverage/default/2.chip_sw_kmac_mode_cshake.519116313 Aug 13 07:28:42 PM PDT 24 Aug 13 07:32:31 PM PDT 24 3032508752 ps
T1082 /workspace/coverage/default/2.chip_sw_hmac_multistream.1862287623 Aug 13 07:27:56 PM PDT 24 Aug 13 07:55:57 PM PDT 24 6924105320 ps
T1083 /workspace/coverage/default/1.chip_sw_keymgr_key_derivation.1556310472 Aug 13 07:16:01 PM PDT 24 Aug 13 07:33:05 PM PDT 24 6054622390 ps
T811 /workspace/coverage/default/10.chip_sw_alert_handler_lpg_sleep_mode_alerts.126832265 Aug 13 07:34:29 PM PDT 24 Aug 13 07:41:12 PM PDT 24 3168353128 ps
T822 /workspace/coverage/default/4.chip_sw_alert_handler_lpg_sleep_mode_alerts.884858286 Aug 13 07:35:28 PM PDT 24 Aug 13 07:44:26 PM PDT 24 4547557400 ps
T1084 /workspace/coverage/default/1.chip_sw_rstmgr_sw_req.4207519532 Aug 13 07:17:16 PM PDT 24 Aug 13 07:22:05 PM PDT 24 3323935160 ps
T259 /workspace/coverage/default/2.chip_sw_rv_timer_irq.2121585355 Aug 13 07:25:18 PM PDT 24 Aug 13 07:28:44 PM PDT 24 2298923460 ps
T1085 /workspace/coverage/default/1.chip_sw_pwrmgr_sysrst_ctrl_reset.2868162038 Aug 13 07:15:15 PM PDT 24 Aug 13 07:32:50 PM PDT 24 5709869730 ps
T1086 /workspace/coverage/default/2.chip_sw_sleep_sram_ret_contents_no_scramble.468377999 Aug 13 07:29:03 PM PDT 24 Aug 13 07:39:57 PM PDT 24 6556374478 ps
T1087 /workspace/coverage/default/2.chip_sw_pwrmgr_b2b_sleep_reset_req.1947660678 Aug 13 07:29:21 PM PDT 24 Aug 13 07:58:05 PM PDT 24 25946600605 ps
T1088 /workspace/coverage/default/1.chip_sw_csrng_smoketest.1039063997 Aug 13 07:21:40 PM PDT 24 Aug 13 07:26:31 PM PDT 24 2898884976 ps
T263 /workspace/coverage/default/0.rom_e2e_jtag_debug_test_unlocked0.3490218186 Aug 13 07:11:56 PM PDT 24 Aug 13 07:45:14 PM PDT 24 11291066626 ps
T370 /workspace/coverage/default/2.chip_sw_flash_ctrl_ops_jitter_en.4027334294 Aug 13 07:24:35 PM PDT 24 Aug 13 07:37:30 PM PDT 24 4260012696 ps
T283 /workspace/coverage/default/0.chip_sw_data_integrity_escalation.670696592 Aug 13 07:09:24 PM PDT 24 Aug 13 07:21:41 PM PDT 24 5561391400 ps
T1089 /workspace/coverage/default/3.chip_tap_straps_prod.1570233976 Aug 13 07:31:50 PM PDT 24 Aug 13 07:49:51 PM PDT 24 8914323372 ps
T293 /workspace/coverage/default/1.chip_sw_sram_ctrl_scrambled_access_jitter_en.2799179538 Aug 13 07:18:08 PM PDT 24 Aug 13 07:29:12 PM PDT 24 5653374454 ps
T1090 /workspace/coverage/default/19.chip_sw_all_escalation_resets.243679470 Aug 13 07:35:22 PM PDT 24 Aug 13 07:46:22 PM PDT 24 5244248608 ps
T1091 /workspace/coverage/default/0.rom_e2e_asm_init_dev.3636813418 Aug 13 07:16:46 PM PDT 24 Aug 13 08:19:51 PM PDT 24 15344054008 ps
T847 /workspace/coverage/default/36.chip_sw_alert_handler_lpg_sleep_mode_alerts.1353844681 Aug 13 07:38:55 PM PDT 24 Aug 13 07:45:37 PM PDT 24 4253530630 ps
T1092 /workspace/coverage/default/4.chip_sw_uart_tx_rx_alt_clk_freq.1734574489 Aug 13 07:33:44 PM PDT 24 Aug 13 07:42:50 PM PDT 24 4330742818 ps
T1093 /workspace/coverage/default/0.rom_e2e_keymgr_init_rom_ext_invalid_meas.182627269 Aug 13 07:19:17 PM PDT 24 Aug 13 08:32:04 PM PDT 24 14823320040 ps
T1094 /workspace/coverage/default/49.chip_sw_all_escalation_resets.540616474 Aug 13 07:37:11 PM PDT 24 Aug 13 07:45:37 PM PDT 24 5614686532 ps
T1095 /workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0.3522127182 Aug 13 07:12:01 PM PDT 24 Aug 13 07:24:08 PM PDT 24 3976938134 ps
T1096 /workspace/coverage/default/0.chip_sw_flash_ctrl_mem_protection.3636850547 Aug 13 07:12:49 PM PDT 24 Aug 13 07:33:56 PM PDT 24 5322981078 ps
T264 /workspace/coverage/default/0.rom_e2e_jtag_debug_dev.859599153 Aug 13 07:12:54 PM PDT 24 Aug 13 07:57:48 PM PDT 24 12306667796 ps
T1097 /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_bad_prod_end.331851546 Aug 13 07:21:17 PM PDT 24 Aug 13 08:39:35 PM PDT 24 15450897924 ps
T1098 /workspace/coverage/default/1.chip_sw_flash_crash_alert.3321504512 Aug 13 07:19:13 PM PDT 24 Aug 13 07:32:30 PM PDT 24 6323239752 ps
T348 /workspace/coverage/default/1.chip_sw_flash_ctrl_ops.824866489 Aug 13 07:13:50 PM PDT 24 Aug 13 07:25:20 PM PDT 24 4696821984 ps
T1099 /workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_lc.2898088494 Aug 13 07:32:08 PM PDT 24 Aug 13 07:51:24 PM PDT 24 9837332853 ps
T349 /workspace/coverage/default/1.chip_sw_flash_ctrl_ops_jitter_en_reduced_freq.73577725 Aug 13 07:20:37 PM PDT 24 Aug 13 07:31:51 PM PDT 24 4958598904 ps
T1100 /workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0.3123727500 Aug 13 07:20:08 PM PDT 24 Aug 13 07:30:50 PM PDT 24 4540856862 ps
T813 /workspace/coverage/default/6.chip_sw_all_escalation_resets.3058486102 Aug 13 07:33:23 PM PDT 24 Aug 13 07:46:33 PM PDT 24 5740774936 ps
T1101 /workspace/coverage/default/1.chip_sw_pwrmgr_sleep_power_glitch_reset.814134145 Aug 13 07:15:33 PM PDT 24 Aug 13 07:23:08 PM PDT 24 4746551960 ps
T1102 /workspace/coverage/default/0.chip_sw_pwrmgr_smoketest.4179892753 Aug 13 07:13:36 PM PDT 24 Aug 13 07:20:49 PM PDT 24 4827049896 ps
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