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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
96.20 95.54 94.20 95.34 95.05 97.53 99.52


Total test records in report: 2943
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T809 /workspace/coverage/default/22.chip_sw_alert_handler_lpg_sleep_mode_alerts.2521211754 Aug 13 07:36:49 PM PDT 24 Aug 13 07:43:13 PM PDT 24 3793597940 ps
T461 /workspace/coverage/default/2.chip_sw_alert_handler_lpg_clkoff.14882696 Aug 13 07:26:59 PM PDT 24 Aug 13 08:00:49 PM PDT 24 9131411056 ps
T1103 /workspace/coverage/default/0.chip_sw_edn_entropy_reqs_jitter.2597285872 Aug 13 07:12:28 PM PDT 24 Aug 13 07:28:38 PM PDT 24 7680520951 ps
T1104 /workspace/coverage/default/1.rom_e2e_asm_init_prod_end.3445881362 Aug 13 07:26:53 PM PDT 24 Aug 13 08:20:26 PM PDT 24 15029696319 ps
T1105 /workspace/coverage/default/4.chip_sw_uart_tx_rx.1583445177 Aug 13 07:35:19 PM PDT 24 Aug 13 07:44:59 PM PDT 24 4848435800 ps
T170 /workspace/coverage/default/0.chip_sw_all_escalation_resets.2032375134 Aug 13 07:07:53 PM PDT 24 Aug 13 07:16:45 PM PDT 24 5625990748 ps
T1106 /workspace/coverage/default/0.rom_e2e_smoke.1085143252 Aug 13 07:16:20 PM PDT 24 Aug 13 08:22:57 PM PDT 24 14459574488 ps
T1107 /workspace/coverage/default/2.chip_sw_uart_tx_rx_alt_clk_freq.1656846303 Aug 13 07:25:23 PM PDT 24 Aug 13 07:57:57 PM PDT 24 8625359956 ps
T340 /workspace/coverage/default/0.chip_sw_uart_tx_rx_alt_clk_freq_low_speed.807034353 Aug 13 07:09:45 PM PDT 24 Aug 13 07:18:05 PM PDT 24 4761345949 ps
T1108 /workspace/coverage/default/1.chip_sw_pwrmgr_main_power_glitch_reset.1335546820 Aug 13 07:17:09 PM PDT 24 Aug 13 07:22:35 PM PDT 24 4321641288 ps
T50 /workspace/coverage/default/1.chip_sw_sleep_pin_retention.988068520 Aug 13 07:14:39 PM PDT 24 Aug 13 07:21:01 PM PDT 24 4277106460 ps
T26 /workspace/coverage/default/1.chip_sw_gpio.2308547093 Aug 13 07:15:09 PM PDT 24 Aug 13 07:24:25 PM PDT 24 4323560184 ps
T171 /workspace/coverage/default/0.chip_sw_otp_ctrl_escalation.1864554285 Aug 13 07:16:44 PM PDT 24 Aug 13 07:27:04 PM PDT 24 5749379538 ps
T338 /workspace/coverage/default/1.chip_sw_i2c_host_tx_rx_idx1.1334276865 Aug 13 07:15:40 PM PDT 24 Aug 13 07:27:50 PM PDT 24 4605758278 ps
T206 /workspace/coverage/default/1.chip_sw_spi_device_pass_through.572832665 Aug 13 07:12:59 PM PDT 24 Aug 13 07:22:45 PM PDT 24 6858531437 ps
T830 /workspace/coverage/default/77.chip_sw_alert_handler_lpg_sleep_mode_alerts.728227777 Aug 13 07:40:24 PM PDT 24 Aug 13 07:44:49 PM PDT 24 4010801016 ps
T1109 /workspace/coverage/default/2.chip_sw_lc_ctrl_transition.3388489303 Aug 13 07:24:59 PM PDT 24 Aug 13 07:37:26 PM PDT 24 6853970588 ps
T1110 /workspace/coverage/default/1.chip_sw_alert_handler_lpg_clkoff.1384882732 Aug 13 07:18:59 PM PDT 24 Aug 13 07:55:51 PM PDT 24 7967867768 ps
T1111 /workspace/coverage/default/2.chip_sw_alert_handler_ping_ok.2744262134 Aug 13 07:27:59 PM PDT 24 Aug 13 07:50:08 PM PDT 24 8213130532 ps
T423 /workspace/coverage/default/91.chip_sw_all_escalation_resets.3074566083 Aug 13 07:42:06 PM PDT 24 Aug 13 07:51:20 PM PDT 24 4911115090 ps
T1112 /workspace/coverage/default/80.chip_sw_alert_handler_lpg_sleep_mode_alerts.3787916577 Aug 13 07:40:16 PM PDT 24 Aug 13 07:47:25 PM PDT 24 4262674568 ps
T1113 /workspace/coverage/default/13.chip_sw_uart_rand_baudrate.1384952444 Aug 13 07:35:39 PM PDT 24 Aug 13 07:56:38 PM PDT 24 8802965768 ps
T1114 /workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_fast_rma.1753085340 Aug 13 07:22:45 PM PDT 24 Aug 13 07:34:56 PM PDT 24 4629625736 ps
T332 /workspace/coverage/default/2.chip_sw_rstmgr_alert_info.2542062032 Aug 13 07:28:08 PM PDT 24 Aug 13 07:53:11 PM PDT 24 10361534646 ps
T207 /workspace/coverage/default/0.chip_sw_power_virus.3639263427 Aug 13 07:17:17 PM PDT 24 Aug 13 07:43:57 PM PDT 24 5542764328 ps
T1115 /workspace/coverage/default/2.chip_sw_clkmgr_jitter_reduced_freq.2618064420 Aug 13 07:30:49 PM PDT 24 Aug 13 07:33:55 PM PDT 24 2551816738 ps
T377 /workspace/coverage/default/85.chip_sw_alert_handler_lpg_sleep_mode_alerts.2794404571 Aug 13 07:40:46 PM PDT 24 Aug 13 07:47:29 PM PDT 24 3208527980 ps
T51 /workspace/coverage/default/2.chip_sw_sleep_pin_retention.4117021654 Aug 13 07:22:49 PM PDT 24 Aug 13 07:27:46 PM PDT 24 3021992860 ps
T294 /workspace/coverage/default/0.chip_sw_sram_ctrl_scrambled_access.3658349115 Aug 13 07:10:51 PM PDT 24 Aug 13 07:21:29 PM PDT 24 5897314732 ps
T1116 /workspace/coverage/default/2.rom_e2e_asm_init_test_unlocked0.553221360 Aug 13 07:36:40 PM PDT 24 Aug 13 08:19:35 PM PDT 24 11777531372 ps
T342 /workspace/coverage/default/2.chip_sw_i2c_host_tx_rx.3232900580 Aug 13 07:23:22 PM PDT 24 Aug 13 07:38:21 PM PDT 24 4618616952 ps
T326 /workspace/coverage/default/2.chip_plic_all_irqs_0.3469324648 Aug 13 07:31:24 PM PDT 24 Aug 13 07:47:34 PM PDT 24 6825311784 ps
T265 /workspace/coverage/default/0.rom_e2e_jtag_inject_rma.2112163891 Aug 13 07:14:44 PM PDT 24 Aug 13 07:50:38 PM PDT 24 24767927271 ps
T350 /workspace/coverage/default/2.chip_sw_flash_ctrl_ops_jitter_en_reduced_freq.1890527332 Aug 13 07:29:49 PM PDT 24 Aug 13 07:40:09 PM PDT 24 4618222328 ps
T835 /workspace/coverage/default/2.chip_sw_alert_handler_lpg_sleep_mode_alerts.472157180 Aug 13 07:27:06 PM PDT 24 Aug 13 07:33:15 PM PDT 24 3670593700 ps
T1117 /workspace/coverage/default/1.chip_tap_straps_prod.1516759051 Aug 13 07:18:37 PM PDT 24 Aug 13 07:20:46 PM PDT 24 3177683535 ps
T378 /workspace/coverage/default/62.chip_sw_alert_handler_lpg_sleep_mode_alerts.4285126430 Aug 13 07:40:28 PM PDT 24 Aug 13 07:46:20 PM PDT 24 3331085180 ps
T1118 /workspace/coverage/default/2.chip_sw_rv_timer_smoketest.2270935699 Aug 13 07:31:29 PM PDT 24 Aug 13 07:35:47 PM PDT 24 2805597220 ps
T823 /workspace/coverage/default/72.chip_sw_all_escalation_resets.2534200996 Aug 13 07:39:34 PM PDT 24 Aug 13 07:50:28 PM PDT 24 5414119972 ps
T747 /workspace/coverage/default/1.chip_sw_plic_sw_irq.3490980742 Aug 13 07:18:26 PM PDT 24 Aug 13 07:22:40 PM PDT 24 2416423896 ps
T1119 /workspace/coverage/default/1.chip_sw_gpio_smoketest.3239528946 Aug 13 07:22:35 PM PDT 24 Aug 13 07:27:10 PM PDT 24 3401409497 ps
T1120 /workspace/coverage/default/2.chip_sw_flash_ctrl_ops.2574315741 Aug 13 07:26:07 PM PDT 24 Aug 13 07:38:43 PM PDT 24 4389119922 ps
T1121 /workspace/coverage/default/1.chip_sw_hmac_enc.2273169699 Aug 13 07:15:40 PM PDT 24 Aug 13 07:20:46 PM PDT 24 3191418200 ps
T1122 /workspace/coverage/default/2.chip_sw_aes_entropy.3334850223 Aug 13 07:30:33 PM PDT 24 Aug 13 07:35:02 PM PDT 24 2960243958 ps
T810 /workspace/coverage/default/23.chip_sw_all_escalation_resets.846073740 Aug 13 07:36:58 PM PDT 24 Aug 13 07:47:06 PM PDT 24 4993367852 ps
T361 /workspace/coverage/default/0.chip_sw_adc_ctrl_sleep_debug_cable_wakeup.2942963076 Aug 13 07:13:08 PM PDT 24 Aug 13 07:23:52 PM PDT 24 18143013864 ps
T1123 /workspace/coverage/default/1.chip_sw_lc_walkthrough_testunlocks.1847070034 Aug 13 07:15:36 PM PDT 24 Aug 13 07:47:36 PM PDT 24 20774915201 ps
T333 /workspace/coverage/default/0.chip_sw_rstmgr_alert_info.1720002093 Aug 13 07:08:35 PM PDT 24 Aug 13 07:35:22 PM PDT 24 13111930336 ps
T1124 /workspace/coverage/default/2.chip_sw_uart_smoketest.1390180454 Aug 13 07:31:47 PM PDT 24 Aug 13 07:37:33 PM PDT 24 2557557376 ps
T1125 /workspace/coverage/default/0.chip_sw_usbdev_dpi.4285688475 Aug 13 07:08:36 PM PDT 24 Aug 13 08:01:46 PM PDT 24 11813533162 ps
T785 /workspace/coverage/default/37.chip_sw_alert_handler_lpg_sleep_mode_alerts.2121900281 Aug 13 07:37:38 PM PDT 24 Aug 13 07:44:12 PM PDT 24 3574591560 ps
T1126 /workspace/coverage/default/0.chip_sw_clkmgr_sleep_frequency.2639489797 Aug 13 07:13:07 PM PDT 24 Aug 13 07:25:24 PM PDT 24 5008953504 ps
T1127 /workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_lc.4224198855 Aug 13 07:13:15 PM PDT 24 Aug 13 07:29:19 PM PDT 24 9979204429 ps
T1128 /workspace/coverage/default/1.chip_sw_pwrmgr_usb_clk_disabled_when_active.1350188843 Aug 13 07:16:17 PM PDT 24 Aug 13 07:24:13 PM PDT 24 4707787074 ps
T1129 /workspace/coverage/default/0.chip_sw_kmac_idle.3114571442 Aug 13 07:10:41 PM PDT 24 Aug 13 07:14:59 PM PDT 24 2581177376 ps
T1130 /workspace/coverage/default/0.rom_e2e_asm_init_rma.4259014027 Aug 13 07:17:51 PM PDT 24 Aug 13 08:21:37 PM PDT 24 14422536540 ps
T778 /workspace/coverage/default/56.chip_sw_alert_handler_lpg_sleep_mode_alerts.2626343163 Aug 13 07:39:21 PM PDT 24 Aug 13 07:47:07 PM PDT 24 3391334560 ps
T844 /workspace/coverage/default/75.chip_sw_all_escalation_resets.2528461864 Aug 13 07:40:03 PM PDT 24 Aug 13 07:49:44 PM PDT 24 5232951204 ps
T243 /workspace/coverage/default/1.chip_sw_lc_walkthrough_prod.683976735 Aug 13 07:15:37 PM PDT 24 Aug 13 08:47:52 PM PDT 24 47452731520 ps
T836 /workspace/coverage/default/25.chip_sw_all_escalation_resets.1917516314 Aug 13 07:38:07 PM PDT 24 Aug 13 07:45:54 PM PDT 24 4192171356 ps
T27 /workspace/coverage/default/0.chip_sw_gpio.2740689998 Aug 13 07:10:13 PM PDT 24 Aug 13 07:17:21 PM PDT 24 4057674252 ps
T783 /workspace/coverage/default/90.chip_sw_all_escalation_resets.2399543868 Aug 13 07:41:59 PM PDT 24 Aug 13 07:50:42 PM PDT 24 5840315600 ps
T1131 /workspace/coverage/default/0.chip_sw_flash_ctrl_access_jitter_en_reduced_freq.4250563388 Aug 13 07:14:36 PM PDT 24 Aug 13 07:34:40 PM PDT 24 7107148330 ps
T1132 /workspace/coverage/default/1.chip_sw_pwrmgr_sleep_wake_5_bug.2271641223 Aug 13 07:23:07 PM PDT 24 Aug 13 07:32:37 PM PDT 24 6640679984 ps
T1133 /workspace/coverage/default/4.chip_sw_uart_tx_rx_idx3.4143976143 Aug 13 07:32:50 PM PDT 24 Aug 13 07:44:26 PM PDT 24 4505553404 ps
T1134 /workspace/coverage/default/4.chip_tap_straps_prod.352586742 Aug 13 07:34:28 PM PDT 24 Aug 13 07:48:40 PM PDT 24 9849289380 ps
T1135 /workspace/coverage/default/17.chip_sw_uart_rand_baudrate.3115877430 Aug 13 07:36:15 PM PDT 24 Aug 13 07:45:11 PM PDT 24 3597189500 ps
T838 /workspace/coverage/default/52.chip_sw_all_escalation_resets.1984410290 Aug 13 07:40:31 PM PDT 24 Aug 13 07:48:37 PM PDT 24 4121768880 ps
T446 /workspace/coverage/default/20.chip_sw_alert_handler_lpg_sleep_mode_alerts.3992299888 Aug 13 07:36:49 PM PDT 24 Aug 13 07:43:15 PM PDT 24 3118621050 ps
T448 /workspace/coverage/default/0.chip_sw_keymgr_key_derivation_jitter_en.3449042425 Aug 13 07:12:43 PM PDT 24 Aug 13 07:36:12 PM PDT 24 9292006373 ps
T449 /workspace/coverage/default/1.chip_sw_pwrmgr_smoketest.1737207160 Aug 13 07:26:41 PM PDT 24 Aug 13 07:36:13 PM PDT 24 5888119558 ps
T244 /workspace/coverage/default/0.chip_sw_lc_walkthrough_rma.3787615670 Aug 13 07:09:15 PM PDT 24 Aug 13 08:43:35 PM PDT 24 46444846487 ps
T450 /workspace/coverage/default/33.chip_sw_alert_handler_lpg_sleep_mode_alerts.1991529525 Aug 13 07:37:00 PM PDT 24 Aug 13 07:46:14 PM PDT 24 3837476276 ps
T451 /workspace/coverage/default/1.chip_sw_example_flash.1501143058 Aug 13 07:15:53 PM PDT 24 Aug 13 07:20:53 PM PDT 24 2864784184 ps
T110 /workspace/coverage/default/1.chip_sw_pwrmgr_random_sleep_all_wake_ups.2918575601 Aug 13 07:19:15 PM PDT 24 Aug 13 07:43:29 PM PDT 24 21802718822 ps
T334 /workspace/coverage/default/2.chip_sw_entropy_src_csrng.2898807296 Aug 13 07:28:11 PM PDT 24 Aug 13 07:55:27 PM PDT 24 7944550936 ps
T452 /workspace/coverage/default/0.chip_tap_straps_dev.1017871518 Aug 13 07:10:31 PM PDT 24 Aug 13 07:45:12 PM PDT 24 16649258255 ps
T453 /workspace/coverage/default/1.chip_sw_uart_tx_rx_bootstrap.637185101 Aug 13 07:15:17 PM PDT 24 Aug 13 10:44:56 PM PDT 24 78896097106 ps
T1136 /workspace/coverage/default/0.chip_sw_rstmgr_rst_cnsty_escalation.1993127491 Aug 13 07:10:05 PM PDT 24 Aug 13 07:22:26 PM PDT 24 5715715400 ps
T1137 /workspace/coverage/default/1.chip_sw_edn_auto_mode.2593385757 Aug 13 07:17:28 PM PDT 24 Aug 13 07:36:58 PM PDT 24 4461246624 ps
T1138 /workspace/coverage/default/0.chip_sw_keymgr_key_derivation_jitter_en_reduced_freq.3035741685 Aug 13 07:15:43 PM PDT 24 Aug 13 07:52:26 PM PDT 24 12804439506 ps
T1139 /workspace/coverage/default/1.chip_sw_edn_sw_mode.3478683652 Aug 13 07:18:38 PM PDT 24 Aug 13 07:41:08 PM PDT 24 6397040240 ps
T341 /workspace/coverage/default/2.chip_sw_uart_tx_rx_bootstrap.1077876477 Aug 13 07:26:33 PM PDT 24 Aug 13 11:32:30 PM PDT 24 77447432508 ps
T236 /workspace/coverage/default/2.chip_sw_keymgr_sideload_aes.3102911167 Aug 13 07:28:40 PM PDT 24 Aug 13 07:45:41 PM PDT 24 5273710608 ps
T1140 /workspace/coverage/default/1.chip_sw_otbn_smoketest.2274956617 Aug 13 07:23:04 PM PDT 24 Aug 13 07:46:07 PM PDT 24 6957007022 ps
T1141 /workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_bad_dev.2840755550 Aug 13 07:17:13 PM PDT 24 Aug 13 08:53:28 PM PDT 24 22901234245 ps
T1142 /workspace/coverage/default/0.chip_sw_pwrmgr_sleep_power_glitch_reset.426027113 Aug 13 07:14:21 PM PDT 24 Aug 13 07:21:13 PM PDT 24 5819466856 ps
T1143 /workspace/coverage/default/45.chip_sw_all_escalation_resets.427052306 Aug 13 07:38:37 PM PDT 24 Aug 13 07:47:50 PM PDT 24 4794730840 ps
T1144 /workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_slow_dev.384628302 Aug 13 07:30:55 PM PDT 24 Aug 13 07:41:32 PM PDT 24 4515229188 ps
T1145 /workspace/coverage/default/0.chip_sw_kmac_app_rom.51141491 Aug 13 07:10:12 PM PDT 24 Aug 13 07:14:33 PM PDT 24 3103807736 ps
T1146 /workspace/coverage/default/1.chip_sw_flash_scrambling_smoketest.1384690328 Aug 13 07:25:13 PM PDT 24 Aug 13 07:28:51 PM PDT 24 3190417398 ps
T52 /workspace/coverage/default/2.chip_jtag_csr_rw.4075856808 Aug 13 07:22:07 PM PDT 24 Aug 13 07:59:35 PM PDT 24 20625063596 ps
T431 /workspace/coverage/default/0.chip_sw_lc_ctrl_test_locked0_to_scrap.1404012372 Aug 13 07:16:40 PM PDT 24 Aug 13 07:19:24 PM PDT 24 3870863912 ps
T432 /workspace/coverage/default/1.chip_sw_rstmgr_smoketest.3605975249 Aug 13 07:24:46 PM PDT 24 Aug 13 07:28:30 PM PDT 24 2746262416 ps
T218 /workspace/coverage/default/2.chip_sw_sysrst_ctrl_in_irq.1581313575 Aug 13 07:26:44 PM PDT 24 Aug 13 07:36:24 PM PDT 24 4012844277 ps
T56 /workspace/coverage/default/0.chip_sw_sleep_pin_wake.579459663 Aug 13 07:09:38 PM PDT 24 Aug 13 07:13:26 PM PDT 24 3525138416 ps
T172 /workspace/coverage/default/3.chip_sw_all_escalation_resets.3968675564 Aug 13 07:34:42 PM PDT 24 Aug 13 07:45:58 PM PDT 24 6057110666 ps
T433 /workspace/coverage/default/2.chip_sw_sleep_pwm_pulses.2727646034 Aug 13 07:25:44 PM PDT 24 Aug 13 07:49:44 PM PDT 24 9092605694 ps
T434 /workspace/coverage/default/0.chip_sw_uart_rand_baudrate.2966376333 Aug 13 07:12:04 PM PDT 24 Aug 13 07:23:08 PM PDT 24 4604261180 ps
T435 /workspace/coverage/default/1.chip_sw_pwrmgr_wdog_reset.1377941523 Aug 13 07:17:09 PM PDT 24 Aug 13 07:28:57 PM PDT 24 4190202692 ps
T436 /workspace/coverage/default/0.chip_tap_straps_testunlock0.3796503244 Aug 13 07:10:57 PM PDT 24 Aug 13 07:16:06 PM PDT 24 3761926328 ps
T364 /workspace/coverage/default/1.chip_sw_uart_tx_rx_idx1.2797699195 Aug 13 07:13:23 PM PDT 24 Aug 13 07:24:55 PM PDT 24 4139700712 ps
T1147 /workspace/coverage/default/2.chip_sw_keymgr_key_derivation_jitter_en.2135269710 Aug 13 07:30:28 PM PDT 24 Aug 13 07:43:18 PM PDT 24 8027507052 ps
T208 /workspace/coverage/default/2.chip_sw_spi_device_pass_through.2234664562 Aug 13 07:26:16 PM PDT 24 Aug 13 07:37:16 PM PDT 24 6257442627 ps
T76 /workspace/coverage/default/1.chip_jtag_csr_rw.1428579487 Aug 13 07:11:52 PM PDT 24 Aug 13 07:41:36 PM PDT 24 12691913900 ps
T1148 /workspace/coverage/default/51.chip_sw_alert_handler_lpg_sleep_mode_alerts.355021822 Aug 13 07:38:42 PM PDT 24 Aug 13 07:46:35 PM PDT 24 4001489404 ps
T1149 /workspace/coverage/default/2.chip_sw_kmac_idle.875099865 Aug 13 07:29:49 PM PDT 24 Aug 13 07:34:37 PM PDT 24 3052666856 ps
T1150 /workspace/coverage/default/0.rom_e2e_sigverify_always_a_nothing_b_bad_rma.728121737 Aug 13 07:18:31 PM PDT 24 Aug 13 08:11:23 PM PDT 24 13963969726 ps
T1151 /workspace/coverage/default/2.chip_sw_pwrmgr_deep_sleep_por_reset.1630185781 Aug 13 07:24:42 PM PDT 24 Aug 13 07:33:10 PM PDT 24 6755593488 ps
T1152 /workspace/coverage/default/1.chip_sw_entropy_src_kat_test.49615086 Aug 13 07:19:02 PM PDT 24 Aug 13 07:22:18 PM PDT 24 3183915150 ps
T211 /workspace/coverage/default/1.chip_jtag_mem_access.2836148419 Aug 13 07:11:26 PM PDT 24 Aug 13 07:40:45 PM PDT 24 13307483048 ps
T115 /workspace/coverage/default/0.chip_sw_ast_clk_rst_inputs.449779002 Aug 13 07:13:25 PM PDT 24 Aug 13 07:51:07 PM PDT 24 16415770812 ps
T1153 /workspace/coverage/default/0.chip_sw_uart_tx_rx_bootstrap.1637550807 Aug 13 07:09:14 PM PDT 24 Aug 13 11:22:16 PM PDT 24 78930149201 ps
T188 /workspace/coverage/default/1.chip_sw_rv_core_ibex_icache_invalidate.2970610967 Aug 13 07:19:55 PM PDT 24 Aug 13 07:24:17 PM PDT 24 3300153676 ps
T1154 /workspace/coverage/default/2.chip_sw_flash_ctrl_idle_low_power.3127561750 Aug 13 07:26:31 PM PDT 24 Aug 13 07:32:48 PM PDT 24 3049916400 ps
T219 /workspace/coverage/default/1.chip_sw_sysrst_ctrl_in_irq.3426325388 Aug 13 07:14:06 PM PDT 24 Aug 13 07:25:47 PM PDT 24 4641116410 ps
T1155 /workspace/coverage/default/0.chip_sw_csrng_kat_test.1377293099 Aug 13 07:12:38 PM PDT 24 Aug 13 07:16:41 PM PDT 24 3343612384 ps
T1156 /workspace/coverage/default/0.chip_sw_hmac_enc_idle.292300125 Aug 13 07:11:39 PM PDT 24 Aug 13 07:17:08 PM PDT 24 3300903898 ps
T1157 /workspace/coverage/default/2.chip_sw_alert_handler_escalation.2864698177 Aug 13 07:27:38 PM PDT 24 Aug 13 07:37:29 PM PDT 24 4767711316 ps
T1158 /workspace/coverage/default/2.chip_sw_pwrmgr_random_sleep_power_glitch_reset.1352565382 Aug 13 07:34:06 PM PDT 24 Aug 13 08:28:37 PM PDT 24 43403410613 ps
T1159 /workspace/coverage/default/2.chip_sw_pwrmgr_random_sleep_all_reset_reqs.2744260906 Aug 13 07:26:19 PM PDT 24 Aug 13 08:12:08 PM PDT 24 29880980325 ps
T779 /workspace/coverage/default/15.chip_sw_alert_handler_lpg_sleep_mode_alerts.1066453784 Aug 13 07:34:33 PM PDT 24 Aug 13 07:42:35 PM PDT 24 3811116096 ps
T1160 /workspace/coverage/default/1.rom_e2e_shutdown_exception_c.943468161 Aug 13 07:24:18 PM PDT 24 Aug 13 08:21:34 PM PDT 24 15627809991 ps
T695 /workspace/coverage/default/2.chip_sw_sram_ctrl_scrambled_access_jitter_en.4281141390 Aug 13 07:28:18 PM PDT 24 Aug 13 07:40:47 PM PDT 24 4989373238 ps
T1161 /workspace/coverage/default/0.rom_e2e_sigverify_always_a_nothing_b_bad_dev.2653015833 Aug 13 07:17:07 PM PDT 24 Aug 13 08:16:34 PM PDT 24 14860596382 ps
T821 /workspace/coverage/default/85.chip_sw_all_escalation_resets.2029098105 Aug 13 07:40:20 PM PDT 24 Aug 13 07:48:15 PM PDT 24 4114858440 ps
T372 /workspace/coverage/default/0.chip_sw_hmac_enc_jitter_en.3198058969 Aug 13 07:10:53 PM PDT 24 Aug 13 07:16:13 PM PDT 24 3482107510 ps
T1162 /workspace/coverage/default/1.chip_sw_flash_ctrl_clock_freqs.2093406821 Aug 13 07:15:15 PM PDT 24 Aug 13 07:32:57 PM PDT 24 6216350780 ps
T1163 /workspace/coverage/default/0.rom_e2e_shutdown_exception_c.75465293 Aug 13 07:16:31 PM PDT 24 Aug 13 08:14:19 PM PDT 24 15040098400 ps
T1164 /workspace/coverage/default/2.chip_sw_example_manufacturer.3125883791 Aug 13 07:23:47 PM PDT 24 Aug 13 07:27:44 PM PDT 24 2834612302 ps
T346 /workspace/coverage/default/2.chip_sw_pwrmgr_lowpower_cancel.1490152853 Aug 13 07:30:06 PM PDT 24 Aug 13 07:36:24 PM PDT 24 3639328680 ps
T860 /workspace/coverage/default/42.chip_sw_alert_handler_lpg_sleep_mode_alerts.4052991057 Aug 13 07:42:01 PM PDT 24 Aug 13 07:48:56 PM PDT 24 3476111718 ps
T375 /workspace/coverage/default/2.chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up.2595253078 Aug 13 07:30:16 PM PDT 24 Aug 13 07:40:30 PM PDT 24 6851076272 ps
T1165 /workspace/coverage/default/11.chip_sw_lc_ctrl_transition.2304740199 Aug 13 07:33:44 PM PDT 24 Aug 13 07:43:37 PM PDT 24 7130768012 ps
T343 /workspace/coverage/default/1.chip_sw_i2c_device_tx_rx.2819376467 Aug 13 07:13:28 PM PDT 24 Aug 13 07:25:24 PM PDT 24 4426928712 ps
T1166 /workspace/coverage/default/2.chip_tap_straps_dev.3860831500 Aug 13 07:29:56 PM PDT 24 Aug 13 07:48:38 PM PDT 24 12080076276 ps
T1167 /workspace/coverage/default/73.chip_sw_all_escalation_resets.3745105463 Aug 13 07:40:29 PM PDT 24 Aug 13 07:52:05 PM PDT 24 5654334590 ps
T816 /workspace/coverage/default/87.chip_sw_alert_handler_lpg_sleep_mode_alerts.1193184086 Aug 13 07:42:00 PM PDT 24 Aug 13 07:47:37 PM PDT 24 3549869496 ps
T358 /workspace/coverage/default/5.chip_sw_data_integrity_escalation.205921413 Aug 13 07:33:20 PM PDT 24 Aug 13 07:43:33 PM PDT 24 6364450278 ps
T829 /workspace/coverage/default/31.chip_sw_alert_handler_lpg_sleep_mode_alerts.871366988 Aug 13 07:39:09 PM PDT 24 Aug 13 07:46:34 PM PDT 24 3538110946 ps
T1168 /workspace/coverage/default/2.chip_sw_aes_enc_jitter_en.3953228010 Aug 13 07:27:58 PM PDT 24 Aug 13 07:32:13 PM PDT 24 3324983219 ps
T1169 /workspace/coverage/default/0.rom_e2e_keymgr_init_rom_ext_meas.988532653 Aug 13 07:21:46 PM PDT 24 Aug 13 08:13:36 PM PDT 24 15082454492 ps
T245 /workspace/coverage/default/1.chip_sw_flash_init_reduced_freq.133400813 Aug 13 07:20:16 PM PDT 24 Aug 13 07:52:09 PM PDT 24 23071568731 ps
T1170 /workspace/coverage/default/1.chip_sw_pwrmgr_usbdev_smoketest.4075352317 Aug 13 07:22:03 PM PDT 24 Aug 13 07:31:22 PM PDT 24 5859843120 ps
T248 /workspace/coverage/default/2.chip_sw_rstmgr_cpu_info.2188413858 Aug 13 07:26:15 PM PDT 24 Aug 13 07:35:58 PM PDT 24 4788046858 ps
T268 /workspace/coverage/default/88.chip_sw_all_escalation_resets.1292961810 Aug 13 07:41:13 PM PDT 24 Aug 13 07:49:25 PM PDT 24 4350879002 ps
T269 /workspace/coverage/default/1.chip_sw_pwrmgr_lowpower_cancel.2499217461 Aug 13 07:19:35 PM PDT 24 Aug 13 07:27:12 PM PDT 24 4165552822 ps
T270 /workspace/coverage/default/14.chip_sw_all_escalation_resets.2712210689 Aug 13 07:34:59 PM PDT 24 Aug 13 07:48:09 PM PDT 24 6014479820 ps
T271 /workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_slow_dev.376733611 Aug 13 07:21:36 PM PDT 24 Aug 13 07:32:56 PM PDT 24 5222194074 ps
T272 /workspace/coverage/default/1.rom_e2e_keymgr_init_rom_ext_invalid_meas.791760021 Aug 13 07:27:01 PM PDT 24 Aug 13 08:19:18 PM PDT 24 14660628440 ps
T273 /workspace/coverage/default/69.chip_sw_all_escalation_resets.2751086047 Aug 13 07:39:53 PM PDT 24 Aug 13 07:49:20 PM PDT 24 5601625272 ps
T274 /workspace/coverage/default/4.chip_sw_uart_tx_rx_alt_clk_freq_low_speed.999891861 Aug 13 07:35:30 PM PDT 24 Aug 13 07:45:50 PM PDT 24 4219170995 ps
T275 /workspace/coverage/default/0.chip_sw_otbn_mem_scramble.1829849622 Aug 13 07:11:17 PM PDT 24 Aug 13 07:20:43 PM PDT 24 3236018894 ps
T276 /workspace/coverage/default/14.chip_sw_alert_handler_lpg_sleep_mode_alerts.853990604 Aug 13 07:36:37 PM PDT 24 Aug 13 07:44:23 PM PDT 24 3624829384 ps
T1171 /workspace/coverage/default/2.chip_sw_flash_ctrl_access.3354377594 Aug 13 07:24:32 PM PDT 24 Aug 13 07:41:51 PM PDT 24 5626192300 ps
T1172 /workspace/coverage/default/0.chip_sw_aes_entropy.352922633 Aug 13 07:12:03 PM PDT 24 Aug 13 07:15:43 PM PDT 24 2084267338 ps
T1173 /workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_fast_dev.1240020502 Aug 13 07:20:06 PM PDT 24 Aug 13 07:29:44 PM PDT 24 3426572132 ps
T1174 /workspace/coverage/default/0.chip_sw_pwrmgr_deep_sleep_all_reset_reqs.2585119360 Aug 13 07:10:49 PM PDT 24 Aug 13 07:32:26 PM PDT 24 14056150195 ps
T846 /workspace/coverage/default/60.chip_sw_all_escalation_resets.1283298635 Aug 13 07:39:04 PM PDT 24 Aug 13 07:50:13 PM PDT 24 4929451720 ps
T284 /workspace/coverage/default/2.chip_sw_data_integrity_escalation.2594186634 Aug 13 07:22:18 PM PDT 24 Aug 13 07:37:48 PM PDT 24 5970348100 ps
T109 /workspace/coverage/default/0.chip_rv_dm_ndm_reset_req.194207069 Aug 13 07:14:12 PM PDT 24 Aug 13 07:22:22 PM PDT 24 5497818276 ps
T196 /workspace/coverage/default/2.chip_sw_csrng_fuse_en_sw_app_read_test.2599748953 Aug 13 07:28:02 PM PDT 24 Aug 13 07:38:12 PM PDT 24 3873197140 ps
T53 /workspace/coverage/default/0.chip_sw_spi_device_pinmux_sleep_retention.2145063468 Aug 13 07:10:36 PM PDT 24 Aug 13 07:16:21 PM PDT 24 3653223797 ps
T1175 /workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_fast_dev.4005841095 Aug 13 07:29:09 PM PDT 24 Aug 13 07:40:21 PM PDT 24 3769943056 ps
T157 /workspace/coverage/default/0.rom_raw_unlock.4231788822 Aug 13 07:15:25 PM PDT 24 Aug 13 07:21:08 PM PDT 24 6897980462 ps
T327 /workspace/coverage/default/0.chip_plic_all_irqs_0.2515178092 Aug 13 07:09:49 PM PDT 24 Aug 13 07:25:50 PM PDT 24 6223268844 ps
T1176 /workspace/coverage/default/6.chip_sw_csrng_edn_concurrency.3582452871 Aug 13 07:32:26 PM PDT 24 Aug 13 09:10:48 PM PDT 24 29131207772 ps
T1177 /workspace/coverage/default/0.chip_sw_keymgr_key_derivation.3920202911 Aug 13 07:11:04 PM PDT 24 Aug 13 07:38:18 PM PDT 24 8375225590 ps
T166 /workspace/coverage/default/0.chip_sw_alert_handler_lpg_sleep_mode_pings.2224929408 Aug 13 07:11:12 PM PDT 24 Aug 13 07:34:45 PM PDT 24 10881194520 ps
T831 /workspace/coverage/default/50.chip_sw_all_escalation_resets.3132455156 Aug 13 07:37:22 PM PDT 24 Aug 13 07:45:33 PM PDT 24 4495545512 ps
T1178 /workspace/coverage/default/2.chip_sw_pwrmgr_all_reset_reqs.2144523123 Aug 13 07:26:23 PM PDT 24 Aug 13 07:55:22 PM PDT 24 10088552341 ps
T145 /workspace/coverage/default/1.chip_sw_ast_clk_rst_inputs.1969541645 Aug 13 07:23:17 PM PDT 24 Aug 13 08:22:54 PM PDT 24 25453688715 ps
T1179 /workspace/coverage/default/2.chip_sw_otp_ctrl_lc_signals_rma.2377588135 Aug 13 07:26:10 PM PDT 24 Aug 13 07:47:40 PM PDT 24 7619690684 ps
T1180 /workspace/coverage/default/2.rom_e2e_keymgr_init_rom_ext_meas.2112173996 Aug 13 07:37:35 PM PDT 24 Aug 13 08:26:51 PM PDT 24 15402955088 ps
T192 /workspace/coverage/default/1.chip_sw_flash_rma_unlocked.3593563391 Aug 13 07:14:46 PM PDT 24 Aug 13 08:31:51 PM PDT 24 43185563100 ps
T1181 /workspace/coverage/default/0.chip_sw_uart_tx_rx_idx1.2360187268 Aug 13 07:09:20 PM PDT 24 Aug 13 07:21:05 PM PDT 24 4448807620 ps
T1182 /workspace/coverage/default/0.chip_sw_csrng_lc_hw_debug_en_test.830855224 Aug 13 07:11:51 PM PDT 24 Aug 13 07:22:14 PM PDT 24 6820002288 ps
T1183 /workspace/coverage/default/0.chip_sw_pwrmgr_random_sleep_all_reset_reqs.86079738 Aug 13 07:09:50 PM PDT 24 Aug 13 07:48:04 PM PDT 24 24553078487 ps
T1184 /workspace/coverage/default/2.chip_sw_csrng_edn_concurrency.3422333808 Aug 13 07:30:57 PM PDT 24 Aug 13 08:38:08 PM PDT 24 17760333640 ps
T1185 /workspace/coverage/default/1.chip_sw_keymgr_key_derivation_prod.3714660559 Aug 13 07:18:13 PM PDT 24 Aug 13 07:46:18 PM PDT 24 10531700580 ps
T1186 /workspace/coverage/default/0.chip_sw_lc_ctrl_rand_to_scrap.2443521123 Aug 13 07:09:03 PM PDT 24 Aug 13 07:11:41 PM PDT 24 2876609857 ps
T141 /workspace/coverage/default/0.chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup.56405673 Aug 13 07:12:43 PM PDT 24 Aug 13 07:23:02 PM PDT 24 5724444652 ps
T33 /workspace/coverage/default/2.chip_sw_spi_host_tx_rx.948664045 Aug 13 07:24:54 PM PDT 24 Aug 13 07:30:37 PM PDT 24 3601145464 ps
T801 /workspace/coverage/default/54.chip_sw_all_escalation_resets.811780496 Aug 13 07:39:27 PM PDT 24 Aug 13 07:47:43 PM PDT 24 4597560882 ps
T1187 /workspace/coverage/default/1.rom_e2e_asm_init_rma.1866230899 Aug 13 07:27:31 PM PDT 24 Aug 13 08:28:14 PM PDT 24 14573640578 ps
T1188 /workspace/coverage/default/43.chip_sw_alert_handler_lpg_sleep_mode_alerts.2970964866 Aug 13 07:37:05 PM PDT 24 Aug 13 07:44:09 PM PDT 24 3494113152 ps
T1189 /workspace/coverage/default/0.chip_sw_rom_ctrl_integrity_check.686773698 Aug 13 07:13:17 PM PDT 24 Aug 13 07:25:56 PM PDT 24 9691757241 ps
T1190 /workspace/coverage/default/0.chip_sw_lc_walkthrough_testunlocks.1307058667 Aug 13 07:09:55 PM PDT 24 Aug 13 07:51:26 PM PDT 24 30561222207 ps
T1191 /workspace/coverage/default/1.chip_sw_keymgr_key_derivation_jitter_en_reduced_freq.3103606985 Aug 13 07:20:16 PM PDT 24 Aug 13 07:56:45 PM PDT 24 11388813769 ps
T745 /workspace/coverage/default/2.chip_sw_pwrmgr_sleep_disabled.1389021934 Aug 13 07:25:26 PM PDT 24 Aug 13 07:32:06 PM PDT 24 3151813634 ps
T1192 /workspace/coverage/default/0.chip_sw_uart_smoketest.1950575114 Aug 13 07:17:39 PM PDT 24 Aug 13 07:22:22 PM PDT 24 2512612084 ps
T1193 /workspace/coverage/default/0.chip_sw_rv_plic_smoketest.2017250318 Aug 13 07:13:32 PM PDT 24 Aug 13 07:17:55 PM PDT 24 2699650142 ps
T819 /workspace/coverage/default/25.chip_sw_alert_handler_lpg_sleep_mode_alerts.3809993362 Aug 13 07:38:08 PM PDT 24 Aug 13 07:45:30 PM PDT 24 4104080224 ps
T1194 /workspace/coverage/default/2.chip_sw_otbn_smoketest.3698937729 Aug 13 07:33:34 PM PDT 24 Aug 13 08:07:10 PM PDT 24 8796542090 ps
T1195 /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_bad_rma.2340602863 Aug 13 07:16:38 PM PDT 24 Aug 13 08:21:38 PM PDT 24 14524781768 ps
T319 /workspace/coverage/default/0.chip_sw_rv_dm_ndm_reset_req_when_cpu_halted.3284561919 Aug 13 07:14:59 PM PDT 24 Aug 13 07:22:46 PM PDT 24 3829736888 ps
T189 /workspace/coverage/default/0.chip_sw_rv_core_ibex_address_translation.571863573 Aug 13 07:13:36 PM PDT 24 Aug 13 07:18:07 PM PDT 24 3049254304 ps
T409 /workspace/coverage/default/2.chip_sw_keymgr_key_derivation.1269606944 Aug 13 07:29:23 PM PDT 24 Aug 13 07:50:50 PM PDT 24 7642286580 ps
T301 /workspace/coverage/default/1.chip_sw_rv_core_ibex_address_translation.939711687 Aug 13 07:19:28 PM PDT 24 Aug 13 07:24:25 PM PDT 24 2776384116 ps
T410 /workspace/coverage/default/0.chip_sw_otbn_randomness.3230109066 Aug 13 07:12:08 PM PDT 24 Aug 13 07:29:13 PM PDT 24 5983304292 ps
T285 /workspace/coverage/default/1.chip_sw_data_integrity_escalation.2399223468 Aug 13 07:15:42 PM PDT 24 Aug 13 07:29:32 PM PDT 24 5410756644 ps
T411 /workspace/coverage/default/2.chip_sw_alert_handler_ping_timeout.2291853573 Aug 13 07:28:19 PM PDT 24 Aug 13 07:37:57 PM PDT 24 5060693400 ps
T412 /workspace/coverage/default/2.chip_sw_entropy_src_ast_rng_req.2195380562 Aug 13 07:28:06 PM PDT 24 Aug 13 07:32:52 PM PDT 24 2898327580 ps
T413 /workspace/coverage/default/1.chip_sw_csrng_kat_test.2409760293 Aug 13 07:16:57 PM PDT 24 Aug 13 07:22:15 PM PDT 24 2530726820 ps
T414 /workspace/coverage/default/2.chip_sw_clkmgr_off_aes_trans.3939065822 Aug 13 07:29:37 PM PDT 24 Aug 13 07:37:15 PM PDT 24 5084560268 ps
T415 /workspace/coverage/default/2.chip_sw_pwrmgr_sleep_power_glitch_reset.1447023343 Aug 13 07:34:51 PM PDT 24 Aug 13 07:41:47 PM PDT 24 6198841152 ps
T833 /workspace/coverage/default/83.chip_sw_all_escalation_resets.1156649855 Aug 13 07:40:52 PM PDT 24 Aug 13 07:51:31 PM PDT 24 6118970864 ps
T1196 /workspace/coverage/default/6.chip_sw_lc_ctrl_transition.655564226 Aug 13 07:35:32 PM PDT 24 Aug 13 07:43:15 PM PDT 24 6851278741 ps
T1197 /workspace/coverage/default/2.chip_sw_aes_smoketest.1009461127 Aug 13 07:32:09 PM PDT 24 Aug 13 07:36:25 PM PDT 24 3027454472 ps
T1198 /workspace/coverage/default/4.chip_tap_straps_rma.1517185286 Aug 13 07:31:55 PM PDT 24 Aug 13 07:35:49 PM PDT 24 3513996571 ps
T767 /workspace/coverage/default/1.chip_sw_sysrst_ctrl_outputs.159997686 Aug 13 07:17:16 PM PDT 24 Aug 13 07:23:54 PM PDT 24 3764455554 ps
T808 /workspace/coverage/default/6.chip_sw_alert_handler_lpg_sleep_mode_alerts.2464772758 Aug 13 07:34:03 PM PDT 24 Aug 13 07:42:11 PM PDT 24 3965932888 ps
T1199 /workspace/coverage/default/0.chip_sw_alert_handler_lpg_clkoff.4238689609 Aug 13 07:13:14 PM PDT 24 Aug 13 07:32:54 PM PDT 24 5726214784 ps
T1200 /workspace/coverage/default/0.chip_sw_ast_clk_outputs.301370446 Aug 13 07:12:02 PM PDT 24 Aug 13 07:26:52 PM PDT 24 6860390840 ps
T403 /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_bad_b_good_rma.1854359425 Aug 13 07:15:11 PM PDT 24 Aug 13 08:54:23 PM PDT 24 23093395184 ps
T1201 /workspace/coverage/default/2.rom_e2e_asm_init_dev.140379974 Aug 13 07:35:57 PM PDT 24 Aug 13 08:28:35 PM PDT 24 16172134149 ps
T1202 /workspace/coverage/default/0.chip_sw_aon_timer_smoketest.2554377944 Aug 13 07:17:55 PM PDT 24 Aug 13 07:23:47 PM PDT 24 2674086528 ps
T787 /workspace/coverage/default/2.chip_sw_all_escalation_resets.2046865755 Aug 13 07:22:30 PM PDT 24 Aug 13 07:31:19 PM PDT 24 4407549210 ps
T379 /workspace/coverage/default/39.chip_sw_alert_handler_lpg_sleep_mode_alerts.743766676 Aug 13 07:38:37 PM PDT 24 Aug 13 07:45:59 PM PDT 24 4346462434 ps
T858 /workspace/coverage/default/49.chip_sw_alert_handler_lpg_sleep_mode_alerts.3702669663 Aug 13 07:43:05 PM PDT 24 Aug 13 07:50:54 PM PDT 24 3779798726 ps
T1203 /workspace/coverage/default/3.chip_sw_uart_rand_baudrate.3382265515 Aug 13 07:33:24 PM PDT 24 Aug 13 07:43:04 PM PDT 24 3866378440 ps
T1204 /workspace/coverage/default/0.chip_sw_hmac_enc.2323492618 Aug 13 07:11:28 PM PDT 24 Aug 13 07:15:19 PM PDT 24 2994102504 ps
T1205 /workspace/coverage/default/8.chip_sw_all_escalation_resets.2100788825 Aug 13 07:34:26 PM PDT 24 Aug 13 07:45:59 PM PDT 24 5397078308 ps
T1206 /workspace/coverage/default/2.chip_sw_sleep_sram_ret_contents_scramble.514237949 Aug 13 07:28:08 PM PDT 24 Aug 13 07:41:18 PM PDT 24 7780461292 ps
T1207 /workspace/coverage/default/35.chip_sw_alert_handler_lpg_sleep_mode_alerts.1393777910 Aug 13 07:36:51 PM PDT 24 Aug 13 07:42:56 PM PDT 24 3947724538 ps
T1208 /workspace/coverage/default/1.chip_sw_edn_kat.3648771842 Aug 13 07:16:46 PM PDT 24 Aug 13 07:27:03 PM PDT 24 3649621230 ps
T1209 /workspace/coverage/default/8.chip_sw_lc_ctrl_transition.4123129048 Aug 13 07:33:32 PM PDT 24 Aug 13 07:43:28 PM PDT 24 6022350203 ps
T1210 /workspace/coverage/default/0.chip_sw_pwrmgr_normal_sleep_all_reset_reqs.3186572759 Aug 13 07:14:31 PM PDT 24 Aug 13 07:38:09 PM PDT 24 10004909622 ps
T249 /workspace/coverage/default/0.chip_sw_rstmgr_cpu_info.2043461951 Aug 13 07:11:42 PM PDT 24 Aug 13 07:23:17 PM PDT 24 7096929128 ps
T1211 /workspace/coverage/default/2.chip_sw_alert_handler_entropy.3490635916 Aug 13 07:28:37 PM PDT 24 Aug 13 07:34:15 PM PDT 24 3716341597 ps
T1212 /workspace/coverage/default/1.chip_sw_kmac_mode_kmac.2114340546 Aug 13 07:17:45 PM PDT 24 Aug 13 07:22:14 PM PDT 24 2942983248 ps
T1213 /workspace/coverage/default/2.chip_sw_clkmgr_jitter.3055332959 Aug 13 07:28:37 PM PDT 24 Aug 13 07:32:02 PM PDT 24 2931410816 ps
T1214 /workspace/coverage/default/0.chip_sw_otp_ctrl_ecc_error_vendor_test.3514573706 Aug 13 07:13:57 PM PDT 24 Aug 13 07:17:52 PM PDT 24 2900416519 ps
T839 /workspace/coverage/default/86.chip_sw_all_escalation_resets.3237098007 Aug 13 07:41:08 PM PDT 24 Aug 13 07:53:21 PM PDT 24 5877241600 ps
T1215 /workspace/coverage/default/1.chip_sw_flash_ctrl_idle_low_power.1302243348 Aug 13 07:14:44 PM PDT 24 Aug 13 07:20:03 PM PDT 24 3923410608 ps
T790 /workspace/coverage/default/66.chip_sw_alert_handler_lpg_sleep_mode_alerts.1865291950 Aug 13 07:39:42 PM PDT 24 Aug 13 07:45:28 PM PDT 24 3708151272 ps
T1216 /workspace/coverage/default/15.chip_sw_uart_rand_baudrate.4265524459 Aug 13 07:35:45 PM PDT 24 Aug 13 08:01:14 PM PDT 24 8385185424 ps
T1217 /workspace/coverage/default/0.chip_sw_otp_ctrl_lc_signals_dev.817098536 Aug 13 07:14:16 PM PDT 24 Aug 13 07:37:24 PM PDT 24 8398322616 ps
T780 /workspace/coverage/default/81.chip_sw_alert_handler_lpg_sleep_mode_alerts.268331784 Aug 13 07:40:40 PM PDT 24 Aug 13 07:47:34 PM PDT 24 4685824300 ps
T1218 /workspace/coverage/default/0.chip_sw_lc_ctrl_rma_to_scrap.3439678057 Aug 13 07:14:20 PM PDT 24 Aug 13 07:18:16 PM PDT 24 3894103090 ps
T1219 /workspace/coverage/default/2.chip_sw_clkmgr_off_kmac_trans.1596218022 Aug 13 07:32:39 PM PDT 24 Aug 13 07:40:45 PM PDT 24 3511606800 ps
T1220 /workspace/coverage/default/2.chip_sw_uart_tx_rx_idx3.4259772971 Aug 13 07:23:54 PM PDT 24 Aug 13 07:33:29 PM PDT 24 3989175184 ps
T804 /workspace/coverage/default/22.chip_sw_all_escalation_resets.1569272445 Aug 13 07:36:46 PM PDT 24 Aug 13 07:46:52 PM PDT 24 4853402802 ps
T191 /workspace/coverage/default/2.chip_sw_flash_rma_unlocked.3034169764 Aug 13 07:25:28 PM PDT 24 Aug 13 08:37:13 PM PDT 24 43884394728 ps
T1221 /workspace/coverage/default/1.chip_sw_lc_ctrl_volatile_raw_unlock.524343769 Aug 13 07:20:19 PM PDT 24 Aug 13 07:22:15 PM PDT 24 2557779657 ps
T137 /workspace/coverage/default/3.chip_sw_sensor_ctrl_alert.1054124165 Aug 13 07:32:08 PM PDT 24 Aug 13 07:43:34 PM PDT 24 6450044922 ps
T1222 /workspace/coverage/default/0.chip_sw_aon_timer_wdog_lc_escalate.1849356602 Aug 13 07:10:24 PM PDT 24 Aug 13 07:22:50 PM PDT 24 5916004990 ps
T1223 /workspace/coverage/default/2.rom_e2e_shutdown_exception_c.4026564782 Aug 13 07:37:22 PM PDT 24 Aug 13 08:32:31 PM PDT 24 14937293112 ps
T1224 /workspace/coverage/default/1.chip_sw_alert_handler_ping_ok.3467825074 Aug 13 07:18:42 PM PDT 24 Aug 13 07:44:43 PM PDT 24 8658145324 ps
T246 /workspace/coverage/default/0.chip_sw_flash_ctrl_lc_rw_en.4238421970 Aug 13 07:10:30 PM PDT 24 Aug 13 07:20:42 PM PDT 24 4898017404 ps
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