| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
| 96.20 | 95.54 | 94.20 | 95.34 | 95.05 | 97.53 | 99.52 |
| T2767 | /workspace/coverage/cover_reg_top/6.xbar_smoke_zero_delays.3752028377 | Aug 13 06:50:54 PM PDT 24 | Aug 13 06:51:01 PM PDT 24 | 51438659 ps | ||
| T2768 | /workspace/coverage/cover_reg_top/16.xbar_random_large_delays.2241061054 | Aug 13 06:51:14 PM PDT 24 | Aug 13 06:59:25 PM PDT 24 | 45283065495 ps | ||
| T2769 | /workspace/coverage/cover_reg_top/1.chip_rv_dm_lc_disabled.4241030324 | Aug 13 06:50:40 PM PDT 24 | Aug 13 06:58:33 PM PDT 24 | 15369342369 ps | ||
| T921 | /workspace/coverage/cover_reg_top/42.xbar_stress_all_with_rand_reset.1508553163 | Aug 13 06:54:01 PM PDT 24 | Aug 13 07:04:57 PM PDT 24 | 12578137557 ps | ||
| T2770 | /workspace/coverage/cover_reg_top/51.xbar_access_same_device_slow_rsp.738334589 | Aug 13 06:55:04 PM PDT 24 | Aug 13 07:24:23 PM PDT 24 | 104758094943 ps | ||
| T2771 | /workspace/coverage/cover_reg_top/5.xbar_access_same_device.1130022956 | Aug 13 06:50:49 PM PDT 24 | Aug 13 06:51:12 PM PDT 24 | 497628653 ps | ||
| T2772 | /workspace/coverage/cover_reg_top/88.xbar_access_same_device_slow_rsp.1904900170 | Aug 13 06:59:46 PM PDT 24 | Aug 13 07:06:23 PM PDT 24 | 23383890579 ps | ||
| T2773 | /workspace/coverage/cover_reg_top/38.xbar_smoke_large_delays.2378763779 | Aug 13 06:53:30 PM PDT 24 | Aug 13 06:55:04 PM PDT 24 | 8677183090 ps | ||
| T2774 | /workspace/coverage/cover_reg_top/96.xbar_random.832774410 | Aug 13 07:00:45 PM PDT 24 | Aug 13 07:00:57 PM PDT 24 | 272761252 ps | ||
| T2775 | /workspace/coverage/cover_reg_top/67.xbar_smoke_slow_rsp.3422737013 | Aug 13 06:57:00 PM PDT 24 | Aug 13 06:58:32 PM PDT 24 | 5346258953 ps | ||
| T2776 | /workspace/coverage/cover_reg_top/45.xbar_random_large_delays.231056837 | Aug 13 06:54:20 PM PDT 24 | Aug 13 06:56:13 PM PDT 24 | 10766614877 ps | ||
| T2777 | /workspace/coverage/cover_reg_top/82.xbar_stress_all_with_rand_reset.2076130380 | Aug 13 06:59:07 PM PDT 24 | Aug 13 07:03:10 PM PDT 24 | 2004184558 ps | ||
| T2778 | /workspace/coverage/cover_reg_top/65.xbar_error_random.3302210648 | Aug 13 06:56:56 PM PDT 24 | Aug 13 06:57:17 PM PDT 24 | 623012330 ps | ||
| T2779 | /workspace/coverage/cover_reg_top/48.xbar_same_source.3586231557 | Aug 13 06:54:43 PM PDT 24 | Aug 13 06:55:52 PM PDT 24 | 2174899055 ps | ||
| T2780 | /workspace/coverage/cover_reg_top/52.xbar_random.1229909079 | Aug 13 06:55:08 PM PDT 24 | Aug 13 06:56:23 PM PDT 24 | 2212584963 ps | ||
| T2781 | /workspace/coverage/cover_reg_top/67.xbar_same_source.3232897616 | Aug 13 06:57:03 PM PDT 24 | Aug 13 06:58:16 PM PDT 24 | 2728146207 ps | ||
| T2782 | /workspace/coverage/cover_reg_top/15.xbar_access_same_device.1116785866 | Aug 13 06:51:14 PM PDT 24 | Aug 13 06:52:15 PM PDT 24 | 793521293 ps | ||
| T2783 | /workspace/coverage/cover_reg_top/15.chip_csr_mem_rw_with_rand_reset.3601893965 | Aug 13 06:51:14 PM PDT 24 | Aug 13 06:58:52 PM PDT 24 | 7040713224 ps | ||
| T2784 | /workspace/coverage/cover_reg_top/9.chip_csr_rw.4241500461 | Aug 13 06:51:01 PM PDT 24 | Aug 13 06:59:38 PM PDT 24 | 5031703640 ps | ||
| T2785 | /workspace/coverage/cover_reg_top/33.xbar_smoke.2243184510 | Aug 13 06:53:04 PM PDT 24 | Aug 13 06:53:12 PM PDT 24 | 192810958 ps | ||
| T2786 | /workspace/coverage/cover_reg_top/62.xbar_unmapped_addr.1456645684 | Aug 13 06:56:27 PM PDT 24 | Aug 13 06:56:56 PM PDT 24 | 253730759 ps | ||
| T2787 | /workspace/coverage/cover_reg_top/31.xbar_random_slow_rsp.553202991 | Aug 13 06:52:58 PM PDT 24 | Aug 13 07:01:09 PM PDT 24 | 28539563300 ps | ||
| T2788 | /workspace/coverage/cover_reg_top/57.xbar_random_slow_rsp.3948909224 | Aug 13 06:55:48 PM PDT 24 | Aug 13 07:16:02 PM PDT 24 | 62001370873 ps | ||
| T2789 | /workspace/coverage/cover_reg_top/14.chip_csr_rw.3536725178 | Aug 13 06:51:27 PM PDT 24 | Aug 13 06:58:00 PM PDT 24 | 4469551874 ps | ||
| T2790 | /workspace/coverage/cover_reg_top/32.xbar_random_slow_rsp.2035985733 | Aug 13 06:52:55 PM PDT 24 | Aug 13 07:05:45 PM PDT 24 | 43328396737 ps | ||
| T2791 | /workspace/coverage/cover_reg_top/37.xbar_smoke_slow_rsp.4227029128 | Aug 13 06:53:29 PM PDT 24 | Aug 13 06:55:05 PM PDT 24 | 5638271461 ps | ||
| T2792 | /workspace/coverage/cover_reg_top/31.xbar_smoke.826544396 | Aug 13 06:52:49 PM PDT 24 | Aug 13 06:52:58 PM PDT 24 | 204377407 ps | ||
| T2793 | /workspace/coverage/cover_reg_top/71.xbar_stress_all_with_rand_reset.2877259064 | Aug 13 06:57:45 PM PDT 24 | Aug 13 07:07:21 PM PDT 24 | 11347579603 ps | ||
| T2794 | /workspace/coverage/cover_reg_top/47.xbar_stress_all_with_reset_error.408139253 | Aug 13 06:54:40 PM PDT 24 | Aug 13 06:57:28 PM PDT 24 | 3402899773 ps | ||
| T2795 | /workspace/coverage/cover_reg_top/32.xbar_stress_all_with_rand_reset.3124766750 | Aug 13 06:53:01 PM PDT 24 | Aug 13 06:57:48 PM PDT 24 | 3357126686 ps | ||
| T2796 | /workspace/coverage/cover_reg_top/76.xbar_random_large_delays.3388644720 | Aug 13 06:58:11 PM PDT 24 | Aug 13 07:06:22 PM PDT 24 | 48514961597 ps | ||
| T2797 | /workspace/coverage/cover_reg_top/38.xbar_same_source.2346919613 | Aug 13 06:53:30 PM PDT 24 | Aug 13 06:53:48 PM PDT 24 | 232336280 ps | ||
| T2798 | /workspace/coverage/cover_reg_top/16.xbar_stress_all.3770178648 | Aug 13 06:51:32 PM PDT 24 | Aug 13 06:57:28 PM PDT 24 | 9188927774 ps | ||
| T2799 | /workspace/coverage/cover_reg_top/89.xbar_error_random.3465800635 | Aug 13 06:59:59 PM PDT 24 | Aug 13 07:00:36 PM PDT 24 | 1199985771 ps | ||
| T2800 | /workspace/coverage/cover_reg_top/49.xbar_stress_all.1125505374 | Aug 13 06:54:50 PM PDT 24 | Aug 13 06:57:31 PM PDT 24 | 4325697218 ps | ||
| T913 | /workspace/coverage/cover_reg_top/77.xbar_stress_all_with_rand_reset.2948918897 | Aug 13 06:58:31 PM PDT 24 | Aug 13 07:04:59 PM PDT 24 | 5573084790 ps | ||
| T2801 | /workspace/coverage/cover_reg_top/24.xbar_stress_all.1596502224 | Aug 13 06:52:09 PM PDT 24 | Aug 13 06:52:40 PM PDT 24 | 430267978 ps | ||
| T2802 | /workspace/coverage/cover_reg_top/94.xbar_access_same_device.1655898843 | Aug 13 07:00:44 PM PDT 24 | Aug 13 07:01:19 PM PDT 24 | 370271158 ps | ||
| T2803 | /workspace/coverage/cover_reg_top/20.xbar_same_source.1914813306 | Aug 13 06:51:40 PM PDT 24 | Aug 13 06:52:58 PM PDT 24 | 2667230804 ps | ||
| T2804 | /workspace/coverage/cover_reg_top/37.xbar_smoke_large_delays.618346875 | Aug 13 06:53:29 PM PDT 24 | Aug 13 06:54:42 PM PDT 24 | 7665372055 ps | ||
| T922 | /workspace/coverage/cover_reg_top/46.xbar_stress_all_with_rand_reset.253118088 | Aug 13 06:54:31 PM PDT 24 | Aug 13 06:59:01 PM PDT 24 | 671182973 ps | ||
| T2805 | /workspace/coverage/cover_reg_top/78.xbar_random.2343322165 | Aug 13 06:58:29 PM PDT 24 | Aug 13 06:58:37 PM PDT 24 | 170760086 ps | ||
| T2806 | /workspace/coverage/cover_reg_top/2.xbar_stress_all.2724327859 | Aug 13 06:50:57 PM PDT 24 | Aug 13 06:53:57 PM PDT 24 | 4612911780 ps | ||
| T2807 | /workspace/coverage/cover_reg_top/45.xbar_stress_all.3480370438 | Aug 13 06:54:22 PM PDT 24 | Aug 13 07:03:45 PM PDT 24 | 16945847303 ps | ||
| T2808 | /workspace/coverage/cover_reg_top/16.xbar_smoke_slow_rsp.2010776037 | Aug 13 06:51:25 PM PDT 24 | Aug 13 06:52:41 PM PDT 24 | 4832866871 ps | ||
| T2809 | /workspace/coverage/cover_reg_top/3.xbar_stress_all_with_error.3546700232 | Aug 13 06:50:53 PM PDT 24 | Aug 13 06:53:07 PM PDT 24 | 1761980589 ps | ||
| T2810 | /workspace/coverage/cover_reg_top/93.xbar_random_zero_delays.3813526542 | Aug 13 07:00:25 PM PDT 24 | Aug 13 07:00:36 PM PDT 24 | 97654163 ps | ||
| T2811 | /workspace/coverage/cover_reg_top/12.chip_csr_rw.1839726859 | Aug 13 06:51:15 PM PDT 24 | Aug 13 06:59:47 PM PDT 24 | 5811030400 ps | ||
| T2812 | /workspace/coverage/cover_reg_top/21.xbar_smoke_large_delays.1693108506 | Aug 13 06:51:36 PM PDT 24 | Aug 13 06:52:48 PM PDT 24 | 7006053980 ps | ||
| T677 | /workspace/coverage/cover_reg_top/72.xbar_stress_all_with_reset_error.908152596 | Aug 13 06:57:44 PM PDT 24 | Aug 13 07:03:13 PM PDT 24 | 4900763496 ps | ||
| T2813 | /workspace/coverage/cover_reg_top/48.xbar_random_slow_rsp.2049716028 | Aug 13 06:54:45 PM PDT 24 | Aug 13 06:58:31 PM PDT 24 | 13181005548 ps | ||
| T2814 | /workspace/coverage/cover_reg_top/14.xbar_random.1307412895 | Aug 13 06:51:27 PM PDT 24 | Aug 13 06:52:14 PM PDT 24 | 606796180 ps | ||
| T2815 | /workspace/coverage/cover_reg_top/13.xbar_random_slow_rsp.204458249 | Aug 13 06:51:20 PM PDT 24 | Aug 13 07:05:17 PM PDT 24 | 53217761894 ps | ||
| T2816 | /workspace/coverage/cover_reg_top/21.xbar_unmapped_addr.330725908 | Aug 13 06:51:50 PM PDT 24 | Aug 13 06:52:09 PM PDT 24 | 401026438 ps | ||
| T2817 | /workspace/coverage/cover_reg_top/13.xbar_random.806495489 | Aug 13 06:51:25 PM PDT 24 | Aug 13 06:51:46 PM PDT 24 | 231293217 ps | ||
| T2818 | /workspace/coverage/cover_reg_top/61.xbar_random_zero_delays.1304276735 | Aug 13 06:56:19 PM PDT 24 | Aug 13 06:56:48 PM PDT 24 | 344756422 ps | ||
| T2819 | /workspace/coverage/cover_reg_top/54.xbar_stress_all_with_rand_reset.2776985298 | Aug 13 06:55:25 PM PDT 24 | Aug 13 07:02:53 PM PDT 24 | 2034654475 ps | ||
| T2820 | /workspace/coverage/cover_reg_top/14.xbar_stress_all.3661441523 | Aug 13 06:51:21 PM PDT 24 | Aug 13 06:54:50 PM PDT 24 | 5758558272 ps | ||
| T2821 | /workspace/coverage/cover_reg_top/3.xbar_smoke_slow_rsp.253436038 | Aug 13 06:50:36 PM PDT 24 | Aug 13 06:52:03 PM PDT 24 | 5043605947 ps | ||
| T733 | /workspace/coverage/cover_reg_top/2.chip_tl_errors.1823350056 | Aug 13 06:50:48 PM PDT 24 | Aug 13 06:53:41 PM PDT 24 | 3468956024 ps | ||
| T2822 | /workspace/coverage/cover_reg_top/24.xbar_access_same_device.4205940219 | Aug 13 06:52:11 PM PDT 24 | Aug 13 06:53:31 PM PDT 24 | 1688694709 ps | ||
| T2823 | /workspace/coverage/cover_reg_top/27.xbar_error_and_unmapped_addr.4082631007 | Aug 13 06:52:34 PM PDT 24 | Aug 13 06:52:53 PM PDT 24 | 430677883 ps | ||
| T2824 | /workspace/coverage/cover_reg_top/48.xbar_access_same_device.1016870761 | Aug 13 06:54:42 PM PDT 24 | Aug 13 06:55:15 PM PDT 24 | 852866781 ps | ||
| T2825 | /workspace/coverage/cover_reg_top/8.xbar_random.4213534106 | Aug 13 06:51:10 PM PDT 24 | Aug 13 06:51:19 PM PDT 24 | 146761281 ps | ||
| T2826 | /workspace/coverage/cover_reg_top/98.xbar_stress_all.2055347283 | Aug 13 07:01:13 PM PDT 24 | Aug 13 07:10:40 PM PDT 24 | 14016315987 ps | ||
| T2827 | /workspace/coverage/cover_reg_top/58.xbar_access_same_device.1130771737 | Aug 13 06:55:56 PM PDT 24 | Aug 13 06:56:14 PM PDT 24 | 342392301 ps | ||
| T2828 | /workspace/coverage/cover_reg_top/31.xbar_smoke_slow_rsp.3590171066 | Aug 13 06:52:53 PM PDT 24 | Aug 13 06:54:11 PM PDT 24 | 4522889196 ps | ||
| T2829 | /workspace/coverage/cover_reg_top/78.xbar_smoke.1821855254 | Aug 13 06:58:27 PM PDT 24 | Aug 13 06:58:37 PM PDT 24 | 243901716 ps | ||
| T2830 | /workspace/coverage/cover_reg_top/43.xbar_random_large_delays.1667724715 | Aug 13 06:54:09 PM PDT 24 | Aug 13 07:15:03 PM PDT 24 | 112181535260 ps | ||
| T2831 | /workspace/coverage/cover_reg_top/9.xbar_unmapped_addr.2759344889 | Aug 13 06:51:09 PM PDT 24 | Aug 13 06:51:15 PM PDT 24 | 20385352 ps | ||
| T2832 | /workspace/coverage/cover_reg_top/46.xbar_smoke.550078880 | Aug 13 06:54:21 PM PDT 24 | Aug 13 06:54:31 PM PDT 24 | 222337440 ps | ||
| T2833 | /workspace/coverage/cover_reg_top/59.xbar_random_slow_rsp.1947550765 | Aug 13 06:56:01 PM PDT 24 | Aug 13 07:05:18 PM PDT 24 | 31083848484 ps | ||
| T2834 | /workspace/coverage/cover_reg_top/23.xbar_unmapped_addr.683033191 | Aug 13 06:52:11 PM PDT 24 | Aug 13 06:52:48 PM PDT 24 | 915969396 ps | ||
| T672 | /workspace/coverage/cover_reg_top/21.xbar_stress_all_with_reset_error.4294495296 | Aug 13 06:51:43 PM PDT 24 | Aug 13 06:53:05 PM PDT 24 | 330463152 ps | ||
| T2835 | /workspace/coverage/cover_reg_top/1.xbar_stress_all_with_reset_error.898929936 | Aug 13 06:50:41 PM PDT 24 | Aug 13 06:52:34 PM PDT 24 | 412199721 ps | ||
| T2836 | /workspace/coverage/cover_reg_top/76.xbar_smoke_slow_rsp.3257045929 | Aug 13 06:58:11 PM PDT 24 | Aug 13 06:59:31 PM PDT 24 | 4969821709 ps | ||
| T2837 | /workspace/coverage/cover_reg_top/0.chip_csr_mem_rw_with_rand_reset.2409673756 | Aug 13 06:50:32 PM PDT 24 | Aug 13 07:00:00 PM PDT 24 | 7311697480 ps | ||
| T2838 | /workspace/coverage/cover_reg_top/6.xbar_random_large_delays.282907805 | Aug 13 06:51:01 PM PDT 24 | Aug 13 06:56:09 PM PDT 24 | 31739975042 ps | ||
| T2839 | /workspace/coverage/cover_reg_top/41.xbar_stress_all_with_reset_error.4068830634 | Aug 13 06:54:02 PM PDT 24 | Aug 13 06:56:44 PM PDT 24 | 2497082773 ps | ||
| T2840 | /workspace/coverage/cover_reg_top/8.chip_tl_errors.1101006438 | Aug 13 06:51:10 PM PDT 24 | Aug 13 06:55:24 PM PDT 24 | 3652835600 ps | ||
| T2841 | /workspace/coverage/cover_reg_top/12.xbar_stress_all_with_error.304771641 | Aug 13 06:51:16 PM PDT 24 | Aug 13 06:57:30 PM PDT 24 | 10483195945 ps | ||
| T2842 | /workspace/coverage/cover_reg_top/84.xbar_error_random.4036900697 | Aug 13 06:59:15 PM PDT 24 | Aug 13 07:00:37 PM PDT 24 | 2300547445 ps | ||
| T2843 | /workspace/coverage/cover_reg_top/19.chip_same_csr_outstanding.2539022007 | Aug 13 06:51:32 PM PDT 24 | Aug 13 07:51:06 PM PDT 24 | 28073573074 ps | ||
| T2844 | /workspace/coverage/cover_reg_top/15.xbar_same_source.797522843 | Aug 13 06:51:18 PM PDT 24 | Aug 13 06:52:16 PM PDT 24 | 2153638920 ps | ||
| T2845 | /workspace/coverage/cover_reg_top/69.xbar_unmapped_addr.1261436196 | Aug 13 06:57:27 PM PDT 24 | Aug 13 06:57:49 PM PDT 24 | 171229804 ps | ||
| T2846 | /workspace/coverage/cover_reg_top/90.xbar_stress_all_with_error.2964613116 | Aug 13 07:00:13 PM PDT 24 | Aug 13 07:03:50 PM PDT 24 | 6576276906 ps | ||
| T2847 | /workspace/coverage/cover_reg_top/69.xbar_same_source.109958156 | Aug 13 06:57:21 PM PDT 24 | Aug 13 06:58:05 PM PDT 24 | 1620363054 ps | ||
| T2848 | /workspace/coverage/cover_reg_top/13.xbar_smoke.3963604018 | Aug 13 06:51:24 PM PDT 24 | Aug 13 06:51:33 PM PDT 24 | 198454805 ps | ||
| T2849 | /workspace/coverage/cover_reg_top/74.xbar_stress_all_with_rand_reset.1640886059 | Aug 13 06:58:08 PM PDT 24 | Aug 13 07:00:19 PM PDT 24 | 169619932 ps | ||
| T2850 | /workspace/coverage/cover_reg_top/39.xbar_stress_all.812451232 | Aug 13 06:53:39 PM PDT 24 | Aug 13 06:57:04 PM PDT 24 | 2596802534 ps | ||
| T2851 | /workspace/coverage/cover_reg_top/21.xbar_access_same_device.4052452079 | Aug 13 06:51:34 PM PDT 24 | Aug 13 06:52:31 PM PDT 24 | 1265768878 ps | ||
| T2852 | /workspace/coverage/cover_reg_top/23.xbar_stress_all_with_reset_error.1887920124 | Aug 13 06:52:05 PM PDT 24 | Aug 13 06:57:38 PM PDT 24 | 2567220764 ps | ||
| T2853 | /workspace/coverage/cover_reg_top/63.xbar_stress_all.3952742519 | Aug 13 06:56:37 PM PDT 24 | Aug 13 06:58:44 PM PDT 24 | 3089500933 ps | ||
| T2854 | /workspace/coverage/cover_reg_top/83.xbar_stress_all_with_reset_error.696685877 | Aug 13 06:59:13 PM PDT 24 | Aug 13 07:06:30 PM PDT 24 | 5719511828 ps | ||
| T2855 | /workspace/coverage/cover_reg_top/32.xbar_random_zero_delays.2168000247 | Aug 13 06:52:54 PM PDT 24 | Aug 13 06:53:12 PM PDT 24 | 207690696 ps | ||
| T2856 | /workspace/coverage/cover_reg_top/30.xbar_smoke_zero_delays.2886872266 | Aug 13 06:52:49 PM PDT 24 | Aug 13 06:52:56 PM PDT 24 | 57424063 ps | ||
| T2857 | /workspace/coverage/cover_reg_top/25.xbar_random_large_delays.1765060316 | Aug 13 06:52:19 PM PDT 24 | Aug 13 06:59:14 PM PDT 24 | 43740850721 ps | ||
| T2858 | /workspace/coverage/cover_reg_top/47.xbar_random.3967701653 | Aug 13 06:54:34 PM PDT 24 | Aug 13 06:55:22 PM PDT 24 | 536017899 ps | ||
| T2859 | /workspace/coverage/cover_reg_top/25.xbar_same_source.3564724335 | Aug 13 06:52:17 PM PDT 24 | Aug 13 06:52:51 PM PDT 24 | 445030440 ps | ||
| T2860 | /workspace/coverage/cover_reg_top/84.xbar_random_zero_delays.3940064510 | Aug 13 06:59:13 PM PDT 24 | Aug 13 06:59:25 PM PDT 24 | 98134285 ps | ||
| T2861 | /workspace/coverage/cover_reg_top/42.xbar_smoke_large_delays.1898123791 | Aug 13 06:54:02 PM PDT 24 | Aug 13 06:55:59 PM PDT 24 | 11240267913 ps | ||
| T2862 | /workspace/coverage/cover_reg_top/88.xbar_stress_all_with_error.53965763 | Aug 13 06:59:57 PM PDT 24 | Aug 13 07:00:55 PM PDT 24 | 794750497 ps | ||
| T2863 | /workspace/coverage/cover_reg_top/3.xbar_access_same_device.1384478018 | Aug 13 06:50:55 PM PDT 24 | Aug 13 06:51:30 PM PDT 24 | 452846047 ps | ||
| T2864 | /workspace/coverage/cover_reg_top/93.xbar_same_source.1910739465 | Aug 13 07:00:23 PM PDT 24 | Aug 13 07:01:27 PM PDT 24 | 2115675203 ps | ||
| T2865 | /workspace/coverage/cover_reg_top/40.xbar_error_random.3929544955 | Aug 13 06:53:55 PM PDT 24 | Aug 13 06:54:10 PM PDT 24 | 133346019 ps | ||
| T2866 | /workspace/coverage/cover_reg_top/71.xbar_access_same_device.4106493103 | Aug 13 06:57:35 PM PDT 24 | Aug 13 06:58:09 PM PDT 24 | 693486855 ps | ||
| T2867 | /workspace/coverage/cover_reg_top/53.xbar_random.908540252 | Aug 13 06:55:19 PM PDT 24 | Aug 13 06:55:28 PM PDT 24 | 55929197 ps | ||
| T2868 | /workspace/coverage/cover_reg_top/25.xbar_access_same_device.2185475262 | Aug 13 06:52:16 PM PDT 24 | Aug 13 06:53:41 PM PDT 24 | 944417123 ps | ||
| T2869 | /workspace/coverage/cover_reg_top/86.xbar_smoke.3390774280 | Aug 13 06:59:30 PM PDT 24 | Aug 13 06:59:41 PM PDT 24 | 258227955 ps | ||
| T2870 | /workspace/coverage/cover_reg_top/43.xbar_stress_all_with_rand_reset.268090131 | Aug 13 06:54:09 PM PDT 24 | Aug 13 06:57:02 PM PDT 24 | 903762627 ps | ||
| T2871 | /workspace/coverage/cover_reg_top/30.xbar_stress_all_with_error.3317851253 | Aug 13 06:52:50 PM PDT 24 | Aug 13 06:55:46 PM PDT 24 | 2208966165 ps | ||
| T2872 | /workspace/coverage/cover_reg_top/85.xbar_smoke_large_delays.1910203452 | Aug 13 06:59:22 PM PDT 24 | Aug 13 07:01:12 PM PDT 24 | 10136811371 ps | ||
| T2873 | /workspace/coverage/cover_reg_top/70.xbar_stress_all.3632704583 | Aug 13 06:57:36 PM PDT 24 | Aug 13 07:03:42 PM PDT 24 | 10785499746 ps | ||
| T2874 | /workspace/coverage/cover_reg_top/12.xbar_random_large_delays.1232930906 | Aug 13 06:51:04 PM PDT 24 | Aug 13 06:56:26 PM PDT 24 | 34579600463 ps | ||
| T2875 | /workspace/coverage/cover_reg_top/3.xbar_stress_all_with_rand_reset.2267589364 | Aug 13 06:50:52 PM PDT 24 | Aug 13 06:51:51 PM PDT 24 | 127353866 ps | ||
| T2876 | /workspace/coverage/cover_reg_top/20.xbar_access_same_device.2941017357 | Aug 13 06:51:34 PM PDT 24 | Aug 13 06:52:56 PM PDT 24 | 1033264179 ps | ||
| T2877 | /workspace/coverage/cover_reg_top/79.xbar_smoke_slow_rsp.2995361741 | Aug 13 06:58:36 PM PDT 24 | Aug 13 06:59:48 PM PDT 24 | 4624360014 ps | ||
| T2878 | /workspace/coverage/cover_reg_top/5.xbar_error_random.1288759314 | Aug 13 06:50:57 PM PDT 24 | Aug 13 06:51:59 PM PDT 24 | 2038050373 ps | ||
| T2879 | /workspace/coverage/cover_reg_top/34.xbar_stress_all_with_reset_error.2666093904 | Aug 13 06:53:16 PM PDT 24 | Aug 13 06:53:34 PM PDT 24 | 25875325 ps | ||
| T2880 | /workspace/coverage/cover_reg_top/24.xbar_unmapped_addr.2442223119 | Aug 13 06:52:09 PM PDT 24 | Aug 13 06:52:21 PM PDT 24 | 86338352 ps | ||
| T2881 | /workspace/coverage/cover_reg_top/26.xbar_error_and_unmapped_addr.1726807281 | Aug 13 06:52:28 PM PDT 24 | Aug 13 06:52:55 PM PDT 24 | 246838371 ps | ||
| T2882 | /workspace/coverage/cover_reg_top/99.xbar_stress_all.123895405 | Aug 13 07:01:20 PM PDT 24 | Aug 13 07:06:40 PM PDT 24 | 8995519672 ps | ||
| T2883 | /workspace/coverage/cover_reg_top/95.xbar_stress_all.764846246 | Aug 13 07:00:45 PM PDT 24 | Aug 13 07:02:58 PM PDT 24 | 3915637708 ps | ||
| T2884 | /workspace/coverage/cover_reg_top/7.xbar_stress_all_with_rand_reset.1556162908 | Aug 13 06:51:01 PM PDT 24 | Aug 13 07:02:33 PM PDT 24 | 6017055806 ps | ||
| T2885 | /workspace/coverage/cover_reg_top/42.xbar_random_zero_delays.158888151 | Aug 13 06:54:04 PM PDT 24 | Aug 13 06:54:18 PM PDT 24 | 116885628 ps | ||
| T2886 | /workspace/coverage/cover_reg_top/79.xbar_smoke.8829433 | Aug 13 06:58:36 PM PDT 24 | Aug 13 06:58:42 PM PDT 24 | 50969374 ps | ||
| T2887 | /workspace/coverage/cover_reg_top/24.xbar_error_random.34275454 | Aug 13 06:52:10 PM PDT 24 | Aug 13 06:52:56 PM PDT 24 | 612362265 ps | ||
| T2888 | /workspace/coverage/cover_reg_top/2.xbar_error_random.3610456021 | Aug 13 06:50:50 PM PDT 24 | Aug 13 06:51:06 PM PDT 24 | 166119063 ps | ||
| T2889 | /workspace/coverage/cover_reg_top/5.xbar_smoke.1922121424 | Aug 13 06:51:03 PM PDT 24 | Aug 13 06:51:12 PM PDT 24 | 202331577 ps | ||
| T2890 | /workspace/coverage/cover_reg_top/93.xbar_smoke.520149754 | Aug 13 07:00:22 PM PDT 24 | Aug 13 07:00:31 PM PDT 24 | 162516677 ps | ||
| T2891 | /workspace/coverage/cover_reg_top/35.xbar_stress_all_with_rand_reset.3818287359 | Aug 13 06:53:17 PM PDT 24 | Aug 13 07:02:38 PM PDT 24 | 2911155320 ps | ||
| T2892 | /workspace/coverage/cover_reg_top/98.xbar_access_same_device.1713377888 | Aug 13 07:01:12 PM PDT 24 | Aug 13 07:01:49 PM PDT 24 | 1019889868 ps | ||
| T2893 | /workspace/coverage/cover_reg_top/15.xbar_smoke_slow_rsp.2124620950 | Aug 13 06:51:13 PM PDT 24 | Aug 13 06:52:35 PM PDT 24 | 4721736081 ps | ||
| T2894 | /workspace/coverage/cover_reg_top/65.xbar_error_and_unmapped_addr.2726395590 | Aug 13 06:56:54 PM PDT 24 | Aug 13 06:57:13 PM PDT 24 | 178120433 ps | ||
| T2895 | /workspace/coverage/cover_reg_top/12.chip_same_csr_outstanding.2286144054 | Aug 13 06:51:16 PM PDT 24 | Aug 13 08:05:45 PM PDT 24 | 27506067650 ps | ||
| T2896 | /workspace/coverage/cover_reg_top/15.xbar_stress_all_with_reset_error.1080550775 | Aug 13 06:51:40 PM PDT 24 | Aug 13 06:52:13 PM PDT 24 | 141491533 ps | ||
| T2897 | /workspace/coverage/cover_reg_top/86.xbar_stress_all.2446003431 | Aug 13 06:59:36 PM PDT 24 | Aug 13 07:02:17 PM PDT 24 | 4357736183 ps | ||
| T2898 | /workspace/coverage/cover_reg_top/81.xbar_smoke_zero_delays.996802341 | Aug 13 06:58:57 PM PDT 24 | Aug 13 06:59:04 PM PDT 24 | 51103670 ps | ||
| T2899 | /workspace/coverage/cover_reg_top/50.xbar_random_large_delays.408161978 | Aug 13 06:55:01 PM PDT 24 | Aug 13 06:59:44 PM PDT 24 | 27808864704 ps | ||
| T2900 | /workspace/coverage/cover_reg_top/98.xbar_stress_all_with_rand_reset.2892430086 | Aug 13 07:01:15 PM PDT 24 | Aug 13 07:01:52 PM PDT 24 | 114014313 ps | ||
| T2901 | /workspace/coverage/cover_reg_top/76.xbar_smoke.2933783652 | Aug 13 06:58:12 PM PDT 24 | Aug 13 06:58:18 PM PDT 24 | 39826821 ps | ||
| T2902 | /workspace/coverage/cover_reg_top/52.xbar_access_same_device_slow_rsp.360233072 | Aug 13 06:55:10 PM PDT 24 | Aug 13 07:14:49 PM PDT 24 | 64802325817 ps | ||
| T2903 | /workspace/coverage/cover_reg_top/86.xbar_smoke_slow_rsp.4198466216 | Aug 13 06:59:29 PM PDT 24 | Aug 13 07:00:52 PM PDT 24 | 5013401477 ps | ||
| T2904 | /workspace/coverage/cover_reg_top/73.xbar_error_random.392164074 | Aug 13 06:57:49 PM PDT 24 | Aug 13 06:59:05 PM PDT 24 | 1938093050 ps | ||
| T2905 | /workspace/coverage/cover_reg_top/4.chip_same_csr_outstanding.859973369 | Aug 13 06:51:00 PM PDT 24 | Aug 13 07:20:02 PM PDT 24 | 16807896150 ps | ||
| T2906 | /workspace/coverage/cover_reg_top/89.xbar_random_large_delays.1804804958 | Aug 13 06:59:56 PM PDT 24 | Aug 13 07:00:56 PM PDT 24 | 6019911277 ps | ||
| T2907 | /workspace/coverage/cover_reg_top/83.xbar_stress_all_with_rand_reset.1186563451 | Aug 13 06:59:14 PM PDT 24 | Aug 13 07:04:49 PM PDT 24 | 2352903989 ps | ||
| T2908 | /workspace/coverage/cover_reg_top/87.xbar_stress_all_with_error.3685755985 | Aug 13 06:59:44 PM PDT 24 | Aug 13 07:09:17 PM PDT 24 | 14609356643 ps | ||
| T2909 | /workspace/coverage/cover_reg_top/78.xbar_random_zero_delays.3922885894 | Aug 13 06:58:28 PM PDT 24 | Aug 13 06:58:47 PM PDT 24 | 198816441 ps | ||
| T2910 | /workspace/coverage/cover_reg_top/85.xbar_smoke_zero_delays.4266035210 | Aug 13 06:59:25 PM PDT 24 | Aug 13 06:59:30 PM PDT 24 | 36102536 ps | ||
| T2911 | /workspace/coverage/cover_reg_top/80.xbar_random_large_delays.1084261887 | Aug 13 06:58:51 PM PDT 24 | Aug 13 07:19:48 PM PDT 24 | 102348734449 ps | ||
| T2912 | /workspace/coverage/cover_reg_top/16.xbar_stress_all_with_reset_error.2542176596 | Aug 13 06:51:18 PM PDT 24 | Aug 13 06:58:31 PM PDT 24 | 2475382195 ps | ||
| T2913 | /workspace/coverage/cover_reg_top/71.xbar_unmapped_addr.3367447850 | Aug 13 06:57:44 PM PDT 24 | Aug 13 06:57:56 PM PDT 24 | 225031914 ps | ||
| T2914 | /workspace/coverage/cover_reg_top/77.xbar_random_large_delays.4248442284 | Aug 13 06:58:21 PM PDT 24 | Aug 13 07:16:03 PM PDT 24 | 93870771635 ps | ||
| T2915 | /workspace/coverage/cover_reg_top/20.xbar_stress_all_with_rand_reset.86358402 | Aug 13 06:51:41 PM PDT 24 | Aug 13 06:54:51 PM PDT 24 | 448614283 ps | ||
| T2916 | /workspace/coverage/cover_reg_top/26.xbar_access_same_device.3693143217 | Aug 13 06:52:22 PM PDT 24 | Aug 13 06:53:37 PM PDT 24 | 851443413 ps | ||
| T2917 | /workspace/coverage/cover_reg_top/33.xbar_stress_all_with_reset_error.3194301836 | Aug 13 06:53:08 PM PDT 24 | Aug 13 07:01:25 PM PDT 24 | 3907203705 ps | ||
| T2918 | /workspace/coverage/cover_reg_top/96.xbar_smoke_large_delays.3971746633 | Aug 13 07:00:44 PM PDT 24 | Aug 13 07:02:34 PM PDT 24 | 10316457424 ps | ||
| T2919 | /workspace/coverage/cover_reg_top/0.xbar_access_same_device.892483384 | Aug 13 06:50:48 PM PDT 24 | Aug 13 06:52:12 PM PDT 24 | 1897452061 ps | ||
| T2920 | /workspace/coverage/cover_reg_top/34.xbar_stress_all.845454859 | Aug 13 06:53:18 PM PDT 24 | Aug 13 06:53:22 PM PDT 24 | 5754985 ps | ||
| T2921 | /workspace/coverage/cover_reg_top/85.xbar_same_source.3796195265 | Aug 13 06:59:22 PM PDT 24 | Aug 13 06:59:56 PM PDT 24 | 487114373 ps | ||
| T2922 | /workspace/coverage/cover_reg_top/84.xbar_random.3065293249 | Aug 13 06:59:29 PM PDT 24 | Aug 13 07:00:07 PM PDT 24 | 421884061 ps | ||
| T2923 | /workspace/coverage/cover_reg_top/75.xbar_random_large_delays.3238775111 | Aug 13 06:58:03 PM PDT 24 | Aug 13 07:11:23 PM PDT 24 | 72648893176 ps | ||
| T2924 | /workspace/coverage/cover_reg_top/40.xbar_smoke_slow_rsp.3427634724 | Aug 13 06:53:46 PM PDT 24 | Aug 13 06:54:46 PM PDT 24 | 3528340616 ps | ||
| T2925 | /workspace/coverage/cover_reg_top/61.xbar_random.2508101030 | Aug 13 06:56:18 PM PDT 24 | Aug 13 06:56:47 PM PDT 24 | 770720947 ps | ||
| T2926 | /workspace/coverage/cover_reg_top/41.xbar_random_large_delays.1965785536 | Aug 13 06:53:54 PM PDT 24 | Aug 13 06:57:17 PM PDT 24 | 20640119767 ps | ||
| T2927 | /workspace/coverage/cover_reg_top/65.xbar_stress_all.276060720 | Aug 13 06:56:55 PM PDT 24 | Aug 13 06:58:16 PM PDT 24 | 1867407091 ps | ||
| T2928 | /workspace/coverage/cover_reg_top/60.xbar_stress_all_with_error.805515883 | Aug 13 06:56:15 PM PDT 24 | Aug 13 06:57:11 PM PDT 24 | 1321176495 ps | ||
| T2929 | /workspace/coverage/cover_reg_top/47.xbar_access_same_device.551573790 | Aug 13 06:54:35 PM PDT 24 | Aug 13 06:55:41 PM PDT 24 | 720026990 ps | ||
| T2930 | /workspace/coverage/cover_reg_top/74.xbar_unmapped_addr.1127080462 | Aug 13 06:58:04 PM PDT 24 | Aug 13 06:58:22 PM PDT 24 | 362463344 ps | ||
| T2931 | /workspace/coverage/cover_reg_top/70.xbar_smoke_zero_delays.3236080825 | Aug 13 06:57:30 PM PDT 24 | Aug 13 06:57:37 PM PDT 24 | 53118438 ps | ||
| T2932 | /workspace/coverage/cover_reg_top/50.xbar_smoke_slow_rsp.2131966120 | Aug 13 06:54:51 PM PDT 24 | Aug 13 06:56:23 PM PDT 24 | 5557778996 ps | ||
| T2933 | /workspace/coverage/cover_reg_top/79.xbar_stress_all.3139148218 | Aug 13 06:58:36 PM PDT 24 | Aug 13 07:13:52 PM PDT 24 | 23482281995 ps | ||
| T2934 | /workspace/coverage/cover_reg_top/11.xbar_stress_all.1866306842 | Aug 13 06:51:11 PM PDT 24 | Aug 13 06:57:25 PM PDT 24 | 4993692851 ps | ||
| T2935 | /workspace/coverage/cover_reg_top/75.xbar_error_random.123374849 | Aug 13 06:58:04 PM PDT 24 | Aug 13 06:58:29 PM PDT 24 | 662374009 ps | ||
| T2936 | /workspace/coverage/cover_reg_top/70.xbar_unmapped_addr.3998352426 | Aug 13 06:57:34 PM PDT 24 | Aug 13 06:58:15 PM PDT 24 | 1013088317 ps | ||
| T2937 | /workspace/coverage/cover_reg_top/20.xbar_smoke_large_delays.3993107139 | Aug 13 06:51:29 PM PDT 24 | Aug 13 06:52:29 PM PDT 24 | 6008936283 ps | ||
| T2938 | /workspace/coverage/cover_reg_top/88.xbar_random_large_delays.1554965270 | Aug 13 06:59:45 PM PDT 24 | Aug 13 07:05:05 PM PDT 24 | 31211111124 ps | ||
| T2939 | /workspace/coverage/cover_reg_top/65.xbar_stress_all_with_reset_error.1682218454 | Aug 13 06:56:55 PM PDT 24 | Aug 13 07:14:29 PM PDT 24 | 21427891074 ps | ||
| T2940 | /workspace/coverage/cover_reg_top/56.xbar_stress_all_with_error.474799124 | Aug 13 06:55:42 PM PDT 24 | Aug 13 07:00:28 PM PDT 24 | 7229884877 ps | ||
| T2941 | /workspace/coverage/cover_reg_top/59.xbar_smoke_large_delays.1491420088 | Aug 13 06:56:02 PM PDT 24 | Aug 13 06:57:25 PM PDT 24 | 7842465590 ps | ||
| T2942 | /workspace/coverage/cover_reg_top/45.xbar_access_same_device.3428653253 | Aug 13 06:54:25 PM PDT 24 | Aug 13 06:55:20 PM PDT 24 | 557650015 ps | ||
| T2943 | /workspace/coverage/cover_reg_top/57.xbar_error_random.1304535672 | Aug 13 06:55:48 PM PDT 24 | Aug 13 06:55:54 PM PDT 24 | 38206657 ps | ||
| T28 | /workspace/coverage/pad_ctrl_test_mode/1.chip_padctrl_attributes.2422837402 | Aug 13 06:31:51 PM PDT 24 | Aug 13 06:36:57 PM PDT 24 | 5263622628 ps | ||
| T29 | /workspace/coverage/pad_ctrl_test_mode/5.chip_padctrl_attributes.545032498 | Aug 13 06:32:17 PM PDT 24 | Aug 13 06:36:33 PM PDT 24 | 4201993156 ps | ||
| T30 | /workspace/coverage/pad_ctrl_test_mode/0.chip_padctrl_attributes.617184267 | Aug 13 06:31:58 PM PDT 24 | Aug 13 06:36:23 PM PDT 24 | 4521223330 ps | ||
| T198 | /workspace/coverage/pad_ctrl_test_mode/2.chip_padctrl_attributes.3444893650 | Aug 13 06:32:02 PM PDT 24 | Aug 13 06:37:06 PM PDT 24 | 5159243328 ps | ||
| T199 | /workspace/coverage/pad_ctrl_test_mode/6.chip_padctrl_attributes.425694906 | Aug 13 06:31:51 PM PDT 24 | Aug 13 06:37:21 PM PDT 24 | 5579820551 ps | ||
| T200 | /workspace/coverage/pad_ctrl_test_mode/7.chip_padctrl_attributes.1487253681 | Aug 13 06:31:52 PM PDT 24 | Aug 13 06:37:03 PM PDT 24 | 4837907696 ps | ||
| T201 | /workspace/coverage/pad_ctrl_test_mode/4.chip_padctrl_attributes.2882537077 | Aug 13 06:31:50 PM PDT 24 | Aug 13 06:35:42 PM PDT 24 | 3741941530 ps | ||
| T202 | /workspace/coverage/pad_ctrl_test_mode/9.chip_padctrl_attributes.2321294617 | Aug 13 06:31:50 PM PDT 24 | Aug 13 06:36:06 PM PDT 24 | 5342585530 ps | ||
| T203 | /workspace/coverage/pad_ctrl_test_mode/8.chip_padctrl_attributes.495014914 | Aug 13 06:32:03 PM PDT 24 | Aug 13 06:36:07 PM PDT 24 | 4676077876 ps | ||
| T204 | /workspace/coverage/pad_ctrl_test_mode/3.chip_padctrl_attributes.1029802104 | Aug 13 06:31:55 PM PDT 24 | Aug 13 06:36:21 PM PDT 24 | 5132507834 ps |
| Test location | /workspace/coverage/default/5.chip_sw_all_escalation_resets.2795141087 |
| Short name | T61 |
| Test name | |
| Test status | |
| Simulation time | 4525981836 ps |
| CPU time | 558.75 seconds |
| Started | Aug 13 07:34:19 PM PDT 24 |
| Finished | Aug 13 07:43:38 PM PDT 24 |
| Peak memory | 650660 kb |
| Host | smart-61e468d6-646f-4b4f-aa68-2af2c3a4fa09 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 2795141087 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.chip_sw_all_escalation_resets.2795141087 |
| Directory | /workspace/5.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/cover_reg_top/17.chip_csr_rw.3710489270 |
| Short name | T150 |
| Test name | |
| Test status | |
| Simulation time | 4893750051 ps |
| CPU time | 461.48 seconds |
| Started | Aug 13 06:51:33 PM PDT 24 |
| Finished | Aug 13 06:59:15 PM PDT 24 |
| Peak memory | 598672 kb |
| Host | smart-b6190170-771f-49e7-84fb-39293e7882f2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3710489270 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.chip_csr_rw.3710489270 |
| Directory | /workspace/17.chip_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/37.xbar_stress_all.1324996543 |
| Short name | T131 |
| Test name | |
| Test status | |
| Simulation time | 11794955492 ps |
| CPU time | 455.43 seconds |
| Started | Aug 13 06:53:25 PM PDT 24 |
| Finished | Aug 13 07:01:01 PM PDT 24 |
| Peak memory | 575892 kb |
| Host | smart-49b76108-4c03-441f-ae3c-4f55d33c3cae |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1324996543 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.xbar_stress_all.1324996543 |
| Directory | /workspace/37.xbar_stress_all/latest |
| Test location | /workspace/coverage/default/0.chip_plic_all_irqs_20.3000670873 |
| Short name | T325 |
| Test name | |
| Test status | |
| Simulation time | 5158392216 ps |
| CPU time | 935.75 seconds |
| Started | Aug 13 07:12:47 PM PDT 24 |
| Finished | Aug 13 07:28:23 PM PDT 24 |
| Peak memory | 610576 kb |
| Host | smart-6aaf1641-377d-486f-a497-bda447895d38 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=plic_all_irqs_test_20:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3000670873 -assert nopostproc +UVM_TESTN AME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log / dev/null -cm_name 0.chip_plic_all_irqs_20.3000670873 |
| Directory | /workspace/0.chip_plic_all_irqs_20/latest |
| Test location | /workspace/coverage/cover_reg_top/68.xbar_access_same_device_slow_rsp.2600239791 |
| Short name | T869 |
| Test name | |
| Test status | |
| Simulation time | 123472903933 ps |
| CPU time | 2289.19 seconds |
| Started | Aug 13 06:57:08 PM PDT 24 |
| Finished | Aug 13 07:35:17 PM PDT 24 |
| Peak memory | 575736 kb |
| Host | smart-090f33ef-410b-40ff-9cca-6143aa90bffa |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2600239791 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 68.xbar_access_same_ device_slow_rsp.2600239791 |
| Directory | /workspace/68.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/default/2.chip_sw_power_virus.587022283 |
| Short name | T11 |
| Test name | |
| Test status | |
| Simulation time | 6160513090 ps |
| CPU time | 1298.18 seconds |
| Started | Aug 13 07:36:10 PM PDT 24 |
| Finished | Aug 13 07:57:49 PM PDT 24 |
| Peak memory | 625476 kb |
| Host | smart-ecb45386-5330-4a0c-b1ec-09998a0fc2ff |
| User | root |
| Command | /workspace/default/simv +rng_srate_value_min=15 +rng_srate_value_max=20 +sw_test_timeout_ns=400_000_000 +use_otp_image=OtpTypeCustom +accelerate_cold_ power_up_time=3 +accelerate_regulators_power_up_time=2 +sw_build_device=sim_dv +sw_images=power_virus_systemtest:1:new_rules,power_virus_systemtes t_otp_img_rma:4,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d v/tools/sim.tcl +ntb_random_seed=587022283 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_power_virus_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_power_virus.587022283 |
| Directory | /workspace/2.chip_sw_power_virus/latest |
| Test location | /workspace/coverage/default/2.rom_e2e_self_hash.3766307634 |
| Short name | T44 |
| Test name | |
| Test status | |
| Simulation time | 25911556120 ps |
| CPU time | 5506.33 seconds |
| Started | Aug 13 07:37:08 PM PDT 24 |
| Finished | Aug 13 09:08:55 PM PDT 24 |
| Peak memory | 610908 kb |
| Host | smart-b11bd5bb-2725-4c5f-b37f-16e91a7ad6d2 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=200_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=rom_e2e_self_hash_test:1:new_r ules,otp_img_sigverify_spx_prod:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3766307634 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_e2e_self_hash.3766307634 |
| Directory | /workspace/2.rom_e2e_self_hash/latest |
| Test location | /workspace/coverage/pad_ctrl_test_mode/1.chip_padctrl_attributes.2422837402 |
| Short name | T28 |
| Test name | |
| Test status | |
| Simulation time | 5263622628 ps |
| CPU time | 305.93 seconds |
| Started | Aug 13 06:31:51 PM PDT 24 |
| Finished | Aug 13 06:36:57 PM PDT 24 |
| Peak memory | 655824 kb |
| Host | smart-74d57960-2fc0-4c12-a5bc-3cdcf746fab9 |
| User | root |
| Command | /workspace/pad_ctrl_test_mode/simv +use_otp_image=OtpTypeLcStProd +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2422837402 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TE ST_SEQ=chip_padctrl_attributes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/pad_ctrl_test_mode.vdb -cm_log /dev/ null -cm_name 1.chip_padctrl_attributes.2422837402 |
| Directory | /workspace/1.chip_padctrl_attributes/latest |
| Test location | /workspace/coverage/cover_reg_top/24.xbar_access_same_device_slow_rsp.98870203 |
| Short name | T870 |
| Test name | |
| Test status | |
| Simulation time | 114125264233 ps |
| CPU time | 2049.78 seconds |
| Started | Aug 13 06:52:10 PM PDT 24 |
| Finished | Aug 13 07:26:20 PM PDT 24 |
| Peak memory | 575620 kb |
| Host | smart-1ce7baf6-02e9-4af4-94c4-81e435a5be87 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=98870203 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.xbar_access_same_de vice_slow_rsp.98870203 |
| Directory | /workspace/24.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/default/2.chip_sw_keymgr_sideload_kmac.3094056722 |
| Short name | T128 |
| Test name | |
| Test status | |
| Simulation time | 6847270304 ps |
| CPU time | 955.2 seconds |
| Started | Aug 13 07:30:28 PM PDT 24 |
| Finished | Aug 13 07:46:23 PM PDT 24 |
| Peak memory | 610616 kb |
| Host | smart-d6cd7e17-163b-40a7-8068-fafe34a602be |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=20_000_000 +sw_build_device=sim_dv +sw_images=keymgr_sideload_kmac_test:1:new_rules,test_rom:0 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30940 56722 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_keymgr_sideload_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_keymgr_sideload_kmac.3094056722 |
| Directory | /workspace/2.chip_sw_keymgr_sideload_kmac/latest |
| Test location | /workspace/coverage/cover_reg_top/96.xbar_access_same_device_slow_rsp.3736345466 |
| Short name | T524 |
| Test name | |
| Test status | |
| Simulation time | 128303557469 ps |
| CPU time | 2440.52 seconds |
| Started | Aug 13 07:00:51 PM PDT 24 |
| Finished | Aug 13 07:41:32 PM PDT 24 |
| Peak memory | 575696 kb |
| Host | smart-7100367e-8557-42d4-9a93-d930f9a87b37 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3736345466 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 96.xbar_access_same_ device_slow_rsp.3736345466 |
| Directory | /workspace/96.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/default/2.chip_jtag_csr_rw.4075856808 |
| Short name | T52 |
| Test name | |
| Test status | |
| Simulation time | 20625063596 ps |
| CPU time | 2248.04 seconds |
| Started | Aug 13 07:22:07 PM PDT 24 |
| Finished | Aug 13 07:59:35 PM PDT 24 |
| Peak memory | 608600 kb |
| Host | smart-679cfc28-c72b-4aff-b52c-832b2d36c707 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +csr_rw +create_jtag_riscv_map=1 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4075856808 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_T EST_SEQ=chip_jtag_csr_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.c hip_jtag_csr_rw.4075856808 |
| Directory | /workspace/2.chip_jtag_csr_rw/latest |
| Test location | /workspace/coverage/default/1.chip_sw_lc_walkthrough_rma.1415314010 |
| Short name | T6 |
| Test name | |
| Test status | |
| Simulation time | 45476640120 ps |
| CPU time | 5668.65 seconds |
| Started | Aug 13 07:13:37 PM PDT 24 |
| Finished | Aug 13 08:48:06 PM PDT 24 |
| Peak memory | 624868 kb |
| Host | smart-7489ab88-07c9-42fb-8f1e-e261419cbcf6 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStRaw +dest_dec_state=DecLcStRma +flash_program_latency=5 +sw_test_timeout_ns=200_000_000 +sw_build_de vice=sim_dv +sw_images=lc_walkthrough_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1415314010 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=c hip_sw_lc_walkthrough_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip _sw_lc_walkthrough_rma.1415314010 |
| Directory | /workspace/1.chip_sw_lc_walkthrough_rma/latest |
| Test location | /workspace/coverage/cover_reg_top/18.xbar_access_same_device_slow_rsp.3388515011 |
| Short name | T740 |
| Test name | |
| Test status | |
| Simulation time | 154563640229 ps |
| CPU time | 2725.11 seconds |
| Started | Aug 13 06:51:35 PM PDT 24 |
| Finished | Aug 13 07:37:00 PM PDT 24 |
| Peak memory | 575596 kb |
| Host | smart-2f46c362-e7bd-4b4a-b059-b77e98177ffc |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3388515011 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.xbar_access_same_ device_slow_rsp.3388515011 |
| Directory | /workspace/18.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/34.xbar_stress_all_with_error.1873760358 |
| Short name | T726 |
| Test name | |
| Test status | |
| Simulation time | 14640082504 ps |
| CPU time | 480.58 seconds |
| Started | Aug 13 06:53:20 PM PDT 24 |
| Finished | Aug 13 07:01:21 PM PDT 24 |
| Peak memory | 575836 kb |
| Host | smart-603c1446-ea51-4a15-8a98-d3d3c78e0ad2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1873760358 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.xbar_stress_all_with_error.1873760358 |
| Directory | /workspace/34.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/default/2.chip_plic_all_irqs_0.3469324648 |
| Short name | T326 |
| Test name | |
| Test status | |
| Simulation time | 6825311784 ps |
| CPU time | 970.09 seconds |
| Started | Aug 13 07:31:24 PM PDT 24 |
| Finished | Aug 13 07:47:34 PM PDT 24 |
| Peak memory | 610684 kb |
| Host | smart-d977d45b-330a-4ca6-aff0-8a24efeed4e6 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=plic_all_irqs_test_0:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3469324648 -assert nopostproc +UVM_TESTNA ME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 2.chip_plic_all_irqs_0.3469324648 |
| Directory | /workspace/2.chip_plic_all_irqs_0/latest |
| Test location | /workspace/coverage/default/2.chip_sw_pwrmgr_deep_sleep_all_wake_ups.1982254544 |
| Short name | T18 |
| Test name | |
| Test status | |
| Simulation time | 22918380570 ps |
| CPU time | 1731.85 seconds |
| Started | Aug 13 07:31:08 PM PDT 24 |
| Finished | Aug 13 08:00:00 PM PDT 24 |
| Peak memory | 612556 kb |
| Host | smart-1dfccbe7-c2cc-4349-9e44-c57451643748 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=pwrmgr_deep_sleep_all_wake_ups:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 1982254544 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_pwrmgr_deep_sleep_all_wake_ups_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_pwrmgr_deep_sleep_all_wake_ups.1982254544 |
| Directory | /workspace/2.chip_sw_pwrmgr_deep_sleep_all_wake_ups/latest |
| Test location | /workspace/coverage/default/2.chip_sw_sleep_pin_mio_dio_val.2784896510 |
| Short name | T8 |
| Test name | |
| Test status | |
| Simulation time | 3174185073 ps |
| CPU time | 389.7 seconds |
| Started | Aug 13 07:24:33 PM PDT 24 |
| Finished | Aug 13 07:31:04 PM PDT 24 |
| Peak memory | 611444 kb |
| Host | smart-5e3b6bd9-3ea0-4a3d-8b82-2c34bea877a8 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStProd +sw_build_device=sim_dv +sw_images=sleep_pin_mio_dio_val_test:1:new_rules,test_rom:0 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2784 896510 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sleep_pin_mio_dio_val_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_sleep_pin_mio_dio_val.2784896510 |
| Directory | /workspace/2.chip_sw_sleep_pin_mio_dio_val/latest |
| Test location | /workspace/coverage/default/0.chip_sw_rv_core_ibex_address_translation.571863573 |
| Short name | T189 |
| Test name | |
| Test status | |
| Simulation time | 3049254304 ps |
| CPU time | 270.09 seconds |
| Started | Aug 13 07:13:36 PM PDT 24 |
| Finished | Aug 13 07:18:07 PM PDT 24 |
| Peak memory | 610488 kb |
| Host | smart-3a856edd-edcd-4081-a464-658ea29ad57f |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=7_000_000 +sw_build_device=sim_dv +sw_images=rv_core_ibex_address_translation_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random _seed=571863573 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_rv_core_ibex_address_translation.571863573 |
| Directory | /workspace/0.chip_sw_rv_core_ibex_address_translation/latest |
| Test location | /workspace/coverage/cover_reg_top/67.xbar_access_same_device_slow_rsp.3725216523 |
| Short name | T893 |
| Test name | |
| Test status | |
| Simulation time | 140274488954 ps |
| CPU time | 2362.53 seconds |
| Started | Aug 13 06:57:03 PM PDT 24 |
| Finished | Aug 13 07:36:25 PM PDT 24 |
| Peak memory | 575808 kb |
| Host | smart-92e0d47f-395c-4a9c-b48c-038a4b6e4dfb |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3725216523 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 67.xbar_access_same_ device_slow_rsp.3725216523 |
| Directory | /workspace/67.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/88.xbar_error_and_unmapped_addr.1971908150 |
| Short name | T464 |
| Test name | |
| Test status | |
| Simulation time | 311150879 ps |
| CPU time | 33.67 seconds |
| Started | Aug 13 06:59:56 PM PDT 24 |
| Finished | Aug 13 07:00:30 PM PDT 24 |
| Peak memory | 575748 kb |
| Host | smart-79fad865-114f-4ee1-83f0-e6699c4a3be4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1971908150 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 88.xbar_error_and_unmapped_add r.1971908150 |
| Directory | /workspace/88.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/default/32.chip_sw_alert_handler_lpg_sleep_mode_alerts.808823475 |
| Short name | T5 |
| Test name | |
| Test status | |
| Simulation time | 4548659160 ps |
| CPU time | 481.55 seconds |
| Started | Aug 13 07:36:30 PM PDT 24 |
| Finished | Aug 13 07:44:33 PM PDT 24 |
| Peak memory | 649876 kb |
| Host | smart-8e2973d6-95a8-4c28-bb8c-e2dfa7c56bf9 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=808823475 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all _escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.chip_s w_alert_handler_lpg_sleep_mode_alerts.808823475 |
| Directory | /workspace/32.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/cover_reg_top/12.chip_tl_errors.1945187114 |
| Short name | T566 |
| Test name | |
| Test status | |
| Simulation time | 3790523080 ps |
| CPU time | 326.47 seconds |
| Started | Aug 13 06:51:11 PM PDT 24 |
| Finished | Aug 13 06:56:38 PM PDT 24 |
| Peak memory | 598324 kb |
| Host | smart-b7317313-7928-4dcf-a54f-e6237f564f17 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1945187114 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.chip_tl_errors.1945187114 |
| Directory | /workspace/12.chip_tl_errors/latest |
| Test location | /workspace/coverage/default/1.chip_sw_alert_test.3353519822 |
| Short name | T46 |
| Test name | |
| Test status | |
| Simulation time | 2822047740 ps |
| CPU time | 390.43 seconds |
| Started | Aug 13 07:17:09 PM PDT 24 |
| Finished | Aug 13 07:23:40 PM PDT 24 |
| Peak memory | 610360 kb |
| Host | smart-d1173321-5c09-4df5-94ef-00dc64df81de |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=alert_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3353519822 -assert nopostproc +UVM_TESTNAME=chip_ba se_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 1.chip_sw_alert_test.3353519822 |
| Directory | /workspace/1.chip_sw_alert_test/latest |
| Test location | /workspace/coverage/default/2.chip_sw_gpio.3368522160 |
| Short name | T25 |
| Test name | |
| Test status | |
| Simulation time | 3876589268 ps |
| CPU time | 629.41 seconds |
| Started | Aug 13 07:24:06 PM PDT 24 |
| Finished | Aug 13 07:34:35 PM PDT 24 |
| Peak memory | 609904 kb |
| Host | smart-2206a6f9-47a7-4b4d-944f-e2fc25aa9ebb |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=gpio_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3368522160 -assert nopostproc +UVM_TESTNAME=chip_bas e_test +UVM_TEST_SEQ=chip_sw_gpio_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm _name 2.chip_sw_gpio.3368522160 |
| Directory | /workspace/2.chip_sw_gpio/latest |
| Test location | /workspace/coverage/cover_reg_top/81.xbar_stress_all_with_rand_reset.1304061264 |
| Short name | T473 |
| Test name | |
| Test status | |
| Simulation time | 8515522545 ps |
| CPU time | 634.85 seconds |
| Started | Aug 13 06:59:16 PM PDT 24 |
| Finished | Aug 13 07:09:51 PM PDT 24 |
| Peak memory | 575220 kb |
| Host | smart-de4f5e61-7830-463b-9e35-474ab1140b1e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1304061264 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 81.xbar_stress_all _with_rand_reset.1304061264 |
| Directory | /workspace/81.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/1.chip_plic_all_irqs_10.3661476053 |
| Short name | T159 |
| Test name | |
| Test status | |
| Simulation time | 3918962938 ps |
| CPU time | 534.49 seconds |
| Started | Aug 13 07:18:32 PM PDT 24 |
| Finished | Aug 13 07:27:26 PM PDT 24 |
| Peak memory | 610368 kb |
| Host | smart-467afe33-2987-4396-9b8f-239d820315b0 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=plic_all_irqs_test_10:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3661476053 -assert nopostproc +UVM_TESTN AME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log / dev/null -cm_name 1.chip_plic_all_irqs_10.3661476053 |
| Directory | /workspace/1.chip_plic_all_irqs_10/latest |
| Test location | /workspace/coverage/cover_reg_top/19.xbar_stress_all_with_reset_error.3724978789 |
| Short name | T889 |
| Test name | |
| Test status | |
| Simulation time | 2496267143 ps |
| CPU time | 220.85 seconds |
| Started | Aug 13 06:51:36 PM PDT 24 |
| Finished | Aug 13 06:55:17 PM PDT 24 |
| Peak memory | 576576 kb |
| Host | smart-c88f7130-c283-4916-9195-2ff028d17418 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3724978789 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.xbar_stress_al l_with_reset_error.3724978789 |
| Directory | /workspace/19.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/56.xbar_random_large_delays.332482913 |
| Short name | T557 |
| Test name | |
| Test status | |
| Simulation time | 43788711695 ps |
| CPU time | 468.56 seconds |
| Started | Aug 13 06:55:43 PM PDT 24 |
| Finished | Aug 13 07:03:32 PM PDT 24 |
| Peak memory | 575788 kb |
| Host | smart-ca7eeb0b-95ce-4961-80f3-d63870755803 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=332482913 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 56.xbar_random_large_delays.332482913 |
| Directory | /workspace/56.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/default/0.chip_sw_flash_rma_unlocked.1912031896 |
| Short name | T190 |
| Test name | |
| Test status | |
| Simulation time | 43479315067 ps |
| CPU time | 4646.83 seconds |
| Started | Aug 13 07:13:53 PM PDT 24 |
| Finished | Aug 13 08:31:22 PM PDT 24 |
| Peak memory | 624848 kb |
| Host | smart-d14654b0-aaf5-4af4-b29e-4224f848dad2 |
| User | root |
| Command | /workspace/default/simv +flash_program_latency=5 +sw_test_timeout_ns=150_000_000 +sw_build_device=sim_dv +sw_images=flash_rma_unlocked_test:0:test_in_ rom:new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t cl +ntb_random_seed=1912031896 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_flash_rma_unlocked_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_flash_rma_unlocked.1912031896 |
| Directory | /workspace/0.chip_sw_flash_rma_unlocked/latest |
| Test location | /workspace/coverage/cover_reg_top/3.chip_same_csr_outstanding.4130156650 |
| Short name | T387 |
| Test name | |
| Test status | |
| Simulation time | 28861236176 ps |
| CPU time | 4099.78 seconds |
| Started | Aug 13 06:50:34 PM PDT 24 |
| Finished | Aug 13 07:58:55 PM PDT 24 |
| Peak memory | 592976 kb |
| Host | smart-1a597bd4-10e4-48da-b587-fb07a76a09b5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +run_same_csr_outstanding +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4130156650 -assert nopostproc +UVM_TE STNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb - cm_log /dev/null -cm_name 3.chip_same_csr_outstanding.4130156650 |
| Directory | /workspace/3.chip_same_csr_outstanding/latest |
| Test location | /workspace/coverage/default/1.chip_sw_csrng_edn_concurrency_reduced_freq.1683748036 |
| Short name | T113 |
| Test name | |
| Test status | |
| Simulation time | 148346178621 ps |
| CPU time | 20034.8 seconds |
| Started | Aug 13 07:20:42 PM PDT 24 |
| Finished | Aug 14 12:54:40 AM PDT 24 |
| Peak memory | 611156 kb |
| Host | smart-b2da8828-40c3-40fb-bb45-943ada303532 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=360_000_000 +rng_srate_value_min=15 +rng_srate_value_max=20 +cal_sys_clk_70mhz=1 +en_jitter=1 +accelerate_ cold_power_up_time=3 +accelerate_regulators_power_up_time=2 +sw_build_device=sim_dv +sw_images=csrng_edn_concurrency_test:1:new_rules,test_rom:0 + cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_ seed=1683748036 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_csrng_edn_concurrency_reduced_freq.1683748036 |
| Directory | /workspace/1.chip_sw_csrng_edn_concurrency_reduced_freq/latest |
| Test location | /workspace/coverage/default/1.chip_sw_sleep_pin_mio_dio_val.399825295 |
| Short name | T10 |
| Test name | |
| Test status | |
| Simulation time | 2900174877 ps |
| CPU time | 283.2 seconds |
| Started | Aug 13 07:14:50 PM PDT 24 |
| Finished | Aug 13 07:19:33 PM PDT 24 |
| Peak memory | 611428 kb |
| Host | smart-379b4382-876c-476e-b4d6-77e37d3c94c9 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStProd +sw_build_device=sim_dv +sw_images=sleep_pin_mio_dio_val_test:1:new_rules,test_rom:0 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3998 25295 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sleep_pin_mio_dio_val_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_sleep_pin_mio_dio_val.399825295 |
| Directory | /workspace/1.chip_sw_sleep_pin_mio_dio_val/latest |
| Test location | /workspace/coverage/default/0.chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup.56405673 |
| Short name | T141 |
| Test name | |
| Test status | |
| Simulation time | 5724444652 ps |
| CPU time | 617.79 seconds |
| Started | Aug 13 07:12:43 PM PDT 24 |
| Finished | Aug 13 07:23:02 PM PDT 24 |
| Peak memory | 610684 kb |
| Host | smart-221b845d-9742-4202-b216-773934b4983b |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=8_000_000 +sw_build_device=sim_dv +sw_images=sensor_ctrl_wakeup_test:1:new_rules,test_rom:0 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=56405673 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/ coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup.56405673 |
| Directory | /workspace/0.chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup/latest |
| Test location | /workspace/coverage/cover_reg_top/81.xbar_stress_all.1487170890 |
| Short name | T429 |
| Test name | |
| Test status | |
| Simulation time | 13912558868 ps |
| CPU time | 557.28 seconds |
| Started | Aug 13 06:58:59 PM PDT 24 |
| Finished | Aug 13 07:08:16 PM PDT 24 |
| Peak memory | 575708 kb |
| Host | smart-d694d108-27fd-4965-accf-25bae8797f51 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1487170890 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 81.xbar_stress_all.1487170890 |
| Directory | /workspace/81.xbar_stress_all/latest |
| Test location | /workspace/coverage/default/2.chip_sw_sram_ctrl_scrambled_access.4009090730 |
| Short name | T3 |
| Test name | |
| Test status | |
| Simulation time | 4669694450 ps |
| CPU time | 696.5 seconds |
| Started | Aug 13 07:28:19 PM PDT 24 |
| Finished | Aug 13 07:39:56 PM PDT 24 |
| Peak memory | 611332 kb |
| Host | smart-d900de51-eb09-493a-9dec-369d981f5e9f |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=12_000_000 +en_scb_tl_err_chk=0 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=sram _ctrl_scrambled_access_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4009090730 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sram_ctr l_scrambled_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw _sram_ctrl_scrambled_access.4009090730 |
| Directory | /workspace/2.chip_sw_sram_ctrl_scrambled_access/latest |
| Test location | /workspace/coverage/default/2.chip_sw_exit_test_unlocked_bootstrap.618082728 |
| Short name | T7 |
| Test name | |
| Test status | |
| Simulation time | 58280580768 ps |
| CPU time | 10399.4 seconds |
| Started | Aug 13 07:23:18 PM PDT 24 |
| Finished | Aug 13 10:16:39 PM PDT 24 |
| Peak memory | 625200 kb |
| Host | smart-25ee2d52-1fd1-4f81-87c4-88789ffd5c27 |
| User | root |
| Command | /workspace/default/simv +flash_program_latency=5 +sw_test_timeout_ns=150_000_000 +sw_build_device=sim_dv +sw_images=exit_test_unlocked_bootstrap:1:new _rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/s im.tcl +ntb_random_seed=618082728 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_exit_test_unlocked_bootstrap_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_exit_test_unlocked_bootstrap.618082728 |
| Directory | /workspace/2.chip_sw_exit_test_unlocked_bootstrap/latest |
| Test location | /workspace/coverage/default/0.chip_sw_alert_handler_entropy.4264546333 |
| Short name | T80 |
| Test name | |
| Test status | |
| Simulation time | 4268574959 ps |
| CPU time | 454.48 seconds |
| Started | Aug 13 07:12:47 PM PDT 24 |
| Finished | Aug 13 07:20:22 PM PDT 24 |
| Peak memory | 610132 kb |
| Host | smart-4b946de0-b94f-4d0f-a3f9-2a8542a8ce69 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=alert_handler_entropy_test:1:new_rules,test_ro m:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=4264546333 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_alert_handler_entropy.4264546333 |
| Directory | /workspace/0.chip_sw_alert_handler_entropy/latest |
| Test location | /workspace/coverage/cover_reg_top/93.xbar_access_same_device_slow_rsp.2672059678 |
| Short name | T1924 |
| Test name | |
| Test status | |
| Simulation time | 156716322288 ps |
| CPU time | 2792.29 seconds |
| Started | Aug 13 07:00:24 PM PDT 24 |
| Finished | Aug 13 07:46:57 PM PDT 24 |
| Peak memory | 575852 kb |
| Host | smart-14cd6653-edc1-4ed6-b9a9-a4bdb5190354 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2672059678 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 93.xbar_access_same_ device_slow_rsp.2672059678 |
| Directory | /workspace/93.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/default/1.chip_sw_pwrmgr_normal_sleep_all_reset_reqs.4167164466 |
| Short name | T261 |
| Test name | |
| Test status | |
| Simulation time | 10334364860 ps |
| CPU time | 1480.08 seconds |
| Started | Aug 13 07:15:58 PM PDT 24 |
| Finished | Aug 13 07:40:38 PM PDT 24 |
| Peak memory | 612256 kb |
| Host | smart-7eea33d9-7c17-4997-91b9-7e7ca6d92c89 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_normal_sleep_all_reset_reqs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4167164466 -assert nop ostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_deep_sleep_all_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_pwrmgr_normal_sleep_all_reset_reqs.4167164466 |
| Directory | /workspace/1.chip_sw_pwrmgr_normal_sleep_all_reset_reqs/latest |
| Test location | /workspace/coverage/cover_reg_top/23.chip_tl_errors.3199304601 |
| Short name | T572 |
| Test name | |
| Test status | |
| Simulation time | 4901898178 ps |
| CPU time | 449.66 seconds |
| Started | Aug 13 06:52:07 PM PDT 24 |
| Finished | Aug 13 06:59:37 PM PDT 24 |
| Peak memory | 603484 kb |
| Host | smart-fbc66adc-5887-4d6a-a1f3-bb0243a9d929 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3199304601 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.chip_tl_errors.3199304601 |
| Directory | /workspace/23.chip_tl_errors/latest |
| Test location | /workspace/coverage/default/0.chip_sw_all_escalation_resets.2032375134 |
| Short name | T170 |
| Test name | |
| Test status | |
| Simulation time | 5625990748 ps |
| CPU time | 532.68 seconds |
| Started | Aug 13 07:07:53 PM PDT 24 |
| Finished | Aug 13 07:16:45 PM PDT 24 |
| Peak memory | 620672 kb |
| Host | smart-2f1a1358-a118-4e39-b6f1-cb83bb69de1b |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 2032375134 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_all_escalation_resets.2032375134 |
| Directory | /workspace/0.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/cover_reg_top/2.xbar_stress_all_with_error.3565451797 |
| Short name | T864 |
| Test name | |
| Test status | |
| Simulation time | 15466446396 ps |
| CPU time | 583.31 seconds |
| Started | Aug 13 06:50:47 PM PDT 24 |
| Finished | Aug 13 07:00:30 PM PDT 24 |
| Peak memory | 575740 kb |
| Host | smart-5ce6fb9a-fd5b-4e83-93e2-bbf261f73a32 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3565451797 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.xbar_stress_all_with_error.3565451797 |
| Directory | /workspace/2.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/default/0.chip_sw_lc_walkthrough_prod.68550076 |
| Short name | T240 |
| Test name | |
| Test status | |
| Simulation time | 50834619900 ps |
| CPU time | 5517.45 seconds |
| Started | Aug 13 07:09:33 PM PDT 24 |
| Finished | Aug 13 08:41:32 PM PDT 24 |
| Peak memory | 621016 kb |
| Host | smart-3593a425-4f10-4c93-ba0a-a21929ab038b |
| User | root |
| Command | /workspace/default/simv +flash_program_latency=5 +use_otp_image=OtpTypeLcStRaw +dest_dec_state=DecLcStProd +sw_test_timeout_ns=200_000_000 +sw_build_d evice=sim_dv +sw_images=lc_walkthrough_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=68550076 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=ch ip_sw_lc_walkthrough_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_ sw_lc_walkthrough_prod.68550076 |
| Directory | /workspace/0.chip_sw_lc_walkthrough_prod/latest |
| Test location | /workspace/coverage/default/1.chip_sw_sysrst_ctrl_reset.237230514 |
| Short name | T20 |
| Test name | |
| Test status | |
| Simulation time | 25205845000 ps |
| CPU time | 1739.75 seconds |
| Started | Aug 13 07:15:22 PM PDT 24 |
| Finished | Aug 13 07:44:22 PM PDT 24 |
| Peak memory | 614916 kb |
| Host | smart-a971c642-94fe-48e2-8fd0-3593898a7b89 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=36_000_000 +sw_build_device=sim_dv +sw_images=sysrst_ctrl_reset_test:1:new_rules,test_rom:0 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23723051 4 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sysrst_ctrl_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_sysrst_ctrl_reset.237230514 |
| Directory | /workspace/1.chip_sw_sysrst_ctrl_reset/latest |
| Test location | /workspace/coverage/default/0.chip_sw_sleep_pin_mio_dio_val.3676659456 |
| Short name | T9 |
| Test name | |
| Test status | |
| Simulation time | 3131418029 ps |
| CPU time | 421.52 seconds |
| Started | Aug 13 07:11:18 PM PDT 24 |
| Finished | Aug 13 07:18:20 PM PDT 24 |
| Peak memory | 610432 kb |
| Host | smart-ca6cbf1b-0484-48e8-b6e2-561be88a3859 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStProd +sw_build_device=sim_dv +sw_images=sleep_pin_mio_dio_val_test:1:new_rules,test_rom:0 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3676 659456 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sleep_pin_mio_dio_val_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_sleep_pin_mio_dio_val.3676659456 |
| Directory | /workspace/0.chip_sw_sleep_pin_mio_dio_val/latest |
| Test location | /workspace/coverage/cover_reg_top/88.xbar_stress_all_with_rand_reset.1174263828 |
| Short name | T469 |
| Test name | |
| Test status | |
| Simulation time | 13381738337 ps |
| CPU time | 822.07 seconds |
| Started | Aug 13 06:59:54 PM PDT 24 |
| Finished | Aug 13 07:13:37 PM PDT 24 |
| Peak memory | 576548 kb |
| Host | smart-1d28f4cb-d674-4596-bbff-86b644a33e03 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1174263828 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 88.xbar_stress_all _with_rand_reset.1174263828 |
| Directory | /workspace/88.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/0.chip_jtag_csr_rw.138050510 |
| Short name | T213 |
| Test name | |
| Test status | |
| Simulation time | 11619074566 ps |
| CPU time | 1386.53 seconds |
| Started | Aug 13 07:02:45 PM PDT 24 |
| Finished | Aug 13 07:25:52 PM PDT 24 |
| Peak memory | 604444 kb |
| Host | smart-acfbd026-4c9e-4cfb-a662-cdf98c36bc30 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +csr_rw +create_jtag_riscv_map=1 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=138050510 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TE ST_SEQ=chip_jtag_csr_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.ch ip_jtag_csr_rw.138050510 |
| Directory | /workspace/0.chip_jtag_csr_rw/latest |
| Test location | /workspace/coverage/default/2.chip_sw_flash_ctrl_lc_rw_en.1624929982 |
| Short name | T178 |
| Test name | |
| Test status | |
| Simulation time | 4235216200 ps |
| CPU time | 528.06 seconds |
| Started | Aug 13 07:24:16 PM PDT 24 |
| Finished | Aug 13 07:33:05 PM PDT 24 |
| Peak memory | 611248 kb |
| Host | smart-af75951d-a070-40c8-8aca-d9ed7f93376a |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=flash_ctrl_lc_rw_en_test:1:new_rules,test_rom:0 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16 24929982 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_flash_ctrl_lc_rw_en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_flash_ctrl_lc_rw_en.1624929982 |
| Directory | /workspace/2.chip_sw_flash_ctrl_lc_rw_en/latest |
| Test location | /workspace/coverage/default/42.chip_sw_all_escalation_resets.4074531658 |
| Short name | T376 |
| Test name | |
| Test status | |
| Simulation time | 4597580158 ps |
| CPU time | 624.5 seconds |
| Started | Aug 13 07:37:09 PM PDT 24 |
| Finished | Aug 13 07:47:34 PM PDT 24 |
| Peak memory | 650520 kb |
| Host | smart-cfd462a7-42db-4734-8abd-c516d72393b1 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 4074531658 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.chip_sw_all_escalation_resets.4074531658 |
| Directory | /workspace/42.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/3.chip_sw_uart_tx_rx.2788011419 |
| Short name | T2 |
| Test name | |
| Test status | |
| Simulation time | 3898484606 ps |
| CPU time | 531.16 seconds |
| Started | Aug 13 07:34:10 PM PDT 24 |
| Finished | Aug 13 07:43:01 PM PDT 24 |
| Peak memory | 624372 kb |
| Host | smart-d7bd0723-91db-493d-ac47-2332ceee793e |
| User | root |
| Command | /workspace/default/simv +uart_idx=0 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2788011419 -a ssert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ce/coverage/default.vdb -cm_log /dev/null -cm_name 3.chip_sw_uart_tx_rx.2788011419 |
| Directory | /workspace/3.chip_sw_uart_tx_rx/latest |
| Test location | /workspace/coverage/cover_reg_top/15.chip_tl_errors.1026570267 |
| Short name | T570 |
| Test name | |
| Test status | |
| Simulation time | 4736017000 ps |
| CPU time | 324.12 seconds |
| Started | Aug 13 06:51:14 PM PDT 24 |
| Finished | Aug 13 06:56:38 PM PDT 24 |
| Peak memory | 603332 kb |
| Host | smart-cc55fe88-1012-4369-ab6a-97b5642e4be7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1026570267 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.chip_tl_errors.1026570267 |
| Directory | /workspace/15.chip_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/3.xbar_error_random.2896813645 |
| Short name | T71 |
| Test name | |
| Test status | |
| Simulation time | 1285466409 ps |
| CPU time | 41.2 seconds |
| Started | Aug 13 06:50:57 PM PDT 24 |
| Finished | Aug 13 06:51:38 PM PDT 24 |
| Peak memory | 575616 kb |
| Host | smart-62bd58ed-39a2-4c36-a989-87b342ee9c08 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2896813645 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.xbar_error_random.2896813645 |
| Directory | /workspace/3.xbar_error_random/latest |
| Test location | /workspace/coverage/default/21.chip_sw_all_escalation_resets.1280022266 |
| Short name | T86 |
| Test name | |
| Test status | |
| Simulation time | 4336505088 ps |
| CPU time | 680.21 seconds |
| Started | Aug 13 07:36:29 PM PDT 24 |
| Finished | Aug 13 07:47:50 PM PDT 24 |
| Peak memory | 651268 kb |
| Host | smart-d8d20c95-d40f-46f4-8c0f-9c037ad41712 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 1280022266 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.chip_sw_all_escalation_resets.1280022266 |
| Directory | /workspace/21.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/1.chip_sw_csrng_lc_hw_debug_en_test.4107116534 |
| Short name | T194 |
| Test name | |
| Test status | |
| Simulation time | 5924934408 ps |
| CPU time | 662.47 seconds |
| Started | Aug 13 07:15:46 PM PDT 24 |
| Finished | Aug 13 07:26:48 PM PDT 24 |
| Peak memory | 611792 kb |
| Host | smart-3e6896dd-668f-40c5-bb3c-7a60e658125e |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=15_000_000 +rng_srate_value_min=15 +use_otp_image=OtpTypeLcStTestUnlocked0 +sw_build_device=sim_dv +sw_ima ges=csrng_lc_hw_debug_en_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4107116534 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_csrng_ lc_hw_debug_en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_csr ng_lc_hw_debug_en_test.4107116534 |
| Directory | /workspace/1.chip_sw_csrng_lc_hw_debug_en_test/latest |
| Test location | /workspace/coverage/default/0.chip_sw_sleep_pin_retention.3741695782 |
| Short name | T15 |
| Test name | |
| Test status | |
| Simulation time | 4768210036 ps |
| CPU time | 407.17 seconds |
| Started | Aug 13 07:11:33 PM PDT 24 |
| Finished | Aug 13 07:18:21 PM PDT 24 |
| Peak memory | 611204 kb |
| Host | smart-f52eba6d-87c6-45b1-8d4d-271eeb8059fe |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=sleep_pin_retention_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3741695782 -assert nopostproc +UVM_TE STNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sleep_pin_retention_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def ault.vdb -cm_log /dev/null -cm_name 0.chip_sw_sleep_pin_retention.3741695782 |
| Directory | /workspace/0.chip_sw_sleep_pin_retention/latest |
| Test location | /workspace/coverage/default/0.chip_sw_rstmgr_cpu_info.2043461951 |
| Short name | T249 |
| Test name | |
| Test status | |
| Simulation time | 7096929128 ps |
| CPU time | 693.74 seconds |
| Started | Aug 13 07:11:42 PM PDT 24 |
| Finished | Aug 13 07:23:17 PM PDT 24 |
| Peak memory | 611328 kb |
| Host | smart-965bd1b7-24b4-4924-b206-25c50542ec26 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=rstmgr_cpu_info_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2043461951 -assert nopostproc +UVM_TESTNA ME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 0.chip_sw_rstmgr_cpu_info.2043461951 |
| Directory | /workspace/0.chip_sw_rstmgr_cpu_info/latest |
| Test location | /workspace/coverage/default/48.chip_sw_all_escalation_resets.1004497580 |
| Short name | T253 |
| Test name | |
| Test status | |
| Simulation time | 5082735076 ps |
| CPU time | 643.19 seconds |
| Started | Aug 13 07:37:05 PM PDT 24 |
| Finished | Aug 13 07:47:49 PM PDT 24 |
| Peak memory | 650788 kb |
| Host | smart-09164485-146c-4c36-b9c8-b74e3c39c6fa |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 1004497580 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.chip_sw_all_escalation_resets.1004497580 |
| Directory | /workspace/48.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/20.chip_sw_alert_handler_lpg_sleep_mode_alerts.3992299888 |
| Short name | T446 |
| Test name | |
| Test status | |
| Simulation time | 3118621050 ps |
| CPU time | 385.49 seconds |
| Started | Aug 13 07:36:49 PM PDT 24 |
| Finished | Aug 13 07:43:15 PM PDT 24 |
| Peak memory | 649524 kb |
| Host | smart-35143768-78d1-413d-b540-310d48eb0df0 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3992299888 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.chip_ sw_alert_handler_lpg_sleep_mode_alerts.3992299888 |
| Directory | /workspace/20.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/0.chip_sw_data_integrity_escalation.670696592 |
| Short name | T283 |
| Test name | |
| Test status | |
| Simulation time | 5561391400 ps |
| CPU time | 735.9 seconds |
| Started | Aug 13 07:09:24 PM PDT 24 |
| Finished | Aug 13 07:21:41 PM PDT 24 |
| Peak memory | 611596 kb |
| Host | smart-89b5ca07-ea9a-4aa0-96c6-187d804d5ff8 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=data_integrity_escalation_reset_test:1:new_rules,test_ro m:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=670696592 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_data_integrity_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_data_integrity_escalation.670696592 |
| Directory | /workspace/0.chip_sw_data_integrity_escalation/latest |
| Test location | /workspace/coverage/default/0.chip_sw_lc_ctrl_raw_to_scrap.1114096698 |
| Short name | T181 |
| Test name | |
| Test status | |
| Simulation time | 2538940949 ps |
| CPU time | 156.87 seconds |
| Started | Aug 13 07:09:35 PM PDT 24 |
| Finished | Aug 13 07:12:12 PM PDT 24 |
| Peak memory | 620508 kb |
| Host | smart-b6c270c1-db54-4056-9b26-b660fbec1dba |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +src_dec_state=DecLcStRaw +sw_build_device=sim_dv +sw_images=lc_ctrl_scrap_test:1:new_rules ,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1114096698 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_scrap_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_lc_ctrl_raw_to_scrap.1114096698 |
| Directory | /workspace/0.chip_sw_lc_ctrl_raw_to_scrap/latest |
| Test location | /workspace/coverage/default/0.chip_plic_all_irqs_0.2515178092 |
| Short name | T327 |
| Test name | |
| Test status | |
| Simulation time | 6223268844 ps |
| CPU time | 961.2 seconds |
| Started | Aug 13 07:09:49 PM PDT 24 |
| Finished | Aug 13 07:25:50 PM PDT 24 |
| Peak memory | 610916 kb |
| Host | smart-1dd3c9c0-17b6-4180-bcc3-235a604d67e9 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=plic_all_irqs_test_0:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2515178092 -assert nopostproc +UVM_TESTNA ME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 0.chip_plic_all_irqs_0.2515178092 |
| Directory | /workspace/0.chip_plic_all_irqs_0/latest |
| Test location | /workspace/coverage/default/1.chip_sw_sensor_ctrl_alert.2178907775 |
| Short name | T139 |
| Test name | |
| Test status | |
| Simulation time | 6945282456 ps |
| CPU time | 746.45 seconds |
| Started | Aug 13 07:16:44 PM PDT 24 |
| Finished | Aug 13 07:29:11 PM PDT 24 |
| Peak memory | 609928 kb |
| Host | smart-7895d453-7333-4784-8540-94e9a98b3237 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=40_000_000 +sw_build_device=sim_dv +sw_images=sensor_ctrl_alert_test:1:new_rules,test_rom:0 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21789077 75 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac e/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_sensor_ctrl_alert.2178907775 |
| Directory | /workspace/1.chip_sw_sensor_ctrl_alert/latest |
| Test location | /workspace/coverage/default/0.chip_tap_straps_rma.3098555754 |
| Short name | T63 |
| Test name | |
| Test status | |
| Simulation time | 7362385000 ps |
| CPU time | 742.09 seconds |
| Started | Aug 13 07:10:32 PM PDT 24 |
| Finished | Aug 13 07:22:55 PM PDT 24 |
| Peak memory | 625672 kb |
| Host | smart-8cd9eede-00bf-4817-8182-e94466c13a63 |
| User | root |
| Command | /workspace/default/simv +create_jtag_riscv_map=1 +sw_build_device=sim_dv +sw_images=example_test_from_rom:0:test_in_rom:new_rules +cdc_instrumentation _enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3098555754 -as sert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_tap_straps_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/c overage/default.vdb -cm_log /dev/null -cm_name 0.chip_tap_straps_rma.3098555754 |
| Directory | /workspace/0.chip_tap_straps_rma/latest |
| Test location | /workspace/coverage/cover_reg_top/10.chip_csr_rw.4052224634 |
| Short name | T151 |
| Test name | |
| Test status | |
| Simulation time | 5026711429 ps |
| CPU time | 538.9 seconds |
| Started | Aug 13 06:51:07 PM PDT 24 |
| Finished | Aug 13 07:00:06 PM PDT 24 |
| Peak memory | 598988 kb |
| Host | smart-e1ac1474-59bd-4207-b99d-d63696c6c937 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4052224634 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.chip_csr_rw.4052224634 |
| Directory | /workspace/10.chip_csr_rw/latest |
| Test location | /workspace/coverage/default/2.chip_sw_sleep_pin_wake.987738256 |
| Short name | T55 |
| Test name | |
| Test status | |
| Simulation time | 5949986820 ps |
| CPU time | 410.19 seconds |
| Started | Aug 13 07:25:25 PM PDT 24 |
| Finished | Aug 13 07:32:16 PM PDT 24 |
| Peak memory | 611524 kb |
| Host | smart-9c6b37eb-1b33-4b7f-94c0-54d64691ab77 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStProd +sw_build_device=sim_dv +sw_images=sleep_pin_wake_test:1:new_rules,test_rom:0 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=987738256 - assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sleep_pin_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_sleep_pin_wake.987738256 |
| Directory | /workspace/2.chip_sw_sleep_pin_wake/latest |
| Test location | /workspace/coverage/default/0.chip_sw_flash_ctrl_ops_jitter_en_reduced_freq.2176072631 |
| Short name | T351 |
| Test name | |
| Test status | |
| Simulation time | 4994321049 ps |
| CPU time | 779.14 seconds |
| Started | Aug 13 07:14:16 PM PDT 24 |
| Finished | Aug 13 07:27:16 PM PDT 24 |
| Peak memory | 610896 kb |
| Host | smart-07fd55f1-b9ea-4620-99a2-643381f76496 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=50_000_000 +en_jitter=1 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=flash_ctrl_ops_test:1:new_ rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si m.tcl +ntb_random_seed=2176072631 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_flash_ctrl_ops_jitter_en_reduced_freq.2176072631 |
| Directory | /workspace/0.chip_sw_flash_ctrl_ops_jitter_en_reduced_freq/latest |
| Test location | /workspace/coverage/cover_reg_top/19.chip_tl_errors.2746948262 |
| Short name | T748 |
| Test name | |
| Test status | |
| Simulation time | 4041826632 ps |
| CPU time | 376.19 seconds |
| Started | Aug 13 06:51:42 PM PDT 24 |
| Finished | Aug 13 06:57:58 PM PDT 24 |
| Peak memory | 598324 kb |
| Host | smart-8b27994d-06c2-4d89-a158-f89fccb725e9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2746948262 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.chip_tl_errors.2746948262 |
| Directory | /workspace/19.chip_tl_errors/latest |
| Test location | /workspace/coverage/default/0.chip_sw_sleep_pin_wake.579459663 |
| Short name | T56 |
| Test name | |
| Test status | |
| Simulation time | 3525138416 ps |
| CPU time | 227.97 seconds |
| Started | Aug 13 07:09:38 PM PDT 24 |
| Finished | Aug 13 07:13:26 PM PDT 24 |
| Peak memory | 610380 kb |
| Host | smart-a10cb8ae-0298-4aec-a547-4b0e8f41e1f2 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStProd +sw_build_device=sim_dv +sw_images=sleep_pin_wake_test:1:new_rules,test_rom:0 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=579459663 - assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sleep_pin_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_sleep_pin_wake.579459663 |
| Directory | /workspace/0.chip_sw_sleep_pin_wake/latest |
| Test location | /workspace/coverage/cover_reg_top/2.chip_csr_hw_reset.1779382064 |
| Short name | T140 |
| Test name | |
| Test status | |
| Simulation time | 6248639126 ps |
| CPU time | 413.87 seconds |
| Started | Aug 13 06:50:44 PM PDT 24 |
| Finished | Aug 13 06:57:37 PM PDT 24 |
| Peak memory | 661848 kb |
| Host | smart-57a12ffd-6b90-4d9a-b7e4-6ac26aa951ca |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1779382064 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.chip_csr_hw_r eset.1779382064 |
| Directory | /workspace/2.chip_csr_hw_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/27.xbar_stress_all_with_reset_error.4110169322 |
| Short name | T871 |
| Test name | |
| Test status | |
| Simulation time | 787207910 ps |
| CPU time | 298.02 seconds |
| Started | Aug 13 06:52:34 PM PDT 24 |
| Finished | Aug 13 06:57:32 PM PDT 24 |
| Peak memory | 576496 kb |
| Host | smart-8322b5f2-7a88-491c-8c11-20aa1a1c9989 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4110169322 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.xbar_stress_al l_with_reset_error.4110169322 |
| Directory | /workspace/27.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/default/0.chip_sw_power_sleep_load.2570450937 |
| Short name | T112 |
| Test name | |
| Test status | |
| Simulation time | 4096371144 ps |
| CPU time | 291.25 seconds |
| Started | Aug 13 07:11:44 PM PDT 24 |
| Finished | Aug 13 07:16:36 PM PDT 24 |
| Peak memory | 610404 kb |
| Host | smart-3d90c4c8-7851-45f3-8916-5c0fde4bb63e |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=chip_power_sleep_load:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2570450937 -assert nopostproc +UVM_TESTN AME=chip_base_test +UVM_TEST_SEQ=chip_sw_power_sleep_load_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v db -cm_log /dev/null -cm_name 0.chip_sw_power_sleep_load.2570450937 |
| Directory | /workspace/0.chip_sw_power_sleep_load/latest |
| Test location | /workspace/coverage/cover_reg_top/5.xbar_stress_all.3800456843 |
| Short name | T471 |
| Test name | |
| Test status | |
| Simulation time | 17061245762 ps |
| CPU time | 717.16 seconds |
| Started | Aug 13 06:51:10 PM PDT 24 |
| Finished | Aug 13 07:03:08 PM PDT 24 |
| Peak memory | 576588 kb |
| Host | smart-04c0ef4b-0261-423b-b885-89ce34a9277c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3800456843 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.xbar_stress_all.3800456843 |
| Directory | /workspace/5.xbar_stress_all/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_nothing_rma.2534115767 |
| Short name | T40 |
| Test name | |
| Test status | |
| Simulation time | 14202577380 ps |
| CPU time | 3257.81 seconds |
| Started | Aug 13 07:18:32 PM PDT 24 |
| Finished | Aug 13 08:12:51 PM PDT 24 |
| Peak memory | 610440 kb |
| Host | smart-e9570a99-5ee3-4d8a-9b73-3f25ad6c500a |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=100_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_corrupted:1: ot_flash_binary:signed:fake_ecdsa_prod_key_0,otp_img_sigverify_always_rma:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2534115767 -assert nopostproc +UVM_TESTNAME=chip_base _test +UVM_TEST_SEQ=chip_sw_rom_e2e_sigverify_always_a_bad_b_bad_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de fault.vdb -cm_log /dev/null -cm_name 0.rom_e2e_sigverify_always_a_bad_b_nothing_rma.2534115767 |
| Directory | /workspace/0.rom_e2e_sigverify_always_a_bad_b_nothing_rma/latest |
| Test location | /workspace/coverage/default/0.chip_sw_usbdev_aon_pullup.3896349886 |
| Short name | T70 |
| Test name | |
| Test status | |
| Simulation time | 4342479300 ps |
| CPU time | 433.45 seconds |
| Started | Aug 13 07:08:32 PM PDT 24 |
| Finished | Aug 13 07:15:46 PM PDT 24 |
| Peak memory | 610668 kb |
| Host | smart-38dd4f9c-57af-40ac-934c-6b0782be3fac |
| User | root |
| Command | /workspace/default/simv +uart_idx=0 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=usbdev_aon_pullup_test:1:new_rules,test_rom:0 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=389634 9886 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_usbdev_dpi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_usbdev_aon_pullup.3896349886 |
| Directory | /workspace/0.chip_sw_usbdev_aon_pullup/latest |
| Test location | /workspace/coverage/default/1.chip_sw_flash_rma_unlocked.3593563391 |
| Short name | T192 |
| Test name | |
| Test status | |
| Simulation time | 43185563100 ps |
| CPU time | 4623.95 seconds |
| Started | Aug 13 07:14:46 PM PDT 24 |
| Finished | Aug 13 08:31:51 PM PDT 24 |
| Peak memory | 620452 kb |
| Host | smart-731de098-d9f7-4f1d-bb7e-192d54b77397 |
| User | root |
| Command | /workspace/default/simv +flash_program_latency=5 +sw_test_timeout_ns=150_000_000 +sw_build_device=sim_dv +sw_images=flash_rma_unlocked_test:0:test_in_ rom:new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t cl +ntb_random_seed=3593563391 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_flash_rma_unlocked_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_flash_rma_unlocked.3593563391 |
| Directory | /workspace/1.chip_sw_flash_rma_unlocked/latest |
| Test location | /workspace/coverage/cover_reg_top/86.xbar_stress_all_with_rand_reset.1819849399 |
| Short name | T503 |
| Test name | |
| Test status | |
| Simulation time | 9020546434 ps |
| CPU time | 553.63 seconds |
| Started | Aug 13 06:59:42 PM PDT 24 |
| Finished | Aug 13 07:08:57 PM PDT 24 |
| Peak memory | 575724 kb |
| Host | smart-f7bd0d72-1886-48fa-a32f-a2eef68bb711 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1819849399 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 86.xbar_stress_all _with_rand_reset.1819849399 |
| Directory | /workspace/86.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/1.chip_plic_all_irqs_0.1606063759 |
| Short name | T331 |
| Test name | |
| Test status | |
| Simulation time | 6118304936 ps |
| CPU time | 1046.96 seconds |
| Started | Aug 13 07:17:51 PM PDT 24 |
| Finished | Aug 13 07:35:18 PM PDT 24 |
| Peak memory | 609824 kb |
| Host | smart-fa870dc9-eeda-492a-9a80-862a932a7bf0 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=plic_all_irqs_test_0:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1606063759 -assert nopostproc +UVM_TESTNA ME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 1.chip_plic_all_irqs_0.1606063759 |
| Directory | /workspace/1.chip_plic_all_irqs_0/latest |
| Test location | /workspace/coverage/default/0.chip_sw_spi_device_pinmux_sleep_retention.2145063468 |
| Short name | T53 |
| Test name | |
| Test status | |
| Simulation time | 3653223797 ps |
| CPU time | 344.72 seconds |
| Started | Aug 13 07:10:36 PM PDT 24 |
| Finished | Aug 13 07:16:21 PM PDT 24 |
| Peak memory | 618484 kb |
| Host | smart-b5a22250-b83e-49f8-b255-4e5fca11f229 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=spi_device_sleep_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2145063468 -assert nopostproc +UVM_TESTN AME=chip_base_test +UVM_TEST_SEQ=chip_sw_spi_device_pinmux_sleep_retention_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/c overage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_spi_device_pinmux_sleep_retention.2145063468 |
| Directory | /workspace/0.chip_sw_spi_device_pinmux_sleep_retention/latest |
| Test location | /workspace/coverage/cover_reg_top/26.xbar_stress_all_with_rand_reset.3298125345 |
| Short name | T910 |
| Test name | |
| Test status | |
| Simulation time | 3593301329 ps |
| CPU time | 336.57 seconds |
| Started | Aug 13 06:52:34 PM PDT 24 |
| Finished | Aug 13 06:58:10 PM PDT 24 |
| Peak memory | 575700 kb |
| Host | smart-b927f650-7526-4c07-b462-dd4d70616bb3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3298125345 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.xbar_stress_all _with_rand_reset.3298125345 |
| Directory | /workspace/26.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_slow_rma.467760023 |
| Short name | T45 |
| Test name | |
| Test status | |
| Simulation time | 4416201536 ps |
| CPU time | 599.24 seconds |
| Started | Aug 13 07:10:51 PM PDT 24 |
| Finished | Aug 13 07:20:51 PM PDT 24 |
| Peak memory | 613800 kb |
| Host | smart-0faf73d6-91a4-47b5-b1a4-6d613e5120c7 |
| User | root |
| Command | /workspace/default/simv +chip_clock_source=ChipClockSourceExternal48Mhz +calibrate_usb_clk=1 +src_dec_state=DecLcStRma +sw_build_device=sim_dv +sw_ima ges=clkmgr_external_clk_src_for_sw_slow_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=467760023 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ= chip_sw_lc_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_cl kmgr_external_clk_src_for_sw_slow_rma.467760023 |
| Directory | /workspace/0.chip_sw_clkmgr_external_clk_src_for_sw_slow_rma/latest |
| Test location | /workspace/coverage/default/2.chip_plic_all_irqs_20.272261083 |
| Short name | T337 |
| Test name | |
| Test status | |
| Simulation time | 4857915776 ps |
| CPU time | 763.37 seconds |
| Started | Aug 13 07:31:20 PM PDT 24 |
| Finished | Aug 13 07:44:03 PM PDT 24 |
| Peak memory | 610504 kb |
| Host | smart-7598c472-7729-4ef1-9d37-882718ec97c1 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=plic_all_irqs_test_20:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=272261083 -assert nopostproc +UVM_TESTNA ME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 2.chip_plic_all_irqs_20.272261083 |
| Directory | /workspace/2.chip_plic_all_irqs_20/latest |
| Test location | /workspace/coverage/cover_reg_top/42.xbar_stress_all_with_error.3754824258 |
| Short name | T559 |
| Test name | |
| Test status | |
| Simulation time | 9376114814 ps |
| CPU time | 331.93 seconds |
| Started | Aug 13 06:54:01 PM PDT 24 |
| Finished | Aug 13 06:59:33 PM PDT 24 |
| Peak memory | 576520 kb |
| Host | smart-ba00d62f-544b-4b35-aba8-ecb73acae95a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3754824258 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.xbar_stress_all_with_error.3754824258 |
| Directory | /workspace/42.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/default/0.chip_sw_sensor_ctrl_alert.2523229249 |
| Short name | T136 |
| Test name | |
| Test status | |
| Simulation time | 6209591296 ps |
| CPU time | 534.45 seconds |
| Started | Aug 13 07:10:27 PM PDT 24 |
| Finished | Aug 13 07:19:22 PM PDT 24 |
| Peak memory | 610996 kb |
| Host | smart-1af4df21-46ed-48b3-9a1d-c3fa5cc2d3e4 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=40_000_000 +sw_build_device=sim_dv +sw_images=sensor_ctrl_alert_test:1:new_rules,test_rom:0 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25232292 49 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac e/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_sensor_ctrl_alert.2523229249 |
| Directory | /workspace/0.chip_sw_sensor_ctrl_alert/latest |
| Test location | /workspace/coverage/cover_reg_top/36.xbar_stress_all_with_reset_error.1339924993 |
| Short name | T903 |
| Test name | |
| Test status | |
| Simulation time | 7630477509 ps |
| CPU time | 424.96 seconds |
| Started | Aug 13 06:53:30 PM PDT 24 |
| Finished | Aug 13 07:00:35 PM PDT 24 |
| Peak memory | 575480 kb |
| Host | smart-45c80526-f11d-4769-ba0a-d40289722734 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1339924993 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.xbar_stress_al l_with_reset_error.1339924993 |
| Directory | /workspace/36.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/default/1.chip_sw_otp_ctrl_vendor_test_csr_access.2704697268 |
| Short name | T167 |
| Test name | |
| Test status | |
| Simulation time | 2947608175 ps |
| CPU time | 123.68 seconds |
| Started | Aug 13 07:12:39 PM PDT 24 |
| Finished | Aug 13 07:14:43 PM PDT 24 |
| Peak memory | 621872 kb |
| Host | smart-f917adeb-9969-49d1-8544-b0e73915c333 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=otp_ctrl_vendor_test_csr_access_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2704697268 -assert nopost proc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_otp_ctrl_vendor_test_csr_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_otp_ctrl_vendor_test_csr_access.2704697268 |
| Directory | /workspace/1.chip_sw_otp_ctrl_vendor_test_csr_access/latest |
| Test location | /workspace/coverage/cover_reg_top/18.chip_tl_errors.1034041212 |
| Short name | T725 |
| Test name | |
| Test status | |
| Simulation time | 3179507416 ps |
| CPU time | 315.74 seconds |
| Started | Aug 13 06:51:26 PM PDT 24 |
| Finished | Aug 13 06:56:42 PM PDT 24 |
| Peak memory | 598332 kb |
| Host | smart-3f54088c-4b9c-4424-a571-616553501981 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1034041212 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.chip_tl_errors.1034041212 |
| Directory | /workspace/18.chip_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/30.xbar_stress_all_with_rand_reset.2711623841 |
| Short name | T489 |
| Test name | |
| Test status | |
| Simulation time | 2540868500 ps |
| CPU time | 358.92 seconds |
| Started | Aug 13 06:52:47 PM PDT 24 |
| Finished | Aug 13 06:58:46 PM PDT 24 |
| Peak memory | 576528 kb |
| Host | smart-74a63538-5524-44c6-b1b5-19dd17fe82a4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2711623841 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.xbar_stress_all _with_rand_reset.2711623841 |
| Directory | /workspace/30.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/3.chip_sw_uart_tx_rx_idx2.2059465156 |
| Short name | T152 |
| Test name | |
| Test status | |
| Simulation time | 4036625308 ps |
| CPU time | 643.1 seconds |
| Started | Aug 13 07:31:48 PM PDT 24 |
| Finished | Aug 13 07:42:31 PM PDT 24 |
| Peak memory | 624344 kb |
| Host | smart-0c1f7e2b-03ed-489a-8eb3-2d5ae2a2d77e |
| User | root |
| Command | /workspace/default/simv +uart_idx=2 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2059465156 -a ssert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ce/coverage/default.vdb -cm_log /dev/null -cm_name 3.chip_sw_uart_tx_rx_idx2.2059465156 |
| Directory | /workspace/3.chip_sw_uart_tx_rx_idx2/latest |
| Test location | /workspace/coverage/default/0.chip_sw_uart_tx_rx_idx1.2360187268 |
| Short name | T1181 |
| Test name | |
| Test status | |
| Simulation time | 4448807620 ps |
| CPU time | 703.74 seconds |
| Started | Aug 13 07:09:20 PM PDT 24 |
| Finished | Aug 13 07:21:05 PM PDT 24 |
| Peak memory | 620808 kb |
| Host | smart-7adc70f1-e81c-4122-be78-461bc794441d |
| User | root |
| Command | /workspace/default/simv +uart_idx=1 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2360187268 -a ssert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ce/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_uart_tx_rx_idx1.2360187268 |
| Directory | /workspace/0.chip_sw_uart_tx_rx_idx1/latest |
| Test location | /workspace/coverage/default/2.chip_sw_adc_ctrl_sleep_debug_cable_wakeup.1305312234 |
| Short name | T111 |
| Test name | |
| Test status | |
| Simulation time | 19971442656 ps |
| CPU time | 577.78 seconds |
| Started | Aug 13 07:25:37 PM PDT 24 |
| Finished | Aug 13 07:35:15 PM PDT 24 |
| Peak memory | 620044 kb |
| Host | smart-212950e9-201f-45ef-a431-02b2dbde26e8 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=adc_ctrl_sleep_debug_cable_wakeup_test:1:new_rules,test_rom: 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand om_seed=1305312234 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_adc_ctrl_sleep_debug_cable_wakeup_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_adc_ctrl_sleep_debug_cable_wakeup.1305312234 |
| Directory | /workspace/2.chip_sw_adc_ctrl_sleep_debug_cable_wakeup/latest |
| Test location | /workspace/coverage/default/0.chip_sw_uart_tx_rx_idx3.1385285901 |
| Short name | T14 |
| Test name | |
| Test status | |
| Simulation time | 3880041212 ps |
| CPU time | 690.06 seconds |
| Started | Aug 13 07:08:54 PM PDT 24 |
| Finished | Aug 13 07:20:24 PM PDT 24 |
| Peak memory | 624356 kb |
| Host | smart-f983cd6f-25b3-4c7c-a885-72daf1f1f453 |
| User | root |
| Command | /workspace/default/simv +uart_idx=3 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1385285901 -a ssert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ce/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_uart_tx_rx_idx3.1385285901 |
| Directory | /workspace/0.chip_sw_uart_tx_rx_idx3/latest |
| Test location | /workspace/coverage/cover_reg_top/90.xbar_stress_all_with_reset_error.1474481952 |
| Short name | T772 |
| Test name | |
| Test status | |
| Simulation time | 3389374038 ps |
| CPU time | 248.7 seconds |
| Started | Aug 13 07:00:11 PM PDT 24 |
| Finished | Aug 13 07:04:20 PM PDT 24 |
| Peak memory | 576560 kb |
| Host | smart-9fff92a3-be96-4765-aa15-fdfb6ff22fe2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1474481952 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 90.xbar_stress_al l_with_reset_error.1474481952 |
| Directory | /workspace/90.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/default/2.chip_sw_flash_init_reduced_freq.1796245282 |
| Short name | T177 |
| Test name | |
| Test status | |
| Simulation time | 25064352558 ps |
| CPU time | 2416.12 seconds |
| Started | Aug 13 07:29:16 PM PDT 24 |
| Finished | Aug 13 08:09:33 PM PDT 24 |
| Peak memory | 614112 kb |
| Host | smart-37884dd5-51e3-49e6-ab28-94feda2f1f76 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=25_000_000 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=flash_init_test:0:test_in_rom:new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=1796245282 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_flash_init_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_flash_init_reduced_freq.1796245282 |
| Directory | /workspace/2.chip_sw_flash_init_reduced_freq/latest |
| Test location | /workspace/coverage/cover_reg_top/54.xbar_stress_all.2091223105 |
| Short name | T1801 |
| Test name | |
| Test status | |
| Simulation time | 19465108695 ps |
| CPU time | 752.11 seconds |
| Started | Aug 13 06:55:26 PM PDT 24 |
| Finished | Aug 13 07:07:58 PM PDT 24 |
| Peak memory | 575696 kb |
| Host | smart-78d6f8ee-4a24-4e01-acd8-c7568519dc55 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2091223105 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 54.xbar_stress_all.2091223105 |
| Directory | /workspace/54.xbar_stress_all/latest |
| Test location | /workspace/coverage/default/1.chip_plic_all_irqs_20.3440120815 |
| Short name | T330 |
| Test name | |
| Test status | |
| Simulation time | 5404848964 ps |
| CPU time | 853.13 seconds |
| Started | Aug 13 07:18:04 PM PDT 24 |
| Finished | Aug 13 07:32:18 PM PDT 24 |
| Peak memory | 610312 kb |
| Host | smart-9004bada-abc5-4b83-889c-3a1954932212 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=plic_all_irqs_test_20:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3440120815 -assert nopostproc +UVM_TESTN AME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log / dev/null -cm_name 1.chip_plic_all_irqs_20.3440120815 |
| Directory | /workspace/1.chip_plic_all_irqs_20/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_jtag_debug_dev.859599153 |
| Short name | T264 |
| Test name | |
| Test status | |
| Simulation time | 12306667796 ps |
| CPU time | 2692.25 seconds |
| Started | Aug 13 07:12:54 PM PDT 24 |
| Finished | Aug 13 07:57:48 PM PDT 24 |
| Peak memory | 624648 kb |
| Host | smart-d94b5c3e-208e-437d-a80d-5e770a540f77 |
| User | root |
| Command | /workspace/default/simv +use_jtag_dmi=1 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=img_dev_exec_disabled:4,mask_rom:0 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=85959 9153 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rom_e2e_jtag_debug_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_jtag_debug_dev.859599153 |
| Directory | /workspace/0.rom_e2e_jtag_debug_dev/latest |
| Test location | /workspace/coverage/cover_reg_top/26.chip_tl_errors.373736654 |
| Short name | T576 |
| Test name | |
| Test status | |
| Simulation time | 3900306729 ps |
| CPU time | 248.49 seconds |
| Started | Aug 13 06:52:22 PM PDT 24 |
| Finished | Aug 13 06:56:30 PM PDT 24 |
| Peak memory | 598392 kb |
| Host | smart-e206d930-7f30-4bc2-826f-e779cc888c47 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=373736654 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.chip_tl_errors.373736654 |
| Directory | /workspace/26.chip_tl_errors/latest |
| Test location | /workspace/coverage/pad_ctrl_test_mode/0.chip_padctrl_attributes.617184267 |
| Short name | T30 |
| Test name | |
| Test status | |
| Simulation time | 4521223330 ps |
| CPU time | 264.62 seconds |
| Started | Aug 13 06:31:58 PM PDT 24 |
| Finished | Aug 13 06:36:23 PM PDT 24 |
| Peak memory | 657864 kb |
| Host | smart-81c177bb-682f-4885-a43b-e3b8627af4cd |
| User | root |
| Command | /workspace/pad_ctrl_test_mode/simv +use_otp_image=OtpTypeLcStProd +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=617184267 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TES T_SEQ=chip_padctrl_attributes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/pad_ctrl_test_mode.vdb -cm_log /dev/n ull -cm_name 0.chip_padctrl_attributes.617184267 |
| Directory | /workspace/0.chip_padctrl_attributes/latest |
| Test location | /workspace/coverage/default/13.chip_sw_lc_ctrl_transition.171464704 |
| Short name | T59 |
| Test name | |
| Test status | |
| Simulation time | 13917159466 ps |
| CPU time | 844.92 seconds |
| Started | Aug 13 07:37:35 PM PDT 24 |
| Finished | Aug 13 07:51:40 PM PDT 24 |
| Peak memory | 621816 kb |
| Host | smart-50eed272-67fc-4c96-9738-bd0dcd4cebda |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=lc_ctrl_transition_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=171464704 -assert nopostproc +UVM_TEST NAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_transition_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul t.vdb -cm_log /dev/null -cm_name 13.chip_sw_lc_ctrl_transition.171464704 |
| Directory | /workspace/13.chip_sw_lc_ctrl_transition/latest |
| Test location | /workspace/coverage/default/1.chip_sw_gpio.2308547093 |
| Short name | T26 |
| Test name | |
| Test status | |
| Simulation time | 4323560184 ps |
| CPU time | 555.55 seconds |
| Started | Aug 13 07:15:09 PM PDT 24 |
| Finished | Aug 13 07:24:25 PM PDT 24 |
| Peak memory | 610668 kb |
| Host | smart-4c9b5969-982f-4df6-b68b-476f4a0afa55 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=gpio_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2308547093 -assert nopostproc +UVM_TESTNAME=chip_bas e_test +UVM_TEST_SEQ=chip_sw_gpio_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm _name 1.chip_sw_gpio.2308547093 |
| Directory | /workspace/1.chip_sw_gpio/latest |
| Test location | /workspace/coverage/default/2.chip_plic_all_irqs_10.1231938151 |
| Short name | T161 |
| Test name | |
| Test status | |
| Simulation time | 3613728040 ps |
| CPU time | 596.07 seconds |
| Started | Aug 13 07:28:09 PM PDT 24 |
| Finished | Aug 13 07:38:06 PM PDT 24 |
| Peak memory | 610628 kb |
| Host | smart-a78bd44c-3e8c-4fae-a456-44d5629e3433 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=plic_all_irqs_test_10:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1231938151 -assert nopostproc +UVM_TESTN AME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log / dev/null -cm_name 2.chip_plic_all_irqs_10.1231938151 |
| Directory | /workspace/2.chip_plic_all_irqs_10/latest |
| Test location | /workspace/coverage/cover_reg_top/1.chip_same_csr_outstanding.3954018528 |
| Short name | T388 |
| Test name | |
| Test status | |
| Simulation time | 17307646538 ps |
| CPU time | 2502.24 seconds |
| Started | Aug 13 06:50:47 PM PDT 24 |
| Finished | Aug 13 07:32:30 PM PDT 24 |
| Peak memory | 592612 kb |
| Host | smart-3cf988f4-cf7b-4e7c-8fa3-b63d22ee6999 |
| User | root |
| Command | /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +run_same_csr_outstanding +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3954018528 -assert nopostproc +UVM_TE STNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb - cm_log /dev/null -cm_name 1.chip_same_csr_outstanding.3954018528 |
| Directory | /workspace/1.chip_same_csr_outstanding/latest |
| Test location | /workspace/coverage/default/0.chip_sw_usbdev_setuprx.2079963565 |
| Short name | T17 |
| Test name | |
| Test status | |
| Simulation time | 4201465112 ps |
| CPU time | 432.84 seconds |
| Started | Aug 13 07:08:49 PM PDT 24 |
| Finished | Aug 13 07:16:02 PM PDT 24 |
| Peak memory | 610548 kb |
| Host | smart-c7adb8d4-9f23-491e-86e0-f4b46ed57b2e |
| User | root |
| Command | /workspace/default/simv +uart_idx=0 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=usbdev_setuprx_test:1:new_rules,test_rom:0 +cdc_instrument ation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=207996356 5 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_usbdev_dpi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_usbdev_setuprx.2079963565 |
| Directory | /workspace/0.chip_sw_usbdev_setuprx/latest |
| Test location | /workspace/coverage/default/1.chip_sw_edn_entropy_reqs_jitter.579421172 |
| Short name | T118 |
| Test name | |
| Test status | |
| Simulation time | 8282700606 ps |
| CPU time | 1346.02 seconds |
| Started | Aug 13 07:19:02 PM PDT 24 |
| Finished | Aug 13 07:41:28 PM PDT 24 |
| Peak memory | 611636 kb |
| Host | smart-cf3c0715-04ee-454c-8ace-af09d584708f |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=15000000 +rng_srate_value_min=15 +rng_srate_value_max=30 +en_jitter=1 +sw_build_device=sim_dv +sw_images=e ntropy_src_edn_reqs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=579421172 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_edn_entropy_reqs_jitter.579421172 |
| Directory | /workspace/1.chip_sw_edn_entropy_reqs_jitter/latest |
| Test location | /workspace/coverage/cover_reg_top/0.xbar_stress_all_with_rand_reset.2275588674 |
| Short name | T907 |
| Test name | |
| Test status | |
| Simulation time | 7791864409 ps |
| CPU time | 475.73 seconds |
| Started | Aug 13 06:50:41 PM PDT 24 |
| Finished | Aug 13 06:58:37 PM PDT 24 |
| Peak memory | 576552 kb |
| Host | smart-bf987664-2feb-42dc-be92-81594a4a0499 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2275588674 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.xbar_stress_all_ with_rand_reset.2275588674 |
| Directory | /workspace/0.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/4.chip_csr_hw_reset.4275243295 |
| Short name | T143 |
| Test name | |
| Test status | |
| Simulation time | 4273129625 ps |
| CPU time | 234.93 seconds |
| Started | Aug 13 06:51:03 PM PDT 24 |
| Finished | Aug 13 06:54:58 PM PDT 24 |
| Peak memory | 659188 kb |
| Host | smart-d7639723-4eef-4af6-9cf5-eb8efa936296 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4275243295 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.chip_csr_hw_r eset.4275243295 |
| Directory | /workspace/4.chip_csr_hw_reset/latest |
| Test location | /workspace/coverage/default/2.chip_sw_flash_rma_unlocked.3034169764 |
| Short name | T191 |
| Test name | |
| Test status | |
| Simulation time | 43884394728 ps |
| CPU time | 4304.59 seconds |
| Started | Aug 13 07:25:28 PM PDT 24 |
| Finished | Aug 13 08:37:13 PM PDT 24 |
| Peak memory | 624752 kb |
| Host | smart-ddf28a5c-2740-4eb7-a5b3-53603d9421be |
| User | root |
| Command | /workspace/default/simv +flash_program_latency=5 +sw_test_timeout_ns=150_000_000 +sw_build_device=sim_dv +sw_images=flash_rma_unlocked_test:0:test_in_ rom:new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t cl +ntb_random_seed=3034169764 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_flash_rma_unlocked_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_flash_rma_unlocked.3034169764 |
| Directory | /workspace/2.chip_sw_flash_rma_unlocked/latest |
| Test location | /workspace/coverage/cover_reg_top/5.chip_tl_errors.410546722 |
| Short name | T574 |
| Test name | |
| Test status | |
| Simulation time | 2484523889 ps |
| CPU time | 135.54 seconds |
| Started | Aug 13 06:51:03 PM PDT 24 |
| Finished | Aug 13 06:53:18 PM PDT 24 |
| Peak memory | 598380 kb |
| Host | smart-bc3fe8b5-33f5-483f-b215-516e881fa318 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=410546722 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.chip_tl_errors.410546722 |
| Directory | /workspace/5.chip_tl_errors/latest |
| Test location | /workspace/coverage/default/1.chip_sw_flash_ctrl_ops_jitter_en_reduced_freq.73577725 |
| Short name | T349 |
| Test name | |
| Test status | |
| Simulation time | 4958598904 ps |
| CPU time | 673.55 seconds |
| Started | Aug 13 07:20:37 PM PDT 24 |
| Finished | Aug 13 07:31:51 PM PDT 24 |
| Peak memory | 610936 kb |
| Host | smart-18defe3d-b3b6-4d7a-9523-9beeb5497397 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=50_000_000 +en_jitter=1 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=flash_ctrl_ops_test:1:new_ rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si m.tcl +ntb_random_seed=73577725 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_flash_ctrl_ops_jitter_en_reduced_freq.73577725 |
| Directory | /workspace/1.chip_sw_flash_ctrl_ops_jitter_en_reduced_freq/latest |
| Test location | /workspace/coverage/default/61.chip_sw_all_escalation_resets.1030848343 |
| Short name | T369 |
| Test name | |
| Test status | |
| Simulation time | 5735374216 ps |
| CPU time | 468.18 seconds |
| Started | Aug 13 07:39:44 PM PDT 24 |
| Finished | Aug 13 07:47:33 PM PDT 24 |
| Peak memory | 650872 kb |
| Host | smart-b6e25ce1-67ff-4aeb-ae1b-8d537063773e |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 1030848343 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 61.chip_sw_all_escalation_resets.1030848343 |
| Directory | /workspace/61.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/cover_reg_top/14.chip_tl_errors.2139474153 |
| Short name | T791 |
| Test name | |
| Test status | |
| Simulation time | 2972198710 ps |
| CPU time | 177.1 seconds |
| Started | Aug 13 06:51:12 PM PDT 24 |
| Finished | Aug 13 06:54:09 PM PDT 24 |
| Peak memory | 599508 kb |
| Host | smart-82634a69-96f1-4d1e-8933-dfe1e5f4f4a6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2139474153 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.chip_tl_errors.2139474153 |
| Directory | /workspace/14.chip_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/72.xbar_stress_all_with_reset_error.908152596 |
| Short name | T677 |
| Test name | |
| Test status | |
| Simulation time | 4900763496 ps |
| CPU time | 329.25 seconds |
| Started | Aug 13 06:57:44 PM PDT 24 |
| Finished | Aug 13 07:03:13 PM PDT 24 |
| Peak memory | 575708 kb |
| Host | smart-adffc85a-9b7d-4624-810e-b42ff606c13c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=908152596 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 72.xbar_stress_all _with_reset_error.908152596 |
| Directory | /workspace/72.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/3.xbar_access_same_device_slow_rsp.61537251 |
| Short name | T482 |
| Test name | |
| Test status | |
| Simulation time | 141869351480 ps |
| CPU time | 2511.06 seconds |
| Started | Aug 13 06:50:44 PM PDT 24 |
| Finished | Aug 13 07:32:35 PM PDT 24 |
| Peak memory | 575816 kb |
| Host | smart-e673708e-d932-4ecb-a012-eb1c311e8921 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=61537251 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.xbar_access_same_dev ice_slow_rsp.61537251 |
| Directory | /workspace/3.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/30.xbar_stress_all.3823517007 |
| Short name | T2124 |
| Test name | |
| Test status | |
| Simulation time | 4297068077 ps |
| CPU time | 375.49 seconds |
| Started | Aug 13 06:52:50 PM PDT 24 |
| Finished | Aug 13 06:59:06 PM PDT 24 |
| Peak memory | 576584 kb |
| Host | smart-6d68950e-4b2c-404d-b067-71d4dd5aa968 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3823517007 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.xbar_stress_all.3823517007 |
| Directory | /workspace/30.xbar_stress_all/latest |
| Test location | /workspace/coverage/default/34.chip_sw_all_escalation_resets.351464768 |
| Short name | T102 |
| Test name | |
| Test status | |
| Simulation time | 6005790704 ps |
| CPU time | 816.43 seconds |
| Started | Aug 13 07:36:08 PM PDT 24 |
| Finished | Aug 13 07:49:45 PM PDT 24 |
| Peak memory | 651128 kb |
| Host | smart-5dcf3c9f-b819-4c60-9efb-5a435a3dafc4 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 351464768 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.chip_sw_all_escalation_resets.351464768 |
| Directory | /workspace/34.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/0.chip_sw_spi_device_pass_through_collision.3903919125 |
| Short name | T12 |
| Test name | |
| Test status | |
| Simulation time | 4026644466 ps |
| CPU time | 592.46 seconds |
| Started | Aug 13 07:11:44 PM PDT 24 |
| Finished | Aug 13 07:21:37 PM PDT 24 |
| Peak memory | 625284 kb |
| Host | smart-d4e93d74-1541-4200-b6ae-a5b7fbef8037 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=spi_passthrough_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3903919125 -assert nopostproc +UVM_TESTNA ME=chip_base_test +UVM_TEST_SEQ=chip_sw_spi_passthrough_collision_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/d efault.vdb -cm_log /dev/null -cm_name 0.chip_sw_spi_device_pass_through_collision.3903919125 |
| Directory | /workspace/0.chip_sw_spi_device_pass_through_collision/latest |
| Test location | /workspace/coverage/default/2.chip_sw_otp_ctrl_vendor_test_csr_access.2238360423 |
| Short name | T169 |
| Test name | |
| Test status | |
| Simulation time | 2569145556 ps |
| CPU time | 113.08 seconds |
| Started | Aug 13 07:25:27 PM PDT 24 |
| Finished | Aug 13 07:27:21 PM PDT 24 |
| Peak memory | 622332 kb |
| Host | smart-26d82f4e-9745-4ad2-8fa0-75522852f4a8 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=otp_ctrl_vendor_test_csr_access_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2238360423 -assert nopost proc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_otp_ctrl_vendor_test_csr_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_otp_ctrl_vendor_test_csr_access.2238360423 |
| Directory | /workspace/2.chip_sw_otp_ctrl_vendor_test_csr_access/latest |
| Test location | /workspace/coverage/cover_reg_top/0.xbar_stress_all_with_reset_error.2246295975 |
| Short name | T915 |
| Test name | |
| Test status | |
| Simulation time | 20068230132 ps |
| CPU time | 841.42 seconds |
| Started | Aug 13 06:50:35 PM PDT 24 |
| Finished | Aug 13 07:04:36 PM PDT 24 |
| Peak memory | 576536 kb |
| Host | smart-04931827-4727-4fec-83bf-17d97d9e71e6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2246295975 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.xbar_stress_all _with_reset_error.2246295975 |
| Directory | /workspace/0.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/29.xbar_stress_all_with_reset_error.2697326206 |
| Short name | T911 |
| Test name | |
| Test status | |
| Simulation time | 1957506115 ps |
| CPU time | 269.98 seconds |
| Started | Aug 13 06:52:47 PM PDT 24 |
| Finished | Aug 13 06:57:17 PM PDT 24 |
| Peak memory | 576512 kb |
| Host | smart-db5dc121-66c7-4067-9d49-9b1495877495 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2697326206 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.xbar_stress_al l_with_reset_error.2697326206 |
| Directory | /workspace/29.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/default/0.chip_sw_alert_handler_lpg_sleep_mode_alerts.2143128895 |
| Short name | T841 |
| Test name | |
| Test status | |
| Simulation time | 4060993836 ps |
| CPU time | 395.44 seconds |
| Started | Aug 13 07:11:43 PM PDT 24 |
| Finished | Aug 13 07:18:19 PM PDT 24 |
| Peak memory | 649556 kb |
| Host | smart-99d94dbf-720b-4df2-9a07-b0267d9a2303 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2143128895 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_s w_alert_handler_lpg_sleep_mode_alerts.2143128895 |
| Directory | /workspace/0.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/1.chip_sw_alert_handler_lpg_sleep_mode_alerts.2648372548 |
| Short name | T851 |
| Test name | |
| Test status | |
| Simulation time | 3395110696 ps |
| CPU time | 405.07 seconds |
| Started | Aug 13 07:18:31 PM PDT 24 |
| Finished | Aug 13 07:25:16 PM PDT 24 |
| Peak memory | 649576 kb |
| Host | smart-5f463cbd-d2c6-4e00-bb16-714a22dfcaa9 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2648372548 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_s w_alert_handler_lpg_sleep_mode_alerts.2648372548 |
| Directory | /workspace/1.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/1.chip_sw_all_escalation_resets.485899380 |
| Short name | T782 |
| Test name | |
| Test status | |
| Simulation time | 4484834680 ps |
| CPU time | 547.22 seconds |
| Started | Aug 13 07:14:37 PM PDT 24 |
| Finished | Aug 13 07:23:45 PM PDT 24 |
| Peak memory | 650788 kb |
| Host | smart-5cfbec39-5d59-46aa-95db-186347bc7eea |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 485899380 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_all_escalation_resets.485899380 |
| Directory | /workspace/1.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/10.chip_sw_alert_handler_lpg_sleep_mode_alerts.126832265 |
| Short name | T811 |
| Test name | |
| Test status | |
| Simulation time | 3168353128 ps |
| CPU time | 403.12 seconds |
| Started | Aug 13 07:34:29 PM PDT 24 |
| Finished | Aug 13 07:41:12 PM PDT 24 |
| Peak memory | 649412 kb |
| Host | smart-1278295e-f522-47f5-ac7e-f2d359efa76c |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=126832265 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all _escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.chip_s w_alert_handler_lpg_sleep_mode_alerts.126832265 |
| Directory | /workspace/10.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/10.chip_sw_all_escalation_resets.424171298 |
| Short name | T862 |
| Test name | |
| Test status | |
| Simulation time | 5169468792 ps |
| CPU time | 609.45 seconds |
| Started | Aug 13 07:34:38 PM PDT 24 |
| Finished | Aug 13 07:44:47 PM PDT 24 |
| Peak memory | 650824 kb |
| Host | smart-5230493e-b149-47a0-aa37-8230406ccb7a |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 424171298 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.chip_sw_all_escalation_resets.424171298 |
| Directory | /workspace/10.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/11.chip_sw_alert_handler_lpg_sleep_mode_alerts.4183999946 |
| Short name | T1302 |
| Test name | |
| Test status | |
| Simulation time | 4302896808 ps |
| CPU time | 406.95 seconds |
| Started | Aug 13 07:34:00 PM PDT 24 |
| Finished | Aug 13 07:40:48 PM PDT 24 |
| Peak memory | 649752 kb |
| Host | smart-a8b53b75-7bd3-4c9f-8ffa-ee53d3273ec9 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4183999946 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.chip_ sw_alert_handler_lpg_sleep_mode_alerts.4183999946 |
| Directory | /workspace/11.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/11.chip_sw_all_escalation_resets.1090442177 |
| Short name | T1246 |
| Test name | |
| Test status | |
| Simulation time | 5875091320 ps |
| CPU time | 600.43 seconds |
| Started | Aug 13 07:34:29 PM PDT 24 |
| Finished | Aug 13 07:44:30 PM PDT 24 |
| Peak memory | 650752 kb |
| Host | smart-6143b7c9-2ff0-49c4-9af3-5a41038f1500 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 1090442177 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.chip_sw_all_escalation_resets.1090442177 |
| Directory | /workspace/11.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/12.chip_sw_alert_handler_lpg_sleep_mode_alerts.2123834069 |
| Short name | T1060 |
| Test name | |
| Test status | |
| Simulation time | 3887546396 ps |
| CPU time | 493.48 seconds |
| Started | Aug 13 07:33:37 PM PDT 24 |
| Finished | Aug 13 07:41:51 PM PDT 24 |
| Peak memory | 649460 kb |
| Host | smart-337c9c72-fbf0-4226-89a1-a36f6a284389 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2123834069 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.chip_ sw_alert_handler_lpg_sleep_mode_alerts.2123834069 |
| Directory | /workspace/12.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/12.chip_sw_all_escalation_resets.222326615 |
| Short name | T318 |
| Test name | |
| Test status | |
| Simulation time | 4796741704 ps |
| CPU time | 615.64 seconds |
| Started | Aug 13 07:35:44 PM PDT 24 |
| Finished | Aug 13 07:46:00 PM PDT 24 |
| Peak memory | 650800 kb |
| Host | smart-880d8024-1713-4495-bf78-491120ba7222 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 222326615 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.chip_sw_all_escalation_resets.222326615 |
| Directory | /workspace/12.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/13.chip_sw_alert_handler_lpg_sleep_mode_alerts.2437090036 |
| Short name | T394 |
| Test name | |
| Test status | |
| Simulation time | 4012779300 ps |
| CPU time | 374.51 seconds |
| Started | Aug 13 07:37:47 PM PDT 24 |
| Finished | Aug 13 07:44:02 PM PDT 24 |
| Peak memory | 649308 kb |
| Host | smart-6402f763-38ad-4fed-9fba-6748cda08294 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2437090036 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.chip_ sw_alert_handler_lpg_sleep_mode_alerts.2437090036 |
| Directory | /workspace/13.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/13.chip_sw_all_escalation_resets.3019012246 |
| Short name | T848 |
| Test name | |
| Test status | |
| Simulation time | 5352273032 ps |
| CPU time | 663.58 seconds |
| Started | Aug 13 07:37:44 PM PDT 24 |
| Finished | Aug 13 07:48:47 PM PDT 24 |
| Peak memory | 650876 kb |
| Host | smart-1040c174-ccdc-4d15-95d3-b6a8e1c5234c |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 3019012246 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.chip_sw_all_escalation_resets.3019012246 |
| Directory | /workspace/13.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/15.chip_sw_alert_handler_lpg_sleep_mode_alerts.1066453784 |
| Short name | T779 |
| Test name | |
| Test status | |
| Simulation time | 3811116096 ps |
| CPU time | 482.16 seconds |
| Started | Aug 13 07:34:33 PM PDT 24 |
| Finished | Aug 13 07:42:35 PM PDT 24 |
| Peak memory | 649480 kb |
| Host | smart-402f5813-7a72-4054-9608-4ad22c402cd5 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1066453784 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.chip_ sw_alert_handler_lpg_sleep_mode_alerts.1066453784 |
| Directory | /workspace/15.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/18.chip_sw_alert_handler_lpg_sleep_mode_alerts.599333359 |
| Short name | T1290 |
| Test name | |
| Test status | |
| Simulation time | 3459480146 ps |
| CPU time | 503.12 seconds |
| Started | Aug 13 07:35:08 PM PDT 24 |
| Finished | Aug 13 07:43:32 PM PDT 24 |
| Peak memory | 649504 kb |
| Host | smart-e1eeb6e2-96e8-4a0b-a44b-65cf8019627d |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=599333359 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all _escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.chip_s w_alert_handler_lpg_sleep_mode_alerts.599333359 |
| Directory | /workspace/18.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/19.chip_sw_alert_handler_lpg_sleep_mode_alerts.1012057593 |
| Short name | T723 |
| Test name | |
| Test status | |
| Simulation time | 3362325476 ps |
| CPU time | 423.43 seconds |
| Started | Aug 13 07:34:55 PM PDT 24 |
| Finished | Aug 13 07:41:59 PM PDT 24 |
| Peak memory | 649548 kb |
| Host | smart-a9550690-9821-4110-bf06-72c85d440974 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1012057593 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.chip_ sw_alert_handler_lpg_sleep_mode_alerts.1012057593 |
| Directory | /workspace/19.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/19.chip_sw_all_escalation_resets.243679470 |
| Short name | T1090 |
| Test name | |
| Test status | |
| Simulation time | 5244248608 ps |
| CPU time | 659.26 seconds |
| Started | Aug 13 07:35:22 PM PDT 24 |
| Finished | Aug 13 07:46:22 PM PDT 24 |
| Peak memory | 650704 kb |
| Host | smart-7abd2d8b-bcff-4c37-a542-fc5e406b2585 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 243679470 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.chip_sw_all_escalation_resets.243679470 |
| Directory | /workspace/19.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/2.chip_sw_all_escalation_resets.2046865755 |
| Short name | T787 |
| Test name | |
| Test status | |
| Simulation time | 4407549210 ps |
| CPU time | 529.1 seconds |
| Started | Aug 13 07:22:30 PM PDT 24 |
| Finished | Aug 13 07:31:19 PM PDT 24 |
| Peak memory | 650804 kb |
| Host | smart-1a9d313d-74ae-4153-aba2-5378bfe46686 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 2046865755 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_all_escalation_resets.2046865755 |
| Directory | /workspace/2.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/20.chip_sw_all_escalation_resets.232845337 |
| Short name | T1050 |
| Test name | |
| Test status | |
| Simulation time | 4265562192 ps |
| CPU time | 623.56 seconds |
| Started | Aug 13 07:34:52 PM PDT 24 |
| Finished | Aug 13 07:45:16 PM PDT 24 |
| Peak memory | 651144 kb |
| Host | smart-51d82113-73a5-4a05-ab10-a44f6d112a2c |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 232845337 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.chip_sw_all_escalation_resets.232845337 |
| Directory | /workspace/20.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/21.chip_sw_alert_handler_lpg_sleep_mode_alerts.3644420223 |
| Short name | T826 |
| Test name | |
| Test status | |
| Simulation time | 3156427424 ps |
| CPU time | 426.33 seconds |
| Started | Aug 13 07:34:26 PM PDT 24 |
| Finished | Aug 13 07:41:33 PM PDT 24 |
| Peak memory | 649516 kb |
| Host | smart-97b3d7a1-8f5b-4bb9-b3da-41ab80de7bce |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3644420223 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.chip_ sw_alert_handler_lpg_sleep_mode_alerts.3644420223 |
| Directory | /workspace/21.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/22.chip_sw_alert_handler_lpg_sleep_mode_alerts.2521211754 |
| Short name | T809 |
| Test name | |
| Test status | |
| Simulation time | 3793597940 ps |
| CPU time | 383.39 seconds |
| Started | Aug 13 07:36:49 PM PDT 24 |
| Finished | Aug 13 07:43:13 PM PDT 24 |
| Peak memory | 649500 kb |
| Host | smart-3a77b599-ae93-40e0-b711-1414c1ddbc4a |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2521211754 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.chip_ sw_alert_handler_lpg_sleep_mode_alerts.2521211754 |
| Directory | /workspace/22.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/22.chip_sw_all_escalation_resets.1569272445 |
| Short name | T804 |
| Test name | |
| Test status | |
| Simulation time | 4853402802 ps |
| CPU time | 605.63 seconds |
| Started | Aug 13 07:36:46 PM PDT 24 |
| Finished | Aug 13 07:46:52 PM PDT 24 |
| Peak memory | 650680 kb |
| Host | smart-2cc17f42-d461-44b8-a82d-eaa16cf41f7c |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 1569272445 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.chip_sw_all_escalation_resets.1569272445 |
| Directory | /workspace/22.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/24.chip_sw_alert_handler_lpg_sleep_mode_alerts.3309624210 |
| Short name | T771 |
| Test name | |
| Test status | |
| Simulation time | 3304427112 ps |
| CPU time | 342.97 seconds |
| Started | Aug 13 07:36:52 PM PDT 24 |
| Finished | Aug 13 07:42:35 PM PDT 24 |
| Peak memory | 649244 kb |
| Host | smart-34cd6886-c58e-43f2-9926-58feb494b498 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3309624210 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.chip_ sw_alert_handler_lpg_sleep_mode_alerts.3309624210 |
| Directory | /workspace/24.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/24.chip_sw_all_escalation_resets.75681393 |
| Short name | T853 |
| Test name | |
| Test status | |
| Simulation time | 5137793152 ps |
| CPU time | 602.22 seconds |
| Started | Aug 13 07:34:59 PM PDT 24 |
| Finished | Aug 13 07:45:01 PM PDT 24 |
| Peak memory | 650412 kb |
| Host | smart-c2e6a71b-2f9a-4fe4-87a9-258fbd3bba7b |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 75681393 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.chip_sw_all_escalation_resets.75681393 |
| Directory | /workspace/24.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/25.chip_sw_alert_handler_lpg_sleep_mode_alerts.3809993362 |
| Short name | T819 |
| Test name | |
| Test status | |
| Simulation time | 4104080224 ps |
| CPU time | 441.95 seconds |
| Started | Aug 13 07:38:08 PM PDT 24 |
| Finished | Aug 13 07:45:30 PM PDT 24 |
| Peak memory | 649948 kb |
| Host | smart-e1739736-29e6-4654-8a1a-9e02f7322b09 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3809993362 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.chip_ sw_alert_handler_lpg_sleep_mode_alerts.3809993362 |
| Directory | /workspace/25.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/26.chip_sw_all_escalation_resets.655752770 |
| Short name | T1281 |
| Test name | |
| Test status | |
| Simulation time | 5319920578 ps |
| CPU time | 588.76 seconds |
| Started | Aug 13 07:36:01 PM PDT 24 |
| Finished | Aug 13 07:45:50 PM PDT 24 |
| Peak memory | 650752 kb |
| Host | smart-9c3795ce-821b-44fe-911c-84c8ead340a8 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 655752770 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.chip_sw_all_escalation_resets.655752770 |
| Directory | /workspace/26.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/27.chip_sw_all_escalation_resets.3907963118 |
| Short name | T231 |
| Test name | |
| Test status | |
| Simulation time | 5012004928 ps |
| CPU time | 581.83 seconds |
| Started | Aug 13 07:35:27 PM PDT 24 |
| Finished | Aug 13 07:45:09 PM PDT 24 |
| Peak memory | 650648 kb |
| Host | smart-52ad4ac5-bc07-4566-9a91-8070e8f918c7 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 3907963118 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.chip_sw_all_escalation_resets.3907963118 |
| Directory | /workspace/27.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/28.chip_sw_alert_handler_lpg_sleep_mode_alerts.3284459955 |
| Short name | T724 |
| Test name | |
| Test status | |
| Simulation time | 3269652680 ps |
| CPU time | 372.09 seconds |
| Started | Aug 13 07:35:46 PM PDT 24 |
| Finished | Aug 13 07:41:59 PM PDT 24 |
| Peak memory | 649516 kb |
| Host | smart-e27b1773-b4f4-4519-9547-489f73a1781b |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3284459955 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.chip_ sw_alert_handler_lpg_sleep_mode_alerts.3284459955 |
| Directory | /workspace/28.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/30.chip_sw_alert_handler_lpg_sleep_mode_alerts.2185329967 |
| Short name | T807 |
| Test name | |
| Test status | |
| Simulation time | 3268102870 ps |
| CPU time | 372.5 seconds |
| Started | Aug 13 07:36:02 PM PDT 24 |
| Finished | Aug 13 07:42:15 PM PDT 24 |
| Peak memory | 649532 kb |
| Host | smart-d0c3f849-ebc2-468d-98d1-90222fcc0771 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2185329967 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.chip_ sw_alert_handler_lpg_sleep_mode_alerts.2185329967 |
| Directory | /workspace/30.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/30.chip_sw_all_escalation_resets.942492487 |
| Short name | T845 |
| Test name | |
| Test status | |
| Simulation time | 5492461952 ps |
| CPU time | 706.05 seconds |
| Started | Aug 13 07:37:15 PM PDT 24 |
| Finished | Aug 13 07:49:01 PM PDT 24 |
| Peak memory | 650728 kb |
| Host | smart-fa275f8c-4123-4c29-98e1-8db59f3e5e36 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 942492487 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.chip_sw_all_escalation_resets.942492487 |
| Directory | /workspace/30.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/31.chip_sw_alert_handler_lpg_sleep_mode_alerts.871366988 |
| Short name | T829 |
| Test name | |
| Test status | |
| Simulation time | 3538110946 ps |
| CPU time | 443.85 seconds |
| Started | Aug 13 07:39:09 PM PDT 24 |
| Finished | Aug 13 07:46:34 PM PDT 24 |
| Peak memory | 649676 kb |
| Host | smart-6e2a3b10-6b84-4064-a5ec-d266e99ab5fc |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=871366988 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all _escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.chip_s w_alert_handler_lpg_sleep_mode_alerts.871366988 |
| Directory | /workspace/31.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/33.chip_sw_alert_handler_lpg_sleep_mode_alerts.1991529525 |
| Short name | T450 |
| Test name | |
| Test status | |
| Simulation time | 3837476276 ps |
| CPU time | 554.31 seconds |
| Started | Aug 13 07:37:00 PM PDT 24 |
| Finished | Aug 13 07:46:14 PM PDT 24 |
| Peak memory | 649500 kb |
| Host | smart-12816ff6-93f4-4b8a-810e-1dfa2a69a4af |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1991529525 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.chip_ sw_alert_handler_lpg_sleep_mode_alerts.1991529525 |
| Directory | /workspace/33.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/36.chip_sw_alert_handler_lpg_sleep_mode_alerts.1353844681 |
| Short name | T847 |
| Test name | |
| Test status | |
| Simulation time | 4253530630 ps |
| CPU time | 401.88 seconds |
| Started | Aug 13 07:38:55 PM PDT 24 |
| Finished | Aug 13 07:45:37 PM PDT 24 |
| Peak memory | 649208 kb |
| Host | smart-bea73b2e-7485-407e-b7a4-27834363e5fd |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1353844681 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.chip_ sw_alert_handler_lpg_sleep_mode_alerts.1353844681 |
| Directory | /workspace/36.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/37.chip_sw_alert_handler_lpg_sleep_mode_alerts.2121900281 |
| Short name | T785 |
| Test name | |
| Test status | |
| Simulation time | 3574591560 ps |
| CPU time | 394.23 seconds |
| Started | Aug 13 07:37:38 PM PDT 24 |
| Finished | Aug 13 07:44:12 PM PDT 24 |
| Peak memory | 649456 kb |
| Host | smart-2b25fe46-b6f7-4985-8f32-bcb5e6d6c0dc |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2121900281 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.chip_ sw_alert_handler_lpg_sleep_mode_alerts.2121900281 |
| Directory | /workspace/37.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/37.chip_sw_all_escalation_resets.3807759857 |
| Short name | T817 |
| Test name | |
| Test status | |
| Simulation time | 5200368312 ps |
| CPU time | 712.28 seconds |
| Started | Aug 13 07:39:00 PM PDT 24 |
| Finished | Aug 13 07:50:53 PM PDT 24 |
| Peak memory | 650776 kb |
| Host | smart-1df52d9d-a67d-47f6-9e94-57711e59d4e7 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 3807759857 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.chip_sw_all_escalation_resets.3807759857 |
| Directory | /workspace/37.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/4.chip_sw_alert_handler_lpg_sleep_mode_alerts.884858286 |
| Short name | T822 |
| Test name | |
| Test status | |
| Simulation time | 4547557400 ps |
| CPU time | 537.94 seconds |
| Started | Aug 13 07:35:28 PM PDT 24 |
| Finished | Aug 13 07:44:26 PM PDT 24 |
| Peak memory | 649604 kb |
| Host | smart-09d794aa-8d67-4667-b726-17925181b7f6 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=884858286 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all _escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.chip_sw _alert_handler_lpg_sleep_mode_alerts.884858286 |
| Directory | /workspace/4.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/40.chip_sw_alert_handler_lpg_sleep_mode_alerts.2390665522 |
| Short name | T854 |
| Test name | |
| Test status | |
| Simulation time | 3925102500 ps |
| CPU time | 350.6 seconds |
| Started | Aug 13 07:37:04 PM PDT 24 |
| Finished | Aug 13 07:42:55 PM PDT 24 |
| Peak memory | 649520 kb |
| Host | smart-1edd6351-5284-4f3e-b70d-3ee6a8e00990 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2390665522 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.chip_ sw_alert_handler_lpg_sleep_mode_alerts.2390665522 |
| Directory | /workspace/40.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/41.chip_sw_alert_handler_lpg_sleep_mode_alerts.1090470863 |
| Short name | T768 |
| Test name | |
| Test status | |
| Simulation time | 4420693576 ps |
| CPU time | 527.95 seconds |
| Started | Aug 13 07:37:22 PM PDT 24 |
| Finished | Aug 13 07:46:10 PM PDT 24 |
| Peak memory | 649564 kb |
| Host | smart-fb7e2a10-a50f-4cc1-830f-4b20082b4a47 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1090470863 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.chip_ sw_alert_handler_lpg_sleep_mode_alerts.1090470863 |
| Directory | /workspace/41.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/47.chip_sw_alert_handler_lpg_sleep_mode_alerts.2757027469 |
| Short name | T815 |
| Test name | |
| Test status | |
| Simulation time | 3240797148 ps |
| CPU time | 412.65 seconds |
| Started | Aug 13 07:36:54 PM PDT 24 |
| Finished | Aug 13 07:43:47 PM PDT 24 |
| Peak memory | 649816 kb |
| Host | smart-94683f3e-9d30-4f50-b7a4-1b10f3cba4c5 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2757027469 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.chip_ sw_alert_handler_lpg_sleep_mode_alerts.2757027469 |
| Directory | /workspace/47.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/49.chip_sw_alert_handler_lpg_sleep_mode_alerts.3702669663 |
| Short name | T858 |
| Test name | |
| Test status | |
| Simulation time | 3779798726 ps |
| CPU time | 469.18 seconds |
| Started | Aug 13 07:43:05 PM PDT 24 |
| Finished | Aug 13 07:50:54 PM PDT 24 |
| Peak memory | 649588 kb |
| Host | smart-9336cc04-aba7-4311-8cf9-065ad8a1020b |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3702669663 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.chip_ sw_alert_handler_lpg_sleep_mode_alerts.3702669663 |
| Directory | /workspace/49.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/50.chip_sw_all_escalation_resets.3132455156 |
| Short name | T831 |
| Test name | |
| Test status | |
| Simulation time | 4495545512 ps |
| CPU time | 490.59 seconds |
| Started | Aug 13 07:37:22 PM PDT 24 |
| Finished | Aug 13 07:45:33 PM PDT 24 |
| Peak memory | 650912 kb |
| Host | smart-ee5d6ab8-b576-4697-bcc6-3d3cb57d6f51 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 3132455156 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 50.chip_sw_all_escalation_resets.3132455156 |
| Directory | /workspace/50.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/53.chip_sw_all_escalation_resets.953638028 |
| Short name | T840 |
| Test name | |
| Test status | |
| Simulation time | 5068714400 ps |
| CPU time | 488.94 seconds |
| Started | Aug 13 07:38:03 PM PDT 24 |
| Finished | Aug 13 07:46:12 PM PDT 24 |
| Peak memory | 650840 kb |
| Host | smart-e786c908-e1b5-4efa-9916-9c3ee593f7eb |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 953638028 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 53.chip_sw_all_escalation_resets.953638028 |
| Directory | /workspace/53.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/54.chip_sw_all_escalation_resets.811780496 |
| Short name | T801 |
| Test name | |
| Test status | |
| Simulation time | 4597560882 ps |
| CPU time | 496.28 seconds |
| Started | Aug 13 07:39:27 PM PDT 24 |
| Finished | Aug 13 07:47:43 PM PDT 24 |
| Peak memory | 650932 kb |
| Host | smart-1a458aee-afab-4130-b840-f6fb04e03e18 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 811780496 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 54.chip_sw_all_escalation_resets.811780496 |
| Directory | /workspace/54.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/55.chip_sw_all_escalation_resets.1219743647 |
| Short name | T828 |
| Test name | |
| Test status | |
| Simulation time | 5194405504 ps |
| CPU time | 485.43 seconds |
| Started | Aug 13 07:38:43 PM PDT 24 |
| Finished | Aug 13 07:46:48 PM PDT 24 |
| Peak memory | 649764 kb |
| Host | smart-cd507c19-8c6b-4338-9cc8-a006b9524ecb |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 1219743647 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 55.chip_sw_all_escalation_resets.1219743647 |
| Directory | /workspace/55.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/57.chip_sw_all_escalation_resets.1627847608 |
| Short name | T814 |
| Test name | |
| Test status | |
| Simulation time | 5234885360 ps |
| CPU time | 651.02 seconds |
| Started | Aug 13 07:39:15 PM PDT 24 |
| Finished | Aug 13 07:50:06 PM PDT 24 |
| Peak memory | 651052 kb |
| Host | smart-7ffdff70-43f3-45f0-9750-defc29b0af6f |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 1627847608 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 57.chip_sw_all_escalation_resets.1627847608 |
| Directory | /workspace/57.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/6.chip_sw_alert_handler_lpg_sleep_mode_alerts.2464772758 |
| Short name | T808 |
| Test name | |
| Test status | |
| Simulation time | 3965932888 ps |
| CPU time | 487.48 seconds |
| Started | Aug 13 07:34:03 PM PDT 24 |
| Finished | Aug 13 07:42:11 PM PDT 24 |
| Peak memory | 649488 kb |
| Host | smart-f8975284-6acf-4944-a425-3f2de3e3509c |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2464772758 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.chip_s w_alert_handler_lpg_sleep_mode_alerts.2464772758 |
| Directory | /workspace/6.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/6.chip_sw_all_escalation_resets.3058486102 |
| Short name | T813 |
| Test name | |
| Test status | |
| Simulation time | 5740774936 ps |
| CPU time | 787.97 seconds |
| Started | Aug 13 07:33:23 PM PDT 24 |
| Finished | Aug 13 07:46:33 PM PDT 24 |
| Peak memory | 650768 kb |
| Host | smart-db5afbfd-bc8a-4d1c-a237-879cbd55a8b5 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 3058486102 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.chip_sw_all_escalation_resets.3058486102 |
| Directory | /workspace/6.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/62.chip_sw_all_escalation_resets.371139345 |
| Short name | T84 |
| Test name | |
| Test status | |
| Simulation time | 4918449462 ps |
| CPU time | 665.64 seconds |
| Started | Aug 13 07:39:53 PM PDT 24 |
| Finished | Aug 13 07:51:00 PM PDT 24 |
| Peak memory | 650976 kb |
| Host | smart-3196df74-29fc-409f-97c4-28d4147b73bb |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 371139345 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 62.chip_sw_all_escalation_resets.371139345 |
| Directory | /workspace/62.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/63.chip_sw_alert_handler_lpg_sleep_mode_alerts.87857176 |
| Short name | T852 |
| Test name | |
| Test status | |
| Simulation time | 4078008300 ps |
| CPU time | 411.46 seconds |
| Started | Aug 13 07:39:50 PM PDT 24 |
| Finished | Aug 13 07:46:42 PM PDT 24 |
| Peak memory | 649704 kb |
| Host | smart-849d4319-411c-4528-a0bd-82f291338f4d |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87857176 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_ escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 63.chip_sw _alert_handler_lpg_sleep_mode_alerts.87857176 |
| Directory | /workspace/63.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/63.chip_sw_all_escalation_resets.2068291129 |
| Short name | T777 |
| Test name | |
| Test status | |
| Simulation time | 4488209378 ps |
| CPU time | 678.61 seconds |
| Started | Aug 13 07:38:59 PM PDT 24 |
| Finished | Aug 13 07:50:17 PM PDT 24 |
| Peak memory | 650896 kb |
| Host | smart-cdd76754-ddfa-4461-947e-783e66f24f10 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 2068291129 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 63.chip_sw_all_escalation_resets.2068291129 |
| Directory | /workspace/63.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/67.chip_sw_all_escalation_resets.1205670536 |
| Short name | T796 |
| Test name | |
| Test status | |
| Simulation time | 6441321522 ps |
| CPU time | 544.91 seconds |
| Started | Aug 13 07:40:28 PM PDT 24 |
| Finished | Aug 13 07:49:33 PM PDT 24 |
| Peak memory | 650784 kb |
| Host | smart-507b473d-259f-4791-b3b1-19904325f796 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 1205670536 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 67.chip_sw_all_escalation_resets.1205670536 |
| Directory | /workspace/67.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/7.chip_sw_alert_handler_lpg_sleep_mode_alerts.2163312399 |
| Short name | T254 |
| Test name | |
| Test status | |
| Simulation time | 3450420710 ps |
| CPU time | 438.3 seconds |
| Started | Aug 13 07:33:44 PM PDT 24 |
| Finished | Aug 13 07:41:03 PM PDT 24 |
| Peak memory | 649264 kb |
| Host | smart-ecf55983-5b9e-4b96-93db-36b948b051e7 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2163312399 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.chip_s w_alert_handler_lpg_sleep_mode_alerts.2163312399 |
| Directory | /workspace/7.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/7.chip_sw_all_escalation_resets.2505339715 |
| Short name | T458 |
| Test name | |
| Test status | |
| Simulation time | 5566921514 ps |
| CPU time | 794.86 seconds |
| Started | Aug 13 07:34:38 PM PDT 24 |
| Finished | Aug 13 07:47:53 PM PDT 24 |
| Peak memory | 650800 kb |
| Host | smart-7c4a0b56-891a-418c-b50e-d54c6c2e6ed8 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 2505339715 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.chip_sw_all_escalation_resets.2505339715 |
| Directory | /workspace/7.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/73.chip_sw_alert_handler_lpg_sleep_mode_alerts.1940693666 |
| Short name | T424 |
| Test name | |
| Test status | |
| Simulation time | 3083707600 ps |
| CPU time | 293.27 seconds |
| Started | Aug 13 07:41:00 PM PDT 24 |
| Finished | Aug 13 07:45:53 PM PDT 24 |
| Peak memory | 649780 kb |
| Host | smart-563f2e7f-bc56-4c2a-bcf7-08ce4474efb9 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1940693666 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 73.chip_ sw_alert_handler_lpg_sleep_mode_alerts.1940693666 |
| Directory | /workspace/73.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/74.chip_sw_alert_handler_lpg_sleep_mode_alerts.3346244624 |
| Short name | T795 |
| Test name | |
| Test status | |
| Simulation time | 3287143424 ps |
| CPU time | 432.16 seconds |
| Started | Aug 13 07:40:23 PM PDT 24 |
| Finished | Aug 13 07:47:36 PM PDT 24 |
| Peak memory | 649472 kb |
| Host | smart-f3a7e516-f5f2-405c-9304-f9e7398ce728 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3346244624 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 74.chip_ sw_alert_handler_lpg_sleep_mode_alerts.3346244624 |
| Directory | /workspace/74.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/74.chip_sw_all_escalation_resets.2131336027 |
| Short name | T799 |
| Test name | |
| Test status | |
| Simulation time | 4467050630 ps |
| CPU time | 675.07 seconds |
| Started | Aug 13 07:39:49 PM PDT 24 |
| Finished | Aug 13 07:51:04 PM PDT 24 |
| Peak memory | 650952 kb |
| Host | smart-3c0d357a-9b95-465d-91ee-ba0b28de0d8c |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 2131336027 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 74.chip_sw_all_escalation_resets.2131336027 |
| Directory | /workspace/74.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/76.chip_sw_alert_handler_lpg_sleep_mode_alerts.2311901317 |
| Short name | T843 |
| Test name | |
| Test status | |
| Simulation time | 3777008476 ps |
| CPU time | 373.79 seconds |
| Started | Aug 13 07:40:50 PM PDT 24 |
| Finished | Aug 13 07:47:04 PM PDT 24 |
| Peak memory | 649240 kb |
| Host | smart-c18f794b-4816-4557-a860-0dd3730e4048 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2311901317 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 76.chip_ sw_alert_handler_lpg_sleep_mode_alerts.2311901317 |
| Directory | /workspace/76.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/77.chip_sw_alert_handler_lpg_sleep_mode_alerts.728227777 |
| Short name | T830 |
| Test name | |
| Test status | |
| Simulation time | 4010801016 ps |
| CPU time | 264.47 seconds |
| Started | Aug 13 07:40:24 PM PDT 24 |
| Finished | Aug 13 07:44:49 PM PDT 24 |
| Peak memory | 649660 kb |
| Host | smart-14dfced0-b42a-4da9-b17f-2719abec2c31 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=728227777 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all _escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 77.chip_s w_alert_handler_lpg_sleep_mode_alerts.728227777 |
| Directory | /workspace/77.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/80.chip_sw_all_escalation_resets.1598604898 |
| Short name | T769 |
| Test name | |
| Test status | |
| Simulation time | 5953184836 ps |
| CPU time | 613.46 seconds |
| Started | Aug 13 07:40:06 PM PDT 24 |
| Finished | Aug 13 07:50:20 PM PDT 24 |
| Peak memory | 650708 kb |
| Host | smart-4276888f-2f7e-460d-bf08-d7840a767c84 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 1598604898 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 80.chip_sw_all_escalation_resets.1598604898 |
| Directory | /workspace/80.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/83.chip_sw_alert_handler_lpg_sleep_mode_alerts.2335747882 |
| Short name | T164 |
| Test name | |
| Test status | |
| Simulation time | 3789094800 ps |
| CPU time | 338.23 seconds |
| Started | Aug 13 07:41:50 PM PDT 24 |
| Finished | Aug 13 07:47:28 PM PDT 24 |
| Peak memory | 649592 kb |
| Host | smart-c91d2f0a-9b22-4b58-82ff-42bf7594427c |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2335747882 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 83.chip_ sw_alert_handler_lpg_sleep_mode_alerts.2335747882 |
| Directory | /workspace/83.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/89.chip_sw_all_escalation_resets.2121319102 |
| Short name | T380 |
| Test name | |
| Test status | |
| Simulation time | 4799329386 ps |
| CPU time | 667.75 seconds |
| Started | Aug 13 07:42:21 PM PDT 24 |
| Finished | Aug 13 07:53:29 PM PDT 24 |
| Peak memory | 650452 kb |
| Host | smart-b58f3a49-a2f8-41d0-92b2-76e4ed6452c3 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 2121319102 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 89.chip_sw_all_escalation_resets.2121319102 |
| Directory | /workspace/89.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/97.chip_sw_all_escalation_resets.2591319193 |
| Short name | T384 |
| Test name | |
| Test status | |
| Simulation time | 4930295160 ps |
| CPU time | 584.2 seconds |
| Started | Aug 13 07:41:51 PM PDT 24 |
| Finished | Aug 13 07:51:35 PM PDT 24 |
| Peak memory | 650732 kb |
| Host | smart-f8d4e012-3bdf-485a-9496-7ba6abb5075b |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 2591319193 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 97.chip_sw_all_escalation_resets.2591319193 |
| Directory | /workspace/97.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/98.chip_sw_all_escalation_resets.2053248979 |
| Short name | T820 |
| Test name | |
| Test status | |
| Simulation time | 4729989208 ps |
| CPU time | 401.14 seconds |
| Started | Aug 13 07:41:04 PM PDT 24 |
| Finished | Aug 13 07:47:45 PM PDT 24 |
| Peak memory | 651104 kb |
| Host | smart-c20258fe-da07-4a37-a9bb-5030d756f872 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 2053248979 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 98.chip_sw_all_escalation_resets.2053248979 |
| Directory | /workspace/98.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/0.chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up.3547244380 |
| Short name | T374 |
| Test name | |
| Test status | |
| Simulation time | 4878494238 ps |
| CPU time | 378.86 seconds |
| Started | Aug 13 07:12:35 PM PDT 24 |
| Finished | Aug 13 07:18:54 PM PDT 24 |
| Peak memory | 611940 kb |
| Host | smart-a96ac919-a295-4e93-9493-d08046716d0d |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +do_random=1 +sw_build_device=sim_dv +sw_images=pwrmgr_sensor_ctrl_deep_sleep_wake_up:1:new_rul es,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t cl +ntb_random_seed=3547244380 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_pwrmgr_sensor_ctrl_deep_s leep_wake_up.3547244380 |
| Directory | /workspace/0.chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up/latest |
| Test location | /workspace/coverage/default/4.chip_sw_all_escalation_resets.122935670 |
| Short name | T739 |
| Test name | |
| Test status | |
| Simulation time | 4530102040 ps |
| CPU time | 716.27 seconds |
| Started | Aug 13 07:34:09 PM PDT 24 |
| Finished | Aug 13 07:46:06 PM PDT 24 |
| Peak memory | 611732 kb |
| Host | smart-0df4e8b1-00a0-4595-9a96-21b262aa6ac0 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 122935670 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.chip_sw_all_escalation_resets.122935670 |
| Directory | /workspace/4.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/cover_reg_top/3.chip_csr_hw_reset.2118127131 |
| Short name | T144 |
| Test name | |
| Test status | |
| Simulation time | 4382560754 ps |
| CPU time | 240.02 seconds |
| Started | Aug 13 06:50:42 PM PDT 24 |
| Finished | Aug 13 06:54:42 PM PDT 24 |
| Peak memory | 663412 kb |
| Host | smart-b912ede6-86d5-4479-84f2-2658a1940285 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2118127131 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.chip_csr_hw_r eset.2118127131 |
| Directory | /workspace/3.chip_csr_hw_reset/latest |
| Test location | /workspace/coverage/default/0.chip_rv_dm_ndm_reset_req.194207069 |
| Short name | T109 |
| Test name | |
| Test status | |
| Simulation time | 5497818276 ps |
| CPU time | 489.9 seconds |
| Started | Aug 13 07:14:12 PM PDT 24 |
| Finished | Aug 13 07:22:22 PM PDT 24 |
| Peak memory | 620268 kb |
| Host | smart-99a014eb-18c5-4663-9fc9-fa90affb0745 |
| User | root |
| Command | /workspace/default/simv +en_scb_tl_err_chk=0 +use_jtag_dmi=1 +sw_build_device=sim_dv +sw_images=rv_dm_ndm_reset_req_rma:1:new_rules,test_rom:0 +cdc_in strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1 94207069 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_rv_dm_ndm_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_rv_dm_ndm_reset_req.194207069 |
| Directory | /workspace/0.chip_rv_dm_ndm_reset_req/latest |
| Test location | /workspace/coverage/default/0.chip_sw_pwrmgr_full_aon_reset.1388438146 |
| Short name | T149 |
| Test name | |
| Test status | |
| Simulation time | 8089823072 ps |
| CPU time | 454.2 seconds |
| Started | Aug 13 07:08:27 PM PDT 24 |
| Finished | Aug 13 07:16:01 PM PDT 24 |
| Peak memory | 610876 kb |
| Host | smart-2eca2ed9-b58e-4d50-bff4-ad593e839539 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=rstmgr_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1388438146 -assert nopostproc +UVM_TESTNAME=c hip_base_test +UVM_TEST_SEQ=chip_sw_full_aon_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_ log /dev/null -cm_name 0.chip_sw_pwrmgr_full_aon_reset.1388438146 |
| Directory | /workspace/0.chip_sw_pwrmgr_full_aon_reset/latest |
| Test location | /workspace/coverage/default/0.chip_sw_sysrst_ctrl_in_irq.836202391 |
| Short name | T217 |
| Test name | |
| Test status | |
| Simulation time | 4714479666 ps |
| CPU time | 567.02 seconds |
| Started | Aug 13 07:10:56 PM PDT 24 |
| Finished | Aug 13 07:20:26 PM PDT 24 |
| Peak memory | 614236 kb |
| Host | smart-ae4d4161-66f6-400a-b1a2-2a1596f9bc8f |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=sysrst_ctrl_in_irq_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=836202391 -assert nopostproc +UVM_TEST NAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sysrst_ctrl_in_irq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul t.vdb -cm_log /dev/null -cm_name 0.chip_sw_sysrst_ctrl_in_irq.836202391 |
| Directory | /workspace/0.chip_sw_sysrst_ctrl_in_irq/latest |
| Test location | /workspace/coverage/default/0.chip_sw_rv_dm_access_after_escalation_reset.3400362633 |
| Short name | T736 |
| Test name | |
| Test status | |
| Simulation time | 5617672933 ps |
| CPU time | 487.64 seconds |
| Started | Aug 13 07:11:31 PM PDT 24 |
| Finished | Aug 13 07:19:39 PM PDT 24 |
| Peak memory | 624684 kb |
| Host | smart-041746ab-b3a2-40df-b8e4-1c3504326d96 |
| User | root |
| Command | /workspace/default/simv +use_jtag_dmi=1 +sw_build_device=sim_dv +sw_images=alert_handler_escalation_test:1:new_rules,test_rom:0 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3400362633 -asse rt nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rv_dm_access_after_escalation_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_rv_dm_access_after_escalation_reset.3400362633 |
| Directory | /workspace/0.chip_sw_rv_dm_access_after_escalation_reset/latest |
| Test location | /workspace/coverage/default/0.chip_tap_straps_dev.1017871518 |
| Short name | T452 |
| Test name | |
| Test status | |
| Simulation time | 16649258255 ps |
| CPU time | 2079.91 seconds |
| Started | Aug 13 07:10:31 PM PDT 24 |
| Finished | Aug 13 07:45:12 PM PDT 24 |
| Peak memory | 633828 kb |
| Host | smart-33e46dce-65ce-4d70-88b9-18eecf37a367 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStDev +create_jtag_riscv_map=1 +sw_build_device=sim_dv +sw_images=example_test_from_rom:0:test_in_rom: new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=1017871518 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_tap_straps_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_tap_straps_dev.1017871518 |
| Directory | /workspace/0.chip_tap_straps_dev/latest |
| Test location | /workspace/coverage/cover_reg_top/0.xbar_stress_all.883151822 |
| Short name | T2730 |
| Test name | |
| Test status | |
| Simulation time | 1500854413 ps |
| CPU time | 108.15 seconds |
| Started | Aug 13 06:50:26 PM PDT 24 |
| Finished | Aug 13 06:52:15 PM PDT 24 |
| Peak memory | 575728 kb |
| Host | smart-568fccd9-45ba-4748-95fd-0f6e2bb450e8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=883151822 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.xbar_stress_all.883151822 |
| Directory | /workspace/0.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/15.xbar_stress_all_with_rand_reset.1169583447 |
| Short name | T506 |
| Test name | |
| Test status | |
| Simulation time | 1918026921 ps |
| CPU time | 164.84 seconds |
| Started | Aug 13 06:51:25 PM PDT 24 |
| Finished | Aug 13 06:54:10 PM PDT 24 |
| Peak memory | 576176 kb |
| Host | smart-5b06393f-2c15-41ee-bbae-c261d01b0334 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1169583447 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.xbar_stress_all _with_rand_reset.1169583447 |
| Directory | /workspace/15.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/16.chip_tl_errors.361941706 |
| Short name | T755 |
| Test name | |
| Test status | |
| Simulation time | 3856029640 ps |
| CPU time | 270.23 seconds |
| Started | Aug 13 06:51:25 PM PDT 24 |
| Finished | Aug 13 06:55:56 PM PDT 24 |
| Peak memory | 598368 kb |
| Host | smart-7dfe12cc-6c32-430c-af7d-e0710972b95f |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=361941706 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.chip_tl_errors.361941706 |
| Directory | /workspace/16.chip_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/16.xbar_stress_all_with_rand_reset.634990448 |
| Short name | T495 |
| Test name | |
| Test status | |
| Simulation time | 6538137122 ps |
| CPU time | 701.91 seconds |
| Started | Aug 13 06:51:27 PM PDT 24 |
| Finished | Aug 13 07:03:09 PM PDT 24 |
| Peak memory | 576548 kb |
| Host | smart-dc1bf2ab-4786-4ff2-80af-613b25002fa6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=634990448 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_res et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.xbar_stress_all_ with_rand_reset.634990448 |
| Directory | /workspace/16.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/0.chip_plic_all_irqs_10.259189008 |
| Short name | T160 |
| Test name | |
| Test status | |
| Simulation time | 3715434750 ps |
| CPU time | 702.18 seconds |
| Started | Aug 13 07:13:23 PM PDT 24 |
| Finished | Aug 13 07:25:06 PM PDT 24 |
| Peak memory | 610436 kb |
| Host | smart-db7241e9-1d53-4b63-aff6-8e696e147a27 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=plic_all_irqs_test_10:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=259189008 -assert nopostproc +UVM_TESTNA ME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 0.chip_plic_all_irqs_10.259189008 |
| Directory | /workspace/0.chip_plic_all_irqs_10/latest |
| Test location | /workspace/coverage/default/0.chip_sw_entropy_src_csrng.1225443076 |
| Short name | T335 |
| Test name | |
| Test status | |
| Simulation time | 7296864478 ps |
| CPU time | 1735.88 seconds |
| Started | Aug 13 07:12:38 PM PDT 24 |
| Finished | Aug 13 07:41:34 PM PDT 24 |
| Peak memory | 611064 kb |
| Host | smart-9f463ba2-f175-4294-80ee-fec60b6ff1ec |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=50_000_000 +rng_srate_value_min=15 +rng_srate_value_max=30 +sw_build_device=sim_dv +sw_images=entropy_src_ csrng_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1225443076 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_entropy_src_csrng.1225443076 |
| Directory | /workspace/0.chip_sw_entropy_src_csrng/latest |
| Test location | /workspace/coverage/default/0.chip_sw_gpio.2740689998 |
| Short name | T27 |
| Test name | |
| Test status | |
| Simulation time | 4057674252 ps |
| CPU time | 427.97 seconds |
| Started | Aug 13 07:10:13 PM PDT 24 |
| Finished | Aug 13 07:17:21 PM PDT 24 |
| Peak memory | 609864 kb |
| Host | smart-f397984f-6a87-449e-a843-1f33b4c10016 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=gpio_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2740689998 -assert nopostproc +UVM_TESTNAME=chip_bas e_test +UVM_TEST_SEQ=chip_sw_gpio_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm _name 0.chip_sw_gpio.2740689998 |
| Directory | /workspace/0.chip_sw_gpio/latest |
| Test location | /workspace/coverage/default/0.chip_sw_pwrmgr_lowpower_cancel.2743527689 |
| Short name | T347 |
| Test name | |
| Test status | |
| Simulation time | 3760347440 ps |
| CPU time | 526.61 seconds |
| Started | Aug 13 07:12:45 PM PDT 24 |
| Finished | Aug 13 07:21:33 PM PDT 24 |
| Peak memory | 610576 kb |
| Host | smart-544824e4-28f9-476c-92f5-0d4716d79f00 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_lowpower_cancel_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2743527689 -assert nopostproc +UVM _TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm _log /dev/null -cm_name 0.chip_sw_pwrmgr_lowpower_cancel.2743527689 |
| Directory | /workspace/0.chip_sw_pwrmgr_lowpower_cancel/latest |
| Test location | /workspace/coverage/default/0.chip_sw_rstmgr_alert_info.1720002093 |
| Short name | T333 |
| Test name | |
| Test status | |
| Simulation time | 13111930336 ps |
| CPU time | 1607.41 seconds |
| Started | Aug 13 07:08:35 PM PDT 24 |
| Finished | Aug 13 07:35:22 PM PDT 24 |
| Peak memory | 611644 kb |
| Host | smart-d1bdc94a-5dd2-4e25-a6c8-47a81cee03cc |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=30_000_000 +en_scb_tl_err_chk=0 +sw_build_device=sim_dv +sw_images=rstmgr_alert_info_test:1:new_rules,test _rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb _random_seed=1720002093 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_rstmgr_alert_info.1720002093 |
| Directory | /workspace/0.chip_sw_rstmgr_alert_info/latest |
| Test location | /workspace/coverage/default/1.chip_sw_uart_tx_rx_alt_clk_freq_low_speed.1472223838 |
| Short name | T122 |
| Test name | |
| Test status | |
| Simulation time | 3782462234 ps |
| CPU time | 453.47 seconds |
| Started | Aug 13 07:12:57 PM PDT 24 |
| Finished | Aug 13 07:20:31 PM PDT 24 |
| Peak memory | 624776 kb |
| Host | smart-49f532ab-cddd-49b5-b1b5-802350cc9f8e |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +chip_clock_source=ChipClockSourceExternal48Mhz +sw_build_device=sim_dv +s w_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1472223838 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_b audrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_uart_tx_rx _alt_clk_freq_low_speed.1472223838 |
| Directory | /workspace/1.chip_sw_uart_tx_rx_alt_clk_freq_low_speed/latest |
| Test location | /workspace/coverage/default/2.chip_sw_i2c_host_tx_rx_idx2.2549633585 |
| Short name | T228 |
| Test name | |
| Test status | |
| Simulation time | 4480870150 ps |
| CPU time | 749.3 seconds |
| Started | Aug 13 07:23:27 PM PDT 24 |
| Finished | Aug 13 07:35:57 PM PDT 24 |
| Peak memory | 611016 kb |
| Host | smart-5cb3d389-1bb6-4fc4-9e7f-9d5292f7e02c |
| User | root |
| Command | /workspace/default/simv +i2c_idx=2 +sw_build_device=sim_dv +sw_images=i2c_host_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2549633585 -assert nopostproc + UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_i2c_host_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de fault.vdb -cm_log /dev/null -cm_name 2.chip_sw_i2c_host_tx_rx_idx2.2549633585 |
| Directory | /workspace/2.chip_sw_i2c_host_tx_rx_idx2/latest |
| Test location | /workspace/coverage/default/0.chip_sw_ast_clk_rst_inputs.449779002 |
| Short name | T115 |
| Test name | |
| Test status | |
| Simulation time | 16415770812 ps |
| CPU time | 2260.73 seconds |
| Started | Aug 13 07:13:25 PM PDT 24 |
| Finished | Aug 13 07:51:07 PM PDT 24 |
| Peak memory | 611796 kb |
| Host | smart-113c35b2-5dc7-446d-8e25-c13592c28d9e |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=200_000_000 +sw_build_device=sim_dv +sw_images=ast_clk_rst_inputs:1:new_rules,test_rom:0 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=449779002 - assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_ast_clk_rst_inputs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_ast_clk_rst_inputs.449779002 |
| Directory | /workspace/0.chip_sw_ast_clk_rst_inputs/latest |
| Test location | /workspace/coverage/default/0.chip_sw_keymgr_sideload_aes.3526467010 |
| Short name | T130 |
| Test name | |
| Test status | |
| Simulation time | 11264919760 ps |
| CPU time | 2149.38 seconds |
| Started | Aug 13 07:13:22 PM PDT 24 |
| Finished | Aug 13 07:49:12 PM PDT 24 |
| Peak memory | 611856 kb |
| Host | smart-39c63d9a-efb8-4dba-a3e4-e23a64116293 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=20_000_000 +sw_build_device=sim_dv +sw_images=keymgr_sideload_aes_test:1:new_rules,test_rom:0 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=352646 7010 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_keymgr_sideload_aes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_keymgr_sideload_aes.3526467010 |
| Directory | /workspace/0.chip_sw_keymgr_sideload_aes/latest |
| Test location | /workspace/coverage/default/0.chip_sw_spi_host_tx_rx.1630886635 |
| Short name | T31 |
| Test name | |
| Test status | |
| Simulation time | 3619430934 ps |
| CPU time | 237.43 seconds |
| Started | Aug 13 07:09:45 PM PDT 24 |
| Finished | Aug 13 07:13:43 PM PDT 24 |
| Peak memory | 610328 kb |
| Host | smart-6425fc7b-c163-47bd-9280-2ff39afa3535 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=spi_host_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1630886635 -assert nopostproc +UVM_TESTNAM E=chip_base_test +UVM_TEST_SEQ=chip_sw_spi_host_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb - cm_log /dev/null -cm_name 0.chip_sw_spi_host_tx_rx.1630886635 |
| Directory | /workspace/0.chip_sw_spi_host_tx_rx/latest |
| Test location | /workspace/coverage/default/0.chip_sw_keymgr_sideload_otbn.568915840 |
| Short name | T237 |
| Test name | |
| Test status | |
| Simulation time | 16769054744 ps |
| CPU time | 4237.87 seconds |
| Started | Aug 13 07:11:20 PM PDT 24 |
| Finished | Aug 13 08:21:58 PM PDT 24 |
| Peak memory | 611612 kb |
| Host | smart-f7c3e5ac-de97-44a3-b778-b6b40f350ef2 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=20_000_000 +sw_build_device=sim_dv +sw_images=keymgr_sideload_otbn_test:1:new_rules,test_rom:0 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=56891 5840 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_keymgr_sideload_otbn.568915840 |
| Directory | /workspace/0.chip_sw_keymgr_sideload_otbn/latest |
| Test location | /workspace/coverage/default/0.chip_sw_kmac_idle.3114571442 |
| Short name | T1129 |
| Test name | |
| Test status | |
| Simulation time | 2581177376 ps |
| CPU time | 257.02 seconds |
| Started | Aug 13 07:10:41 PM PDT 24 |
| Finished | Aug 13 07:14:59 PM PDT 24 |
| Peak memory | 610344 kb |
| Host | smart-5883a262-2b4f-42f7-b3aa-8019793c3775 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=kmac_idle_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3114571442 -assert nopostproc +UVM_TESTNAME=chi p_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul l -cm_name 0.chip_sw_kmac_idle.3114571442 |
| Directory | /workspace/0.chip_sw_kmac_idle/latest |
| Test location | /workspace/coverage/default/0.chip_sw_lc_ctrl_program_error.2868061506 |
| Short name | T174 |
| Test name | |
| Test status | |
| Simulation time | 5909646832 ps |
| CPU time | 435.54 seconds |
| Started | Aug 13 07:09:12 PM PDT 24 |
| Finished | Aug 13 07:16:28 PM PDT 24 |
| Peak memory | 611868 kb |
| Host | smart-0d1480da-9306-4499-9d51-743465fbd922 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=lc_ctrl_program_error:1:new_rules,test_rom:0 + cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_ seed=2868061506 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_program_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_lc_ctrl_program_error.2868061506 |
| Directory | /workspace/0.chip_sw_lc_ctrl_program_error/latest |
| Test location | /workspace/coverage/default/0.chip_sw_otp_ctrl_vendor_test_csr_access.2874739709 |
| Short name | T168 |
| Test name | |
| Test status | |
| Simulation time | 2056634682 ps |
| CPU time | 112.01 seconds |
| Started | Aug 13 07:16:40 PM PDT 24 |
| Finished | Aug 13 07:18:32 PM PDT 24 |
| Peak memory | 621472 kb |
| Host | smart-80d1e24e-d51f-45a7-848a-b6e3be646df1 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=otp_ctrl_vendor_test_csr_access_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2874739709 -assert nopost proc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_otp_ctrl_vendor_test_csr_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_otp_ctrl_vendor_test_csr_access.2874739709 |
| Directory | /workspace/0.chip_sw_otp_ctrl_vendor_test_csr_access/latest |
| Test location | /workspace/coverage/default/0.chip_sw_pwrmgr_deep_sleep_power_glitch_reset.188562509 |
| Short name | T962 |
| Test name | |
| Test status | |
| Simulation time | 8027334696 ps |
| CPU time | 570.1 seconds |
| Started | Aug 13 07:09:49 PM PDT 24 |
| Finished | Aug 13 07:19:20 PM PDT 24 |
| Peak memory | 618244 kb |
| Host | smart-66d25dae-0ca3-4519-9f1f-1567444fd571 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=pwrmgr_deep_sleep_power_glitch_test:1:new_rules,test_rom :0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=188562509 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_deep_power_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_pwrmgr_deep_sleep_power_glitch_reset.188562509 |
| Directory | /workspace/0.chip_sw_pwrmgr_deep_sleep_power_glitch_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/16.xbar_stress_all_with_error.2889534573 |
| Short name | T744 |
| Test name | |
| Test status | |
| Simulation time | 12391874810 ps |
| CPU time | 478.57 seconds |
| Started | Aug 13 06:51:26 PM PDT 24 |
| Finished | Aug 13 06:59:25 PM PDT 24 |
| Peak memory | 575684 kb |
| Host | smart-8d357a83-8df5-4954-89f2-bbdba33faaa7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2889534573 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.xbar_stress_all_with_error.2889534573 |
| Directory | /workspace/16.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/2.chip_tl_errors.1823350056 |
| Short name | T733 |
| Test name | |
| Test status | |
| Simulation time | 3468956024 ps |
| CPU time | 173.19 seconds |
| Started | Aug 13 06:50:48 PM PDT 24 |
| Finished | Aug 13 06:53:41 PM PDT 24 |
| Peak memory | 603480 kb |
| Host | smart-2ceca718-0960-4f9c-9477-2fc193e3803f |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1823350056 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.chip_tl_errors.1823350056 |
| Directory | /workspace/2.chip_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/21.xbar_stress_all_with_reset_error.4294495296 |
| Short name | T672 |
| Test name | |
| Test status | |
| Simulation time | 330463152 ps |
| CPU time | 81.74 seconds |
| Started | Aug 13 06:51:43 PM PDT 24 |
| Finished | Aug 13 06:53:05 PM PDT 24 |
| Peak memory | 575624 kb |
| Host | smart-e8bac511-d1ec-4fef-ba99-29a8187da0f9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4294495296 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.xbar_stress_al l_with_reset_error.4294495296 |
| Directory | /workspace/21.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/22.xbar_stress_all_with_error.3943965300 |
| Short name | T671 |
| Test name | |
| Test status | |
| Simulation time | 3624273996 ps |
| CPU time | 273.88 seconds |
| Started | Aug 13 06:51:55 PM PDT 24 |
| Finished | Aug 13 06:56:29 PM PDT 24 |
| Peak memory | 576532 kb |
| Host | smart-ac60d273-d518-4fcb-9fd5-f1eaf0bae051 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3943965300 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.xbar_stress_all_with_error.3943965300 |
| Directory | /workspace/22.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/4.chip_tl_errors.109512559 |
| Short name | T610 |
| Test name | |
| Test status | |
| Simulation time | 3629136680 ps |
| CPU time | 179.05 seconds |
| Started | Aug 13 06:50:38 PM PDT 24 |
| Finished | Aug 13 06:53:38 PM PDT 24 |
| Peak memory | 603464 kb |
| Host | smart-cf19e446-f4dc-4f50-a5b1-bcd6e3b66307 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=109512559 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.chip_tl_errors.109512559 |
| Directory | /workspace/4.chip_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/47.xbar_stress_all_with_error.1724480780 |
| Short name | T663 |
| Test name | |
| Test status | |
| Simulation time | 18493755925 ps |
| CPU time | 601.19 seconds |
| Started | Aug 13 06:54:37 PM PDT 24 |
| Finished | Aug 13 07:04:38 PM PDT 24 |
| Peak memory | 576524 kb |
| Host | smart-fd2f6620-c85a-4fd9-a969-e33c4446b202 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1724480780 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.xbar_stress_all_with_error.1724480780 |
| Directory | /workspace/47.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/81.xbar_error_random.3726074643 |
| Short name | T562 |
| Test name | |
| Test status | |
| Simulation time | 425837846 ps |
| CPU time | 32.86 seconds |
| Started | Aug 13 06:59:00 PM PDT 24 |
| Finished | Aug 13 06:59:33 PM PDT 24 |
| Peak memory | 575692 kb |
| Host | smart-a2d1411f-2b04-45e1-a69e-f8455cae4d3d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3726074643 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 81.xbar_error_random.3726074643 |
| Directory | /workspace/81.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/83.xbar_error_and_unmapped_addr.1080477948 |
| Short name | T681 |
| Test name | |
| Test status | |
| Simulation time | 752683451 ps |
| CPU time | 29.75 seconds |
| Started | Aug 13 06:59:14 PM PDT 24 |
| Finished | Aug 13 06:59:43 PM PDT 24 |
| Peak memory | 575636 kb |
| Host | smart-41e11621-d906-4af2-993d-b4f5e6c6c111 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1080477948 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 83.xbar_error_and_unmapped_add r.1080477948 |
| Directory | /workspace/83.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/86.xbar_stress_all_with_error.2239214858 |
| Short name | T668 |
| Test name | |
| Test status | |
| Simulation time | 752802429 ps |
| CPU time | 56.84 seconds |
| Started | Aug 13 06:59:38 PM PDT 24 |
| Finished | Aug 13 07:00:35 PM PDT 24 |
| Peak memory | 575692 kb |
| Host | smart-ec1f9a03-37a1-426e-813a-c63b09429782 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2239214858 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 86.xbar_stress_all_with_error.2239214858 |
| Directory | /workspace/86.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/97.xbar_stress_all_with_reset_error.3106795977 |
| Short name | T679 |
| Test name | |
| Test status | |
| Simulation time | 484013089 ps |
| CPU time | 142.15 seconds |
| Started | Aug 13 07:00:59 PM PDT 24 |
| Finished | Aug 13 07:03:21 PM PDT 24 |
| Peak memory | 576508 kb |
| Host | smart-2b09336d-5195-468f-9b9a-7b92649e44de |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3106795977 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 97.xbar_stress_al l_with_reset_error.3106795977 |
| Directory | /workspace/97.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/98.xbar_stress_all_with_error.685450956 |
| Short name | T665 |
| Test name | |
| Test status | |
| Simulation time | 10205141881 ps |
| CPU time | 370.23 seconds |
| Started | Aug 13 07:01:11 PM PDT 24 |
| Finished | Aug 13 07:07:22 PM PDT 24 |
| Peak memory | 576576 kb |
| Host | smart-2334beec-c7e3-4f8a-b7cd-f4396404bc6d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=685450956 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 98.xbar_stress_all_with_error.685450956 |
| Directory | /workspace/98.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/default/0.chip_sw_i2c_host_tx_rx_idx1.932453016 |
| Short name | T93 |
| Test name | |
| Test status | |
| Simulation time | 4714119164 ps |
| CPU time | 822.61 seconds |
| Started | Aug 13 07:09:25 PM PDT 24 |
| Finished | Aug 13 07:23:08 PM PDT 24 |
| Peak memory | 610724 kb |
| Host | smart-45b767d2-62dc-4fca-8143-02bc5f00fc5a |
| User | root |
| Command | /workspace/default/simv +i2c_idx=1 +sw_build_device=sim_dv +sw_images=i2c_host_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=932453016 -assert nopostproc +U VM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_i2c_host_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def ault.vdb -cm_log /dev/null -cm_name 0.chip_sw_i2c_host_tx_rx_idx1.932453016 |
| Directory | /workspace/0.chip_sw_i2c_host_tx_rx_idx1/latest |
| Test location | /workspace/coverage/default/0.chip_sw_rv_core_ibex_nmi_irq.96892489 |
| Short name | T546 |
| Test name | |
| Test status | |
| Simulation time | 4396642676 ps |
| CPU time | 847.7 seconds |
| Started | Aug 13 07:12:22 PM PDT 24 |
| Finished | Aug 13 07:26:30 PM PDT 24 |
| Peak memory | 610844 kb |
| Host | smart-50328df9-e606-4aea-8c96-6715f6632b95 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=10_000_000 +sw_build_device=sim_dv +sw_images=rv_core_ibex_nmi_irq_test:1:new_rules,test_rom:0 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=96892 489 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ce/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_rv_core_ibex_nmi_irq.96892489 |
| Directory | /workspace/0.chip_sw_rv_core_ibex_nmi_irq/latest |
| Test location | /workspace/coverage/default/1.chip_tap_straps_testunlock0.3701747531 |
| Short name | T1416 |
| Test name | |
| Test status | |
| Simulation time | 9218751791 ps |
| CPU time | 853.39 seconds |
| Started | Aug 13 07:18:31 PM PDT 24 |
| Finished | Aug 13 07:32:44 PM PDT 24 |
| Peak memory | 625720 kb |
| Host | smart-aa6879d5-d799-429a-981b-1248127940d7 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStTestUnlocked0 +create_jtag_riscv_map=1 +sw_build_device=sim_dv +sw_images=example_test_from_rom:0:te st_in_rom:new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3701747531 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_tap_straps_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_tap_straps_testunlock0.3701747531 |
| Directory | /workspace/1.chip_tap_straps_testunlock0/latest |
| Test location | /workspace/coverage/cover_reg_top/0.chip_csr_hw_reset.4058240205 |
| Short name | T142 |
| Test name | |
| Test status | |
| Simulation time | 4837982530 ps |
| CPU time | 269.48 seconds |
| Started | Aug 13 06:50:39 PM PDT 24 |
| Finished | Aug 13 06:55:08 PM PDT 24 |
| Peak memory | 659312 kb |
| Host | smart-47a91119-349b-4cfa-b65f-0f739bf483ad |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4058240205 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.chip_csr_hw_r eset.4058240205 |
| Directory | /workspace/0.chip_csr_hw_reset/latest |
| Test location | /workspace/coverage/default/0.chip_sw_csrng_fuse_en_sw_app_read_test.2047046688 |
| Short name | T193 |
| Test name | |
| Test status | |
| Simulation time | 5105950280 ps |
| CPU time | 437.89 seconds |
| Started | Aug 13 07:09:42 PM PDT 24 |
| Finished | Aug 13 07:17:00 PM PDT 24 |
| Peak memory | 611420 kb |
| Host | smart-7b7878d2-8ed1-48e3-bfd6-b4c2c670807a |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=15_000_000 +sw_build_device=sim_dv +sw_images=csrng_fuse_en_sw_app_read:1:new_rules,test_rom:0 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20470 46688 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_entropy_src_fuse_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_csrng_fuse_en_sw_app_read_test.2047046688 |
| Directory | /workspace/0.chip_sw_csrng_fuse_en_sw_app_read_test/latest |
| Test location | /workspace/coverage/default/0.chip_sw_edn_boot_mode.2032936015 |
| Short name | T720 |
| Test name | |
| Test status | |
| Simulation time | 3237550696 ps |
| CPU time | 643.48 seconds |
| Started | Aug 13 07:11:15 PM PDT 24 |
| Finished | Aug 13 07:21:59 PM PDT 24 |
| Peak memory | 610460 kb |
| Host | smart-606ccfc6-4d41-40cd-9ac2-f6a66ac366f3 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +rng_srate_value=5 +accelerate_cold_power_up_time=3 +accelerate_regulators_power_up_time=2 +sw_ build_device=sim_dv +sw_images=edn_boot_mode:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2032936015 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ =chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_edn_ boot_mode.2032936015 |
| Directory | /workspace/0.chip_sw_edn_boot_mode/latest |
| Test location | /workspace/coverage/default/0.chip_sw_otbn_ecdsa_op_irq.3105168592 |
| Short name | T156 |
| Test name | |
| Test status | |
| Simulation time | 17783851436 ps |
| CPU time | 3669.83 seconds |
| Started | Aug 13 07:10:51 PM PDT 24 |
| Finished | Aug 13 08:12:01 PM PDT 24 |
| Peak memory | 611040 kb |
| Host | smart-07f50613-7432-4e1f-a04d-93c5f0329664 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=28_000_000 +rng_srate_value=30 +sw_build_device=sim_dv +sw_images=otbn_ecdsa_op_irq_test:1:new_rules,test_ rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ random_seed=3105168592 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_otbn_ecdsa_op_irq.3105168592 |
| Directory | /workspace/0.chip_sw_otbn_ecdsa_op_irq/latest |
| Test location | /workspace/coverage/default/0.chip_sw_rv_core_ibex_lockstep_glitch.397823570 |
| Short name | T404 |
| Test name | |
| Test status | |
| Simulation time | 2119010412 ps |
| CPU time | 173.95 seconds |
| Started | Aug 13 07:11:33 PM PDT 24 |
| Finished | Aug 13 07:14:27 PM PDT 24 |
| Peak memory | 610832 kb |
| Host | smart-6c326f14-b301-4c54-8301-c30a2154b42c |
| User | root |
| Command | /workspace/default/simv +disable_assert_final_checks +sw_build_device=sim_dv +sw_images=aes_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=397823570 -assert n opostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rv_core_ibex_lockstep_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_rv_core_ibex_lockstep_glitch.397823570 |
| Directory | /workspace/0.chip_sw_rv_core_ibex_lockstep_glitch/latest |
| Test location | /workspace/coverage/default/0.chip_sw_sram_ctrl_execution_main.1091120518 |
| Short name | T96 |
| Test name | |
| Test status | |
| Simulation time | 7824281109 ps |
| CPU time | 690.93 seconds |
| Started | Aug 13 07:10:10 PM PDT 24 |
| Finished | Aug 13 07:21:41 PM PDT 24 |
| Peak memory | 611128 kb |
| Host | smart-58eb8831-c214-4d46-9cec-402a8cc91c87 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=sram_ctrl_execution_main_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1091120518 -assert nopostproc +U VM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sram_ctrl_execution_main_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co verage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_sram_ctrl_execution_main.1091120518 |
| Directory | /workspace/0.chip_sw_sram_ctrl_execution_main/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_bad_b_good_dev.2343161667 |
| Short name | T1360 |
| Test name | |
| Test status | |
| Simulation time | 24625211144 ps |
| CPU time | 5734.83 seconds |
| Started | Aug 13 07:17:39 PM PDT 24 |
| Finished | Aug 13 08:53:14 PM PDT 24 |
| Peak memory | 611476 kb |
| Host | smart-9d5bd5e7-b2d1-4fdd-9507-500c4a508001 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=100_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_corrupted:1: ot_flash_binary:signed:fake_ecdsa_prod_key_0,empty_test_slot_b_fake_ecdsa_prod_key_0:2:ot_flash_binary,otp_img_boot_policy_valid_dev:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random _seed=2343161667 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_boot_policy_valid_a_bad_b_good_dev.2343161667 |
| Directory | /workspace/0.rom_e2e_boot_policy_valid_a_bad_b_good_dev/latest |
| Test location | /workspace/coverage/cover_reg_top/0.chip_csr_bit_bash.4233226757 |
| Short name | T1749 |
| Test name | |
| Test status | |
| Simulation time | 8109251472 ps |
| CPU time | 897.03 seconds |
| Started | Aug 13 06:50:22 PM PDT 24 |
| Finished | Aug 13 07:05:19 PM PDT 24 |
| Peak memory | 592260 kb |
| Host | smart-2747a161-12e4-4227-a380-fe3130be4cbf |
| User | root |
| Command | /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +num_test_csrs=200 +csr_bit_bash +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4233226757 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to p.vdb -cm_log /dev/null -cm_name 0.chip_csr_bit_bash.4233226757 |
| Directory | /workspace/0.chip_csr_bit_bash/latest |
| Test location | /workspace/coverage/cover_reg_top/0.chip_csr_mem_rw_with_rand_reset.2409673756 |
| Short name | T2837 |
| Test name | |
| Test status | |
| Simulation time | 7311697480 ps |
| CPU time | 567.44 seconds |
| Started | Aug 13 06:50:32 PM PDT 24 |
| Finished | Aug 13 07:00:00 PM PDT 24 |
| Peak memory | 644100 kb |
| Host | smart-01b8c325-67d0-45ba-bc66-2c1c922526d8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2409673756 -assert nopostproc + UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top .vdb -cm_log /dev/null -cm_name 0.chip_csr_mem_rw_with_rand_reset.2409673756 |
| Directory | /workspace/0.chip_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/0.chip_csr_rw.3203490750 |
| Short name | T1993 |
| Test name | |
| Test status | |
| Simulation time | 5085607390 ps |
| CPU time | 415.58 seconds |
| Started | Aug 13 06:50:46 PM PDT 24 |
| Finished | Aug 13 06:57:42 PM PDT 24 |
| Peak memory | 598188 kb |
| Host | smart-22a94fb8-3557-44f5-82ad-e8bebeee55b5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3203490750 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.chip_csr_rw.3203490750 |
| Directory | /workspace/0.chip_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/0.chip_prim_tl_access.1116095001 |
| Short name | T2580 |
| Test name | |
| Test status | |
| Simulation time | 7213502920 ps |
| CPU time | 267.34 seconds |
| Started | Aug 13 06:50:23 PM PDT 24 |
| Finished | Aug 13 06:54:50 PM PDT 24 |
| Peak memory | 589988 kb |
| Host | smart-5e2f5512-b17b-4ea5-8f9b-14d01622617b |
| User | root |
| Command | /workspace/cover_reg_top/simv +en_scb=0 +en_scb_tl_err_chk=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1116095001 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SE Q=chip_prim_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.chip_prim_tl_access.1116095001 |
| Directory | /workspace/0.chip_prim_tl_access/latest |
| Test location | /workspace/coverage/cover_reg_top/0.chip_rv_dm_lc_disabled.769839571 |
| Short name | T2306 |
| Test name | |
| Test status | |
| Simulation time | 9730087256 ps |
| CPU time | 472.82 seconds |
| Started | Aug 13 06:50:19 PM PDT 24 |
| Finished | Aug 13 06:58:12 PM PDT 24 |
| Peak memory | 590948 kb |
| Host | smart-2f5841a9-f2c0-4b96-8cb6-ef8004f98f28 |
| User | root |
| Command | /workspace/cover_reg_top/simv +en_scb=0 +en_scb_tl_err_chk=0 +use_jtag_dmi=1 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=769839571 -assert nopostproc +UVM_TESTNAME=chip_base_te st +UVM_TEST_SEQ=chip_rv_dm_lc_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log / dev/null -cm_name 0.chip_rv_dm_lc_disabled.769839571 |
| Directory | /workspace/0.chip_rv_dm_lc_disabled/latest |
| Test location | /workspace/coverage/cover_reg_top/0.chip_same_csr_outstanding.1001694841 |
| Short name | T408 |
| Test name | |
| Test status | |
| Simulation time | 26709237198 ps |
| CPU time | 5138.37 seconds |
| Started | Aug 13 06:50:21 PM PDT 24 |
| Finished | Aug 13 08:16:00 PM PDT 24 |
| Peak memory | 592688 kb |
| Host | smart-c64c8418-5fa4-44a0-a6ac-8391bd6963bd |
| User | root |
| Command | /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +run_same_csr_outstanding +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1001694841 -assert nopostproc +UVM_TE STNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb - cm_log /dev/null -cm_name 0.chip_same_csr_outstanding.1001694841 |
| Directory | /workspace/0.chip_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/0.chip_tl_errors.1293680062 |
| Short name | T749 |
| Test name | |
| Test status | |
| Simulation time | 3333888711 ps |
| CPU time | 186.18 seconds |
| Started | Aug 13 06:50:26 PM PDT 24 |
| Finished | Aug 13 06:53:32 PM PDT 24 |
| Peak memory | 603400 kb |
| Host | smart-6789f370-2f6e-49f2-91bb-6af80473c85c |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1293680062 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.chip_tl_errors.1293680062 |
| Directory | /workspace/0.chip_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/0.xbar_access_same_device.892483384 |
| Short name | T2919 |
| Test name | |
| Test status | |
| Simulation time | 1897452061 ps |
| CPU time | 83.41 seconds |
| Started | Aug 13 06:50:48 PM PDT 24 |
| Finished | Aug 13 06:52:12 PM PDT 24 |
| Peak memory | 576396 kb |
| Host | smart-591f0d90-c65a-42a9-b5db-bceeee7ac600 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=892483384 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.xbar_access_same_device.892483384 |
| Directory | /workspace/0.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/0.xbar_access_same_device_slow_rsp.1933315122 |
| Short name | T2551 |
| Test name | |
| Test status | |
| Simulation time | 114287469095 ps |
| CPU time | 2031.28 seconds |
| Started | Aug 13 06:50:22 PM PDT 24 |
| Finished | Aug 13 07:24:14 PM PDT 24 |
| Peak memory | 575856 kb |
| Host | smart-9004af91-fd63-4370-92c7-62b93c6ffe8c |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1933315122 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.xbar_access_same_d evice_slow_rsp.1933315122 |
| Directory | /workspace/0.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/0.xbar_error_and_unmapped_addr.3922450780 |
| Short name | T2377 |
| Test name | |
| Test status | |
| Simulation time | 192478421 ps |
| CPU time | 21.27 seconds |
| Started | Aug 13 06:51:09 PM PDT 24 |
| Finished | Aug 13 06:51:31 PM PDT 24 |
| Peak memory | 575528 kb |
| Host | smart-7563a9ef-c60f-4c25-864b-95955c4aa50e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3922450780 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.xbar_error_and_unmapped_addr .3922450780 |
| Directory | /workspace/0.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/0.xbar_error_random.1739747342 |
| Short name | T2754 |
| Test name | |
| Test status | |
| Simulation time | 113211567 ps |
| CPU time | 6.37 seconds |
| Started | Aug 13 06:50:46 PM PDT 24 |
| Finished | Aug 13 06:50:53 PM PDT 24 |
| Peak memory | 573556 kb |
| Host | smart-668d8382-1963-4b1b-b043-ca2686434f48 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1739747342 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.xbar_error_random.1739747342 |
| Directory | /workspace/0.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/0.xbar_random.2342491546 |
| Short name | T2049 |
| Test name | |
| Test status | |
| Simulation time | 596716031 ps |
| CPU time | 44.15 seconds |
| Started | Aug 13 06:50:47 PM PDT 24 |
| Finished | Aug 13 06:51:36 PM PDT 24 |
| Peak memory | 575680 kb |
| Host | smart-c3d67984-573a-4199-9eec-2284c181fb63 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2342491546 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.xbar_random.2342491546 |
| Directory | /workspace/0.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/0.xbar_random_large_delays.355452384 |
| Short name | T1425 |
| Test name | |
| Test status | |
| Simulation time | 8816864392 ps |
| CPU time | 89.29 seconds |
| Started | Aug 13 06:50:23 PM PDT 24 |
| Finished | Aug 13 06:51:52 PM PDT 24 |
| Peak memory | 574328 kb |
| Host | smart-ea6f8ea5-ebd3-4dfc-a3aa-60927878db9a |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=355452384 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.xbar_random_large_delays.355452384 |
| Directory | /workspace/0.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/0.xbar_random_slow_rsp.3077870310 |
| Short name | T2162 |
| Test name | |
| Test status | |
| Simulation time | 53420212148 ps |
| CPU time | 856.98 seconds |
| Started | Aug 13 06:50:23 PM PDT 24 |
| Finished | Aug 13 07:04:40 PM PDT 24 |
| Peak memory | 575672 kb |
| Host | smart-0d676907-27de-4b63-8e14-0ef5b60f2193 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3077870310 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.xbar_random_slow_rsp.3077870310 |
| Directory | /workspace/0.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/0.xbar_random_zero_delays.3970602255 |
| Short name | T2221 |
| Test name | |
| Test status | |
| Simulation time | 132114701 ps |
| CPU time | 12.4 seconds |
| Started | Aug 13 06:50:25 PM PDT 24 |
| Finished | Aug 13 06:50:37 PM PDT 24 |
| Peak memory | 575628 kb |
| Host | smart-991d1b50-fc3f-4b96-a39d-b973132646ea |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3970602255 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.xbar_random_zero_dela ys.3970602255 |
| Directory | /workspace/0.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/0.xbar_same_source.1122494174 |
| Short name | T2213 |
| Test name | |
| Test status | |
| Simulation time | 434778819 ps |
| CPU time | 27.55 seconds |
| Started | Aug 13 06:50:37 PM PDT 24 |
| Finished | Aug 13 06:51:05 PM PDT 24 |
| Peak memory | 575404 kb |
| Host | smart-3f2c10d5-c236-47c0-b540-0d461cf733f4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1122494174 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.xbar_same_source.1122494174 |
| Directory | /workspace/0.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/0.xbar_smoke.1030831972 |
| Short name | T1441 |
| Test name | |
| Test status | |
| Simulation time | 44004702 ps |
| CPU time | 6.2 seconds |
| Started | Aug 13 06:50:22 PM PDT 24 |
| Finished | Aug 13 06:50:28 PM PDT 24 |
| Peak memory | 573576 kb |
| Host | smart-704d966f-8671-4981-b3bd-0e7b34f7415c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1030831972 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.xbar_smoke.1030831972 |
| Directory | /workspace/0.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/0.xbar_smoke_large_delays.4113793582 |
| Short name | T1607 |
| Test name | |
| Test status | |
| Simulation time | 7514663821 ps |
| CPU time | 74.56 seconds |
| Started | Aug 13 06:50:38 PM PDT 24 |
| Finished | Aug 13 06:51:52 PM PDT 24 |
| Peak memory | 574296 kb |
| Host | smart-5e09985b-2798-49d2-b33f-e43ca5afeb1f |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4113793582 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.xbar_smoke_large_delays.4113793582 |
| Directory | /workspace/0.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/0.xbar_smoke_slow_rsp.2865535869 |
| Short name | T2270 |
| Test name | |
| Test status | |
| Simulation time | 4669826471 ps |
| CPU time | 79.88 seconds |
| Started | Aug 13 06:50:33 PM PDT 24 |
| Finished | Aug 13 06:51:58 PM PDT 24 |
| Peak memory | 573692 kb |
| Host | smart-33065170-0c33-47d7-ad0f-1457b77821a3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2865535869 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.xbar_smoke_slow_rsp.2865535869 |
| Directory | /workspace/0.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/0.xbar_smoke_zero_delays.3309816687 |
| Short name | T1841 |
| Test name | |
| Test status | |
| Simulation time | 48558991 ps |
| CPU time | 6.29 seconds |
| Started | Aug 13 06:50:52 PM PDT 24 |
| Finished | Aug 13 06:50:58 PM PDT 24 |
| Peak memory | 573556 kb |
| Host | smart-1cfe4909-3a16-4108-9025-9febc1840efe |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3309816687 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.xbar_smoke_zero_delays .3309816687 |
| Directory | /workspace/0.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/0.xbar_stress_all_with_error.2440279476 |
| Short name | T2467 |
| Test name | |
| Test status | |
| Simulation time | 2512943797 ps |
| CPU time | 91.67 seconds |
| Started | Aug 13 06:50:42 PM PDT 24 |
| Finished | Aug 13 06:52:13 PM PDT 24 |
| Peak memory | 575556 kb |
| Host | smart-1d6fa608-46d9-4a6b-ab81-82217725da15 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2440279476 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.xbar_stress_all_with_error.2440279476 |
| Directory | /workspace/0.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/0.xbar_unmapped_addr.258565182 |
| Short name | T2512 |
| Test name | |
| Test status | |
| Simulation time | 227977090 ps |
| CPU time | 25.72 seconds |
| Started | Aug 13 06:51:02 PM PDT 24 |
| Finished | Aug 13 06:51:28 PM PDT 24 |
| Peak memory | 575724 kb |
| Host | smart-e8e8d84d-9b51-4d0a-98eb-17f64e673643 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=258565182 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.xbar_unmapped_addr.258565182 |
| Directory | /workspace/0.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/1.chip_csr_aliasing.3686890824 |
| Short name | T2432 |
| Test name | |
| Test status | |
| Simulation time | 50288485144 ps |
| CPU time | 8275.6 seconds |
| Started | Aug 13 06:50:26 PM PDT 24 |
| Finished | Aug 13 09:08:22 PM PDT 24 |
| Peak memory | 636128 kb |
| Host | smart-e69a3e92-5e8e-4f7b-a267-568372019e11 |
| User | root |
| Command | /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +csr_aliasing +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3686890824 -assert nopostproc +UVM_TESTNAME=chip_ base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/ null -cm_name 1.chip_csr_aliasing.3686890824 |
| Directory | /workspace/1.chip_csr_aliasing/latest |
| Test location | /workspace/coverage/cover_reg_top/1.chip_csr_bit_bash.2972624305 |
| Short name | T2288 |
| Test name | |
| Test status | |
| Simulation time | 46137889366 ps |
| CPU time | 5658.36 seconds |
| Started | Aug 13 06:50:47 PM PDT 24 |
| Finished | Aug 13 08:25:06 PM PDT 24 |
| Peak memory | 593240 kb |
| Host | smart-4b6ac30a-e2df-4692-b63c-a3c9be192681 |
| User | root |
| Command | /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +num_test_csrs=200 +csr_bit_bash +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2972624305 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to p.vdb -cm_log /dev/null -cm_name 1.chip_csr_bit_bash.2972624305 |
| Directory | /workspace/1.chip_csr_bit_bash/latest |
| Test location | /workspace/coverage/cover_reg_top/1.chip_csr_hw_reset.299211633 |
| Short name | T147 |
| Test name | |
| Test status | |
| Simulation time | 4881975437 ps |
| CPU time | 216.93 seconds |
| Started | Aug 13 06:50:58 PM PDT 24 |
| Finished | Aug 13 06:54:35 PM PDT 24 |
| Peak memory | 663264 kb |
| Host | smart-ca16c9aa-59e4-462f-b1d3-92f63636ce2f |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=299211633 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_c ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.chip_csr_hw_re set.299211633 |
| Directory | /workspace/1.chip_csr_hw_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/1.chip_csr_mem_rw_with_rand_reset.1933838091 |
| Short name | T2733 |
| Test name | |
| Test status | |
| Simulation time | 11175767984 ps |
| CPU time | 985.57 seconds |
| Started | Aug 13 06:50:53 PM PDT 24 |
| Finished | Aug 13 07:07:19 PM PDT 24 |
| Peak memory | 641328 kb |
| Host | smart-776c1b17-35dc-401e-961a-db40a8c0240e |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1933838091 -assert nopostproc + UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top .vdb -cm_log /dev/null -cm_name 1.chip_csr_mem_rw_with_rand_reset.1933838091 |
| Directory | /workspace/1.chip_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/1.chip_csr_rw.1368311047 |
| Short name | T1849 |
| Test name | |
| Test status | |
| Simulation time | 5413128880 ps |
| CPU time | 546.61 seconds |
| Started | Aug 13 06:50:34 PM PDT 24 |
| Finished | Aug 13 06:59:41 PM PDT 24 |
| Peak memory | 598204 kb |
| Host | smart-52400a05-6ffc-4d00-b402-f1420e9c1758 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1368311047 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.chip_csr_rw.1368311047 |
| Directory | /workspace/1.chip_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/1.chip_prim_tl_access.400483429 |
| Short name | T1928 |
| Test name | |
| Test status | |
| Simulation time | 4584020924 ps |
| CPU time | 169.33 seconds |
| Started | Aug 13 06:50:47 PM PDT 24 |
| Finished | Aug 13 06:53:37 PM PDT 24 |
| Peak memory | 591092 kb |
| Host | smart-7ee80238-3117-4053-94c2-a47dadc9b92b |
| User | root |
| Command | /workspace/cover_reg_top/simv +en_scb=0 +en_scb_tl_err_chk=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=400483429 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ =chip_prim_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1 .chip_prim_tl_access.400483429 |
| Directory | /workspace/1.chip_prim_tl_access/latest |
| Test location | /workspace/coverage/cover_reg_top/1.chip_rv_dm_lc_disabled.4241030324 |
| Short name | T2769 |
| Test name | |
| Test status | |
| Simulation time | 15369342369 ps |
| CPU time | 472.97 seconds |
| Started | Aug 13 06:50:40 PM PDT 24 |
| Finished | Aug 13 06:58:33 PM PDT 24 |
| Peak memory | 590960 kb |
| Host | smart-193c7b26-7418-4440-8575-6be4fdbc6916 |
| User | root |
| Command | /workspace/cover_reg_top/simv +en_scb=0 +en_scb_tl_err_chk=0 +use_jtag_dmi=1 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4241030324 -assert nopostproc +UVM_TESTNAME=chip_base_t est +UVM_TEST_SEQ=chip_rv_dm_lc_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.chip_rv_dm_lc_disabled.4241030324 |
| Directory | /workspace/1.chip_rv_dm_lc_disabled/latest |
| Test location | /workspace/coverage/cover_reg_top/1.chip_tl_errors.226600924 |
| Short name | T571 |
| Test name | |
| Test status | |
| Simulation time | 2952556692 ps |
| CPU time | 172.66 seconds |
| Started | Aug 13 06:50:47 PM PDT 24 |
| Finished | Aug 13 06:53:40 PM PDT 24 |
| Peak memory | 603308 kb |
| Host | smart-de8c28a1-88de-4836-80df-934ee3954a85 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=226600924 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.chip_tl_errors.226600924 |
| Directory | /workspace/1.chip_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/1.xbar_access_same_device.267516346 |
| Short name | T2175 |
| Test name | |
| Test status | |
| Simulation time | 610260595 ps |
| CPU time | 27.75 seconds |
| Started | Aug 13 06:50:23 PM PDT 24 |
| Finished | Aug 13 06:50:51 PM PDT 24 |
| Peak memory | 575652 kb |
| Host | smart-f4ba237f-5b7a-46a7-a93f-f5a59b76fba1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=267516346 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.xbar_access_same_device.267516346 |
| Directory | /workspace/1.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/1.xbar_access_same_device_slow_rsp.557956235 |
| Short name | T1981 |
| Test name | |
| Test status | |
| Simulation time | 143387698795 ps |
| CPU time | 2501 seconds |
| Started | Aug 13 06:50:32 PM PDT 24 |
| Finished | Aug 13 07:32:13 PM PDT 24 |
| Peak memory | 575764 kb |
| Host | smart-544c6844-ca5c-4e46-867e-63646eeb540e |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=557956235 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.xbar_access_same_de vice_slow_rsp.557956235 |
| Directory | /workspace/1.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/1.xbar_error_and_unmapped_addr.3270068221 |
| Short name | T1694 |
| Test name | |
| Test status | |
| Simulation time | 265327869 ps |
| CPU time | 25.4 seconds |
| Started | Aug 13 06:50:47 PM PDT 24 |
| Finished | Aug 13 06:51:12 PM PDT 24 |
| Peak memory | 575468 kb |
| Host | smart-30c14059-476a-4708-8263-a3fa459f1a1a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3270068221 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.xbar_error_and_unmapped_addr .3270068221 |
| Directory | /workspace/1.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/1.xbar_error_random.295520019 |
| Short name | T2429 |
| Test name | |
| Test status | |
| Simulation time | 226755484 ps |
| CPU time | 21.24 seconds |
| Started | Aug 13 06:50:42 PM PDT 24 |
| Finished | Aug 13 06:51:03 PM PDT 24 |
| Peak memory | 575420 kb |
| Host | smart-109a4563-0e63-4145-b88f-e996640568fc |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=295520019 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.xbar_error_random.295520019 |
| Directory | /workspace/1.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/1.xbar_random.2598855407 |
| Short name | T1926 |
| Test name | |
| Test status | |
| Simulation time | 943606309 ps |
| CPU time | 34.24 seconds |
| Started | Aug 13 06:50:49 PM PDT 24 |
| Finished | Aug 13 06:51:24 PM PDT 24 |
| Peak memory | 575536 kb |
| Host | smart-363eac93-c0ed-4dcf-bd71-df8526e3ac44 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2598855407 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.xbar_random.2598855407 |
| Directory | /workspace/1.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/1.xbar_random_large_delays.3629657654 |
| Short name | T2691 |
| Test name | |
| Test status | |
| Simulation time | 37346370815 ps |
| CPU time | 380.25 seconds |
| Started | Aug 13 06:50:41 PM PDT 24 |
| Finished | Aug 13 06:57:01 PM PDT 24 |
| Peak memory | 575600 kb |
| Host | smart-a496840d-2a05-4e2f-b255-65c9e321dfad |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3629657654 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.xbar_random_large_delays.3629657654 |
| Directory | /workspace/1.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/1.xbar_random_slow_rsp.3746982857 |
| Short name | T1822 |
| Test name | |
| Test status | |
| Simulation time | 23521391455 ps |
| CPU time | 393.31 seconds |
| Started | Aug 13 06:50:36 PM PDT 24 |
| Finished | Aug 13 06:57:09 PM PDT 24 |
| Peak memory | 575736 kb |
| Host | smart-c49a6f38-5ed4-4c0d-918d-c1afa6fc0c86 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3746982857 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.xbar_random_slow_rsp.3746982857 |
| Directory | /workspace/1.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/1.xbar_random_zero_delays.4228718263 |
| Short name | T2739 |
| Test name | |
| Test status | |
| Simulation time | 177475815 ps |
| CPU time | 14.87 seconds |
| Started | Aug 13 06:50:49 PM PDT 24 |
| Finished | Aug 13 06:51:04 PM PDT 24 |
| Peak memory | 575576 kb |
| Host | smart-e3067406-3a67-4683-a1b8-1ee50f60071b |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4228718263 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.xbar_random_zero_dela ys.4228718263 |
| Directory | /workspace/1.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/1.xbar_same_source.4223398549 |
| Short name | T634 |
| Test name | |
| Test status | |
| Simulation time | 2101927691 ps |
| CPU time | 61.1 seconds |
| Started | Aug 13 06:50:49 PM PDT 24 |
| Finished | Aug 13 06:51:50 PM PDT 24 |
| Peak memory | 575596 kb |
| Host | smart-3d2e64d0-0871-428d-8d06-1a1f731eec01 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4223398549 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.xbar_same_source.4223398549 |
| Directory | /workspace/1.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/1.xbar_smoke.3109011465 |
| Short name | T2109 |
| Test name | |
| Test status | |
| Simulation time | 39975735 ps |
| CPU time | 5.42 seconds |
| Started | Aug 13 06:50:41 PM PDT 24 |
| Finished | Aug 13 06:50:46 PM PDT 24 |
| Peak memory | 573592 kb |
| Host | smart-fb81b2ad-946a-40a1-9fb0-699dc9d2fb81 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3109011465 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.xbar_smoke.3109011465 |
| Directory | /workspace/1.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/1.xbar_smoke_large_delays.2795931674 |
| Short name | T2039 |
| Test name | |
| Test status | |
| Simulation time | 9109186263 ps |
| CPU time | 95.64 seconds |
| Started | Aug 13 06:50:36 PM PDT 24 |
| Finished | Aug 13 06:52:12 PM PDT 24 |
| Peak memory | 574332 kb |
| Host | smart-c1b45f17-01a8-45bb-9bf6-4c2180b34648 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2795931674 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.xbar_smoke_large_delays.2795931674 |
| Directory | /workspace/1.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/1.xbar_smoke_slow_rsp.3729761974 |
| Short name | T2016 |
| Test name | |
| Test status | |
| Simulation time | 5872972332 ps |
| CPU time | 97.48 seconds |
| Started | Aug 13 06:50:35 PM PDT 24 |
| Finished | Aug 13 06:52:13 PM PDT 24 |
| Peak memory | 573624 kb |
| Host | smart-712e824f-0669-4153-944c-2e66a7611dac |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3729761974 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.xbar_smoke_slow_rsp.3729761974 |
| Directory | /workspace/1.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/1.xbar_smoke_zero_delays.2491903659 |
| Short name | T1437 |
| Test name | |
| Test status | |
| Simulation time | 52421046 ps |
| CPU time | 6.02 seconds |
| Started | Aug 13 06:50:59 PM PDT 24 |
| Finished | Aug 13 06:51:06 PM PDT 24 |
| Peak memory | 573560 kb |
| Host | smart-54485414-49e7-4d69-a379-de65a60cbf46 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2491903659 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.xbar_smoke_zero_delays .2491903659 |
| Directory | /workspace/1.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/1.xbar_stress_all.2225969032 |
| Short name | T1985 |
| Test name | |
| Test status | |
| Simulation time | 1588637698 ps |
| CPU time | 57.5 seconds |
| Started | Aug 13 06:50:51 PM PDT 24 |
| Finished | Aug 13 06:51:48 PM PDT 24 |
| Peak memory | 575720 kb |
| Host | smart-313a65b7-3882-429f-b5ad-5d7367e64f7b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2225969032 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.xbar_stress_all.2225969032 |
| Directory | /workspace/1.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/1.xbar_stress_all_with_error.3915105270 |
| Short name | T2613 |
| Test name | |
| Test status | |
| Simulation time | 1755191471 ps |
| CPU time | 128.99 seconds |
| Started | Aug 13 06:50:58 PM PDT 24 |
| Finished | Aug 13 06:53:07 PM PDT 24 |
| Peak memory | 576332 kb |
| Host | smart-d0c02701-2b8a-40a7-b65d-fff5fa340072 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3915105270 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.xbar_stress_all_with_error.3915105270 |
| Directory | /workspace/1.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/1.xbar_stress_all_with_rand_reset.3728231098 |
| Short name | T2059 |
| Test name | |
| Test status | |
| Simulation time | 9952367689 ps |
| CPU time | 602.54 seconds |
| Started | Aug 13 06:50:36 PM PDT 24 |
| Finished | Aug 13 07:00:38 PM PDT 24 |
| Peak memory | 575700 kb |
| Host | smart-e71d3324-96cc-4537-b484-44582347ae1e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3728231098 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.xbar_stress_all_ with_rand_reset.3728231098 |
| Directory | /workspace/1.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/1.xbar_stress_all_with_reset_error.898929936 |
| Short name | T2835 |
| Test name | |
| Test status | |
| Simulation time | 412199721 ps |
| CPU time | 112.33 seconds |
| Started | Aug 13 06:50:41 PM PDT 24 |
| Finished | Aug 13 06:52:34 PM PDT 24 |
| Peak memory | 575676 kb |
| Host | smart-3a8eae8d-161b-4ba2-9ccf-d09f727e9eef |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=898929936 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.xbar_stress_all_ with_reset_error.898929936 |
| Directory | /workspace/1.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/1.xbar_unmapped_addr.2443665134 |
| Short name | T635 |
| Test name | |
| Test status | |
| Simulation time | 1100585122 ps |
| CPU time | 47.24 seconds |
| Started | Aug 13 06:51:04 PM PDT 24 |
| Finished | Aug 13 06:51:51 PM PDT 24 |
| Peak memory | 575744 kb |
| Host | smart-9a005cf4-6a56-4818-85c6-ab670b3936b5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2443665134 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.xbar_unmapped_addr.2443665134 |
| Directory | /workspace/1.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/10.chip_csr_mem_rw_with_rand_reset.711312735 |
| Short name | T543 |
| Test name | |
| Test status | |
| Simulation time | 10577889120 ps |
| CPU time | 814.77 seconds |
| Started | Aug 13 06:51:14 PM PDT 24 |
| Finished | Aug 13 07:04:50 PM PDT 24 |
| Peak memory | 652656 kb |
| Host | smart-1c34a7ac-f208-4b52-84c0-e5861e999410 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=711312735 -assert nopostproc +U VM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top. vdb -cm_log /dev/null -cm_name 10.chip_csr_mem_rw_with_rand_reset.711312735 |
| Directory | /workspace/10.chip_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/10.chip_same_csr_outstanding.2533274275 |
| Short name | T2553 |
| Test name | |
| Test status | |
| Simulation time | 27610649819 ps |
| CPU time | 4144.31 seconds |
| Started | Aug 13 06:51:10 PM PDT 24 |
| Finished | Aug 13 08:00:15 PM PDT 24 |
| Peak memory | 593268 kb |
| Host | smart-383b601b-b581-461c-a6dd-e410f173e7f7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +run_same_csr_outstanding +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2533274275 -assert nopostproc +UVM_TE STNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb - cm_log /dev/null -cm_name 10.chip_same_csr_outstanding.2533274275 |
| Directory | /workspace/10.chip_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/10.chip_tl_errors.463280477 |
| Short name | T754 |
| Test name | |
| Test status | |
| Simulation time | 2976579704 ps |
| CPU time | 208.97 seconds |
| Started | Aug 13 06:51:09 PM PDT 24 |
| Finished | Aug 13 06:54:38 PM PDT 24 |
| Peak memory | 603504 kb |
| Host | smart-76639f9d-7810-4308-9110-5bd31fe92a75 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=463280477 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.chip_tl_errors.463280477 |
| Directory | /workspace/10.chip_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/10.xbar_access_same_device.4218707591 |
| Short name | T1654 |
| Test name | |
| Test status | |
| Simulation time | 979272263 ps |
| CPU time | 38.85 seconds |
| Started | Aug 13 06:51:09 PM PDT 24 |
| Finished | Aug 13 06:51:48 PM PDT 24 |
| Peak memory | 575672 kb |
| Host | smart-3301b9bd-d8fb-4833-aed5-e742b8515e21 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4218707591 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.xbar_access_same_device .4218707591 |
| Directory | /workspace/10.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/10.xbar_access_same_device_slow_rsp.139963278 |
| Short name | T2729 |
| Test name | |
| Test status | |
| Simulation time | 56255535317 ps |
| CPU time | 927.53 seconds |
| Started | Aug 13 06:51:12 PM PDT 24 |
| Finished | Aug 13 07:06:39 PM PDT 24 |
| Peak memory | 575632 kb |
| Host | smart-e0dab93a-6451-46b6-b886-2f96561c62f0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=139963278 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.xbar_access_same_d evice_slow_rsp.139963278 |
| Directory | /workspace/10.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/10.xbar_error_and_unmapped_addr.3821043120 |
| Short name | T2417 |
| Test name | |
| Test status | |
| Simulation time | 348646714 ps |
| CPU time | 15.36 seconds |
| Started | Aug 13 06:51:00 PM PDT 24 |
| Finished | Aug 13 06:51:15 PM PDT 24 |
| Peak memory | 575636 kb |
| Host | smart-242ebb7f-c7fc-4c7b-a94f-d55e32c77ef9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3821043120 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.xbar_error_and_unmapped_add r.3821043120 |
| Directory | /workspace/10.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/10.xbar_error_random.3907977492 |
| Short name | T2138 |
| Test name | |
| Test status | |
| Simulation time | 368787411 ps |
| CPU time | 16.72 seconds |
| Started | Aug 13 06:51:11 PM PDT 24 |
| Finished | Aug 13 06:51:28 PM PDT 24 |
| Peak memory | 575488 kb |
| Host | smart-48da1390-3cfc-4ac0-9b3b-932235ef5997 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3907977492 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.xbar_error_random.3907977492 |
| Directory | /workspace/10.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/10.xbar_random.3198341048 |
| Short name | T1851 |
| Test name | |
| Test status | |
| Simulation time | 492666821 ps |
| CPU time | 40.86 seconds |
| Started | Aug 13 06:51:13 PM PDT 24 |
| Finished | Aug 13 06:51:54 PM PDT 24 |
| Peak memory | 575640 kb |
| Host | smart-c51ea191-83e5-488f-9940-85969131f5c6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3198341048 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.xbar_random.3198341048 |
| Directory | /workspace/10.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/10.xbar_random_large_delays.3446502325 |
| Short name | T1764 |
| Test name | |
| Test status | |
| Simulation time | 71261923369 ps |
| CPU time | 722.74 seconds |
| Started | Aug 13 06:51:03 PM PDT 24 |
| Finished | Aug 13 07:03:06 PM PDT 24 |
| Peak memory | 575628 kb |
| Host | smart-11a6a064-4407-4965-927d-df9deea8134b |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3446502325 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.xbar_random_large_delays.3446502325 |
| Directory | /workspace/10.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/10.xbar_random_slow_rsp.889611222 |
| Short name | T599 |
| Test name | |
| Test status | |
| Simulation time | 67533066865 ps |
| CPU time | 1092.52 seconds |
| Started | Aug 13 06:51:09 PM PDT 24 |
| Finished | Aug 13 07:09:22 PM PDT 24 |
| Peak memory | 575764 kb |
| Host | smart-d21ebf25-e924-4cad-aa10-79e60f73255e |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=889611222 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.xbar_random_slow_rsp.889611222 |
| Directory | /workspace/10.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/10.xbar_random_zero_delays.3170318122 |
| Short name | T1866 |
| Test name | |
| Test status | |
| Simulation time | 242639633 ps |
| CPU time | 22.96 seconds |
| Started | Aug 13 06:51:05 PM PDT 24 |
| Finished | Aug 13 06:51:28 PM PDT 24 |
| Peak memory | 575552 kb |
| Host | smart-1173f42b-92cc-47bd-abbf-7a32176c16f7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3170318122 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.xbar_random_zero_del ays.3170318122 |
| Directory | /workspace/10.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/10.xbar_same_source.3608608963 |
| Short name | T1713 |
| Test name | |
| Test status | |
| Simulation time | 497333489 ps |
| CPU time | 34.61 seconds |
| Started | Aug 13 06:50:54 PM PDT 24 |
| Finished | Aug 13 06:51:29 PM PDT 24 |
| Peak memory | 575628 kb |
| Host | smart-6348e2a7-a239-4f84-8959-a7bd5b2c46e7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3608608963 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.xbar_same_source.3608608963 |
| Directory | /workspace/10.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/10.xbar_smoke.2992800251 |
| Short name | T1528 |
| Test name | |
| Test status | |
| Simulation time | 54742857 ps |
| CPU time | 6.72 seconds |
| Started | Aug 13 06:51:02 PM PDT 24 |
| Finished | Aug 13 06:51:09 PM PDT 24 |
| Peak memory | 574224 kb |
| Host | smart-e1dacc4f-fbca-4a24-b920-4e4d25f6fa52 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2992800251 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.xbar_smoke.2992800251 |
| Directory | /workspace/10.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/10.xbar_smoke_large_delays.2541649858 |
| Short name | T2622 |
| Test name | |
| Test status | |
| Simulation time | 6818418741 ps |
| CPU time | 68 seconds |
| Started | Aug 13 06:51:13 PM PDT 24 |
| Finished | Aug 13 06:52:22 PM PDT 24 |
| Peak memory | 574320 kb |
| Host | smart-fa0d85b6-1129-42f6-9ab6-5030f9629a5d |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2541649858 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.xbar_smoke_large_delays.2541649858 |
| Directory | /workspace/10.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/10.xbar_smoke_slow_rsp.3915432031 |
| Short name | T2540 |
| Test name | |
| Test status | |
| Simulation time | 4317532138 ps |
| CPU time | 74.07 seconds |
| Started | Aug 13 06:51:04 PM PDT 24 |
| Finished | Aug 13 06:52:19 PM PDT 24 |
| Peak memory | 573608 kb |
| Host | smart-bee04671-3adb-4bca-9435-f9fbfd11a87a |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3915432031 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.xbar_smoke_slow_rsp.3915432031 |
| Directory | /workspace/10.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/10.xbar_smoke_zero_delays.1147009487 |
| Short name | T2060 |
| Test name | |
| Test status | |
| Simulation time | 43764353 ps |
| CPU time | 6.23 seconds |
| Started | Aug 13 06:51:04 PM PDT 24 |
| Finished | Aug 13 06:51:11 PM PDT 24 |
| Peak memory | 573500 kb |
| Host | smart-b7f06f2d-87dc-4984-b2dd-1b205c5f04d2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1147009487 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.xbar_smoke_zero_delay s.1147009487 |
| Directory | /workspace/10.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/10.xbar_stress_all.2621054651 |
| Short name | T2268 |
| Test name | |
| Test status | |
| Simulation time | 10320345390 ps |
| CPU time | 354.19 seconds |
| Started | Aug 13 06:51:11 PM PDT 24 |
| Finished | Aug 13 06:57:05 PM PDT 24 |
| Peak memory | 576548 kb |
| Host | smart-f55c950e-4596-44e7-99f8-e894153f39e1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2621054651 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.xbar_stress_all.2621054651 |
| Directory | /workspace/10.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/10.xbar_stress_all_with_error.4125317045 |
| Short name | T2170 |
| Test name | |
| Test status | |
| Simulation time | 7954777431 ps |
| CPU time | 290.2 seconds |
| Started | Aug 13 06:51:12 PM PDT 24 |
| Finished | Aug 13 06:56:02 PM PDT 24 |
| Peak memory | 575704 kb |
| Host | smart-ef0c0f5c-74f9-41bc-b932-cd7b82adcfb2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4125317045 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.xbar_stress_all_with_error.4125317045 |
| Directory | /workspace/10.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/10.xbar_stress_all_with_rand_reset.3537424873 |
| Short name | T602 |
| Test name | |
| Test status | |
| Simulation time | 6171353673 ps |
| CPU time | 411.15 seconds |
| Started | Aug 13 06:51:22 PM PDT 24 |
| Finished | Aug 13 06:58:13 PM PDT 24 |
| Peak memory | 575744 kb |
| Host | smart-f5ad3244-070e-49e4-84b0-26aea9b6c81c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3537424873 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.xbar_stress_all _with_rand_reset.3537424873 |
| Directory | /workspace/10.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/10.xbar_stress_all_with_reset_error.257655110 |
| Short name | T2311 |
| Test name | |
| Test status | |
| Simulation time | 4788210773 ps |
| CPU time | 219.55 seconds |
| Started | Aug 13 06:51:02 PM PDT 24 |
| Finished | Aug 13 06:54:42 PM PDT 24 |
| Peak memory | 576548 kb |
| Host | smart-8357a1a5-1ed5-47ec-ab99-24aa88ee2f1d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=257655110 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.xbar_stress_all _with_reset_error.257655110 |
| Directory | /workspace/10.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/10.xbar_unmapped_addr.953845364 |
| Short name | T2277 |
| Test name | |
| Test status | |
| Simulation time | 976540127 ps |
| CPU time | 45.72 seconds |
| Started | Aug 13 06:51:14 PM PDT 24 |
| Finished | Aug 13 06:52:00 PM PDT 24 |
| Peak memory | 575688 kb |
| Host | smart-4dd1be1b-b50f-4a4e-abc3-337cf0181415 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=953845364 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.xbar_unmapped_addr.953845364 |
| Directory | /workspace/10.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/11.chip_csr_mem_rw_with_rand_reset.2573626819 |
| Short name | T468 |
| Test name | |
| Test status | |
| Simulation time | 5336701946 ps |
| CPU time | 379.76 seconds |
| Started | Aug 13 06:51:15 PM PDT 24 |
| Finished | Aug 13 06:57:35 PM PDT 24 |
| Peak memory | 638264 kb |
| Host | smart-86e82fab-b8e1-4467-a980-78a56ab9a165 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2573626819 -assert nopostproc + UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top .vdb -cm_log /dev/null -cm_name 11.chip_csr_mem_rw_with_rand_reset.2573626819 |
| Directory | /workspace/11.chip_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/11.chip_csr_rw.526375919 |
| Short name | T390 |
| Test name | |
| Test status | |
| Simulation time | 5946188398 ps |
| CPU time | 443.22 seconds |
| Started | Aug 13 06:51:16 PM PDT 24 |
| Finished | Aug 13 06:58:39 PM PDT 24 |
| Peak memory | 598444 kb |
| Host | smart-bb29a96e-11d2-46c0-802f-21d9eb3492dc |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=526375919 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.chip_csr_rw.526375919 |
| Directory | /workspace/11.chip_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/11.chip_same_csr_outstanding.2348910464 |
| Short name | T2669 |
| Test name | |
| Test status | |
| Simulation time | 28448745537 ps |
| CPU time | 3375.51 seconds |
| Started | Aug 13 06:51:04 PM PDT 24 |
| Finished | Aug 13 07:47:20 PM PDT 24 |
| Peak memory | 593072 kb |
| Host | smart-2b252a3e-2c77-4924-be46-47a2eb8a915a |
| User | root |
| Command | /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +run_same_csr_outstanding +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2348910464 -assert nopostproc +UVM_TE STNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb - cm_log /dev/null -cm_name 11.chip_same_csr_outstanding.2348910464 |
| Directory | /workspace/11.chip_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/11.chip_tl_errors.2783221295 |
| Short name | T568 |
| Test name | |
| Test status | |
| Simulation time | 2968028774 ps |
| CPU time | 135.23 seconds |
| Started | Aug 13 06:51:18 PM PDT 24 |
| Finished | Aug 13 06:53:33 PM PDT 24 |
| Peak memory | 598396 kb |
| Host | smart-0aeb0b59-a27e-4317-8e45-87426ef7e29f |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2783221295 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.chip_tl_errors.2783221295 |
| Directory | /workspace/11.chip_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/11.xbar_access_same_device.2207896749 |
| Short name | T2600 |
| Test name | |
| Test status | |
| Simulation time | 898441261 ps |
| CPU time | 65.83 seconds |
| Started | Aug 13 06:51:14 PM PDT 24 |
| Finished | Aug 13 06:52:20 PM PDT 24 |
| Peak memory | 575588 kb |
| Host | smart-2e715b90-07be-49e4-95df-bc447fc08ad4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2207896749 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.xbar_access_same_device .2207896749 |
| Directory | /workspace/11.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/11.xbar_access_same_device_slow_rsp.1871040288 |
| Short name | T900 |
| Test name | |
| Test status | |
| Simulation time | 3799982372 ps |
| CPU time | 59.54 seconds |
| Started | Aug 13 06:51:15 PM PDT 24 |
| Finished | Aug 13 06:52:15 PM PDT 24 |
| Peak memory | 573648 kb |
| Host | smart-f9739bf7-0e8e-4543-9763-6afef4e244d4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1871040288 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.xbar_access_same_ device_slow_rsp.1871040288 |
| Directory | /workspace/11.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/11.xbar_error_and_unmapped_addr.2640403345 |
| Short name | T1803 |
| Test name | |
| Test status | |
| Simulation time | 1153077320 ps |
| CPU time | 48.41 seconds |
| Started | Aug 13 06:51:12 PM PDT 24 |
| Finished | Aug 13 06:52:01 PM PDT 24 |
| Peak memory | 575512 kb |
| Host | smart-c30bc3c8-01e1-40be-8b5d-fd4b9ad9d0e2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2640403345 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.xbar_error_and_unmapped_add r.2640403345 |
| Directory | /workspace/11.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/11.xbar_error_random.1834966091 |
| Short name | T1690 |
| Test name | |
| Test status | |
| Simulation time | 2345250943 ps |
| CPU time | 73.43 seconds |
| Started | Aug 13 06:51:16 PM PDT 24 |
| Finished | Aug 13 06:52:30 PM PDT 24 |
| Peak memory | 575772 kb |
| Host | smart-7eea32e0-75ee-4f36-b10a-b418cb6b4253 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1834966091 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.xbar_error_random.1834966091 |
| Directory | /workspace/11.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/11.xbar_random.2728464966 |
| Short name | T2088 |
| Test name | |
| Test status | |
| Simulation time | 631014589 ps |
| CPU time | 50.87 seconds |
| Started | Aug 13 06:51:13 PM PDT 24 |
| Finished | Aug 13 06:52:04 PM PDT 24 |
| Peak memory | 575688 kb |
| Host | smart-6991240d-946b-4863-8418-bf02194bf44d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2728464966 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.xbar_random.2728464966 |
| Directory | /workspace/11.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/11.xbar_random_large_delays.1868288344 |
| Short name | T1911 |
| Test name | |
| Test status | |
| Simulation time | 93569985691 ps |
| CPU time | 987.89 seconds |
| Started | Aug 13 06:51:07 PM PDT 24 |
| Finished | Aug 13 07:07:36 PM PDT 24 |
| Peak memory | 575824 kb |
| Host | smart-fe5c6b63-e6b9-477d-97e4-6ead7cf0ad8f |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1868288344 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.xbar_random_large_delays.1868288344 |
| Directory | /workspace/11.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/11.xbar_random_slow_rsp.980040505 |
| Short name | T2721 |
| Test name | |
| Test status | |
| Simulation time | 27226064205 ps |
| CPU time | 460.58 seconds |
| Started | Aug 13 06:51:16 PM PDT 24 |
| Finished | Aug 13 06:58:57 PM PDT 24 |
| Peak memory | 575744 kb |
| Host | smart-49813e78-885f-4796-8530-5ff0b940e2e9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=980040505 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.xbar_random_slow_rsp.980040505 |
| Directory | /workspace/11.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/11.xbar_random_zero_delays.2702106105 |
| Short name | T2694 |
| Test name | |
| Test status | |
| Simulation time | 598103416 ps |
| CPU time | 53.98 seconds |
| Started | Aug 13 06:51:16 PM PDT 24 |
| Finished | Aug 13 06:52:11 PM PDT 24 |
| Peak memory | 575612 kb |
| Host | smart-98d41a87-f439-4aed-9e96-c021c81d1db2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2702106105 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.xbar_random_zero_del ays.2702106105 |
| Directory | /workspace/11.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/11.xbar_same_source.2636576119 |
| Short name | T536 |
| Test name | |
| Test status | |
| Simulation time | 2582706829 ps |
| CPU time | 73.94 seconds |
| Started | Aug 13 06:51:11 PM PDT 24 |
| Finished | Aug 13 06:52:25 PM PDT 24 |
| Peak memory | 575540 kb |
| Host | smart-6eeb6444-d2a4-4d9c-aa6e-245d7b637a87 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2636576119 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.xbar_same_source.2636576119 |
| Directory | /workspace/11.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/11.xbar_smoke.3921711285 |
| Short name | T2765 |
| Test name | |
| Test status | |
| Simulation time | 203037083 ps |
| CPU time | 8.59 seconds |
| Started | Aug 13 06:51:13 PM PDT 24 |
| Finished | Aug 13 06:51:22 PM PDT 24 |
| Peak memory | 573592 kb |
| Host | smart-0e752bdc-f0c7-4937-b605-0026439a2891 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3921711285 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.xbar_smoke.3921711285 |
| Directory | /workspace/11.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/11.xbar_smoke_large_delays.2900157360 |
| Short name | T696 |
| Test name | |
| Test status | |
| Simulation time | 6353867477 ps |
| CPU time | 64.89 seconds |
| Started | Aug 13 06:51:19 PM PDT 24 |
| Finished | Aug 13 06:52:23 PM PDT 24 |
| Peak memory | 573660 kb |
| Host | smart-d039d4e6-ee63-4430-940b-9edada71b4be |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2900157360 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.xbar_smoke_large_delays.2900157360 |
| Directory | /workspace/11.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/11.xbar_smoke_slow_rsp.738717285 |
| Short name | T2688 |
| Test name | |
| Test status | |
| Simulation time | 5831682512 ps |
| CPU time | 98.39 seconds |
| Started | Aug 13 06:51:19 PM PDT 24 |
| Finished | Aug 13 06:52:58 PM PDT 24 |
| Peak memory | 573604 kb |
| Host | smart-ea3a0a7e-a032-4e44-992b-1a055bf17ba6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=738717285 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.xbar_smoke_slow_rsp.738717285 |
| Directory | /workspace/11.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/11.xbar_smoke_zero_delays.3563028662 |
| Short name | T2713 |
| Test name | |
| Test status | |
| Simulation time | 39063292 ps |
| CPU time | 5.84 seconds |
| Started | Aug 13 06:51:16 PM PDT 24 |
| Finished | Aug 13 06:51:22 PM PDT 24 |
| Peak memory | 573532 kb |
| Host | smart-13ece8b7-1409-44ed-a792-6cee6dc7661e |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3563028662 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.xbar_smoke_zero_delay s.3563028662 |
| Directory | /workspace/11.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/11.xbar_stress_all.1866306842 |
| Short name | T2934 |
| Test name | |
| Test status | |
| Simulation time | 4993692851 ps |
| CPU time | 374.19 seconds |
| Started | Aug 13 06:51:11 PM PDT 24 |
| Finished | Aug 13 06:57:25 PM PDT 24 |
| Peak memory | 576536 kb |
| Host | smart-ed552e46-2421-4edb-a503-41547de78b35 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1866306842 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.xbar_stress_all.1866306842 |
| Directory | /workspace/11.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/11.xbar_stress_all_with_error.3662674451 |
| Short name | T1961 |
| Test name | |
| Test status | |
| Simulation time | 15119781759 ps |
| CPU time | 545.25 seconds |
| Started | Aug 13 06:51:15 PM PDT 24 |
| Finished | Aug 13 07:00:21 PM PDT 24 |
| Peak memory | 575728 kb |
| Host | smart-17ab45d3-0a42-4129-856b-4c40994798dc |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3662674451 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.xbar_stress_all_with_error.3662674451 |
| Directory | /workspace/11.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/11.xbar_stress_all_with_rand_reset.2990444857 |
| Short name | T1895 |
| Test name | |
| Test status | |
| Simulation time | 3958709999 ps |
| CPU time | 296.28 seconds |
| Started | Aug 13 06:51:15 PM PDT 24 |
| Finished | Aug 13 06:56:12 PM PDT 24 |
| Peak memory | 576628 kb |
| Host | smart-2ce46761-f9b5-439a-9c36-f3949908dfd3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2990444857 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.xbar_stress_all _with_rand_reset.2990444857 |
| Directory | /workspace/11.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/11.xbar_stress_all_with_reset_error.1854690807 |
| Short name | T1658 |
| Test name | |
| Test status | |
| Simulation time | 111410389 ps |
| CPU time | 52.19 seconds |
| Started | Aug 13 06:51:13 PM PDT 24 |
| Finished | Aug 13 06:52:05 PM PDT 24 |
| Peak memory | 576484 kb |
| Host | smart-6f795970-a1b6-4a2f-ad86-68a9738d3f33 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1854690807 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.xbar_stress_al l_with_reset_error.1854690807 |
| Directory | /workspace/11.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/11.xbar_unmapped_addr.611328322 |
| Short name | T2041 |
| Test name | |
| Test status | |
| Simulation time | 1097125207 ps |
| CPU time | 44.97 seconds |
| Started | Aug 13 06:51:16 PM PDT 24 |
| Finished | Aug 13 06:52:01 PM PDT 24 |
| Peak memory | 575608 kb |
| Host | smart-792b7192-26fc-40b9-aa0e-b718953911b8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=611328322 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.xbar_unmapped_addr.611328322 |
| Directory | /workspace/11.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/12.chip_csr_mem_rw_with_rand_reset.1553413012 |
| Short name | T1661 |
| Test name | |
| Test status | |
| Simulation time | 9285633282 ps |
| CPU time | 687.59 seconds |
| Started | Aug 13 06:51:11 PM PDT 24 |
| Finished | Aug 13 07:02:39 PM PDT 24 |
| Peak memory | 652652 kb |
| Host | smart-60f34561-c2dd-45df-9f21-4b973a9a39bc |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1553413012 -assert nopostproc + UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top .vdb -cm_log /dev/null -cm_name 12.chip_csr_mem_rw_with_rand_reset.1553413012 |
| Directory | /workspace/12.chip_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/12.chip_csr_rw.1839726859 |
| Short name | T2811 |
| Test name | |
| Test status | |
| Simulation time | 5811030400 ps |
| CPU time | 511.41 seconds |
| Started | Aug 13 06:51:15 PM PDT 24 |
| Finished | Aug 13 06:59:47 PM PDT 24 |
| Peak memory | 598472 kb |
| Host | smart-0bbb8882-7ead-41a0-9f2b-216017a9d41f |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1839726859 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.chip_csr_rw.1839726859 |
| Directory | /workspace/12.chip_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/12.chip_same_csr_outstanding.2286144054 |
| Short name | T2895 |
| Test name | |
| Test status | |
| Simulation time | 27506067650 ps |
| CPU time | 4468.21 seconds |
| Started | Aug 13 06:51:16 PM PDT 24 |
| Finished | Aug 13 08:05:45 PM PDT 24 |
| Peak memory | 592984 kb |
| Host | smart-e8575f28-bf58-4c75-ad25-e682e690f613 |
| User | root |
| Command | /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +run_same_csr_outstanding +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2286144054 -assert nopostproc +UVM_TE STNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb - cm_log /dev/null -cm_name 12.chip_same_csr_outstanding.2286144054 |
| Directory | /workspace/12.chip_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/12.xbar_access_same_device.2933565874 |
| Short name | T1571 |
| Test name | |
| Test status | |
| Simulation time | 2503763813 ps |
| CPU time | 129.55 seconds |
| Started | Aug 13 06:51:14 PM PDT 24 |
| Finished | Aug 13 06:53:24 PM PDT 24 |
| Peak memory | 575624 kb |
| Host | smart-5b53495b-e109-4187-8362-cd46b3f59388 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2933565874 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.xbar_access_same_device .2933565874 |
| Directory | /workspace/12.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/12.xbar_access_same_device_slow_rsp.2458142926 |
| Short name | T2223 |
| Test name | |
| Test status | |
| Simulation time | 69414313511 ps |
| CPU time | 1207.78 seconds |
| Started | Aug 13 06:51:17 PM PDT 24 |
| Finished | Aug 13 07:11:25 PM PDT 24 |
| Peak memory | 575760 kb |
| Host | smart-8c94b38b-f2e9-40b0-b0d1-536489ac24c2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2458142926 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.xbar_access_same_ device_slow_rsp.2458142926 |
| Directory | /workspace/12.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/12.xbar_error_and_unmapped_addr.1979950748 |
| Short name | T1664 |
| Test name | |
| Test status | |
| Simulation time | 689263876 ps |
| CPU time | 30.56 seconds |
| Started | Aug 13 06:51:34 PM PDT 24 |
| Finished | Aug 13 06:52:05 PM PDT 24 |
| Peak memory | 575680 kb |
| Host | smart-025d22ea-9749-4758-aef0-98b4cff7dbae |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1979950748 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.xbar_error_and_unmapped_add r.1979950748 |
| Directory | /workspace/12.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/12.xbar_error_random.2548275726 |
| Short name | T2544 |
| Test name | |
| Test status | |
| Simulation time | 1972829184 ps |
| CPU time | 59.56 seconds |
| Started | Aug 13 06:51:11 PM PDT 24 |
| Finished | Aug 13 06:52:11 PM PDT 24 |
| Peak memory | 575732 kb |
| Host | smart-74cdb07f-4fd9-4ecd-b569-f23d2cce898c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2548275726 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.xbar_error_random.2548275726 |
| Directory | /workspace/12.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/12.xbar_random.1741566128 |
| Short name | T2731 |
| Test name | |
| Test status | |
| Simulation time | 449395362 ps |
| CPU time | 36.88 seconds |
| Started | Aug 13 06:51:11 PM PDT 24 |
| Finished | Aug 13 06:51:48 PM PDT 24 |
| Peak memory | 575544 kb |
| Host | smart-d95a6a03-c3a5-4937-b904-aa57c0d890c5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1741566128 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.xbar_random.1741566128 |
| Directory | /workspace/12.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/12.xbar_random_large_delays.1232930906 |
| Short name | T2874 |
| Test name | |
| Test status | |
| Simulation time | 34579600463 ps |
| CPU time | 321.59 seconds |
| Started | Aug 13 06:51:04 PM PDT 24 |
| Finished | Aug 13 06:56:26 PM PDT 24 |
| Peak memory | 575784 kb |
| Host | smart-ff287c0e-b0b5-445a-a2c8-f13d21fff909 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1232930906 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.xbar_random_large_delays.1232930906 |
| Directory | /workspace/12.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/12.xbar_random_slow_rsp.2520573943 |
| Short name | T1939 |
| Test name | |
| Test status | |
| Simulation time | 65795791098 ps |
| CPU time | 1119.41 seconds |
| Started | Aug 13 06:51:18 PM PDT 24 |
| Finished | Aug 13 07:09:58 PM PDT 24 |
| Peak memory | 575792 kb |
| Host | smart-3a25bb7f-6122-45b7-bce6-c4704559c761 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2520573943 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.xbar_random_slow_rsp.2520573943 |
| Directory | /workspace/12.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/12.xbar_random_zero_delays.573118599 |
| Short name | T590 |
| Test name | |
| Test status | |
| Simulation time | 93659985 ps |
| CPU time | 11.52 seconds |
| Started | Aug 13 06:51:12 PM PDT 24 |
| Finished | Aug 13 06:51:24 PM PDT 24 |
| Peak memory | 575596 kb |
| Host | smart-83e59f71-774c-4bcb-af1b-5a8d58b203f6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=573118599 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.xbar_random_zero_dela ys.573118599 |
| Directory | /workspace/12.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/12.xbar_same_source.4150938293 |
| Short name | T533 |
| Test name | |
| Test status | |
| Simulation time | 2043742265 ps |
| CPU time | 58.36 seconds |
| Started | Aug 13 06:51:16 PM PDT 24 |
| Finished | Aug 13 06:52:15 PM PDT 24 |
| Peak memory | 575592 kb |
| Host | smart-ddbc2dbe-73fc-4015-ae34-6b3be05b2f4f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4150938293 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.xbar_same_source.4150938293 |
| Directory | /workspace/12.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/12.xbar_smoke.847017678 |
| Short name | T1493 |
| Test name | |
| Test status | |
| Simulation time | 153629024 ps |
| CPU time | 7.8 seconds |
| Started | Aug 13 06:51:15 PM PDT 24 |
| Finished | Aug 13 06:51:24 PM PDT 24 |
| Peak memory | 573596 kb |
| Host | smart-8f251b66-1d04-4ebc-b34d-8edaa00a78fd |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=847017678 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.xbar_smoke.847017678 |
| Directory | /workspace/12.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/12.xbar_smoke_large_delays.3176134690 |
| Short name | T2449 |
| Test name | |
| Test status | |
| Simulation time | 5314029772 ps |
| CPU time | 60.13 seconds |
| Started | Aug 13 06:51:15 PM PDT 24 |
| Finished | Aug 13 06:52:15 PM PDT 24 |
| Peak memory | 574308 kb |
| Host | smart-4e070654-23d5-4244-8010-76c757da9621 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3176134690 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.xbar_smoke_large_delays.3176134690 |
| Directory | /workspace/12.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/12.xbar_smoke_slow_rsp.1006033423 |
| Short name | T1473 |
| Test name | |
| Test status | |
| Simulation time | 4535380713 ps |
| CPU time | 77.39 seconds |
| Started | Aug 13 06:51:18 PM PDT 24 |
| Finished | Aug 13 06:52:35 PM PDT 24 |
| Peak memory | 574344 kb |
| Host | smart-b79efa13-dbd7-496d-b9a0-292515fe8563 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1006033423 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.xbar_smoke_slow_rsp.1006033423 |
| Directory | /workspace/12.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/12.xbar_smoke_zero_delays.3508175734 |
| Short name | T1684 |
| Test name | |
| Test status | |
| Simulation time | 43857102 ps |
| CPU time | 6.17 seconds |
| Started | Aug 13 06:51:21 PM PDT 24 |
| Finished | Aug 13 06:51:27 PM PDT 24 |
| Peak memory | 573508 kb |
| Host | smart-01f035d8-878c-4305-a57c-0146c236cf70 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3508175734 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.xbar_smoke_zero_delay s.3508175734 |
| Directory | /workspace/12.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/12.xbar_stress_all.1202540522 |
| Short name | T483 |
| Test name | |
| Test status | |
| Simulation time | 8039605679 ps |
| CPU time | 277.66 seconds |
| Started | Aug 13 06:51:12 PM PDT 24 |
| Finished | Aug 13 06:55:50 PM PDT 24 |
| Peak memory | 575632 kb |
| Host | smart-8e0fadff-b7d1-490c-a630-47736540cc40 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1202540522 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.xbar_stress_all.1202540522 |
| Directory | /workspace/12.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/12.xbar_stress_all_with_error.304771641 |
| Short name | T2841 |
| Test name | |
| Test status | |
| Simulation time | 10483195945 ps |
| CPU time | 373.61 seconds |
| Started | Aug 13 06:51:16 PM PDT 24 |
| Finished | Aug 13 06:57:30 PM PDT 24 |
| Peak memory | 575712 kb |
| Host | smart-93781364-48a4-4bbf-8a22-79e7ceb41621 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=304771641 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.xbar_stress_all_with_error.304771641 |
| Directory | /workspace/12.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/12.xbar_stress_all_with_rand_reset.2131694868 |
| Short name | T927 |
| Test name | |
| Test status | |
| Simulation time | 651833526 ps |
| CPU time | 283.33 seconds |
| Started | Aug 13 06:51:10 PM PDT 24 |
| Finished | Aug 13 06:55:54 PM PDT 24 |
| Peak memory | 575656 kb |
| Host | smart-8579e1f2-34ed-405b-ae84-c19efde9f477 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2131694868 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.xbar_stress_all _with_rand_reset.2131694868 |
| Directory | /workspace/12.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/12.xbar_stress_all_with_reset_error.3540440706 |
| Short name | T1976 |
| Test name | |
| Test status | |
| Simulation time | 1206804201 ps |
| CPU time | 217.13 seconds |
| Started | Aug 13 06:51:23 PM PDT 24 |
| Finished | Aug 13 06:55:01 PM PDT 24 |
| Peak memory | 576472 kb |
| Host | smart-08935084-408b-427b-b1fc-f8ad39967851 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3540440706 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.xbar_stress_al l_with_reset_error.3540440706 |
| Directory | /workspace/12.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/12.xbar_unmapped_addr.1959089201 |
| Short name | T1765 |
| Test name | |
| Test status | |
| Simulation time | 121831548 ps |
| CPU time | 8.37 seconds |
| Started | Aug 13 06:51:15 PM PDT 24 |
| Finished | Aug 13 06:51:24 PM PDT 24 |
| Peak memory | 573608 kb |
| Host | smart-80e2bf9c-2ff0-482a-941f-41e5184f95c3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1959089201 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.xbar_unmapped_addr.1959089201 |
| Directory | /workspace/12.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/13.chip_csr_mem_rw_with_rand_reset.2161259327 |
| Short name | T426 |
| Test name | |
| Test status | |
| Simulation time | 6642951549 ps |
| CPU time | 453.28 seconds |
| Started | Aug 13 06:51:15 PM PDT 24 |
| Finished | Aug 13 06:58:49 PM PDT 24 |
| Peak memory | 637328 kb |
| Host | smart-a9b3e0da-5f40-44fb-92eb-2e1fb67a6819 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2161259327 -assert nopostproc + UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top .vdb -cm_log /dev/null -cm_name 13.chip_csr_mem_rw_with_rand_reset.2161259327 |
| Directory | /workspace/13.chip_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/13.chip_csr_rw.2245259403 |
| Short name | T729 |
| Test name | |
| Test status | |
| Simulation time | 5128061882 ps |
| CPU time | 441.94 seconds |
| Started | Aug 13 06:51:12 PM PDT 24 |
| Finished | Aug 13 06:58:34 PM PDT 24 |
| Peak memory | 597424 kb |
| Host | smart-d0d0f9ee-8c8e-4bbe-a5b4-bf2ecccec6f6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2245259403 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.chip_csr_rw.2245259403 |
| Directory | /workspace/13.chip_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/13.chip_same_csr_outstanding.2955919281 |
| Short name | T454 |
| Test name | |
| Test status | |
| Simulation time | 30419397622 ps |
| CPU time | 3464.68 seconds |
| Started | Aug 13 06:51:15 PM PDT 24 |
| Finished | Aug 13 07:49:00 PM PDT 24 |
| Peak memory | 593244 kb |
| Host | smart-d6da09c1-6edf-4477-b980-ff9ed024eb41 |
| User | root |
| Command | /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +run_same_csr_outstanding +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2955919281 -assert nopostproc +UVM_TE STNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb - cm_log /dev/null -cm_name 13.chip_same_csr_outstanding.2955919281 |
| Directory | /workspace/13.chip_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/13.chip_tl_errors.2364272878 |
| Short name | T2462 |
| Test name | |
| Test status | |
| Simulation time | 2934353560 ps |
| CPU time | 186.16 seconds |
| Started | Aug 13 06:51:15 PM PDT 24 |
| Finished | Aug 13 06:54:21 PM PDT 24 |
| Peak memory | 603376 kb |
| Host | smart-8804f63b-4697-4fed-aedf-491fbdcc86c0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2364272878 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.chip_tl_errors.2364272878 |
| Directory | /workspace/13.chip_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/13.xbar_access_same_device.1685845875 |
| Short name | T1884 |
| Test name | |
| Test status | |
| Simulation time | 856296937 ps |
| CPU time | 60.01 seconds |
| Started | Aug 13 06:51:19 PM PDT 24 |
| Finished | Aug 13 06:52:19 PM PDT 24 |
| Peak memory | 575464 kb |
| Host | smart-74ffd73c-a859-459c-8bf8-5a3ed2644095 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1685845875 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.xbar_access_same_device .1685845875 |
| Directory | /workspace/13.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/13.xbar_access_same_device_slow_rsp.564582272 |
| Short name | T2690 |
| Test name | |
| Test status | |
| Simulation time | 43371745809 ps |
| CPU time | 733.78 seconds |
| Started | Aug 13 06:51:18 PM PDT 24 |
| Finished | Aug 13 07:03:32 PM PDT 24 |
| Peak memory | 575828 kb |
| Host | smart-f56b2de5-873a-4529-8ef9-c1d6aca6a34c |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=564582272 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.xbar_access_same_d evice_slow_rsp.564582272 |
| Directory | /workspace/13.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/13.xbar_error_and_unmapped_addr.2268753594 |
| Short name | T1623 |
| Test name | |
| Test status | |
| Simulation time | 219254842 ps |
| CPU time | 10.33 seconds |
| Started | Aug 13 06:51:21 PM PDT 24 |
| Finished | Aug 13 06:51:32 PM PDT 24 |
| Peak memory | 575656 kb |
| Host | smart-70585eee-d3a7-4d18-ae97-9de394106ae9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2268753594 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.xbar_error_and_unmapped_add r.2268753594 |
| Directory | /workspace/13.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/13.xbar_error_random.2898675045 |
| Short name | T2718 |
| Test name | |
| Test status | |
| Simulation time | 1679661555 ps |
| CPU time | 48.91 seconds |
| Started | Aug 13 06:51:15 PM PDT 24 |
| Finished | Aug 13 06:52:04 PM PDT 24 |
| Peak memory | 575740 kb |
| Host | smart-b901b984-8d77-4996-8dda-8f57743180c4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2898675045 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.xbar_error_random.2898675045 |
| Directory | /workspace/13.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/13.xbar_random.806495489 |
| Short name | T2817 |
| Test name | |
| Test status | |
| Simulation time | 231293217 ps |
| CPU time | 20.93 seconds |
| Started | Aug 13 06:51:25 PM PDT 24 |
| Finished | Aug 13 06:51:46 PM PDT 24 |
| Peak memory | 575688 kb |
| Host | smart-014211b8-e632-4e25-86b8-49eba7418fe2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=806495489 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.xbar_random.806495489 |
| Directory | /workspace/13.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/13.xbar_random_large_delays.1894504715 |
| Short name | T2035 |
| Test name | |
| Test status | |
| Simulation time | 49087777264 ps |
| CPU time | 484.08 seconds |
| Started | Aug 13 06:51:19 PM PDT 24 |
| Finished | Aug 13 06:59:23 PM PDT 24 |
| Peak memory | 575612 kb |
| Host | smart-792fe384-d76b-4ef8-94b9-bb8a13776326 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1894504715 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.xbar_random_large_delays.1894504715 |
| Directory | /workspace/13.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/13.xbar_random_slow_rsp.204458249 |
| Short name | T2815 |
| Test name | |
| Test status | |
| Simulation time | 53217761894 ps |
| CPU time | 836.52 seconds |
| Started | Aug 13 06:51:20 PM PDT 24 |
| Finished | Aug 13 07:05:17 PM PDT 24 |
| Peak memory | 575676 kb |
| Host | smart-92ff9e8e-9636-4669-b39b-b1e0dd554edc |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=204458249 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.xbar_random_slow_rsp.204458249 |
| Directory | /workspace/13.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/13.xbar_random_zero_delays.1825415706 |
| Short name | T1576 |
| Test name | |
| Test status | |
| Simulation time | 305451611 ps |
| CPU time | 26.49 seconds |
| Started | Aug 13 06:51:13 PM PDT 24 |
| Finished | Aug 13 06:51:40 PM PDT 24 |
| Peak memory | 575576 kb |
| Host | smart-c6b15ecc-49cd-4057-8b80-ce6db84f8b31 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1825415706 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.xbar_random_zero_del ays.1825415706 |
| Directory | /workspace/13.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/13.xbar_same_source.4079970609 |
| Short name | T1799 |
| Test name | |
| Test status | |
| Simulation time | 1389105558 ps |
| CPU time | 40.24 seconds |
| Started | Aug 13 06:51:14 PM PDT 24 |
| Finished | Aug 13 06:51:54 PM PDT 24 |
| Peak memory | 575608 kb |
| Host | smart-c478cd59-6915-4f95-9bde-b6bb88669138 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4079970609 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.xbar_same_source.4079970609 |
| Directory | /workspace/13.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/13.xbar_smoke.3963604018 |
| Short name | T2848 |
| Test name | |
| Test status | |
| Simulation time | 198454805 ps |
| CPU time | 9.3 seconds |
| Started | Aug 13 06:51:24 PM PDT 24 |
| Finished | Aug 13 06:51:33 PM PDT 24 |
| Peak memory | 573508 kb |
| Host | smart-26d8ad44-acdc-4101-bdfc-e59c596b7eef |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3963604018 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.xbar_smoke.3963604018 |
| Directory | /workspace/13.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/13.xbar_smoke_large_delays.754233450 |
| Short name | T1925 |
| Test name | |
| Test status | |
| Simulation time | 7962239412 ps |
| CPU time | 80.99 seconds |
| Started | Aug 13 06:51:15 PM PDT 24 |
| Finished | Aug 13 06:52:36 PM PDT 24 |
| Peak memory | 574332 kb |
| Host | smart-5ffd9b4d-0435-47bf-9139-9099db182ff2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=754233450 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.xbar_smoke_large_delays.754233450 |
| Directory | /workspace/13.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/13.xbar_smoke_slow_rsp.1868977805 |
| Short name | T2420 |
| Test name | |
| Test status | |
| Simulation time | 6003094679 ps |
| CPU time | 98.9 seconds |
| Started | Aug 13 06:51:16 PM PDT 24 |
| Finished | Aug 13 06:52:55 PM PDT 24 |
| Peak memory | 574332 kb |
| Host | smart-877f192d-2445-4918-a8ad-42bf44fcc655 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1868977805 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.xbar_smoke_slow_rsp.1868977805 |
| Directory | /workspace/13.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/13.xbar_smoke_zero_delays.666762134 |
| Short name | T2535 |
| Test name | |
| Test status | |
| Simulation time | 47161452 ps |
| CPU time | 6.22 seconds |
| Started | Aug 13 06:51:23 PM PDT 24 |
| Finished | Aug 13 06:51:29 PM PDT 24 |
| Peak memory | 574224 kb |
| Host | smart-9095ffed-dbd2-47d1-8313-b51c188ef97a |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=666762134 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.xbar_smoke_zero_delays .666762134 |
| Directory | /workspace/13.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/13.xbar_stress_all.1358474146 |
| Short name | T519 |
| Test name | |
| Test status | |
| Simulation time | 8359228638 ps |
| CPU time | 314.27 seconds |
| Started | Aug 13 06:51:16 PM PDT 24 |
| Finished | Aug 13 06:56:31 PM PDT 24 |
| Peak memory | 576524 kb |
| Host | smart-a7129e30-1967-485f-889e-6248c7fd6bdc |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1358474146 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.xbar_stress_all.1358474146 |
| Directory | /workspace/13.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/13.xbar_stress_all_with_error.1602673586 |
| Short name | T2677 |
| Test name | |
| Test status | |
| Simulation time | 12084858240 ps |
| CPU time | 440.19 seconds |
| Started | Aug 13 06:51:14 PM PDT 24 |
| Finished | Aug 13 06:58:34 PM PDT 24 |
| Peak memory | 576532 kb |
| Host | smart-54f8d92b-f3cc-4cf2-9740-8380b1592f05 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1602673586 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.xbar_stress_all_with_error.1602673586 |
| Directory | /workspace/13.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/13.xbar_stress_all_with_rand_reset.3812744233 |
| Short name | T2766 |
| Test name | |
| Test status | |
| Simulation time | 3049381250 ps |
| CPU time | 354.73 seconds |
| Started | Aug 13 06:51:15 PM PDT 24 |
| Finished | Aug 13 06:57:10 PM PDT 24 |
| Peak memory | 576548 kb |
| Host | smart-272d5d47-446b-4605-833a-47de44b41dd6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3812744233 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.xbar_stress_all _with_rand_reset.3812744233 |
| Directory | /workspace/13.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/13.xbar_stress_all_with_reset_error.1655997663 |
| Short name | T2750 |
| Test name | |
| Test status | |
| Simulation time | 15546873728 ps |
| CPU time | 647.63 seconds |
| Started | Aug 13 06:51:23 PM PDT 24 |
| Finished | Aug 13 07:02:11 PM PDT 24 |
| Peak memory | 576576 kb |
| Host | smart-a1db10a2-d869-4337-90db-bc4d79ac1526 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1655997663 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.xbar_stress_al l_with_reset_error.1655997663 |
| Directory | /workspace/13.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/13.xbar_unmapped_addr.430558393 |
| Short name | T2001 |
| Test name | |
| Test status | |
| Simulation time | 78581378 ps |
| CPU time | 7.26 seconds |
| Started | Aug 13 06:51:14 PM PDT 24 |
| Finished | Aug 13 06:51:21 PM PDT 24 |
| Peak memory | 573624 kb |
| Host | smart-2df3385b-0a53-459f-98af-c645398caaec |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=430558393 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.xbar_unmapped_addr.430558393 |
| Directory | /workspace/13.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/14.chip_csr_mem_rw_with_rand_reset.1756752689 |
| Short name | T418 |
| Test name | |
| Test status | |
| Simulation time | 12953667542 ps |
| CPU time | 1196.25 seconds |
| Started | Aug 13 06:51:14 PM PDT 24 |
| Finished | Aug 13 07:11:10 PM PDT 24 |
| Peak memory | 652660 kb |
| Host | smart-63e79b84-3026-4d1f-b721-aa9dd360c965 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1756752689 -assert nopostproc + UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top .vdb -cm_log /dev/null -cm_name 14.chip_csr_mem_rw_with_rand_reset.1756752689 |
| Directory | /workspace/14.chip_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/14.chip_csr_rw.3536725178 |
| Short name | T2789 |
| Test name | |
| Test status | |
| Simulation time | 4469551874 ps |
| CPU time | 392.7 seconds |
| Started | Aug 13 06:51:27 PM PDT 24 |
| Finished | Aug 13 06:58:00 PM PDT 24 |
| Peak memory | 598616 kb |
| Host | smart-608bac24-9abd-40d8-a111-e5abc17c9c2f |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3536725178 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.chip_csr_rw.3536725178 |
| Directory | /workspace/14.chip_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/14.chip_same_csr_outstanding.2081788412 |
| Short name | T2246 |
| Test name | |
| Test status | |
| Simulation time | 28232869334 ps |
| CPU time | 3739.2 seconds |
| Started | Aug 13 06:51:17 PM PDT 24 |
| Finished | Aug 13 07:53:37 PM PDT 24 |
| Peak memory | 592468 kb |
| Host | smart-275d1c7c-35d1-4612-956e-def881d0a34a |
| User | root |
| Command | /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +run_same_csr_outstanding +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2081788412 -assert nopostproc +UVM_TE STNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb - cm_log /dev/null -cm_name 14.chip_same_csr_outstanding.2081788412 |
| Directory | /workspace/14.chip_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/14.xbar_access_same_device.4191575063 |
| Short name | T2014 |
| Test name | |
| Test status | |
| Simulation time | 625247627 ps |
| CPU time | 45.72 seconds |
| Started | Aug 13 06:51:18 PM PDT 24 |
| Finished | Aug 13 06:52:04 PM PDT 24 |
| Peak memory | 575668 kb |
| Host | smart-e51945a6-0614-47d4-b119-385210035c17 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4191575063 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.xbar_access_same_device .4191575063 |
| Directory | /workspace/14.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/14.xbar_access_same_device_slow_rsp.202492326 |
| Short name | T2619 |
| Test name | |
| Test status | |
| Simulation time | 14343650548 ps |
| CPU time | 242.18 seconds |
| Started | Aug 13 06:51:14 PM PDT 24 |
| Finished | Aug 13 06:55:17 PM PDT 24 |
| Peak memory | 575652 kb |
| Host | smart-3c11e9a5-ae9c-431d-96f4-a0ae46af627e |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=202492326 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.xbar_access_same_d evice_slow_rsp.202492326 |
| Directory | /workspace/14.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/14.xbar_error_and_unmapped_addr.3736504070 |
| Short name | T2239 |
| Test name | |
| Test status | |
| Simulation time | 699471274 ps |
| CPU time | 28.77 seconds |
| Started | Aug 13 06:51:26 PM PDT 24 |
| Finished | Aug 13 06:51:55 PM PDT 24 |
| Peak memory | 575652 kb |
| Host | smart-37de81e6-8e7e-4a23-96fd-6b9a85e04eff |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3736504070 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.xbar_error_and_unmapped_add r.3736504070 |
| Directory | /workspace/14.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/14.xbar_error_random.3818874503 |
| Short name | T2494 |
| Test name | |
| Test status | |
| Simulation time | 88523259 ps |
| CPU time | 10.12 seconds |
| Started | Aug 13 06:51:15 PM PDT 24 |
| Finished | Aug 13 06:51:25 PM PDT 24 |
| Peak memory | 575672 kb |
| Host | smart-0d836d69-2862-4cdf-a13c-961dc6207298 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3818874503 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.xbar_error_random.3818874503 |
| Directory | /workspace/14.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/14.xbar_random.1307412895 |
| Short name | T2814 |
| Test name | |
| Test status | |
| Simulation time | 606796180 ps |
| CPU time | 46.66 seconds |
| Started | Aug 13 06:51:27 PM PDT 24 |
| Finished | Aug 13 06:52:14 PM PDT 24 |
| Peak memory | 575692 kb |
| Host | smart-9161bf8d-1898-4b04-a984-48128aee18dd |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1307412895 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.xbar_random.1307412895 |
| Directory | /workspace/14.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/14.xbar_random_large_delays.3143514392 |
| Short name | T2351 |
| Test name | |
| Test status | |
| Simulation time | 107846926843 ps |
| CPU time | 1159.02 seconds |
| Started | Aug 13 06:51:12 PM PDT 24 |
| Finished | Aug 13 07:10:32 PM PDT 24 |
| Peak memory | 575540 kb |
| Host | smart-d02a77b8-ceb8-4201-8d04-e0c733e01938 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3143514392 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.xbar_random_large_delays.3143514392 |
| Directory | /workspace/14.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/14.xbar_random_slow_rsp.2266835712 |
| Short name | T647 |
| Test name | |
| Test status | |
| Simulation time | 35406841541 ps |
| CPU time | 581.65 seconds |
| Started | Aug 13 06:51:16 PM PDT 24 |
| Finished | Aug 13 07:00:58 PM PDT 24 |
| Peak memory | 575808 kb |
| Host | smart-817eb18e-d917-4d18-95ad-94de36e19138 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2266835712 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.xbar_random_slow_rsp.2266835712 |
| Directory | /workspace/14.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/14.xbar_random_zero_delays.91865006 |
| Short name | T2425 |
| Test name | |
| Test status | |
| Simulation time | 26988955 ps |
| CPU time | 5.39 seconds |
| Started | Aug 13 06:51:32 PM PDT 24 |
| Finished | Aug 13 06:51:37 PM PDT 24 |
| Peak memory | 573528 kb |
| Host | smart-9a59f14f-11ac-49ca-abe6-d1d50c7a5023 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=91865006 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.xbar_random_zero_delay s.91865006 |
| Directory | /workspace/14.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/14.xbar_same_source.1028008576 |
| Short name | T2148 |
| Test name | |
| Test status | |
| Simulation time | 2256859181 ps |
| CPU time | 66.39 seconds |
| Started | Aug 13 06:51:25 PM PDT 24 |
| Finished | Aug 13 06:52:32 PM PDT 24 |
| Peak memory | 575568 kb |
| Host | smart-ab60afe9-7be8-45e2-92f8-342f6b04531a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1028008576 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.xbar_same_source.1028008576 |
| Directory | /workspace/14.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/14.xbar_smoke.2306826136 |
| Short name | T1874 |
| Test name | |
| Test status | |
| Simulation time | 42828710 ps |
| CPU time | 5.86 seconds |
| Started | Aug 13 06:51:15 PM PDT 24 |
| Finished | Aug 13 06:51:21 PM PDT 24 |
| Peak memory | 573608 kb |
| Host | smart-405ac1a5-f3d1-4eb2-9dea-8f22ef94a704 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2306826136 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.xbar_smoke.2306826136 |
| Directory | /workspace/14.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/14.xbar_smoke_large_delays.3799567145 |
| Short name | T666 |
| Test name | |
| Test status | |
| Simulation time | 7971701413 ps |
| CPU time | 86.12 seconds |
| Started | Aug 13 06:51:19 PM PDT 24 |
| Finished | Aug 13 06:52:45 PM PDT 24 |
| Peak memory | 573684 kb |
| Host | smart-5a5f504e-2ed9-4972-b2d8-0556be301478 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3799567145 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.xbar_smoke_large_delays.3799567145 |
| Directory | /workspace/14.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/14.xbar_smoke_slow_rsp.968491343 |
| Short name | T2337 |
| Test name | |
| Test status | |
| Simulation time | 5895647249 ps |
| CPU time | 94.96 seconds |
| Started | Aug 13 06:51:17 PM PDT 24 |
| Finished | Aug 13 06:52:52 PM PDT 24 |
| Peak memory | 573604 kb |
| Host | smart-c62dfd27-173b-4b5c-8b95-fb12a17ee50d |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=968491343 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.xbar_smoke_slow_rsp.968491343 |
| Directory | /workspace/14.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/14.xbar_smoke_zero_delays.3832768606 |
| Short name | T1482 |
| Test name | |
| Test status | |
| Simulation time | 50216203 ps |
| CPU time | 6.07 seconds |
| Started | Aug 13 06:51:28 PM PDT 24 |
| Finished | Aug 13 06:51:34 PM PDT 24 |
| Peak memory | 574240 kb |
| Host | smart-3b2017a3-ea29-44c8-ba2c-a747fae629c7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3832768606 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.xbar_smoke_zero_delay s.3832768606 |
| Directory | /workspace/14.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/14.xbar_stress_all.3661441523 |
| Short name | T2820 |
| Test name | |
| Test status | |
| Simulation time | 5758558272 ps |
| CPU time | 208.94 seconds |
| Started | Aug 13 06:51:21 PM PDT 24 |
| Finished | Aug 13 06:54:50 PM PDT 24 |
| Peak memory | 575788 kb |
| Host | smart-a1f3f1b0-c149-4f94-b7d9-8665c87401b7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3661441523 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.xbar_stress_all.3661441523 |
| Directory | /workspace/14.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/14.xbar_stress_all_with_error.1387323010 |
| Short name | T1627 |
| Test name | |
| Test status | |
| Simulation time | 2204291534 ps |
| CPU time | 160.08 seconds |
| Started | Aug 13 06:51:18 PM PDT 24 |
| Finished | Aug 13 06:53:58 PM PDT 24 |
| Peak memory | 575724 kb |
| Host | smart-186cfac1-bd17-4bcb-a98b-dc396d5133cf |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1387323010 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.xbar_stress_all_with_error.1387323010 |
| Directory | /workspace/14.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/14.xbar_stress_all_with_rand_reset.173003481 |
| Short name | T2106 |
| Test name | |
| Test status | |
| Simulation time | 701355971 ps |
| CPU time | 142.7 seconds |
| Started | Aug 13 06:51:17 PM PDT 24 |
| Finished | Aug 13 06:53:40 PM PDT 24 |
| Peak memory | 576496 kb |
| Host | smart-453481ff-776f-4daa-b2cf-6eac6f596545 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=173003481 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_res et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.xbar_stress_all_ with_rand_reset.173003481 |
| Directory | /workspace/14.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/14.xbar_stress_all_with_reset_error.1217826868 |
| Short name | T1793 |
| Test name | |
| Test status | |
| Simulation time | 668877290 ps |
| CPU time | 196.06 seconds |
| Started | Aug 13 06:51:17 PM PDT 24 |
| Finished | Aug 13 06:54:34 PM PDT 24 |
| Peak memory | 576504 kb |
| Host | smart-566ff8af-a7c4-40bd-8abd-209c56ec40da |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1217826868 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.xbar_stress_al l_with_reset_error.1217826868 |
| Directory | /workspace/14.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/14.xbar_unmapped_addr.2576366156 |
| Short name | T1860 |
| Test name | |
| Test status | |
| Simulation time | 484434229 ps |
| CPU time | 23.7 seconds |
| Started | Aug 13 06:51:13 PM PDT 24 |
| Finished | Aug 13 06:51:37 PM PDT 24 |
| Peak memory | 575628 kb |
| Host | smart-4308408c-e576-404f-94d3-f8657036f52e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2576366156 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.xbar_unmapped_addr.2576366156 |
| Directory | /workspace/14.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/15.chip_csr_mem_rw_with_rand_reset.3601893965 |
| Short name | T2783 |
| Test name | |
| Test status | |
| Simulation time | 7040713224 ps |
| CPU time | 457.84 seconds |
| Started | Aug 13 06:51:14 PM PDT 24 |
| Finished | Aug 13 06:58:52 PM PDT 24 |
| Peak memory | 638288 kb |
| Host | smart-9c65bb85-fb73-44ba-8d86-49e79a65b5ba |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3601893965 -assert nopostproc + UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top .vdb -cm_log /dev/null -cm_name 15.chip_csr_mem_rw_with_rand_reset.3601893965 |
| Directory | /workspace/15.chip_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/15.chip_csr_rw.1848936849 |
| Short name | T2119 |
| Test name | |
| Test status | |
| Simulation time | 4337565272 ps |
| CPU time | 313.91 seconds |
| Started | Aug 13 06:51:29 PM PDT 24 |
| Finished | Aug 13 06:56:43 PM PDT 24 |
| Peak memory | 596896 kb |
| Host | smart-57f2cde0-5a1a-464f-8c4d-2346ec2d3d8f |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1848936849 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.chip_csr_rw.1848936849 |
| Directory | /workspace/15.chip_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/15.chip_same_csr_outstanding.3941044558 |
| Short name | T407 |
| Test name | |
| Test status | |
| Simulation time | 28949719664 ps |
| CPU time | 4166.91 seconds |
| Started | Aug 13 06:51:28 PM PDT 24 |
| Finished | Aug 13 08:00:55 PM PDT 24 |
| Peak memory | 592568 kb |
| Host | smart-778e30bc-46bd-4d52-9979-cb5d47f3a9ad |
| User | root |
| Command | /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +run_same_csr_outstanding +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3941044558 -assert nopostproc +UVM_TE STNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb - cm_log /dev/null -cm_name 15.chip_same_csr_outstanding.3941044558 |
| Directory | /workspace/15.chip_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/15.xbar_access_same_device.1116785866 |
| Short name | T2782 |
| Test name | |
| Test status | |
| Simulation time | 793521293 ps |
| CPU time | 60.79 seconds |
| Started | Aug 13 06:51:14 PM PDT 24 |
| Finished | Aug 13 06:52:15 PM PDT 24 |
| Peak memory | 575648 kb |
| Host | smart-f76b6133-c3c2-4078-aac4-dcb0224c4d58 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1116785866 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.xbar_access_same_device .1116785866 |
| Directory | /workspace/15.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/15.xbar_access_same_device_slow_rsp.3044509206 |
| Short name | T2488 |
| Test name | |
| Test status | |
| Simulation time | 80069562446 ps |
| CPU time | 1439.73 seconds |
| Started | Aug 13 06:51:18 PM PDT 24 |
| Finished | Aug 13 07:15:18 PM PDT 24 |
| Peak memory | 575832 kb |
| Host | smart-99aa42c6-d09b-4464-9e08-4a786970ae40 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3044509206 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.xbar_access_same_ device_slow_rsp.3044509206 |
| Directory | /workspace/15.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/15.xbar_error_and_unmapped_addr.3228114348 |
| Short name | T2163 |
| Test name | |
| Test status | |
| Simulation time | 195654873 ps |
| CPU time | 22.2 seconds |
| Started | Aug 13 06:51:17 PM PDT 24 |
| Finished | Aug 13 06:51:40 PM PDT 24 |
| Peak memory | 575408 kb |
| Host | smart-66cbe8bd-ef71-4814-8346-de9e75594c3e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3228114348 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.xbar_error_and_unmapped_add r.3228114348 |
| Directory | /workspace/15.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/15.xbar_error_random.3656857255 |
| Short name | T2717 |
| Test name | |
| Test status | |
| Simulation time | 530469121 ps |
| CPU time | 44.4 seconds |
| Started | Aug 13 06:51:28 PM PDT 24 |
| Finished | Aug 13 06:52:13 PM PDT 24 |
| Peak memory | 575632 kb |
| Host | smart-f72f51c4-ed2a-4610-a310-b273280993f5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3656857255 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.xbar_error_random.3656857255 |
| Directory | /workspace/15.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/15.xbar_random.1109127659 |
| Short name | T2126 |
| Test name | |
| Test status | |
| Simulation time | 397943443 ps |
| CPU time | 33.57 seconds |
| Started | Aug 13 06:51:28 PM PDT 24 |
| Finished | Aug 13 06:52:01 PM PDT 24 |
| Peak memory | 575636 kb |
| Host | smart-6be8c908-6543-42c9-92be-e41254cf6cbc |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1109127659 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.xbar_random.1109127659 |
| Directory | /workspace/15.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/15.xbar_random_large_delays.1093791673 |
| Short name | T2381 |
| Test name | |
| Test status | |
| Simulation time | 84343055453 ps |
| CPU time | 847.53 seconds |
| Started | Aug 13 06:51:18 PM PDT 24 |
| Finished | Aug 13 07:05:26 PM PDT 24 |
| Peak memory | 575732 kb |
| Host | smart-e44c4c1c-0450-43db-93f8-fe40238b53d8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1093791673 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.xbar_random_large_delays.1093791673 |
| Directory | /workspace/15.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/15.xbar_random_slow_rsp.2279289858 |
| Short name | T2092 |
| Test name | |
| Test status | |
| Simulation time | 17928439034 ps |
| CPU time | 312.21 seconds |
| Started | Aug 13 06:51:30 PM PDT 24 |
| Finished | Aug 13 06:56:43 PM PDT 24 |
| Peak memory | 575620 kb |
| Host | smart-e7b80db7-ff60-4774-813f-59d53f464aaf |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2279289858 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.xbar_random_slow_rsp.2279289858 |
| Directory | /workspace/15.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/15.xbar_random_zero_delays.1167047806 |
| Short name | T2640 |
| Test name | |
| Test status | |
| Simulation time | 162916490 ps |
| CPU time | 16.43 seconds |
| Started | Aug 13 06:51:19 PM PDT 24 |
| Finished | Aug 13 06:51:36 PM PDT 24 |
| Peak memory | 575648 kb |
| Host | smart-fbb8d08b-da20-4971-a7d3-51a98a93df9e |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1167047806 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.xbar_random_zero_del ays.1167047806 |
| Directory | /workspace/15.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/15.xbar_same_source.797522843 |
| Short name | T2844 |
| Test name | |
| Test status | |
| Simulation time | 2153638920 ps |
| CPU time | 57.52 seconds |
| Started | Aug 13 06:51:18 PM PDT 24 |
| Finished | Aug 13 06:52:16 PM PDT 24 |
| Peak memory | 575568 kb |
| Host | smart-024887c1-1bca-464a-b4b7-7b0a0d5e71ed |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=797522843 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.xbar_same_source.797522843 |
| Directory | /workspace/15.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/15.xbar_smoke.2772055628 |
| Short name | T1618 |
| Test name | |
| Test status | |
| Simulation time | 192514076 ps |
| CPU time | 8.4 seconds |
| Started | Aug 13 06:51:16 PM PDT 24 |
| Finished | Aug 13 06:51:25 PM PDT 24 |
| Peak memory | 573528 kb |
| Host | smart-85c81cdc-97b2-41c3-831e-0e7019128496 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2772055628 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.xbar_smoke.2772055628 |
| Directory | /workspace/15.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/15.xbar_smoke_large_delays.1885633519 |
| Short name | T1825 |
| Test name | |
| Test status | |
| Simulation time | 6582400302 ps |
| CPU time | 72.78 seconds |
| Started | Aug 13 06:51:19 PM PDT 24 |
| Finished | Aug 13 06:52:32 PM PDT 24 |
| Peak memory | 573772 kb |
| Host | smart-fd47478c-7b85-43dc-938a-8b9f93b1102e |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1885633519 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.xbar_smoke_large_delays.1885633519 |
| Directory | /workspace/15.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/15.xbar_smoke_slow_rsp.2124620950 |
| Short name | T2893 |
| Test name | |
| Test status | |
| Simulation time | 4721736081 ps |
| CPU time | 81.47 seconds |
| Started | Aug 13 06:51:13 PM PDT 24 |
| Finished | Aug 13 06:52:35 PM PDT 24 |
| Peak memory | 573620 kb |
| Host | smart-72417785-8224-4dcb-ae39-063de6888750 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2124620950 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.xbar_smoke_slow_rsp.2124620950 |
| Directory | /workspace/15.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/15.xbar_smoke_zero_delays.2254413214 |
| Short name | T1675 |
| Test name | |
| Test status | |
| Simulation time | 44636130 ps |
| CPU time | 6.72 seconds |
| Started | Aug 13 06:51:14 PM PDT 24 |
| Finished | Aug 13 06:51:21 PM PDT 24 |
| Peak memory | 573520 kb |
| Host | smart-1b451309-7200-4c50-b090-c032cdaa58cd |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2254413214 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.xbar_smoke_zero_delay s.2254413214 |
| Directory | /workspace/15.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/15.xbar_stress_all.2183947295 |
| Short name | T2366 |
| Test name | |
| Test status | |
| Simulation time | 3871650439 ps |
| CPU time | 251.97 seconds |
| Started | Aug 13 06:51:37 PM PDT 24 |
| Finished | Aug 13 06:55:49 PM PDT 24 |
| Peak memory | 576540 kb |
| Host | smart-87077a71-8e4a-4310-8b85-ef8269e7fd98 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2183947295 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.xbar_stress_all.2183947295 |
| Directory | /workspace/15.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/15.xbar_stress_all_with_error.3262589933 |
| Short name | T2628 |
| Test name | |
| Test status | |
| Simulation time | 14669579890 ps |
| CPU time | 481.6 seconds |
| Started | Aug 13 06:51:15 PM PDT 24 |
| Finished | Aug 13 06:59:17 PM PDT 24 |
| Peak memory | 576492 kb |
| Host | smart-ceaf2f9d-3bef-4a7b-97e3-7b58496668a8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3262589933 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.xbar_stress_all_with_error.3262589933 |
| Directory | /workspace/15.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/15.xbar_stress_all_with_reset_error.1080550775 |
| Short name | T2896 |
| Test name | |
| Test status | |
| Simulation time | 141491533 ps |
| CPU time | 33.57 seconds |
| Started | Aug 13 06:51:40 PM PDT 24 |
| Finished | Aug 13 06:52:13 PM PDT 24 |
| Peak memory | 575668 kb |
| Host | smart-b63070c2-f979-4421-816f-828b903a2446 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1080550775 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.xbar_stress_al l_with_reset_error.1080550775 |
| Directory | /workspace/15.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/15.xbar_unmapped_addr.1875803038 |
| Short name | T2276 |
| Test name | |
| Test status | |
| Simulation time | 432046913 ps |
| CPU time | 17.79 seconds |
| Started | Aug 13 06:51:15 PM PDT 24 |
| Finished | Aug 13 06:51:32 PM PDT 24 |
| Peak memory | 575712 kb |
| Host | smart-5cda9b35-afe7-46f4-be47-0bcb2906dc65 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1875803038 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.xbar_unmapped_addr.1875803038 |
| Directory | /workspace/15.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/16.chip_csr_mem_rw_with_rand_reset.4242924962 |
| Short name | T2623 |
| Test name | |
| Test status | |
| Simulation time | 6949234904 ps |
| CPU time | 441.29 seconds |
| Started | Aug 13 06:51:24 PM PDT 24 |
| Finished | Aug 13 06:58:46 PM PDT 24 |
| Peak memory | 638280 kb |
| Host | smart-edacb0a7-2cd6-4680-bfcd-7c70f6fd9ed8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4242924962 -assert nopostproc + UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top .vdb -cm_log /dev/null -cm_name 16.chip_csr_mem_rw_with_rand_reset.4242924962 |
| Directory | /workspace/16.chip_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/16.chip_csr_rw.3673099641 |
| Short name | T2345 |
| Test name | |
| Test status | |
| Simulation time | 3570996136 ps |
| CPU time | 333.11 seconds |
| Started | Aug 13 06:51:26 PM PDT 24 |
| Finished | Aug 13 06:57:00 PM PDT 24 |
| Peak memory | 597872 kb |
| Host | smart-c7d329d2-7663-447b-bc3d-09bd4b2ccdc1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3673099641 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.chip_csr_rw.3673099641 |
| Directory | /workspace/16.chip_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/16.chip_same_csr_outstanding.2677772966 |
| Short name | T456 |
| Test name | |
| Test status | |
| Simulation time | 31362641559 ps |
| CPU time | 3420.02 seconds |
| Started | Aug 13 06:51:27 PM PDT 24 |
| Finished | Aug 13 07:48:27 PM PDT 24 |
| Peak memory | 593296 kb |
| Host | smart-88fd1447-ce3a-4a59-9c99-9527589843cc |
| User | root |
| Command | /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +run_same_csr_outstanding +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2677772966 -assert nopostproc +UVM_TE STNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb - cm_log /dev/null -cm_name 16.chip_same_csr_outstanding.2677772966 |
| Directory | /workspace/16.chip_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/16.xbar_access_same_device.2512076498 |
| Short name | T1878 |
| Test name | |
| Test status | |
| Simulation time | 795420346 ps |
| CPU time | 58.08 seconds |
| Started | Aug 13 06:51:14 PM PDT 24 |
| Finished | Aug 13 06:52:12 PM PDT 24 |
| Peak memory | 575580 kb |
| Host | smart-301a7b37-de99-43e6-bf00-8f97eb937f33 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2512076498 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.xbar_access_same_device .2512076498 |
| Directory | /workspace/16.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/16.xbar_access_same_device_slow_rsp.1751077314 |
| Short name | T876 |
| Test name | |
| Test status | |
| Simulation time | 113689372826 ps |
| CPU time | 1951.65 seconds |
| Started | Aug 13 06:51:26 PM PDT 24 |
| Finished | Aug 13 07:23:58 PM PDT 24 |
| Peak memory | 575820 kb |
| Host | smart-16944c1c-745c-429c-838b-80a77d427cc4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1751077314 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.xbar_access_same_ device_slow_rsp.1751077314 |
| Directory | /workspace/16.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/16.xbar_error_and_unmapped_addr.4289875737 |
| Short name | T1606 |
| Test name | |
| Test status | |
| Simulation time | 835985540 ps |
| CPU time | 31.87 seconds |
| Started | Aug 13 06:51:19 PM PDT 24 |
| Finished | Aug 13 06:51:51 PM PDT 24 |
| Peak memory | 575472 kb |
| Host | smart-a7235a52-4124-48e0-9ee0-3d33e8bfd112 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4289875737 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.xbar_error_and_unmapped_add r.4289875737 |
| Directory | /workspace/16.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/16.xbar_error_random.1806923283 |
| Short name | T1426 |
| Test name | |
| Test status | |
| Simulation time | 1981786811 ps |
| CPU time | 69.68 seconds |
| Started | Aug 13 06:51:32 PM PDT 24 |
| Finished | Aug 13 06:52:42 PM PDT 24 |
| Peak memory | 575728 kb |
| Host | smart-9cf0e249-ee77-482e-97e8-b00ff4a98af8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1806923283 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.xbar_error_random.1806923283 |
| Directory | /workspace/16.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/16.xbar_random.3297305203 |
| Short name | T1716 |
| Test name | |
| Test status | |
| Simulation time | 853240500 ps |
| CPU time | 31.36 seconds |
| Started | Aug 13 06:51:17 PM PDT 24 |
| Finished | Aug 13 06:51:49 PM PDT 24 |
| Peak memory | 575636 kb |
| Host | smart-fdf323b8-6161-4297-8542-baf54ba595b1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3297305203 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.xbar_random.3297305203 |
| Directory | /workspace/16.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/16.xbar_random_large_delays.2241061054 |
| Short name | T2768 |
| Test name | |
| Test status | |
| Simulation time | 45283065495 ps |
| CPU time | 490.09 seconds |
| Started | Aug 13 06:51:14 PM PDT 24 |
| Finished | Aug 13 06:59:25 PM PDT 24 |
| Peak memory | 575724 kb |
| Host | smart-5586d086-e630-4c51-a592-529951941582 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2241061054 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.xbar_random_large_delays.2241061054 |
| Directory | /workspace/16.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/16.xbar_random_slow_rsp.1504795410 |
| Short name | T2209 |
| Test name | |
| Test status | |
| Simulation time | 29827396457 ps |
| CPU time | 483.82 seconds |
| Started | Aug 13 06:51:16 PM PDT 24 |
| Finished | Aug 13 06:59:20 PM PDT 24 |
| Peak memory | 575780 kb |
| Host | smart-3e1f1548-23b3-414e-b79b-19a6b1be5d75 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1504795410 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.xbar_random_slow_rsp.1504795410 |
| Directory | /workspace/16.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/16.xbar_random_zero_delays.844957334 |
| Short name | T1914 |
| Test name | |
| Test status | |
| Simulation time | 365494847 ps |
| CPU time | 30.84 seconds |
| Started | Aug 13 06:51:11 PM PDT 24 |
| Finished | Aug 13 06:51:42 PM PDT 24 |
| Peak memory | 575568 kb |
| Host | smart-901903fe-1231-412f-aab9-c2e34496c800 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=844957334 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.xbar_random_zero_dela ys.844957334 |
| Directory | /workspace/16.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/16.xbar_same_source.2181618733 |
| Short name | T1892 |
| Test name | |
| Test status | |
| Simulation time | 310928306 ps |
| CPU time | 25.35 seconds |
| Started | Aug 13 06:51:26 PM PDT 24 |
| Finished | Aug 13 06:51:52 PM PDT 24 |
| Peak memory | 575556 kb |
| Host | smart-a8a0746b-3edb-48fe-9a4f-de3c6cbb4c68 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2181618733 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.xbar_same_source.2181618733 |
| Directory | /workspace/16.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/16.xbar_smoke.2625426102 |
| Short name | T2256 |
| Test name | |
| Test status | |
| Simulation time | 56469119 ps |
| CPU time | 6.41 seconds |
| Started | Aug 13 06:51:15 PM PDT 24 |
| Finished | Aug 13 06:51:22 PM PDT 24 |
| Peak memory | 573572 kb |
| Host | smart-789318cb-2f77-415c-bd2a-269e264f9bdb |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2625426102 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.xbar_smoke.2625426102 |
| Directory | /workspace/16.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/16.xbar_smoke_large_delays.1121237219 |
| Short name | T2071 |
| Test name | |
| Test status | |
| Simulation time | 9331604726 ps |
| CPU time | 106.28 seconds |
| Started | Aug 13 06:51:18 PM PDT 24 |
| Finished | Aug 13 06:53:04 PM PDT 24 |
| Peak memory | 573664 kb |
| Host | smart-150c47b7-d354-4b15-9508-47d874255373 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1121237219 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.xbar_smoke_large_delays.1121237219 |
| Directory | /workspace/16.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/16.xbar_smoke_slow_rsp.2010776037 |
| Short name | T2808 |
| Test name | |
| Test status | |
| Simulation time | 4832866871 ps |
| CPU time | 75.52 seconds |
| Started | Aug 13 06:51:25 PM PDT 24 |
| Finished | Aug 13 06:52:41 PM PDT 24 |
| Peak memory | 574332 kb |
| Host | smart-048185dc-11a7-480c-ad1f-f36190e41f76 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2010776037 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.xbar_smoke_slow_rsp.2010776037 |
| Directory | /workspace/16.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/16.xbar_smoke_zero_delays.1590576983 |
| Short name | T2217 |
| Test name | |
| Test status | |
| Simulation time | 47605879 ps |
| CPU time | 6.59 seconds |
| Started | Aug 13 06:51:16 PM PDT 24 |
| Finished | Aug 13 06:51:23 PM PDT 24 |
| Peak memory | 573512 kb |
| Host | smart-f79b66fd-69ad-4852-801c-0e54763666ef |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1590576983 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.xbar_smoke_zero_delay s.1590576983 |
| Directory | /workspace/16.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/16.xbar_stress_all.3770178648 |
| Short name | T2798 |
| Test name | |
| Test status | |
| Simulation time | 9188927774 ps |
| CPU time | 355.47 seconds |
| Started | Aug 13 06:51:32 PM PDT 24 |
| Finished | Aug 13 06:57:28 PM PDT 24 |
| Peak memory | 576528 kb |
| Host | smart-806852a0-2244-4e05-82c4-64b5873dfb73 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3770178648 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.xbar_stress_all.3770178648 |
| Directory | /workspace/16.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/16.xbar_stress_all_with_reset_error.2542176596 |
| Short name | T2912 |
| Test name | |
| Test status | |
| Simulation time | 2475382195 ps |
| CPU time | 433.32 seconds |
| Started | Aug 13 06:51:18 PM PDT 24 |
| Finished | Aug 13 06:58:31 PM PDT 24 |
| Peak memory | 578220 kb |
| Host | smart-6daac7cc-0e2f-4aa4-a71e-89ec1021de73 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2542176596 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.xbar_stress_al l_with_reset_error.2542176596 |
| Directory | /workspace/16.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/16.xbar_unmapped_addr.1239754696 |
| Short name | T2147 |
| Test name | |
| Test status | |
| Simulation time | 1445672423 ps |
| CPU time | 58.61 seconds |
| Started | Aug 13 06:51:19 PM PDT 24 |
| Finished | Aug 13 06:52:17 PM PDT 24 |
| Peak memory | 575684 kb |
| Host | smart-4f4d104c-c7d7-42a3-b724-de280972e03b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1239754696 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.xbar_unmapped_addr.1239754696 |
| Directory | /workspace/16.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/17.chip_csr_mem_rw_with_rand_reset.1542558180 |
| Short name | T2347 |
| Test name | |
| Test status | |
| Simulation time | 11657968180 ps |
| CPU time | 915.81 seconds |
| Started | Aug 13 06:51:39 PM PDT 24 |
| Finished | Aug 13 07:06:55 PM PDT 24 |
| Peak memory | 648872 kb |
| Host | smart-75d5c969-d9cd-4add-84cb-6c9e7a378009 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1542558180 -assert nopostproc + UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top .vdb -cm_log /dev/null -cm_name 17.chip_csr_mem_rw_with_rand_reset.1542558180 |
| Directory | /workspace/17.chip_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/17.chip_same_csr_outstanding.1708768377 |
| Short name | T417 |
| Test name | |
| Test status | |
| Simulation time | 31126140279 ps |
| CPU time | 4256.16 seconds |
| Started | Aug 13 06:51:19 PM PDT 24 |
| Finished | Aug 13 08:02:16 PM PDT 24 |
| Peak memory | 592968 kb |
| Host | smart-ff5e200c-91e4-4522-bb5f-dd9de6a3ef92 |
| User | root |
| Command | /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +run_same_csr_outstanding +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1708768377 -assert nopostproc +UVM_TE STNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb - cm_log /dev/null -cm_name 17.chip_same_csr_outstanding.1708768377 |
| Directory | /workspace/17.chip_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/17.chip_tl_errors.3181093008 |
| Short name | T2485 |
| Test name | |
| Test status | |
| Simulation time | 2395449546 ps |
| CPU time | 70.73 seconds |
| Started | Aug 13 06:51:33 PM PDT 24 |
| Finished | Aug 13 06:52:44 PM PDT 24 |
| Peak memory | 598324 kb |
| Host | smart-1409ef4e-ca90-4bdc-9935-9ea6a371d056 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3181093008 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.chip_tl_errors.3181093008 |
| Directory | /workspace/17.chip_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/17.xbar_access_same_device.3822199449 |
| Short name | T898 |
| Test name | |
| Test status | |
| Simulation time | 1722494323 ps |
| CPU time | 75.38 seconds |
| Started | Aug 13 06:51:31 PM PDT 24 |
| Finished | Aug 13 06:52:46 PM PDT 24 |
| Peak memory | 576444 kb |
| Host | smart-6be3e2f6-7e62-4142-8932-8dbaf0f7bddd |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3822199449 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.xbar_access_same_device .3822199449 |
| Directory | /workspace/17.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/17.xbar_access_same_device_slow_rsp.83418862 |
| Short name | T894 |
| Test name | |
| Test status | |
| Simulation time | 114199218333 ps |
| CPU time | 2253.64 seconds |
| Started | Aug 13 06:51:22 PM PDT 24 |
| Finished | Aug 13 07:28:56 PM PDT 24 |
| Peak memory | 575768 kb |
| Host | smart-63ad9a29-100b-4d97-8fdf-a999a9b43368 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=83418862 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.xbar_access_same_de vice_slow_rsp.83418862 |
| Directory | /workspace/17.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/17.xbar_error_and_unmapped_addr.2068061095 |
| Short name | T2007 |
| Test name | |
| Test status | |
| Simulation time | 202962620 ps |
| CPU time | 22.24 seconds |
| Started | Aug 13 06:51:38 PM PDT 24 |
| Finished | Aug 13 06:52:01 PM PDT 24 |
| Peak memory | 575432 kb |
| Host | smart-7a1b0b99-c8ec-4ca3-b32f-4c0e86f0d53d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2068061095 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.xbar_error_and_unmapped_add r.2068061095 |
| Directory | /workspace/17.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/17.xbar_error_random.4016969112 |
| Short name | T2077 |
| Test name | |
| Test status | |
| Simulation time | 444891022 ps |
| CPU time | 34.02 seconds |
| Started | Aug 13 06:51:37 PM PDT 24 |
| Finished | Aug 13 06:52:11 PM PDT 24 |
| Peak memory | 575680 kb |
| Host | smart-487d677a-00fb-49a1-bed8-4432fcf2dc91 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4016969112 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.xbar_error_random.4016969112 |
| Directory | /workspace/17.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/17.xbar_random.2402435188 |
| Short name | T741 |
| Test name | |
| Test status | |
| Simulation time | 147273319 ps |
| CPU time | 13.31 seconds |
| Started | Aug 13 06:51:39 PM PDT 24 |
| Finished | Aug 13 06:51:52 PM PDT 24 |
| Peak memory | 575676 kb |
| Host | smart-ebc976fe-4edc-4534-94d2-51dc5b7c4d4d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2402435188 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.xbar_random.2402435188 |
| Directory | /workspace/17.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/17.xbar_random_large_delays.2578583585 |
| Short name | T2295 |
| Test name | |
| Test status | |
| Simulation time | 101983031830 ps |
| CPU time | 1098.34 seconds |
| Started | Aug 13 06:51:27 PM PDT 24 |
| Finished | Aug 13 07:09:45 PM PDT 24 |
| Peak memory | 575796 kb |
| Host | smart-25ba7e4a-3fe4-4b34-babc-6e4008b1dad8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2578583585 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.xbar_random_large_delays.2578583585 |
| Directory | /workspace/17.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/17.xbar_random_slow_rsp.1206764059 |
| Short name | T1984 |
| Test name | |
| Test status | |
| Simulation time | 58809750379 ps |
| CPU time | 988.43 seconds |
| Started | Aug 13 06:51:36 PM PDT 24 |
| Finished | Aug 13 07:08:05 PM PDT 24 |
| Peak memory | 575748 kb |
| Host | smart-8dcc4fdc-d7f9-400f-ad15-847d2d0fdb61 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1206764059 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.xbar_random_slow_rsp.1206764059 |
| Directory | /workspace/17.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/17.xbar_random_zero_delays.1085038530 |
| Short name | T2452 |
| Test name | |
| Test status | |
| Simulation time | 235883762 ps |
| CPU time | 22.38 seconds |
| Started | Aug 13 06:51:42 PM PDT 24 |
| Finished | Aug 13 06:52:05 PM PDT 24 |
| Peak memory | 575564 kb |
| Host | smart-158c6a5c-f7bb-4e3a-9556-769d88ecdf8c |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1085038530 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.xbar_random_zero_del ays.1085038530 |
| Directory | /workspace/17.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/17.xbar_same_source.3272366942 |
| Short name | T2566 |
| Test name | |
| Test status | |
| Simulation time | 494075746 ps |
| CPU time | 37.46 seconds |
| Started | Aug 13 06:51:33 PM PDT 24 |
| Finished | Aug 13 06:52:11 PM PDT 24 |
| Peak memory | 575516 kb |
| Host | smart-aa8e9ac8-f065-404d-8878-e595a29cc06d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3272366942 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.xbar_same_source.3272366942 |
| Directory | /workspace/17.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/17.xbar_smoke.3612357068 |
| Short name | T1434 |
| Test name | |
| Test status | |
| Simulation time | 43279775 ps |
| CPU time | 6.17 seconds |
| Started | Aug 13 06:51:20 PM PDT 24 |
| Finished | Aug 13 06:51:27 PM PDT 24 |
| Peak memory | 573568 kb |
| Host | smart-8c509e7e-238d-4c8e-b9b9-e35e3c2f0ece |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3612357068 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.xbar_smoke.3612357068 |
| Directory | /workspace/17.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/17.xbar_smoke_large_delays.637115407 |
| Short name | T1440 |
| Test name | |
| Test status | |
| Simulation time | 7161295548 ps |
| CPU time | 72.67 seconds |
| Started | Aug 13 06:51:28 PM PDT 24 |
| Finished | Aug 13 06:52:41 PM PDT 24 |
| Peak memory | 573644 kb |
| Host | smart-6a9119c9-150c-427b-acc6-ba4fae46a65e |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=637115407 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.xbar_smoke_large_delays.637115407 |
| Directory | /workspace/17.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/17.xbar_smoke_slow_rsp.2188537428 |
| Short name | T1432 |
| Test name | |
| Test status | |
| Simulation time | 5324361406 ps |
| CPU time | 89.49 seconds |
| Started | Aug 13 06:51:16 PM PDT 24 |
| Finished | Aug 13 06:52:46 PM PDT 24 |
| Peak memory | 573684 kb |
| Host | smart-fbc5dacd-1b8e-4395-8f51-6bb13a257ffb |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2188537428 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.xbar_smoke_slow_rsp.2188537428 |
| Directory | /workspace/17.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/17.xbar_smoke_zero_delays.1358207936 |
| Short name | T2211 |
| Test name | |
| Test status | |
| Simulation time | 46417109 ps |
| CPU time | 6.18 seconds |
| Started | Aug 13 06:51:32 PM PDT 24 |
| Finished | Aug 13 06:51:38 PM PDT 24 |
| Peak memory | 573528 kb |
| Host | smart-ab2cbd63-a4f8-43fa-95fc-d69e8c8e3f02 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1358207936 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.xbar_smoke_zero_delay s.1358207936 |
| Directory | /workspace/17.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/17.xbar_stress_all.1027703216 |
| Short name | T535 |
| Test name | |
| Test status | |
| Simulation time | 8046077162 ps |
| CPU time | 313.15 seconds |
| Started | Aug 13 06:51:33 PM PDT 24 |
| Finished | Aug 13 06:56:46 PM PDT 24 |
| Peak memory | 575704 kb |
| Host | smart-ae199f79-3279-408f-97fb-84369e012cf1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1027703216 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.xbar_stress_all.1027703216 |
| Directory | /workspace/17.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/17.xbar_stress_all_with_error.78393671 |
| Short name | T2490 |
| Test name | |
| Test status | |
| Simulation time | 17638599248 ps |
| CPU time | 659.96 seconds |
| Started | Aug 13 06:51:35 PM PDT 24 |
| Finished | Aug 13 07:02:35 PM PDT 24 |
| Peak memory | 575700 kb |
| Host | smart-8c92eb65-7476-4519-ac09-26681ad2d83a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=78393671 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.xbar_stress_all_with_error.78393671 |
| Directory | /workspace/17.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/17.xbar_stress_all_with_rand_reset.886180644 |
| Short name | T2563 |
| Test name | |
| Test status | |
| Simulation time | 398672260 ps |
| CPU time | 70.83 seconds |
| Started | Aug 13 06:51:22 PM PDT 24 |
| Finished | Aug 13 06:52:32 PM PDT 24 |
| Peak memory | 576416 kb |
| Host | smart-d50162c6-d7ae-4154-ade1-73b5d89a43b1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=886180644 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_res et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.xbar_stress_all_ with_rand_reset.886180644 |
| Directory | /workspace/17.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/17.xbar_stress_all_with_reset_error.1329168227 |
| Short name | T2584 |
| Test name | |
| Test status | |
| Simulation time | 1837803074 ps |
| CPU time | 338.53 seconds |
| Started | Aug 13 06:51:25 PM PDT 24 |
| Finished | Aug 13 06:57:04 PM PDT 24 |
| Peak memory | 575624 kb |
| Host | smart-64ba2d9e-df81-42ec-8567-f02fc053d22f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1329168227 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.xbar_stress_al l_with_reset_error.1329168227 |
| Directory | /workspace/17.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/17.xbar_unmapped_addr.1121429281 |
| Short name | T1463 |
| Test name | |
| Test status | |
| Simulation time | 1087140552 ps |
| CPU time | 42.55 seconds |
| Started | Aug 13 06:51:35 PM PDT 24 |
| Finished | Aug 13 06:52:18 PM PDT 24 |
| Peak memory | 575668 kb |
| Host | smart-71d2748d-ec2f-472f-b0b6-1b104ec60140 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1121429281 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.xbar_unmapped_addr.1121429281 |
| Directory | /workspace/17.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/18.chip_csr_mem_rw_with_rand_reset.3151073320 |
| Short name | T1956 |
| Test name | |
| Test status | |
| Simulation time | 8190515440 ps |
| CPU time | 717.42 seconds |
| Started | Aug 13 06:51:30 PM PDT 24 |
| Finished | Aug 13 07:03:28 PM PDT 24 |
| Peak memory | 652644 kb |
| Host | smart-39efeff2-73d2-4825-979a-b3e76af6e95c |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3151073320 -assert nopostproc + UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top .vdb -cm_log /dev/null -cm_name 18.chip_csr_mem_rw_with_rand_reset.3151073320 |
| Directory | /workspace/18.chip_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/18.chip_csr_rw.1533451072 |
| Short name | T2681 |
| Test name | |
| Test status | |
| Simulation time | 3419693785 ps |
| CPU time | 372.59 seconds |
| Started | Aug 13 06:51:34 PM PDT 24 |
| Finished | Aug 13 06:57:47 PM PDT 24 |
| Peak memory | 598104 kb |
| Host | smart-34631683-a181-49cd-bc4f-7823d2b8eca8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1533451072 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.chip_csr_rw.1533451072 |
| Directory | /workspace/18.chip_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/18.chip_same_csr_outstanding.934859241 |
| Short name | T2589 |
| Test name | |
| Test status | |
| Simulation time | 15180863878 ps |
| CPU time | 1674.54 seconds |
| Started | Aug 13 06:51:33 PM PDT 24 |
| Finished | Aug 13 07:19:28 PM PDT 24 |
| Peak memory | 592916 kb |
| Host | smart-e5192dc1-288d-4c08-ad2a-5ae99fc93bd2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +run_same_csr_outstanding +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=934859241 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c m_log /dev/null -cm_name 18.chip_same_csr_outstanding.934859241 |
| Directory | /workspace/18.chip_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/18.xbar_access_same_device.2159399287 |
| Short name | T2178 |
| Test name | |
| Test status | |
| Simulation time | 1204275771 ps |
| CPU time | 37.87 seconds |
| Started | Aug 13 06:51:34 PM PDT 24 |
| Finished | Aug 13 06:52:12 PM PDT 24 |
| Peak memory | 575524 kb |
| Host | smart-6da98e98-d111-414f-ba95-7625d5fa5e72 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2159399287 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.xbar_access_same_device .2159399287 |
| Directory | /workspace/18.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/18.xbar_error_and_unmapped_addr.4010942507 |
| Short name | T774 |
| Test name | |
| Test status | |
| Simulation time | 403246418 ps |
| CPU time | 22.79 seconds |
| Started | Aug 13 06:51:32 PM PDT 24 |
| Finished | Aug 13 06:51:55 PM PDT 24 |
| Peak memory | 575724 kb |
| Host | smart-aea9dfd2-8888-4e56-904a-5713d38be66f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4010942507 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.xbar_error_and_unmapped_add r.4010942507 |
| Directory | /workspace/18.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/18.xbar_error_random.3636050131 |
| Short name | T1811 |
| Test name | |
| Test status | |
| Simulation time | 1537626812 ps |
| CPU time | 47.45 seconds |
| Started | Aug 13 06:51:29 PM PDT 24 |
| Finished | Aug 13 06:52:17 PM PDT 24 |
| Peak memory | 575676 kb |
| Host | smart-103aa17e-5989-4008-ad8c-7f35f2f1803d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3636050131 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.xbar_error_random.3636050131 |
| Directory | /workspace/18.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/18.xbar_random.3787247677 |
| Short name | T2648 |
| Test name | |
| Test status | |
| Simulation time | 1328341585 ps |
| CPU time | 49.78 seconds |
| Started | Aug 13 06:51:29 PM PDT 24 |
| Finished | Aug 13 06:52:19 PM PDT 24 |
| Peak memory | 575712 kb |
| Host | smart-e3f10090-3be3-4867-bc7b-0f18ff9eb109 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3787247677 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.xbar_random.3787247677 |
| Directory | /workspace/18.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/18.xbar_random_large_delays.3430500933 |
| Short name | T2664 |
| Test name | |
| Test status | |
| Simulation time | 88667625214 ps |
| CPU time | 961.4 seconds |
| Started | Aug 13 06:51:28 PM PDT 24 |
| Finished | Aug 13 07:07:30 PM PDT 24 |
| Peak memory | 575636 kb |
| Host | smart-334f43a6-738c-4653-8061-10aac268d764 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3430500933 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.xbar_random_large_delays.3430500933 |
| Directory | /workspace/18.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/18.xbar_random_slow_rsp.2911986752 |
| Short name | T1490 |
| Test name | |
| Test status | |
| Simulation time | 11291903388 ps |
| CPU time | 187.55 seconds |
| Started | Aug 13 06:51:28 PM PDT 24 |
| Finished | Aug 13 06:54:36 PM PDT 24 |
| Peak memory | 575744 kb |
| Host | smart-cb0d7534-2ee8-4b37-90aa-b266467bf2a4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2911986752 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.xbar_random_slow_rsp.2911986752 |
| Directory | /workspace/18.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/18.xbar_random_zero_delays.4215675354 |
| Short name | T2024 |
| Test name | |
| Test status | |
| Simulation time | 588340367 ps |
| CPU time | 45.15 seconds |
| Started | Aug 13 06:51:30 PM PDT 24 |
| Finished | Aug 13 06:52:15 PM PDT 24 |
| Peak memory | 575620 kb |
| Host | smart-6c6596a0-2fa7-4e22-90d5-9dc8ce148c9d |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4215675354 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.xbar_random_zero_del ays.4215675354 |
| Directory | /workspace/18.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/18.xbar_same_source.2664521838 |
| Short name | T2019 |
| Test name | |
| Test status | |
| Simulation time | 441519182 ps |
| CPU time | 30.57 seconds |
| Started | Aug 13 06:51:32 PM PDT 24 |
| Finished | Aug 13 06:52:02 PM PDT 24 |
| Peak memory | 575656 kb |
| Host | smart-1298a346-4672-4e83-8247-ba6f92c851af |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2664521838 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.xbar_same_source.2664521838 |
| Directory | /workspace/18.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/18.xbar_smoke.2752262453 |
| Short name | T2705 |
| Test name | |
| Test status | |
| Simulation time | 174668939 ps |
| CPU time | 8.92 seconds |
| Started | Aug 13 06:51:30 PM PDT 24 |
| Finished | Aug 13 06:51:39 PM PDT 24 |
| Peak memory | 573496 kb |
| Host | smart-a777664e-8a4c-44ba-a626-920e75094963 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2752262453 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.xbar_smoke.2752262453 |
| Directory | /workspace/18.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/18.xbar_smoke_large_delays.2080735075 |
| Short name | T2191 |
| Test name | |
| Test status | |
| Simulation time | 9215242079 ps |
| CPU time | 88.26 seconds |
| Started | Aug 13 06:51:39 PM PDT 24 |
| Finished | Aug 13 06:53:07 PM PDT 24 |
| Peak memory | 573636 kb |
| Host | smart-0a5b9253-fc53-4ec0-b4c0-f8f8fdc7385e |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2080735075 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.xbar_smoke_large_delays.2080735075 |
| Directory | /workspace/18.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/18.xbar_smoke_slow_rsp.164080071 |
| Short name | T2504 |
| Test name | |
| Test status | |
| Simulation time | 5424306415 ps |
| CPU time | 88.21 seconds |
| Started | Aug 13 06:51:33 PM PDT 24 |
| Finished | Aug 13 06:53:01 PM PDT 24 |
| Peak memory | 573648 kb |
| Host | smart-02be9f2a-11af-4bd2-8bb7-7e2f1c3c874a |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=164080071 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.xbar_smoke_slow_rsp.164080071 |
| Directory | /workspace/18.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/18.xbar_smoke_zero_delays.2652688787 |
| Short name | T1553 |
| Test name | |
| Test status | |
| Simulation time | 56588556 ps |
| CPU time | 7.03 seconds |
| Started | Aug 13 06:51:34 PM PDT 24 |
| Finished | Aug 13 06:51:41 PM PDT 24 |
| Peak memory | 573596 kb |
| Host | smart-a4b1d0dd-a7ae-486d-998c-162ca47c5eb2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2652688787 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.xbar_smoke_zero_delay s.2652688787 |
| Directory | /workspace/18.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/18.xbar_stress_all.1376829432 |
| Short name | T2547 |
| Test name | |
| Test status | |
| Simulation time | 3897510500 ps |
| CPU time | 144.98 seconds |
| Started | Aug 13 06:51:37 PM PDT 24 |
| Finished | Aug 13 06:54:02 PM PDT 24 |
| Peak memory | 575740 kb |
| Host | smart-9be32599-4767-41ec-8505-b7abf834252e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1376829432 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.xbar_stress_all.1376829432 |
| Directory | /workspace/18.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/18.xbar_stress_all_with_error.2138105018 |
| Short name | T1979 |
| Test name | |
| Test status | |
| Simulation time | 6538450549 ps |
| CPU time | 226.67 seconds |
| Started | Aug 13 06:51:29 PM PDT 24 |
| Finished | Aug 13 06:55:15 PM PDT 24 |
| Peak memory | 575848 kb |
| Host | smart-bf3cb15c-353a-43ee-8002-f0de25d31580 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2138105018 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.xbar_stress_all_with_error.2138105018 |
| Directory | /workspace/18.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/18.xbar_stress_all_with_rand_reset.3542283098 |
| Short name | T1886 |
| Test name | |
| Test status | |
| Simulation time | 153039003 ps |
| CPU time | 71.26 seconds |
| Started | Aug 13 06:51:34 PM PDT 24 |
| Finished | Aug 13 06:52:46 PM PDT 24 |
| Peak memory | 576428 kb |
| Host | smart-c9a0274b-606c-44ad-a52e-cfb2b833a8dc |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3542283098 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.xbar_stress_all _with_rand_reset.3542283098 |
| Directory | /workspace/18.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/18.xbar_stress_all_with_reset_error.269518692 |
| Short name | T2258 |
| Test name | |
| Test status | |
| Simulation time | 8992403 ps |
| CPU time | 16.93 seconds |
| Started | Aug 13 06:51:28 PM PDT 24 |
| Finished | Aug 13 06:51:45 PM PDT 24 |
| Peak memory | 573656 kb |
| Host | smart-3484bb3e-43bf-44c8-9eee-2f244fc468c5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=269518692 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.xbar_stress_all _with_reset_error.269518692 |
| Directory | /workspace/18.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/18.xbar_unmapped_addr.614773898 |
| Short name | T631 |
| Test name | |
| Test status | |
| Simulation time | 305271222 ps |
| CPU time | 35.26 seconds |
| Started | Aug 13 06:51:39 PM PDT 24 |
| Finished | Aug 13 06:52:14 PM PDT 24 |
| Peak memory | 575688 kb |
| Host | smart-f8eaff92-f341-4f3b-8ea4-2a8b46c65558 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=614773898 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.xbar_unmapped_addr.614773898 |
| Directory | /workspace/18.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/19.chip_csr_mem_rw_with_rand_reset.803318341 |
| Short name | T2478 |
| Test name | |
| Test status | |
| Simulation time | 5652086914 ps |
| CPU time | 503.02 seconds |
| Started | Aug 13 06:51:32 PM PDT 24 |
| Finished | Aug 13 06:59:55 PM PDT 24 |
| Peak memory | 637652 kb |
| Host | smart-19213aa1-655f-42df-89de-0a672d66e6c7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=803318341 -assert nopostproc +U VM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top. vdb -cm_log /dev/null -cm_name 19.chip_csr_mem_rw_with_rand_reset.803318341 |
| Directory | /workspace/19.chip_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/19.chip_csr_rw.1850243510 |
| Short name | T1669 |
| Test name | |
| Test status | |
| Simulation time | 3834505050 ps |
| CPU time | 258.44 seconds |
| Started | Aug 13 06:51:36 PM PDT 24 |
| Finished | Aug 13 06:55:54 PM PDT 24 |
| Peak memory | 598744 kb |
| Host | smart-58c52cf5-31ed-4c49-85d4-b12f36419b08 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1850243510 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.chip_csr_rw.1850243510 |
| Directory | /workspace/19.chip_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/19.chip_same_csr_outstanding.2539022007 |
| Short name | T2843 |
| Test name | |
| Test status | |
| Simulation time | 28073573074 ps |
| CPU time | 3573.84 seconds |
| Started | Aug 13 06:51:32 PM PDT 24 |
| Finished | Aug 13 07:51:06 PM PDT 24 |
| Peak memory | 593056 kb |
| Host | smart-96da8e07-3c95-4a1e-93cc-94d358a11090 |
| User | root |
| Command | /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +run_same_csr_outstanding +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2539022007 -assert nopostproc +UVM_TE STNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb - cm_log /dev/null -cm_name 19.chip_same_csr_outstanding.2539022007 |
| Directory | /workspace/19.chip_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/19.xbar_access_same_device.2324509540 |
| Short name | T2645 |
| Test name | |
| Test status | |
| Simulation time | 756117797 ps |
| CPU time | 54.51 seconds |
| Started | Aug 13 06:51:36 PM PDT 24 |
| Finished | Aug 13 06:52:31 PM PDT 24 |
| Peak memory | 575672 kb |
| Host | smart-db11c25d-e350-4261-afef-be10aff078e2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2324509540 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.xbar_access_same_device .2324509540 |
| Directory | /workspace/19.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/19.xbar_access_same_device_slow_rsp.2876957374 |
| Short name | T867 |
| Test name | |
| Test status | |
| Simulation time | 92144087064 ps |
| CPU time | 1672.72 seconds |
| Started | Aug 13 06:51:32 PM PDT 24 |
| Finished | Aug 13 07:19:25 PM PDT 24 |
| Peak memory | 575752 kb |
| Host | smart-b4d23c10-cae6-48fd-8cdb-5ad585226d8b |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2876957374 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.xbar_access_same_ device_slow_rsp.2876957374 |
| Directory | /workspace/19.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/19.xbar_error_and_unmapped_addr.978180518 |
| Short name | T1532 |
| Test name | |
| Test status | |
| Simulation time | 991691823 ps |
| CPU time | 41.14 seconds |
| Started | Aug 13 06:51:41 PM PDT 24 |
| Finished | Aug 13 06:52:22 PM PDT 24 |
| Peak memory | 575704 kb |
| Host | smart-d9a223a4-d97b-47c2-845c-b1f6a972e741 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=978180518 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.xbar_error_and_unmapped_addr .978180518 |
| Directory | /workspace/19.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/19.xbar_error_random.471163419 |
| Short name | T1718 |
| Test name | |
| Test status | |
| Simulation time | 526016641 ps |
| CPU time | 44.35 seconds |
| Started | Aug 13 06:51:28 PM PDT 24 |
| Finished | Aug 13 06:52:12 PM PDT 24 |
| Peak memory | 575672 kb |
| Host | smart-1434da75-895a-4ab1-b918-460d729540cb |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=471163419 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.xbar_error_random.471163419 |
| Directory | /workspace/19.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/19.xbar_random.2336004466 |
| Short name | T479 |
| Test name | |
| Test status | |
| Simulation time | 365375535 ps |
| CPU time | 30.96 seconds |
| Started | Aug 13 06:51:28 PM PDT 24 |
| Finished | Aug 13 06:51:59 PM PDT 24 |
| Peak memory | 575620 kb |
| Host | smart-00c4aeec-5433-4ea0-9279-22de59a3a7bc |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2336004466 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.xbar_random.2336004466 |
| Directory | /workspace/19.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/19.xbar_random_large_delays.2214855381 |
| Short name | T1725 |
| Test name | |
| Test status | |
| Simulation time | 99594930426 ps |
| CPU time | 1044.81 seconds |
| Started | Aug 13 06:51:18 PM PDT 24 |
| Finished | Aug 13 07:08:43 PM PDT 24 |
| Peak memory | 575696 kb |
| Host | smart-5f137452-90eb-4633-81f4-b2f186c7a5b8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2214855381 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.xbar_random_large_delays.2214855381 |
| Directory | /workspace/19.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/19.xbar_random_slow_rsp.2909719876 |
| Short name | T2299 |
| Test name | |
| Test status | |
| Simulation time | 63472698239 ps |
| CPU time | 1001.77 seconds |
| Started | Aug 13 06:51:35 PM PDT 24 |
| Finished | Aug 13 07:08:17 PM PDT 24 |
| Peak memory | 575760 kb |
| Host | smart-efeb69ac-29a1-44c8-9da2-e46432dc6479 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2909719876 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.xbar_random_slow_rsp.2909719876 |
| Directory | /workspace/19.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/19.xbar_random_zero_delays.1797620230 |
| Short name | T1755 |
| Test name | |
| Test status | |
| Simulation time | 37967388 ps |
| CPU time | 6.05 seconds |
| Started | Aug 13 06:51:29 PM PDT 24 |
| Finished | Aug 13 06:51:36 PM PDT 24 |
| Peak memory | 573516 kb |
| Host | smart-3739b315-679f-4d7d-87db-b462bcaba2f4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1797620230 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.xbar_random_zero_del ays.1797620230 |
| Directory | /workspace/19.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/19.xbar_same_source.1370789367 |
| Short name | T1882 |
| Test name | |
| Test status | |
| Simulation time | 315878695 ps |
| CPU time | 21.49 seconds |
| Started | Aug 13 06:51:37 PM PDT 24 |
| Finished | Aug 13 06:51:58 PM PDT 24 |
| Peak memory | 575648 kb |
| Host | smart-6c845464-42ad-43a2-a6e0-44eb05f86726 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1370789367 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.xbar_same_source.1370789367 |
| Directory | /workspace/19.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/19.xbar_smoke.2090445396 |
| Short name | T1433 |
| Test name | |
| Test status | |
| Simulation time | 120409656 ps |
| CPU time | 7.01 seconds |
| Started | Aug 13 06:51:26 PM PDT 24 |
| Finished | Aug 13 06:51:33 PM PDT 24 |
| Peak memory | 573600 kb |
| Host | smart-d5a52f0f-a6aa-4be8-a934-529b37c8f097 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2090445396 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.xbar_smoke.2090445396 |
| Directory | /workspace/19.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/19.xbar_smoke_large_delays.1852866167 |
| Short name | T675 |
| Test name | |
| Test status | |
| Simulation time | 8315134844 ps |
| CPU time | 88.26 seconds |
| Started | Aug 13 06:51:41 PM PDT 24 |
| Finished | Aug 13 06:53:09 PM PDT 24 |
| Peak memory | 573516 kb |
| Host | smart-4b8d33a3-3356-4da2-800b-200eb06472b6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1852866167 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.xbar_smoke_large_delays.1852866167 |
| Directory | /workspace/19.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/19.xbar_smoke_slow_rsp.3744035795 |
| Short name | T1962 |
| Test name | |
| Test status | |
| Simulation time | 4913864505 ps |
| CPU time | 84.73 seconds |
| Started | Aug 13 06:51:41 PM PDT 24 |
| Finished | Aug 13 06:53:05 PM PDT 24 |
| Peak memory | 573624 kb |
| Host | smart-f447450d-d0ab-42ce-8a59-c80a685312d6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3744035795 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.xbar_smoke_slow_rsp.3744035795 |
| Directory | /workspace/19.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/19.xbar_smoke_zero_delays.2304396848 |
| Short name | T1643 |
| Test name | |
| Test status | |
| Simulation time | 48844996 ps |
| CPU time | 5.97 seconds |
| Started | Aug 13 06:51:39 PM PDT 24 |
| Finished | Aug 13 06:51:45 PM PDT 24 |
| Peak memory | 573476 kb |
| Host | smart-7786f656-6454-4e4e-8405-19bd2666829b |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2304396848 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.xbar_smoke_zero_delay s.2304396848 |
| Directory | /workspace/19.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/19.xbar_stress_all.784785411 |
| Short name | T493 |
| Test name | |
| Test status | |
| Simulation time | 11565109342 ps |
| CPU time | 402.75 seconds |
| Started | Aug 13 06:51:29 PM PDT 24 |
| Finished | Aug 13 06:58:12 PM PDT 24 |
| Peak memory | 576532 kb |
| Host | smart-f29f1870-c1b8-47a9-ae95-a1ae631f0940 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=784785411 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.xbar_stress_all.784785411 |
| Directory | /workspace/19.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/19.xbar_stress_all_with_error.957569584 |
| Short name | T1501 |
| Test name | |
| Test status | |
| Simulation time | 1179044958 ps |
| CPU time | 93.35 seconds |
| Started | Aug 13 06:51:40 PM PDT 24 |
| Finished | Aug 13 06:53:13 PM PDT 24 |
| Peak memory | 575592 kb |
| Host | smart-45866127-3251-4d8f-9bcf-98bc7446c1d1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=957569584 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.xbar_stress_all_with_error.957569584 |
| Directory | /workspace/19.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/19.xbar_stress_all_with_rand_reset.565563399 |
| Short name | T2572 |
| Test name | |
| Test status | |
| Simulation time | 120064320 ps |
| CPU time | 34.76 seconds |
| Started | Aug 13 06:51:27 PM PDT 24 |
| Finished | Aug 13 06:52:02 PM PDT 24 |
| Peak memory | 575648 kb |
| Host | smart-4cbbd1e7-b8fe-42fe-bff5-87404e7195a6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=565563399 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_res et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.xbar_stress_all_ with_rand_reset.565563399 |
| Directory | /workspace/19.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/19.xbar_unmapped_addr.3161527208 |
| Short name | T2714 |
| Test name | |
| Test status | |
| Simulation time | 205520842 ps |
| CPU time | 28.31 seconds |
| Started | Aug 13 06:51:24 PM PDT 24 |
| Finished | Aug 13 06:51:53 PM PDT 24 |
| Peak memory | 575656 kb |
| Host | smart-62526209-206b-406e-8816-80d01d61dc78 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3161527208 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.xbar_unmapped_addr.3161527208 |
| Directory | /workspace/19.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/2.chip_csr_aliasing.1080311814 |
| Short name | T544 |
| Test name | |
| Test status | |
| Simulation time | 38296493659 ps |
| CPU time | 6590.82 seconds |
| Started | Aug 13 06:50:32 PM PDT 24 |
| Finished | Aug 13 08:40:24 PM PDT 24 |
| Peak memory | 593636 kb |
| Host | smart-f37460fd-1c09-4239-882e-fbd05459ed8b |
| User | root |
| Command | /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +csr_aliasing +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1080311814 -assert nopostproc +UVM_TESTNAME=chip_ base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/ null -cm_name 2.chip_csr_aliasing.1080311814 |
| Directory | /workspace/2.chip_csr_aliasing/latest |
| Test location | /workspace/coverage/cover_reg_top/2.chip_csr_bit_bash.3020324586 |
| Short name | T2610 |
| Test name | |
| Test status | |
| Simulation time | 30867678600 ps |
| CPU time | 3833.71 seconds |
| Started | Aug 13 06:50:37 PM PDT 24 |
| Finished | Aug 13 07:54:32 PM PDT 24 |
| Peak memory | 590032 kb |
| Host | smart-ff25d5c6-aa92-41e5-a308-aedfcd7948e2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +num_test_csrs=200 +csr_bit_bash +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3020324586 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to p.vdb -cm_log /dev/null -cm_name 2.chip_csr_bit_bash.3020324586 |
| Directory | /workspace/2.chip_csr_bit_bash/latest |
| Test location | /workspace/coverage/cover_reg_top/2.chip_csr_mem_rw_with_rand_reset.2383811525 |
| Short name | T457 |
| Test name | |
| Test status | |
| Simulation time | 5527584850 ps |
| CPU time | 469.96 seconds |
| Started | Aug 13 06:50:52 PM PDT 24 |
| Finished | Aug 13 06:58:42 PM PDT 24 |
| Peak memory | 642232 kb |
| Host | smart-0b338520-103c-4daf-8c66-b20d19540d00 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2383811525 -assert nopostproc + UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top .vdb -cm_log /dev/null -cm_name 2.chip_csr_mem_rw_with_rand_reset.2383811525 |
| Directory | /workspace/2.chip_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/2.chip_csr_rw.4012529854 |
| Short name | T1957 |
| Test name | |
| Test status | |
| Simulation time | 5777954558 ps |
| CPU time | 579.79 seconds |
| Started | Aug 13 06:50:40 PM PDT 24 |
| Finished | Aug 13 07:00:19 PM PDT 24 |
| Peak memory | 598792 kb |
| Host | smart-e24f34f8-6980-4e33-b5b1-a5595fc6b512 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4012529854 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.chip_csr_rw.4012529854 |
| Directory | /workspace/2.chip_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/2.chip_prim_tl_access.3674943077 |
| Short name | T1719 |
| Test name | |
| Test status | |
| Simulation time | 13509961405 ps |
| CPU time | 447.78 seconds |
| Started | Aug 13 06:50:54 PM PDT 24 |
| Finished | Aug 13 06:58:22 PM PDT 24 |
| Peak memory | 590080 kb |
| Host | smart-17b20967-9d62-43ab-9f5c-c17af07f4107 |
| User | root |
| Command | /workspace/cover_reg_top/simv +en_scb=0 +en_scb_tl_err_chk=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3674943077 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SE Q=chip_prim_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.chip_prim_tl_access.3674943077 |
| Directory | /workspace/2.chip_prim_tl_access/latest |
| Test location | /workspace/coverage/cover_reg_top/2.chip_rv_dm_lc_disabled.3094889904 |
| Short name | T2195 |
| Test name | |
| Test status | |
| Simulation time | 13159144458 ps |
| CPU time | 390.22 seconds |
| Started | Aug 13 06:50:23 PM PDT 24 |
| Finished | Aug 13 06:56:53 PM PDT 24 |
| Peak memory | 591908 kb |
| Host | smart-bc24e7e6-f4ca-4beb-a9d4-eaaf4f270cea |
| User | root |
| Command | /workspace/cover_reg_top/simv +en_scb=0 +en_scb_tl_err_chk=0 +use_jtag_dmi=1 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3094889904 -assert nopostproc +UVM_TESTNAME=chip_base_t est +UVM_TEST_SEQ=chip_rv_dm_lc_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.chip_rv_dm_lc_disabled.3094889904 |
| Directory | /workspace/2.chip_rv_dm_lc_disabled/latest |
| Test location | /workspace/coverage/cover_reg_top/2.chip_same_csr_outstanding.2312584970 |
| Short name | T455 |
| Test name | |
| Test status | |
| Simulation time | 17321456688 ps |
| CPU time | 2131.96 seconds |
| Started | Aug 13 06:50:41 PM PDT 24 |
| Finished | Aug 13 07:26:14 PM PDT 24 |
| Peak memory | 592584 kb |
| Host | smart-09b8f298-9b7f-49ce-8a12-f7b4f862f40b |
| User | root |
| Command | /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +run_same_csr_outstanding +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2312584970 -assert nopostproc +UVM_TE STNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb - cm_log /dev/null -cm_name 2.chip_same_csr_outstanding.2312584970 |
| Directory | /workspace/2.chip_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/2.xbar_access_same_device.1440701888 |
| Short name | T1778 |
| Test name | |
| Test status | |
| Simulation time | 796489738 ps |
| CPU time | 33.1 seconds |
| Started | Aug 13 06:50:46 PM PDT 24 |
| Finished | Aug 13 06:51:19 PM PDT 24 |
| Peak memory | 575444 kb |
| Host | smart-f64b02d4-fd33-4490-844d-287e05b30bdd |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1440701888 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.xbar_access_same_device. 1440701888 |
| Directory | /workspace/2.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/2.xbar_access_same_device_slow_rsp.1166026061 |
| Short name | T877 |
| Test name | |
| Test status | |
| Simulation time | 90242801358 ps |
| CPU time | 1590.84 seconds |
| Started | Aug 13 06:50:51 PM PDT 24 |
| Finished | Aug 13 07:17:22 PM PDT 24 |
| Peak memory | 575632 kb |
| Host | smart-f8bad0be-a318-4f68-916d-b351096a04e4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1166026061 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.xbar_access_same_d evice_slow_rsp.1166026061 |
| Directory | /workspace/2.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/2.xbar_error_and_unmapped_addr.26477469 |
| Short name | T1727 |
| Test name | |
| Test status | |
| Simulation time | 1192611738 ps |
| CPU time | 39.62 seconds |
| Started | Aug 13 06:50:41 PM PDT 24 |
| Finished | Aug 13 06:51:21 PM PDT 24 |
| Peak memory | 575704 kb |
| Host | smart-cfad2609-7f3b-4913-b87a-9755e644bd8e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26477469 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.xbar_error_and_unmapped_addr.26477469 |
| Directory | /workspace/2.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/2.xbar_error_random.3610456021 |
| Short name | T2888 |
| Test name | |
| Test status | |
| Simulation time | 166119063 ps |
| CPU time | 15.73 seconds |
| Started | Aug 13 06:50:50 PM PDT 24 |
| Finished | Aug 13 06:51:06 PM PDT 24 |
| Peak memory | 575676 kb |
| Host | smart-3f7216ef-1332-4e43-bd26-7261aa4f48cf |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3610456021 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.xbar_error_random.3610456021 |
| Directory | /workspace/2.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/2.xbar_random.1731931898 |
| Short name | T2251 |
| Test name | |
| Test status | |
| Simulation time | 1996898982 ps |
| CPU time | 67.14 seconds |
| Started | Aug 13 06:50:37 PM PDT 24 |
| Finished | Aug 13 06:51:44 PM PDT 24 |
| Peak memory | 575664 kb |
| Host | smart-ea9b08d2-30a8-4fa4-a703-ae81b7d94581 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1731931898 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.xbar_random.1731931898 |
| Directory | /workspace/2.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/2.xbar_random_large_delays.1088795245 |
| Short name | T662 |
| Test name | |
| Test status | |
| Simulation time | 62143886707 ps |
| CPU time | 655.02 seconds |
| Started | Aug 13 06:50:39 PM PDT 24 |
| Finished | Aug 13 07:01:34 PM PDT 24 |
| Peak memory | 575748 kb |
| Host | smart-4eb73bde-2742-4527-8f1d-28908329ac7d |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1088795245 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.xbar_random_large_delays.1088795245 |
| Directory | /workspace/2.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/2.xbar_random_slow_rsp.4187881969 |
| Short name | T484 |
| Test name | |
| Test status | |
| Simulation time | 65685004991 ps |
| CPU time | 1272.54 seconds |
| Started | Aug 13 06:50:30 PM PDT 24 |
| Finished | Aug 13 07:11:43 PM PDT 24 |
| Peak memory | 575764 kb |
| Host | smart-501f64b8-e8fb-4a2c-bca5-63fe7ad8153e |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4187881969 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.xbar_random_slow_rsp.4187881969 |
| Directory | /workspace/2.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/2.xbar_random_zero_delays.523876578 |
| Short name | T588 |
| Test name | |
| Test status | |
| Simulation time | 516418606 ps |
| CPU time | 41.13 seconds |
| Started | Aug 13 06:50:46 PM PDT 24 |
| Finished | Aug 13 06:51:27 PM PDT 24 |
| Peak memory | 575540 kb |
| Host | smart-d4c5b069-e149-4d36-b21d-6c9b8387f8b3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=523876578 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.xbar_random_zero_delay s.523876578 |
| Directory | /workspace/2.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/2.xbar_same_source.312283764 |
| Short name | T496 |
| Test name | |
| Test status | |
| Simulation time | 1698433122 ps |
| CPU time | 48.69 seconds |
| Started | Aug 13 06:50:41 PM PDT 24 |
| Finished | Aug 13 06:51:30 PM PDT 24 |
| Peak memory | 575696 kb |
| Host | smart-7fee6063-f0bd-4bdb-9e82-d5e7b5cbde8d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=312283764 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.xbar_same_source.312283764 |
| Directory | /workspace/2.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/2.xbar_smoke.82854720 |
| Short name | T73 |
| Test name | |
| Test status | |
| Simulation time | 174720440 ps |
| CPU time | 7.86 seconds |
| Started | Aug 13 06:51:02 PM PDT 24 |
| Finished | Aug 13 06:51:10 PM PDT 24 |
| Peak memory | 574136 kb |
| Host | smart-5aa7bd9c-ce09-48b4-bdbb-3dbadf1d1165 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82854720 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.xbar_smoke.82854720 |
| Directory | /workspace/2.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/2.xbar_smoke_large_delays.3282904580 |
| Short name | T2282 |
| Test name | |
| Test status | |
| Simulation time | 7305880397 ps |
| CPU time | 76.48 seconds |
| Started | Aug 13 06:50:47 PM PDT 24 |
| Finished | Aug 13 06:52:03 PM PDT 24 |
| Peak memory | 573684 kb |
| Host | smart-277593d5-0818-425d-ae5e-3ec39b012f37 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3282904580 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.xbar_smoke_large_delays.3282904580 |
| Directory | /workspace/2.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/2.xbar_smoke_slow_rsp.1734610666 |
| Short name | T2086 |
| Test name | |
| Test status | |
| Simulation time | 5386282875 ps |
| CPU time | 88.86 seconds |
| Started | Aug 13 06:50:34 PM PDT 24 |
| Finished | Aug 13 06:52:03 PM PDT 24 |
| Peak memory | 574276 kb |
| Host | smart-85a86829-fbbe-4322-ad6c-8a8a7978db43 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1734610666 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.xbar_smoke_slow_rsp.1734610666 |
| Directory | /workspace/2.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/2.xbar_smoke_zero_delays.1659150193 |
| Short name | T1458 |
| Test name | |
| Test status | |
| Simulation time | 46364806 ps |
| CPU time | 5.8 seconds |
| Started | Aug 13 06:50:53 PM PDT 24 |
| Finished | Aug 13 06:50:59 PM PDT 24 |
| Peak memory | 574356 kb |
| Host | smart-92d72df5-0a82-4584-9e48-1d3cc3928ad2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1659150193 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.xbar_smoke_zero_delays .1659150193 |
| Directory | /workspace/2.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/2.xbar_stress_all.2724327859 |
| Short name | T2806 |
| Test name | |
| Test status | |
| Simulation time | 4612911780 ps |
| CPU time | 179.24 seconds |
| Started | Aug 13 06:50:57 PM PDT 24 |
| Finished | Aug 13 06:53:57 PM PDT 24 |
| Peak memory | 575712 kb |
| Host | smart-c903561e-cb2a-4fd2-80d2-e0b99c99cc79 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2724327859 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.xbar_stress_all.2724327859 |
| Directory | /workspace/2.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/2.xbar_stress_all_with_rand_reset.3065287374 |
| Short name | T2577 |
| Test name | |
| Test status | |
| Simulation time | 65955432 ps |
| CPU time | 8.54 seconds |
| Started | Aug 13 06:50:48 PM PDT 24 |
| Finished | Aug 13 06:50:57 PM PDT 24 |
| Peak memory | 573668 kb |
| Host | smart-3d06ca06-7d58-407e-af20-cb4e54cc25ee |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3065287374 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.xbar_stress_all_ with_rand_reset.3065287374 |
| Directory | /workspace/2.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/2.xbar_stress_all_with_reset_error.3053800207 |
| Short name | T2389 |
| Test name | |
| Test status | |
| Simulation time | 66711564 ps |
| CPU time | 21.49 seconds |
| Started | Aug 13 06:50:43 PM PDT 24 |
| Finished | Aug 13 06:51:05 PM PDT 24 |
| Peak memory | 575756 kb |
| Host | smart-0ac1fde4-e8bd-4753-8238-ec59ce9c6395 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3053800207 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.xbar_stress_all _with_reset_error.3053800207 |
| Directory | /workspace/2.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/2.xbar_unmapped_addr.2377344350 |
| Short name | T657 |
| Test name | |
| Test status | |
| Simulation time | 52589694 ps |
| CPU time | 8.76 seconds |
| Started | Aug 13 06:50:44 PM PDT 24 |
| Finished | Aug 13 06:50:53 PM PDT 24 |
| Peak memory | 575584 kb |
| Host | smart-4e02839b-6b7d-41c8-90d0-92290e545687 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2377344350 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.xbar_unmapped_addr.2377344350 |
| Directory | /workspace/2.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/20.chip_tl_errors.3902983215 |
| Short name | T614 |
| Test name | |
| Test status | |
| Simulation time | 3628473950 ps |
| CPU time | 149.77 seconds |
| Started | Aug 13 06:51:42 PM PDT 24 |
| Finished | Aug 13 06:54:12 PM PDT 24 |
| Peak memory | 598392 kb |
| Host | smart-dad1045a-0c82-4570-8b85-a9fe9fb79073 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3902983215 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.chip_tl_errors.3902983215 |
| Directory | /workspace/20.chip_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/20.xbar_access_same_device.2941017357 |
| Short name | T2876 |
| Test name | |
| Test status | |
| Simulation time | 1033264179 ps |
| CPU time | 82.86 seconds |
| Started | Aug 13 06:51:34 PM PDT 24 |
| Finished | Aug 13 06:52:56 PM PDT 24 |
| Peak memory | 575724 kb |
| Host | smart-78abbb4e-813c-40dd-9451-c6a2116153ca |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2941017357 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.xbar_access_same_device .2941017357 |
| Directory | /workspace/20.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/20.xbar_access_same_device_slow_rsp.77736737 |
| Short name | T2595 |
| Test name | |
| Test status | |
| Simulation time | 5398294324 ps |
| CPU time | 93.59 seconds |
| Started | Aug 13 06:51:27 PM PDT 24 |
| Finished | Aug 13 06:53:00 PM PDT 24 |
| Peak memory | 574432 kb |
| Host | smart-1ee79d33-b216-4583-9c4d-e957f5378cf2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=77736737 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.xbar_access_same_de vice_slow_rsp.77736737 |
| Directory | /workspace/20.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/20.xbar_error_and_unmapped_addr.1711251732 |
| Short name | T1628 |
| Test name | |
| Test status | |
| Simulation time | 625192304 ps |
| CPU time | 27.82 seconds |
| Started | Aug 13 06:51:37 PM PDT 24 |
| Finished | Aug 13 06:52:05 PM PDT 24 |
| Peak memory | 575492 kb |
| Host | smart-7523cf1d-e2ee-480d-ba3a-54f05ef17ba4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1711251732 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.xbar_error_and_unmapped_add r.1711251732 |
| Directory | /workspace/20.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/20.xbar_error_random.3163511723 |
| Short name | T2394 |
| Test name | |
| Test status | |
| Simulation time | 78608502 ps |
| CPU time | 8.34 seconds |
| Started | Aug 13 06:51:39 PM PDT 24 |
| Finished | Aug 13 06:51:47 PM PDT 24 |
| Peak memory | 575480 kb |
| Host | smart-6635f0de-9758-4317-b060-464c081b3c7d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3163511723 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.xbar_error_random.3163511723 |
| Directory | /workspace/20.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/20.xbar_random.2144579558 |
| Short name | T2545 |
| Test name | |
| Test status | |
| Simulation time | 581863604 ps |
| CPU time | 53.11 seconds |
| Started | Aug 13 06:51:28 PM PDT 24 |
| Finished | Aug 13 06:52:21 PM PDT 24 |
| Peak memory | 575640 kb |
| Host | smart-b79d4492-dae1-46ce-bb14-aa005d50da3f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2144579558 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.xbar_random.2144579558 |
| Directory | /workspace/20.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/20.xbar_random_large_delays.3184586800 |
| Short name | T1887 |
| Test name | |
| Test status | |
| Simulation time | 6473866868 ps |
| CPU time | 61.99 seconds |
| Started | Aug 13 06:51:41 PM PDT 24 |
| Finished | Aug 13 06:52:43 PM PDT 24 |
| Peak memory | 574276 kb |
| Host | smart-3551df22-6ef0-4a42-b138-8c9300c99ab4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3184586800 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.xbar_random_large_delays.3184586800 |
| Directory | /workspace/20.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/20.xbar_random_slow_rsp.1902415695 |
| Short name | T612 |
| Test name | |
| Test status | |
| Simulation time | 22530660550 ps |
| CPU time | 366.38 seconds |
| Started | Aug 13 06:51:32 PM PDT 24 |
| Finished | Aug 13 06:57:38 PM PDT 24 |
| Peak memory | 575776 kb |
| Host | smart-329cff5d-b841-407d-b78c-db5a870350ed |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1902415695 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.xbar_random_slow_rsp.1902415695 |
| Directory | /workspace/20.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/20.xbar_random_zero_delays.216512536 |
| Short name | T2233 |
| Test name | |
| Test status | |
| Simulation time | 364830282 ps |
| CPU time | 33.01 seconds |
| Started | Aug 13 06:51:38 PM PDT 24 |
| Finished | Aug 13 06:52:11 PM PDT 24 |
| Peak memory | 575644 kb |
| Host | smart-0f842520-2378-48f8-8ae6-d5ffeed246f9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=216512536 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.xbar_random_zero_dela ys.216512536 |
| Directory | /workspace/20.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/20.xbar_same_source.1914813306 |
| Short name | T2803 |
| Test name | |
| Test status | |
| Simulation time | 2667230804 ps |
| CPU time | 78.38 seconds |
| Started | Aug 13 06:51:40 PM PDT 24 |
| Finished | Aug 13 06:52:58 PM PDT 24 |
| Peak memory | 575736 kb |
| Host | smart-609d7274-a60d-4b00-92a3-3c1bce893eed |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1914813306 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.xbar_same_source.1914813306 |
| Directory | /workspace/20.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/20.xbar_smoke.1507769485 |
| Short name | T2130 |
| Test name | |
| Test status | |
| Simulation time | 58022755 ps |
| CPU time | 6.77 seconds |
| Started | Aug 13 06:51:30 PM PDT 24 |
| Finished | Aug 13 06:51:36 PM PDT 24 |
| Peak memory | 573528 kb |
| Host | smart-cede8d2b-8c1b-4710-8a73-1fa04af8be7d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1507769485 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.xbar_smoke.1507769485 |
| Directory | /workspace/20.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/20.xbar_smoke_large_delays.3993107139 |
| Short name | T2937 |
| Test name | |
| Test status | |
| Simulation time | 6008936283 ps |
| CPU time | 59.07 seconds |
| Started | Aug 13 06:51:29 PM PDT 24 |
| Finished | Aug 13 06:52:29 PM PDT 24 |
| Peak memory | 574328 kb |
| Host | smart-dfd7a2cd-ae95-427a-89cf-ea85b549ba00 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3993107139 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.xbar_smoke_large_delays.3993107139 |
| Directory | /workspace/20.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/20.xbar_smoke_slow_rsp.3149974533 |
| Short name | T2150 |
| Test name | |
| Test status | |
| Simulation time | 4977993019 ps |
| CPU time | 83.28 seconds |
| Started | Aug 13 06:51:37 PM PDT 24 |
| Finished | Aug 13 06:53:00 PM PDT 24 |
| Peak memory | 573668 kb |
| Host | smart-61b2f18b-5ee7-482d-ac10-2936c2889c79 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3149974533 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.xbar_smoke_slow_rsp.3149974533 |
| Directory | /workspace/20.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/20.xbar_smoke_zero_delays.4110194077 |
| Short name | T2329 |
| Test name | |
| Test status | |
| Simulation time | 45480362 ps |
| CPU time | 6.19 seconds |
| Started | Aug 13 06:51:40 PM PDT 24 |
| Finished | Aug 13 06:51:47 PM PDT 24 |
| Peak memory | 574232 kb |
| Host | smart-ae2f5dbd-44eb-4724-abd7-cca895aa4558 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4110194077 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.xbar_smoke_zero_delay s.4110194077 |
| Directory | /workspace/20.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/20.xbar_stress_all.676611024 |
| Short name | T1678 |
| Test name | |
| Test status | |
| Simulation time | 2575053895 ps |
| CPU time | 78.73 seconds |
| Started | Aug 13 06:51:38 PM PDT 24 |
| Finished | Aug 13 06:52:57 PM PDT 24 |
| Peak memory | 575520 kb |
| Host | smart-6ecfe8a1-4dba-470d-bb37-3c04af398a67 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=676611024 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.xbar_stress_all.676611024 |
| Directory | /workspace/20.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/20.xbar_stress_all_with_error.316956665 |
| Short name | T1829 |
| Test name | |
| Test status | |
| Simulation time | 2306686816 ps |
| CPU time | 73.89 seconds |
| Started | Aug 13 06:51:38 PM PDT 24 |
| Finished | Aug 13 06:52:52 PM PDT 24 |
| Peak memory | 575568 kb |
| Host | smart-21066715-aa62-4448-96af-2ddf52f5f34c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=316956665 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.xbar_stress_all_with_error.316956665 |
| Directory | /workspace/20.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/20.xbar_stress_all_with_rand_reset.86358402 |
| Short name | T2915 |
| Test name | |
| Test status | |
| Simulation time | 448614283 ps |
| CPU time | 189.94 seconds |
| Started | Aug 13 06:51:41 PM PDT 24 |
| Finished | Aug 13 06:54:51 PM PDT 24 |
| Peak memory | 576468 kb |
| Host | smart-0962fca7-85c5-4fb1-99be-b767a65797ef |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86358402 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_rese t_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.xbar_stress_all_w ith_rand_reset.86358402 |
| Directory | /workspace/20.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/20.xbar_stress_all_with_reset_error.2097850560 |
| Short name | T1951 |
| Test name | |
| Test status | |
| Simulation time | 2227706394 ps |
| CPU time | 260.03 seconds |
| Started | Aug 13 06:51:32 PM PDT 24 |
| Finished | Aug 13 06:55:52 PM PDT 24 |
| Peak memory | 576564 kb |
| Host | smart-f4a69af4-3d40-48a9-aff1-dec943b76653 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2097850560 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.xbar_stress_al l_with_reset_error.2097850560 |
| Directory | /workspace/20.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/20.xbar_unmapped_addr.2873179667 |
| Short name | T2702 |
| Test name | |
| Test status | |
| Simulation time | 20381308 ps |
| CPU time | 5.83 seconds |
| Started | Aug 13 06:51:39 PM PDT 24 |
| Finished | Aug 13 06:51:45 PM PDT 24 |
| Peak memory | 573592 kb |
| Host | smart-362d0b31-d06b-4c3d-9ca7-1ad6f8079913 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2873179667 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.xbar_unmapped_addr.2873179667 |
| Directory | /workspace/20.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/21.chip_tl_errors.4264252400 |
| Short name | T565 |
| Test name | |
| Test status | |
| Simulation time | 4348387326 ps |
| CPU time | 345.89 seconds |
| Started | Aug 13 06:51:37 PM PDT 24 |
| Finished | Aug 13 06:57:23 PM PDT 24 |
| Peak memory | 598380 kb |
| Host | smart-8c9225fa-ea65-4a75-bfab-25b95e6571ad |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4264252400 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.chip_tl_errors.4264252400 |
| Directory | /workspace/21.chip_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/21.xbar_access_same_device.4052452079 |
| Short name | T2851 |
| Test name | |
| Test status | |
| Simulation time | 1265768878 ps |
| CPU time | 56.58 seconds |
| Started | Aug 13 06:51:34 PM PDT 24 |
| Finished | Aug 13 06:52:31 PM PDT 24 |
| Peak memory | 575528 kb |
| Host | smart-028bbb11-58b6-4504-9af4-1c63282ec8e5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4052452079 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.xbar_access_same_device .4052452079 |
| Directory | /workspace/21.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/21.xbar_access_same_device_slow_rsp.4290101817 |
| Short name | T2318 |
| Test name | |
| Test status | |
| Simulation time | 13598065680 ps |
| CPU time | 230.21 seconds |
| Started | Aug 13 06:51:41 PM PDT 24 |
| Finished | Aug 13 06:55:31 PM PDT 24 |
| Peak memory | 575696 kb |
| Host | smart-4f6db33c-cdc1-4ae3-9c8c-57e83f64e67c |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4290101817 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.xbar_access_same_ device_slow_rsp.4290101817 |
| Directory | /workspace/21.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/21.xbar_error_and_unmapped_addr.161263066 |
| Short name | T2006 |
| Test name | |
| Test status | |
| Simulation time | 732609752 ps |
| CPU time | 25.29 seconds |
| Started | Aug 13 06:51:50 PM PDT 24 |
| Finished | Aug 13 06:52:15 PM PDT 24 |
| Peak memory | 575512 kb |
| Host | smart-eae76db9-8226-415e-b035-e6bb1fd764f7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=161263066 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.xbar_error_and_unmapped_addr .161263066 |
| Directory | /workspace/21.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/21.xbar_error_random.113394216 |
| Short name | T1624 |
| Test name | |
| Test status | |
| Simulation time | 560693199 ps |
| CPU time | 45.25 seconds |
| Started | Aug 13 06:51:37 PM PDT 24 |
| Finished | Aug 13 06:52:23 PM PDT 24 |
| Peak memory | 575700 kb |
| Host | smart-e3d36617-66c2-452c-a3e2-81af6e0805b9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=113394216 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.xbar_error_random.113394216 |
| Directory | /workspace/21.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/21.xbar_random.1128452452 |
| Short name | T1609 |
| Test name | |
| Test status | |
| Simulation time | 561518175 ps |
| CPU time | 50.09 seconds |
| Started | Aug 13 06:51:35 PM PDT 24 |
| Finished | Aug 13 06:52:25 PM PDT 24 |
| Peak memory | 575528 kb |
| Host | smart-994ef16d-08d8-420f-86c7-7a11891f078a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1128452452 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.xbar_random.1128452452 |
| Directory | /workspace/21.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/21.xbar_random_large_delays.2809871532 |
| Short name | T2696 |
| Test name | |
| Test status | |
| Simulation time | 116244430332 ps |
| CPU time | 1278.07 seconds |
| Started | Aug 13 06:51:38 PM PDT 24 |
| Finished | Aug 13 07:12:56 PM PDT 24 |
| Peak memory | 575804 kb |
| Host | smart-e8040172-e1e4-491e-ab6a-5c84a9d86909 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2809871532 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.xbar_random_large_delays.2809871532 |
| Directory | /workspace/21.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/21.xbar_random_slow_rsp.1393013362 |
| Short name | T1474 |
| Test name | |
| Test status | |
| Simulation time | 12950367621 ps |
| CPU time | 221.58 seconds |
| Started | Aug 13 06:51:32 PM PDT 24 |
| Finished | Aug 13 06:55:14 PM PDT 24 |
| Peak memory | 575740 kb |
| Host | smart-31a68650-c34e-4c4f-94d8-0055cd684437 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1393013362 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.xbar_random_slow_rsp.1393013362 |
| Directory | /workspace/21.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/21.xbar_random_zero_delays.4265863149 |
| Short name | T2336 |
| Test name | |
| Test status | |
| Simulation time | 156244835 ps |
| CPU time | 13.72 seconds |
| Started | Aug 13 06:51:43 PM PDT 24 |
| Finished | Aug 13 06:51:57 PM PDT 24 |
| Peak memory | 575656 kb |
| Host | smart-21408994-2791-4333-82c1-ff5754975ec7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4265863149 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.xbar_random_zero_del ays.4265863149 |
| Directory | /workspace/21.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/21.xbar_same_source.2418461728 |
| Short name | T660 |
| Test name | |
| Test status | |
| Simulation time | 1318316762 ps |
| CPU time | 35.76 seconds |
| Started | Aug 13 06:51:40 PM PDT 24 |
| Finished | Aug 13 06:52:16 PM PDT 24 |
| Peak memory | 575644 kb |
| Host | smart-01fda1b3-3f53-4a11-874d-4167aa69edc6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2418461728 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.xbar_same_source.2418461728 |
| Directory | /workspace/21.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/21.xbar_smoke.3074848222 |
| Short name | T2698 |
| Test name | |
| Test status | |
| Simulation time | 42048127 ps |
| CPU time | 6.3 seconds |
| Started | Aug 13 06:51:36 PM PDT 24 |
| Finished | Aug 13 06:51:42 PM PDT 24 |
| Peak memory | 574248 kb |
| Host | smart-045d5914-cb43-4e97-b569-05841cae1c2d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3074848222 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.xbar_smoke.3074848222 |
| Directory | /workspace/21.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/21.xbar_smoke_large_delays.1693108506 |
| Short name | T2812 |
| Test name | |
| Test status | |
| Simulation time | 7006053980 ps |
| CPU time | 72.38 seconds |
| Started | Aug 13 06:51:36 PM PDT 24 |
| Finished | Aug 13 06:52:48 PM PDT 24 |
| Peak memory | 573620 kb |
| Host | smart-21390a4f-54a9-406e-a733-9a2fb1440fa3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1693108506 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.xbar_smoke_large_delays.1693108506 |
| Directory | /workspace/21.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/21.xbar_smoke_slow_rsp.1797564668 |
| Short name | T2103 |
| Test name | |
| Test status | |
| Simulation time | 6189645835 ps |
| CPU time | 100.67 seconds |
| Started | Aug 13 06:51:39 PM PDT 24 |
| Finished | Aug 13 06:53:19 PM PDT 24 |
| Peak memory | 573688 kb |
| Host | smart-c01ee7f5-a8a7-4c3c-94f7-b29b12ed57c1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1797564668 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.xbar_smoke_slow_rsp.1797564668 |
| Directory | /workspace/21.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/21.xbar_smoke_zero_delays.3859836140 |
| Short name | T2574 |
| Test name | |
| Test status | |
| Simulation time | 45819891 ps |
| CPU time | 6.25 seconds |
| Started | Aug 13 06:51:42 PM PDT 24 |
| Finished | Aug 13 06:51:48 PM PDT 24 |
| Peak memory | 574252 kb |
| Host | smart-7f805406-bb46-4f3b-b482-cd63bcda09a7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3859836140 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.xbar_smoke_zero_delay s.3859836140 |
| Directory | /workspace/21.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/21.xbar_stress_all.752337947 |
| Short name | T532 |
| Test name | |
| Test status | |
| Simulation time | 10941830719 ps |
| CPU time | 361.42 seconds |
| Started | Aug 13 06:51:41 PM PDT 24 |
| Finished | Aug 13 06:57:43 PM PDT 24 |
| Peak memory | 575708 kb |
| Host | smart-085faa38-8cba-44f7-ae35-a87385b5b96f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=752337947 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.xbar_stress_all.752337947 |
| Directory | /workspace/21.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/21.xbar_stress_all_with_error.2971459313 |
| Short name | T2682 |
| Test name | |
| Test status | |
| Simulation time | 329836848 ps |
| CPU time | 32.12 seconds |
| Started | Aug 13 06:51:44 PM PDT 24 |
| Finished | Aug 13 06:52:16 PM PDT 24 |
| Peak memory | 575552 kb |
| Host | smart-3b18580b-b06b-4eb3-9456-16335aadd247 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2971459313 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.xbar_stress_all_with_error.2971459313 |
| Directory | /workspace/21.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/21.xbar_stress_all_with_rand_reset.2674149319 |
| Short name | T2517 |
| Test name | |
| Test status | |
| Simulation time | 1752608673 ps |
| CPU time | 273.98 seconds |
| Started | Aug 13 06:51:57 PM PDT 24 |
| Finished | Aug 13 06:56:31 PM PDT 24 |
| Peak memory | 575716 kb |
| Host | smart-ebb3285d-850d-461f-94e9-cc13662d0a2f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2674149319 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.xbar_stress_all _with_rand_reset.2674149319 |
| Directory | /workspace/21.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/21.xbar_unmapped_addr.330725908 |
| Short name | T2816 |
| Test name | |
| Test status | |
| Simulation time | 401026438 ps |
| CPU time | 19.31 seconds |
| Started | Aug 13 06:51:50 PM PDT 24 |
| Finished | Aug 13 06:52:09 PM PDT 24 |
| Peak memory | 575748 kb |
| Host | smart-c3f0d68c-300b-4338-8cbe-801aac3ee040 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=330725908 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.xbar_unmapped_addr.330725908 |
| Directory | /workspace/21.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/22.chip_tl_errors.205861433 |
| Short name | T753 |
| Test name | |
| Test status | |
| Simulation time | 4074764790 ps |
| CPU time | 295.2 seconds |
| Started | Aug 13 06:51:45 PM PDT 24 |
| Finished | Aug 13 06:56:41 PM PDT 24 |
| Peak memory | 603376 kb |
| Host | smart-409e2370-732e-4cb0-a1a0-05b47393df89 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=205861433 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.chip_tl_errors.205861433 |
| Directory | /workspace/22.chip_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/22.xbar_access_same_device.4007407801 |
| Short name | T1443 |
| Test name | |
| Test status | |
| Simulation time | 80482114 ps |
| CPU time | 17.68 seconds |
| Started | Aug 13 06:51:47 PM PDT 24 |
| Finished | Aug 13 06:52:05 PM PDT 24 |
| Peak memory | 575516 kb |
| Host | smart-d3f85644-94f4-4bf0-ad68-88f592ecd0dd |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4007407801 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.xbar_access_same_device .4007407801 |
| Directory | /workspace/22.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/22.xbar_access_same_device_slow_rsp.2215870794 |
| Short name | T1844 |
| Test name | |
| Test status | |
| Simulation time | 155417246821 ps |
| CPU time | 2674.55 seconds |
| Started | Aug 13 06:51:48 PM PDT 24 |
| Finished | Aug 13 07:36:23 PM PDT 24 |
| Peak memory | 575656 kb |
| Host | smart-08dcf0dc-7be9-4d86-b154-64c49ab0bb58 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2215870794 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.xbar_access_same_ device_slow_rsp.2215870794 |
| Directory | /workspace/22.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/22.xbar_error_and_unmapped_addr.527959936 |
| Short name | T2020 |
| Test name | |
| Test status | |
| Simulation time | 314215723 ps |
| CPU time | 31.09 seconds |
| Started | Aug 13 06:51:55 PM PDT 24 |
| Finished | Aug 13 06:52:26 PM PDT 24 |
| Peak memory | 575632 kb |
| Host | smart-ba012cc0-a827-49ce-bb66-459346cdbf9a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=527959936 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.xbar_error_and_unmapped_addr .527959936 |
| Directory | /workspace/22.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/22.xbar_error_random.1281922446 |
| Short name | T1445 |
| Test name | |
| Test status | |
| Simulation time | 354036573 ps |
| CPU time | 30.9 seconds |
| Started | Aug 13 06:51:56 PM PDT 24 |
| Finished | Aug 13 06:52:27 PM PDT 24 |
| Peak memory | 575708 kb |
| Host | smart-c83784b3-99d7-43c1-b75b-b6c58aa81b3b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1281922446 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.xbar_error_random.1281922446 |
| Directory | /workspace/22.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/22.xbar_random.709735884 |
| Short name | T2074 |
| Test name | |
| Test status | |
| Simulation time | 2046640924 ps |
| CPU time | 78.49 seconds |
| Started | Aug 13 06:51:50 PM PDT 24 |
| Finished | Aug 13 06:53:08 PM PDT 24 |
| Peak memory | 575548 kb |
| Host | smart-122b92d7-2a3a-4d29-b26d-28a23bcec691 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=709735884 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.xbar_random.709735884 |
| Directory | /workspace/22.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/22.xbar_random_large_delays.3508853886 |
| Short name | T2271 |
| Test name | |
| Test status | |
| Simulation time | 62460515807 ps |
| CPU time | 670.99 seconds |
| Started | Aug 13 06:51:59 PM PDT 24 |
| Finished | Aug 13 07:03:10 PM PDT 24 |
| Peak memory | 575720 kb |
| Host | smart-4e82f709-4725-41fc-b2c4-835cbb9630cb |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3508853886 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.xbar_random_large_delays.3508853886 |
| Directory | /workspace/22.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/22.xbar_random_slow_rsp.2601595724 |
| Short name | T1978 |
| Test name | |
| Test status | |
| Simulation time | 51453734852 ps |
| CPU time | 876.52 seconds |
| Started | Aug 13 06:51:54 PM PDT 24 |
| Finished | Aug 13 07:06:30 PM PDT 24 |
| Peak memory | 575792 kb |
| Host | smart-8f2b69b5-6596-450a-8632-dbe03ab33cb8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2601595724 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.xbar_random_slow_rsp.2601595724 |
| Directory | /workspace/22.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/22.xbar_random_zero_delays.1409530709 |
| Short name | T1672 |
| Test name | |
| Test status | |
| Simulation time | 28935291 ps |
| CPU time | 5.61 seconds |
| Started | Aug 13 06:52:00 PM PDT 24 |
| Finished | Aug 13 06:52:06 PM PDT 24 |
| Peak memory | 573600 kb |
| Host | smart-d5df0a87-a7ab-43f0-959b-c67527f27424 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1409530709 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.xbar_random_zero_del ays.1409530709 |
| Directory | /workspace/22.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/22.xbar_same_source.2608806907 |
| Short name | T2599 |
| Test name | |
| Test status | |
| Simulation time | 1846031936 ps |
| CPU time | 47.58 seconds |
| Started | Aug 13 06:51:54 PM PDT 24 |
| Finished | Aug 13 06:52:42 PM PDT 24 |
| Peak memory | 575648 kb |
| Host | smart-a6731628-acc9-4d11-a6b4-d18c2a521390 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2608806907 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.xbar_same_source.2608806907 |
| Directory | /workspace/22.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/22.xbar_smoke.699569833 |
| Short name | T1469 |
| Test name | |
| Test status | |
| Simulation time | 40384760 ps |
| CPU time | 6.24 seconds |
| Started | Aug 13 06:51:45 PM PDT 24 |
| Finished | Aug 13 06:51:51 PM PDT 24 |
| Peak memory | 573532 kb |
| Host | smart-46567ced-e834-4d92-ab7b-01cdbdf4850e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=699569833 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.xbar_smoke.699569833 |
| Directory | /workspace/22.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/22.xbar_smoke_large_delays.1062489344 |
| Short name | T2552 |
| Test name | |
| Test status | |
| Simulation time | 7628481263 ps |
| CPU time | 81.65 seconds |
| Started | Aug 13 06:51:49 PM PDT 24 |
| Finished | Aug 13 06:53:11 PM PDT 24 |
| Peak memory | 573688 kb |
| Host | smart-5b40584b-08f0-4ba0-8736-eacbf3cc286a |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1062489344 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.xbar_smoke_large_delays.1062489344 |
| Directory | /workspace/22.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/22.xbar_smoke_slow_rsp.4227049846 |
| Short name | T2472 |
| Test name | |
| Test status | |
| Simulation time | 4975318937 ps |
| CPU time | 83.71 seconds |
| Started | Aug 13 06:51:44 PM PDT 24 |
| Finished | Aug 13 06:53:07 PM PDT 24 |
| Peak memory | 573628 kb |
| Host | smart-2f9d1a84-9dd2-4982-826b-de335e1f5942 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4227049846 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.xbar_smoke_slow_rsp.4227049846 |
| Directory | /workspace/22.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/22.xbar_smoke_zero_delays.4350476 |
| Short name | T1662 |
| Test name | |
| Test status | |
| Simulation time | 50173501 ps |
| CPU time | 6.88 seconds |
| Started | Aug 13 06:51:49 PM PDT 24 |
| Finished | Aug 13 06:51:56 PM PDT 24 |
| Peak memory | 574228 kb |
| Host | smart-309df94d-1571-4c0f-8e23-c4d63622840c |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4350476 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.xbar_smoke_zero_delays.4350476 |
| Directory | /workspace/22.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/22.xbar_stress_all.2129647938 |
| Short name | T480 |
| Test name | |
| Test status | |
| Simulation time | 12300459036 ps |
| CPU time | 486.68 seconds |
| Started | Aug 13 06:51:55 PM PDT 24 |
| Finished | Aug 13 07:00:02 PM PDT 24 |
| Peak memory | 576564 kb |
| Host | smart-b3c1bcdc-6f7a-4eb1-9bb6-2cd9e8d9fe0d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2129647938 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.xbar_stress_all.2129647938 |
| Directory | /workspace/22.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/22.xbar_stress_all_with_rand_reset.2446485375 |
| Short name | T646 |
| Test name | |
| Test status | |
| Simulation time | 3950932020 ps |
| CPU time | 272.01 seconds |
| Started | Aug 13 06:51:55 PM PDT 24 |
| Finished | Aug 13 06:56:28 PM PDT 24 |
| Peak memory | 575708 kb |
| Host | smart-e82ef73f-7997-4214-a0d9-2f048c3c5b2f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2446485375 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.xbar_stress_all _with_rand_reset.2446485375 |
| Directory | /workspace/22.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/22.xbar_stress_all_with_reset_error.3876385093 |
| Short name | T2630 |
| Test name | |
| Test status | |
| Simulation time | 144905189 ps |
| CPU time | 41.9 seconds |
| Started | Aug 13 06:52:09 PM PDT 24 |
| Finished | Aug 13 06:52:50 PM PDT 24 |
| Peak memory | 576284 kb |
| Host | smart-ef41a6b8-36ef-4148-97f4-643648c8547f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3876385093 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.xbar_stress_al l_with_reset_error.3876385093 |
| Directory | /workspace/22.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/22.xbar_unmapped_addr.2547511115 |
| Short name | T1743 |
| Test name | |
| Test status | |
| Simulation time | 24099714 ps |
| CPU time | 5.83 seconds |
| Started | Aug 13 06:51:56 PM PDT 24 |
| Finished | Aug 13 06:52:02 PM PDT 24 |
| Peak memory | 573648 kb |
| Host | smart-b4a96814-cb35-4d71-823d-f34e3e02713e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2547511115 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.xbar_unmapped_addr.2547511115 |
| Directory | /workspace/22.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/23.xbar_access_same_device.3388191579 |
| Short name | T2398 |
| Test name | |
| Test status | |
| Simulation time | 766408330 ps |
| CPU time | 64.93 seconds |
| Started | Aug 13 06:51:58 PM PDT 24 |
| Finished | Aug 13 06:53:03 PM PDT 24 |
| Peak memory | 575492 kb |
| Host | smart-8ad1dc4f-8fac-4c34-8913-41e383502f2f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3388191579 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.xbar_access_same_device .3388191579 |
| Directory | /workspace/23.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/23.xbar_access_same_device_slow_rsp.4043069090 |
| Short name | T1813 |
| Test name | |
| Test status | |
| Simulation time | 90039864985 ps |
| CPU time | 1811.36 seconds |
| Started | Aug 13 06:51:58 PM PDT 24 |
| Finished | Aug 13 07:22:10 PM PDT 24 |
| Peak memory | 575852 kb |
| Host | smart-3a17fa99-9504-4b3e-abf5-42590eadb2e1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4043069090 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.xbar_access_same_ device_slow_rsp.4043069090 |
| Directory | /workspace/23.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/23.xbar_error_and_unmapped_addr.3663571754 |
| Short name | T1646 |
| Test name | |
| Test status | |
| Simulation time | 395682423 ps |
| CPU time | 16.29 seconds |
| Started | Aug 13 06:52:05 PM PDT 24 |
| Finished | Aug 13 06:52:22 PM PDT 24 |
| Peak memory | 575848 kb |
| Host | smart-cacda044-ee69-4b43-9378-6a4fbb4ff3b4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3663571754 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.xbar_error_and_unmapped_add r.3663571754 |
| Directory | /workspace/23.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/23.xbar_error_random.2966915764 |
| Short name | T1663 |
| Test name | |
| Test status | |
| Simulation time | 2343042697 ps |
| CPU time | 87.28 seconds |
| Started | Aug 13 06:52:02 PM PDT 24 |
| Finished | Aug 13 06:53:29 PM PDT 24 |
| Peak memory | 575552 kb |
| Host | smart-3ee597e0-83ae-475e-a562-d9248ffa2f5a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2966915764 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.xbar_error_random.2966915764 |
| Directory | /workspace/23.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/23.xbar_random.1473165179 |
| Short name | T1683 |
| Test name | |
| Test status | |
| Simulation time | 431368455 ps |
| CPU time | 17.48 seconds |
| Started | Aug 13 06:51:56 PM PDT 24 |
| Finished | Aug 13 06:52:13 PM PDT 24 |
| Peak memory | 575616 kb |
| Host | smart-6a10e6ca-3513-4796-932d-22a0983e1b31 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1473165179 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.xbar_random.1473165179 |
| Directory | /workspace/23.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/23.xbar_random_large_delays.722840765 |
| Short name | T692 |
| Test name | |
| Test status | |
| Simulation time | 87215858059 ps |
| CPU time | 922.49 seconds |
| Started | Aug 13 06:51:57 PM PDT 24 |
| Finished | Aug 13 07:07:20 PM PDT 24 |
| Peak memory | 575732 kb |
| Host | smart-fc3cfde5-71c5-48a1-ae27-9cdbc06a7bba |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=722840765 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.xbar_random_large_delays.722840765 |
| Directory | /workspace/23.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/23.xbar_random_slow_rsp.3591829808 |
| Short name | T2341 |
| Test name | |
| Test status | |
| Simulation time | 7076675784 ps |
| CPU time | 127.76 seconds |
| Started | Aug 13 06:52:06 PM PDT 24 |
| Finished | Aug 13 06:54:14 PM PDT 24 |
| Peak memory | 575740 kb |
| Host | smart-7f4c9ad4-391d-46ed-9995-9f1077f45e3b |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3591829808 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.xbar_random_slow_rsp.3591829808 |
| Directory | /workspace/23.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/23.xbar_random_zero_delays.980878508 |
| Short name | T1864 |
| Test name | |
| Test status | |
| Simulation time | 572146438 ps |
| CPU time | 48.09 seconds |
| Started | Aug 13 06:52:00 PM PDT 24 |
| Finished | Aug 13 06:52:48 PM PDT 24 |
| Peak memory | 575612 kb |
| Host | smart-914138a6-7b58-402f-aba9-0ef79cc8fa86 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=980878508 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.xbar_random_zero_dela ys.980878508 |
| Directory | /workspace/23.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/23.xbar_same_source.347793709 |
| Short name | T2448 |
| Test name | |
| Test status | |
| Simulation time | 475600361 ps |
| CPU time | 18.14 seconds |
| Started | Aug 13 06:52:03 PM PDT 24 |
| Finished | Aug 13 06:52:21 PM PDT 24 |
| Peak memory | 575464 kb |
| Host | smart-659a0abd-d63b-42e1-8823-a24568c5cb73 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=347793709 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.xbar_same_source.347793709 |
| Directory | /workspace/23.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/23.xbar_smoke.1778247913 |
| Short name | T2023 |
| Test name | |
| Test status | |
| Simulation time | 54750214 ps |
| CPU time | 7.2 seconds |
| Started | Aug 13 06:51:55 PM PDT 24 |
| Finished | Aug 13 06:52:03 PM PDT 24 |
| Peak memory | 574244 kb |
| Host | smart-63009d03-ac49-4bcf-af13-4714b6cb5a63 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1778247913 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.xbar_smoke.1778247913 |
| Directory | /workspace/23.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/23.xbar_smoke_large_delays.2440000056 |
| Short name | T2637 |
| Test name | |
| Test status | |
| Simulation time | 6174355670 ps |
| CPU time | 64.69 seconds |
| Started | Aug 13 06:51:56 PM PDT 24 |
| Finished | Aug 13 06:53:00 PM PDT 24 |
| Peak memory | 573676 kb |
| Host | smart-1dfc78ee-7125-487f-bdab-0cc2fba78807 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2440000056 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.xbar_smoke_large_delays.2440000056 |
| Directory | /workspace/23.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/23.xbar_smoke_slow_rsp.824912567 |
| Short name | T2460 |
| Test name | |
| Test status | |
| Simulation time | 2886283169 ps |
| CPU time | 50.81 seconds |
| Started | Aug 13 06:51:58 PM PDT 24 |
| Finished | Aug 13 06:52:49 PM PDT 24 |
| Peak memory | 574296 kb |
| Host | smart-6f6e7620-d4e7-40c7-ab82-9f19e06be139 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=824912567 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.xbar_smoke_slow_rsp.824912567 |
| Directory | /workspace/23.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/23.xbar_smoke_zero_delays.3997101946 |
| Short name | T2616 |
| Test name | |
| Test status | |
| Simulation time | 53682826 ps |
| CPU time | 7.37 seconds |
| Started | Aug 13 06:51:56 PM PDT 24 |
| Finished | Aug 13 06:52:03 PM PDT 24 |
| Peak memory | 574228 kb |
| Host | smart-7c271a68-a070-4c1e-894b-070fdd882f7b |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3997101946 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.xbar_smoke_zero_delay s.3997101946 |
| Directory | /workspace/23.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/23.xbar_stress_all.390267928 |
| Short name | T703 |
| Test name | |
| Test status | |
| Simulation time | 9774575754 ps |
| CPU time | 350.31 seconds |
| Started | Aug 13 06:52:04 PM PDT 24 |
| Finished | Aug 13 06:57:55 PM PDT 24 |
| Peak memory | 575636 kb |
| Host | smart-10520a11-16b8-4278-bd9a-5092f828bb54 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=390267928 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.xbar_stress_all.390267928 |
| Directory | /workspace/23.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/23.xbar_stress_all_with_error.2011526214 |
| Short name | T1761 |
| Test name | |
| Test status | |
| Simulation time | 12351498841 ps |
| CPU time | 404.88 seconds |
| Started | Aug 13 06:52:04 PM PDT 24 |
| Finished | Aug 13 06:58:49 PM PDT 24 |
| Peak memory | 576512 kb |
| Host | smart-d1f28436-4845-4f79-8be1-479d517e31b4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2011526214 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.xbar_stress_all_with_error.2011526214 |
| Directory | /workspace/23.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/23.xbar_stress_all_with_rand_reset.728507551 |
| Short name | T2636 |
| Test name | |
| Test status | |
| Simulation time | 6068268620 ps |
| CPU time | 371.48 seconds |
| Started | Aug 13 06:52:04 PM PDT 24 |
| Finished | Aug 13 06:58:16 PM PDT 24 |
| Peak memory | 576556 kb |
| Host | smart-bb32f15f-5b58-4d27-b933-a8c0874851d5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=728507551 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_res et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.xbar_stress_all_ with_rand_reset.728507551 |
| Directory | /workspace/23.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/23.xbar_stress_all_with_reset_error.1887920124 |
| Short name | T2852 |
| Test name | |
| Test status | |
| Simulation time | 2567220764 ps |
| CPU time | 332.05 seconds |
| Started | Aug 13 06:52:05 PM PDT 24 |
| Finished | Aug 13 06:57:38 PM PDT 24 |
| Peak memory | 576576 kb |
| Host | smart-554462ea-fef8-49e2-bd33-fd62c3e3b1eb |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1887920124 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.xbar_stress_al l_with_reset_error.1887920124 |
| Directory | /workspace/23.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/23.xbar_unmapped_addr.683033191 |
| Short name | T2834 |
| Test name | |
| Test status | |
| Simulation time | 915969396 ps |
| CPU time | 37.13 seconds |
| Started | Aug 13 06:52:11 PM PDT 24 |
| Finished | Aug 13 06:52:48 PM PDT 24 |
| Peak memory | 575728 kb |
| Host | smart-234abd75-f760-430e-a98e-ec70bc14a8ee |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=683033191 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.xbar_unmapped_addr.683033191 |
| Directory | /workspace/23.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/24.chip_tl_errors.317467443 |
| Short name | T569 |
| Test name | |
| Test status | |
| Simulation time | 3541851152 ps |
| CPU time | 215.95 seconds |
| Started | Aug 13 06:52:04 PM PDT 24 |
| Finished | Aug 13 06:55:40 PM PDT 24 |
| Peak memory | 603500 kb |
| Host | smart-18fafc64-58c5-4e8b-a908-f901da05c740 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=317467443 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.chip_tl_errors.317467443 |
| Directory | /workspace/24.chip_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/24.xbar_access_same_device.4205940219 |
| Short name | T2822 |
| Test name | |
| Test status | |
| Simulation time | 1688694709 ps |
| CPU time | 79.6 seconds |
| Started | Aug 13 06:52:11 PM PDT 24 |
| Finished | Aug 13 06:53:31 PM PDT 24 |
| Peak memory | 576356 kb |
| Host | smart-6c1ddac7-4358-4ac5-90a6-5108b0343c62 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4205940219 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.xbar_access_same_device .4205940219 |
| Directory | /workspace/24.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/24.xbar_error_and_unmapped_addr.2597230067 |
| Short name | T1653 |
| Test name | |
| Test status | |
| Simulation time | 299326989 ps |
| CPU time | 31.44 seconds |
| Started | Aug 13 06:52:09 PM PDT 24 |
| Finished | Aug 13 06:52:40 PM PDT 24 |
| Peak memory | 575624 kb |
| Host | smart-a4853879-0a60-4b71-b473-578b782b1204 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2597230067 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.xbar_error_and_unmapped_add r.2597230067 |
| Directory | /workspace/24.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/24.xbar_error_random.34275454 |
| Short name | T2887 |
| Test name | |
| Test status | |
| Simulation time | 612362265 ps |
| CPU time | 45.39 seconds |
| Started | Aug 13 06:52:10 PM PDT 24 |
| Finished | Aug 13 06:52:56 PM PDT 24 |
| Peak memory | 575552 kb |
| Host | smart-44fa0bd5-2278-4952-becc-61f48750f2c2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34275454 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.xbar_error_random.34275454 |
| Directory | /workspace/24.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/24.xbar_random.2414895343 |
| Short name | T2559 |
| Test name | |
| Test status | |
| Simulation time | 1503704501 ps |
| CPU time | 52.32 seconds |
| Started | Aug 13 06:52:12 PM PDT 24 |
| Finished | Aug 13 06:53:04 PM PDT 24 |
| Peak memory | 575620 kb |
| Host | smart-48640021-ab9d-4d1a-b878-192c86dd1f56 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2414895343 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.xbar_random.2414895343 |
| Directory | /workspace/24.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/24.xbar_random_large_delays.1695164027 |
| Short name | T1808 |
| Test name | |
| Test status | |
| Simulation time | 12418294425 ps |
| CPU time | 133.85 seconds |
| Started | Aug 13 06:52:09 PM PDT 24 |
| Finished | Aug 13 06:54:23 PM PDT 24 |
| Peak memory | 575692 kb |
| Host | smart-c69c26f9-00db-4432-976d-9e90ed49d0e1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1695164027 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.xbar_random_large_delays.1695164027 |
| Directory | /workspace/24.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/24.xbar_random_slow_rsp.2365387815 |
| Short name | T2300 |
| Test name | |
| Test status | |
| Simulation time | 36311293036 ps |
| CPU time | 572.31 seconds |
| Started | Aug 13 06:52:11 PM PDT 24 |
| Finished | Aug 13 07:01:43 PM PDT 24 |
| Peak memory | 575668 kb |
| Host | smart-95b838b0-265e-4a5c-bb18-3c933f8e5c6b |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2365387815 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.xbar_random_slow_rsp.2365387815 |
| Directory | /workspace/24.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/24.xbar_random_zero_delays.1992586002 |
| Short name | T534 |
| Test name | |
| Test status | |
| Simulation time | 472011691 ps |
| CPU time | 45.25 seconds |
| Started | Aug 13 06:52:11 PM PDT 24 |
| Finished | Aug 13 06:52:56 PM PDT 24 |
| Peak memory | 575564 kb |
| Host | smart-b3c585c6-c184-468d-a033-879262ec6bb3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1992586002 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.xbar_random_zero_del ays.1992586002 |
| Directory | /workspace/24.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/24.xbar_same_source.202675299 |
| Short name | T1762 |
| Test name | |
| Test status | |
| Simulation time | 360381401 ps |
| CPU time | 27.64 seconds |
| Started | Aug 13 06:52:11 PM PDT 24 |
| Finished | Aug 13 06:52:39 PM PDT 24 |
| Peak memory | 575632 kb |
| Host | smart-a6006866-b2d4-4239-bf9b-98a57d1144fe |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=202675299 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.xbar_same_source.202675299 |
| Directory | /workspace/24.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/24.xbar_smoke.2970715457 |
| Short name | T2402 |
| Test name | |
| Test status | |
| Simulation time | 178296809 ps |
| CPU time | 8.85 seconds |
| Started | Aug 13 06:52:05 PM PDT 24 |
| Finished | Aug 13 06:52:13 PM PDT 24 |
| Peak memory | 574200 kb |
| Host | smart-277af03a-5596-4e10-8ceb-037f1215fadd |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2970715457 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.xbar_smoke.2970715457 |
| Directory | /workspace/24.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/24.xbar_smoke_large_delays.3293520372 |
| Short name | T2502 |
| Test name | |
| Test status | |
| Simulation time | 7733182697 ps |
| CPU time | 78.7 seconds |
| Started | Aug 13 06:52:06 PM PDT 24 |
| Finished | Aug 13 06:53:25 PM PDT 24 |
| Peak memory | 573688 kb |
| Host | smart-e9f1f98f-2d0e-41ad-9284-be28a8a200a9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3293520372 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.xbar_smoke_large_delays.3293520372 |
| Directory | /workspace/24.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/24.xbar_smoke_slow_rsp.3638016174 |
| Short name | T2659 |
| Test name | |
| Test status | |
| Simulation time | 4769239125 ps |
| CPU time | 82.51 seconds |
| Started | Aug 13 06:52:06 PM PDT 24 |
| Finished | Aug 13 06:53:28 PM PDT 24 |
| Peak memory | 573768 kb |
| Host | smart-ff580ce6-c486-4652-a2c5-c9968ef40577 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3638016174 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.xbar_smoke_slow_rsp.3638016174 |
| Directory | /workspace/24.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/24.xbar_smoke_zero_delays.763570739 |
| Short name | T1671 |
| Test name | |
| Test status | |
| Simulation time | 46370277 ps |
| CPU time | 5.95 seconds |
| Started | Aug 13 06:52:03 PM PDT 24 |
| Finished | Aug 13 06:52:09 PM PDT 24 |
| Peak memory | 574216 kb |
| Host | smart-add0f081-334f-4327-82cb-20424d837b51 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=763570739 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.xbar_smoke_zero_delays .763570739 |
| Directory | /workspace/24.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/24.xbar_stress_all.1596502224 |
| Short name | T2801 |
| Test name | |
| Test status | |
| Simulation time | 430267978 ps |
| CPU time | 30.44 seconds |
| Started | Aug 13 06:52:09 PM PDT 24 |
| Finished | Aug 13 06:52:40 PM PDT 24 |
| Peak memory | 575636 kb |
| Host | smart-3ba635da-bf1c-4475-9f86-0be97c24e07a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1596502224 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.xbar_stress_all.1596502224 |
| Directory | /workspace/24.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/24.xbar_stress_all_with_error.878226259 |
| Short name | T2034 |
| Test name | |
| Test status | |
| Simulation time | 11852038259 ps |
| CPU time | 417.38 seconds |
| Started | Aug 13 06:52:12 PM PDT 24 |
| Finished | Aug 13 06:59:09 PM PDT 24 |
| Peak memory | 576528 kb |
| Host | smart-21d8c9fd-c9ce-4603-886a-f6eb97eb9c74 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=878226259 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.xbar_stress_all_with_error.878226259 |
| Directory | /workspace/24.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/24.xbar_stress_all_with_rand_reset.3704906636 |
| Short name | T2404 |
| Test name | |
| Test status | |
| Simulation time | 520315786 ps |
| CPU time | 288.09 seconds |
| Started | Aug 13 06:52:14 PM PDT 24 |
| Finished | Aug 13 06:57:02 PM PDT 24 |
| Peak memory | 576496 kb |
| Host | smart-67279efc-d95a-4dcd-b859-e0693481d30f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3704906636 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.xbar_stress_all _with_rand_reset.3704906636 |
| Directory | /workspace/24.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/24.xbar_stress_all_with_reset_error.1580180275 |
| Short name | T2312 |
| Test name | |
| Test status | |
| Simulation time | 394680620 ps |
| CPU time | 204.07 seconds |
| Started | Aug 13 06:52:10 PM PDT 24 |
| Finished | Aug 13 06:55:35 PM PDT 24 |
| Peak memory | 576488 kb |
| Host | smart-60321915-cf2e-424e-b509-7b3aaf40ec54 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1580180275 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.xbar_stress_al l_with_reset_error.1580180275 |
| Directory | /workspace/24.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/24.xbar_unmapped_addr.2442223119 |
| Short name | T2880 |
| Test name | |
| Test status | |
| Simulation time | 86338352 ps |
| CPU time | 12.01 seconds |
| Started | Aug 13 06:52:09 PM PDT 24 |
| Finished | Aug 13 06:52:21 PM PDT 24 |
| Peak memory | 575572 kb |
| Host | smart-39b001ac-1081-41c2-8acc-b9649f9bed54 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2442223119 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.xbar_unmapped_addr.2442223119 |
| Directory | /workspace/24.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/25.chip_tl_errors.2912493031 |
| Short name | T750 |
| Test name | |
| Test status | |
| Simulation time | 4152547754 ps |
| CPU time | 240.64 seconds |
| Started | Aug 13 06:52:11 PM PDT 24 |
| Finished | Aug 13 06:56:12 PM PDT 24 |
| Peak memory | 603404 kb |
| Host | smart-43ff459c-8e14-467a-9b60-94ff47714d42 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2912493031 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.chip_tl_errors.2912493031 |
| Directory | /workspace/25.chip_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/25.xbar_access_same_device.2185475262 |
| Short name | T2868 |
| Test name | |
| Test status | |
| Simulation time | 944417123 ps |
| CPU time | 84.72 seconds |
| Started | Aug 13 06:52:16 PM PDT 24 |
| Finished | Aug 13 06:53:41 PM PDT 24 |
| Peak memory | 575756 kb |
| Host | smart-49c32cec-a7dd-43f8-a6ce-4c0635b796c7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2185475262 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.xbar_access_same_device .2185475262 |
| Directory | /workspace/25.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/25.xbar_access_same_device_slow_rsp.584882109 |
| Short name | T2241 |
| Test name | |
| Test status | |
| Simulation time | 40817920492 ps |
| CPU time | 712.08 seconds |
| Started | Aug 13 06:52:18 PM PDT 24 |
| Finished | Aug 13 07:04:11 PM PDT 24 |
| Peak memory | 575768 kb |
| Host | smart-f384f27b-a69f-4559-bc56-ec130c4d456b |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=584882109 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.xbar_access_same_d evice_slow_rsp.584882109 |
| Directory | /workspace/25.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/25.xbar_error_and_unmapped_addr.1529413571 |
| Short name | T1942 |
| Test name | |
| Test status | |
| Simulation time | 283154616 ps |
| CPU time | 31.93 seconds |
| Started | Aug 13 06:52:20 PM PDT 24 |
| Finished | Aug 13 06:52:52 PM PDT 24 |
| Peak memory | 575476 kb |
| Host | smart-503225eb-baf7-4bab-8186-d7ef6ef7e922 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1529413571 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.xbar_error_and_unmapped_add r.1529413571 |
| Directory | /workspace/25.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/25.xbar_error_random.315748345 |
| Short name | T77 |
| Test name | |
| Test status | |
| Simulation time | 519886122 ps |
| CPU time | 18.04 seconds |
| Started | Aug 13 06:52:19 PM PDT 24 |
| Finished | Aug 13 06:52:37 PM PDT 24 |
| Peak memory | 575820 kb |
| Host | smart-37eedff5-c7a9-4b84-a3bc-34946a7d60ea |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=315748345 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.xbar_error_random.315748345 |
| Directory | /workspace/25.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/25.xbar_random.3590508528 |
| Short name | T2342 |
| Test name | |
| Test status | |
| Simulation time | 1140771305 ps |
| CPU time | 45.92 seconds |
| Started | Aug 13 06:52:19 PM PDT 24 |
| Finished | Aug 13 06:53:05 PM PDT 24 |
| Peak memory | 575580 kb |
| Host | smart-f409f48c-c20e-452d-98e9-2c7f0b08bae8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3590508528 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.xbar_random.3590508528 |
| Directory | /workspace/25.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/25.xbar_random_large_delays.1765060316 |
| Short name | T2857 |
| Test name | |
| Test status | |
| Simulation time | 43740850721 ps |
| CPU time | 414.52 seconds |
| Started | Aug 13 06:52:19 PM PDT 24 |
| Finished | Aug 13 06:59:14 PM PDT 24 |
| Peak memory | 575532 kb |
| Host | smart-c1707a3f-d3e0-4eed-961a-735946fc9bae |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1765060316 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.xbar_random_large_delays.1765060316 |
| Directory | /workspace/25.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/25.xbar_random_slow_rsp.3431518463 |
| Short name | T1893 |
| Test name | |
| Test status | |
| Simulation time | 11297637529 ps |
| CPU time | 206.3 seconds |
| Started | Aug 13 06:52:15 PM PDT 24 |
| Finished | Aug 13 06:55:42 PM PDT 24 |
| Peak memory | 575676 kb |
| Host | smart-3041164b-f17c-4347-8797-f89abd3bb5ff |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3431518463 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.xbar_random_slow_rsp.3431518463 |
| Directory | /workspace/25.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/25.xbar_random_zero_delays.3798167081 |
| Short name | T1988 |
| Test name | |
| Test status | |
| Simulation time | 237980668 ps |
| CPU time | 22.33 seconds |
| Started | Aug 13 06:52:19 PM PDT 24 |
| Finished | Aug 13 06:52:41 PM PDT 24 |
| Peak memory | 575600 kb |
| Host | smart-ee73a278-be4e-4719-8ad7-86007370b534 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3798167081 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.xbar_random_zero_del ays.3798167081 |
| Directory | /workspace/25.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/25.xbar_same_source.3564724335 |
| Short name | T2859 |
| Test name | |
| Test status | |
| Simulation time | 445030440 ps |
| CPU time | 34.01 seconds |
| Started | Aug 13 06:52:17 PM PDT 24 |
| Finished | Aug 13 06:52:51 PM PDT 24 |
| Peak memory | 575596 kb |
| Host | smart-918c7ec1-82bb-4a5a-9ef5-52e900802429 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3564724335 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.xbar_same_source.3564724335 |
| Directory | /workspace/25.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/25.xbar_smoke.443669141 |
| Short name | T1600 |
| Test name | |
| Test status | |
| Simulation time | 197361201 ps |
| CPU time | 8.12 seconds |
| Started | Aug 13 06:52:13 PM PDT 24 |
| Finished | Aug 13 06:52:21 PM PDT 24 |
| Peak memory | 573588 kb |
| Host | smart-a5d58651-a6f5-4b7c-8aaa-2a4e2093ff4e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=443669141 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.xbar_smoke.443669141 |
| Directory | /workspace/25.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/25.xbar_smoke_large_delays.1431347655 |
| Short name | T1483 |
| Test name | |
| Test status | |
| Simulation time | 8864145489 ps |
| CPU time | 93.39 seconds |
| Started | Aug 13 06:52:11 PM PDT 24 |
| Finished | Aug 13 06:53:45 PM PDT 24 |
| Peak memory | 573596 kb |
| Host | smart-6168fd2e-c9ad-416e-a091-d8b72e072f6c |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1431347655 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.xbar_smoke_large_delays.1431347655 |
| Directory | /workspace/25.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/25.xbar_smoke_slow_rsp.3426257678 |
| Short name | T1566 |
| Test name | |
| Test status | |
| Simulation time | 4212691259 ps |
| CPU time | 74.93 seconds |
| Started | Aug 13 06:52:12 PM PDT 24 |
| Finished | Aug 13 06:53:27 PM PDT 24 |
| Peak memory | 573584 kb |
| Host | smart-1b8871e7-8a86-400d-9248-cd07270f8005 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3426257678 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.xbar_smoke_slow_rsp.3426257678 |
| Directory | /workspace/25.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/25.xbar_smoke_zero_delays.3189685322 |
| Short name | T1554 |
| Test name | |
| Test status | |
| Simulation time | 50897237 ps |
| CPU time | 6.46 seconds |
| Started | Aug 13 06:52:15 PM PDT 24 |
| Finished | Aug 13 06:52:22 PM PDT 24 |
| Peak memory | 573608 kb |
| Host | smart-91100e9a-4d9d-4f03-b241-b5951bdb5024 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3189685322 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.xbar_smoke_zero_delay s.3189685322 |
| Directory | /workspace/25.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/25.xbar_stress_all.2687431231 |
| Short name | T2522 |
| Test name | |
| Test status | |
| Simulation time | 13093631381 ps |
| CPU time | 470.32 seconds |
| Started | Aug 13 06:52:18 PM PDT 24 |
| Finished | Aug 13 07:00:08 PM PDT 24 |
| Peak memory | 575688 kb |
| Host | smart-a43583bd-13e2-4f0c-be94-7a7900763c28 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2687431231 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.xbar_stress_all.2687431231 |
| Directory | /workspace/25.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/25.xbar_stress_all_with_error.2439071931 |
| Short name | T2022 |
| Test name | |
| Test status | |
| Simulation time | 5887051812 ps |
| CPU time | 226.21 seconds |
| Started | Aug 13 06:52:19 PM PDT 24 |
| Finished | Aug 13 06:56:05 PM PDT 24 |
| Peak memory | 575680 kb |
| Host | smart-28f5e6ab-40f5-4576-9d9e-999ba246b4a9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2439071931 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.xbar_stress_all_with_error.2439071931 |
| Directory | /workspace/25.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/25.xbar_stress_all_with_rand_reset.3299252511 |
| Short name | T904 |
| Test name | |
| Test status | |
| Simulation time | 401719374 ps |
| CPU time | 197.98 seconds |
| Started | Aug 13 06:52:19 PM PDT 24 |
| Finished | Aug 13 06:55:37 PM PDT 24 |
| Peak memory | 576468 kb |
| Host | smart-59f6292d-c21d-4c49-9218-5c57d040952e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3299252511 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.xbar_stress_all _with_rand_reset.3299252511 |
| Directory | /workspace/25.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/25.xbar_stress_all_with_reset_error.2954721090 |
| Short name | T1853 |
| Test name | |
| Test status | |
| Simulation time | 3578498319 ps |
| CPU time | 501.89 seconds |
| Started | Aug 13 06:52:17 PM PDT 24 |
| Finished | Aug 13 07:00:39 PM PDT 24 |
| Peak memory | 576516 kb |
| Host | smart-bda9f97d-095b-4071-a990-64f7af0cb23c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2954721090 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.xbar_stress_al l_with_reset_error.2954721090 |
| Directory | /workspace/25.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/25.xbar_unmapped_addr.3571739275 |
| Short name | T1842 |
| Test name | |
| Test status | |
| Simulation time | 405189172 ps |
| CPU time | 17.77 seconds |
| Started | Aug 13 06:52:17 PM PDT 24 |
| Finished | Aug 13 06:52:35 PM PDT 24 |
| Peak memory | 575712 kb |
| Host | smart-3cad2306-53f4-49fa-958b-9eebaabe43a7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3571739275 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.xbar_unmapped_addr.3571739275 |
| Directory | /workspace/25.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/26.xbar_access_same_device.3693143217 |
| Short name | T2916 |
| Test name | |
| Test status | |
| Simulation time | 851443413 ps |
| CPU time | 74.77 seconds |
| Started | Aug 13 06:52:22 PM PDT 24 |
| Finished | Aug 13 06:53:37 PM PDT 24 |
| Peak memory | 575732 kb |
| Host | smart-1f1a5b3b-1fb0-4bab-b073-a09cf396c9fb |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3693143217 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.xbar_access_same_device .3693143217 |
| Directory | /workspace/26.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/26.xbar_access_same_device_slow_rsp.3883760551 |
| Short name | T2626 |
| Test name | |
| Test status | |
| Simulation time | 70046118195 ps |
| CPU time | 1241.07 seconds |
| Started | Aug 13 06:52:24 PM PDT 24 |
| Finished | Aug 13 07:13:05 PM PDT 24 |
| Peak memory | 575684 kb |
| Host | smart-f8714b76-07c8-461f-8fc4-37706d80374f |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3883760551 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.xbar_access_same_ device_slow_rsp.3883760551 |
| Directory | /workspace/26.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/26.xbar_error_and_unmapped_addr.1726807281 |
| Short name | T2881 |
| Test name | |
| Test status | |
| Simulation time | 246838371 ps |
| CPU time | 26.91 seconds |
| Started | Aug 13 06:52:28 PM PDT 24 |
| Finished | Aug 13 06:52:55 PM PDT 24 |
| Peak memory | 575444 kb |
| Host | smart-13a7513b-d98c-4427-9d94-0285962e0988 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1726807281 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.xbar_error_and_unmapped_add r.1726807281 |
| Directory | /workspace/26.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/26.xbar_error_random.3455185576 |
| Short name | T2570 |
| Test name | |
| Test status | |
| Simulation time | 557457015 ps |
| CPU time | 46.48 seconds |
| Started | Aug 13 06:52:25 PM PDT 24 |
| Finished | Aug 13 06:53:12 PM PDT 24 |
| Peak memory | 575720 kb |
| Host | smart-fea7cc39-5f8c-460a-9021-595d2c84cd5c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3455185576 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.xbar_error_random.3455185576 |
| Directory | /workspace/26.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/26.xbar_random.1025386527 |
| Short name | T1863 |
| Test name | |
| Test status | |
| Simulation time | 169225166 ps |
| CPU time | 18.4 seconds |
| Started | Aug 13 06:52:26 PM PDT 24 |
| Finished | Aug 13 06:52:44 PM PDT 24 |
| Peak memory | 575460 kb |
| Host | smart-1eed685a-78e1-4057-bef1-058d61fa1990 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1025386527 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.xbar_random.1025386527 |
| Directory | /workspace/26.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/26.xbar_random_large_delays.2101645450 |
| Short name | T1992 |
| Test name | |
| Test status | |
| Simulation time | 60774092549 ps |
| CPU time | 635.75 seconds |
| Started | Aug 13 06:52:34 PM PDT 24 |
| Finished | Aug 13 07:03:10 PM PDT 24 |
| Peak memory | 575768 kb |
| Host | smart-00117828-a90b-415e-a3cc-a0bd1f997eac |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2101645450 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.xbar_random_large_delays.2101645450 |
| Directory | /workspace/26.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/26.xbar_random_slow_rsp.1582943654 |
| Short name | T2229 |
| Test name | |
| Test status | |
| Simulation time | 21491892040 ps |
| CPU time | 366.37 seconds |
| Started | Aug 13 06:52:32 PM PDT 24 |
| Finished | Aug 13 06:58:38 PM PDT 24 |
| Peak memory | 575644 kb |
| Host | smart-d2426eb7-feb9-4504-9d51-454775fc430b |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1582943654 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.xbar_random_slow_rsp.1582943654 |
| Directory | /workspace/26.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/26.xbar_random_zero_delays.367954049 |
| Short name | T1977 |
| Test name | |
| Test status | |
| Simulation time | 71907628 ps |
| CPU time | 9.47 seconds |
| Started | Aug 13 06:52:26 PM PDT 24 |
| Finished | Aug 13 06:52:35 PM PDT 24 |
| Peak memory | 575596 kb |
| Host | smart-70300c07-dbca-48da-8257-04f178db16d5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=367954049 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.xbar_random_zero_dela ys.367954049 |
| Directory | /workspace/26.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/26.xbar_same_source.3114756219 |
| Short name | T698 |
| Test name | |
| Test status | |
| Simulation time | 194943841 ps |
| CPU time | 15.21 seconds |
| Started | Aug 13 06:52:30 PM PDT 24 |
| Finished | Aug 13 06:52:45 PM PDT 24 |
| Peak memory | 575656 kb |
| Host | smart-af0891bb-2089-4840-bff0-31e8715a7ce2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3114756219 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.xbar_same_source.3114756219 |
| Directory | /workspace/26.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/26.xbar_smoke.4197602451 |
| Short name | T2216 |
| Test name | |
| Test status | |
| Simulation time | 51429401 ps |
| CPU time | 6.17 seconds |
| Started | Aug 13 06:52:19 PM PDT 24 |
| Finished | Aug 13 06:52:25 PM PDT 24 |
| Peak memory | 574216 kb |
| Host | smart-1ec41a54-3db3-454f-8f2c-b39f6864c592 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4197602451 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.xbar_smoke.4197602451 |
| Directory | /workspace/26.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/26.xbar_smoke_large_delays.48707981 |
| Short name | T2639 |
| Test name | |
| Test status | |
| Simulation time | 7131178750 ps |
| CPU time | 72.14 seconds |
| Started | Aug 13 06:52:31 PM PDT 24 |
| Finished | Aug 13 06:53:44 PM PDT 24 |
| Peak memory | 573680 kb |
| Host | smart-0e79d419-92e5-47a8-a56d-d83531b6d1da |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=48707981 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.xbar_smoke_large_delays.48707981 |
| Directory | /workspace/26.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/26.xbar_smoke_slow_rsp.922210714 |
| Short name | T2734 |
| Test name | |
| Test status | |
| Simulation time | 5616800671 ps |
| CPU time | 91.78 seconds |
| Started | Aug 13 06:52:29 PM PDT 24 |
| Finished | Aug 13 06:54:01 PM PDT 24 |
| Peak memory | 573656 kb |
| Host | smart-3be53e1b-dfc2-4fd2-b4cf-9af1babd5675 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=922210714 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.xbar_smoke_slow_rsp.922210714 |
| Directory | /workspace/26.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/26.xbar_smoke_zero_delays.164016649 |
| Short name | T72 |
| Test name | |
| Test status | |
| Simulation time | 48594627 ps |
| CPU time | 6.25 seconds |
| Started | Aug 13 06:52:20 PM PDT 24 |
| Finished | Aug 13 06:52:26 PM PDT 24 |
| Peak memory | 574204 kb |
| Host | smart-e9f75db5-7450-443a-b7c0-72e0990797b0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=164016649 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.xbar_smoke_zero_delays .164016649 |
| Directory | /workspace/26.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/26.xbar_stress_all.2918662521 |
| Short name | T585 |
| Test name | |
| Test status | |
| Simulation time | 10643278138 ps |
| CPU time | 426.72 seconds |
| Started | Aug 13 06:52:28 PM PDT 24 |
| Finished | Aug 13 06:59:35 PM PDT 24 |
| Peak memory | 575660 kb |
| Host | smart-0d1d4311-02a0-48df-9e32-675ef45745c4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2918662521 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.xbar_stress_all.2918662521 |
| Directory | /workspace/26.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/26.xbar_stress_all_with_error.3058260169 |
| Short name | T1792 |
| Test name | |
| Test status | |
| Simulation time | 1977815585 ps |
| CPU time | 162.27 seconds |
| Started | Aug 13 06:52:27 PM PDT 24 |
| Finished | Aug 13 06:55:09 PM PDT 24 |
| Peak memory | 576468 kb |
| Host | smart-4391b34c-8e58-47f4-b929-1e09920aaa2c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3058260169 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.xbar_stress_all_with_error.3058260169 |
| Directory | /workspace/26.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/26.xbar_stress_all_with_reset_error.2596247205 |
| Short name | T1917 |
| Test name | |
| Test status | |
| Simulation time | 154477591 ps |
| CPU time | 66.35 seconds |
| Started | Aug 13 06:52:24 PM PDT 24 |
| Finished | Aug 13 06:53:30 PM PDT 24 |
| Peak memory | 575568 kb |
| Host | smart-eddc7d21-5c4a-4f37-988e-87315e374a01 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2596247205 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.xbar_stress_al l_with_reset_error.2596247205 |
| Directory | /workspace/26.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/26.xbar_unmapped_addr.1684684916 |
| Short name | T1567 |
| Test name | |
| Test status | |
| Simulation time | 474115505 ps |
| CPU time | 22.63 seconds |
| Started | Aug 13 06:52:30 PM PDT 24 |
| Finished | Aug 13 06:52:52 PM PDT 24 |
| Peak memory | 575680 kb |
| Host | smart-b3a06446-803e-4fe0-acee-f6219d047c88 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1684684916 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.xbar_unmapped_addr.1684684916 |
| Directory | /workspace/26.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/27.chip_tl_errors.3840070740 |
| Short name | T2719 |
| Test name | |
| Test status | |
| Simulation time | 3312470176 ps |
| CPU time | 150.43 seconds |
| Started | Aug 13 06:52:31 PM PDT 24 |
| Finished | Aug 13 06:55:02 PM PDT 24 |
| Peak memory | 598372 kb |
| Host | smart-b82e2b71-96d9-4b09-a0b7-5583524946d2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3840070740 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.chip_tl_errors.3840070740 |
| Directory | /workspace/27.chip_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/27.xbar_access_same_device.147437468 |
| Short name | T1904 |
| Test name | |
| Test status | |
| Simulation time | 460078955 ps |
| CPU time | 20.07 seconds |
| Started | Aug 13 06:52:35 PM PDT 24 |
| Finished | Aug 13 06:52:55 PM PDT 24 |
| Peak memory | 576324 kb |
| Host | smart-91173053-2fe6-4c68-af8c-0ad427764f13 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=147437468 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.xbar_access_same_device. 147437468 |
| Directory | /workspace/27.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/27.xbar_access_same_device_slow_rsp.1970826110 |
| Short name | T511 |
| Test name | |
| Test status | |
| Simulation time | 78596303918 ps |
| CPU time | 1466.69 seconds |
| Started | Aug 13 06:52:37 PM PDT 24 |
| Finished | Aug 13 07:17:04 PM PDT 24 |
| Peak memory | 575616 kb |
| Host | smart-3a68b006-0920-4858-9950-f2196772b6b9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1970826110 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.xbar_access_same_ device_slow_rsp.1970826110 |
| Directory | /workspace/27.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/27.xbar_error_and_unmapped_addr.4082631007 |
| Short name | T2823 |
| Test name | |
| Test status | |
| Simulation time | 430677883 ps |
| CPU time | 18.11 seconds |
| Started | Aug 13 06:52:34 PM PDT 24 |
| Finished | Aug 13 06:52:53 PM PDT 24 |
| Peak memory | 575684 kb |
| Host | smart-acbb5fb1-533d-4d4e-bd21-2075ef13f7e4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4082631007 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.xbar_error_and_unmapped_add r.4082631007 |
| Directory | /workspace/27.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/27.xbar_error_random.3818938059 |
| Short name | T2413 |
| Test name | |
| Test status | |
| Simulation time | 1017820468 ps |
| CPU time | 33.64 seconds |
| Started | Aug 13 06:52:34 PM PDT 24 |
| Finished | Aug 13 06:53:08 PM PDT 24 |
| Peak memory | 575524 kb |
| Host | smart-ffaef1e2-4c51-4ed3-9c12-1cd852befca7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3818938059 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.xbar_error_random.3818938059 |
| Directory | /workspace/27.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/27.xbar_random.3798975383 |
| Short name | T650 |
| Test name | |
| Test status | |
| Simulation time | 797174279 ps |
| CPU time | 32.48 seconds |
| Started | Aug 13 06:52:25 PM PDT 24 |
| Finished | Aug 13 06:52:58 PM PDT 24 |
| Peak memory | 575664 kb |
| Host | smart-723476bd-a2e5-41e8-b9d2-17be9cb2452b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3798975383 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.xbar_random.3798975383 |
| Directory | /workspace/27.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/27.xbar_random_large_delays.4144461180 |
| Short name | T2529 |
| Test name | |
| Test status | |
| Simulation time | 24308970543 ps |
| CPU time | 248.33 seconds |
| Started | Aug 13 06:52:34 PM PDT 24 |
| Finished | Aug 13 06:56:42 PM PDT 24 |
| Peak memory | 575608 kb |
| Host | smart-bd79166f-3590-4e51-a42a-5523962df137 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4144461180 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.xbar_random_large_delays.4144461180 |
| Directory | /workspace/27.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/27.xbar_random_slow_rsp.108706342 |
| Short name | T1544 |
| Test name | |
| Test status | |
| Simulation time | 7228493265 ps |
| CPU time | 128.44 seconds |
| Started | Aug 13 06:52:35 PM PDT 24 |
| Finished | Aug 13 06:54:43 PM PDT 24 |
| Peak memory | 575580 kb |
| Host | smart-3d3b8a11-8f41-4218-9517-e5ebfd554ee5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=108706342 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.xbar_random_slow_rsp.108706342 |
| Directory | /workspace/27.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/27.xbar_random_zero_delays.187153494 |
| Short name | T2571 |
| Test name | |
| Test status | |
| Simulation time | 66329647 ps |
| CPU time | 9.02 seconds |
| Started | Aug 13 06:52:28 PM PDT 24 |
| Finished | Aug 13 06:52:37 PM PDT 24 |
| Peak memory | 575664 kb |
| Host | smart-4842de51-5c5f-41e0-8fb2-ddf80e82a269 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=187153494 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.xbar_random_zero_dela ys.187153494 |
| Directory | /workspace/27.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/27.xbar_same_source.2340040777 |
| Short name | T1595 |
| Test name | |
| Test status | |
| Simulation time | 210739295 ps |
| CPU time | 17.07 seconds |
| Started | Aug 13 06:52:35 PM PDT 24 |
| Finished | Aug 13 06:52:53 PM PDT 24 |
| Peak memory | 575492 kb |
| Host | smart-550d88f5-36e8-48b2-9276-85d5e34c9d5f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2340040777 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.xbar_same_source.2340040777 |
| Directory | /workspace/27.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/27.xbar_smoke.434287248 |
| Short name | T2632 |
| Test name | |
| Test status | |
| Simulation time | 46298862 ps |
| CPU time | 6.07 seconds |
| Started | Aug 13 06:52:25 PM PDT 24 |
| Finished | Aug 13 06:52:31 PM PDT 24 |
| Peak memory | 573584 kb |
| Host | smart-2a6ca950-1838-4fea-9355-2c8c0589d93e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=434287248 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.xbar_smoke.434287248 |
| Directory | /workspace/27.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/27.xbar_smoke_large_delays.2536304558 |
| Short name | T2450 |
| Test name | |
| Test status | |
| Simulation time | 7329490558 ps |
| CPU time | 75.76 seconds |
| Started | Aug 13 06:52:31 PM PDT 24 |
| Finished | Aug 13 06:53:47 PM PDT 24 |
| Peak memory | 573656 kb |
| Host | smart-4c5faf07-5f0b-4233-a713-22b45056950c |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2536304558 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.xbar_smoke_large_delays.2536304558 |
| Directory | /workspace/27.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/27.xbar_smoke_slow_rsp.1063105957 |
| Short name | T1541 |
| Test name | |
| Test status | |
| Simulation time | 3526922080 ps |
| CPU time | 58.54 seconds |
| Started | Aug 13 06:52:25 PM PDT 24 |
| Finished | Aug 13 06:53:24 PM PDT 24 |
| Peak memory | 573640 kb |
| Host | smart-05558c08-70eb-46e3-b9df-75f4718b5318 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1063105957 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.xbar_smoke_slow_rsp.1063105957 |
| Directory | /workspace/27.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/27.xbar_smoke_zero_delays.2464371522 |
| Short name | T2550 |
| Test name | |
| Test status | |
| Simulation time | 36280314 ps |
| CPU time | 5.97 seconds |
| Started | Aug 13 06:52:25 PM PDT 24 |
| Finished | Aug 13 06:52:31 PM PDT 24 |
| Peak memory | 573608 kb |
| Host | smart-cc413e03-55a3-4371-a5c1-f6b2bd016722 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2464371522 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.xbar_smoke_zero_delay s.2464371522 |
| Directory | /workspace/27.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/27.xbar_stress_all.4088631889 |
| Short name | T1794 |
| Test name | |
| Test status | |
| Simulation time | 1256036035 ps |
| CPU time | 55.33 seconds |
| Started | Aug 13 06:52:35 PM PDT 24 |
| Finished | Aug 13 06:53:31 PM PDT 24 |
| Peak memory | 575792 kb |
| Host | smart-a37e35b6-a503-46e4-b890-ffbf8f14b212 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4088631889 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.xbar_stress_all.4088631889 |
| Directory | /workspace/27.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/27.xbar_stress_all_with_error.3874469070 |
| Short name | T1973 |
| Test name | |
| Test status | |
| Simulation time | 1796613215 ps |
| CPU time | 127.13 seconds |
| Started | Aug 13 06:52:33 PM PDT 24 |
| Finished | Aug 13 06:54:40 PM PDT 24 |
| Peak memory | 575544 kb |
| Host | smart-cf4c66db-c60f-48a8-9e48-cedcef43480f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3874469070 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.xbar_stress_all_with_error.3874469070 |
| Directory | /workspace/27.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/27.xbar_stress_all_with_rand_reset.480535942 |
| Short name | T2732 |
| Test name | |
| Test status | |
| Simulation time | 7172152881 ps |
| CPU time | 898.09 seconds |
| Started | Aug 13 06:52:35 PM PDT 24 |
| Finished | Aug 13 07:07:34 PM PDT 24 |
| Peak memory | 575736 kb |
| Host | smart-67c9c17d-9201-4776-b2d1-3423a9da8f75 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=480535942 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_res et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.xbar_stress_all_ with_rand_reset.480535942 |
| Directory | /workspace/27.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/27.xbar_unmapped_addr.1398781002 |
| Short name | T2294 |
| Test name | |
| Test status | |
| Simulation time | 810177935 ps |
| CPU time | 34 seconds |
| Started | Aug 13 06:52:37 PM PDT 24 |
| Finished | Aug 13 06:53:11 PM PDT 24 |
| Peak memory | 575736 kb |
| Host | smart-7c43f92f-f438-4e6c-9bb4-16b5e894eada |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1398781002 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.xbar_unmapped_addr.1398781002 |
| Directory | /workspace/27.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/28.chip_tl_errors.2823560240 |
| Short name | T589 |
| Test name | |
| Test status | |
| Simulation time | 2655635465 ps |
| CPU time | 129.93 seconds |
| Started | Aug 13 06:52:33 PM PDT 24 |
| Finished | Aug 13 06:54:43 PM PDT 24 |
| Peak memory | 603488 kb |
| Host | smart-99adff73-a0de-4622-bc3c-1dbeae42e580 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2823560240 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.chip_tl_errors.2823560240 |
| Directory | /workspace/28.chip_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/28.xbar_access_same_device.1120083591 |
| Short name | T874 |
| Test name | |
| Test status | |
| Simulation time | 614136610 ps |
| CPU time | 29.59 seconds |
| Started | Aug 13 06:52:36 PM PDT 24 |
| Finished | Aug 13 06:53:05 PM PDT 24 |
| Peak memory | 575624 kb |
| Host | smart-9a3bd74c-be37-4c9f-96f5-9f7a0a2030b7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1120083591 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.xbar_access_same_device .1120083591 |
| Directory | /workspace/28.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/28.xbar_access_same_device_slow_rsp.3303762810 |
| Short name | T1936 |
| Test name | |
| Test status | |
| Simulation time | 159037921035 ps |
| CPU time | 2866.62 seconds |
| Started | Aug 13 06:52:33 PM PDT 24 |
| Finished | Aug 13 07:40:20 PM PDT 24 |
| Peak memory | 575824 kb |
| Host | smart-33a13d0a-63b8-41f2-a068-5951ceba0ce3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3303762810 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.xbar_access_same_ device_slow_rsp.3303762810 |
| Directory | /workspace/28.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/28.xbar_error_and_unmapped_addr.286771071 |
| Short name | T2153 |
| Test name | |
| Test status | |
| Simulation time | 1195282404 ps |
| CPU time | 51.97 seconds |
| Started | Aug 13 06:52:42 PM PDT 24 |
| Finished | Aug 13 06:53:34 PM PDT 24 |
| Peak memory | 575668 kb |
| Host | smart-a33c5c08-4317-4219-b4af-f531e92f9557 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=286771071 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.xbar_error_and_unmapped_addr .286771071 |
| Directory | /workspace/28.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/28.xbar_error_random.4094931244 |
| Short name | T2012 |
| Test name | |
| Test status | |
| Simulation time | 432098773 ps |
| CPU time | 33.82 seconds |
| Started | Aug 13 06:52:45 PM PDT 24 |
| Finished | Aug 13 06:53:19 PM PDT 24 |
| Peak memory | 575628 kb |
| Host | smart-ea3f2a96-dc13-4504-bb15-6158ac86c12e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4094931244 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.xbar_error_random.4094931244 |
| Directory | /workspace/28.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/28.xbar_random.3606894917 |
| Short name | T485 |
| Test name | |
| Test status | |
| Simulation time | 519561738 ps |
| CPU time | 43.95 seconds |
| Started | Aug 13 06:52:35 PM PDT 24 |
| Finished | Aug 13 06:53:19 PM PDT 24 |
| Peak memory | 575664 kb |
| Host | smart-b2c4de69-d1cc-4961-85cb-a8e496a87dc3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3606894917 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.xbar_random.3606894917 |
| Directory | /workspace/28.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/28.xbar_random_large_delays.2628314523 |
| Short name | T2473 |
| Test name | |
| Test status | |
| Simulation time | 12749240222 ps |
| CPU time | 140.36 seconds |
| Started | Aug 13 06:52:35 PM PDT 24 |
| Finished | Aug 13 06:54:56 PM PDT 24 |
| Peak memory | 575796 kb |
| Host | smart-ccef7b73-209d-4471-9fed-7a40c9bed128 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2628314523 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.xbar_random_large_delays.2628314523 |
| Directory | /workspace/28.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/28.xbar_random_slow_rsp.3680573053 |
| Short name | T636 |
| Test name | |
| Test status | |
| Simulation time | 17987456118 ps |
| CPU time | 295.14 seconds |
| Started | Aug 13 06:52:34 PM PDT 24 |
| Finished | Aug 13 06:57:29 PM PDT 24 |
| Peak memory | 575572 kb |
| Host | smart-5d3ca069-7ebd-4e6c-b4b5-363f0af23a87 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3680573053 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.xbar_random_slow_rsp.3680573053 |
| Directory | /workspace/28.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/28.xbar_random_zero_delays.3515357071 |
| Short name | T1870 |
| Test name | |
| Test status | |
| Simulation time | 512456870 ps |
| CPU time | 39.37 seconds |
| Started | Aug 13 06:52:32 PM PDT 24 |
| Finished | Aug 13 06:53:11 PM PDT 24 |
| Peak memory | 575708 kb |
| Host | smart-b6433c8d-03b3-4401-a130-c9a10a2288da |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3515357071 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.xbar_random_zero_del ays.3515357071 |
| Directory | /workspace/28.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/28.xbar_same_source.1913888243 |
| Short name | T2491 |
| Test name | |
| Test status | |
| Simulation time | 2095270029 ps |
| CPU time | 61.08 seconds |
| Started | Aug 13 06:52:42 PM PDT 24 |
| Finished | Aug 13 06:53:43 PM PDT 24 |
| Peak memory | 575604 kb |
| Host | smart-4172468b-ff15-4f3c-935f-e9cce246144d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1913888243 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.xbar_same_source.1913888243 |
| Directory | /workspace/28.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/28.xbar_smoke.4260760526 |
| Short name | T2411 |
| Test name | |
| Test status | |
| Simulation time | 199029662 ps |
| CPU time | 9.39 seconds |
| Started | Aug 13 06:52:33 PM PDT 24 |
| Finished | Aug 13 06:52:42 PM PDT 24 |
| Peak memory | 574240 kb |
| Host | smart-8e92ad2d-bdf7-414c-8c89-a566f326f870 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4260760526 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.xbar_smoke.4260760526 |
| Directory | /workspace/28.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/28.xbar_smoke_large_delays.4217560697 |
| Short name | T2740 |
| Test name | |
| Test status | |
| Simulation time | 10041646233 ps |
| CPU time | 108.73 seconds |
| Started | Aug 13 06:52:34 PM PDT 24 |
| Finished | Aug 13 06:54:23 PM PDT 24 |
| Peak memory | 574284 kb |
| Host | smart-f86c78cb-cc6d-4dc9-a713-a415ebd44804 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4217560697 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.xbar_smoke_large_delays.4217560697 |
| Directory | /workspace/28.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/28.xbar_smoke_slow_rsp.1079124494 |
| Short name | T1656 |
| Test name | |
| Test status | |
| Simulation time | 4396411992 ps |
| CPU time | 75.67 seconds |
| Started | Aug 13 06:52:33 PM PDT 24 |
| Finished | Aug 13 06:53:48 PM PDT 24 |
| Peak memory | 573628 kb |
| Host | smart-fc33f1a1-3524-40aa-939a-3d655f2f7637 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1079124494 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.xbar_smoke_slow_rsp.1079124494 |
| Directory | /workspace/28.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/28.xbar_smoke_zero_delays.2273275343 |
| Short name | T1545 |
| Test name | |
| Test status | |
| Simulation time | 50374131 ps |
| CPU time | 7.14 seconds |
| Started | Aug 13 06:52:35 PM PDT 24 |
| Finished | Aug 13 06:52:43 PM PDT 24 |
| Peak memory | 573540 kb |
| Host | smart-20707a6a-f4a9-4bec-9742-5eebaf7414d2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2273275343 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.xbar_smoke_zero_delay s.2273275343 |
| Directory | /workspace/28.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/28.xbar_stress_all.4191024238 |
| Short name | T2764 |
| Test name | |
| Test status | |
| Simulation time | 5052277323 ps |
| CPU time | 178.31 seconds |
| Started | Aug 13 06:52:40 PM PDT 24 |
| Finished | Aug 13 06:55:38 PM PDT 24 |
| Peak memory | 576316 kb |
| Host | smart-ccfe8c46-8345-4784-a7c5-c0fc5124721e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4191024238 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.xbar_stress_all.4191024238 |
| Directory | /workspace/28.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/28.xbar_stress_all_with_error.635894597 |
| Short name | T1919 |
| Test name | |
| Test status | |
| Simulation time | 2011504829 ps |
| CPU time | 70.05 seconds |
| Started | Aug 13 06:52:41 PM PDT 24 |
| Finished | Aug 13 06:53:52 PM PDT 24 |
| Peak memory | 575476 kb |
| Host | smart-cc2e05f6-43d3-448f-b82c-e96f0e00a315 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=635894597 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.xbar_stress_all_with_error.635894597 |
| Directory | /workspace/28.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/28.xbar_stress_all_with_rand_reset.3189494080 |
| Short name | T932 |
| Test name | |
| Test status | |
| Simulation time | 405587450 ps |
| CPU time | 250.24 seconds |
| Started | Aug 13 06:52:41 PM PDT 24 |
| Finished | Aug 13 06:56:52 PM PDT 24 |
| Peak memory | 576424 kb |
| Host | smart-c88bc564-7d0a-4619-82e1-4d3ac049dc0c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3189494080 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.xbar_stress_all _with_rand_reset.3189494080 |
| Directory | /workspace/28.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/28.xbar_stress_all_with_reset_error.2011765449 |
| Short name | T731 |
| Test name | |
| Test status | |
| Simulation time | 522929902 ps |
| CPU time | 194.78 seconds |
| Started | Aug 13 06:52:41 PM PDT 24 |
| Finished | Aug 13 06:55:55 PM PDT 24 |
| Peak memory | 575676 kb |
| Host | smart-ea350b18-98dd-401c-8592-912e619b0087 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2011765449 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.xbar_stress_al l_with_reset_error.2011765449 |
| Directory | /workspace/28.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/28.xbar_unmapped_addr.635554252 |
| Short name | T2297 |
| Test name | |
| Test status | |
| Simulation time | 109177083 ps |
| CPU time | 15.05 seconds |
| Started | Aug 13 06:52:44 PM PDT 24 |
| Finished | Aug 13 06:52:59 PM PDT 24 |
| Peak memory | 575680 kb |
| Host | smart-fa9c586f-5972-49ec-8ace-ad2fc9f09baf |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=635554252 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.xbar_unmapped_addr.635554252 |
| Directory | /workspace/28.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/29.chip_tl_errors.1022054400 |
| Short name | T752 |
| Test name | |
| Test status | |
| Simulation time | 2923701596 ps |
| CPU time | 190.79 seconds |
| Started | Aug 13 06:52:48 PM PDT 24 |
| Finished | Aug 13 06:55:58 PM PDT 24 |
| Peak memory | 598400 kb |
| Host | smart-2d3dbe79-f60b-4732-bbb2-abfe164ea330 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1022054400 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.chip_tl_errors.1022054400 |
| Directory | /workspace/29.chip_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/29.xbar_access_same_device.3515275745 |
| Short name | T2390 |
| Test name | |
| Test status | |
| Simulation time | 1130369692 ps |
| CPU time | 47.33 seconds |
| Started | Aug 13 06:52:43 PM PDT 24 |
| Finished | Aug 13 06:53:30 PM PDT 24 |
| Peak memory | 575708 kb |
| Host | smart-fb07a759-f7bd-4431-8d96-29c28db137c0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3515275745 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.xbar_access_same_device .3515275745 |
| Directory | /workspace/29.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/29.xbar_access_same_device_slow_rsp.2117980215 |
| Short name | T2602 |
| Test name | |
| Test status | |
| Simulation time | 2537485002 ps |
| CPU time | 43.7 seconds |
| Started | Aug 13 06:52:44 PM PDT 24 |
| Finished | Aug 13 06:53:28 PM PDT 24 |
| Peak memory | 574316 kb |
| Host | smart-97ab5325-9da9-433a-89d2-6113a0bd9e8b |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2117980215 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.xbar_access_same_ device_slow_rsp.2117980215 |
| Directory | /workspace/29.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/29.xbar_error_and_unmapped_addr.2946928147 |
| Short name | T1702 |
| Test name | |
| Test status | |
| Simulation time | 281337325 ps |
| CPU time | 29.11 seconds |
| Started | Aug 13 06:52:40 PM PDT 24 |
| Finished | Aug 13 06:53:09 PM PDT 24 |
| Peak memory | 575496 kb |
| Host | smart-d41a9eaf-2a1f-4f66-9b17-d2bb0bc45fa7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2946928147 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.xbar_error_and_unmapped_add r.2946928147 |
| Directory | /workspace/29.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/29.xbar_error_random.2422891763 |
| Short name | T1526 |
| Test name | |
| Test status | |
| Simulation time | 469100448 ps |
| CPU time | 36.16 seconds |
| Started | Aug 13 06:52:48 PM PDT 24 |
| Finished | Aug 13 06:53:24 PM PDT 24 |
| Peak memory | 575648 kb |
| Host | smart-73dff6f7-77f6-429a-9ee4-7ef176339135 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2422891763 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.xbar_error_random.2422891763 |
| Directory | /workspace/29.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/29.xbar_random.1199346601 |
| Short name | T2606 |
| Test name | |
| Test status | |
| Simulation time | 1895801043 ps |
| CPU time | 66.75 seconds |
| Started | Aug 13 06:52:45 PM PDT 24 |
| Finished | Aug 13 06:53:52 PM PDT 24 |
| Peak memory | 575660 kb |
| Host | smart-dda241ac-8307-461e-8f71-a328c37c3605 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1199346601 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.xbar_random.1199346601 |
| Directory | /workspace/29.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/29.xbar_random_large_delays.3682533677 |
| Short name | T1798 |
| Test name | |
| Test status | |
| Simulation time | 107919547701 ps |
| CPU time | 1250.13 seconds |
| Started | Aug 13 06:52:42 PM PDT 24 |
| Finished | Aug 13 07:13:32 PM PDT 24 |
| Peak memory | 575792 kb |
| Host | smart-624dc61f-ba02-4271-a6b1-c590cf061993 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3682533677 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.xbar_random_large_delays.3682533677 |
| Directory | /workspace/29.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/29.xbar_random_slow_rsp.2430764838 |
| Short name | T1527 |
| Test name | |
| Test status | |
| Simulation time | 3911734839 ps |
| CPU time | 67.76 seconds |
| Started | Aug 13 06:52:42 PM PDT 24 |
| Finished | Aug 13 06:53:50 PM PDT 24 |
| Peak memory | 573684 kb |
| Host | smart-314fd752-95b3-47b8-8118-83bce3d994d1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2430764838 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.xbar_random_slow_rsp.2430764838 |
| Directory | /workspace/29.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/29.xbar_random_zero_delays.571387691 |
| Short name | T1820 |
| Test name | |
| Test status | |
| Simulation time | 566118454 ps |
| CPU time | 46.8 seconds |
| Started | Aug 13 06:52:43 PM PDT 24 |
| Finished | Aug 13 06:53:29 PM PDT 24 |
| Peak memory | 575700 kb |
| Host | smart-2b9aec66-c19e-494f-8881-d53fd5948b51 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=571387691 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.xbar_random_zero_dela ys.571387691 |
| Directory | /workspace/29.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/29.xbar_same_source.657006221 |
| Short name | T2356 |
| Test name | |
| Test status | |
| Simulation time | 872376053 ps |
| CPU time | 27.57 seconds |
| Started | Aug 13 06:52:44 PM PDT 24 |
| Finished | Aug 13 06:53:12 PM PDT 24 |
| Peak memory | 575508 kb |
| Host | smart-7d192bea-f7ca-4b23-9923-5bb21b1d1dda |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=657006221 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.xbar_same_source.657006221 |
| Directory | /workspace/29.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/29.xbar_smoke.2976919047 |
| Short name | T465 |
| Test name | |
| Test status | |
| Simulation time | 34178255 ps |
| CPU time | 5.34 seconds |
| Started | Aug 13 06:52:44 PM PDT 24 |
| Finished | Aug 13 06:52:50 PM PDT 24 |
| Peak memory | 573568 kb |
| Host | smart-6026dc71-cfa4-4589-a62b-7c3019675325 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2976919047 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.xbar_smoke.2976919047 |
| Directory | /workspace/29.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/29.xbar_smoke_large_delays.1966637995 |
| Short name | T1492 |
| Test name | |
| Test status | |
| Simulation time | 10058259329 ps |
| CPU time | 102.65 seconds |
| Started | Aug 13 06:52:46 PM PDT 24 |
| Finished | Aug 13 06:54:28 PM PDT 24 |
| Peak memory | 573696 kb |
| Host | smart-95c69568-b3dc-42a0-908a-01b6074f5369 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1966637995 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.xbar_smoke_large_delays.1966637995 |
| Directory | /workspace/29.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/29.xbar_smoke_slow_rsp.2554831595 |
| Short name | T1739 |
| Test name | |
| Test status | |
| Simulation time | 3268986514 ps |
| CPU time | 54.46 seconds |
| Started | Aug 13 06:52:44 PM PDT 24 |
| Finished | Aug 13 06:53:38 PM PDT 24 |
| Peak memory | 573588 kb |
| Host | smart-87ea9385-a452-4fed-8220-3dc5a1a18d40 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2554831595 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.xbar_smoke_slow_rsp.2554831595 |
| Directory | /workspace/29.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/29.xbar_smoke_zero_delays.3619045865 |
| Short name | T1557 |
| Test name | |
| Test status | |
| Simulation time | 50233685 ps |
| CPU time | 6.42 seconds |
| Started | Aug 13 06:52:42 PM PDT 24 |
| Finished | Aug 13 06:52:48 PM PDT 24 |
| Peak memory | 574228 kb |
| Host | smart-f623ad32-6def-4237-88d4-19c3aecacf65 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3619045865 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.xbar_smoke_zero_delay s.3619045865 |
| Directory | /workspace/29.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/29.xbar_stress_all.554035108 |
| Short name | T2068 |
| Test name | |
| Test status | |
| Simulation time | 1808949543 ps |
| CPU time | 60.02 seconds |
| Started | Aug 13 06:52:43 PM PDT 24 |
| Finished | Aug 13 06:53:43 PM PDT 24 |
| Peak memory | 575764 kb |
| Host | smart-8525ca8e-92db-4631-94a5-562504660cae |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=554035108 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.xbar_stress_all.554035108 |
| Directory | /workspace/29.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/29.xbar_stress_all_with_error.563925449 |
| Short name | T2265 |
| Test name | |
| Test status | |
| Simulation time | 5244311279 ps |
| CPU time | 181.63 seconds |
| Started | Aug 13 06:52:40 PM PDT 24 |
| Finished | Aug 13 06:55:42 PM PDT 24 |
| Peak memory | 575864 kb |
| Host | smart-1e499b82-2d48-4325-9e99-812a76c4c29e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=563925449 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.xbar_stress_all_with_error.563925449 |
| Directory | /workspace/29.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/29.xbar_stress_all_with_rand_reset.298606619 |
| Short name | T2370 |
| Test name | |
| Test status | |
| Simulation time | 5043766224 ps |
| CPU time | 619.51 seconds |
| Started | Aug 13 06:52:46 PM PDT 24 |
| Finished | Aug 13 07:03:05 PM PDT 24 |
| Peak memory | 575632 kb |
| Host | smart-3ee09f3f-6978-4bac-9bbf-56339f166d80 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=298606619 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_res et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.xbar_stress_all_ with_rand_reset.298606619 |
| Directory | /workspace/29.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/29.xbar_unmapped_addr.973216329 |
| Short name | T603 |
| Test name | |
| Test status | |
| Simulation time | 828178825 ps |
| CPU time | 34.07 seconds |
| Started | Aug 13 06:52:47 PM PDT 24 |
| Finished | Aug 13 06:53:21 PM PDT 24 |
| Peak memory | 575572 kb |
| Host | smart-0768dd49-85be-4869-b625-5b6adcdc2fb2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=973216329 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.xbar_unmapped_addr.973216329 |
| Directory | /workspace/29.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/3.chip_csr_aliasing.3230844021 |
| Short name | T1771 |
| Test name | |
| Test status | |
| Simulation time | 71491843860 ps |
| CPU time | 10106 seconds |
| Started | Aug 13 06:50:48 PM PDT 24 |
| Finished | Aug 13 09:39:15 PM PDT 24 |
| Peak memory | 626856 kb |
| Host | smart-eb013fee-2d86-4f62-bcd5-0242b52d7da7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +csr_aliasing +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3230844021 -assert nopostproc +UVM_TESTNAME=chip_ base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/ null -cm_name 3.chip_csr_aliasing.3230844021 |
| Directory | /workspace/3.chip_csr_aliasing/latest |
| Test location | /workspace/coverage/cover_reg_top/3.chip_csr_bit_bash.3671846822 |
| Short name | T1585 |
| Test name | |
| Test status | |
| Simulation time | 11362446296 ps |
| CPU time | 1571.33 seconds |
| Started | Aug 13 06:50:40 PM PDT 24 |
| Finished | Aug 13 07:16:51 PM PDT 24 |
| Peak memory | 589648 kb |
| Host | smart-22903973-9b91-45df-82c3-51c0eb1ca556 |
| User | root |
| Command | /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +num_test_csrs=200 +csr_bit_bash +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3671846822 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to p.vdb -cm_log /dev/null -cm_name 3.chip_csr_bit_bash.3671846822 |
| Directory | /workspace/3.chip_csr_bit_bash/latest |
| Test location | /workspace/coverage/cover_reg_top/3.chip_csr_mem_rw_with_rand_reset.4019670591 |
| Short name | T2165 |
| Test name | |
| Test status | |
| Simulation time | 7715820406 ps |
| CPU time | 435.5 seconds |
| Started | Aug 13 06:50:54 PM PDT 24 |
| Finished | Aug 13 06:58:10 PM PDT 24 |
| Peak memory | 637780 kb |
| Host | smart-eda1ce2f-a540-418e-855e-077c11f55d60 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4019670591 -assert nopostproc + UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top .vdb -cm_log /dev/null -cm_name 3.chip_csr_mem_rw_with_rand_reset.4019670591 |
| Directory | /workspace/3.chip_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/3.chip_csr_rw.2237715275 |
| Short name | T2753 |
| Test name | |
| Test status | |
| Simulation time | 4242729925 ps |
| CPU time | 392.36 seconds |
| Started | Aug 13 06:51:07 PM PDT 24 |
| Finished | Aug 13 06:57:40 PM PDT 24 |
| Peak memory | 598420 kb |
| Host | smart-46860a00-d2cf-4ac1-b213-a6140719b821 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2237715275 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.chip_csr_rw.2237715275 |
| Directory | /workspace/3.chip_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/3.chip_tl_errors.422904709 |
| Short name | T756 |
| Test name | |
| Test status | |
| Simulation time | 3800303258 ps |
| CPU time | 400.99 seconds |
| Started | Aug 13 06:50:56 PM PDT 24 |
| Finished | Aug 13 06:57:37 PM PDT 24 |
| Peak memory | 599648 kb |
| Host | smart-84c5647d-3486-4b65-9d51-dfa8a947bdd8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=422904709 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.chip_tl_errors.422904709 |
| Directory | /workspace/3.chip_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/3.xbar_access_same_device.1384478018 |
| Short name | T2863 |
| Test name | |
| Test status | |
| Simulation time | 452846047 ps |
| CPU time | 34.46 seconds |
| Started | Aug 13 06:50:55 PM PDT 24 |
| Finished | Aug 13 06:51:30 PM PDT 24 |
| Peak memory | 575712 kb |
| Host | smart-a8a2d86e-398e-44c4-b60c-c2f984d46b5b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1384478018 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.xbar_access_same_device. 1384478018 |
| Directory | /workspace/3.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/3.xbar_error_and_unmapped_addr.3710361945 |
| Short name | T1442 |
| Test name | |
| Test status | |
| Simulation time | 278435771 ps |
| CPU time | 11.71 seconds |
| Started | Aug 13 06:50:49 PM PDT 24 |
| Finished | Aug 13 06:51:00 PM PDT 24 |
| Peak memory | 575672 kb |
| Host | smart-f320a83f-d437-4ed4-9a5d-7824a1b3aa7e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3710361945 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.xbar_error_and_unmapped_addr .3710361945 |
| Directory | /workspace/3.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/3.xbar_random.1495871034 |
| Short name | T491 |
| Test name | |
| Test status | |
| Simulation time | 428759839 ps |
| CPU time | 35.43 seconds |
| Started | Aug 13 06:50:57 PM PDT 24 |
| Finished | Aug 13 06:51:33 PM PDT 24 |
| Peak memory | 575552 kb |
| Host | smart-24b5c6d4-0207-4cb1-9a62-d925f759a309 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1495871034 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.xbar_random.1495871034 |
| Directory | /workspace/3.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/3.xbar_random_large_delays.962013716 |
| Short name | T1748 |
| Test name | |
| Test status | |
| Simulation time | 27298706138 ps |
| CPU time | 273.67 seconds |
| Started | Aug 13 06:51:00 PM PDT 24 |
| Finished | Aug 13 06:55:34 PM PDT 24 |
| Peak memory | 575744 kb |
| Host | smart-a5f25ae3-b67c-48ec-8821-2fd443f76141 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=962013716 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.xbar_random_large_delays.962013716 |
| Directory | /workspace/3.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/3.xbar_random_slow_rsp.3716506813 |
| Short name | T2331 |
| Test name | |
| Test status | |
| Simulation time | 39697766205 ps |
| CPU time | 664.09 seconds |
| Started | Aug 13 06:50:48 PM PDT 24 |
| Finished | Aug 13 07:01:52 PM PDT 24 |
| Peak memory | 575644 kb |
| Host | smart-69e79293-3135-42cd-b260-16acbc686329 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3716506813 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.xbar_random_slow_rsp.3716506813 |
| Directory | /workspace/3.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/3.xbar_random_zero_delays.1271517651 |
| Short name | T1737 |
| Test name | |
| Test status | |
| Simulation time | 39784123 ps |
| CPU time | 6.46 seconds |
| Started | Aug 13 06:50:45 PM PDT 24 |
| Finished | Aug 13 06:50:51 PM PDT 24 |
| Peak memory | 574268 kb |
| Host | smart-8b826a9d-2ee6-4dc2-a323-103efcd3c1e5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1271517651 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.xbar_random_zero_dela ys.1271517651 |
| Directory | /workspace/3.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/3.xbar_same_source.1665178035 |
| Short name | T531 |
| Test name | |
| Test status | |
| Simulation time | 496983541 ps |
| CPU time | 33.47 seconds |
| Started | Aug 13 06:50:51 PM PDT 24 |
| Finished | Aug 13 06:51:24 PM PDT 24 |
| Peak memory | 575612 kb |
| Host | smart-4af3d549-a9bd-4754-b9c1-4d3cd066e838 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1665178035 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.xbar_same_source.1665178035 |
| Directory | /workspace/3.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/3.xbar_smoke.463264720 |
| Short name | T2097 |
| Test name | |
| Test status | |
| Simulation time | 174140513 ps |
| CPU time | 7.93 seconds |
| Started | Aug 13 06:50:52 PM PDT 24 |
| Finished | Aug 13 06:51:00 PM PDT 24 |
| Peak memory | 573576 kb |
| Host | smart-de7b1221-2e6b-451e-a9bb-7fa5a2d20f8b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=463264720 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.xbar_smoke.463264720 |
| Directory | /workspace/3.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/3.xbar_smoke_large_delays.3988538992 |
| Short name | T2181 |
| Test name | |
| Test status | |
| Simulation time | 8144190608 ps |
| CPU time | 88.24 seconds |
| Started | Aug 13 06:50:50 PM PDT 24 |
| Finished | Aug 13 06:52:19 PM PDT 24 |
| Peak memory | 573560 kb |
| Host | smart-c442c486-6912-4a4a-bf2d-6075ca9ee2e5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3988538992 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.xbar_smoke_large_delays.3988538992 |
| Directory | /workspace/3.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/3.xbar_smoke_slow_rsp.253436038 |
| Short name | T2821 |
| Test name | |
| Test status | |
| Simulation time | 5043605947 ps |
| CPU time | 87.39 seconds |
| Started | Aug 13 06:50:36 PM PDT 24 |
| Finished | Aug 13 06:52:03 PM PDT 24 |
| Peak memory | 573616 kb |
| Host | smart-81870d17-7eeb-4926-b10d-1c4068d553b8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=253436038 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.xbar_smoke_slow_rsp.253436038 |
| Directory | /workspace/3.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/3.xbar_smoke_zero_delays.2442054976 |
| Short name | T1497 |
| Test name | |
| Test status | |
| Simulation time | 49523016 ps |
| CPU time | 6.39 seconds |
| Started | Aug 13 06:50:57 PM PDT 24 |
| Finished | Aug 13 06:51:04 PM PDT 24 |
| Peak memory | 573552 kb |
| Host | smart-bcb0c599-165b-482e-a557-f4cda9c22308 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2442054976 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.xbar_smoke_zero_delays .2442054976 |
| Directory | /workspace/3.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/3.xbar_stress_all.389441235 |
| Short name | T500 |
| Test name | |
| Test status | |
| Simulation time | 4026094681 ps |
| CPU time | 117.75 seconds |
| Started | Aug 13 06:50:41 PM PDT 24 |
| Finished | Aug 13 06:52:39 PM PDT 24 |
| Peak memory | 575636 kb |
| Host | smart-15675fc7-cab7-4435-9c6b-b424ad5000da |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=389441235 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.xbar_stress_all.389441235 |
| Directory | /workspace/3.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/3.xbar_stress_all_with_error.3546700232 |
| Short name | T2809 |
| Test name | |
| Test status | |
| Simulation time | 1761980589 ps |
| CPU time | 134.09 seconds |
| Started | Aug 13 06:50:53 PM PDT 24 |
| Finished | Aug 13 06:53:07 PM PDT 24 |
| Peak memory | 575976 kb |
| Host | smart-626bb335-e5dd-48ae-b559-026ca4d0cacd |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3546700232 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.xbar_stress_all_with_error.3546700232 |
| Directory | /workspace/3.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/3.xbar_stress_all_with_rand_reset.2267589364 |
| Short name | T2875 |
| Test name | |
| Test status | |
| Simulation time | 127353866 ps |
| CPU time | 58.57 seconds |
| Started | Aug 13 06:50:52 PM PDT 24 |
| Finished | Aug 13 06:51:51 PM PDT 24 |
| Peak memory | 575632 kb |
| Host | smart-2c7c2584-8a7a-4aca-b44c-23208120396b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2267589364 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.xbar_stress_all_ with_rand_reset.2267589364 |
| Directory | /workspace/3.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/3.xbar_stress_all_with_reset_error.3375680400 |
| Short name | T928 |
| Test name | |
| Test status | |
| Simulation time | 412986404 ps |
| CPU time | 102.66 seconds |
| Started | Aug 13 06:50:49 PM PDT 24 |
| Finished | Aug 13 06:52:32 PM PDT 24 |
| Peak memory | 575436 kb |
| Host | smart-cce409cf-5148-4021-ba62-888c33b14c3f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3375680400 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.xbar_stress_all _with_reset_error.3375680400 |
| Directory | /workspace/3.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/3.xbar_unmapped_addr.3685577687 |
| Short name | T651 |
| Test name | |
| Test status | |
| Simulation time | 581314637 ps |
| CPU time | 24.73 seconds |
| Started | Aug 13 06:50:46 PM PDT 24 |
| Finished | Aug 13 06:51:11 PM PDT 24 |
| Peak memory | 575584 kb |
| Host | smart-0c03ab7a-12b0-4b8a-a8af-5d4f68337802 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3685577687 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.xbar_unmapped_addr.3685577687 |
| Directory | /workspace/3.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/30.xbar_access_same_device.3143827807 |
| Short name | T872 |
| Test name | |
| Test status | |
| Simulation time | 2210935445 ps |
| CPU time | 88.65 seconds |
| Started | Aug 13 06:52:51 PM PDT 24 |
| Finished | Aug 13 06:54:19 PM PDT 24 |
| Peak memory | 575664 kb |
| Host | smart-a83e8a0d-10fd-4140-9798-8088fa895083 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3143827807 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.xbar_access_same_device .3143827807 |
| Directory | /workspace/30.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/30.xbar_access_same_device_slow_rsp.1451493326 |
| Short name | T2189 |
| Test name | |
| Test status | |
| Simulation time | 107393579317 ps |
| CPU time | 2101.14 seconds |
| Started | Aug 13 06:52:50 PM PDT 24 |
| Finished | Aug 13 07:27:52 PM PDT 24 |
| Peak memory | 575840 kb |
| Host | smart-1947189b-0c88-4980-90c3-c0fd9ce1f127 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1451493326 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.xbar_access_same_ device_slow_rsp.1451493326 |
| Directory | /workspace/30.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/30.xbar_error_and_unmapped_addr.164219895 |
| Short name | T1965 |
| Test name | |
| Test status | |
| Simulation time | 123303895 ps |
| CPU time | 14.66 seconds |
| Started | Aug 13 06:52:47 PM PDT 24 |
| Finished | Aug 13 06:53:02 PM PDT 24 |
| Peak memory | 575620 kb |
| Host | smart-25385203-f3d8-413d-9f47-28c39516054d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=164219895 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.xbar_error_and_unmapped_addr .164219895 |
| Directory | /workspace/30.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/30.xbar_error_random.3095726865 |
| Short name | T2431 |
| Test name | |
| Test status | |
| Simulation time | 1067737309 ps |
| CPU time | 30.14 seconds |
| Started | Aug 13 06:52:48 PM PDT 24 |
| Finished | Aug 13 06:53:18 PM PDT 24 |
| Peak memory | 575636 kb |
| Host | smart-c7c19647-1d96-4c41-8771-e7a25cdd4928 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3095726865 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.xbar_error_random.3095726865 |
| Directory | /workspace/30.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/30.xbar_random.1294734450 |
| Short name | T2539 |
| Test name | |
| Test status | |
| Simulation time | 1864446538 ps |
| CPU time | 61.05 seconds |
| Started | Aug 13 06:52:48 PM PDT 24 |
| Finished | Aug 13 06:53:49 PM PDT 24 |
| Peak memory | 575552 kb |
| Host | smart-e99d142c-0c5f-481f-aa14-db0a49476487 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1294734450 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.xbar_random.1294734450 |
| Directory | /workspace/30.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/30.xbar_random_large_delays.1871567655 |
| Short name | T1655 |
| Test name | |
| Test status | |
| Simulation time | 8188078877 ps |
| CPU time | 93.18 seconds |
| Started | Aug 13 06:52:47 PM PDT 24 |
| Finished | Aug 13 06:54:20 PM PDT 24 |
| Peak memory | 573744 kb |
| Host | smart-fe66da8c-7815-487a-aafd-cd511545c563 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1871567655 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.xbar_random_large_delays.1871567655 |
| Directory | /workspace/30.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/30.xbar_random_slow_rsp.3582183368 |
| Short name | T2040 |
| Test name | |
| Test status | |
| Simulation time | 56336758707 ps |
| CPU time | 1069.21 seconds |
| Started | Aug 13 06:52:49 PM PDT 24 |
| Finished | Aug 13 07:10:39 PM PDT 24 |
| Peak memory | 575796 kb |
| Host | smart-fc420f14-b9c7-4644-af7b-1f67901306da |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3582183368 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.xbar_random_slow_rsp.3582183368 |
| Directory | /workspace/30.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/30.xbar_random_zero_delays.253803354 |
| Short name | T2131 |
| Test name | |
| Test status | |
| Simulation time | 332468955 ps |
| CPU time | 27.74 seconds |
| Started | Aug 13 06:52:51 PM PDT 24 |
| Finished | Aug 13 06:53:19 PM PDT 24 |
| Peak memory | 575684 kb |
| Host | smart-31cf7903-3294-41ea-8a94-b2d6bf3e9e9c |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=253803354 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.xbar_random_zero_dela ys.253803354 |
| Directory | /workspace/30.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/30.xbar_same_source.495768102 |
| Short name | T1873 |
| Test name | |
| Test status | |
| Simulation time | 261271710 ps |
| CPU time | 19.45 seconds |
| Started | Aug 13 06:52:48 PM PDT 24 |
| Finished | Aug 13 06:53:07 PM PDT 24 |
| Peak memory | 575680 kb |
| Host | smart-69d47f1b-88eb-47d1-936e-dfb36bacf26e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=495768102 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.xbar_same_source.495768102 |
| Directory | /workspace/30.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/30.xbar_smoke.187753531 |
| Short name | T2742 |
| Test name | |
| Test status | |
| Simulation time | 57999862 ps |
| CPU time | 6.64 seconds |
| Started | Aug 13 06:52:55 PM PDT 24 |
| Finished | Aug 13 06:53:02 PM PDT 24 |
| Peak memory | 573608 kb |
| Host | smart-fce14a1a-6f54-447c-ae64-4e317bbee5c9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=187753531 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.xbar_smoke.187753531 |
| Directory | /workspace/30.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/30.xbar_smoke_large_delays.1136516201 |
| Short name | T1732 |
| Test name | |
| Test status | |
| Simulation time | 9308207663 ps |
| CPU time | 98.44 seconds |
| Started | Aug 13 06:52:50 PM PDT 24 |
| Finished | Aug 13 06:54:29 PM PDT 24 |
| Peak memory | 574280 kb |
| Host | smart-8520a820-0eea-4e3d-89ea-cbf8f15016b7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1136516201 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.xbar_smoke_large_delays.1136516201 |
| Directory | /workspace/30.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/30.xbar_smoke_slow_rsp.3870454279 |
| Short name | T1453 |
| Test name | |
| Test status | |
| Simulation time | 3139736025 ps |
| CPU time | 53.6 seconds |
| Started | Aug 13 06:52:47 PM PDT 24 |
| Finished | Aug 13 06:53:41 PM PDT 24 |
| Peak memory | 573548 kb |
| Host | smart-27415aa4-30e8-44e7-90ae-603b22c7a85b |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3870454279 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.xbar_smoke_slow_rsp.3870454279 |
| Directory | /workspace/30.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/30.xbar_smoke_zero_delays.2886872266 |
| Short name | T2856 |
| Test name | |
| Test status | |
| Simulation time | 57424063 ps |
| CPU time | 7.41 seconds |
| Started | Aug 13 06:52:49 PM PDT 24 |
| Finished | Aug 13 06:52:56 PM PDT 24 |
| Peak memory | 573532 kb |
| Host | smart-6bb8d458-c41f-439e-9291-c8ac746a5cba |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2886872266 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.xbar_smoke_zero_delay s.2886872266 |
| Directory | /workspace/30.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/30.xbar_stress_all_with_error.3317851253 |
| Short name | T2871 |
| Test name | |
| Test status | |
| Simulation time | 2208966165 ps |
| CPU time | 176.47 seconds |
| Started | Aug 13 06:52:50 PM PDT 24 |
| Finished | Aug 13 06:55:46 PM PDT 24 |
| Peak memory | 575604 kb |
| Host | smart-58f54434-cc53-442d-ab7d-7c77bab6cb51 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3317851253 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.xbar_stress_all_with_error.3317851253 |
| Directory | /workspace/30.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/30.xbar_stress_all_with_reset_error.3674059787 |
| Short name | T935 |
| Test name | |
| Test status | |
| Simulation time | 5180687344 ps |
| CPU time | 315.87 seconds |
| Started | Aug 13 06:52:50 PM PDT 24 |
| Finished | Aug 13 06:58:06 PM PDT 24 |
| Peak memory | 576580 kb |
| Host | smart-1578071f-2a7f-4963-8986-74f9bf6ab9fc |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3674059787 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.xbar_stress_al l_with_reset_error.3674059787 |
| Directory | /workspace/30.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/30.xbar_unmapped_addr.298805159 |
| Short name | T2186 |
| Test name | |
| Test status | |
| Simulation time | 1151750303 ps |
| CPU time | 53.73 seconds |
| Started | Aug 13 06:52:49 PM PDT 24 |
| Finished | Aug 13 06:53:43 PM PDT 24 |
| Peak memory | 575668 kb |
| Host | smart-5e67bc58-176e-435b-8aa2-6a3347938018 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=298805159 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.xbar_unmapped_addr.298805159 |
| Directory | /workspace/30.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/31.xbar_access_same_device.1113939315 |
| Short name | T1579 |
| Test name | |
| Test status | |
| Simulation time | 580910556 ps |
| CPU time | 40.85 seconds |
| Started | Aug 13 06:52:56 PM PDT 24 |
| Finished | Aug 13 06:53:37 PM PDT 24 |
| Peak memory | 576384 kb |
| Host | smart-cfbcb432-4294-4b15-abdd-e099e7f4d2a8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1113939315 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.xbar_access_same_device .1113939315 |
| Directory | /workspace/31.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/31.xbar_access_same_device_slow_rsp.658073262 |
| Short name | T899 |
| Test name | |
| Test status | |
| Simulation time | 49615035183 ps |
| CPU time | 821.83 seconds |
| Started | Aug 13 06:52:55 PM PDT 24 |
| Finished | Aug 13 07:06:37 PM PDT 24 |
| Peak memory | 575824 kb |
| Host | smart-35a6ecf2-c730-40e4-b086-f32ad6bfdb98 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=658073262 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.xbar_access_same_d evice_slow_rsp.658073262 |
| Directory | /workspace/31.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/31.xbar_error_and_unmapped_addr.2940040580 |
| Short name | T1461 |
| Test name | |
| Test status | |
| Simulation time | 97353945 ps |
| CPU time | 11.79 seconds |
| Started | Aug 13 06:53:06 PM PDT 24 |
| Finished | Aug 13 06:53:17 PM PDT 24 |
| Peak memory | 575656 kb |
| Host | smart-b1c012cc-d781-4fa0-9ca5-15bc91c8a438 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2940040580 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.xbar_error_and_unmapped_add r.2940040580 |
| Directory | /workspace/31.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/31.xbar_error_random.2503486123 |
| Short name | T1457 |
| Test name | |
| Test status | |
| Simulation time | 1836313834 ps |
| CPU time | 58.27 seconds |
| Started | Aug 13 06:53:06 PM PDT 24 |
| Finished | Aug 13 06:54:04 PM PDT 24 |
| Peak memory | 575720 kb |
| Host | smart-e4700b43-27be-49fb-b0bd-bd8172c389ca |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2503486123 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.xbar_error_random.2503486123 |
| Directory | /workspace/31.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/31.xbar_random.2513489735 |
| Short name | T1790 |
| Test name | |
| Test status | |
| Simulation time | 1018787559 ps |
| CPU time | 39.89 seconds |
| Started | Aug 13 06:52:54 PM PDT 24 |
| Finished | Aug 13 06:53:34 PM PDT 24 |
| Peak memory | 575628 kb |
| Host | smart-fb429400-7a4c-43ba-8aac-5de8c53ed3ee |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2513489735 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.xbar_random.2513489735 |
| Directory | /workspace/31.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/31.xbar_random_large_delays.301527553 |
| Short name | T710 |
| Test name | |
| Test status | |
| Simulation time | 58465234120 ps |
| CPU time | 619.45 seconds |
| Started | Aug 13 06:52:57 PM PDT 24 |
| Finished | Aug 13 07:03:16 PM PDT 24 |
| Peak memory | 575788 kb |
| Host | smart-2c882bc7-2c91-46e3-8fc1-cd6b5995c71b |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=301527553 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.xbar_random_large_delays.301527553 |
| Directory | /workspace/31.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/31.xbar_random_slow_rsp.553202991 |
| Short name | T2787 |
| Test name | |
| Test status | |
| Simulation time | 28539563300 ps |
| CPU time | 491.64 seconds |
| Started | Aug 13 06:52:58 PM PDT 24 |
| Finished | Aug 13 07:01:09 PM PDT 24 |
| Peak memory | 575616 kb |
| Host | smart-0e2cad53-0563-469d-a878-fdf2523ba182 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=553202991 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.xbar_random_slow_rsp.553202991 |
| Directory | /workspace/31.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/31.xbar_random_zero_delays.2341234389 |
| Short name | T2070 |
| Test name | |
| Test status | |
| Simulation time | 81720075 ps |
| CPU time | 8.69 seconds |
| Started | Aug 13 06:52:54 PM PDT 24 |
| Finished | Aug 13 06:53:03 PM PDT 24 |
| Peak memory | 575628 kb |
| Host | smart-88d554f0-bfc4-4d38-9a7f-fb46af79b8a8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2341234389 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.xbar_random_zero_del ays.2341234389 |
| Directory | /workspace/31.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/31.xbar_same_source.1535120822 |
| Short name | T1944 |
| Test name | |
| Test status | |
| Simulation time | 254449308 ps |
| CPU time | 10.61 seconds |
| Started | Aug 13 06:52:55 PM PDT 24 |
| Finished | Aug 13 06:53:06 PM PDT 24 |
| Peak memory | 575456 kb |
| Host | smart-77c273b6-700c-46bd-93fb-a95790779b8a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1535120822 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.xbar_same_source.1535120822 |
| Directory | /workspace/31.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/31.xbar_smoke.826544396 |
| Short name | T2792 |
| Test name | |
| Test status | |
| Simulation time | 204377407 ps |
| CPU time | 9.45 seconds |
| Started | Aug 13 06:52:49 PM PDT 24 |
| Finished | Aug 13 06:52:58 PM PDT 24 |
| Peak memory | 573588 kb |
| Host | smart-be124847-ae4e-4876-b6eb-893033b05932 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=826544396 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.xbar_smoke.826544396 |
| Directory | /workspace/31.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/31.xbar_smoke_large_delays.2936124063 |
| Short name | T1876 |
| Test name | |
| Test status | |
| Simulation time | 8107224619 ps |
| CPU time | 81.23 seconds |
| Started | Aug 13 06:53:06 PM PDT 24 |
| Finished | Aug 13 06:54:27 PM PDT 24 |
| Peak memory | 573676 kb |
| Host | smart-5ecae675-2fc4-421d-9756-74e24a14382c |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2936124063 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.xbar_smoke_large_delays.2936124063 |
| Directory | /workspace/31.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/31.xbar_smoke_slow_rsp.3590171066 |
| Short name | T2828 |
| Test name | |
| Test status | |
| Simulation time | 4522889196 ps |
| CPU time | 77.92 seconds |
| Started | Aug 13 06:52:53 PM PDT 24 |
| Finished | Aug 13 06:54:11 PM PDT 24 |
| Peak memory | 573656 kb |
| Host | smart-a491a231-5534-42b8-887c-854e8f8ffafd |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3590171066 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.xbar_smoke_slow_rsp.3590171066 |
| Directory | /workspace/31.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/31.xbar_smoke_zero_delays.3433802841 |
| Short name | T1494 |
| Test name | |
| Test status | |
| Simulation time | 55336234 ps |
| CPU time | 6.73 seconds |
| Started | Aug 13 06:52:56 PM PDT 24 |
| Finished | Aug 13 06:53:03 PM PDT 24 |
| Peak memory | 573436 kb |
| Host | smart-fb45ca51-3414-45f0-9ff1-55522b7b76e1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3433802841 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.xbar_smoke_zero_delay s.3433802841 |
| Directory | /workspace/31.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/31.xbar_stress_all.1780800883 |
| Short name | T2005 |
| Test name | |
| Test status | |
| Simulation time | 443888108 ps |
| CPU time | 56.37 seconds |
| Started | Aug 13 06:52:54 PM PDT 24 |
| Finished | Aug 13 06:53:50 PM PDT 24 |
| Peak memory | 575720 kb |
| Host | smart-fe6eaddc-aaf1-455d-8a86-5b3b80db71ad |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1780800883 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.xbar_stress_all.1780800883 |
| Directory | /workspace/31.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/31.xbar_stress_all_with_error.1055864099 |
| Short name | T1610 |
| Test name | |
| Test status | |
| Simulation time | 842844549 ps |
| CPU time | 71.44 seconds |
| Started | Aug 13 06:53:06 PM PDT 24 |
| Finished | Aug 13 06:54:17 PM PDT 24 |
| Peak memory | 575860 kb |
| Host | smart-683ef2c4-2060-425b-b4ca-e759e4395cf3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1055864099 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.xbar_stress_all_with_error.1055864099 |
| Directory | /workspace/31.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/31.xbar_stress_all_with_rand_reset.1625188202 |
| Short name | T521 |
| Test name | |
| Test status | |
| Simulation time | 3640325250 ps |
| CPU time | 468.08 seconds |
| Started | Aug 13 06:52:54 PM PDT 24 |
| Finished | Aug 13 07:00:43 PM PDT 24 |
| Peak memory | 576480 kb |
| Host | smart-9f0c69bf-f477-4b10-aa04-f551d708d2cb |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1625188202 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.xbar_stress_all _with_rand_reset.1625188202 |
| Directory | /workspace/31.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/31.xbar_stress_all_with_reset_error.2087622814 |
| Short name | T902 |
| Test name | |
| Test status | |
| Simulation time | 209840271 ps |
| CPU time | 90.71 seconds |
| Started | Aug 13 06:52:56 PM PDT 24 |
| Finished | Aug 13 06:54:27 PM PDT 24 |
| Peak memory | 576492 kb |
| Host | smart-7a41c6d8-1b89-45a3-acd8-0be5262e7b2b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2087622814 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.xbar_stress_al l_with_reset_error.2087622814 |
| Directory | /workspace/31.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/31.xbar_unmapped_addr.948314949 |
| Short name | T678 |
| Test name | |
| Test status | |
| Simulation time | 190666865 ps |
| CPU time | 25.38 seconds |
| Started | Aug 13 06:52:58 PM PDT 24 |
| Finished | Aug 13 06:53:23 PM PDT 24 |
| Peak memory | 575696 kb |
| Host | smart-78bac26a-2d2a-4007-b47b-76fbdf8d669f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=948314949 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.xbar_unmapped_addr.948314949 |
| Directory | /workspace/31.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/32.xbar_access_same_device.3986166232 |
| Short name | T1998 |
| Test name | |
| Test status | |
| Simulation time | 1167719381 ps |
| CPU time | 82.85 seconds |
| Started | Aug 13 06:52:57 PM PDT 24 |
| Finished | Aug 13 06:54:20 PM PDT 24 |
| Peak memory | 575724 kb |
| Host | smart-9b79392a-46a8-48b8-9b53-49a7d49680ba |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3986166232 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.xbar_access_same_device .3986166232 |
| Directory | /workspace/32.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/32.xbar_access_same_device_slow_rsp.3460299120 |
| Short name | T896 |
| Test name | |
| Test status | |
| Simulation time | 20776021706 ps |
| CPU time | 343.04 seconds |
| Started | Aug 13 06:53:04 PM PDT 24 |
| Finished | Aug 13 06:58:47 PM PDT 24 |
| Peak memory | 575548 kb |
| Host | smart-b872ec82-62cb-49aa-8874-5d0b6ddcd92a |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3460299120 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.xbar_access_same_ device_slow_rsp.3460299120 |
| Directory | /workspace/32.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/32.xbar_error_and_unmapped_addr.3134815931 |
| Short name | T1804 |
| Test name | |
| Test status | |
| Simulation time | 244717086 ps |
| CPU time | 27.87 seconds |
| Started | Aug 13 06:53:04 PM PDT 24 |
| Finished | Aug 13 06:53:32 PM PDT 24 |
| Peak memory | 575724 kb |
| Host | smart-e9894123-a88e-4518-a54a-ce6b6ba0aee0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3134815931 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.xbar_error_and_unmapped_add r.3134815931 |
| Directory | /workspace/32.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/32.xbar_error_random.2551689721 |
| Short name | T2250 |
| Test name | |
| Test status | |
| Simulation time | 2714856727 ps |
| CPU time | 104.83 seconds |
| Started | Aug 13 06:53:04 PM PDT 24 |
| Finished | Aug 13 06:54:49 PM PDT 24 |
| Peak memory | 575704 kb |
| Host | smart-5fcab743-2e83-4339-a1cf-f72c3da288a6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2551689721 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.xbar_error_random.2551689721 |
| Directory | /workspace/32.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/32.xbar_random.2188318583 |
| Short name | T1896 |
| Test name | |
| Test status | |
| Simulation time | 466694820 ps |
| CPU time | 21.84 seconds |
| Started | Aug 13 06:52:54 PM PDT 24 |
| Finished | Aug 13 06:53:16 PM PDT 24 |
| Peak memory | 575512 kb |
| Host | smart-c84a9747-88d9-4eba-b88c-a5de61f2e73b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2188318583 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.xbar_random.2188318583 |
| Directory | /workspace/32.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/32.xbar_random_large_delays.962242741 |
| Short name | T936 |
| Test name | |
| Test status | |
| Simulation time | 5767598681 ps |
| CPU time | 61.03 seconds |
| Started | Aug 13 06:52:55 PM PDT 24 |
| Finished | Aug 13 06:53:56 PM PDT 24 |
| Peak memory | 573700 kb |
| Host | smart-9f10f8a3-1623-4f14-9a3e-cbb7fc6bb018 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=962242741 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.xbar_random_large_delays.962242741 |
| Directory | /workspace/32.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/32.xbar_random_slow_rsp.2035985733 |
| Short name | T2790 |
| Test name | |
| Test status | |
| Simulation time | 43328396737 ps |
| CPU time | 768.79 seconds |
| Started | Aug 13 06:52:55 PM PDT 24 |
| Finished | Aug 13 07:05:45 PM PDT 24 |
| Peak memory | 575788 kb |
| Host | smart-f054a8e8-ebf9-4e80-876b-59c75b7ab325 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2035985733 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.xbar_random_slow_rsp.2035985733 |
| Directory | /workspace/32.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/32.xbar_random_zero_delays.2168000247 |
| Short name | T2855 |
| Test name | |
| Test status | |
| Simulation time | 207690696 ps |
| CPU time | 17.19 seconds |
| Started | Aug 13 06:52:54 PM PDT 24 |
| Finished | Aug 13 06:53:12 PM PDT 24 |
| Peak memory | 575532 kb |
| Host | smart-a70ca101-b2ff-4fde-829e-66f2623904ed |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2168000247 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.xbar_random_zero_del ays.2168000247 |
| Directory | /workspace/32.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/32.xbar_same_source.1310255179 |
| Short name | T689 |
| Test name | |
| Test status | |
| Simulation time | 269279407 ps |
| CPU time | 10.78 seconds |
| Started | Aug 13 06:53:03 PM PDT 24 |
| Finished | Aug 13 06:53:14 PM PDT 24 |
| Peak memory | 575576 kb |
| Host | smart-a9016997-82af-4bb5-9f56-f4f87bfb86b0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1310255179 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.xbar_same_source.1310255179 |
| Directory | /workspace/32.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/32.xbar_smoke.306149145 |
| Short name | T1691 |
| Test name | |
| Test status | |
| Simulation time | 200281378 ps |
| CPU time | 7.98 seconds |
| Started | Aug 13 06:52:53 PM PDT 24 |
| Finished | Aug 13 06:53:01 PM PDT 24 |
| Peak memory | 574240 kb |
| Host | smart-3225a3b0-cbec-483d-8958-dec1625a5913 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=306149145 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.xbar_smoke.306149145 |
| Directory | /workspace/32.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/32.xbar_smoke_large_delays.447765841 |
| Short name | T595 |
| Test name | |
| Test status | |
| Simulation time | 6453749437 ps |
| CPU time | 64.44 seconds |
| Started | Aug 13 06:52:56 PM PDT 24 |
| Finished | Aug 13 06:54:00 PM PDT 24 |
| Peak memory | 573628 kb |
| Host | smart-748caca9-6aa3-437b-bb6d-fe87dcb59548 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=447765841 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.xbar_smoke_large_delays.447765841 |
| Directory | /workspace/32.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/32.xbar_smoke_slow_rsp.4250688360 |
| Short name | T605 |
| Test name | |
| Test status | |
| Simulation time | 4295191381 ps |
| CPU time | 72.23 seconds |
| Started | Aug 13 06:52:59 PM PDT 24 |
| Finished | Aug 13 06:54:11 PM PDT 24 |
| Peak memory | 573676 kb |
| Host | smart-3f27014d-887f-475f-ad4a-b5519265487b |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4250688360 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.xbar_smoke_slow_rsp.4250688360 |
| Directory | /workspace/32.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/32.xbar_smoke_zero_delays.4223720107 |
| Short name | T2647 |
| Test name | |
| Test status | |
| Simulation time | 52283829 ps |
| CPU time | 6.4 seconds |
| Started | Aug 13 06:52:55 PM PDT 24 |
| Finished | Aug 13 06:53:02 PM PDT 24 |
| Peak memory | 573592 kb |
| Host | smart-db901b68-76d5-43cd-97ee-4dd9a741d576 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4223720107 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.xbar_smoke_zero_delay s.4223720107 |
| Directory | /workspace/32.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/32.xbar_stress_all.1511479597 |
| Short name | T2400 |
| Test name | |
| Test status | |
| Simulation time | 11778252962 ps |
| CPU time | 474.69 seconds |
| Started | Aug 13 06:53:02 PM PDT 24 |
| Finished | Aug 13 07:00:57 PM PDT 24 |
| Peak memory | 576540 kb |
| Host | smart-1821fcf8-8e1a-40d3-b49e-755d8c86acfc |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1511479597 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.xbar_stress_all.1511479597 |
| Directory | /workspace/32.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/32.xbar_stress_all_with_error.1066653672 |
| Short name | T1574 |
| Test name | |
| Test status | |
| Simulation time | 11519085727 ps |
| CPU time | 376.96 seconds |
| Started | Aug 13 06:53:02 PM PDT 24 |
| Finished | Aug 13 06:59:19 PM PDT 24 |
| Peak memory | 575724 kb |
| Host | smart-09afcc0d-1707-49d5-97d7-995820e6e4c5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1066653672 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.xbar_stress_all_with_error.1066653672 |
| Directory | /workspace/32.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/32.xbar_stress_all_with_rand_reset.3124766750 |
| Short name | T2795 |
| Test name | |
| Test status | |
| Simulation time | 3357126686 ps |
| CPU time | 287.19 seconds |
| Started | Aug 13 06:53:01 PM PDT 24 |
| Finished | Aug 13 06:57:48 PM PDT 24 |
| Peak memory | 575676 kb |
| Host | smart-7733d265-2547-47dd-99f4-af29d1dc83ae |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3124766750 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.xbar_stress_all _with_rand_reset.3124766750 |
| Directory | /workspace/32.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/32.xbar_stress_all_with_reset_error.882397820 |
| Short name | T1913 |
| Test name | |
| Test status | |
| Simulation time | 1473689078 ps |
| CPU time | 153.95 seconds |
| Started | Aug 13 06:53:05 PM PDT 24 |
| Finished | Aug 13 06:55:39 PM PDT 24 |
| Peak memory | 575660 kb |
| Host | smart-89f54369-4a65-4a02-8965-6f87fd8bd0b5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=882397820 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.xbar_stress_all _with_reset_error.882397820 |
| Directory | /workspace/32.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/32.xbar_unmapped_addr.2949194825 |
| Short name | T1594 |
| Test name | |
| Test status | |
| Simulation time | 743242649 ps |
| CPU time | 32.53 seconds |
| Started | Aug 13 06:53:04 PM PDT 24 |
| Finished | Aug 13 06:53:37 PM PDT 24 |
| Peak memory | 575576 kb |
| Host | smart-c4889e0d-08b2-4639-badc-3aeb72c9771c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2949194825 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.xbar_unmapped_addr.2949194825 |
| Directory | /workspace/32.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/33.xbar_access_same_device.1666804464 |
| Short name | T490 |
| Test name | |
| Test status | |
| Simulation time | 861032813 ps |
| CPU time | 71.87 seconds |
| Started | Aug 13 06:53:08 PM PDT 24 |
| Finished | Aug 13 06:54:20 PM PDT 24 |
| Peak memory | 575724 kb |
| Host | smart-8ba05f19-4c4c-4790-99b3-c5b6f6c3ba15 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1666804464 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.xbar_access_same_device .1666804464 |
| Directory | /workspace/33.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/33.xbar_access_same_device_slow_rsp.3244426431 |
| Short name | T2678 |
| Test name | |
| Test status | |
| Simulation time | 40966430990 ps |
| CPU time | 747.84 seconds |
| Started | Aug 13 06:53:09 PM PDT 24 |
| Finished | Aug 13 07:05:38 PM PDT 24 |
| Peak memory | 575804 kb |
| Host | smart-72e4d35e-815c-4608-b5c9-8fa122de29e4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3244426431 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.xbar_access_same_ device_slow_rsp.3244426431 |
| Directory | /workspace/33.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/33.xbar_error_and_unmapped_addr.3632463653 |
| Short name | T2524 |
| Test name | |
| Test status | |
| Simulation time | 147496449 ps |
| CPU time | 8.27 seconds |
| Started | Aug 13 06:53:08 PM PDT 24 |
| Finished | Aug 13 06:53:16 PM PDT 24 |
| Peak memory | 574220 kb |
| Host | smart-705cc8f6-cc42-41aa-8b7d-f50131260d42 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3632463653 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.xbar_error_and_unmapped_add r.3632463653 |
| Directory | /workspace/33.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/33.xbar_error_random.1886870118 |
| Short name | T2646 |
| Test name | |
| Test status | |
| Simulation time | 1765611599 ps |
| CPU time | 56.89 seconds |
| Started | Aug 13 06:53:21 PM PDT 24 |
| Finished | Aug 13 06:54:18 PM PDT 24 |
| Peak memory | 575476 kb |
| Host | smart-c218c71a-f950-40d7-a0e2-a2dcbef308ca |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1886870118 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.xbar_error_random.1886870118 |
| Directory | /workspace/33.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/33.xbar_random.1045997811 |
| Short name | T640 |
| Test name | |
| Test status | |
| Simulation time | 1743275422 ps |
| CPU time | 65.17 seconds |
| Started | Aug 13 06:53:02 PM PDT 24 |
| Finished | Aug 13 06:54:07 PM PDT 24 |
| Peak memory | 575556 kb |
| Host | smart-67560972-21ec-48c5-9e24-36e11f833dac |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1045997811 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.xbar_random.1045997811 |
| Directory | /workspace/33.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/33.xbar_random_large_delays.2740296434 |
| Short name | T591 |
| Test name | |
| Test status | |
| Simulation time | 33077983189 ps |
| CPU time | 332.86 seconds |
| Started | Aug 13 06:53:22 PM PDT 24 |
| Finished | Aug 13 06:58:55 PM PDT 24 |
| Peak memory | 575620 kb |
| Host | smart-a27c9b40-739b-4136-b8f3-ad8f436d8b32 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2740296434 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.xbar_random_large_delays.2740296434 |
| Directory | /workspace/33.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/33.xbar_random_slow_rsp.3719791464 |
| Short name | T2505 |
| Test name | |
| Test status | |
| Simulation time | 62987225926 ps |
| CPU time | 1043.09 seconds |
| Started | Aug 13 06:53:09 PM PDT 24 |
| Finished | Aug 13 07:10:33 PM PDT 24 |
| Peak memory | 575776 kb |
| Host | smart-341654e9-66e4-4584-974e-418fb1dd17c2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3719791464 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.xbar_random_slow_rsp.3719791464 |
| Directory | /workspace/33.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/33.xbar_random_zero_delays.2851068692 |
| Short name | T516 |
| Test name | |
| Test status | |
| Simulation time | 80599623 ps |
| CPU time | 9.24 seconds |
| Started | Aug 13 06:53:02 PM PDT 24 |
| Finished | Aug 13 06:53:11 PM PDT 24 |
| Peak memory | 575576 kb |
| Host | smart-88750de0-0654-4d70-87db-be7909fab060 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2851068692 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.xbar_random_zero_del ays.2851068692 |
| Directory | /workspace/33.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/33.xbar_same_source.822547076 |
| Short name | T1843 |
| Test name | |
| Test status | |
| Simulation time | 1176410637 ps |
| CPU time | 36.57 seconds |
| Started | Aug 13 06:53:10 PM PDT 24 |
| Finished | Aug 13 06:53:46 PM PDT 24 |
| Peak memory | 575636 kb |
| Host | smart-f152ca99-92eb-4ef8-abba-3e4bc107fcc0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=822547076 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.xbar_same_source.822547076 |
| Directory | /workspace/33.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/33.xbar_smoke.2243184510 |
| Short name | T2785 |
| Test name | |
| Test status | |
| Simulation time | 192810958 ps |
| CPU time | 8.59 seconds |
| Started | Aug 13 06:53:04 PM PDT 24 |
| Finished | Aug 13 06:53:12 PM PDT 24 |
| Peak memory | 574164 kb |
| Host | smart-bd571385-7d48-44f0-8b33-8cb29e216fd3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2243184510 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.xbar_smoke.2243184510 |
| Directory | /workspace/33.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/33.xbar_smoke_large_delays.2222897112 |
| Short name | T1729 |
| Test name | |
| Test status | |
| Simulation time | 7876907234 ps |
| CPU time | 80.74 seconds |
| Started | Aug 13 06:53:03 PM PDT 24 |
| Finished | Aug 13 06:54:23 PM PDT 24 |
| Peak memory | 573684 kb |
| Host | smart-c8d1ca1c-c8e0-47f5-b69e-d2df7a5de035 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2222897112 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.xbar_smoke_large_delays.2222897112 |
| Directory | /workspace/33.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/33.xbar_smoke_slow_rsp.1122703740 |
| Short name | T1511 |
| Test name | |
| Test status | |
| Simulation time | 4688813223 ps |
| CPU time | 83.84 seconds |
| Started | Aug 13 06:53:01 PM PDT 24 |
| Finished | Aug 13 06:54:25 PM PDT 24 |
| Peak memory | 573592 kb |
| Host | smart-4863c8b4-19a0-4926-a749-436ec4bf0842 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1122703740 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.xbar_smoke_slow_rsp.1122703740 |
| Directory | /workspace/33.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/33.xbar_smoke_zero_delays.1023134290 |
| Short name | T1637 |
| Test name | |
| Test status | |
| Simulation time | 48511196 ps |
| CPU time | 6.35 seconds |
| Started | Aug 13 06:53:02 PM PDT 24 |
| Finished | Aug 13 06:53:08 PM PDT 24 |
| Peak memory | 573572 kb |
| Host | smart-6968280f-9499-44a8-a54b-f8da9767366e |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1023134290 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.xbar_smoke_zero_delay s.1023134290 |
| Directory | /workspace/33.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/33.xbar_stress_all.331725395 |
| Short name | T1859 |
| Test name | |
| Test status | |
| Simulation time | 587172978 ps |
| CPU time | 58.16 seconds |
| Started | Aug 13 06:53:10 PM PDT 24 |
| Finished | Aug 13 06:54:08 PM PDT 24 |
| Peak memory | 575752 kb |
| Host | smart-f96c77c0-a79a-48a2-bd14-fc91fc1ec1a1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=331725395 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.xbar_stress_all.331725395 |
| Directory | /workspace/33.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/33.xbar_stress_all_with_error.707427212 |
| Short name | T1516 |
| Test name | |
| Test status | |
| Simulation time | 9529070250 ps |
| CPU time | 351.62 seconds |
| Started | Aug 13 06:53:10 PM PDT 24 |
| Finished | Aug 13 06:59:02 PM PDT 24 |
| Peak memory | 575820 kb |
| Host | smart-1a9bffdf-2018-4452-ad63-154a3ce24324 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=707427212 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.xbar_stress_all_with_error.707427212 |
| Directory | /workspace/33.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/33.xbar_stress_all_with_rand_reset.2937840769 |
| Short name | T2620 |
| Test name | |
| Test status | |
| Simulation time | 5174111754 ps |
| CPU time | 480.86 seconds |
| Started | Aug 13 06:53:09 PM PDT 24 |
| Finished | Aug 13 07:01:10 PM PDT 24 |
| Peak memory | 575688 kb |
| Host | smart-6ef48971-90aa-4e31-9992-168ca472d8b9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2937840769 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.xbar_stress_all _with_rand_reset.2937840769 |
| Directory | /workspace/33.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/33.xbar_stress_all_with_reset_error.3194301836 |
| Short name | T2917 |
| Test name | |
| Test status | |
| Simulation time | 3907203705 ps |
| CPU time | 497.14 seconds |
| Started | Aug 13 06:53:08 PM PDT 24 |
| Finished | Aug 13 07:01:25 PM PDT 24 |
| Peak memory | 576552 kb |
| Host | smart-f6eae5f5-a6cd-4ec5-9276-83239ea7ff5c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3194301836 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.xbar_stress_al l_with_reset_error.3194301836 |
| Directory | /workspace/33.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/33.xbar_unmapped_addr.445918176 |
| Short name | T1834 |
| Test name | |
| Test status | |
| Simulation time | 280899435 ps |
| CPU time | 32.43 seconds |
| Started | Aug 13 06:53:09 PM PDT 24 |
| Finished | Aug 13 06:53:42 PM PDT 24 |
| Peak memory | 575756 kb |
| Host | smart-7e1bfc63-1ffb-4697-b3bf-a1cdd2cc72f2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=445918176 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.xbar_unmapped_addr.445918176 |
| Directory | /workspace/33.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/34.xbar_access_same_device.1246059543 |
| Short name | T888 |
| Test name | |
| Test status | |
| Simulation time | 2862917706 ps |
| CPU time | 123.92 seconds |
| Started | Aug 13 06:53:06 PM PDT 24 |
| Finished | Aug 13 06:55:10 PM PDT 24 |
| Peak memory | 575736 kb |
| Host | smart-6b82321d-e967-453f-abc0-c46acddf3cb9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1246059543 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.xbar_access_same_device .1246059543 |
| Directory | /workspace/34.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/34.xbar_access_same_device_slow_rsp.2914399566 |
| Short name | T2709 |
| Test name | |
| Test status | |
| Simulation time | 17634785282 ps |
| CPU time | 302.19 seconds |
| Started | Aug 13 06:53:22 PM PDT 24 |
| Finished | Aug 13 06:58:25 PM PDT 24 |
| Peak memory | 575776 kb |
| Host | smart-6860b21b-70eb-4c8e-9dfd-cf9fa936bb86 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2914399566 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.xbar_access_same_ device_slow_rsp.2914399566 |
| Directory | /workspace/34.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/34.xbar_error_and_unmapped_addr.1706376096 |
| Short name | T1807 |
| Test name | |
| Test status | |
| Simulation time | 50613713 ps |
| CPU time | 5.39 seconds |
| Started | Aug 13 06:53:19 PM PDT 24 |
| Finished | Aug 13 06:53:25 PM PDT 24 |
| Peak memory | 573640 kb |
| Host | smart-6726100e-e774-4865-ae28-9166b91c822c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1706376096 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.xbar_error_and_unmapped_add r.1706376096 |
| Directory | /workspace/34.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/34.xbar_error_random.3745532876 |
| Short name | T2114 |
| Test name | |
| Test status | |
| Simulation time | 528256479 ps |
| CPU time | 47.02 seconds |
| Started | Aug 13 06:53:21 PM PDT 24 |
| Finished | Aug 13 06:54:08 PM PDT 24 |
| Peak memory | 575668 kb |
| Host | smart-e3a06f6d-e0d8-4647-b08e-d3177f690156 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3745532876 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.xbar_error_random.3745532876 |
| Directory | /workspace/34.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/34.xbar_random.890651050 |
| Short name | T2036 |
| Test name | |
| Test status | |
| Simulation time | 1516067918 ps |
| CPU time | 45.01 seconds |
| Started | Aug 13 06:53:09 PM PDT 24 |
| Finished | Aug 13 06:53:54 PM PDT 24 |
| Peak memory | 575460 kb |
| Host | smart-a19dbfc4-91ed-4066-aabe-f78c9c013f09 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=890651050 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.xbar_random.890651050 |
| Directory | /workspace/34.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/34.xbar_random_large_delays.3659905930 |
| Short name | T2340 |
| Test name | |
| Test status | |
| Simulation time | 47885506525 ps |
| CPU time | 465.92 seconds |
| Started | Aug 13 06:53:08 PM PDT 24 |
| Finished | Aug 13 07:00:54 PM PDT 24 |
| Peak memory | 575792 kb |
| Host | smart-9e3f6a8e-f944-4118-aff0-0c2cf7b63dff |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3659905930 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.xbar_random_large_delays.3659905930 |
| Directory | /workspace/34.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/34.xbar_random_slow_rsp.2350185984 |
| Short name | T2392 |
| Test name | |
| Test status | |
| Simulation time | 30369668379 ps |
| CPU time | 525.03 seconds |
| Started | Aug 13 06:53:22 PM PDT 24 |
| Finished | Aug 13 07:02:07 PM PDT 24 |
| Peak memory | 575636 kb |
| Host | smart-e7eff4b2-ab05-4832-b910-039f180f759d |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2350185984 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.xbar_random_slow_rsp.2350185984 |
| Directory | /workspace/34.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/34.xbar_random_zero_delays.2895514361 |
| Short name | T2249 |
| Test name | |
| Test status | |
| Simulation time | 299786753 ps |
| CPU time | 27.97 seconds |
| Started | Aug 13 06:53:07 PM PDT 24 |
| Finished | Aug 13 06:53:35 PM PDT 24 |
| Peak memory | 575524 kb |
| Host | smart-1bf4a84b-1347-4b8b-8408-f3dba87b693e |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2895514361 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.xbar_random_zero_del ays.2895514361 |
| Directory | /workspace/34.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/34.xbar_same_source.1784545458 |
| Short name | T700 |
| Test name | |
| Test status | |
| Simulation time | 1256962124 ps |
| CPU time | 37.82 seconds |
| Started | Aug 13 06:53:11 PM PDT 24 |
| Finished | Aug 13 06:53:49 PM PDT 24 |
| Peak memory | 575500 kb |
| Host | smart-f9104f2e-951a-46dc-bd47-7151576bc17d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1784545458 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.xbar_same_source.1784545458 |
| Directory | /workspace/34.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/34.xbar_smoke.751003116 |
| Short name | T1464 |
| Test name | |
| Test status | |
| Simulation time | 211932669 ps |
| CPU time | 8.7 seconds |
| Started | Aug 13 06:53:11 PM PDT 24 |
| Finished | Aug 13 06:53:20 PM PDT 24 |
| Peak memory | 574220 kb |
| Host | smart-77b9750b-6e8d-4f63-93d8-d7c32221ff41 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=751003116 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.xbar_smoke.751003116 |
| Directory | /workspace/34.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/34.xbar_smoke_large_delays.3252059619 |
| Short name | T2030 |
| Test name | |
| Test status | |
| Simulation time | 9183394433 ps |
| CPU time | 95.07 seconds |
| Started | Aug 13 06:53:09 PM PDT 24 |
| Finished | Aug 13 06:54:44 PM PDT 24 |
| Peak memory | 574304 kb |
| Host | smart-e4cf7f43-60e8-4cc1-a148-454266cf8510 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3252059619 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.xbar_smoke_large_delays.3252059619 |
| Directory | /workspace/34.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/34.xbar_smoke_slow_rsp.574585071 |
| Short name | T897 |
| Test name | |
| Test status | |
| Simulation time | 5723468608 ps |
| CPU time | 99.34 seconds |
| Started | Aug 13 06:53:23 PM PDT 24 |
| Finished | Aug 13 06:55:03 PM PDT 24 |
| Peak memory | 573688 kb |
| Host | smart-b8a9692e-9765-4b42-8f94-fe4e39dc9322 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=574585071 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.xbar_smoke_slow_rsp.574585071 |
| Directory | /workspace/34.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/34.xbar_smoke_zero_delays.165289610 |
| Short name | T713 |
| Test name | |
| Test status | |
| Simulation time | 45162029 ps |
| CPU time | 5.97 seconds |
| Started | Aug 13 06:53:08 PM PDT 24 |
| Finished | Aug 13 06:53:14 PM PDT 24 |
| Peak memory | 574164 kb |
| Host | smart-7de5525c-c21c-40ea-a464-9bd7fae879c6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=165289610 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.xbar_smoke_zero_delays .165289610 |
| Directory | /workspace/34.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/34.xbar_stress_all.845454859 |
| Short name | T2920 |
| Test name | |
| Test status | |
| Simulation time | 5754985 ps |
| CPU time | 3.62 seconds |
| Started | Aug 13 06:53:18 PM PDT 24 |
| Finished | Aug 13 06:53:22 PM PDT 24 |
| Peak memory | 565232 kb |
| Host | smart-9a608533-0442-460b-ac3e-5e5a5fce4cce |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=845454859 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.xbar_stress_all.845454859 |
| Directory | /workspace/34.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/34.xbar_stress_all_with_rand_reset.2645699716 |
| Short name | T926 |
| Test name | |
| Test status | |
| Simulation time | 314775055 ps |
| CPU time | 96.81 seconds |
| Started | Aug 13 06:53:17 PM PDT 24 |
| Finished | Aug 13 06:54:53 PM PDT 24 |
| Peak memory | 576460 kb |
| Host | smart-f838546c-a448-4fa6-9b97-b9cec316d39a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2645699716 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.xbar_stress_all _with_rand_reset.2645699716 |
| Directory | /workspace/34.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/34.xbar_stress_all_with_reset_error.2666093904 |
| Short name | T2879 |
| Test name | |
| Test status | |
| Simulation time | 25875325 ps |
| CPU time | 17.35 seconds |
| Started | Aug 13 06:53:16 PM PDT 24 |
| Finished | Aug 13 06:53:34 PM PDT 24 |
| Peak memory | 575412 kb |
| Host | smart-d9962c62-abd1-4032-a223-ceb7c89ed27b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2666093904 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.xbar_stress_al l_with_reset_error.2666093904 |
| Directory | /workspace/34.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/34.xbar_unmapped_addr.3705111117 |
| Short name | T2129 |
| Test name | |
| Test status | |
| Simulation time | 57976165 ps |
| CPU time | 9.73 seconds |
| Started | Aug 13 06:53:17 PM PDT 24 |
| Finished | Aug 13 06:53:27 PM PDT 24 |
| Peak memory | 575744 kb |
| Host | smart-8ae43afb-fc62-432f-94b5-318db79d82e0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3705111117 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.xbar_unmapped_addr.3705111117 |
| Directory | /workspace/34.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/35.xbar_access_same_device.2083268325 |
| Short name | T1698 |
| Test name | |
| Test status | |
| Simulation time | 2539537910 ps |
| CPU time | 105 seconds |
| Started | Aug 13 06:53:18 PM PDT 24 |
| Finished | Aug 13 06:55:03 PM PDT 24 |
| Peak memory | 575620 kb |
| Host | smart-d8161598-9745-42de-b8a9-7c2e376bba62 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2083268325 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.xbar_access_same_device .2083268325 |
| Directory | /workspace/35.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/35.xbar_access_same_device_slow_rsp.1942160415 |
| Short name | T2557 |
| Test name | |
| Test status | |
| Simulation time | 31146986556 ps |
| CPU time | 529.31 seconds |
| Started | Aug 13 06:53:17 PM PDT 24 |
| Finished | Aug 13 07:02:07 PM PDT 24 |
| Peak memory | 575816 kb |
| Host | smart-66f81a68-6cc1-4ca4-b017-0c595c16eb38 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1942160415 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.xbar_access_same_ device_slow_rsp.1942160415 |
| Directory | /workspace/35.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/35.xbar_error_and_unmapped_addr.2062828608 |
| Short name | T2002 |
| Test name | |
| Test status | |
| Simulation time | 113958996 ps |
| CPU time | 14.51 seconds |
| Started | Aug 13 06:53:23 PM PDT 24 |
| Finished | Aug 13 06:53:38 PM PDT 24 |
| Peak memory | 575712 kb |
| Host | smart-fae8cb93-2bdb-4dfd-82f9-afa30390c5a3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2062828608 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.xbar_error_and_unmapped_add r.2062828608 |
| Directory | /workspace/35.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/35.xbar_error_random.1446691801 |
| Short name | T1634 |
| Test name | |
| Test status | |
| Simulation time | 1003235119 ps |
| CPU time | 36.69 seconds |
| Started | Aug 13 06:53:16 PM PDT 24 |
| Finished | Aug 13 06:53:53 PM PDT 24 |
| Peak memory | 575664 kb |
| Host | smart-b76f94b9-226e-4bfa-be54-cb5e42c7272c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1446691801 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.xbar_error_random.1446691801 |
| Directory | /workspace/35.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/35.xbar_random.2469337347 |
| Short name | T1883 |
| Test name | |
| Test status | |
| Simulation time | 101315513 ps |
| CPU time | 13.05 seconds |
| Started | Aug 13 06:53:16 PM PDT 24 |
| Finished | Aug 13 06:53:29 PM PDT 24 |
| Peak memory | 575496 kb |
| Host | smart-c6c05f63-9c18-4c42-89b1-09153a03086d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2469337347 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.xbar_random.2469337347 |
| Directory | /workspace/35.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/35.xbar_random_large_delays.3541873263 |
| Short name | T2496 |
| Test name | |
| Test status | |
| Simulation time | 113967823711 ps |
| CPU time | 1266.7 seconds |
| Started | Aug 13 06:53:18 PM PDT 24 |
| Finished | Aug 13 07:14:25 PM PDT 24 |
| Peak memory | 575760 kb |
| Host | smart-93cb23ad-f204-4237-b2de-2eb1db09c5f1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3541873263 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.xbar_random_large_delays.3541873263 |
| Directory | /workspace/35.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/35.xbar_random_slow_rsp.304245970 |
| Short name | T513 |
| Test name | |
| Test status | |
| Simulation time | 18616389705 ps |
| CPU time | 296.4 seconds |
| Started | Aug 13 06:53:23 PM PDT 24 |
| Finished | Aug 13 06:58:19 PM PDT 24 |
| Peak memory | 575708 kb |
| Host | smart-a7dcdb38-f267-45f5-a7b0-2c7651485f1e |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=304245970 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.xbar_random_slow_rsp.304245970 |
| Directory | /workspace/35.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/35.xbar_random_zero_delays.3058857984 |
| Short name | T1565 |
| Test name | |
| Test status | |
| Simulation time | 30663852 ps |
| CPU time | 5.54 seconds |
| Started | Aug 13 06:53:16 PM PDT 24 |
| Finished | Aug 13 06:53:21 PM PDT 24 |
| Peak memory | 573536 kb |
| Host | smart-061fb16c-70bd-439e-8ae2-2dc2b315bc27 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3058857984 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.xbar_random_zero_del ays.3058857984 |
| Directory | /workspace/35.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/35.xbar_same_source.1362665729 |
| Short name | T2407 |
| Test name | |
| Test status | |
| Simulation time | 740922322 ps |
| CPU time | 23.69 seconds |
| Started | Aug 13 06:53:18 PM PDT 24 |
| Finished | Aug 13 06:53:42 PM PDT 24 |
| Peak memory | 575556 kb |
| Host | smart-af1f08d2-ba8e-47d1-a2e5-870e4b95ec63 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1362665729 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.xbar_same_source.1362665729 |
| Directory | /workspace/35.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/35.xbar_smoke.2146531173 |
| Short name | T1742 |
| Test name | |
| Test status | |
| Simulation time | 222882653 ps |
| CPU time | 10.38 seconds |
| Started | Aug 13 06:53:21 PM PDT 24 |
| Finished | Aug 13 06:53:31 PM PDT 24 |
| Peak memory | 573548 kb |
| Host | smart-a1b9e4e6-7aec-47ef-92aa-ba909c10015f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2146531173 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.xbar_smoke.2146531173 |
| Directory | /workspace/35.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/35.xbar_smoke_large_delays.2044427549 |
| Short name | T2455 |
| Test name | |
| Test status | |
| Simulation time | 9685018322 ps |
| CPU time | 99.88 seconds |
| Started | Aug 13 06:53:17 PM PDT 24 |
| Finished | Aug 13 06:54:57 PM PDT 24 |
| Peak memory | 573664 kb |
| Host | smart-cb3977cf-5a11-45ac-aa9b-335d790b31af |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2044427549 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.xbar_smoke_large_delays.2044427549 |
| Directory | /workspace/35.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/35.xbar_smoke_slow_rsp.388685370 |
| Short name | T2727 |
| Test name | |
| Test status | |
| Simulation time | 5003665551 ps |
| CPU time | 87.3 seconds |
| Started | Aug 13 06:53:17 PM PDT 24 |
| Finished | Aug 13 06:54:44 PM PDT 24 |
| Peak memory | 573652 kb |
| Host | smart-f289b28e-d681-469d-8a6c-4086eba3cbfb |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=388685370 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.xbar_smoke_slow_rsp.388685370 |
| Directory | /workspace/35.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/35.xbar_smoke_zero_delays.3303579991 |
| Short name | T1429 |
| Test name | |
| Test status | |
| Simulation time | 51058259 ps |
| CPU time | 7 seconds |
| Started | Aug 13 06:53:21 PM PDT 24 |
| Finished | Aug 13 06:53:28 PM PDT 24 |
| Peak memory | 574244 kb |
| Host | smart-2d1311ef-b986-4c9a-a173-7a9d76965f2f |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3303579991 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.xbar_smoke_zero_delay s.3303579991 |
| Directory | /workspace/35.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/35.xbar_stress_all.2230508646 |
| Short name | T2042 |
| Test name | |
| Test status | |
| Simulation time | 2429528950 ps |
| CPU time | 89.38 seconds |
| Started | Aug 13 06:53:24 PM PDT 24 |
| Finished | Aug 13 06:54:53 PM PDT 24 |
| Peak memory | 575836 kb |
| Host | smart-ec46cf97-9901-41e8-91ac-896f8faa6ccb |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2230508646 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.xbar_stress_all.2230508646 |
| Directory | /workspace/35.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/35.xbar_stress_all_with_error.1297777650 |
| Short name | T686 |
| Test name | |
| Test status | |
| Simulation time | 2700649970 ps |
| CPU time | 208.61 seconds |
| Started | Aug 13 06:53:18 PM PDT 24 |
| Finished | Aug 13 06:56:47 PM PDT 24 |
| Peak memory | 576532 kb |
| Host | smart-406988e4-1345-4708-b2b1-b16158aeb0fc |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1297777650 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.xbar_stress_all_with_error.1297777650 |
| Directory | /workspace/35.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/35.xbar_stress_all_with_rand_reset.3818287359 |
| Short name | T2891 |
| Test name | |
| Test status | |
| Simulation time | 2911155320 ps |
| CPU time | 560.85 seconds |
| Started | Aug 13 06:53:17 PM PDT 24 |
| Finished | Aug 13 07:02:38 PM PDT 24 |
| Peak memory | 575676 kb |
| Host | smart-5d6f39be-92ed-4a71-8c3a-cbbbc8f55f74 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3818287359 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.xbar_stress_all _with_rand_reset.3818287359 |
| Directory | /workspace/35.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/35.xbar_stress_all_with_reset_error.1797458853 |
| Short name | T1424 |
| Test name | |
| Test status | |
| Simulation time | 108322373 ps |
| CPU time | 32.54 seconds |
| Started | Aug 13 06:53:17 PM PDT 24 |
| Finished | Aug 13 06:53:50 PM PDT 24 |
| Peak memory | 575608 kb |
| Host | smart-d071803f-dc24-4181-87a3-87ce4de4613b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1797458853 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.xbar_stress_al l_with_reset_error.1797458853 |
| Directory | /workspace/35.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/35.xbar_unmapped_addr.2249281728 |
| Short name | T2631 |
| Test name | |
| Test status | |
| Simulation time | 216316591 ps |
| CPU time | 25.4 seconds |
| Started | Aug 13 06:53:18 PM PDT 24 |
| Finished | Aug 13 06:53:43 PM PDT 24 |
| Peak memory | 575744 kb |
| Host | smart-efe7ea69-3e0b-4a24-82f7-da89e96a9ba4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2249281728 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.xbar_unmapped_addr.2249281728 |
| Directory | /workspace/35.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/36.xbar_access_same_device.3201599642 |
| Short name | T2160 |
| Test name | |
| Test status | |
| Simulation time | 414668697 ps |
| CPU time | 30.85 seconds |
| Started | Aug 13 06:53:29 PM PDT 24 |
| Finished | Aug 13 06:54:00 PM PDT 24 |
| Peak memory | 575716 kb |
| Host | smart-bba9baec-9e24-444f-a58b-1417fabf34d8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3201599642 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.xbar_access_same_device .3201599642 |
| Directory | /workspace/36.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/36.xbar_access_same_device_slow_rsp.3273969866 |
| Short name | T2115 |
| Test name | |
| Test status | |
| Simulation time | 141126568384 ps |
| CPU time | 2636.34 seconds |
| Started | Aug 13 06:53:24 PM PDT 24 |
| Finished | Aug 13 07:37:21 PM PDT 24 |
| Peak memory | 575856 kb |
| Host | smart-a8a8fd89-06af-4a2e-a157-2657cbc4ec76 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3273969866 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.xbar_access_same_ device_slow_rsp.3273969866 |
| Directory | /workspace/36.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/36.xbar_error_and_unmapped_addr.308802006 |
| Short name | T1519 |
| Test name | |
| Test status | |
| Simulation time | 1091696519 ps |
| CPU time | 39.93 seconds |
| Started | Aug 13 06:53:24 PM PDT 24 |
| Finished | Aug 13 06:54:04 PM PDT 24 |
| Peak memory | 575504 kb |
| Host | smart-0c5004b4-c6a4-430d-adfe-9572a291c243 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=308802006 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.xbar_error_and_unmapped_addr .308802006 |
| Directory | /workspace/36.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/36.xbar_error_random.147403348 |
| Short name | T1604 |
| Test name | |
| Test status | |
| Simulation time | 2576782082 ps |
| CPU time | 88.73 seconds |
| Started | Aug 13 06:53:27 PM PDT 24 |
| Finished | Aug 13 06:54:56 PM PDT 24 |
| Peak memory | 575660 kb |
| Host | smart-59a42b74-6a76-41c3-8d51-49cfc3bcb6ea |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=147403348 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.xbar_error_random.147403348 |
| Directory | /workspace/36.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/36.xbar_random.2512816691 |
| Short name | T2409 |
| Test name | |
| Test status | |
| Simulation time | 1541228326 ps |
| CPU time | 60 seconds |
| Started | Aug 13 06:53:25 PM PDT 24 |
| Finished | Aug 13 06:54:25 PM PDT 24 |
| Peak memory | 575688 kb |
| Host | smart-dd55b0fc-af55-45ec-8c54-770c2c9dd21a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2512816691 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.xbar_random.2512816691 |
| Directory | /workspace/36.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/36.xbar_random_large_delays.3022649711 |
| Short name | T2065 |
| Test name | |
| Test status | |
| Simulation time | 31680135126 ps |
| CPU time | 310.77 seconds |
| Started | Aug 13 06:53:28 PM PDT 24 |
| Finished | Aug 13 06:58:39 PM PDT 24 |
| Peak memory | 575756 kb |
| Host | smart-382e291a-87aa-4d46-a471-37ef511d6786 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3022649711 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.xbar_random_large_delays.3022649711 |
| Directory | /workspace/36.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/36.xbar_random_slow_rsp.3427339658 |
| Short name | T1877 |
| Test name | |
| Test status | |
| Simulation time | 15664454582 ps |
| CPU time | 251.92 seconds |
| Started | Aug 13 06:53:31 PM PDT 24 |
| Finished | Aug 13 06:57:43 PM PDT 24 |
| Peak memory | 575556 kb |
| Host | smart-b91eac8f-57df-42a3-b8fc-a9985104a74b |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3427339658 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.xbar_random_slow_rsp.3427339658 |
| Directory | /workspace/36.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/36.xbar_random_zero_delays.3366003683 |
| Short name | T2700 |
| Test name | |
| Test status | |
| Simulation time | 276918015 ps |
| CPU time | 25.51 seconds |
| Started | Aug 13 06:53:27 PM PDT 24 |
| Finished | Aug 13 06:53:52 PM PDT 24 |
| Peak memory | 575460 kb |
| Host | smart-5ce83ba9-15d3-41d8-b3a0-ccfe1dadab7a |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3366003683 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.xbar_random_zero_del ays.3366003683 |
| Directory | /workspace/36.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/36.xbar_same_source.64388489 |
| Short name | T637 |
| Test name | |
| Test status | |
| Simulation time | 167647383 ps |
| CPU time | 14.08 seconds |
| Started | Aug 13 06:53:29 PM PDT 24 |
| Finished | Aug 13 06:53:43 PM PDT 24 |
| Peak memory | 575632 kb |
| Host | smart-ca292fc7-cc86-4078-8990-9a142a954abe |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64388489 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.xbar_same_source.64388489 |
| Directory | /workspace/36.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/36.xbar_smoke.1455855234 |
| Short name | T2080 |
| Test name | |
| Test status | |
| Simulation time | 44341097 ps |
| CPU time | 6.32 seconds |
| Started | Aug 13 06:53:17 PM PDT 24 |
| Finished | Aug 13 06:53:24 PM PDT 24 |
| Peak memory | 573484 kb |
| Host | smart-a8e77000-9114-4612-9567-89f20c2e7ec2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1455855234 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.xbar_smoke.1455855234 |
| Directory | /workspace/36.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/36.xbar_smoke_large_delays.1154784127 |
| Short name | T2662 |
| Test name | |
| Test status | |
| Simulation time | 10469179857 ps |
| CPU time | 110.69 seconds |
| Started | Aug 13 06:53:31 PM PDT 24 |
| Finished | Aug 13 06:55:22 PM PDT 24 |
| Peak memory | 573672 kb |
| Host | smart-757238bb-9b08-4814-8cc9-63e288fc1ea4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1154784127 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.xbar_smoke_large_delays.1154784127 |
| Directory | /workspace/36.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/36.xbar_smoke_slow_rsp.2296720064 |
| Short name | T611 |
| Test name | |
| Test status | |
| Simulation time | 6190995872 ps |
| CPU time | 108.11 seconds |
| Started | Aug 13 06:53:24 PM PDT 24 |
| Finished | Aug 13 06:55:12 PM PDT 24 |
| Peak memory | 573600 kb |
| Host | smart-6a541fde-0d58-496b-a75a-7ff9816412f0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2296720064 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.xbar_smoke_slow_rsp.2296720064 |
| Directory | /workspace/36.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/36.xbar_smoke_zero_delays.1457013967 |
| Short name | T1475 |
| Test name | |
| Test status | |
| Simulation time | 39324861 ps |
| CPU time | 5.47 seconds |
| Started | Aug 13 06:53:24 PM PDT 24 |
| Finished | Aug 13 06:53:30 PM PDT 24 |
| Peak memory | 573572 kb |
| Host | smart-c030a666-55f3-450c-bfd1-6d01de164023 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1457013967 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.xbar_smoke_zero_delay s.1457013967 |
| Directory | /workspace/36.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/36.xbar_stress_all.3297202552 |
| Short name | T1987 |
| Test name | |
| Test status | |
| Simulation time | 1423978461 ps |
| CPU time | 123.54 seconds |
| Started | Aug 13 06:53:28 PM PDT 24 |
| Finished | Aug 13 06:55:32 PM PDT 24 |
| Peak memory | 576444 kb |
| Host | smart-164a3c11-9c4e-4720-a6ee-1c8354ed52b1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3297202552 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.xbar_stress_all.3297202552 |
| Directory | /workspace/36.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/36.xbar_stress_all_with_error.1808718447 |
| Short name | T2327 |
| Test name | |
| Test status | |
| Simulation time | 7809032417 ps |
| CPU time | 287.95 seconds |
| Started | Aug 13 06:53:25 PM PDT 24 |
| Finished | Aug 13 06:58:13 PM PDT 24 |
| Peak memory | 576516 kb |
| Host | smart-3991fdf9-78fa-4cb2-8eac-156184c80c98 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1808718447 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.xbar_stress_all_with_error.1808718447 |
| Directory | /workspace/36.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/36.xbar_stress_all_with_rand_reset.1325204680 |
| Short name | T1996 |
| Test name | |
| Test status | |
| Simulation time | 8849553279 ps |
| CPU time | 542.78 seconds |
| Started | Aug 13 06:53:27 PM PDT 24 |
| Finished | Aug 13 07:02:30 PM PDT 24 |
| Peak memory | 576496 kb |
| Host | smart-1ec2cfd0-4dc0-486e-96ea-d39c42061b3e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1325204680 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.xbar_stress_all _with_rand_reset.1325204680 |
| Directory | /workspace/36.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/36.xbar_unmapped_addr.1702678301 |
| Short name | T1947 |
| Test name | |
| Test status | |
| Simulation time | 1203567501 ps |
| CPU time | 46.76 seconds |
| Started | Aug 13 06:53:25 PM PDT 24 |
| Finished | Aug 13 06:54:12 PM PDT 24 |
| Peak memory | 575668 kb |
| Host | smart-e976d795-865e-4d21-978e-8f98d91dbcc9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1702678301 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.xbar_unmapped_addr.1702678301 |
| Directory | /workspace/36.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/37.xbar_access_same_device.714052188 |
| Short name | T2093 |
| Test name | |
| Test status | |
| Simulation time | 164464207 ps |
| CPU time | 11.77 seconds |
| Started | Aug 13 06:53:25 PM PDT 24 |
| Finished | Aug 13 06:53:37 PM PDT 24 |
| Peak memory | 575604 kb |
| Host | smart-bab47270-c276-4ad4-b592-575e41aabad5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=714052188 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.xbar_access_same_device. 714052188 |
| Directory | /workspace/37.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/37.xbar_access_same_device_slow_rsp.3419239229 |
| Short name | T2555 |
| Test name | |
| Test status | |
| Simulation time | 28721039431 ps |
| CPU time | 507.25 seconds |
| Started | Aug 13 06:53:28 PM PDT 24 |
| Finished | Aug 13 07:01:55 PM PDT 24 |
| Peak memory | 575780 kb |
| Host | smart-ea4d9717-61b3-43e2-8a34-b9aeff4eb31c |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3419239229 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.xbar_access_same_ device_slow_rsp.3419239229 |
| Directory | /workspace/37.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/37.xbar_error_and_unmapped_addr.3007258886 |
| Short name | T1885 |
| Test name | |
| Test status | |
| Simulation time | 1165770406 ps |
| CPU time | 39.58 seconds |
| Started | Aug 13 06:53:26 PM PDT 24 |
| Finished | Aug 13 06:54:05 PM PDT 24 |
| Peak memory | 575736 kb |
| Host | smart-643e7f51-2d6c-4870-8d51-dfccdb9a0fff |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3007258886 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.xbar_error_and_unmapped_add r.3007258886 |
| Directory | /workspace/37.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/37.xbar_error_random.965551458 |
| Short name | T1454 |
| Test name | |
| Test status | |
| Simulation time | 2322145626 ps |
| CPU time | 76.26 seconds |
| Started | Aug 13 06:53:25 PM PDT 24 |
| Finished | Aug 13 06:54:42 PM PDT 24 |
| Peak memory | 575772 kb |
| Host | smart-0168a28d-e98d-470a-9a14-609b96ca1257 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=965551458 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.xbar_error_random.965551458 |
| Directory | /workspace/37.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/37.xbar_random.987798185 |
| Short name | T2314 |
| Test name | |
| Test status | |
| Simulation time | 92464881 ps |
| CPU time | 10.09 seconds |
| Started | Aug 13 06:53:25 PM PDT 24 |
| Finished | Aug 13 06:53:36 PM PDT 24 |
| Peak memory | 575576 kb |
| Host | smart-17b46216-546d-4fe6-ad36-77f8c7b46c55 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=987798185 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.xbar_random.987798185 |
| Directory | /workspace/37.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/37.xbar_random_large_delays.380185848 |
| Short name | T2334 |
| Test name | |
| Test status | |
| Simulation time | 29747543265 ps |
| CPU time | 300.23 seconds |
| Started | Aug 13 06:53:29 PM PDT 24 |
| Finished | Aug 13 06:58:29 PM PDT 24 |
| Peak memory | 575596 kb |
| Host | smart-02d85764-f2f3-4aa3-a4bc-75b3a26df0fc |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=380185848 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.xbar_random_large_delays.380185848 |
| Directory | /workspace/37.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/37.xbar_random_slow_rsp.1628973985 |
| Short name | T1850 |
| Test name | |
| Test status | |
| Simulation time | 37016091195 ps |
| CPU time | 604.62 seconds |
| Started | Aug 13 06:53:26 PM PDT 24 |
| Finished | Aug 13 07:03:30 PM PDT 24 |
| Peak memory | 575800 kb |
| Host | smart-26e5e0ca-a2bf-4654-88c4-5ce9b78d2862 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1628973985 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.xbar_random_slow_rsp.1628973985 |
| Directory | /workspace/37.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/37.xbar_random_zero_delays.1893381374 |
| Short name | T1720 |
| Test name | |
| Test status | |
| Simulation time | 300358048 ps |
| CPU time | 25.96 seconds |
| Started | Aug 13 06:53:24 PM PDT 24 |
| Finished | Aug 13 06:53:50 PM PDT 24 |
| Peak memory | 575608 kb |
| Host | smart-aa9d1b0a-ebd9-4d49-9792-ed29e06efc21 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1893381374 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.xbar_random_zero_del ays.1893381374 |
| Directory | /workspace/37.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/37.xbar_same_source.41849185 |
| Short name | T2225 |
| Test name | |
| Test status | |
| Simulation time | 2620628475 ps |
| CPU time | 71.11 seconds |
| Started | Aug 13 06:53:26 PM PDT 24 |
| Finished | Aug 13 06:54:37 PM PDT 24 |
| Peak memory | 575480 kb |
| Host | smart-dc2ea73c-a72e-406c-a03a-a2251f214a5a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41849185 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.xbar_same_source.41849185 |
| Directory | /workspace/37.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/37.xbar_smoke.1326078175 |
| Short name | T1674 |
| Test name | |
| Test status | |
| Simulation time | 253157384 ps |
| CPU time | 10.59 seconds |
| Started | Aug 13 06:53:24 PM PDT 24 |
| Finished | Aug 13 06:53:35 PM PDT 24 |
| Peak memory | 574232 kb |
| Host | smart-b9525eab-c476-40f0-aa72-a9e72e171fe5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1326078175 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.xbar_smoke.1326078175 |
| Directory | /workspace/37.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/37.xbar_smoke_large_delays.618346875 |
| Short name | T2804 |
| Test name | |
| Test status | |
| Simulation time | 7665372055 ps |
| CPU time | 72.81 seconds |
| Started | Aug 13 06:53:29 PM PDT 24 |
| Finished | Aug 13 06:54:42 PM PDT 24 |
| Peak memory | 573676 kb |
| Host | smart-50f1347a-1810-4133-9653-b7e8a2ef6922 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=618346875 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.xbar_smoke_large_delays.618346875 |
| Directory | /workspace/37.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/37.xbar_smoke_slow_rsp.4227029128 |
| Short name | T2791 |
| Test name | |
| Test status | |
| Simulation time | 5638271461 ps |
| CPU time | 96.38 seconds |
| Started | Aug 13 06:53:29 PM PDT 24 |
| Finished | Aug 13 06:55:05 PM PDT 24 |
| Peak memory | 573668 kb |
| Host | smart-01f8d7b0-acc4-4e62-b072-c2728c147564 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4227029128 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.xbar_smoke_slow_rsp.4227029128 |
| Directory | /workspace/37.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/37.xbar_smoke_zero_delays.1814891419 |
| Short name | T717 |
| Test name | |
| Test status | |
| Simulation time | 37326755 ps |
| CPU time | 5.9 seconds |
| Started | Aug 13 06:53:31 PM PDT 24 |
| Finished | Aug 13 06:53:37 PM PDT 24 |
| Peak memory | 573560 kb |
| Host | smart-3296accd-3aea-4e50-97e7-6834b420c100 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1814891419 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.xbar_smoke_zero_delay s.1814891419 |
| Directory | /workspace/37.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/37.xbar_stress_all_with_error.3344290633 |
| Short name | T2226 |
| Test name | |
| Test status | |
| Simulation time | 3174531636 ps |
| CPU time | 106.85 seconds |
| Started | Aug 13 06:53:27 PM PDT 24 |
| Finished | Aug 13 06:55:14 PM PDT 24 |
| Peak memory | 575632 kb |
| Host | smart-98f70f1e-dcc5-4b1d-a540-9d31ead2b6d0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3344290633 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.xbar_stress_all_with_error.3344290633 |
| Directory | /workspace/37.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/37.xbar_stress_all_with_rand_reset.1877936122 |
| Short name | T2575 |
| Test name | |
| Test status | |
| Simulation time | 1973896037 ps |
| CPU time | 382.72 seconds |
| Started | Aug 13 06:53:28 PM PDT 24 |
| Finished | Aug 13 06:59:51 PM PDT 24 |
| Peak memory | 576472 kb |
| Host | smart-91a33d1c-bd12-44cc-a2b4-e27e284a52ef |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1877936122 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.xbar_stress_all _with_rand_reset.1877936122 |
| Directory | /workspace/37.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/37.xbar_stress_all_with_reset_error.2233456716 |
| Short name | T917 |
| Test name | |
| Test status | |
| Simulation time | 160034158 ps |
| CPU time | 71.24 seconds |
| Started | Aug 13 06:53:25 PM PDT 24 |
| Finished | Aug 13 06:54:36 PM PDT 24 |
| Peak memory | 575624 kb |
| Host | smart-2f3c8973-1c56-4ab5-aa89-52e68a13fdcc |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2233456716 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.xbar_stress_al l_with_reset_error.2233456716 |
| Directory | /workspace/37.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/37.xbar_unmapped_addr.1847323513 |
| Short name | T1781 |
| Test name | |
| Test status | |
| Simulation time | 183899510 ps |
| CPU time | 10.94 seconds |
| Started | Aug 13 06:53:27 PM PDT 24 |
| Finished | Aug 13 06:53:38 PM PDT 24 |
| Peak memory | 574324 kb |
| Host | smart-db56f2ba-dc0f-4f86-966b-5fa640ae8e32 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1847323513 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.xbar_unmapped_addr.1847323513 |
| Directory | /workspace/37.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/38.xbar_access_same_device.2207359724 |
| Short name | T2135 |
| Test name | |
| Test status | |
| Simulation time | 180126872 ps |
| CPU time | 13.68 seconds |
| Started | Aug 13 06:53:34 PM PDT 24 |
| Finished | Aug 13 06:53:48 PM PDT 24 |
| Peak memory | 575624 kb |
| Host | smart-a69e2001-a428-4f5f-8208-97c8bfdbe7db |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2207359724 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.xbar_access_same_device .2207359724 |
| Directory | /workspace/38.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/38.xbar_access_same_device_slow_rsp.785316141 |
| Short name | T2073 |
| Test name | |
| Test status | |
| Simulation time | 124596741544 ps |
| CPU time | 2272.8 seconds |
| Started | Aug 13 06:53:33 PM PDT 24 |
| Finished | Aug 13 07:31:26 PM PDT 24 |
| Peak memory | 575680 kb |
| Host | smart-c9fc87e8-cfa4-44cf-93d0-f7a7090ad275 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=785316141 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.xbar_access_same_d evice_slow_rsp.785316141 |
| Directory | /workspace/38.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/38.xbar_error_and_unmapped_addr.4042161863 |
| Short name | T2421 |
| Test name | |
| Test status | |
| Simulation time | 240374962 ps |
| CPU time | 22.2 seconds |
| Started | Aug 13 06:53:30 PM PDT 24 |
| Finished | Aug 13 06:53:52 PM PDT 24 |
| Peak memory | 575728 kb |
| Host | smart-9f78707b-939d-4d35-9c07-1590c89e9a20 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4042161863 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.xbar_error_and_unmapped_add r.4042161863 |
| Directory | /workspace/38.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/38.xbar_error_random.4045856292 |
| Short name | T2214 |
| Test name | |
| Test status | |
| Simulation time | 644127263 ps |
| CPU time | 54.66 seconds |
| Started | Aug 13 06:53:31 PM PDT 24 |
| Finished | Aug 13 06:54:25 PM PDT 24 |
| Peak memory | 575712 kb |
| Host | smart-73a244d2-75c4-4693-9273-298d934a6357 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4045856292 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.xbar_error_random.4045856292 |
| Directory | /workspace/38.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/38.xbar_random.669654484 |
| Short name | T641 |
| Test name | |
| Test status | |
| Simulation time | 238169473 ps |
| CPU time | 24.42 seconds |
| Started | Aug 13 06:53:40 PM PDT 24 |
| Finished | Aug 13 06:54:05 PM PDT 24 |
| Peak memory | 575816 kb |
| Host | smart-c92ad42d-365a-45fc-87b9-92e9f334d9f8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=669654484 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.xbar_random.669654484 |
| Directory | /workspace/38.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/38.xbar_random_large_delays.2168415369 |
| Short name | T528 |
| Test name | |
| Test status | |
| Simulation time | 49172645145 ps |
| CPU time | 536.27 seconds |
| Started | Aug 13 06:53:33 PM PDT 24 |
| Finished | Aug 13 07:02:29 PM PDT 24 |
| Peak memory | 575784 kb |
| Host | smart-e46fe21f-7947-448a-8fa4-e83c3f22fa82 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2168415369 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.xbar_random_large_delays.2168415369 |
| Directory | /workspace/38.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/38.xbar_random_slow_rsp.1200818555 |
| Short name | T1692 |
| Test name | |
| Test status | |
| Simulation time | 33816676168 ps |
| CPU time | 539.45 seconds |
| Started | Aug 13 06:53:34 PM PDT 24 |
| Finished | Aug 13 07:02:33 PM PDT 24 |
| Peak memory | 575544 kb |
| Host | smart-f82a5aed-b33a-4b2c-b212-7783cf803ff4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1200818555 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.xbar_random_slow_rsp.1200818555 |
| Directory | /workspace/38.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/38.xbar_random_zero_delays.2547359018 |
| Short name | T515 |
| Test name | |
| Test status | |
| Simulation time | 575139345 ps |
| CPU time | 50.93 seconds |
| Started | Aug 13 06:53:31 PM PDT 24 |
| Finished | Aug 13 06:54:22 PM PDT 24 |
| Peak memory | 575640 kb |
| Host | smart-a0614218-a690-40dc-92ba-ac3fc239c80b |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2547359018 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.xbar_random_zero_del ays.2547359018 |
| Directory | /workspace/38.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/38.xbar_same_source.2346919613 |
| Short name | T2797 |
| Test name | |
| Test status | |
| Simulation time | 232336280 ps |
| CPU time | 17.95 seconds |
| Started | Aug 13 06:53:30 PM PDT 24 |
| Finished | Aug 13 06:53:48 PM PDT 24 |
| Peak memory | 575656 kb |
| Host | smart-23b06651-d3b7-43d1-a2a0-4e417d4889a3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2346919613 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.xbar_same_source.2346919613 |
| Directory | /workspace/38.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/38.xbar_smoke.3281240974 |
| Short name | T1573 |
| Test name | |
| Test status | |
| Simulation time | 196596003 ps |
| CPU time | 8.81 seconds |
| Started | Aug 13 06:53:32 PM PDT 24 |
| Finished | Aug 13 06:53:41 PM PDT 24 |
| Peak memory | 574244 kb |
| Host | smart-edb90742-8717-4bcd-a662-9d0646438fa0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3281240974 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.xbar_smoke.3281240974 |
| Directory | /workspace/38.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/38.xbar_smoke_large_delays.2378763779 |
| Short name | T2773 |
| Test name | |
| Test status | |
| Simulation time | 8677183090 ps |
| CPU time | 93.84 seconds |
| Started | Aug 13 06:53:30 PM PDT 24 |
| Finished | Aug 13 06:55:04 PM PDT 24 |
| Peak memory | 573580 kb |
| Host | smart-aa4dfc94-a0d1-4b1d-9713-b3b481823c74 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2378763779 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.xbar_smoke_large_delays.2378763779 |
| Directory | /workspace/38.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/38.xbar_smoke_slow_rsp.3780165218 |
| Short name | T2608 |
| Test name | |
| Test status | |
| Simulation time | 4657062320 ps |
| CPU time | 76.57 seconds |
| Started | Aug 13 06:53:33 PM PDT 24 |
| Finished | Aug 13 06:54:49 PM PDT 24 |
| Peak memory | 573652 kb |
| Host | smart-98394c02-43ef-4d86-bc0e-b845fe8a3d56 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3780165218 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.xbar_smoke_slow_rsp.3780165218 |
| Directory | /workspace/38.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/38.xbar_smoke_zero_delays.2475804227 |
| Short name | T1927 |
| Test name | |
| Test status | |
| Simulation time | 54684448 ps |
| CPU time | 7.12 seconds |
| Started | Aug 13 06:53:33 PM PDT 24 |
| Finished | Aug 13 06:53:40 PM PDT 24 |
| Peak memory | 573596 kb |
| Host | smart-f5bfd3b2-9775-4947-babc-c229b6bb8988 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2475804227 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.xbar_smoke_zero_delay s.2475804227 |
| Directory | /workspace/38.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/38.xbar_stress_all.198654355 |
| Short name | T2009 |
| Test name | |
| Test status | |
| Simulation time | 12547419953 ps |
| CPU time | 552.74 seconds |
| Started | Aug 13 06:53:31 PM PDT 24 |
| Finished | Aug 13 07:02:44 PM PDT 24 |
| Peak memory | 575728 kb |
| Host | smart-e9d90634-2e3f-4280-bb7d-93a385071fdc |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=198654355 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.xbar_stress_all.198654355 |
| Directory | /workspace/38.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/38.xbar_stress_all_with_error.231460452 |
| Short name | T775 |
| Test name | |
| Test status | |
| Simulation time | 2768808702 ps |
| CPU time | 239.9 seconds |
| Started | Aug 13 06:53:39 PM PDT 24 |
| Finished | Aug 13 06:57:39 PM PDT 24 |
| Peak memory | 576336 kb |
| Host | smart-8225d2cb-e39d-47a4-add1-9bbcca8ed671 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=231460452 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.xbar_stress_all_with_error.231460452 |
| Directory | /workspace/38.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/38.xbar_stress_all_with_rand_reset.65471728 |
| Short name | T2098 |
| Test name | |
| Test status | |
| Simulation time | 95260847 ps |
| CPU time | 44.04 seconds |
| Started | Aug 13 06:53:32 PM PDT 24 |
| Finished | Aug 13 06:54:16 PM PDT 24 |
| Peak memory | 576464 kb |
| Host | smart-6c564494-52ca-4645-b375-3b89b9d623fd |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=65471728 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_rese t_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.xbar_stress_all_w ith_rand_reset.65471728 |
| Directory | /workspace/38.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/38.xbar_stress_all_with_reset_error.3199124960 |
| Short name | T2533 |
| Test name | |
| Test status | |
| Simulation time | 3281026613 ps |
| CPU time | 321.13 seconds |
| Started | Aug 13 06:53:39 PM PDT 24 |
| Finished | Aug 13 06:59:00 PM PDT 24 |
| Peak memory | 576564 kb |
| Host | smart-ab0ba1c4-7c28-4380-b4e4-84165987d3cb |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3199124960 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.xbar_stress_al l_with_reset_error.3199124960 |
| Directory | /workspace/38.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/38.xbar_unmapped_addr.3384693989 |
| Short name | T653 |
| Test name | |
| Test status | |
| Simulation time | 225110659 ps |
| CPU time | 23.35 seconds |
| Started | Aug 13 06:53:32 PM PDT 24 |
| Finished | Aug 13 06:53:55 PM PDT 24 |
| Peak memory | 575540 kb |
| Host | smart-0a03cdee-d2ca-4bfe-ad73-d9a394f4947c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3384693989 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.xbar_unmapped_addr.3384693989 |
| Directory | /workspace/38.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/39.xbar_access_same_device.821383416 |
| Short name | T2695 |
| Test name | |
| Test status | |
| Simulation time | 2060435214 ps |
| CPU time | 100.33 seconds |
| Started | Aug 13 06:53:39 PM PDT 24 |
| Finished | Aug 13 06:55:20 PM PDT 24 |
| Peak memory | 575532 kb |
| Host | smart-cff1836b-cf5f-40ea-b997-efe0406a7535 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=821383416 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.xbar_access_same_device. 821383416 |
| Directory | /workspace/39.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/39.xbar_access_same_device_slow_rsp.272827710 |
| Short name | T873 |
| Test name | |
| Test status | |
| Simulation time | 93772574763 ps |
| CPU time | 1611.89 seconds |
| Started | Aug 13 06:53:38 PM PDT 24 |
| Finished | Aug 13 07:20:30 PM PDT 24 |
| Peak memory | 575756 kb |
| Host | smart-90d4d7a0-eeda-4c63-a555-1efa762fbc21 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=272827710 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.xbar_access_same_d evice_slow_rsp.272827710 |
| Directory | /workspace/39.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/39.xbar_error_and_unmapped_addr.2378548932 |
| Short name | T1952 |
| Test name | |
| Test status | |
| Simulation time | 1341242925 ps |
| CPU time | 56.3 seconds |
| Started | Aug 13 06:53:38 PM PDT 24 |
| Finished | Aug 13 06:54:34 PM PDT 24 |
| Peak memory | 575712 kb |
| Host | smart-f5524eec-1d82-417d-a347-ad9fd711e3c1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2378548932 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.xbar_error_and_unmapped_add r.2378548932 |
| Directory | /workspace/39.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/39.xbar_error_random.1720040598 |
| Short name | T2101 |
| Test name | |
| Test status | |
| Simulation time | 1528522170 ps |
| CPU time | 57.82 seconds |
| Started | Aug 13 06:53:38 PM PDT 24 |
| Finished | Aug 13 06:54:36 PM PDT 24 |
| Peak memory | 575736 kb |
| Host | smart-b6951ef5-d409-4997-aa8e-24d0f012a80e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1720040598 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.xbar_error_random.1720040598 |
| Directory | /workspace/39.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/39.xbar_random.288453099 |
| Short name | T1635 |
| Test name | |
| Test status | |
| Simulation time | 134569724 ps |
| CPU time | 8.54 seconds |
| Started | Aug 13 06:53:44 PM PDT 24 |
| Finished | Aug 13 06:53:52 PM PDT 24 |
| Peak memory | 573564 kb |
| Host | smart-d6ea13c7-2ab3-4bfa-be4a-31267301b4b7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=288453099 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.xbar_random.288453099 |
| Directory | /workspace/39.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/39.xbar_random_large_delays.2896018589 |
| Short name | T1648 |
| Test name | |
| Test status | |
| Simulation time | 39389226537 ps |
| CPU time | 428.15 seconds |
| Started | Aug 13 06:53:41 PM PDT 24 |
| Finished | Aug 13 07:00:49 PM PDT 24 |
| Peak memory | 575876 kb |
| Host | smart-94a0531c-8285-4d03-b886-ae61bd1d81f9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2896018589 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.xbar_random_large_delays.2896018589 |
| Directory | /workspace/39.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/39.xbar_random_slow_rsp.2344532488 |
| Short name | T619 |
| Test name | |
| Test status | |
| Simulation time | 3773822597 ps |
| CPU time | 62.69 seconds |
| Started | Aug 13 06:53:41 PM PDT 24 |
| Finished | Aug 13 06:54:45 PM PDT 24 |
| Peak memory | 574364 kb |
| Host | smart-aaba9a11-054b-4cf4-bb3d-a59a0af6687f |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2344532488 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.xbar_random_slow_rsp.2344532488 |
| Directory | /workspace/39.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/39.xbar_random_zero_delays.55561412 |
| Short name | T2095 |
| Test name | |
| Test status | |
| Simulation time | 236458241 ps |
| CPU time | 18.96 seconds |
| Started | Aug 13 06:53:36 PM PDT 24 |
| Finished | Aug 13 06:53:55 PM PDT 24 |
| Peak memory | 575640 kb |
| Host | smart-a9dcd976-2cd3-4997-b067-1f835a4d8db7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=55561412 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.xbar_random_zero_delay s.55561412 |
| Directory | /workspace/39.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/39.xbar_same_source.1404899866 |
| Short name | T1862 |
| Test name | |
| Test status | |
| Simulation time | 236113744 ps |
| CPU time | 19.7 seconds |
| Started | Aug 13 06:53:42 PM PDT 24 |
| Finished | Aug 13 06:54:02 PM PDT 24 |
| Peak memory | 575472 kb |
| Host | smart-ecf2d93a-8158-4ed7-a24f-294ef8df52ea |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1404899866 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.xbar_same_source.1404899866 |
| Directory | /workspace/39.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/39.xbar_smoke.2935111819 |
| Short name | T1647 |
| Test name | |
| Test status | |
| Simulation time | 50305139 ps |
| CPU time | 6.62 seconds |
| Started | Aug 13 06:53:38 PM PDT 24 |
| Finished | Aug 13 06:53:45 PM PDT 24 |
| Peak memory | 574208 kb |
| Host | smart-3318e705-3648-4042-99cf-eac83cf94b4c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2935111819 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.xbar_smoke.2935111819 |
| Directory | /workspace/39.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/39.xbar_smoke_large_delays.830788864 |
| Short name | T2653 |
| Test name | |
| Test status | |
| Simulation time | 8056239321 ps |
| CPU time | 82.1 seconds |
| Started | Aug 13 06:53:42 PM PDT 24 |
| Finished | Aug 13 06:55:05 PM PDT 24 |
| Peak memory | 573576 kb |
| Host | smart-d9cc4815-df9d-4e1d-8ed7-55961ad28fc5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=830788864 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.xbar_smoke_large_delays.830788864 |
| Directory | /workspace/39.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/39.xbar_smoke_slow_rsp.2775296918 |
| Short name | T2102 |
| Test name | |
| Test status | |
| Simulation time | 4465185175 ps |
| CPU time | 78.6 seconds |
| Started | Aug 13 06:53:44 PM PDT 24 |
| Finished | Aug 13 06:55:03 PM PDT 24 |
| Peak memory | 573680 kb |
| Host | smart-7c7b1db5-f30f-4876-80d9-cb7f6ab41817 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2775296918 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.xbar_smoke_slow_rsp.2775296918 |
| Directory | /workspace/39.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/39.xbar_smoke_zero_delays.2934323696 |
| Short name | T1449 |
| Test name | |
| Test status | |
| Simulation time | 36733238 ps |
| CPU time | 5.74 seconds |
| Started | Aug 13 06:53:44 PM PDT 24 |
| Finished | Aug 13 06:53:50 PM PDT 24 |
| Peak memory | 573520 kb |
| Host | smart-14a738c2-1f0a-4aa5-b24c-0a10aa547399 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2934323696 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.xbar_smoke_zero_delay s.2934323696 |
| Directory | /workspace/39.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/39.xbar_stress_all.812451232 |
| Short name | T2850 |
| Test name | |
| Test status | |
| Simulation time | 2596802534 ps |
| CPU time | 204.93 seconds |
| Started | Aug 13 06:53:39 PM PDT 24 |
| Finished | Aug 13 06:57:04 PM PDT 24 |
| Peak memory | 576516 kb |
| Host | smart-63ca0f6a-d47b-47b6-a7a2-3822211ba307 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=812451232 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.xbar_stress_all.812451232 |
| Directory | /workspace/39.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/39.xbar_stress_all_with_error.3373986365 |
| Short name | T707 |
| Test name | |
| Test status | |
| Simulation time | 2830221149 ps |
| CPU time | 246.41 seconds |
| Started | Aug 13 06:53:51 PM PDT 24 |
| Finished | Aug 13 06:57:58 PM PDT 24 |
| Peak memory | 576528 kb |
| Host | smart-4602fcc6-4f00-4043-9002-9cbedec5be9b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3373986365 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.xbar_stress_all_with_error.3373986365 |
| Directory | /workspace/39.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/39.xbar_stress_all_with_rand_reset.3891489233 |
| Short name | T2526 |
| Test name | |
| Test status | |
| Simulation time | 45885283 ps |
| CPU time | 10.68 seconds |
| Started | Aug 13 06:53:47 PM PDT 24 |
| Finished | Aug 13 06:53:57 PM PDT 24 |
| Peak memory | 575764 kb |
| Host | smart-49a49874-1943-4950-a469-009153158788 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3891489233 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.xbar_stress_all _with_rand_reset.3891489233 |
| Directory | /workspace/39.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/39.xbar_stress_all_with_reset_error.405400531 |
| Short name | T2262 |
| Test name | |
| Test status | |
| Simulation time | 848761099 ps |
| CPU time | 292.73 seconds |
| Started | Aug 13 06:53:54 PM PDT 24 |
| Finished | Aug 13 06:58:47 PM PDT 24 |
| Peak memory | 575636 kb |
| Host | smart-1db8bd3e-36cb-4976-9193-a7baccab6dfe |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=405400531 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.xbar_stress_all _with_reset_error.405400531 |
| Directory | /workspace/39.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/39.xbar_unmapped_addr.2288266452 |
| Short name | T2541 |
| Test name | |
| Test status | |
| Simulation time | 330013459 ps |
| CPU time | 39.09 seconds |
| Started | Aug 13 06:53:37 PM PDT 24 |
| Finished | Aug 13 06:54:17 PM PDT 24 |
| Peak memory | 575752 kb |
| Host | smart-1288bb36-1881-471c-99c1-0ce99777f954 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2288266452 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.xbar_unmapped_addr.2288266452 |
| Directory | /workspace/39.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/4.chip_csr_aliasing.3698198831 |
| Short name | T427 |
| Test name | |
| Test status | |
| Simulation time | 36765439735 ps |
| CPU time | 6308.01 seconds |
| Started | Aug 13 06:50:47 PM PDT 24 |
| Finished | Aug 13 08:35:56 PM PDT 24 |
| Peak memory | 593744 kb |
| Host | smart-d9083d95-738a-4acb-a1d8-f08658089800 |
| User | root |
| Command | /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +csr_aliasing +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3698198831 -assert nopostproc +UVM_TESTNAME=chip_ base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/ null -cm_name 4.chip_csr_aliasing.3698198831 |
| Directory | /workspace/4.chip_csr_aliasing/latest |
| Test location | /workspace/coverage/cover_reg_top/4.chip_csr_bit_bash.137768747 |
| Short name | T1709 |
| Test name | |
| Test status | |
| Simulation time | 14819791340 ps |
| CPU time | 1793.26 seconds |
| Started | Aug 13 06:50:47 PM PDT 24 |
| Finished | Aug 13 07:20:41 PM PDT 24 |
| Peak memory | 592204 kb |
| Host | smart-15cb4c94-7078-485f-af90-739bf0c7d64e |
| User | root |
| Command | /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +num_test_csrs=200 +csr_bit_bash +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=137768747 -assert nopostproc + UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top .vdb -cm_log /dev/null -cm_name 4.chip_csr_bit_bash.137768747 |
| Directory | /workspace/4.chip_csr_bit_bash/latest |
| Test location | /workspace/coverage/cover_reg_top/4.chip_csr_mem_rw_with_rand_reset.2248960053 |
| Short name | T2369 |
| Test name | |
| Test status | |
| Simulation time | 6526037410 ps |
| CPU time | 588.22 seconds |
| Started | Aug 13 06:50:47 PM PDT 24 |
| Finished | Aug 13 07:00:35 PM PDT 24 |
| Peak memory | 638272 kb |
| Host | smart-aaa2a5a6-4615-4138-897c-0d9e63060e74 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2248960053 -assert nopostproc + UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top .vdb -cm_log /dev/null -cm_name 4.chip_csr_mem_rw_with_rand_reset.2248960053 |
| Directory | /workspace/4.chip_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/4.chip_csr_rw.4159627419 |
| Short name | T1950 |
| Test name | |
| Test status | |
| Simulation time | 3992080120 ps |
| CPU time | 363.05 seconds |
| Started | Aug 13 06:50:55 PM PDT 24 |
| Finished | Aug 13 06:56:58 PM PDT 24 |
| Peak memory | 598976 kb |
| Host | smart-8e1b37f4-b59a-4469-864b-ff3467110d4b |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4159627419 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.chip_csr_rw.4159627419 |
| Directory | /workspace/4.chip_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/4.chip_same_csr_outstanding.859973369 |
| Short name | T2905 |
| Test name | |
| Test status | |
| Simulation time | 16807896150 ps |
| CPU time | 1742.41 seconds |
| Started | Aug 13 06:51:00 PM PDT 24 |
| Finished | Aug 13 07:20:02 PM PDT 24 |
| Peak memory | 592704 kb |
| Host | smart-9897b444-46cf-4b64-8ea6-940e31fe52e5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +run_same_csr_outstanding +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=859973369 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c m_log /dev/null -cm_name 4.chip_same_csr_outstanding.859973369 |
| Directory | /workspace/4.chip_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/4.xbar_access_same_device.1686773241 |
| Short name | T486 |
| Test name | |
| Test status | |
| Simulation time | 1023220578 ps |
| CPU time | 71.22 seconds |
| Started | Aug 13 06:50:57 PM PDT 24 |
| Finished | Aug 13 06:52:08 PM PDT 24 |
| Peak memory | 575720 kb |
| Host | smart-c4ec7194-5e8e-4c9c-aeeb-bb6ee31d034b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1686773241 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.xbar_access_same_device. 1686773241 |
| Directory | /workspace/4.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/4.xbar_access_same_device_slow_rsp.1141931084 |
| Short name | T2322 |
| Test name | |
| Test status | |
| Simulation time | 119245753504 ps |
| CPU time | 2053.63 seconds |
| Started | Aug 13 06:50:54 PM PDT 24 |
| Finished | Aug 13 07:25:09 PM PDT 24 |
| Peak memory | 575860 kb |
| Host | smart-1b6d577c-649b-4587-afb4-48451e7f250d |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1141931084 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.xbar_access_same_d evice_slow_rsp.1141931084 |
| Directory | /workspace/4.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/4.xbar_error_and_unmapped_addr.2085874163 |
| Short name | T1471 |
| Test name | |
| Test status | |
| Simulation time | 1071451137 ps |
| CPU time | 40.19 seconds |
| Started | Aug 13 06:50:55 PM PDT 24 |
| Finished | Aug 13 06:51:36 PM PDT 24 |
| Peak memory | 575588 kb |
| Host | smart-caf47ef4-d2f8-4abb-b062-5111cbe03467 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2085874163 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.xbar_error_and_unmapped_addr .2085874163 |
| Directory | /workspace/4.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/4.xbar_error_random.3001613919 |
| Short name | T1717 |
| Test name | |
| Test status | |
| Simulation time | 2468975519 ps |
| CPU time | 77.6 seconds |
| Started | Aug 13 06:50:52 PM PDT 24 |
| Finished | Aug 13 06:52:09 PM PDT 24 |
| Peak memory | 575656 kb |
| Host | smart-e1959bdc-d5e7-4d37-9c52-b4551cde5361 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3001613919 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.xbar_error_random.3001613919 |
| Directory | /workspace/4.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/4.xbar_random.635281458 |
| Short name | T2689 |
| Test name | |
| Test status | |
| Simulation time | 31024625 ps |
| CPU time | 5.82 seconds |
| Started | Aug 13 06:50:48 PM PDT 24 |
| Finished | Aug 13 06:50:54 PM PDT 24 |
| Peak memory | 574264 kb |
| Host | smart-5ca96f69-53b1-41b5-a9fe-0c2755518b91 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=635281458 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.xbar_random.635281458 |
| Directory | /workspace/4.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/4.xbar_random_large_delays.1765177192 |
| Short name | T1847 |
| Test name | |
| Test status | |
| Simulation time | 90036062687 ps |
| CPU time | 1015.15 seconds |
| Started | Aug 13 06:50:52 PM PDT 24 |
| Finished | Aug 13 07:07:47 PM PDT 24 |
| Peak memory | 575604 kb |
| Host | smart-0d4b6d4d-14eb-4b11-ba9b-5d58bce43608 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1765177192 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.xbar_random_large_delays.1765177192 |
| Directory | /workspace/4.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/4.xbar_random_slow_rsp.665633590 |
| Short name | T561 |
| Test name | |
| Test status | |
| Simulation time | 3732920615 ps |
| CPU time | 63.92 seconds |
| Started | Aug 13 06:50:39 PM PDT 24 |
| Finished | Aug 13 06:51:43 PM PDT 24 |
| Peak memory | 574332 kb |
| Host | smart-d3aaab42-bcfa-4134-8dd3-e23c9e66be68 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=665633590 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.xbar_random_slow_rsp.665633590 |
| Directory | /workspace/4.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/4.xbar_random_zero_delays.2737129770 |
| Short name | T508 |
| Test name | |
| Test status | |
| Simulation time | 222454566 ps |
| CPU time | 19.62 seconds |
| Started | Aug 13 06:50:51 PM PDT 24 |
| Finished | Aug 13 06:51:11 PM PDT 24 |
| Peak memory | 575620 kb |
| Host | smart-2d19cfc5-e560-4b3c-8633-12efd2082316 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2737129770 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.xbar_random_zero_dela ys.2737129770 |
| Directory | /workspace/4.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/4.xbar_same_source.2523917992 |
| Short name | T1711 |
| Test name | |
| Test status | |
| Simulation time | 616920717 ps |
| CPU time | 19.63 seconds |
| Started | Aug 13 06:50:57 PM PDT 24 |
| Finished | Aug 13 06:51:16 PM PDT 24 |
| Peak memory | 575492 kb |
| Host | smart-980dcb5e-c2bf-42cc-b5ad-6aefdd527615 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2523917992 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.xbar_same_source.2523917992 |
| Directory | /workspace/4.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/4.xbar_smoke.2033330307 |
| Short name | T1515 |
| Test name | |
| Test status | |
| Simulation time | 232517989 ps |
| CPU time | 9.08 seconds |
| Started | Aug 13 06:50:52 PM PDT 24 |
| Finished | Aug 13 06:51:01 PM PDT 24 |
| Peak memory | 573616 kb |
| Host | smart-442f220e-3a2f-4387-9b08-51e44474d9b5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2033330307 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.xbar_smoke.2033330307 |
| Directory | /workspace/4.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/4.xbar_smoke_large_delays.3060786255 |
| Short name | T494 |
| Test name | |
| Test status | |
| Simulation time | 9108259153 ps |
| CPU time | 83.22 seconds |
| Started | Aug 13 06:50:54 PM PDT 24 |
| Finished | Aug 13 06:52:18 PM PDT 24 |
| Peak memory | 573576 kb |
| Host | smart-2de5ab2e-981d-4f88-862f-3d7896a916d7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3060786255 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.xbar_smoke_large_delays.3060786255 |
| Directory | /workspace/4.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/4.xbar_smoke_slow_rsp.2802876175 |
| Short name | T1948 |
| Test name | |
| Test status | |
| Simulation time | 6911355569 ps |
| CPU time | 116.54 seconds |
| Started | Aug 13 06:51:02 PM PDT 24 |
| Finished | Aug 13 06:52:58 PM PDT 24 |
| Peak memory | 574312 kb |
| Host | smart-ce741e4a-b605-42d5-8c32-a4508ea4d269 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2802876175 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.xbar_smoke_slow_rsp.2802876175 |
| Directory | /workspace/4.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/4.xbar_smoke_zero_delays.365261307 |
| Short name | T2536 |
| Test name | |
| Test status | |
| Simulation time | 58435971 ps |
| CPU time | 6.41 seconds |
| Started | Aug 13 06:50:52 PM PDT 24 |
| Finished | Aug 13 06:50:59 PM PDT 24 |
| Peak memory | 573528 kb |
| Host | smart-891b3a5d-b2cf-426d-b985-b1a6549a99d6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=365261307 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.xbar_smoke_zero_delays. 365261307 |
| Directory | /workspace/4.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/4.xbar_stress_all.3907258799 |
| Short name | T1548 |
| Test name | |
| Test status | |
| Simulation time | 161240459 ps |
| CPU time | 19.3 seconds |
| Started | Aug 13 06:50:52 PM PDT 24 |
| Finished | Aug 13 06:51:11 PM PDT 24 |
| Peak memory | 575716 kb |
| Host | smart-70bc20ba-200f-4553-8ac0-553c418236d6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3907258799 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.xbar_stress_all.3907258799 |
| Directory | /workspace/4.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/4.xbar_stress_all_with_error.72713600 |
| Short name | T1460 |
| Test name | |
| Test status | |
| Simulation time | 4344831432 ps |
| CPU time | 151.48 seconds |
| Started | Aug 13 06:50:57 PM PDT 24 |
| Finished | Aug 13 06:53:28 PM PDT 24 |
| Peak memory | 576164 kb |
| Host | smart-eec5676a-f0c7-48f6-bc2b-1558e19f9cf4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=72713600 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.xbar_stress_all_with_error.72713600 |
| Directory | /workspace/4.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/4.xbar_stress_all_with_rand_reset.99933593 |
| Short name | T2137 |
| Test name | |
| Test status | |
| Simulation time | 6142703805 ps |
| CPU time | 635.7 seconds |
| Started | Aug 13 06:50:57 PM PDT 24 |
| Finished | Aug 13 07:01:33 PM PDT 24 |
| Peak memory | 576512 kb |
| Host | smart-60b478a8-9939-468d-8866-fb92896b2d0b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=99933593 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_rese t_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.xbar_stress_all_wi th_rand_reset.99933593 |
| Directory | /workspace/4.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/4.xbar_stress_all_with_reset_error.4218852630 |
| Short name | T1621 |
| Test name | |
| Test status | |
| Simulation time | 429731180 ps |
| CPU time | 104.73 seconds |
| Started | Aug 13 06:50:56 PM PDT 24 |
| Finished | Aug 13 06:52:41 PM PDT 24 |
| Peak memory | 576476 kb |
| Host | smart-df9047d1-0a49-40cc-93b9-cbb1f9b11d33 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4218852630 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.xbar_stress_all _with_reset_error.4218852630 |
| Directory | /workspace/4.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/4.xbar_unmapped_addr.288627925 |
| Short name | T2521 |
| Test name | |
| Test status | |
| Simulation time | 1134538073 ps |
| CPU time | 42.6 seconds |
| Started | Aug 13 06:50:52 PM PDT 24 |
| Finished | Aug 13 06:51:35 PM PDT 24 |
| Peak memory | 575528 kb |
| Host | smart-1999b11a-7a34-4663-acdd-2be09d99cac7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=288627925 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.xbar_unmapped_addr.288627925 |
| Directory | /workspace/4.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/40.xbar_access_same_device.1405567162 |
| Short name | T1767 |
| Test name | |
| Test status | |
| Simulation time | 13094680 ps |
| CPU time | 5.55 seconds |
| Started | Aug 13 06:53:53 PM PDT 24 |
| Finished | Aug 13 06:53:59 PM PDT 24 |
| Peak memory | 573544 kb |
| Host | smart-772744a9-1848-4ca0-880e-d3581fd49640 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1405567162 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.xbar_access_same_device .1405567162 |
| Directory | /workspace/40.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/40.xbar_access_same_device_slow_rsp.143160831 |
| Short name | T2374 |
| Test name | |
| Test status | |
| Simulation time | 21571272428 ps |
| CPU time | 360.77 seconds |
| Started | Aug 13 06:53:53 PM PDT 24 |
| Finished | Aug 13 06:59:54 PM PDT 24 |
| Peak memory | 575748 kb |
| Host | smart-3b037f6d-3db8-4324-b683-45e81dc4888f |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=143160831 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.xbar_access_same_d evice_slow_rsp.143160831 |
| Directory | /workspace/40.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/40.xbar_error_and_unmapped_addr.2190693186 |
| Short name | T2333 |
| Test name | |
| Test status | |
| Simulation time | 359615249 ps |
| CPU time | 38.63 seconds |
| Started | Aug 13 06:53:45 PM PDT 24 |
| Finished | Aug 13 06:54:24 PM PDT 24 |
| Peak memory | 575728 kb |
| Host | smart-22961492-fc7d-4b16-8162-ff7fb4d48361 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2190693186 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.xbar_error_and_unmapped_add r.2190693186 |
| Directory | /workspace/40.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/40.xbar_error_random.3929544955 |
| Short name | T2865 |
| Test name | |
| Test status | |
| Simulation time | 133346019 ps |
| CPU time | 14.79 seconds |
| Started | Aug 13 06:53:55 PM PDT 24 |
| Finished | Aug 13 06:54:10 PM PDT 24 |
| Peak memory | 575472 kb |
| Host | smart-df5212a8-c61f-42e8-a07f-c238c3a62596 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3929544955 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.xbar_error_random.3929544955 |
| Directory | /workspace/40.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/40.xbar_random.3259051134 |
| Short name | T2405 |
| Test name | |
| Test status | |
| Simulation time | 1281493394 ps |
| CPU time | 45.66 seconds |
| Started | Aug 13 06:53:52 PM PDT 24 |
| Finished | Aug 13 06:54:38 PM PDT 24 |
| Peak memory | 575560 kb |
| Host | smart-6dda8ab0-6b16-4596-a027-ef3b12cbe0ce |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3259051134 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.xbar_random.3259051134 |
| Directory | /workspace/40.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/40.xbar_random_large_delays.369009087 |
| Short name | T1949 |
| Test name | |
| Test status | |
| Simulation time | 107889362880 ps |
| CPU time | 1262.15 seconds |
| Started | Aug 13 06:53:52 PM PDT 24 |
| Finished | Aug 13 07:14:55 PM PDT 24 |
| Peak memory | 575716 kb |
| Host | smart-13b1b663-8cc5-4c11-b77b-39939ff9ba47 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=369009087 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.xbar_random_large_delays.369009087 |
| Directory | /workspace/40.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/40.xbar_random_slow_rsp.517642077 |
| Short name | T625 |
| Test name | |
| Test status | |
| Simulation time | 54117720836 ps |
| CPU time | 915.48 seconds |
| Started | Aug 13 06:53:51 PM PDT 24 |
| Finished | Aug 13 07:09:07 PM PDT 24 |
| Peak memory | 575836 kb |
| Host | smart-546d1210-5993-47f8-ba7b-8a3d8ab21555 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=517642077 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.xbar_random_slow_rsp.517642077 |
| Directory | /workspace/40.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/40.xbar_random_zero_delays.1420581867 |
| Short name | T2154 |
| Test name | |
| Test status | |
| Simulation time | 295779995 ps |
| CPU time | 27.68 seconds |
| Started | Aug 13 06:53:53 PM PDT 24 |
| Finished | Aug 13 06:54:21 PM PDT 24 |
| Peak memory | 575652 kb |
| Host | smart-3ddc8234-d5a5-49e5-a411-79022b7f7d68 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1420581867 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.xbar_random_zero_del ays.1420581867 |
| Directory | /workspace/40.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/40.xbar_same_source.3406448780 |
| Short name | T1881 |
| Test name | |
| Test status | |
| Simulation time | 133121230 ps |
| CPU time | 12.22 seconds |
| Started | Aug 13 06:53:52 PM PDT 24 |
| Finished | Aug 13 06:54:04 PM PDT 24 |
| Peak memory | 575560 kb |
| Host | smart-6e8cd4f6-2a86-4bbd-9fef-c49144302fa2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3406448780 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.xbar_same_source.3406448780 |
| Directory | /workspace/40.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/40.xbar_smoke.3105412399 |
| Short name | T1921 |
| Test name | |
| Test status | |
| Simulation time | 51481858 ps |
| CPU time | 6.81 seconds |
| Started | Aug 13 06:53:53 PM PDT 24 |
| Finished | Aug 13 06:54:00 PM PDT 24 |
| Peak memory | 574272 kb |
| Host | smart-2145a353-c221-445d-a7f2-8b932defee53 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3105412399 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.xbar_smoke.3105412399 |
| Directory | /workspace/40.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/40.xbar_smoke_large_delays.946419445 |
| Short name | T2219 |
| Test name | |
| Test status | |
| Simulation time | 7809811868 ps |
| CPU time | 78.94 seconds |
| Started | Aug 13 06:53:52 PM PDT 24 |
| Finished | Aug 13 06:55:12 PM PDT 24 |
| Peak memory | 574296 kb |
| Host | smart-26841c4c-0bc1-4d7f-965d-e057696c5f7e |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=946419445 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.xbar_smoke_large_delays.946419445 |
| Directory | /workspace/40.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/40.xbar_smoke_slow_rsp.3427634724 |
| Short name | T2924 |
| Test name | |
| Test status | |
| Simulation time | 3528340616 ps |
| CPU time | 59.61 seconds |
| Started | Aug 13 06:53:46 PM PDT 24 |
| Finished | Aug 13 06:54:46 PM PDT 24 |
| Peak memory | 574244 kb |
| Host | smart-2020445c-d7b0-4674-9540-d51847b1e8bc |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3427634724 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.xbar_smoke_slow_rsp.3427634724 |
| Directory | /workspace/40.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/40.xbar_smoke_zero_delays.1053265810 |
| Short name | T2487 |
| Test name | |
| Test status | |
| Simulation time | 44797694 ps |
| CPU time | 6.68 seconds |
| Started | Aug 13 06:53:48 PM PDT 24 |
| Finished | Aug 13 06:53:55 PM PDT 24 |
| Peak memory | 573600 kb |
| Host | smart-b93c2310-73d2-4715-bcd5-9318988befe3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1053265810 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.xbar_smoke_zero_delay s.1053265810 |
| Directory | /workspace/40.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/40.xbar_stress_all.907797491 |
| Short name | T2605 |
| Test name | |
| Test status | |
| Simulation time | 446794979 ps |
| CPU time | 40.15 seconds |
| Started | Aug 13 06:53:54 PM PDT 24 |
| Finished | Aug 13 06:54:34 PM PDT 24 |
| Peak memory | 575736 kb |
| Host | smart-feee02c7-7267-4f23-bb93-d1afe53df5b4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=907797491 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.xbar_stress_all.907797491 |
| Directory | /workspace/40.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/40.xbar_stress_all_with_error.2969990988 |
| Short name | T743 |
| Test name | |
| Test status | |
| Simulation time | 9577520906 ps |
| CPU time | 372.2 seconds |
| Started | Aug 13 06:53:49 PM PDT 24 |
| Finished | Aug 13 07:00:02 PM PDT 24 |
| Peak memory | 576536 kb |
| Host | smart-329b2893-eadc-4f32-b79a-f12d0a0941a2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2969990988 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.xbar_stress_all_with_error.2969990988 |
| Directory | /workspace/40.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/40.xbar_stress_all_with_rand_reset.823655120 |
| Short name | T1964 |
| Test name | |
| Test status | |
| Simulation time | 574846756 ps |
| CPU time | 177.59 seconds |
| Started | Aug 13 06:53:47 PM PDT 24 |
| Finished | Aug 13 06:56:45 PM PDT 24 |
| Peak memory | 576480 kb |
| Host | smart-d565c235-6229-4600-90bc-102c0c741a21 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=823655120 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_res et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.xbar_stress_all_ with_rand_reset.823655120 |
| Directory | /workspace/40.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/40.xbar_stress_all_with_reset_error.4208095579 |
| Short name | T2438 |
| Test name | |
| Test status | |
| Simulation time | 100152630 ps |
| CPU time | 27.54 seconds |
| Started | Aug 13 06:53:47 PM PDT 24 |
| Finished | Aug 13 06:54:15 PM PDT 24 |
| Peak memory | 574460 kb |
| Host | smart-cfa4de3e-37b4-4bf5-bb4f-004ba60c17d5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4208095579 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.xbar_stress_al l_with_reset_error.4208095579 |
| Directory | /workspace/40.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/40.xbar_unmapped_addr.4166661092 |
| Short name | T2346 |
| Test name | |
| Test status | |
| Simulation time | 108446479 ps |
| CPU time | 15.49 seconds |
| Started | Aug 13 06:53:45 PM PDT 24 |
| Finished | Aug 13 06:54:01 PM PDT 24 |
| Peak memory | 575732 kb |
| Host | smart-17e42e3b-bd3f-4676-b7d2-3ec36f594a4e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4166661092 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.xbar_unmapped_addr.4166661092 |
| Directory | /workspace/40.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/41.xbar_access_same_device.3432690140 |
| Short name | T875 |
| Test name | |
| Test status | |
| Simulation time | 1978516937 ps |
| CPU time | 66.62 seconds |
| Started | Aug 13 06:54:06 PM PDT 24 |
| Finished | Aug 13 06:55:13 PM PDT 24 |
| Peak memory | 576424 kb |
| Host | smart-22dc523d-065d-4850-9e5d-86500f2c2685 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3432690140 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.xbar_access_same_device .3432690140 |
| Directory | /workspace/41.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/41.xbar_access_same_device_slow_rsp.2068510011 |
| Short name | T1736 |
| Test name | |
| Test status | |
| Simulation time | 2763450922 ps |
| CPU time | 45.22 seconds |
| Started | Aug 13 06:54:05 PM PDT 24 |
| Finished | Aug 13 06:54:51 PM PDT 24 |
| Peak memory | 574308 kb |
| Host | smart-2e3cdd3b-8bfc-4368-9612-8892c3a1e4bf |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2068510011 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.xbar_access_same_ device_slow_rsp.2068510011 |
| Directory | /workspace/41.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/41.xbar_error_and_unmapped_addr.2658440482 |
| Short name | T1505 |
| Test name | |
| Test status | |
| Simulation time | 97124497 ps |
| CPU time | 13.12 seconds |
| Started | Aug 13 06:53:54 PM PDT 24 |
| Finished | Aug 13 06:54:07 PM PDT 24 |
| Peak memory | 575728 kb |
| Host | smart-f6a8394b-d05e-4362-830c-11649ad6fdf0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2658440482 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.xbar_error_and_unmapped_add r.2658440482 |
| Directory | /workspace/41.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/41.xbar_error_random.3762876776 |
| Short name | T728 |
| Test name | |
| Test status | |
| Simulation time | 748246348 ps |
| CPU time | 26.7 seconds |
| Started | Aug 13 06:53:54 PM PDT 24 |
| Finished | Aug 13 06:54:21 PM PDT 24 |
| Peak memory | 575700 kb |
| Host | smart-9fd77e00-970e-4e0b-9426-0bea8159de57 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3762876776 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.xbar_error_random.3762876776 |
| Directory | /workspace/41.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/41.xbar_random.2004809578 |
| Short name | T680 |
| Test name | |
| Test status | |
| Simulation time | 207963570 ps |
| CPU time | 10.02 seconds |
| Started | Aug 13 06:54:06 PM PDT 24 |
| Finished | Aug 13 06:54:16 PM PDT 24 |
| Peak memory | 573552 kb |
| Host | smart-ea7fc95e-4e50-407f-b37f-e48ae4c70a61 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2004809578 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.xbar_random.2004809578 |
| Directory | /workspace/41.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/41.xbar_random_large_delays.1965785536 |
| Short name | T2926 |
| Test name | |
| Test status | |
| Simulation time | 20640119767 ps |
| CPU time | 203.26 seconds |
| Started | Aug 13 06:53:54 PM PDT 24 |
| Finished | Aug 13 06:57:17 PM PDT 24 |
| Peak memory | 575644 kb |
| Host | smart-09a28b7d-19ed-4616-9c08-cbb9b4ab4e17 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1965785536 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.xbar_random_large_delays.1965785536 |
| Directory | /workspace/41.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/41.xbar_random_slow_rsp.3647415560 |
| Short name | T2305 |
| Test name | |
| Test status | |
| Simulation time | 18239711330 ps |
| CPU time | 294.09 seconds |
| Started | Aug 13 06:54:05 PM PDT 24 |
| Finished | Aug 13 06:59:00 PM PDT 24 |
| Peak memory | 575708 kb |
| Host | smart-a734ea16-a038-44b0-aab4-46a4f64fbab7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3647415560 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.xbar_random_slow_rsp.3647415560 |
| Directory | /workspace/41.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/41.xbar_random_zero_delays.385167211 |
| Short name | T523 |
| Test name | |
| Test status | |
| Simulation time | 544311891 ps |
| CPU time | 44.06 seconds |
| Started | Aug 13 06:53:55 PM PDT 24 |
| Finished | Aug 13 06:54:39 PM PDT 24 |
| Peak memory | 575652 kb |
| Host | smart-8cc0af0a-7e43-41cc-b028-40817bb75430 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=385167211 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.xbar_random_zero_dela ys.385167211 |
| Directory | /workspace/41.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/41.xbar_same_source.2332124500 |
| Short name | T2538 |
| Test name | |
| Test status | |
| Simulation time | 357185529 ps |
| CPU time | 14.01 seconds |
| Started | Aug 13 06:53:54 PM PDT 24 |
| Finished | Aug 13 06:54:09 PM PDT 24 |
| Peak memory | 575496 kb |
| Host | smart-13409886-6cf2-46cc-985e-b291a7a7d6e1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2332124500 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.xbar_same_source.2332124500 |
| Directory | /workspace/41.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/41.xbar_smoke.4198490485 |
| Short name | T1419 |
| Test name | |
| Test status | |
| Simulation time | 189266638 ps |
| CPU time | 8.5 seconds |
| Started | Aug 13 06:53:54 PM PDT 24 |
| Finished | Aug 13 06:54:03 PM PDT 24 |
| Peak memory | 573708 kb |
| Host | smart-fc240467-9444-425c-8d14-dc3fcce9eaa2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4198490485 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.xbar_smoke.4198490485 |
| Directory | /workspace/41.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/41.xbar_smoke_large_delays.3604702717 |
| Short name | T1630 |
| Test name | |
| Test status | |
| Simulation time | 8250223233 ps |
| CPU time | 88.49 seconds |
| Started | Aug 13 06:53:51 PM PDT 24 |
| Finished | Aug 13 06:55:20 PM PDT 24 |
| Peak memory | 573672 kb |
| Host | smart-57fb71a9-bd66-4188-9a99-4ba551673f51 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3604702717 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.xbar_smoke_large_delays.3604702717 |
| Directory | /workspace/41.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/41.xbar_smoke_slow_rsp.2055562880 |
| Short name | T1788 |
| Test name | |
| Test status | |
| Simulation time | 4773628515 ps |
| CPU time | 76.84 seconds |
| Started | Aug 13 06:53:55 PM PDT 24 |
| Finished | Aug 13 06:55:12 PM PDT 24 |
| Peak memory | 573668 kb |
| Host | smart-bfaa8a3a-a1ca-4f7c-b633-22b523402433 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2055562880 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.xbar_smoke_slow_rsp.2055562880 |
| Directory | /workspace/41.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/41.xbar_smoke_zero_delays.4074876914 |
| Short name | T1446 |
| Test name | |
| Test status | |
| Simulation time | 43918662 ps |
| CPU time | 6.27 seconds |
| Started | Aug 13 06:53:55 PM PDT 24 |
| Finished | Aug 13 06:54:01 PM PDT 24 |
| Peak memory | 573504 kb |
| Host | smart-05d96594-7466-4fea-991a-3d47f2de758c |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4074876914 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.xbar_smoke_zero_delay s.4074876914 |
| Directory | /workspace/41.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/41.xbar_stress_all.2494255452 |
| Short name | T2515 |
| Test name | |
| Test status | |
| Simulation time | 1326070329 ps |
| CPU time | 115.35 seconds |
| Started | Aug 13 06:54:05 PM PDT 24 |
| Finished | Aug 13 06:56:01 PM PDT 24 |
| Peak memory | 575620 kb |
| Host | smart-2bbce4ca-40c9-43c1-9064-99476f8f6e3f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2494255452 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.xbar_stress_all.2494255452 |
| Directory | /workspace/41.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/41.xbar_stress_all_with_error.2634078551 |
| Short name | T715 |
| Test name | |
| Test status | |
| Simulation time | 2951169304 ps |
| CPU time | 214.9 seconds |
| Started | Aug 13 06:53:52 PM PDT 24 |
| Finished | Aug 13 06:57:27 PM PDT 24 |
| Peak memory | 576176 kb |
| Host | smart-3dc6829b-ce16-4259-be04-c4dc7df5b0a1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2634078551 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.xbar_stress_all_with_error.2634078551 |
| Directory | /workspace/41.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/41.xbar_stress_all_with_rand_reset.2585600927 |
| Short name | T601 |
| Test name | |
| Test status | |
| Simulation time | 976536263 ps |
| CPU time | 140.85 seconds |
| Started | Aug 13 06:54:05 PM PDT 24 |
| Finished | Aug 13 06:56:26 PM PDT 24 |
| Peak memory | 576432 kb |
| Host | smart-5ca76d48-6774-4f85-909c-b4e500cc0032 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2585600927 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.xbar_stress_all _with_rand_reset.2585600927 |
| Directory | /workspace/41.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/41.xbar_stress_all_with_reset_error.4068830634 |
| Short name | T2839 |
| Test name | |
| Test status | |
| Simulation time | 2497082773 ps |
| CPU time | 161.31 seconds |
| Started | Aug 13 06:54:02 PM PDT 24 |
| Finished | Aug 13 06:56:44 PM PDT 24 |
| Peak memory | 576544 kb |
| Host | smart-53ce2fd6-bc65-4afb-a754-ebb159914bda |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4068830634 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.xbar_stress_al l_with_reset_error.4068830634 |
| Directory | /workspace/41.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/41.xbar_unmapped_addr.3575352150 |
| Short name | T1963 |
| Test name | |
| Test status | |
| Simulation time | 554646423 ps |
| CPU time | 24.51 seconds |
| Started | Aug 13 06:53:55 PM PDT 24 |
| Finished | Aug 13 06:54:20 PM PDT 24 |
| Peak memory | 575536 kb |
| Host | smart-306fc647-17fa-4e48-a631-d468b53f256a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3575352150 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.xbar_unmapped_addr.3575352150 |
| Directory | /workspace/41.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/42.xbar_access_same_device.577472766 |
| Short name | T1559 |
| Test name | |
| Test status | |
| Simulation time | 1097034420 ps |
| CPU time | 85.86 seconds |
| Started | Aug 13 06:54:02 PM PDT 24 |
| Finished | Aug 13 06:55:27 PM PDT 24 |
| Peak memory | 575468 kb |
| Host | smart-040b75c5-8143-4d8a-a217-5319b17ad93b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=577472766 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.xbar_access_same_device. 577472766 |
| Directory | /workspace/42.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/42.xbar_access_same_device_slow_rsp.2759019485 |
| Short name | T2332 |
| Test name | |
| Test status | |
| Simulation time | 111209128652 ps |
| CPU time | 1985.33 seconds |
| Started | Aug 13 06:54:00 PM PDT 24 |
| Finished | Aug 13 07:27:05 PM PDT 24 |
| Peak memory | 575848 kb |
| Host | smart-1474cdfd-e740-4599-b632-11c8e69175e5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2759019485 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.xbar_access_same_ device_slow_rsp.2759019485 |
| Directory | /workspace/42.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/42.xbar_error_and_unmapped_addr.3750783212 |
| Short name | T1689 |
| Test name | |
| Test status | |
| Simulation time | 500707335 ps |
| CPU time | 22.98 seconds |
| Started | Aug 13 06:54:01 PM PDT 24 |
| Finished | Aug 13 06:54:24 PM PDT 24 |
| Peak memory | 575472 kb |
| Host | smart-3d45d973-b304-4dee-a791-ad503c21a4fc |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3750783212 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.xbar_error_and_unmapped_add r.3750783212 |
| Directory | /workspace/42.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/42.xbar_error_random.3486934722 |
| Short name | T2360 |
| Test name | |
| Test status | |
| Simulation time | 1861997759 ps |
| CPU time | 70.53 seconds |
| Started | Aug 13 06:54:05 PM PDT 24 |
| Finished | Aug 13 06:55:15 PM PDT 24 |
| Peak memory | 575692 kb |
| Host | smart-ada02918-52ce-444d-80ac-2c2dda7ff2ef |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3486934722 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.xbar_error_random.3486934722 |
| Directory | /workspace/42.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/42.xbar_random.2109780689 |
| Short name | T527 |
| Test name | |
| Test status | |
| Simulation time | 860365218 ps |
| CPU time | 30.65 seconds |
| Started | Aug 13 06:54:03 PM PDT 24 |
| Finished | Aug 13 06:54:34 PM PDT 24 |
| Peak memory | 575616 kb |
| Host | smart-455d293b-59ee-4f1f-86bf-ce2b795d11f7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2109780689 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.xbar_random.2109780689 |
| Directory | /workspace/42.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/42.xbar_random_large_delays.206028209 |
| Short name | T2635 |
| Test name | |
| Test status | |
| Simulation time | 62470475102 ps |
| CPU time | 681.27 seconds |
| Started | Aug 13 06:54:03 PM PDT 24 |
| Finished | Aug 13 07:05:24 PM PDT 24 |
| Peak memory | 575804 kb |
| Host | smart-e8e0c2f9-8b7f-4624-9b1c-d8e9e36e2b35 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=206028209 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.xbar_random_large_delays.206028209 |
| Directory | /workspace/42.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/42.xbar_random_slow_rsp.2525115148 |
| Short name | T2428 |
| Test name | |
| Test status | |
| Simulation time | 42364258019 ps |
| CPU time | 646.22 seconds |
| Started | Aug 13 06:54:00 PM PDT 24 |
| Finished | Aug 13 07:04:47 PM PDT 24 |
| Peak memory | 575800 kb |
| Host | smart-5faf4c73-4112-408c-acbf-18b0d4f6f1b1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2525115148 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.xbar_random_slow_rsp.2525115148 |
| Directory | /workspace/42.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/42.xbar_random_zero_delays.158888151 |
| Short name | T2885 |
| Test name | |
| Test status | |
| Simulation time | 116885628 ps |
| CPU time | 13.4 seconds |
| Started | Aug 13 06:54:04 PM PDT 24 |
| Finished | Aug 13 06:54:18 PM PDT 24 |
| Peak memory | 575628 kb |
| Host | smart-e5c4a7b9-5e71-4838-b37b-513a01d120e7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=158888151 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.xbar_random_zero_dela ys.158888151 |
| Directory | /workspace/42.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/42.xbar_same_source.231576939 |
| Short name | T648 |
| Test name | |
| Test status | |
| Simulation time | 575731560 ps |
| CPU time | 18.9 seconds |
| Started | Aug 13 06:54:05 PM PDT 24 |
| Finished | Aug 13 06:54:23 PM PDT 24 |
| Peak memory | 575652 kb |
| Host | smart-5279f332-b5a2-4873-9e08-926a818103a5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=231576939 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.xbar_same_source.231576939 |
| Directory | /workspace/42.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/42.xbar_smoke.2611927762 |
| Short name | T1495 |
| Test name | |
| Test status | |
| Simulation time | 207401599 ps |
| CPU time | 8.99 seconds |
| Started | Aug 13 06:54:02 PM PDT 24 |
| Finished | Aug 13 06:54:11 PM PDT 24 |
| Peak memory | 574252 kb |
| Host | smart-78b98637-b952-4cc3-a3b4-dedc18ecd29f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2611927762 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.xbar_smoke.2611927762 |
| Directory | /workspace/42.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/42.xbar_smoke_large_delays.1898123791 |
| Short name | T2861 |
| Test name | |
| Test status | |
| Simulation time | 11240267913 ps |
| CPU time | 117.04 seconds |
| Started | Aug 13 06:54:02 PM PDT 24 |
| Finished | Aug 13 06:55:59 PM PDT 24 |
| Peak memory | 574324 kb |
| Host | smart-8ca98f7d-63ed-4112-a929-b09f87fc1a0a |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1898123791 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.xbar_smoke_large_delays.1898123791 |
| Directory | /workspace/42.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/42.xbar_smoke_slow_rsp.3540114690 |
| Short name | T1484 |
| Test name | |
| Test status | |
| Simulation time | 4878997547 ps |
| CPU time | 81.71 seconds |
| Started | Aug 13 06:54:02 PM PDT 24 |
| Finished | Aug 13 06:55:24 PM PDT 24 |
| Peak memory | 573612 kb |
| Host | smart-dcf81e9a-fabd-4bde-8c41-2bb444d33990 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3540114690 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.xbar_smoke_slow_rsp.3540114690 |
| Directory | /workspace/42.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/42.xbar_smoke_zero_delays.1985279842 |
| Short name | T477 |
| Test name | |
| Test status | |
| Simulation time | 54831977 ps |
| CPU time | 6.25 seconds |
| Started | Aug 13 06:54:02 PM PDT 24 |
| Finished | Aug 13 06:54:09 PM PDT 24 |
| Peak memory | 574252 kb |
| Host | smart-a916669b-de80-4a7e-96fe-1609c511f471 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1985279842 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.xbar_smoke_zero_delay s.1985279842 |
| Directory | /workspace/42.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/42.xbar_stress_all.1657355574 |
| Short name | T2260 |
| Test name | |
| Test status | |
| Simulation time | 4268542867 ps |
| CPU time | 325.22 seconds |
| Started | Aug 13 06:54:02 PM PDT 24 |
| Finished | Aug 13 06:59:27 PM PDT 24 |
| Peak memory | 576584 kb |
| Host | smart-350a203d-eb6d-419c-a6ed-1a9ac141b2bb |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1657355574 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.xbar_stress_all.1657355574 |
| Directory | /workspace/42.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/42.xbar_stress_all_with_rand_reset.1508553163 |
| Short name | T921 |
| Test name | |
| Test status | |
| Simulation time | 12578137557 ps |
| CPU time | 656.05 seconds |
| Started | Aug 13 06:54:01 PM PDT 24 |
| Finished | Aug 13 07:04:57 PM PDT 24 |
| Peak memory | 576520 kb |
| Host | smart-66152b89-9e9b-4e0a-b129-0732a564e185 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1508553163 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.xbar_stress_all _with_rand_reset.1508553163 |
| Directory | /workspace/42.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/42.xbar_stress_all_with_reset_error.492200137 |
| Short name | T919 |
| Test name | |
| Test status | |
| Simulation time | 47017894 ps |
| CPU time | 10.12 seconds |
| Started | Aug 13 06:54:01 PM PDT 24 |
| Finished | Aug 13 06:54:12 PM PDT 24 |
| Peak memory | 575680 kb |
| Host | smart-5108fd7d-ef86-4eda-850d-81772c740574 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=492200137 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.xbar_stress_all _with_reset_error.492200137 |
| Directory | /workspace/42.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/42.xbar_unmapped_addr.3612465092 |
| Short name | T1676 |
| Test name | |
| Test status | |
| Simulation time | 278151039 ps |
| CPU time | 31.71 seconds |
| Started | Aug 13 06:54:02 PM PDT 24 |
| Finished | Aug 13 06:54:34 PM PDT 24 |
| Peak memory | 575592 kb |
| Host | smart-d5957e22-d578-4ae0-b708-0d3b2f6af2d3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3612465092 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.xbar_unmapped_addr.3612465092 |
| Directory | /workspace/42.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/43.xbar_access_same_device.549001780 |
| Short name | T2514 |
| Test name | |
| Test status | |
| Simulation time | 1416887906 ps |
| CPU time | 66.19 seconds |
| Started | Aug 13 06:54:05 PM PDT 24 |
| Finished | Aug 13 06:55:12 PM PDT 24 |
| Peak memory | 575592 kb |
| Host | smart-7b0ee2c7-847d-40a7-a292-e7915f88e595 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=549001780 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.xbar_access_same_device. 549001780 |
| Directory | /workspace/43.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/43.xbar_access_same_device_slow_rsp.1326580371 |
| Short name | T883 |
| Test name | |
| Test status | |
| Simulation time | 22815878884 ps |
| CPU time | 375.95 seconds |
| Started | Aug 13 06:54:06 PM PDT 24 |
| Finished | Aug 13 07:00:22 PM PDT 24 |
| Peak memory | 575600 kb |
| Host | smart-479e6874-dced-4c32-8160-dc05ba091ef2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1326580371 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.xbar_access_same_ device_slow_rsp.1326580371 |
| Directory | /workspace/43.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/43.xbar_error_and_unmapped_addr.1657477932 |
| Short name | T1485 |
| Test name | |
| Test status | |
| Simulation time | 551874477 ps |
| CPU time | 22.94 seconds |
| Started | Aug 13 06:54:07 PM PDT 24 |
| Finished | Aug 13 06:54:30 PM PDT 24 |
| Peak memory | 575664 kb |
| Host | smart-dd8906f0-c40c-4ec3-9b28-fdaa0fe113bb |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1657477932 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.xbar_error_and_unmapped_add r.1657477932 |
| Directory | /workspace/43.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/43.xbar_error_random.964716358 |
| Short name | T1934 |
| Test name | |
| Test status | |
| Simulation time | 1199916365 ps |
| CPU time | 35.2 seconds |
| Started | Aug 13 06:54:07 PM PDT 24 |
| Finished | Aug 13 06:54:43 PM PDT 24 |
| Peak memory | 575600 kb |
| Host | smart-dc218d65-19fa-40da-a7b3-1807e3ee3abf |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=964716358 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.xbar_error_random.964716358 |
| Directory | /workspace/43.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/43.xbar_random.2446077262 |
| Short name | T2604 |
| Test name | |
| Test status | |
| Simulation time | 2537443961 ps |
| CPU time | 94.61 seconds |
| Started | Aug 13 06:54:06 PM PDT 24 |
| Finished | Aug 13 06:55:41 PM PDT 24 |
| Peak memory | 575708 kb |
| Host | smart-4be4e9f3-bd4c-43e2-b4ba-88531b8bb69d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2446077262 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.xbar_random.2446077262 |
| Directory | /workspace/43.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/43.xbar_random_large_delays.1667724715 |
| Short name | T2830 |
| Test name | |
| Test status | |
| Simulation time | 112181535260 ps |
| CPU time | 1253.02 seconds |
| Started | Aug 13 06:54:09 PM PDT 24 |
| Finished | Aug 13 07:15:03 PM PDT 24 |
| Peak memory | 575872 kb |
| Host | smart-5a5d6d7c-4438-4965-949e-46a2fca58cde |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1667724715 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.xbar_random_large_delays.1667724715 |
| Directory | /workspace/43.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/43.xbar_random_slow_rsp.1813997103 |
| Short name | T2680 |
| Test name | |
| Test status | |
| Simulation time | 11424677036 ps |
| CPU time | 203.35 seconds |
| Started | Aug 13 06:54:05 PM PDT 24 |
| Finished | Aug 13 06:57:29 PM PDT 24 |
| Peak memory | 575664 kb |
| Host | smart-2ea10194-dd5d-43e1-a2b6-6a9f25a25220 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1813997103 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.xbar_random_slow_rsp.1813997103 |
| Directory | /workspace/43.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/43.xbar_random_zero_delays.2271548057 |
| Short name | T597 |
| Test name | |
| Test status | |
| Simulation time | 525311886 ps |
| CPU time | 46.36 seconds |
| Started | Aug 13 06:54:23 PM PDT 24 |
| Finished | Aug 13 06:55:09 PM PDT 24 |
| Peak memory | 575508 kb |
| Host | smart-234b5748-71fc-4d62-9c4a-45052544f785 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2271548057 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.xbar_random_zero_del ays.2271548057 |
| Directory | /workspace/43.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/43.xbar_same_source.488357044 |
| Short name | T2227 |
| Test name | |
| Test status | |
| Simulation time | 2237577968 ps |
| CPU time | 70.92 seconds |
| Started | Aug 13 06:54:06 PM PDT 24 |
| Finished | Aug 13 06:55:18 PM PDT 24 |
| Peak memory | 575684 kb |
| Host | smart-da387b9c-4468-4c6f-8763-7be766419825 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=488357044 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.xbar_same_source.488357044 |
| Directory | /workspace/43.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/43.xbar_smoke.1695441896 |
| Short name | T1915 |
| Test name | |
| Test status | |
| Simulation time | 38762090 ps |
| CPU time | 5.62 seconds |
| Started | Aug 13 06:54:02 PM PDT 24 |
| Finished | Aug 13 06:54:08 PM PDT 24 |
| Peak memory | 573512 kb |
| Host | smart-cbd15ab2-69d8-4b43-b05b-969b0b2522e6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1695441896 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.xbar_smoke.1695441896 |
| Directory | /workspace/43.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/43.xbar_smoke_large_delays.1764827008 |
| Short name | T1687 |
| Test name | |
| Test status | |
| Simulation time | 10443695282 ps |
| CPU time | 112.02 seconds |
| Started | Aug 13 06:54:02 PM PDT 24 |
| Finished | Aug 13 06:55:54 PM PDT 24 |
| Peak memory | 573700 kb |
| Host | smart-92d90437-7a8e-43d5-8344-70eb8b2930da |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1764827008 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.xbar_smoke_large_delays.1764827008 |
| Directory | /workspace/43.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/43.xbar_smoke_slow_rsp.158772521 |
| Short name | T2549 |
| Test name | |
| Test status | |
| Simulation time | 7414592395 ps |
| CPU time | 126.57 seconds |
| Started | Aug 13 06:54:01 PM PDT 24 |
| Finished | Aug 13 06:56:08 PM PDT 24 |
| Peak memory | 573592 kb |
| Host | smart-a5590534-98f7-45e0-a900-eaf0b0ddd4df |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=158772521 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.xbar_smoke_slow_rsp.158772521 |
| Directory | /workspace/43.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/43.xbar_smoke_zero_delays.806685325 |
| Short name | T1510 |
| Test name | |
| Test status | |
| Simulation time | 51276165 ps |
| CPU time | 6.9 seconds |
| Started | Aug 13 06:54:02 PM PDT 24 |
| Finished | Aug 13 06:54:09 PM PDT 24 |
| Peak memory | 573576 kb |
| Host | smart-6c4f51a1-e604-411f-a63e-1048ed033cec |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=806685325 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.xbar_smoke_zero_delays .806685325 |
| Directory | /workspace/43.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/43.xbar_stress_all.1480509680 |
| Short name | T2348 |
| Test name | |
| Test status | |
| Simulation time | 15948823324 ps |
| CPU time | 611.38 seconds |
| Started | Aug 13 06:54:09 PM PDT 24 |
| Finished | Aug 13 07:04:21 PM PDT 24 |
| Peak memory | 575896 kb |
| Host | smart-f94fda7e-3bc9-4fa8-b712-baff6df3e791 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1480509680 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.xbar_stress_all.1480509680 |
| Directory | /workspace/43.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/43.xbar_stress_all_with_error.1825639899 |
| Short name | T1972 |
| Test name | |
| Test status | |
| Simulation time | 19523186728 ps |
| CPU time | 637.41 seconds |
| Started | Aug 13 06:54:23 PM PDT 24 |
| Finished | Aug 13 07:05:01 PM PDT 24 |
| Peak memory | 576524 kb |
| Host | smart-22670e71-878f-4b71-806b-5c4943e5501e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1825639899 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.xbar_stress_all_with_error.1825639899 |
| Directory | /workspace/43.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/43.xbar_stress_all_with_rand_reset.268090131 |
| Short name | T2870 |
| Test name | |
| Test status | |
| Simulation time | 903762627 ps |
| CPU time | 173.5 seconds |
| Started | Aug 13 06:54:09 PM PDT 24 |
| Finished | Aug 13 06:57:02 PM PDT 24 |
| Peak memory | 575672 kb |
| Host | smart-efc986a8-1a14-4ad7-97e5-4e64bcf56eed |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=268090131 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_res et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.xbar_stress_all_ with_rand_reset.268090131 |
| Directory | /workspace/43.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/43.xbar_stress_all_with_reset_error.2808730744 |
| Short name | T1740 |
| Test name | |
| Test status | |
| Simulation time | 2466127127 ps |
| CPU time | 313.41 seconds |
| Started | Aug 13 06:54:09 PM PDT 24 |
| Finished | Aug 13 06:59:23 PM PDT 24 |
| Peak memory | 575704 kb |
| Host | smart-75b0c447-4df7-409b-a828-2d23d28f2910 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2808730744 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.xbar_stress_al l_with_reset_error.2808730744 |
| Directory | /workspace/43.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/43.xbar_unmapped_addr.709555903 |
| Short name | T2107 |
| Test name | |
| Test status | |
| Simulation time | 1269552111 ps |
| CPU time | 51.22 seconds |
| Started | Aug 13 06:54:06 PM PDT 24 |
| Finished | Aug 13 06:54:57 PM PDT 24 |
| Peak memory | 575724 kb |
| Host | smart-cc97a383-c174-47a6-819c-f0325012c58b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=709555903 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.xbar_unmapped_addr.709555903 |
| Directory | /workspace/43.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/44.xbar_access_same_device.3185639460 |
| Short name | T2047 |
| Test name | |
| Test status | |
| Simulation time | 65702288 ps |
| CPU time | 7.02 seconds |
| Started | Aug 13 06:54:21 PM PDT 24 |
| Finished | Aug 13 06:54:28 PM PDT 24 |
| Peak memory | 573576 kb |
| Host | smart-28093702-90f3-4c5a-8e17-62db0fe047cb |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3185639460 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.xbar_access_same_device .3185639460 |
| Directory | /workspace/44.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/44.xbar_access_same_device_slow_rsp.1816989299 |
| Short name | T1619 |
| Test name | |
| Test status | |
| Simulation time | 2564660688 ps |
| CPU time | 49.72 seconds |
| Started | Aug 13 06:54:15 PM PDT 24 |
| Finished | Aug 13 06:55:04 PM PDT 24 |
| Peak memory | 574264 kb |
| Host | smart-0bca34e6-244e-469e-873a-8de40e0a40db |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1816989299 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.xbar_access_same_ device_slow_rsp.1816989299 |
| Directory | /workspace/44.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/44.xbar_error_and_unmapped_addr.1261291196 |
| Short name | T1568 |
| Test name | |
| Test status | |
| Simulation time | 1127323928 ps |
| CPU time | 50.61 seconds |
| Started | Aug 13 06:54:14 PM PDT 24 |
| Finished | Aug 13 06:55:04 PM PDT 24 |
| Peak memory | 575668 kb |
| Host | smart-2b329398-eda4-4750-950f-adb75b738f0f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1261291196 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.xbar_error_and_unmapped_add r.1261291196 |
| Directory | /workspace/44.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/44.xbar_error_random.2048460675 |
| Short name | T1776 |
| Test name | |
| Test status | |
| Simulation time | 933832938 ps |
| CPU time | 30.94 seconds |
| Started | Aug 13 06:54:16 PM PDT 24 |
| Finished | Aug 13 06:54:47 PM PDT 24 |
| Peak memory | 575628 kb |
| Host | smart-0e604a4d-0d74-43f6-b1ab-29d36c9be517 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2048460675 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.xbar_error_random.2048460675 |
| Directory | /workspace/44.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/44.xbar_random.3867567265 |
| Short name | T2031 |
| Test name | |
| Test status | |
| Simulation time | 433179508 ps |
| CPU time | 33.28 seconds |
| Started | Aug 13 06:54:07 PM PDT 24 |
| Finished | Aug 13 06:54:40 PM PDT 24 |
| Peak memory | 575504 kb |
| Host | smart-54a345d1-0ed7-4a97-9ef0-b86428d0ddc7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3867567265 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.xbar_random.3867567265 |
| Directory | /workspace/44.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/44.xbar_random_large_delays.3252829102 |
| Short name | T674 |
| Test name | |
| Test status | |
| Simulation time | 52132683029 ps |
| CPU time | 569.55 seconds |
| Started | Aug 13 06:54:16 PM PDT 24 |
| Finished | Aug 13 07:03:46 PM PDT 24 |
| Peak memory | 575808 kb |
| Host | smart-85448e5d-13e7-4d92-849e-4990e011c8c9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3252829102 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.xbar_random_large_delays.3252829102 |
| Directory | /workspace/44.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/44.xbar_random_slow_rsp.2442167640 |
| Short name | T499 |
| Test name | |
| Test status | |
| Simulation time | 38579579401 ps |
| CPU time | 673.22 seconds |
| Started | Aug 13 06:54:13 PM PDT 24 |
| Finished | Aug 13 07:05:27 PM PDT 24 |
| Peak memory | 575692 kb |
| Host | smart-6aae053f-2a8a-4781-9b93-af64ce0030a4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2442167640 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.xbar_random_slow_rsp.2442167640 |
| Directory | /workspace/44.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/44.xbar_random_zero_delays.3641615205 |
| Short name | T1649 |
| Test name | |
| Test status | |
| Simulation time | 350547122 ps |
| CPU time | 32.37 seconds |
| Started | Aug 13 06:54:06 PM PDT 24 |
| Finished | Aug 13 06:54:39 PM PDT 24 |
| Peak memory | 575628 kb |
| Host | smart-2912ec05-0a9b-44c4-928a-d7e8a48d19e7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3641615205 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.xbar_random_zero_del ays.3641615205 |
| Directory | /workspace/44.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/44.xbar_same_source.3122702606 |
| Short name | T2415 |
| Test name | |
| Test status | |
| Simulation time | 233776579 ps |
| CPU time | 17.09 seconds |
| Started | Aug 13 06:54:13 PM PDT 24 |
| Finished | Aug 13 06:54:30 PM PDT 24 |
| Peak memory | 575652 kb |
| Host | smart-e375ddbd-9615-4258-8572-b3176ae7b52b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3122702606 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.xbar_same_source.3122702606 |
| Directory | /workspace/44.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/44.xbar_smoke.3982346166 |
| Short name | T2692 |
| Test name | |
| Test status | |
| Simulation time | 52617083 ps |
| CPU time | 6.86 seconds |
| Started | Aug 13 06:54:07 PM PDT 24 |
| Finished | Aug 13 06:54:14 PM PDT 24 |
| Peak memory | 573552 kb |
| Host | smart-eeda37ed-e4de-496e-8866-3223008508e9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3982346166 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.xbar_smoke.3982346166 |
| Directory | /workspace/44.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/44.xbar_smoke_large_delays.3007312635 |
| Short name | T1929 |
| Test name | |
| Test status | |
| Simulation time | 8955122659 ps |
| CPU time | 96.54 seconds |
| Started | Aug 13 06:54:07 PM PDT 24 |
| Finished | Aug 13 06:55:43 PM PDT 24 |
| Peak memory | 573608 kb |
| Host | smart-5a16d97b-12d5-4dfb-aa98-710306c8ddf3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3007312635 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.xbar_smoke_large_delays.3007312635 |
| Directory | /workspace/44.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/44.xbar_smoke_slow_rsp.1899794798 |
| Short name | T1660 |
| Test name | |
| Test status | |
| Simulation time | 4662889088 ps |
| CPU time | 79.55 seconds |
| Started | Aug 13 06:54:06 PM PDT 24 |
| Finished | Aug 13 06:55:26 PM PDT 24 |
| Peak memory | 573600 kb |
| Host | smart-caaa15ac-3edc-40ab-9e48-f1172982801a |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1899794798 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.xbar_smoke_slow_rsp.1899794798 |
| Directory | /workspace/44.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/44.xbar_smoke_zero_delays.712153081 |
| Short name | T2157 |
| Test name | |
| Test status | |
| Simulation time | 49528576 ps |
| CPU time | 5.91 seconds |
| Started | Aug 13 06:54:22 PM PDT 24 |
| Finished | Aug 13 06:54:28 PM PDT 24 |
| Peak memory | 573584 kb |
| Host | smart-89a37a01-56bf-4d9e-bd8a-cfcd1317f5f5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=712153081 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.xbar_smoke_zero_delays .712153081 |
| Directory | /workspace/44.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/44.xbar_stress_all.3748687508 |
| Short name | T1780 |
| Test name | |
| Test status | |
| Simulation time | 2724855963 ps |
| CPU time | 238.5 seconds |
| Started | Aug 13 06:54:17 PM PDT 24 |
| Finished | Aug 13 06:58:15 PM PDT 24 |
| Peak memory | 575668 kb |
| Host | smart-e7238ca4-01f0-4949-83f9-ba6958fe1d29 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3748687508 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.xbar_stress_all.3748687508 |
| Directory | /workspace/44.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/44.xbar_stress_all_with_error.1883362896 |
| Short name | T1906 |
| Test name | |
| Test status | |
| Simulation time | 294153624 ps |
| CPU time | 14.12 seconds |
| Started | Aug 13 06:54:16 PM PDT 24 |
| Finished | Aug 13 06:54:30 PM PDT 24 |
| Peak memory | 575692 kb |
| Host | smart-8b7ef4bf-1732-49da-b89c-2d43f5ba9f40 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1883362896 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.xbar_stress_all_with_error.1883362896 |
| Directory | /workspace/44.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/44.xbar_stress_all_with_rand_reset.3863885144 |
| Short name | T2292 |
| Test name | |
| Test status | |
| Simulation time | 127394861 ps |
| CPU time | 19.58 seconds |
| Started | Aug 13 06:54:14 PM PDT 24 |
| Finished | Aug 13 06:54:33 PM PDT 24 |
| Peak memory | 575680 kb |
| Host | smart-9b1de274-5d24-43d8-b83e-bfb2fef3032f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3863885144 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.xbar_stress_all _with_rand_reset.3863885144 |
| Directory | /workspace/44.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/44.xbar_stress_all_with_reset_error.3984081709 |
| Short name | T909 |
| Test name | |
| Test status | |
| Simulation time | 173879844 ps |
| CPU time | 48.2 seconds |
| Started | Aug 13 06:54:16 PM PDT 24 |
| Finished | Aug 13 06:55:05 PM PDT 24 |
| Peak memory | 575620 kb |
| Host | smart-84bf018c-bff3-4b7f-b48c-8ce6e9a62008 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3984081709 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.xbar_stress_al l_with_reset_error.3984081709 |
| Directory | /workspace/44.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/44.xbar_unmapped_addr.3466692639 |
| Short name | T1518 |
| Test name | |
| Test status | |
| Simulation time | 238463991 ps |
| CPU time | 13.33 seconds |
| Started | Aug 13 06:54:15 PM PDT 24 |
| Finished | Aug 13 06:54:29 PM PDT 24 |
| Peak memory | 575560 kb |
| Host | smart-7d0d76cd-1766-41bc-ada1-936e9c2b5e1a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3466692639 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.xbar_unmapped_addr.3466692639 |
| Directory | /workspace/44.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/45.xbar_access_same_device.3428653253 |
| Short name | T2942 |
| Test name | |
| Test status | |
| Simulation time | 557650015 ps |
| CPU time | 54.85 seconds |
| Started | Aug 13 06:54:25 PM PDT 24 |
| Finished | Aug 13 06:55:20 PM PDT 24 |
| Peak memory | 575468 kb |
| Host | smart-f9c6fb08-c32c-44f9-bebc-e0a447fa9ee2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3428653253 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.xbar_access_same_device .3428653253 |
| Directory | /workspace/45.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/45.xbar_access_same_device_slow_rsp.765701060 |
| Short name | T2519 |
| Test name | |
| Test status | |
| Simulation time | 154662292230 ps |
| CPU time | 3093.21 seconds |
| Started | Aug 13 06:54:21 PM PDT 24 |
| Finished | Aug 13 07:45:55 PM PDT 24 |
| Peak memory | 575720 kb |
| Host | smart-0894b81b-57ea-4595-966d-625a36731a43 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=765701060 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.xbar_access_same_d evice_slow_rsp.765701060 |
| Directory | /workspace/45.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/45.xbar_error_and_unmapped_addr.1180501090 |
| Short name | T1824 |
| Test name | |
| Test status | |
| Simulation time | 117239180 ps |
| CPU time | 16.21 seconds |
| Started | Aug 13 06:54:24 PM PDT 24 |
| Finished | Aug 13 06:54:40 PM PDT 24 |
| Peak memory | 575732 kb |
| Host | smart-e0922ccd-a927-4106-ad71-4884e6b6855b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1180501090 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.xbar_error_and_unmapped_add r.1180501090 |
| Directory | /workspace/45.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/45.xbar_error_random.2373903527 |
| Short name | T556 |
| Test name | |
| Test status | |
| Simulation time | 513052917 ps |
| CPU time | 39.42 seconds |
| Started | Aug 13 06:54:22 PM PDT 24 |
| Finished | Aug 13 06:55:02 PM PDT 24 |
| Peak memory | 575496 kb |
| Host | smart-1081a7ad-f65b-4cb5-9be6-a6abd44ccbd9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2373903527 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.xbar_error_random.2373903527 |
| Directory | /workspace/45.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/45.xbar_random.320410089 |
| Short name | T2116 |
| Test name | |
| Test status | |
| Simulation time | 641968283 ps |
| CPU time | 57.72 seconds |
| Started | Aug 13 06:54:14 PM PDT 24 |
| Finished | Aug 13 06:55:12 PM PDT 24 |
| Peak memory | 575644 kb |
| Host | smart-73685b81-af06-4be9-8c62-27922860b0f1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=320410089 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.xbar_random.320410089 |
| Directory | /workspace/45.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/45.xbar_random_large_delays.231056837 |
| Short name | T2776 |
| Test name | |
| Test status | |
| Simulation time | 10766614877 ps |
| CPU time | 112.39 seconds |
| Started | Aug 13 06:54:20 PM PDT 24 |
| Finished | Aug 13 06:56:13 PM PDT 24 |
| Peak memory | 575628 kb |
| Host | smart-cbc31943-ef1c-4d7e-99e7-b2895f16a122 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=231056837 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.xbar_random_large_delays.231056837 |
| Directory | /workspace/45.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/45.xbar_random_slow_rsp.3113100920 |
| Short name | T1945 |
| Test name | |
| Test status | |
| Simulation time | 54552306242 ps |
| CPU time | 914.44 seconds |
| Started | Aug 13 06:54:16 PM PDT 24 |
| Finished | Aug 13 07:09:30 PM PDT 24 |
| Peak memory | 575496 kb |
| Host | smart-eb6e8e40-8471-40f6-9c58-bfdfab2bb43c |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3113100920 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.xbar_random_slow_rsp.3113100920 |
| Directory | /workspace/45.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/45.xbar_random_zero_delays.1136993928 |
| Short name | T701 |
| Test name | |
| Test status | |
| Simulation time | 213028718 ps |
| CPU time | 19.55 seconds |
| Started | Aug 13 06:54:12 PM PDT 24 |
| Finished | Aug 13 06:54:32 PM PDT 24 |
| Peak memory | 575476 kb |
| Host | smart-13159153-59be-4796-a9ed-8c5f29d22758 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1136993928 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.xbar_random_zero_del ays.1136993928 |
| Directory | /workspace/45.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/45.xbar_same_source.3735159218 |
| Short name | T2193 |
| Test name | |
| Test status | |
| Simulation time | 507598503 ps |
| CPU time | 38.29 seconds |
| Started | Aug 13 06:54:21 PM PDT 24 |
| Finished | Aug 13 06:54:59 PM PDT 24 |
| Peak memory | 575596 kb |
| Host | smart-5b9ab449-cf57-48e1-8fdc-cf2e42dedea8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3735159218 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.xbar_same_source.3735159218 |
| Directory | /workspace/45.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/45.xbar_smoke.335117636 |
| Short name | T2099 |
| Test name | |
| Test status | |
| Simulation time | 208535493 ps |
| CPU time | 9.77 seconds |
| Started | Aug 13 06:54:16 PM PDT 24 |
| Finished | Aug 13 06:54:26 PM PDT 24 |
| Peak memory | 573612 kb |
| Host | smart-ab5a5794-b2f2-4ab7-bf10-6845d4015288 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=335117636 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.xbar_smoke.335117636 |
| Directory | /workspace/45.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/45.xbar_smoke_large_delays.461563427 |
| Short name | T1744 |
| Test name | |
| Test status | |
| Simulation time | 8938966824 ps |
| CPU time | 97.92 seconds |
| Started | Aug 13 06:54:14 PM PDT 24 |
| Finished | Aug 13 06:55:52 PM PDT 24 |
| Peak memory | 573632 kb |
| Host | smart-def25c29-1972-48d5-abd3-86ae52344550 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=461563427 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.xbar_smoke_large_delays.461563427 |
| Directory | /workspace/45.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/45.xbar_smoke_slow_rsp.4004651189 |
| Short name | T2443 |
| Test name | |
| Test status | |
| Simulation time | 6245140068 ps |
| CPU time | 108.33 seconds |
| Started | Aug 13 06:54:14 PM PDT 24 |
| Finished | Aug 13 06:56:03 PM PDT 24 |
| Peak memory | 573640 kb |
| Host | smart-b77dd89d-213e-4b27-8cbe-323e3b557caa |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4004651189 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.xbar_smoke_slow_rsp.4004651189 |
| Directory | /workspace/45.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/45.xbar_smoke_zero_delays.539624738 |
| Short name | T2108 |
| Test name | |
| Test status | |
| Simulation time | 44130859 ps |
| CPU time | 6.06 seconds |
| Started | Aug 13 06:54:20 PM PDT 24 |
| Finished | Aug 13 06:54:27 PM PDT 24 |
| Peak memory | 573604 kb |
| Host | smart-9e17a3fa-92ba-421d-be9b-085b7a954eda |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=539624738 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.xbar_smoke_zero_delays .539624738 |
| Directory | /workspace/45.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/45.xbar_stress_all.3480370438 |
| Short name | T2807 |
| Test name | |
| Test status | |
| Simulation time | 16945847303 ps |
| CPU time | 563.02 seconds |
| Started | Aug 13 06:54:22 PM PDT 24 |
| Finished | Aug 13 07:03:45 PM PDT 24 |
| Peak memory | 575788 kb |
| Host | smart-59a0f0da-378f-4620-86d3-0ab0fbdd35ee |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3480370438 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.xbar_stress_all.3480370438 |
| Directory | /workspace/45.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/45.xbar_stress_all_with_error.3149928341 |
| Short name | T1428 |
| Test name | |
| Test status | |
| Simulation time | 6016986 ps |
| CPU time | 3.93 seconds |
| Started | Aug 13 06:54:24 PM PDT 24 |
| Finished | Aug 13 06:54:28 PM PDT 24 |
| Peak memory | 565332 kb |
| Host | smart-b251db89-3bc1-4f77-ad6c-45a0370fa5f4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3149928341 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.xbar_stress_all_with_error.3149928341 |
| Directory | /workspace/45.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/45.xbar_stress_all_with_rand_reset.3641911884 |
| Short name | T505 |
| Test name | |
| Test status | |
| Simulation time | 7846047310 ps |
| CPU time | 399.11 seconds |
| Started | Aug 13 06:54:20 PM PDT 24 |
| Finished | Aug 13 07:01:00 PM PDT 24 |
| Peak memory | 576556 kb |
| Host | smart-e3015565-e00b-41dc-aed0-27d1a7261a16 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3641911884 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.xbar_stress_all _with_rand_reset.3641911884 |
| Directory | /workspace/45.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/45.xbar_stress_all_with_reset_error.2073894993 |
| Short name | T1581 |
| Test name | |
| Test status | |
| Simulation time | 308955866 ps |
| CPU time | 88.33 seconds |
| Started | Aug 13 06:54:23 PM PDT 24 |
| Finished | Aug 13 06:55:52 PM PDT 24 |
| Peak memory | 575404 kb |
| Host | smart-03e333ee-1c24-4bfb-a0a1-5607582b302e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2073894993 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.xbar_stress_al l_with_reset_error.2073894993 |
| Directory | /workspace/45.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/45.xbar_unmapped_addr.3706548064 |
| Short name | T1836 |
| Test name | |
| Test status | |
| Simulation time | 1274716453 ps |
| CPU time | 50.91 seconds |
| Started | Aug 13 06:54:31 PM PDT 24 |
| Finished | Aug 13 06:55:22 PM PDT 24 |
| Peak memory | 575576 kb |
| Host | smart-9b471fd2-4d87-4d81-8a41-b595d526088d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3706548064 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.xbar_unmapped_addr.3706548064 |
| Directory | /workspace/45.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/46.xbar_access_same_device.3233827009 |
| Short name | T2064 |
| Test name | |
| Test status | |
| Simulation time | 281671545 ps |
| CPU time | 20.05 seconds |
| Started | Aug 13 06:54:42 PM PDT 24 |
| Finished | Aug 13 06:55:02 PM PDT 24 |
| Peak memory | 575684 kb |
| Host | smart-08cf17e1-6e65-444d-8326-0c742ee520fc |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3233827009 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.xbar_access_same_device .3233827009 |
| Directory | /workspace/46.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/46.xbar_access_same_device_slow_rsp.386197640 |
| Short name | T2426 |
| Test name | |
| Test status | |
| Simulation time | 88817925410 ps |
| CPU time | 1612.17 seconds |
| Started | Aug 13 06:54:41 PM PDT 24 |
| Finished | Aug 13 07:21:33 PM PDT 24 |
| Peak memory | 575816 kb |
| Host | smart-ca364529-c9ac-4286-a49e-d45518cfd0ed |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=386197640 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.xbar_access_same_d evice_slow_rsp.386197640 |
| Directory | /workspace/46.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/46.xbar_error_and_unmapped_addr.310433365 |
| Short name | T2685 |
| Test name | |
| Test status | |
| Simulation time | 285248095 ps |
| CPU time | 25.14 seconds |
| Started | Aug 13 06:54:28 PM PDT 24 |
| Finished | Aug 13 06:54:53 PM PDT 24 |
| Peak memory | 575592 kb |
| Host | smart-a17b4a9c-ab86-45d0-b4de-178738ded0c7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=310433365 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.xbar_error_and_unmapped_addr .310433365 |
| Directory | /workspace/46.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/46.xbar_error_random.2453705697 |
| Short name | T554 |
| Test name | |
| Test status | |
| Simulation time | 2528897586 ps |
| CPU time | 88.87 seconds |
| Started | Aug 13 06:54:29 PM PDT 24 |
| Finished | Aug 13 06:55:58 PM PDT 24 |
| Peak memory | 575808 kb |
| Host | smart-217b169a-56dd-4fa3-ab6d-a5683f37e1b1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2453705697 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.xbar_error_random.2453705697 |
| Directory | /workspace/46.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/46.xbar_random.1044313065 |
| Short name | T504 |
| Test name | |
| Test status | |
| Simulation time | 526881321 ps |
| CPU time | 19.83 seconds |
| Started | Aug 13 06:54:27 PM PDT 24 |
| Finished | Aug 13 06:54:47 PM PDT 24 |
| Peak memory | 575544 kb |
| Host | smart-d1d28a03-b26d-4c3d-85aa-50651b7f7a93 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1044313065 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.xbar_random.1044313065 |
| Directory | /workspace/46.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/46.xbar_random_large_delays.1665606222 |
| Short name | T1786 |
| Test name | |
| Test status | |
| Simulation time | 4824897115 ps |
| CPU time | 53.46 seconds |
| Started | Aug 13 06:54:29 PM PDT 24 |
| Finished | Aug 13 06:55:23 PM PDT 24 |
| Peak memory | 573628 kb |
| Host | smart-22a23454-076f-432e-9f39-2c1161387104 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1665606222 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.xbar_random_large_delays.1665606222 |
| Directory | /workspace/46.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/46.xbar_random_slow_rsp.1323373410 |
| Short name | T526 |
| Test name | |
| Test status | |
| Simulation time | 65060698511 ps |
| CPU time | 1156.57 seconds |
| Started | Aug 13 06:54:31 PM PDT 24 |
| Finished | Aug 13 07:13:48 PM PDT 24 |
| Peak memory | 575620 kb |
| Host | smart-5e1af6f7-8675-4d1f-85c5-0d27f054ebd9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1323373410 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.xbar_random_slow_rsp.1323373410 |
| Directory | /workspace/46.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/46.xbar_random_zero_delays.4158041989 |
| Short name | T2495 |
| Test name | |
| Test status | |
| Simulation time | 37965671 ps |
| CPU time | 6.02 seconds |
| Started | Aug 13 06:54:41 PM PDT 24 |
| Finished | Aug 13 06:54:47 PM PDT 24 |
| Peak memory | 573536 kb |
| Host | smart-348ba3e4-2637-4cd3-8496-699afb5be173 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4158041989 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.xbar_random_zero_del ays.4158041989 |
| Directory | /workspace/46.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/46.xbar_same_source.2177489881 |
| Short name | T712 |
| Test name | |
| Test status | |
| Simulation time | 540685748 ps |
| CPU time | 41.31 seconds |
| Started | Aug 13 06:54:32 PM PDT 24 |
| Finished | Aug 13 06:55:13 PM PDT 24 |
| Peak memory | 575520 kb |
| Host | smart-f135e990-53ce-434e-9e84-abb3b79d576b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2177489881 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.xbar_same_source.2177489881 |
| Directory | /workspace/46.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/46.xbar_smoke.550078880 |
| Short name | T2832 |
| Test name | |
| Test status | |
| Simulation time | 222337440 ps |
| CPU time | 9.9 seconds |
| Started | Aug 13 06:54:21 PM PDT 24 |
| Finished | Aug 13 06:54:31 PM PDT 24 |
| Peak memory | 573536 kb |
| Host | smart-2edc0472-4035-4eee-9a2d-35324ac2f649 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=550078880 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.xbar_smoke.550078880 |
| Directory | /workspace/46.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/46.xbar_smoke_large_delays.3251530764 |
| Short name | T1423 |
| Test name | |
| Test status | |
| Simulation time | 8203319679 ps |
| CPU time | 83.38 seconds |
| Started | Aug 13 06:54:29 PM PDT 24 |
| Finished | Aug 13 06:55:53 PM PDT 24 |
| Peak memory | 574336 kb |
| Host | smart-6c2ff806-23ba-424f-857f-904b7899dc07 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3251530764 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.xbar_smoke_large_delays.3251530764 |
| Directory | /workspace/46.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/46.xbar_smoke_slow_rsp.1439464725 |
| Short name | T622 |
| Test name | |
| Test status | |
| Simulation time | 5480615789 ps |
| CPU time | 97.65 seconds |
| Started | Aug 13 06:54:40 PM PDT 24 |
| Finished | Aug 13 06:56:18 PM PDT 24 |
| Peak memory | 574324 kb |
| Host | smart-273d7363-0b0d-42d9-86ad-ea2150de36a3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1439464725 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.xbar_smoke_slow_rsp.1439464725 |
| Directory | /workspace/46.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/46.xbar_smoke_zero_delays.78826422 |
| Short name | T2513 |
| Test name | |
| Test status | |
| Simulation time | 42352332 ps |
| CPU time | 6.14 seconds |
| Started | Aug 13 06:54:22 PM PDT 24 |
| Finished | Aug 13 06:54:28 PM PDT 24 |
| Peak memory | 573520 kb |
| Host | smart-d8e30f0b-d789-49ed-b227-e4e649885929 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=78826422 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.xbar_smoke_zero_delays.78826422 |
| Directory | /workspace/46.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/46.xbar_stress_all.2612555749 |
| Short name | T697 |
| Test name | |
| Test status | |
| Simulation time | 4045294510 ps |
| CPU time | 157.22 seconds |
| Started | Aug 13 06:54:29 PM PDT 24 |
| Finished | Aug 13 06:57:06 PM PDT 24 |
| Peak memory | 576536 kb |
| Host | smart-cfcac758-c22b-48c1-9b62-e23b8b80c870 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2612555749 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.xbar_stress_all.2612555749 |
| Directory | /workspace/46.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/46.xbar_stress_all_with_error.1423772670 |
| Short name | T2029 |
| Test name | |
| Test status | |
| Simulation time | 1047990134 ps |
| CPU time | 68.42 seconds |
| Started | Aug 13 06:54:33 PM PDT 24 |
| Finished | Aug 13 06:55:42 PM PDT 24 |
| Peak memory | 575536 kb |
| Host | smart-2d0c189e-aaaa-4733-ab94-5527413d159d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1423772670 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.xbar_stress_all_with_error.1423772670 |
| Directory | /workspace/46.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/46.xbar_stress_all_with_rand_reset.253118088 |
| Short name | T922 |
| Test name | |
| Test status | |
| Simulation time | 671182973 ps |
| CPU time | 269.99 seconds |
| Started | Aug 13 06:54:31 PM PDT 24 |
| Finished | Aug 13 06:59:01 PM PDT 24 |
| Peak memory | 576476 kb |
| Host | smart-28ec4437-f32b-474e-bd59-7efee00694b4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=253118088 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_res et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.xbar_stress_all_ with_rand_reset.253118088 |
| Directory | /workspace/46.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/46.xbar_stress_all_with_reset_error.1072467531 |
| Short name | T1547 |
| Test name | |
| Test status | |
| Simulation time | 396817449 ps |
| CPU time | 152.58 seconds |
| Started | Aug 13 06:54:35 PM PDT 24 |
| Finished | Aug 13 06:57:08 PM PDT 24 |
| Peak memory | 576500 kb |
| Host | smart-00589b87-9543-44c7-a402-6cf821e59d30 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1072467531 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.xbar_stress_al l_with_reset_error.1072467531 |
| Directory | /workspace/46.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/46.xbar_unmapped_addr.1546049593 |
| Short name | T683 |
| Test name | |
| Test status | |
| Simulation time | 134785507 ps |
| CPU time | 20.76 seconds |
| Started | Aug 13 06:54:42 PM PDT 24 |
| Finished | Aug 13 06:55:03 PM PDT 24 |
| Peak memory | 575676 kb |
| Host | smart-dc5d2367-bc1e-4b2b-a8fa-ae9e2f9480dd |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1546049593 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.xbar_unmapped_addr.1546049593 |
| Directory | /workspace/46.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/47.xbar_access_same_device.551573790 |
| Short name | T2929 |
| Test name | |
| Test status | |
| Simulation time | 720026990 ps |
| CPU time | 65.7 seconds |
| Started | Aug 13 06:54:35 PM PDT 24 |
| Finished | Aug 13 06:55:41 PM PDT 24 |
| Peak memory | 575740 kb |
| Host | smart-6c36bc9b-2258-461b-8e56-9fa142c6de73 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=551573790 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.xbar_access_same_device. 551573790 |
| Directory | /workspace/47.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/47.xbar_access_same_device_slow_rsp.3374877634 |
| Short name | T878 |
| Test name | |
| Test status | |
| Simulation time | 131166773522 ps |
| CPU time | 2333.12 seconds |
| Started | Aug 13 06:54:34 PM PDT 24 |
| Finished | Aug 13 07:33:28 PM PDT 24 |
| Peak memory | 575772 kb |
| Host | smart-31baa4ec-3b78-47bc-9d46-38122ba7acc6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3374877634 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.xbar_access_same_ device_slow_rsp.3374877634 |
| Directory | /workspace/47.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/47.xbar_error_and_unmapped_addr.2174235422 |
| Short name | T1699 |
| Test name | |
| Test status | |
| Simulation time | 193468483 ps |
| CPU time | 11.33 seconds |
| Started | Aug 13 06:54:40 PM PDT 24 |
| Finished | Aug 13 06:54:51 PM PDT 24 |
| Peak memory | 575724 kb |
| Host | smart-816722a8-a76c-4cc7-bdcb-540cf15e628a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2174235422 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.xbar_error_and_unmapped_add r.2174235422 |
| Directory | /workspace/47.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/47.xbar_error_random.1627642575 |
| Short name | T1889 |
| Test name | |
| Test status | |
| Simulation time | 433764476 ps |
| CPU time | 37.1 seconds |
| Started | Aug 13 06:54:38 PM PDT 24 |
| Finished | Aug 13 06:55:15 PM PDT 24 |
| Peak memory | 575680 kb |
| Host | smart-f1de2868-3373-4f21-81e2-d778a94a05aa |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1627642575 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.xbar_error_random.1627642575 |
| Directory | /workspace/47.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/47.xbar_random.3967701653 |
| Short name | T2858 |
| Test name | |
| Test status | |
| Simulation time | 536017899 ps |
| CPU time | 48.53 seconds |
| Started | Aug 13 06:54:34 PM PDT 24 |
| Finished | Aug 13 06:55:22 PM PDT 24 |
| Peak memory | 575484 kb |
| Host | smart-92b8bc14-ca04-400f-8f44-0a3aeae772e6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3967701653 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.xbar_random.3967701653 |
| Directory | /workspace/47.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/47.xbar_random_large_delays.1001397716 |
| Short name | T2104 |
| Test name | |
| Test status | |
| Simulation time | 48911220791 ps |
| CPU time | 497.24 seconds |
| Started | Aug 13 06:54:38 PM PDT 24 |
| Finished | Aug 13 07:02:55 PM PDT 24 |
| Peak memory | 575724 kb |
| Host | smart-f5080dd9-757f-416e-8015-c495d7e3620e |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1001397716 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.xbar_random_large_delays.1001397716 |
| Directory | /workspace/47.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/47.xbar_random_slow_rsp.939591642 |
| Short name | T2201 |
| Test name | |
| Test status | |
| Simulation time | 30924936999 ps |
| CPU time | 535.94 seconds |
| Started | Aug 13 06:54:33 PM PDT 24 |
| Finished | Aug 13 07:03:29 PM PDT 24 |
| Peak memory | 575596 kb |
| Host | smart-16c7a172-a8fe-4a94-9388-c1d202788a65 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=939591642 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.xbar_random_slow_rsp.939591642 |
| Directory | /workspace/47.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/47.xbar_random_zero_delays.94842554 |
| Short name | T1905 |
| Test name | |
| Test status | |
| Simulation time | 412516402 ps |
| CPU time | 39.41 seconds |
| Started | Aug 13 06:54:35 PM PDT 24 |
| Finished | Aug 13 06:55:14 PM PDT 24 |
| Peak memory | 575640 kb |
| Host | smart-fec887f0-a37f-4f0e-a1e7-fdbf08be63c7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=94842554 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.xbar_random_zero_delay s.94842554 |
| Directory | /workspace/47.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/47.xbar_same_source.1770596663 |
| Short name | T1772 |
| Test name | |
| Test status | |
| Simulation time | 53503679 ps |
| CPU time | 7.49 seconds |
| Started | Aug 13 06:54:35 PM PDT 24 |
| Finished | Aug 13 06:54:43 PM PDT 24 |
| Peak memory | 573620 kb |
| Host | smart-02a9744a-f61a-4526-a61d-776927b36c8e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1770596663 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.xbar_same_source.1770596663 |
| Directory | /workspace/47.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/47.xbar_smoke.3155229182 |
| Short name | T1712 |
| Test name | |
| Test status | |
| Simulation time | 219730989 ps |
| CPU time | 9.58 seconds |
| Started | Aug 13 06:54:36 PM PDT 24 |
| Finished | Aug 13 06:54:46 PM PDT 24 |
| Peak memory | 573516 kb |
| Host | smart-439a1ae5-01ad-4572-9e82-33a29d7a16f3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3155229182 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.xbar_smoke.3155229182 |
| Directory | /workspace/47.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/47.xbar_smoke_large_delays.2877943467 |
| Short name | T2419 |
| Test name | |
| Test status | |
| Simulation time | 10086410909 ps |
| CPU time | 107.46 seconds |
| Started | Aug 13 06:54:35 PM PDT 24 |
| Finished | Aug 13 06:56:23 PM PDT 24 |
| Peak memory | 573700 kb |
| Host | smart-957660b0-0078-4fd0-acec-40095bd23119 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2877943467 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.xbar_smoke_large_delays.2877943467 |
| Directory | /workspace/47.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/47.xbar_smoke_slow_rsp.950823825 |
| Short name | T2716 |
| Test name | |
| Test status | |
| Simulation time | 4488306502 ps |
| CPU time | 77.42 seconds |
| Started | Aug 13 06:54:36 PM PDT 24 |
| Finished | Aug 13 06:55:54 PM PDT 24 |
| Peak memory | 574312 kb |
| Host | smart-a73bd079-05aa-4646-a616-680e4186df7d |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=950823825 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.xbar_smoke_slow_rsp.950823825 |
| Directory | /workspace/47.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/47.xbar_smoke_zero_delays.3345947992 |
| Short name | T2171 |
| Test name | |
| Test status | |
| Simulation time | 41743547 ps |
| CPU time | 6.09 seconds |
| Started | Aug 13 06:54:36 PM PDT 24 |
| Finished | Aug 13 06:54:42 PM PDT 24 |
| Peak memory | 574344 kb |
| Host | smart-e26a0901-db82-40cc-88fb-c25490467e37 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3345947992 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.xbar_smoke_zero_delay s.3345947992 |
| Directory | /workspace/47.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/47.xbar_stress_all.3910703378 |
| Short name | T2614 |
| Test name | |
| Test status | |
| Simulation time | 11315689722 ps |
| CPU time | 452.12 seconds |
| Started | Aug 13 06:54:35 PM PDT 24 |
| Finished | Aug 13 07:02:07 PM PDT 24 |
| Peak memory | 575808 kb |
| Host | smart-10dbd455-4334-48bd-a6e5-8b6a7cca3211 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3910703378 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.xbar_stress_all.3910703378 |
| Directory | /workspace/47.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/47.xbar_stress_all_with_rand_reset.4282548419 |
| Short name | T905 |
| Test name | |
| Test status | |
| Simulation time | 156250681 ps |
| CPU time | 43.83 seconds |
| Started | Aug 13 06:54:35 PM PDT 24 |
| Finished | Aug 13 06:55:19 PM PDT 24 |
| Peak memory | 575556 kb |
| Host | smart-509c28c0-ec8a-4325-a047-3c5252f452ca |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4282548419 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.xbar_stress_all _with_rand_reset.4282548419 |
| Directory | /workspace/47.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/47.xbar_stress_all_with_reset_error.408139253 |
| Short name | T2794 |
| Test name | |
| Test status | |
| Simulation time | 3402899773 ps |
| CPU time | 168.66 seconds |
| Started | Aug 13 06:54:40 PM PDT 24 |
| Finished | Aug 13 06:57:28 PM PDT 24 |
| Peak memory | 576572 kb |
| Host | smart-7215a6a3-9a7d-4f6f-9188-e9b90c15d96e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=408139253 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.xbar_stress_all _with_reset_error.408139253 |
| Directory | /workspace/47.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/47.xbar_unmapped_addr.3671831818 |
| Short name | T1539 |
| Test name | |
| Test status | |
| Simulation time | 273556484 ps |
| CPU time | 32.78 seconds |
| Started | Aug 13 06:54:34 PM PDT 24 |
| Finished | Aug 13 06:55:07 PM PDT 24 |
| Peak memory | 575732 kb |
| Host | smart-9f46f9dc-12c4-4e99-877e-af9c7e805836 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3671831818 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.xbar_unmapped_addr.3671831818 |
| Directory | /workspace/47.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/48.xbar_access_same_device.1016870761 |
| Short name | T2824 |
| Test name | |
| Test status | |
| Simulation time | 852866781 ps |
| CPU time | 32.62 seconds |
| Started | Aug 13 06:54:42 PM PDT 24 |
| Finished | Aug 13 06:55:15 PM PDT 24 |
| Peak memory | 575548 kb |
| Host | smart-94358c40-4189-4a7c-b92a-5122dcaf3118 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1016870761 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.xbar_access_same_device .1016870761 |
| Directory | /workspace/48.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/48.xbar_access_same_device_slow_rsp.2922265643 |
| Short name | T866 |
| Test name | |
| Test status | |
| Simulation time | 28208444371 ps |
| CPU time | 492.17 seconds |
| Started | Aug 13 06:54:47 PM PDT 24 |
| Finished | Aug 13 07:02:59 PM PDT 24 |
| Peak memory | 575616 kb |
| Host | smart-468722df-d81e-424f-9aa5-1a90a9a09a02 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2922265643 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.xbar_access_same_ device_slow_rsp.2922265643 |
| Directory | /workspace/48.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/48.xbar_error_and_unmapped_addr.3533924974 |
| Short name | T1784 |
| Test name | |
| Test status | |
| Simulation time | 542154383 ps |
| CPU time | 23.28 seconds |
| Started | Aug 13 06:54:46 PM PDT 24 |
| Finished | Aug 13 06:55:09 PM PDT 24 |
| Peak memory | 575720 kb |
| Host | smart-82b7e1b7-dfd0-4ba4-823f-c60355411683 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3533924974 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.xbar_error_and_unmapped_add r.3533924974 |
| Directory | /workspace/48.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/48.xbar_error_random.761289759 |
| Short name | T1665 |
| Test name | |
| Test status | |
| Simulation time | 2326142728 ps |
| CPU time | 83.99 seconds |
| Started | Aug 13 06:54:45 PM PDT 24 |
| Finished | Aug 13 06:56:09 PM PDT 24 |
| Peak memory | 575716 kb |
| Host | smart-7dd50708-b6d4-4e45-99c9-1a6955b7190c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=761289759 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.xbar_error_random.761289759 |
| Directory | /workspace/48.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/48.xbar_random.2891374407 |
| Short name | T2726 |
| Test name | |
| Test status | |
| Simulation time | 588131193 ps |
| CPU time | 23.11 seconds |
| Started | Aug 13 06:54:42 PM PDT 24 |
| Finished | Aug 13 06:55:06 PM PDT 24 |
| Peak memory | 575660 kb |
| Host | smart-b77f7fda-992c-4380-a95b-b1addc9cf009 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2891374407 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.xbar_random.2891374407 |
| Directory | /workspace/48.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/48.xbar_random_large_delays.19998094 |
| Short name | T1989 |
| Test name | |
| Test status | |
| Simulation time | 6081468531 ps |
| CPU time | 63.22 seconds |
| Started | Aug 13 06:54:45 PM PDT 24 |
| Finished | Aug 13 06:55:49 PM PDT 24 |
| Peak memory | 574224 kb |
| Host | smart-1de8b472-a4a5-4d59-8217-f7bfc612f61d |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19998094 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.xbar_random_large_delays.19998094 |
| Directory | /workspace/48.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/48.xbar_random_slow_rsp.2049716028 |
| Short name | T2813 |
| Test name | |
| Test status | |
| Simulation time | 13181005548 ps |
| CPU time | 226.15 seconds |
| Started | Aug 13 06:54:45 PM PDT 24 |
| Finished | Aug 13 06:58:31 PM PDT 24 |
| Peak memory | 575712 kb |
| Host | smart-eeeafb09-8cd0-44bf-bc84-4e20160920db |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2049716028 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.xbar_random_slow_rsp.2049716028 |
| Directory | /workspace/48.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/48.xbar_random_zero_delays.3954030811 |
| Short name | T1986 |
| Test name | |
| Test status | |
| Simulation time | 172386226 ps |
| CPU time | 16.46 seconds |
| Started | Aug 13 06:54:46 PM PDT 24 |
| Finished | Aug 13 06:55:03 PM PDT 24 |
| Peak memory | 575600 kb |
| Host | smart-e671f272-bd7f-467b-a734-4d12321f9aa4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3954030811 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.xbar_random_zero_del ays.3954030811 |
| Directory | /workspace/48.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/48.xbar_same_source.3586231557 |
| Short name | T2779 |
| Test name | |
| Test status | |
| Simulation time | 2174899055 ps |
| CPU time | 68.04 seconds |
| Started | Aug 13 06:54:43 PM PDT 24 |
| Finished | Aug 13 06:55:52 PM PDT 24 |
| Peak memory | 575568 kb |
| Host | smart-7a280e67-ba16-4ffa-946a-598679f05c02 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3586231557 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.xbar_same_source.3586231557 |
| Directory | /workspace/48.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/48.xbar_smoke.1587272852 |
| Short name | T714 |
| Test name | |
| Test status | |
| Simulation time | 43480453 ps |
| CPU time | 6.14 seconds |
| Started | Aug 13 06:54:46 PM PDT 24 |
| Finished | Aug 13 06:54:52 PM PDT 24 |
| Peak memory | 573504 kb |
| Host | smart-afe928cd-f281-4b1f-88e9-0ead7f6b2308 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1587272852 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.xbar_smoke.1587272852 |
| Directory | /workspace/48.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/48.xbar_smoke_large_delays.2326315964 |
| Short name | T2757 |
| Test name | |
| Test status | |
| Simulation time | 7977467740 ps |
| CPU time | 76.23 seconds |
| Started | Aug 13 06:54:45 PM PDT 24 |
| Finished | Aug 13 06:56:01 PM PDT 24 |
| Peak memory | 573640 kb |
| Host | smart-3dc52e99-0022-41b1-bcf0-e0f9537702d0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2326315964 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.xbar_smoke_large_delays.2326315964 |
| Directory | /workspace/48.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/48.xbar_smoke_slow_rsp.3378583058 |
| Short name | T1700 |
| Test name | |
| Test status | |
| Simulation time | 4940966744 ps |
| CPU time | 87.47 seconds |
| Started | Aug 13 06:54:43 PM PDT 24 |
| Finished | Aug 13 06:56:10 PM PDT 24 |
| Peak memory | 573684 kb |
| Host | smart-f10b968b-34b0-4f57-878f-7188c1de6eec |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3378583058 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.xbar_smoke_slow_rsp.3378583058 |
| Directory | /workspace/48.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/48.xbar_smoke_zero_delays.789051840 |
| Short name | T627 |
| Test name | |
| Test status | |
| Simulation time | 38225607 ps |
| CPU time | 5.54 seconds |
| Started | Aug 13 06:54:46 PM PDT 24 |
| Finished | Aug 13 06:54:51 PM PDT 24 |
| Peak memory | 573600 kb |
| Host | smart-5880fa74-b4a1-4b6b-b221-199d4394ac0d |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=789051840 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.xbar_smoke_zero_delays .789051840 |
| Directory | /workspace/48.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/48.xbar_stress_all.4039606505 |
| Short name | T474 |
| Test name | |
| Test status | |
| Simulation time | 2092836602 ps |
| CPU time | 189.33 seconds |
| Started | Aug 13 06:54:42 PM PDT 24 |
| Finished | Aug 13 06:57:52 PM PDT 24 |
| Peak memory | 575624 kb |
| Host | smart-40837393-f1de-4289-929b-cdaf17dff3ea |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4039606505 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.xbar_stress_all.4039606505 |
| Directory | /workspace/48.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/48.xbar_stress_all_with_error.3689551250 |
| Short name | T670 |
| Test name | |
| Test status | |
| Simulation time | 10597778674 ps |
| CPU time | 396.68 seconds |
| Started | Aug 13 06:54:43 PM PDT 24 |
| Finished | Aug 13 07:01:20 PM PDT 24 |
| Peak memory | 575796 kb |
| Host | smart-26fa160a-1187-46df-9ad8-0e10f1e9940c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3689551250 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.xbar_stress_all_with_error.3689551250 |
| Directory | /workspace/48.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/48.xbar_stress_all_with_rand_reset.2713439231 |
| Short name | T440 |
| Test name | |
| Test status | |
| Simulation time | 3086252533 ps |
| CPU time | 253.93 seconds |
| Started | Aug 13 06:54:43 PM PDT 24 |
| Finished | Aug 13 06:58:57 PM PDT 24 |
| Peak memory | 576496 kb |
| Host | smart-be65245e-c1fa-4be5-90b5-7c5eff3820df |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2713439231 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.xbar_stress_all _with_rand_reset.2713439231 |
| Directory | /workspace/48.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/48.xbar_stress_all_with_reset_error.3369195818 |
| Short name | T923 |
| Test name | |
| Test status | |
| Simulation time | 3115513119 ps |
| CPU time | 492.89 seconds |
| Started | Aug 13 06:54:44 PM PDT 24 |
| Finished | Aug 13 07:02:57 PM PDT 24 |
| Peak memory | 578044 kb |
| Host | smart-de44321b-793e-4aae-9140-fff5e3cfaa57 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3369195818 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.xbar_stress_al l_with_reset_error.3369195818 |
| Directory | /workspace/48.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/48.xbar_unmapped_addr.1371540408 |
| Short name | T2264 |
| Test name | |
| Test status | |
| Simulation time | 51530764 ps |
| CPU time | 7.95 seconds |
| Started | Aug 13 06:54:45 PM PDT 24 |
| Finished | Aug 13 06:54:53 PM PDT 24 |
| Peak memory | 575736 kb |
| Host | smart-cdb8a6b3-62d6-442c-851d-4bcebe8fa578 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1371540408 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.xbar_unmapped_addr.1371540408 |
| Directory | /workspace/48.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/49.xbar_access_same_device.568200565 |
| Short name | T2133 |
| Test name | |
| Test status | |
| Simulation time | 2389704103 ps |
| CPU time | 100.67 seconds |
| Started | Aug 13 06:54:59 PM PDT 24 |
| Finished | Aug 13 06:56:40 PM PDT 24 |
| Peak memory | 575764 kb |
| Host | smart-027f5ff2-1ac4-4d05-98d9-abfe791938cc |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=568200565 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.xbar_access_same_device. 568200565 |
| Directory | /workspace/49.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/49.xbar_access_same_device_slow_rsp.469849750 |
| Short name | T1940 |
| Test name | |
| Test status | |
| Simulation time | 139307252658 ps |
| CPU time | 2558.03 seconds |
| Started | Aug 13 06:54:50 PM PDT 24 |
| Finished | Aug 13 07:37:29 PM PDT 24 |
| Peak memory | 575716 kb |
| Host | smart-2ccd1bb0-0e59-431f-89f1-688ec708d54a |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=469849750 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.xbar_access_same_d evice_slow_rsp.469849750 |
| Directory | /workspace/49.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/49.xbar_error_and_unmapped_addr.1135900284 |
| Short name | T2537 |
| Test name | |
| Test status | |
| Simulation time | 236614997 ps |
| CPU time | 26.67 seconds |
| Started | Aug 13 06:54:59 PM PDT 24 |
| Finished | Aug 13 06:55:25 PM PDT 24 |
| Peak memory | 575728 kb |
| Host | smart-59c18bec-f282-475f-a1bc-e98acf49501a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1135900284 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.xbar_error_and_unmapped_add r.1135900284 |
| Directory | /workspace/49.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/49.xbar_error_random.116976311 |
| Short name | T2266 |
| Test name | |
| Test status | |
| Simulation time | 261758804 ps |
| CPU time | 12.52 seconds |
| Started | Aug 13 06:54:49 PM PDT 24 |
| Finished | Aug 13 06:55:02 PM PDT 24 |
| Peak memory | 575664 kb |
| Host | smart-b38a5203-456f-44e2-93f2-bf40e0141d58 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=116976311 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.xbar_error_random.116976311 |
| Directory | /workspace/49.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/49.xbar_random.3324109936 |
| Short name | T1422 |
| Test name | |
| Test status | |
| Simulation time | 467515103 ps |
| CPU time | 19.94 seconds |
| Started | Aug 13 06:54:50 PM PDT 24 |
| Finished | Aug 13 06:55:10 PM PDT 24 |
| Peak memory | 575676 kb |
| Host | smart-691e3769-085b-44c1-b027-ee162c76a660 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3324109936 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.xbar_random.3324109936 |
| Directory | /workspace/49.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/49.xbar_random_large_delays.1504783556 |
| Short name | T2267 |
| Test name | |
| Test status | |
| Simulation time | 62343887980 ps |
| CPU time | 713.51 seconds |
| Started | Aug 13 06:54:52 PM PDT 24 |
| Finished | Aug 13 07:06:46 PM PDT 24 |
| Peak memory | 575632 kb |
| Host | smart-132b06c2-6366-4d0c-a732-29e3014ec841 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1504783556 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.xbar_random_large_delays.1504783556 |
| Directory | /workspace/49.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/49.xbar_random_slow_rsp.1902232200 |
| Short name | T488 |
| Test name | |
| Test status | |
| Simulation time | 50296527774 ps |
| CPU time | 925.1 seconds |
| Started | Aug 13 06:54:50 PM PDT 24 |
| Finished | Aug 13 07:10:16 PM PDT 24 |
| Peak memory | 575556 kb |
| Host | smart-b227bfbe-e879-4ccb-83df-d1dc8724f6dd |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1902232200 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.xbar_random_slow_rsp.1902232200 |
| Directory | /workspace/49.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/49.xbar_random_zero_delays.2694900514 |
| Short name | T2379 |
| Test name | |
| Test status | |
| Simulation time | 196687472 ps |
| CPU time | 19.48 seconds |
| Started | Aug 13 06:54:50 PM PDT 24 |
| Finished | Aug 13 06:55:09 PM PDT 24 |
| Peak memory | 575672 kb |
| Host | smart-043dd293-8a6f-475b-972b-798f733c0e9d |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2694900514 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.xbar_random_zero_del ays.2694900514 |
| Directory | /workspace/49.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/49.xbar_same_source.22821589 |
| Short name | T2762 |
| Test name | |
| Test status | |
| Simulation time | 880786228 ps |
| CPU time | 25 seconds |
| Started | Aug 13 06:54:55 PM PDT 24 |
| Finished | Aug 13 06:55:20 PM PDT 24 |
| Peak memory | 575712 kb |
| Host | smart-2f3ce758-68e3-4fcf-94fb-38e5a51f0616 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22821589 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.xbar_same_source.22821589 |
| Directory | /workspace/49.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/49.xbar_smoke.2409594589 |
| Short name | T2218 |
| Test name | |
| Test status | |
| Simulation time | 45809533 ps |
| CPU time | 6.37 seconds |
| Started | Aug 13 06:54:46 PM PDT 24 |
| Finished | Aug 13 06:54:52 PM PDT 24 |
| Peak memory | 573608 kb |
| Host | smart-575a444b-f863-46f5-bef9-c6b8c6a467bd |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2409594589 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.xbar_smoke.2409594589 |
| Directory | /workspace/49.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/49.xbar_smoke_large_delays.1403263081 |
| Short name | T2199 |
| Test name | |
| Test status | |
| Simulation time | 8991614019 ps |
| CPU time | 93.13 seconds |
| Started | Aug 13 06:54:54 PM PDT 24 |
| Finished | Aug 13 06:56:27 PM PDT 24 |
| Peak memory | 573712 kb |
| Host | smart-3c1eaa85-91b4-40a0-a59e-6f081e7fc7e1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1403263081 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.xbar_smoke_large_delays.1403263081 |
| Directory | /workspace/49.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/49.xbar_smoke_slow_rsp.4026132186 |
| Short name | T2582 |
| Test name | |
| Test status | |
| Simulation time | 5933726041 ps |
| CPU time | 106.53 seconds |
| Started | Aug 13 06:54:54 PM PDT 24 |
| Finished | Aug 13 06:56:41 PM PDT 24 |
| Peak memory | 573632 kb |
| Host | smart-afc3463d-8fcf-431c-a0ec-056c589e9142 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4026132186 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.xbar_smoke_slow_rsp.4026132186 |
| Directory | /workspace/49.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/49.xbar_smoke_zero_delays.1246202294 |
| Short name | T2591 |
| Test name | |
| Test status | |
| Simulation time | 43735999 ps |
| CPU time | 5.74 seconds |
| Started | Aug 13 06:54:44 PM PDT 24 |
| Finished | Aug 13 06:54:49 PM PDT 24 |
| Peak memory | 573516 kb |
| Host | smart-b8a37208-7067-4df4-9fd8-960eb84cb350 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1246202294 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.xbar_smoke_zero_delay s.1246202294 |
| Directory | /workspace/49.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/49.xbar_stress_all.1125505374 |
| Short name | T2800 |
| Test name | |
| Test status | |
| Simulation time | 4325697218 ps |
| CPU time | 160.21 seconds |
| Started | Aug 13 06:54:50 PM PDT 24 |
| Finished | Aug 13 06:57:31 PM PDT 24 |
| Peak memory | 575724 kb |
| Host | smart-575debbc-9e65-454f-8d2b-9398ec116618 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1125505374 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.xbar_stress_all.1125505374 |
| Directory | /workspace/49.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/49.xbar_stress_all_with_error.2136436346 |
| Short name | T2654 |
| Test name | |
| Test status | |
| Simulation time | 2663534544 ps |
| CPU time | 198.54 seconds |
| Started | Aug 13 06:54:50 PM PDT 24 |
| Finished | Aug 13 06:58:09 PM PDT 24 |
| Peak memory | 576556 kb |
| Host | smart-2226cce5-efa3-423f-9e2c-6de5e253c4fb |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2136436346 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.xbar_stress_all_with_error.2136436346 |
| Directory | /workspace/49.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/49.xbar_stress_all_with_rand_reset.378989747 |
| Short name | T2434 |
| Test name | |
| Test status | |
| Simulation time | 18830963811 ps |
| CPU time | 783.66 seconds |
| Started | Aug 13 06:54:49 PM PDT 24 |
| Finished | Aug 13 07:07:53 PM PDT 24 |
| Peak memory | 576580 kb |
| Host | smart-d8a6c126-f681-43d2-ae8d-b7363e16b181 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=378989747 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_res et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.xbar_stress_all_ with_rand_reset.378989747 |
| Directory | /workspace/49.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/49.xbar_stress_all_with_reset_error.2737327776 |
| Short name | T930 |
| Test name | |
| Test status | |
| Simulation time | 63706090 ps |
| CPU time | 17.03 seconds |
| Started | Aug 13 06:54:53 PM PDT 24 |
| Finished | Aug 13 06:55:10 PM PDT 24 |
| Peak memory | 575588 kb |
| Host | smart-a5050b9c-baf5-47d3-ab7d-170f8ca235c9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2737327776 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.xbar_stress_al l_with_reset_error.2737327776 |
| Directory | /workspace/49.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/49.xbar_unmapped_addr.4064689960 |
| Short name | T2173 |
| Test name | |
| Test status | |
| Simulation time | 540898396 ps |
| CPU time | 26.55 seconds |
| Started | Aug 13 06:54:51 PM PDT 24 |
| Finished | Aug 13 06:55:18 PM PDT 24 |
| Peak memory | 575544 kb |
| Host | smart-c6fb3867-bb02-46c7-83c8-9c60b152a8ac |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4064689960 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.xbar_unmapped_addr.4064689960 |
| Directory | /workspace/49.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/5.chip_csr_mem_rw_with_rand_reset.796715731 |
| Short name | T730 |
| Test name | |
| Test status | |
| Simulation time | 10327030343 ps |
| CPU time | 869.53 seconds |
| Started | Aug 13 06:51:03 PM PDT 24 |
| Finished | Aug 13 07:05:32 PM PDT 24 |
| Peak memory | 642444 kb |
| Host | smart-82e06b8a-5674-45fb-b6e5-089094fbcea6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=796715731 -assert nopostproc +U VM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top. vdb -cm_log /dev/null -cm_name 5.chip_csr_mem_rw_with_rand_reset.796715731 |
| Directory | /workspace/5.chip_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/5.chip_csr_rw.2301203726 |
| Short name | T1591 |
| Test name | |
| Test status | |
| Simulation time | 3862592166 ps |
| CPU time | 282.82 seconds |
| Started | Aug 13 06:50:44 PM PDT 24 |
| Finished | Aug 13 06:55:27 PM PDT 24 |
| Peak memory | 597020 kb |
| Host | smart-66b2fef3-1c0e-4bd7-9355-571f8ff4144e |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2301203726 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.chip_csr_rw.2301203726 |
| Directory | /workspace/5.chip_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/5.chip_same_csr_outstanding.3597312475 |
| Short name | T416 |
| Test name | |
| Test status | |
| Simulation time | 31652878770 ps |
| CPU time | 4382.09 seconds |
| Started | Aug 13 06:50:55 PM PDT 24 |
| Finished | Aug 13 08:03:58 PM PDT 24 |
| Peak memory | 592936 kb |
| Host | smart-31c0ca7b-d2de-4f36-9323-e5c25a023f68 |
| User | root |
| Command | /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +run_same_csr_outstanding +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3597312475 -assert nopostproc +UVM_TE STNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb - cm_log /dev/null -cm_name 5.chip_same_csr_outstanding.3597312475 |
| Directory | /workspace/5.chip_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/5.xbar_access_same_device.1130022956 |
| Short name | T2771 |
| Test name | |
| Test status | |
| Simulation time | 497628653 ps |
| CPU time | 23.24 seconds |
| Started | Aug 13 06:50:49 PM PDT 24 |
| Finished | Aug 13 06:51:12 PM PDT 24 |
| Peak memory | 575628 kb |
| Host | smart-5ed200a5-9f2e-46a3-97aa-9baeb3d6ce74 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1130022956 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.xbar_access_same_device. 1130022956 |
| Directory | /workspace/5.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/5.xbar_access_same_device_slow_rsp.1532280585 |
| Short name | T2624 |
| Test name | |
| Test status | |
| Simulation time | 97816643080 ps |
| CPU time | 1720.41 seconds |
| Started | Aug 13 06:50:59 PM PDT 24 |
| Finished | Aug 13 07:19:40 PM PDT 24 |
| Peak memory | 575780 kb |
| Host | smart-3682a5ef-bcc7-4198-8ec5-bbe26efa6787 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1532280585 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.xbar_access_same_d evice_slow_rsp.1532280585 |
| Directory | /workspace/5.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/5.xbar_error_and_unmapped_addr.1145885887 |
| Short name | T1626 |
| Test name | |
| Test status | |
| Simulation time | 826203983 ps |
| CPU time | 30.49 seconds |
| Started | Aug 13 06:50:52 PM PDT 24 |
| Finished | Aug 13 06:51:23 PM PDT 24 |
| Peak memory | 575728 kb |
| Host | smart-f0ae88f6-79ab-4c0c-b977-d635ac4f8aa8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1145885887 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.xbar_error_and_unmapped_addr .1145885887 |
| Directory | /workspace/5.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/5.xbar_error_random.1288759314 |
| Short name | T2878 |
| Test name | |
| Test status | |
| Simulation time | 2038050373 ps |
| CPU time | 61.53 seconds |
| Started | Aug 13 06:50:57 PM PDT 24 |
| Finished | Aug 13 06:51:59 PM PDT 24 |
| Peak memory | 575452 kb |
| Host | smart-946be311-687d-428a-8916-61e5b7471db5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1288759314 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.xbar_error_random.1288759314 |
| Directory | /workspace/5.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/5.xbar_random.1894299767 |
| Short name | T1974 |
| Test name | |
| Test status | |
| Simulation time | 398674742 ps |
| CPU time | 29.58 seconds |
| Started | Aug 13 06:50:53 PM PDT 24 |
| Finished | Aug 13 06:51:22 PM PDT 24 |
| Peak memory | 575556 kb |
| Host | smart-3bcb9889-1f85-4b9c-989f-9f38db422c30 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1894299767 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.xbar_random.1894299767 |
| Directory | /workspace/5.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/5.xbar_random_large_delays.1135777502 |
| Short name | T1775 |
| Test name | |
| Test status | |
| Simulation time | 103575430933 ps |
| CPU time | 1096.75 seconds |
| Started | Aug 13 06:50:38 PM PDT 24 |
| Finished | Aug 13 07:08:55 PM PDT 24 |
| Peak memory | 575716 kb |
| Host | smart-35cd6759-0915-49d5-9051-ed9bb385b8ea |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1135777502 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.xbar_random_large_delays.1135777502 |
| Directory | /workspace/5.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/5.xbar_random_slow_rsp.3488947496 |
| Short name | T1932 |
| Test name | |
| Test status | |
| Simulation time | 5544619015 ps |
| CPU time | 93.51 seconds |
| Started | Aug 13 06:50:45 PM PDT 24 |
| Finished | Aug 13 06:52:18 PM PDT 24 |
| Peak memory | 573676 kb |
| Host | smart-9556ae88-c6df-4fc0-a216-1fcd645c76a4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3488947496 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.xbar_random_slow_rsp.3488947496 |
| Directory | /workspace/5.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/5.xbar_random_zero_delays.2410797762 |
| Short name | T2309 |
| Test name | |
| Test status | |
| Simulation time | 33977714 ps |
| CPU time | 5.76 seconds |
| Started | Aug 13 06:50:56 PM PDT 24 |
| Finished | Aug 13 06:51:02 PM PDT 24 |
| Peak memory | 574240 kb |
| Host | smart-e7d9e72b-7829-406b-a141-88054b2bf00a |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2410797762 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.xbar_random_zero_dela ys.2410797762 |
| Directory | /workspace/5.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/5.xbar_same_source.831079354 |
| Short name | T1733 |
| Test name | |
| Test status | |
| Simulation time | 812187009 ps |
| CPU time | 24.68 seconds |
| Started | Aug 13 06:50:45 PM PDT 24 |
| Finished | Aug 13 06:51:10 PM PDT 24 |
| Peak memory | 575652 kb |
| Host | smart-f8161b92-d649-4bea-9a32-7fbf255d2b1f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=831079354 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.xbar_same_source.831079354 |
| Directory | /workspace/5.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/5.xbar_smoke.1922121424 |
| Short name | T2889 |
| Test name | |
| Test status | |
| Simulation time | 202331577 ps |
| CPU time | 9.01 seconds |
| Started | Aug 13 06:51:03 PM PDT 24 |
| Finished | Aug 13 06:51:12 PM PDT 24 |
| Peak memory | 573592 kb |
| Host | smart-a3154006-ec76-4170-b660-dd27b8db65e7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1922121424 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.xbar_smoke.1922121424 |
| Directory | /workspace/5.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/5.xbar_smoke_large_delays.494062977 |
| Short name | T2759 |
| Test name | |
| Test status | |
| Simulation time | 8556032722 ps |
| CPU time | 83.81 seconds |
| Started | Aug 13 06:50:59 PM PDT 24 |
| Finished | Aug 13 06:52:23 PM PDT 24 |
| Peak memory | 573660 kb |
| Host | smart-ba50f1e9-325a-4217-bf0f-84d4f6912e0d |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=494062977 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.xbar_smoke_large_delays.494062977 |
| Directory | /workspace/5.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/5.xbar_smoke_slow_rsp.4279395463 |
| Short name | T1525 |
| Test name | |
| Test status | |
| Simulation time | 5576636518 ps |
| CPU time | 88.8 seconds |
| Started | Aug 13 06:50:46 PM PDT 24 |
| Finished | Aug 13 06:52:15 PM PDT 24 |
| Peak memory | 573700 kb |
| Host | smart-30bc7022-e261-4e79-b9b1-c95edeebe2f6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4279395463 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.xbar_smoke_slow_rsp.4279395463 |
| Directory | /workspace/5.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/5.xbar_smoke_zero_delays.4060323074 |
| Short name | T1430 |
| Test name | |
| Test status | |
| Simulation time | 49307497 ps |
| CPU time | 6.19 seconds |
| Started | Aug 13 06:50:48 PM PDT 24 |
| Finished | Aug 13 06:50:54 PM PDT 24 |
| Peak memory | 573632 kb |
| Host | smart-f468ac0e-48ea-4bfc-8f4d-7777a75004d8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4060323074 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.xbar_smoke_zero_delays .4060323074 |
| Directory | /workspace/5.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/5.xbar_stress_all_with_error.3556449255 |
| Short name | T1666 |
| Test name | |
| Test status | |
| Simulation time | 4901377605 ps |
| CPU time | 386.86 seconds |
| Started | Aug 13 06:50:48 PM PDT 24 |
| Finished | Aug 13 06:57:15 PM PDT 24 |
| Peak memory | 575716 kb |
| Host | smart-3b6c8304-5ad4-4920-87f3-214d697338ab |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3556449255 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.xbar_stress_all_with_error.3556449255 |
| Directory | /workspace/5.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/5.xbar_stress_all_with_rand_reset.3809490806 |
| Short name | T1958 |
| Test name | |
| Test status | |
| Simulation time | 311559222 ps |
| CPU time | 95.04 seconds |
| Started | Aug 13 06:51:00 PM PDT 24 |
| Finished | Aug 13 06:52:35 PM PDT 24 |
| Peak memory | 576420 kb |
| Host | smart-32170a10-4592-457e-ab57-adb2bd553cc8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3809490806 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.xbar_stress_all_ with_rand_reset.3809490806 |
| Directory | /workspace/5.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/5.xbar_stress_all_with_reset_error.118505028 |
| Short name | T2238 |
| Test name | |
| Test status | |
| Simulation time | 6346037997 ps |
| CPU time | 281.79 seconds |
| Started | Aug 13 06:51:03 PM PDT 24 |
| Finished | Aug 13 06:55:45 PM PDT 24 |
| Peak memory | 575712 kb |
| Host | smart-5c7d473e-7efd-458d-bee2-252e89278dcb |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=118505028 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.xbar_stress_all_ with_reset_error.118505028 |
| Directory | /workspace/5.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/5.xbar_unmapped_addr.440503434 |
| Short name | T2087 |
| Test name | |
| Test status | |
| Simulation time | 60881118 ps |
| CPU time | 8.82 seconds |
| Started | Aug 13 06:51:12 PM PDT 24 |
| Finished | Aug 13 06:51:20 PM PDT 24 |
| Peak memory | 575612 kb |
| Host | smart-49f146b0-4266-4a27-9cdb-b43b36b9207f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=440503434 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.xbar_unmapped_addr.440503434 |
| Directory | /workspace/5.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/50.xbar_access_same_device.1859558829 |
| Short name | T2612 |
| Test name | |
| Test status | |
| Simulation time | 501454059 ps |
| CPU time | 41.49 seconds |
| Started | Aug 13 06:54:58 PM PDT 24 |
| Finished | Aug 13 06:55:40 PM PDT 24 |
| Peak memory | 575504 kb |
| Host | smart-3d2b85b3-ef8d-4403-9b12-9fa7f99d1d21 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1859558829 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 50.xbar_access_same_device .1859558829 |
| Directory | /workspace/50.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/50.xbar_access_same_device_slow_rsp.197916110 |
| Short name | T2475 |
| Test name | |
| Test status | |
| Simulation time | 151158422362 ps |
| CPU time | 2791.94 seconds |
| Started | Aug 13 06:54:59 PM PDT 24 |
| Finished | Aug 13 07:41:31 PM PDT 24 |
| Peak memory | 575812 kb |
| Host | smart-22308119-9c2c-4055-8bb8-bca27f3f31c3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=197916110 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 50.xbar_access_same_d evice_slow_rsp.197916110 |
| Directory | /workspace/50.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/50.xbar_error_and_unmapped_addr.70763501 |
| Short name | T2200 |
| Test name | |
| Test status | |
| Simulation time | 354467218 ps |
| CPU time | 17.49 seconds |
| Started | Aug 13 06:55:00 PM PDT 24 |
| Finished | Aug 13 06:55:18 PM PDT 24 |
| Peak memory | 575444 kb |
| Host | smart-cba2fc16-4194-4eca-ba94-a868852f9ac1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=70763501 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 50.xbar_error_and_unmapped_addr.70763501 |
| Directory | /workspace/50.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/50.xbar_error_random.4131504866 |
| Short name | T1615 |
| Test name | |
| Test status | |
| Simulation time | 1029788732 ps |
| CPU time | 37.21 seconds |
| Started | Aug 13 06:54:59 PM PDT 24 |
| Finished | Aug 13 06:55:37 PM PDT 24 |
| Peak memory | 575672 kb |
| Host | smart-09da28ca-5f21-4602-8ae1-3f51f156944b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4131504866 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 50.xbar_error_random.4131504866 |
| Directory | /workspace/50.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/50.xbar_random.2224226276 |
| Short name | T617 |
| Test name | |
| Test status | |
| Simulation time | 1336834988 ps |
| CPU time | 54.14 seconds |
| Started | Aug 13 06:54:51 PM PDT 24 |
| Finished | Aug 13 06:55:45 PM PDT 24 |
| Peak memory | 575500 kb |
| Host | smart-d2c03327-8fc5-4e19-b677-06d22b2c2fcb |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2224226276 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 50.xbar_random.2224226276 |
| Directory | /workspace/50.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/50.xbar_random_large_delays.408161978 |
| Short name | T2899 |
| Test name | |
| Test status | |
| Simulation time | 27808864704 ps |
| CPU time | 283.54 seconds |
| Started | Aug 13 06:55:01 PM PDT 24 |
| Finished | Aug 13 06:59:44 PM PDT 24 |
| Peak memory | 575560 kb |
| Host | smart-0d336917-db53-4ca1-83a1-8ea9e038823d |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=408161978 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 50.xbar_random_large_delays.408161978 |
| Directory | /workspace/50.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/50.xbar_random_slow_rsp.217348236 |
| Short name | T2053 |
| Test name | |
| Test status | |
| Simulation time | 31141735290 ps |
| CPU time | 515.02 seconds |
| Started | Aug 13 06:55:00 PM PDT 24 |
| Finished | Aug 13 07:03:35 PM PDT 24 |
| Peak memory | 575812 kb |
| Host | smart-e7bdd1e7-bd3e-4ac8-85f2-1eee85c6e441 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=217348236 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 50.xbar_random_slow_rsp.217348236 |
| Directory | /workspace/50.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/50.xbar_random_zero_delays.1516549320 |
| Short name | T2755 |
| Test name | |
| Test status | |
| Simulation time | 316104289 ps |
| CPU time | 29.11 seconds |
| Started | Aug 13 06:54:51 PM PDT 24 |
| Finished | Aug 13 06:55:21 PM PDT 24 |
| Peak memory | 575660 kb |
| Host | smart-e3f77056-6060-420b-bcd6-367b52295ba7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1516549320 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 50.xbar_random_zero_del ays.1516549320 |
| Directory | /workspace/50.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/50.xbar_same_source.629297732 |
| Short name | T1852 |
| Test name | |
| Test status | |
| Simulation time | 426465923 ps |
| CPU time | 29.72 seconds |
| Started | Aug 13 06:55:02 PM PDT 24 |
| Finished | Aug 13 06:55:31 PM PDT 24 |
| Peak memory | 575668 kb |
| Host | smart-19779002-7009-44d7-882d-c102985dd068 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=629297732 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 50.xbar_same_source.629297732 |
| Directory | /workspace/50.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/50.xbar_smoke.3183538732 |
| Short name | T1990 |
| Test name | |
| Test status | |
| Simulation time | 53774916 ps |
| CPU time | 6.25 seconds |
| Started | Aug 13 06:54:55 PM PDT 24 |
| Finished | Aug 13 06:55:01 PM PDT 24 |
| Peak memory | 573544 kb |
| Host | smart-90fd35ee-5c72-4982-ba13-80bb653082d4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3183538732 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 50.xbar_smoke.3183538732 |
| Directory | /workspace/50.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/50.xbar_smoke_large_delays.3409043990 |
| Short name | T1470 |
| Test name | |
| Test status | |
| Simulation time | 4691630750 ps |
| CPU time | 49.81 seconds |
| Started | Aug 13 06:54:54 PM PDT 24 |
| Finished | Aug 13 06:55:44 PM PDT 24 |
| Peak memory | 573684 kb |
| Host | smart-e22d2bff-238f-484d-8712-f1d2511cfa5b |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3409043990 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 50.xbar_smoke_large_delays.3409043990 |
| Directory | /workspace/50.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/50.xbar_smoke_slow_rsp.2131966120 |
| Short name | T2932 |
| Test name | |
| Test status | |
| Simulation time | 5557778996 ps |
| CPU time | 91.35 seconds |
| Started | Aug 13 06:54:51 PM PDT 24 |
| Finished | Aug 13 06:56:23 PM PDT 24 |
| Peak memory | 573708 kb |
| Host | smart-30d5cc22-9886-4e91-aa5a-7ab12bd39767 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2131966120 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 50.xbar_smoke_slow_rsp.2131966120 |
| Directory | /workspace/50.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/50.xbar_smoke_zero_delays.1025338766 |
| Short name | T1535 |
| Test name | |
| Test status | |
| Simulation time | 45917079 ps |
| CPU time | 6.75 seconds |
| Started | Aug 13 06:54:59 PM PDT 24 |
| Finished | Aug 13 06:55:06 PM PDT 24 |
| Peak memory | 573592 kb |
| Host | smart-ba8ab031-1500-4071-970b-c85ebd630094 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1025338766 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 50.xbar_smoke_zero_delay s.1025338766 |
| Directory | /workspace/50.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/50.xbar_stress_all.3130033850 |
| Short name | T2641 |
| Test name | |
| Test status | |
| Simulation time | 3848519965 ps |
| CPU time | 310.44 seconds |
| Started | Aug 13 06:55:00 PM PDT 24 |
| Finished | Aug 13 07:00:11 PM PDT 24 |
| Peak memory | 576568 kb |
| Host | smart-0e3e6d7e-e8c7-4197-a662-b6144e06897e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3130033850 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 50.xbar_stress_all.3130033850 |
| Directory | /workspace/50.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/50.xbar_stress_all_with_error.729462081 |
| Short name | T2693 |
| Test name | |
| Test status | |
| Simulation time | 6728927811 ps |
| CPU time | 218.15 seconds |
| Started | Aug 13 06:55:00 PM PDT 24 |
| Finished | Aug 13 06:58:38 PM PDT 24 |
| Peak memory | 576552 kb |
| Host | smart-a1dc80f6-19dd-4978-bdf4-956b930e0515 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=729462081 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 50.xbar_stress_all_with_error.729462081 |
| Directory | /workspace/50.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/50.xbar_stress_all_with_rand_reset.1559569871 |
| Short name | T555 |
| Test name | |
| Test status | |
| Simulation time | 99122400 ps |
| CPU time | 51.38 seconds |
| Started | Aug 13 06:54:57 PM PDT 24 |
| Finished | Aug 13 06:55:48 PM PDT 24 |
| Peak memory | 575640 kb |
| Host | smart-ba2e8e82-74fc-4321-a8fa-77375224d892 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1559569871 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 50.xbar_stress_all _with_rand_reset.1559569871 |
| Directory | /workspace/50.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/50.xbar_stress_all_with_reset_error.3387459491 |
| Short name | T2142 |
| Test name | |
| Test status | |
| Simulation time | 3828115211 ps |
| CPU time | 403.42 seconds |
| Started | Aug 13 06:55:02 PM PDT 24 |
| Finished | Aug 13 07:01:45 PM PDT 24 |
| Peak memory | 575736 kb |
| Host | smart-7d28a4ff-d84b-48dc-a697-22d1c73ad2f9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3387459491 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 50.xbar_stress_al l_with_reset_error.3387459491 |
| Directory | /workspace/50.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/50.xbar_unmapped_addr.758927998 |
| Short name | T1714 |
| Test name | |
| Test status | |
| Simulation time | 113810018 ps |
| CPU time | 16.25 seconds |
| Started | Aug 13 06:55:01 PM PDT 24 |
| Finished | Aug 13 06:55:17 PM PDT 24 |
| Peak memory | 575596 kb |
| Host | smart-c306332c-29e7-4c66-ad53-7105f6dee29a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=758927998 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 50.xbar_unmapped_addr.758927998 |
| Directory | /workspace/50.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/51.xbar_access_same_device.121680651 |
| Short name | T1645 |
| Test name | |
| Test status | |
| Simulation time | 803731523 ps |
| CPU time | 52.19 seconds |
| Started | Aug 13 06:55:06 PM PDT 24 |
| Finished | Aug 13 06:55:59 PM PDT 24 |
| Peak memory | 575540 kb |
| Host | smart-2065904b-256b-47a9-90f0-cc6de7c37781 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=121680651 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 51.xbar_access_same_device. 121680651 |
| Directory | /workspace/51.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/51.xbar_access_same_device_slow_rsp.738334589 |
| Short name | T2770 |
| Test name | |
| Test status | |
| Simulation time | 104758094943 ps |
| CPU time | 1758.51 seconds |
| Started | Aug 13 06:55:04 PM PDT 24 |
| Finished | Aug 13 07:24:23 PM PDT 24 |
| Peak memory | 575648 kb |
| Host | smart-882bc941-21cd-49d5-95ff-ba1b4c5bbf80 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=738334589 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 51.xbar_access_same_d evice_slow_rsp.738334589 |
| Directory | /workspace/51.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/51.xbar_error_and_unmapped_addr.3770829611 |
| Short name | T2058 |
| Test name | |
| Test status | |
| Simulation time | 232713521 ps |
| CPU time | 25.55 seconds |
| Started | Aug 13 06:55:04 PM PDT 24 |
| Finished | Aug 13 06:55:30 PM PDT 24 |
| Peak memory | 575696 kb |
| Host | smart-1ffefc13-d194-44af-be09-6ab7f8c15acc |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3770829611 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 51.xbar_error_and_unmapped_add r.3770829611 |
| Directory | /workspace/51.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/51.xbar_error_random.332147137 |
| Short name | T2507 |
| Test name | |
| Test status | |
| Simulation time | 263190116 ps |
| CPU time | 27.05 seconds |
| Started | Aug 13 06:55:07 PM PDT 24 |
| Finished | Aug 13 06:55:34 PM PDT 24 |
| Peak memory | 575628 kb |
| Host | smart-f8231931-8c49-4db2-bf91-89c7fbb9f103 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=332147137 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 51.xbar_error_random.332147137 |
| Directory | /workspace/51.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/51.xbar_random.3234754875 |
| Short name | T2206 |
| Test name | |
| Test status | |
| Simulation time | 2557711271 ps |
| CPU time | 97.22 seconds |
| Started | Aug 13 06:55:06 PM PDT 24 |
| Finished | Aug 13 06:56:43 PM PDT 24 |
| Peak memory | 575696 kb |
| Host | smart-f6b51196-87ba-40f4-8c98-8af61c993799 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3234754875 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 51.xbar_random.3234754875 |
| Directory | /workspace/51.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/51.xbar_random_large_delays.1553535499 |
| Short name | T1833 |
| Test name | |
| Test status | |
| Simulation time | 71300401970 ps |
| CPU time | 846.37 seconds |
| Started | Aug 13 06:55:04 PM PDT 24 |
| Finished | Aug 13 07:09:11 PM PDT 24 |
| Peak memory | 575820 kb |
| Host | smart-ea506590-2bf5-4d6d-a946-d8fb08dc03ce |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1553535499 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 51.xbar_random_large_delays.1553535499 |
| Directory | /workspace/51.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/51.xbar_random_slow_rsp.2926922547 |
| Short name | T1831 |
| Test name | |
| Test status | |
| Simulation time | 54872839064 ps |
| CPU time | 1025.47 seconds |
| Started | Aug 13 06:55:04 PM PDT 24 |
| Finished | Aug 13 07:12:10 PM PDT 24 |
| Peak memory | 575760 kb |
| Host | smart-4b5b5cb8-3a0c-4185-bba3-52da0ad609ea |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2926922547 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 51.xbar_random_slow_rsp.2926922547 |
| Directory | /workspace/51.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/51.xbar_random_zero_delays.1968353913 |
| Short name | T684 |
| Test name | |
| Test status | |
| Simulation time | 634624523 ps |
| CPU time | 52.72 seconds |
| Started | Aug 13 06:55:08 PM PDT 24 |
| Finished | Aug 13 06:56:00 PM PDT 24 |
| Peak memory | 575676 kb |
| Host | smart-6699961f-72ea-4a8b-80e6-6c7ee0c530df |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1968353913 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 51.xbar_random_zero_del ays.1968353913 |
| Directory | /workspace/51.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/51.xbar_same_source.1507361226 |
| Short name | T2486 |
| Test name | |
| Test status | |
| Simulation time | 2081953667 ps |
| CPU time | 63.93 seconds |
| Started | Aug 13 06:55:07 PM PDT 24 |
| Finished | Aug 13 06:56:11 PM PDT 24 |
| Peak memory | 575608 kb |
| Host | smart-3c14d349-0b82-4627-ad9a-9317d1ba5e44 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1507361226 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 51.xbar_same_source.1507361226 |
| Directory | /workspace/51.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/51.xbar_smoke.4210399242 |
| Short name | T2592 |
| Test name | |
| Test status | |
| Simulation time | 216410205 ps |
| CPU time | 9.91 seconds |
| Started | Aug 13 06:54:57 PM PDT 24 |
| Finished | Aug 13 06:55:07 PM PDT 24 |
| Peak memory | 573612 kb |
| Host | smart-130c431d-0f74-40a3-a112-5073dbf8bbdb |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4210399242 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 51.xbar_smoke.4210399242 |
| Directory | /workspace/51.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/51.xbar_smoke_large_delays.3205851178 |
| Short name | T1583 |
| Test name | |
| Test status | |
| Simulation time | 5571494768 ps |
| CPU time | 56.07 seconds |
| Started | Aug 13 06:54:58 PM PDT 24 |
| Finished | Aug 13 06:55:54 PM PDT 24 |
| Peak memory | 573604 kb |
| Host | smart-74db97f8-eb78-4d74-82ee-d02072aba0a2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3205851178 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 51.xbar_smoke_large_delays.3205851178 |
| Directory | /workspace/51.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/51.xbar_smoke_slow_rsp.1372762250 |
| Short name | T1677 |
| Test name | |
| Test status | |
| Simulation time | 4798602593 ps |
| CPU time | 78.85 seconds |
| Started | Aug 13 06:54:57 PM PDT 24 |
| Finished | Aug 13 06:56:16 PM PDT 24 |
| Peak memory | 573676 kb |
| Host | smart-e7f5a55b-bbe2-418b-803f-6799d5b0bae4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1372762250 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 51.xbar_smoke_slow_rsp.1372762250 |
| Directory | /workspace/51.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/51.xbar_smoke_zero_delays.549644009 |
| Short name | T2091 |
| Test name | |
| Test status | |
| Simulation time | 47892798 ps |
| CPU time | 6.53 seconds |
| Started | Aug 13 06:54:56 PM PDT 24 |
| Finished | Aug 13 06:55:03 PM PDT 24 |
| Peak memory | 573544 kb |
| Host | smart-1cd2f99c-5d94-4ecc-b4a7-49e8d8855112 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=549644009 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 51.xbar_smoke_zero_delays .549644009 |
| Directory | /workspace/51.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/51.xbar_stress_all.163771652 |
| Short name | T1779 |
| Test name | |
| Test status | |
| Simulation time | 4603358085 ps |
| CPU time | 179.22 seconds |
| Started | Aug 13 06:55:07 PM PDT 24 |
| Finished | Aug 13 06:58:06 PM PDT 24 |
| Peak memory | 576364 kb |
| Host | smart-e322d307-7595-4e80-b995-f1614be3429d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=163771652 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 51.xbar_stress_all.163771652 |
| Directory | /workspace/51.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/51.xbar_stress_all_with_error.2856882233 |
| Short name | T886 |
| Test name | |
| Test status | |
| Simulation time | 1228388394 ps |
| CPU time | 78.9 seconds |
| Started | Aug 13 06:55:07 PM PDT 24 |
| Finished | Aug 13 06:56:26 PM PDT 24 |
| Peak memory | 575576 kb |
| Host | smart-cba76835-6834-45df-8e22-8319e7777149 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2856882233 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 51.xbar_stress_all_with_error.2856882233 |
| Directory | /workspace/51.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/51.xbar_stress_all_with_rand_reset.1817391787 |
| Short name | T2660 |
| Test name | |
| Test status | |
| Simulation time | 164438921 ps |
| CPU time | 85.94 seconds |
| Started | Aug 13 06:55:04 PM PDT 24 |
| Finished | Aug 13 06:56:30 PM PDT 24 |
| Peak memory | 575660 kb |
| Host | smart-1936f42e-448a-47bd-9cb7-810f7fe2f9db |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1817391787 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 51.xbar_stress_all _with_rand_reset.1817391787 |
| Directory | /workspace/51.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/51.xbar_stress_all_with_reset_error.151987631 |
| Short name | T912 |
| Test name | |
| Test status | |
| Simulation time | 4469172058 ps |
| CPU time | 272 seconds |
| Started | Aug 13 06:55:04 PM PDT 24 |
| Finished | Aug 13 06:59:36 PM PDT 24 |
| Peak memory | 575740 kb |
| Host | smart-85dd2a54-b40a-4382-9fae-10d86302ba90 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=151987631 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 51.xbar_stress_all _with_reset_error.151987631 |
| Directory | /workspace/51.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/51.xbar_unmapped_addr.2444187591 |
| Short name | T2231 |
| Test name | |
| Test status | |
| Simulation time | 149087726 ps |
| CPU time | 8.78 seconds |
| Started | Aug 13 06:55:07 PM PDT 24 |
| Finished | Aug 13 06:55:16 PM PDT 24 |
| Peak memory | 574272 kb |
| Host | smart-f369e30b-9e82-4c63-abd6-f888b6053294 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2444187591 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 51.xbar_unmapped_addr.2444187591 |
| Directory | /workspace/51.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/52.xbar_access_same_device.521350506 |
| Short name | T618 |
| Test name | |
| Test status | |
| Simulation time | 1142904550 ps |
| CPU time | 87.84 seconds |
| Started | Aug 13 06:55:11 PM PDT 24 |
| Finished | Aug 13 06:56:39 PM PDT 24 |
| Peak memory | 576396 kb |
| Host | smart-2237b0b9-8175-4e75-a1d0-7e324af5b3a7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=521350506 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 52.xbar_access_same_device. 521350506 |
| Directory | /workspace/52.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/52.xbar_access_same_device_slow_rsp.360233072 |
| Short name | T2902 |
| Test name | |
| Test status | |
| Simulation time | 64802325817 ps |
| CPU time | 1178.26 seconds |
| Started | Aug 13 06:55:10 PM PDT 24 |
| Finished | Aug 13 07:14:49 PM PDT 24 |
| Peak memory | 575720 kb |
| Host | smart-c572be50-0151-424f-984b-bdcf8359b840 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=360233072 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 52.xbar_access_same_d evice_slow_rsp.360233072 |
| Directory | /workspace/52.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/52.xbar_error_and_unmapped_addr.3815575117 |
| Short name | T1602 |
| Test name | |
| Test status | |
| Simulation time | 184229744 ps |
| CPU time | 11.13 seconds |
| Started | Aug 13 06:55:15 PM PDT 24 |
| Finished | Aug 13 06:55:26 PM PDT 24 |
| Peak memory | 575636 kb |
| Host | smart-329d4aab-114c-47a8-9c4e-41e70c2a5498 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3815575117 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 52.xbar_error_and_unmapped_add r.3815575117 |
| Directory | /workspace/52.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/52.xbar_error_random.1285576222 |
| Short name | T2240 |
| Test name | |
| Test status | |
| Simulation time | 2206701909 ps |
| CPU time | 79.85 seconds |
| Started | Aug 13 06:55:10 PM PDT 24 |
| Finished | Aug 13 06:56:30 PM PDT 24 |
| Peak memory | 575756 kb |
| Host | smart-1d390121-c8bd-4344-b7c8-a995ec14c843 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1285576222 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 52.xbar_error_random.1285576222 |
| Directory | /workspace/52.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/52.xbar_random.1229909079 |
| Short name | T2780 |
| Test name | |
| Test status | |
| Simulation time | 2212584963 ps |
| CPU time | 74.88 seconds |
| Started | Aug 13 06:55:08 PM PDT 24 |
| Finished | Aug 13 06:56:23 PM PDT 24 |
| Peak memory | 575744 kb |
| Host | smart-d002e8a6-0417-40cf-a5cb-36512418d579 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1229909079 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 52.xbar_random.1229909079 |
| Directory | /workspace/52.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/52.xbar_random_large_delays.2366838118 |
| Short name | T633 |
| Test name | |
| Test status | |
| Simulation time | 68021227266 ps |
| CPU time | 759.81 seconds |
| Started | Aug 13 06:55:13 PM PDT 24 |
| Finished | Aug 13 07:07:53 PM PDT 24 |
| Peak memory | 575768 kb |
| Host | smart-88497627-8c3a-43fe-a791-df641454e977 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2366838118 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 52.xbar_random_large_delays.2366838118 |
| Directory | /workspace/52.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/52.xbar_random_slow_rsp.1286453366 |
| Short name | T1857 |
| Test name | |
| Test status | |
| Simulation time | 24398815290 ps |
| CPU time | 389.07 seconds |
| Started | Aug 13 06:55:10 PM PDT 24 |
| Finished | Aug 13 07:01:39 PM PDT 24 |
| Peak memory | 575704 kb |
| Host | smart-d9bf399c-bbf0-4d0e-9619-1cfc3fa58693 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1286453366 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 52.xbar_random_slow_rsp.1286453366 |
| Directory | /workspace/52.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/52.xbar_random_zero_delays.1647692549 |
| Short name | T1960 |
| Test name | |
| Test status | |
| Simulation time | 468802461 ps |
| CPU time | 40.1 seconds |
| Started | Aug 13 06:55:12 PM PDT 24 |
| Finished | Aug 13 06:55:52 PM PDT 24 |
| Peak memory | 575508 kb |
| Host | smart-782dd87b-f45e-4e8e-8bf8-0b95beb1a612 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1647692549 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 52.xbar_random_zero_del ays.1647692549 |
| Directory | /workspace/52.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/52.xbar_same_source.2285207737 |
| Short name | T2321 |
| Test name | |
| Test status | |
| Simulation time | 881636580 ps |
| CPU time | 29.81 seconds |
| Started | Aug 13 06:55:12 PM PDT 24 |
| Finished | Aug 13 06:55:42 PM PDT 24 |
| Peak memory | 575584 kb |
| Host | smart-a5939e47-bd5b-4d90-9434-660e59640016 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2285207737 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 52.xbar_same_source.2285207737 |
| Directory | /workspace/52.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/52.xbar_smoke.3068652279 |
| Short name | T2510 |
| Test name | |
| Test status | |
| Simulation time | 48377062 ps |
| CPU time | 6.61 seconds |
| Started | Aug 13 06:55:08 PM PDT 24 |
| Finished | Aug 13 06:55:14 PM PDT 24 |
| Peak memory | 573616 kb |
| Host | smart-1a9f5de1-07c1-4fb3-ac05-6e6c1ed12af2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3068652279 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 52.xbar_smoke.3068652279 |
| Directory | /workspace/52.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/52.xbar_smoke_large_delays.3353647212 |
| Short name | T2083 |
| Test name | |
| Test status | |
| Simulation time | 7631248203 ps |
| CPU time | 77.94 seconds |
| Started | Aug 13 06:55:05 PM PDT 24 |
| Finished | Aug 13 06:56:23 PM PDT 24 |
| Peak memory | 574328 kb |
| Host | smart-1cd93057-5a47-49a0-b722-20ade15f5735 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3353647212 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 52.xbar_smoke_large_delays.3353647212 |
| Directory | /workspace/52.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/52.xbar_smoke_slow_rsp.3225482089 |
| Short name | T664 |
| Test name | |
| Test status | |
| Simulation time | 5606608332 ps |
| CPU time | 100.11 seconds |
| Started | Aug 13 06:55:05 PM PDT 24 |
| Finished | Aug 13 06:56:45 PM PDT 24 |
| Peak memory | 573636 kb |
| Host | smart-5cdde58f-ebbb-49d2-b336-544e5f3a25bd |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3225482089 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 52.xbar_smoke_slow_rsp.3225482089 |
| Directory | /workspace/52.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/52.xbar_smoke_zero_delays.2851515746 |
| Short name | T1967 |
| Test name | |
| Test status | |
| Simulation time | 49642928 ps |
| CPU time | 6.67 seconds |
| Started | Aug 13 06:55:05 PM PDT 24 |
| Finished | Aug 13 06:55:12 PM PDT 24 |
| Peak memory | 573604 kb |
| Host | smart-49aa7e55-1e96-48e5-9adf-41ac3bd91e95 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2851515746 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 52.xbar_smoke_zero_delay s.2851515746 |
| Directory | /workspace/52.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/52.xbar_stress_all.1989323276 |
| Short name | T481 |
| Test name | |
| Test status | |
| Simulation time | 2308776792 ps |
| CPU time | 171.53 seconds |
| Started | Aug 13 06:55:11 PM PDT 24 |
| Finished | Aug 13 06:58:03 PM PDT 24 |
| Peak memory | 576504 kb |
| Host | smart-de907b4e-5685-403f-abcc-d944ad4ea45a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1989323276 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 52.xbar_stress_all.1989323276 |
| Directory | /workspace/52.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/52.xbar_stress_all_with_error.4212518090 |
| Short name | T1685 |
| Test name | |
| Test status | |
| Simulation time | 8629664973 ps |
| CPU time | 350.2 seconds |
| Started | Aug 13 06:55:15 PM PDT 24 |
| Finished | Aug 13 07:01:05 PM PDT 24 |
| Peak memory | 575740 kb |
| Host | smart-a8dbbf48-56e0-498e-92be-af5bfcb09209 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4212518090 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 52.xbar_stress_all_with_error.4212518090 |
| Directory | /workspace/52.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/52.xbar_stress_all_with_rand_reset.406897205 |
| Short name | T478 |
| Test name | |
| Test status | |
| Simulation time | 6847391840 ps |
| CPU time | 504.72 seconds |
| Started | Aug 13 06:55:17 PM PDT 24 |
| Finished | Aug 13 07:03:42 PM PDT 24 |
| Peak memory | 576548 kb |
| Host | smart-809c3c50-93a3-40b6-94fb-2ad8ccf3282a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=406897205 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_res et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 52.xbar_stress_all_ with_rand_reset.406897205 |
| Directory | /workspace/52.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/52.xbar_stress_all_with_reset_error.2765165439 |
| Short name | T1785 |
| Test name | |
| Test status | |
| Simulation time | 4486290842 ps |
| CPU time | 344.82 seconds |
| Started | Aug 13 06:55:17 PM PDT 24 |
| Finished | Aug 13 07:01:02 PM PDT 24 |
| Peak memory | 576552 kb |
| Host | smart-db48bbb2-5857-45b6-9756-d953522c067e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2765165439 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 52.xbar_stress_al l_with_reset_error.2765165439 |
| Directory | /workspace/52.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/52.xbar_unmapped_addr.1902963795 |
| Short name | T1999 |
| Test name | |
| Test status | |
| Simulation time | 463582305 ps |
| CPU time | 22.12 seconds |
| Started | Aug 13 06:55:17 PM PDT 24 |
| Finished | Aug 13 06:55:40 PM PDT 24 |
| Peak memory | 575732 kb |
| Host | smart-a87d53c8-2ae6-440e-8ecf-2e596ad8cc18 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1902963795 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 52.xbar_unmapped_addr.1902963795 |
| Directory | /workspace/52.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/53.xbar_access_same_device.1521054630 |
| Short name | T2084 |
| Test name | |
| Test status | |
| Simulation time | 2415840966 ps |
| CPU time | 87.26 seconds |
| Started | Aug 13 06:55:17 PM PDT 24 |
| Finished | Aug 13 06:56:45 PM PDT 24 |
| Peak memory | 575636 kb |
| Host | smart-c1465db7-f4e5-46b1-b77f-eeb3563745fc |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1521054630 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 53.xbar_access_same_device .1521054630 |
| Directory | /workspace/53.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/53.xbar_access_same_device_slow_rsp.499922143 |
| Short name | T881 |
| Test name | |
| Test status | |
| Simulation time | 93521935486 ps |
| CPU time | 1701.08 seconds |
| Started | Aug 13 06:55:18 PM PDT 24 |
| Finished | Aug 13 07:23:40 PM PDT 24 |
| Peak memory | 575712 kb |
| Host | smart-b9dc130d-1380-4b3a-87a9-20492c1de908 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=499922143 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 53.xbar_access_same_d evice_slow_rsp.499922143 |
| Directory | /workspace/53.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/53.xbar_error_and_unmapped_addr.2202563674 |
| Short name | T1472 |
| Test name | |
| Test status | |
| Simulation time | 85402037 ps |
| CPU time | 11.4 seconds |
| Started | Aug 13 06:55:20 PM PDT 24 |
| Finished | Aug 13 06:55:32 PM PDT 24 |
| Peak memory | 575760 kb |
| Host | smart-50773c4d-1c07-4b8d-932b-90fd2746da8f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2202563674 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 53.xbar_error_and_unmapped_add r.2202563674 |
| Directory | /workspace/53.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/53.xbar_error_random.3078419860 |
| Short name | T1812 |
| Test name | |
| Test status | |
| Simulation time | 2045218821 ps |
| CPU time | 66.41 seconds |
| Started | Aug 13 06:55:18 PM PDT 24 |
| Finished | Aug 13 06:56:25 PM PDT 24 |
| Peak memory | 575720 kb |
| Host | smart-ed08f4ec-8f90-4c71-a0b3-93b1712e483c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3078419860 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 53.xbar_error_random.3078419860 |
| Directory | /workspace/53.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/53.xbar_random.908540252 |
| Short name | T2867 |
| Test name | |
| Test status | |
| Simulation time | 55929197 ps |
| CPU time | 8.56 seconds |
| Started | Aug 13 06:55:19 PM PDT 24 |
| Finished | Aug 13 06:55:28 PM PDT 24 |
| Peak memory | 575492 kb |
| Host | smart-fc67eda7-9176-4814-bfd6-54a02ef26aad |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=908540252 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 53.xbar_random.908540252 |
| Directory | /workspace/53.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/53.xbar_random_large_delays.793071966 |
| Short name | T1789 |
| Test name | |
| Test status | |
| Simulation time | 69159070153 ps |
| CPU time | 742.26 seconds |
| Started | Aug 13 06:55:18 PM PDT 24 |
| Finished | Aug 13 07:07:40 PM PDT 24 |
| Peak memory | 575816 kb |
| Host | smart-8f707013-2bfd-4b8a-9d7c-40725a11012e |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=793071966 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 53.xbar_random_large_delays.793071966 |
| Directory | /workspace/53.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/53.xbar_random_slow_rsp.3622392678 |
| Short name | T2072 |
| Test name | |
| Test status | |
| Simulation time | 65746330196 ps |
| CPU time | 1139.62 seconds |
| Started | Aug 13 06:55:18 PM PDT 24 |
| Finished | Aug 13 07:14:18 PM PDT 24 |
| Peak memory | 575724 kb |
| Host | smart-87dc25b2-ef36-4272-8d5c-648ffd83ba96 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3622392678 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 53.xbar_random_slow_rsp.3622392678 |
| Directory | /workspace/53.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/53.xbar_random_zero_delays.2308259306 |
| Short name | T1875 |
| Test name | |
| Test status | |
| Simulation time | 329815670 ps |
| CPU time | 26.78 seconds |
| Started | Aug 13 06:55:18 PM PDT 24 |
| Finished | Aug 13 06:55:45 PM PDT 24 |
| Peak memory | 575648 kb |
| Host | smart-6c509b48-ad1f-4183-9d46-33557bae9348 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2308259306 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 53.xbar_random_zero_del ays.2308259306 |
| Directory | /workspace/53.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/53.xbar_same_source.1735862235 |
| Short name | T706 |
| Test name | |
| Test status | |
| Simulation time | 2078744262 ps |
| CPU time | 61.02 seconds |
| Started | Aug 13 06:55:20 PM PDT 24 |
| Finished | Aug 13 06:56:21 PM PDT 24 |
| Peak memory | 576384 kb |
| Host | smart-3f4683bc-58cf-4da5-834f-bebf6bf1bc16 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1735862235 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 53.xbar_same_source.1735862235 |
| Directory | /workspace/53.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/53.xbar_smoke.1581320425 |
| Short name | T1421 |
| Test name | |
| Test status | |
| Simulation time | 159361324 ps |
| CPU time | 8.64 seconds |
| Started | Aug 13 06:55:16 PM PDT 24 |
| Finished | Aug 13 06:55:25 PM PDT 24 |
| Peak memory | 573612 kb |
| Host | smart-d8ba999c-2fcc-4fd6-9256-f968cfecea32 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1581320425 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 53.xbar_smoke.1581320425 |
| Directory | /workspace/53.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/53.xbar_smoke_large_delays.3485924692 |
| Short name | T2286 |
| Test name | |
| Test status | |
| Simulation time | 8489725211 ps |
| CPU time | 90.68 seconds |
| Started | Aug 13 06:55:20 PM PDT 24 |
| Finished | Aug 13 06:56:51 PM PDT 24 |
| Peak memory | 574432 kb |
| Host | smart-c9700621-e401-4c09-b950-f088dfddadb5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3485924692 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 53.xbar_smoke_large_delays.3485924692 |
| Directory | /workspace/53.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/53.xbar_smoke_slow_rsp.826236928 |
| Short name | T2164 |
| Test name | |
| Test status | |
| Simulation time | 3254907062 ps |
| CPU time | 55.88 seconds |
| Started | Aug 13 06:55:18 PM PDT 24 |
| Finished | Aug 13 06:56:14 PM PDT 24 |
| Peak memory | 573676 kb |
| Host | smart-ca5cccad-d675-435c-b79d-f6cb362e5abe |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=826236928 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 53.xbar_smoke_slow_rsp.826236928 |
| Directory | /workspace/53.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/53.xbar_smoke_zero_delays.877290584 |
| Short name | T2399 |
| Test name | |
| Test status | |
| Simulation time | 48385354 ps |
| CPU time | 6.95 seconds |
| Started | Aug 13 06:55:16 PM PDT 24 |
| Finished | Aug 13 06:55:23 PM PDT 24 |
| Peak memory | 573520 kb |
| Host | smart-2a21da35-042b-44e2-9f6a-dcddcff023d6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=877290584 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 53.xbar_smoke_zero_delays .877290584 |
| Directory | /workspace/53.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/53.xbar_stress_all.2577423968 |
| Short name | T2445 |
| Test name | |
| Test status | |
| Simulation time | 4861398462 ps |
| CPU time | 186.05 seconds |
| Started | Aug 13 06:55:19 PM PDT 24 |
| Finished | Aug 13 06:58:25 PM PDT 24 |
| Peak memory | 575732 kb |
| Host | smart-b9f83d5b-08e0-4759-ae90-e0155d7e162c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2577423968 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 53.xbar_stress_all.2577423968 |
| Directory | /workspace/53.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/53.xbar_stress_all_with_error.1208997955 |
| Short name | T1856 |
| Test name | |
| Test status | |
| Simulation time | 2904895577 ps |
| CPU time | 106.49 seconds |
| Started | Aug 13 06:55:19 PM PDT 24 |
| Finished | Aug 13 06:57:05 PM PDT 24 |
| Peak memory | 575812 kb |
| Host | smart-44c709c3-5de4-4ab9-ac15-6696b98a4e3f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1208997955 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 53.xbar_stress_all_with_error.1208997955 |
| Directory | /workspace/53.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/53.xbar_stress_all_with_rand_reset.2145464515 |
| Short name | T2453 |
| Test name | |
| Test status | |
| Simulation time | 4088204936 ps |
| CPU time | 551.24 seconds |
| Started | Aug 13 06:55:17 PM PDT 24 |
| Finished | Aug 13 07:04:28 PM PDT 24 |
| Peak memory | 575740 kb |
| Host | smart-af72f001-42a3-447e-9a4c-895717c02d4b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2145464515 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 53.xbar_stress_all _with_rand_reset.2145464515 |
| Directory | /workspace/53.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/53.xbar_stress_all_with_reset_error.2806234989 |
| Short name | T1806 |
| Test name | |
| Test status | |
| Simulation time | 1891188556 ps |
| CPU time | 283.33 seconds |
| Started | Aug 13 06:55:26 PM PDT 24 |
| Finished | Aug 13 07:00:10 PM PDT 24 |
| Peak memory | 576480 kb |
| Host | smart-c830fe69-c369-4b42-b35d-802eb2adeca6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2806234989 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 53.xbar_stress_al l_with_reset_error.2806234989 |
| Directory | /workspace/53.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/53.xbar_unmapped_addr.3431962319 |
| Short name | T691 |
| Test name | |
| Test status | |
| Simulation time | 175873112 ps |
| CPU time | 22.5 seconds |
| Started | Aug 13 06:55:17 PM PDT 24 |
| Finished | Aug 13 06:55:40 PM PDT 24 |
| Peak memory | 575700 kb |
| Host | smart-f2678d58-4bd3-49a6-9743-f0921ffa4383 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3431962319 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 53.xbar_unmapped_addr.3431962319 |
| Directory | /workspace/53.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/54.xbar_access_same_device.2020656953 |
| Short name | T2323 |
| Test name | |
| Test status | |
| Simulation time | 843956057 ps |
| CPU time | 37.78 seconds |
| Started | Aug 13 06:55:24 PM PDT 24 |
| Finished | Aug 13 06:56:02 PM PDT 24 |
| Peak memory | 575508 kb |
| Host | smart-773bb3bc-8922-4fb5-8637-b567d0918388 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2020656953 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 54.xbar_access_same_device .2020656953 |
| Directory | /workspace/54.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/54.xbar_access_same_device_slow_rsp.3766371923 |
| Short name | T2253 |
| Test name | |
| Test status | |
| Simulation time | 5180579145 ps |
| CPU time | 91.47 seconds |
| Started | Aug 13 06:55:27 PM PDT 24 |
| Finished | Aug 13 06:56:59 PM PDT 24 |
| Peak memory | 575716 kb |
| Host | smart-6e74cb07-4457-4f5c-9223-4711d1099291 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3766371923 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 54.xbar_access_same_ device_slow_rsp.3766371923 |
| Directory | /workspace/54.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/54.xbar_error_and_unmapped_addr.1892517152 |
| Short name | T1805 |
| Test name | |
| Test status | |
| Simulation time | 254184936 ps |
| CPU time | 25.16 seconds |
| Started | Aug 13 06:55:28 PM PDT 24 |
| Finished | Aug 13 06:55:53 PM PDT 24 |
| Peak memory | 575448 kb |
| Host | smart-d80e0391-3052-446e-8aed-f83ae7e0f5cd |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1892517152 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 54.xbar_error_and_unmapped_add r.1892517152 |
| Directory | /workspace/54.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/54.xbar_error_random.3809757007 |
| Short name | T2493 |
| Test name | |
| Test status | |
| Simulation time | 187134120 ps |
| CPU time | 17.48 seconds |
| Started | Aug 13 06:55:25 PM PDT 24 |
| Finished | Aug 13 06:55:42 PM PDT 24 |
| Peak memory | 575680 kb |
| Host | smart-913484de-8351-48cb-9d57-24ce4e4376d6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3809757007 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 54.xbar_error_random.3809757007 |
| Directory | /workspace/54.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/54.xbar_random.3146109463 |
| Short name | T2424 |
| Test name | |
| Test status | |
| Simulation time | 130744763 ps |
| CPU time | 15.02 seconds |
| Started | Aug 13 06:55:24 PM PDT 24 |
| Finished | Aug 13 06:55:39 PM PDT 24 |
| Peak memory | 575676 kb |
| Host | smart-0142e4df-fe76-476c-b44d-c73fb33f0316 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3146109463 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 54.xbar_random.3146109463 |
| Directory | /workspace/54.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/54.xbar_random_large_delays.1055800015 |
| Short name | T2758 |
| Test name | |
| Test status | |
| Simulation time | 40301721155 ps |
| CPU time | 397.68 seconds |
| Started | Aug 13 06:55:25 PM PDT 24 |
| Finished | Aug 13 07:02:03 PM PDT 24 |
| Peak memory | 575840 kb |
| Host | smart-5df369c8-f1ad-402c-8a70-326038c18047 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1055800015 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 54.xbar_random_large_delays.1055800015 |
| Directory | /workspace/54.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/54.xbar_random_slow_rsp.834398837 |
| Short name | T1496 |
| Test name | |
| Test status | |
| Simulation time | 59405796911 ps |
| CPU time | 1107.99 seconds |
| Started | Aug 13 06:55:25 PM PDT 24 |
| Finished | Aug 13 07:13:53 PM PDT 24 |
| Peak memory | 575744 kb |
| Host | smart-73329986-85d1-477c-b1c5-163d3ee67bb7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=834398837 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 54.xbar_random_slow_rsp.834398837 |
| Directory | /workspace/54.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/54.xbar_random_zero_delays.664233135 |
| Short name | T2697 |
| Test name | |
| Test status | |
| Simulation time | 175673921 ps |
| CPU time | 19.46 seconds |
| Started | Aug 13 06:55:26 PM PDT 24 |
| Finished | Aug 13 06:55:45 PM PDT 24 |
| Peak memory | 575660 kb |
| Host | smart-2b48f716-8fed-479f-9b6c-26cf4a81b9d1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=664233135 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 54.xbar_random_zero_dela ys.664233135 |
| Directory | /workspace/54.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/54.xbar_same_source.1669712584 |
| Short name | T1704 |
| Test name | |
| Test status | |
| Simulation time | 138813451 ps |
| CPU time | 12.23 seconds |
| Started | Aug 13 06:55:25 PM PDT 24 |
| Finished | Aug 13 06:55:37 PM PDT 24 |
| Peak memory | 575576 kb |
| Host | smart-ebeba1e9-492d-4ff7-bef3-f83bed0e4f12 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1669712584 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 54.xbar_same_source.1669712584 |
| Directory | /workspace/54.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/54.xbar_smoke.1802136486 |
| Short name | T1452 |
| Test name | |
| Test status | |
| Simulation time | 150985613 ps |
| CPU time | 7.43 seconds |
| Started | Aug 13 06:55:26 PM PDT 24 |
| Finished | Aug 13 06:55:33 PM PDT 24 |
| Peak memory | 573544 kb |
| Host | smart-8debc7e1-0f3d-4cca-9805-ed7ce0f2c5f3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1802136486 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 54.xbar_smoke.1802136486 |
| Directory | /workspace/54.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/54.xbar_smoke_large_delays.817869190 |
| Short name | T1488 |
| Test name | |
| Test status | |
| Simulation time | 5241211600 ps |
| CPU time | 55.59 seconds |
| Started | Aug 13 06:55:26 PM PDT 24 |
| Finished | Aug 13 06:56:22 PM PDT 24 |
| Peak memory | 573628 kb |
| Host | smart-a3cd7da6-0e35-4f94-8ae8-88e43c3c0343 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=817869190 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 54.xbar_smoke_large_delays.817869190 |
| Directory | /workspace/54.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/54.xbar_smoke_slow_rsp.2821765863 |
| Short name | T1937 |
| Test name | |
| Test status | |
| Simulation time | 4426042355 ps |
| CPU time | 76.05 seconds |
| Started | Aug 13 06:55:24 PM PDT 24 |
| Finished | Aug 13 06:56:40 PM PDT 24 |
| Peak memory | 573512 kb |
| Host | smart-5994fc86-c01d-44c2-baa6-be051fd2838d |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2821765863 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 54.xbar_smoke_slow_rsp.2821765863 |
| Directory | /workspace/54.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/54.xbar_smoke_zero_delays.307217784 |
| Short name | T2079 |
| Test name | |
| Test status | |
| Simulation time | 46651628 ps |
| CPU time | 6.62 seconds |
| Started | Aug 13 06:55:25 PM PDT 24 |
| Finished | Aug 13 06:55:31 PM PDT 24 |
| Peak memory | 573588 kb |
| Host | smart-5e14f6ec-4f92-45d4-bfc9-2b47cd108259 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=307217784 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 54.xbar_smoke_zero_delays .307217784 |
| Directory | /workspace/54.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/54.xbar_stress_all_with_error.353497133 |
| Short name | T1555 |
| Test name | |
| Test status | |
| Simulation time | 151166395 ps |
| CPU time | 7.8 seconds |
| Started | Aug 13 06:55:36 PM PDT 24 |
| Finished | Aug 13 06:55:44 PM PDT 24 |
| Peak memory | 573660 kb |
| Host | smart-d61d40db-831e-4878-b247-349d8b6dd279 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=353497133 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 54.xbar_stress_all_with_error.353497133 |
| Directory | /workspace/54.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/54.xbar_stress_all_with_rand_reset.2776985298 |
| Short name | T2819 |
| Test name | |
| Test status | |
| Simulation time | 2034654475 ps |
| CPU time | 447.51 seconds |
| Started | Aug 13 06:55:25 PM PDT 24 |
| Finished | Aug 13 07:02:53 PM PDT 24 |
| Peak memory | 576512 kb |
| Host | smart-fecde29d-5010-4192-9dbe-c0e4c4cfe088 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2776985298 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 54.xbar_stress_all _with_rand_reset.2776985298 |
| Directory | /workspace/54.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/54.xbar_stress_all_with_reset_error.1805411769 |
| Short name | T933 |
| Test name | |
| Test status | |
| Simulation time | 4532220239 ps |
| CPU time | 481.02 seconds |
| Started | Aug 13 06:55:37 PM PDT 24 |
| Finished | Aug 13 07:03:38 PM PDT 24 |
| Peak memory | 576576 kb |
| Host | smart-b49f06ea-de6f-4acf-8fd0-757042d2458f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1805411769 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 54.xbar_stress_al l_with_reset_error.1805411769 |
| Directory | /workspace/54.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/54.xbar_unmapped_addr.3028139438 |
| Short name | T2315 |
| Test name | |
| Test status | |
| Simulation time | 1094737205 ps |
| CPU time | 40.42 seconds |
| Started | Aug 13 06:55:25 PM PDT 24 |
| Finished | Aug 13 06:56:05 PM PDT 24 |
| Peak memory | 575608 kb |
| Host | smart-79f72a0e-4de2-46a4-9cf7-f2aeffb9c8cc |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3028139438 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 54.xbar_unmapped_addr.3028139438 |
| Directory | /workspace/54.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/55.xbar_access_same_device.3804780957 |
| Short name | T1966 |
| Test name | |
| Test status | |
| Simulation time | 141266001 ps |
| CPU time | 11.84 seconds |
| Started | Aug 13 06:55:36 PM PDT 24 |
| Finished | Aug 13 06:55:48 PM PDT 24 |
| Peak memory | 575660 kb |
| Host | smart-67a49d65-85ac-4936-a01e-222f32b10288 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3804780957 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 55.xbar_access_same_device .3804780957 |
| Directory | /workspace/55.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/55.xbar_access_same_device_slow_rsp.1982764227 |
| Short name | T2501 |
| Test name | |
| Test status | |
| Simulation time | 2770436665 ps |
| CPU time | 51.39 seconds |
| Started | Aug 13 06:55:34 PM PDT 24 |
| Finished | Aug 13 06:56:26 PM PDT 24 |
| Peak memory | 574260 kb |
| Host | smart-73823006-f655-40ad-bd1d-496cdad5c7a5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1982764227 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 55.xbar_access_same_ device_slow_rsp.1982764227 |
| Directory | /workspace/55.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/55.xbar_error_and_unmapped_addr.2382788164 |
| Short name | T1752 |
| Test name | |
| Test status | |
| Simulation time | 1372188310 ps |
| CPU time | 47.67 seconds |
| Started | Aug 13 06:55:35 PM PDT 24 |
| Finished | Aug 13 06:56:22 PM PDT 24 |
| Peak memory | 575716 kb |
| Host | smart-5cf127cf-dc5c-4aec-84e7-cba0296f1cd2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2382788164 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 55.xbar_error_and_unmapped_add r.2382788164 |
| Directory | /workspace/55.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/55.xbar_error_random.1992082684 |
| Short name | T1455 |
| Test name | |
| Test status | |
| Simulation time | 2671564310 ps |
| CPU time | 93.28 seconds |
| Started | Aug 13 06:55:37 PM PDT 24 |
| Finished | Aug 13 06:57:10 PM PDT 24 |
| Peak memory | 575656 kb |
| Host | smart-30f2d2f0-6cfc-4866-af81-5891ecb94414 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1992082684 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 55.xbar_error_random.1992082684 |
| Directory | /workspace/55.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/55.xbar_random.1366708413 |
| Short name | T624 |
| Test name | |
| Test status | |
| Simulation time | 433243579 ps |
| CPU time | 35.37 seconds |
| Started | Aug 13 06:55:34 PM PDT 24 |
| Finished | Aug 13 06:56:10 PM PDT 24 |
| Peak memory | 575644 kb |
| Host | smart-7ce2993a-7510-4cc3-bca0-6436da7382d2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1366708413 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 55.xbar_random.1366708413 |
| Directory | /workspace/55.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/55.xbar_random_large_delays.533268762 |
| Short name | T2509 |
| Test name | |
| Test status | |
| Simulation time | 113228203432 ps |
| CPU time | 1218.42 seconds |
| Started | Aug 13 06:55:34 PM PDT 24 |
| Finished | Aug 13 07:15:53 PM PDT 24 |
| Peak memory | 575652 kb |
| Host | smart-9a476dfb-cb26-466b-8b8b-e65b71059415 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=533268762 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 55.xbar_random_large_delays.533268762 |
| Directory | /workspace/55.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/55.xbar_random_slow_rsp.145666645 |
| Short name | T2375 |
| Test name | |
| Test status | |
| Simulation time | 17397688841 ps |
| CPU time | 311.27 seconds |
| Started | Aug 13 06:55:34 PM PDT 24 |
| Finished | Aug 13 07:00:46 PM PDT 24 |
| Peak memory | 575540 kb |
| Host | smart-f07ea22b-ad6e-46f2-84bb-4c1fdbf18ce7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=145666645 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 55.xbar_random_slow_rsp.145666645 |
| Directory | /workspace/55.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/55.xbar_random_zero_delays.3117496752 |
| Short name | T2136 |
| Test name | |
| Test status | |
| Simulation time | 89213133 ps |
| CPU time | 10.18 seconds |
| Started | Aug 13 06:55:35 PM PDT 24 |
| Finished | Aug 13 06:55:46 PM PDT 24 |
| Peak memory | 575756 kb |
| Host | smart-93972900-9aa2-45ca-8bfd-b88640f8b67e |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3117496752 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 55.xbar_random_zero_del ays.3117496752 |
| Directory | /workspace/55.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/55.xbar_same_source.358617765 |
| Short name | T2596 |
| Test name | |
| Test status | |
| Simulation time | 455365528 ps |
| CPU time | 16.24 seconds |
| Started | Aug 13 06:55:35 PM PDT 24 |
| Finished | Aug 13 06:55:51 PM PDT 24 |
| Peak memory | 575648 kb |
| Host | smart-7d5d7f38-b15f-4b4e-97e9-c8c9c6726be5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=358617765 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 55.xbar_same_source.358617765 |
| Directory | /workspace/55.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/55.xbar_smoke.1313601309 |
| Short name | T2208 |
| Test name | |
| Test status | |
| Simulation time | 181728187 ps |
| CPU time | 8.49 seconds |
| Started | Aug 13 06:55:35 PM PDT 24 |
| Finished | Aug 13 06:55:44 PM PDT 24 |
| Peak memory | 573592 kb |
| Host | smart-fa893b9a-4dc6-45f6-9d36-0ca29b4a0ea2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1313601309 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 55.xbar_smoke.1313601309 |
| Directory | /workspace/55.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/55.xbar_smoke_large_delays.3209478868 |
| Short name | T1770 |
| Test name | |
| Test status | |
| Simulation time | 7559549611 ps |
| CPU time | 81.55 seconds |
| Started | Aug 13 06:55:35 PM PDT 24 |
| Finished | Aug 13 06:56:57 PM PDT 24 |
| Peak memory | 573640 kb |
| Host | smart-4dd77332-f474-4416-b777-127bb6d0e146 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3209478868 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 55.xbar_smoke_large_delays.3209478868 |
| Directory | /workspace/55.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/55.xbar_smoke_slow_rsp.3243560314 |
| Short name | T2756 |
| Test name | |
| Test status | |
| Simulation time | 5554953191 ps |
| CPU time | 95.73 seconds |
| Started | Aug 13 06:55:36 PM PDT 24 |
| Finished | Aug 13 06:57:12 PM PDT 24 |
| Peak memory | 573688 kb |
| Host | smart-f6575151-6edf-4999-b613-06d9fdf94e54 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3243560314 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 55.xbar_smoke_slow_rsp.3243560314 |
| Directory | /workspace/55.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/55.xbar_smoke_zero_delays.2573371087 |
| Short name | T1530 |
| Test name | |
| Test status | |
| Simulation time | 43487956 ps |
| CPU time | 6.03 seconds |
| Started | Aug 13 06:55:36 PM PDT 24 |
| Finished | Aug 13 06:55:42 PM PDT 24 |
| Peak memory | 573584 kb |
| Host | smart-c8c03c11-b7b8-4350-b02c-7178cc16f0d2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2573371087 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 55.xbar_smoke_zero_delay s.2573371087 |
| Directory | /workspace/55.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/55.xbar_stress_all.1595529665 |
| Short name | T1918 |
| Test name | |
| Test status | |
| Simulation time | 9123673578 ps |
| CPU time | 322.63 seconds |
| Started | Aug 13 06:55:36 PM PDT 24 |
| Finished | Aug 13 07:00:59 PM PDT 24 |
| Peak memory | 576572 kb |
| Host | smart-08c682a4-3c44-496d-a242-6d74d9824581 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1595529665 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 55.xbar_stress_all.1595529665 |
| Directory | /workspace/55.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/55.xbar_stress_all_with_error.1264132650 |
| Short name | T552 |
| Test name | |
| Test status | |
| Simulation time | 4503816351 ps |
| CPU time | 201.42 seconds |
| Started | Aug 13 06:55:33 PM PDT 24 |
| Finished | Aug 13 06:58:55 PM PDT 24 |
| Peak memory | 576536 kb |
| Host | smart-6b51afa4-a3e0-48a6-9114-8b8857941ba8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1264132650 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 55.xbar_stress_all_with_error.1264132650 |
| Directory | /workspace/55.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/55.xbar_stress_all_with_rand_reset.1944591252 |
| Short name | T2380 |
| Test name | |
| Test status | |
| Simulation time | 198462368 ps |
| CPU time | 89.25 seconds |
| Started | Aug 13 06:55:33 PM PDT 24 |
| Finished | Aug 13 06:57:03 PM PDT 24 |
| Peak memory | 576468 kb |
| Host | smart-0672676b-4edc-4a52-94b9-d9acfd9b820b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1944591252 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 55.xbar_stress_all _with_rand_reset.1944591252 |
| Directory | /workspace/55.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/55.xbar_stress_all_with_reset_error.449267297 |
| Short name | T2123 |
| Test name | |
| Test status | |
| Simulation time | 929006975 ps |
| CPU time | 238.78 seconds |
| Started | Aug 13 06:55:34 PM PDT 24 |
| Finished | Aug 13 06:59:33 PM PDT 24 |
| Peak memory | 575656 kb |
| Host | smart-1cef121d-3bfb-4bd6-9c4e-6a6b226433ff |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=449267297 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 55.xbar_stress_all _with_reset_error.449267297 |
| Directory | /workspace/55.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/55.xbar_unmapped_addr.1896629022 |
| Short name | T1773 |
| Test name | |
| Test status | |
| Simulation time | 1175716183 ps |
| CPU time | 50.33 seconds |
| Started | Aug 13 06:55:37 PM PDT 24 |
| Finished | Aug 13 06:56:27 PM PDT 24 |
| Peak memory | 575724 kb |
| Host | smart-ba3a8044-6798-4a8f-8c53-5fc1a8a0899a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1896629022 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 55.xbar_unmapped_addr.1896629022 |
| Directory | /workspace/55.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/56.xbar_access_same_device.641664389 |
| Short name | T892 |
| Test name | |
| Test status | |
| Simulation time | 429430018 ps |
| CPU time | 40.37 seconds |
| Started | Aug 13 06:55:43 PM PDT 24 |
| Finished | Aug 13 06:56:23 PM PDT 24 |
| Peak memory | 575420 kb |
| Host | smart-9a483e7b-4930-47e4-8361-73b303e9ac7c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=641664389 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 56.xbar_access_same_device. 641664389 |
| Directory | /workspace/56.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/56.xbar_access_same_device_slow_rsp.732706327 |
| Short name | T1605 |
| Test name | |
| Test status | |
| Simulation time | 90133169161 ps |
| CPU time | 1670.5 seconds |
| Started | Aug 13 06:55:42 PM PDT 24 |
| Finished | Aug 13 07:23:33 PM PDT 24 |
| Peak memory | 575848 kb |
| Host | smart-64e63e0f-184c-46e6-8dd4-ed08e3518441 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=732706327 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 56.xbar_access_same_d evice_slow_rsp.732706327 |
| Directory | /workspace/56.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/56.xbar_error_and_unmapped_addr.424292409 |
| Short name | T2528 |
| Test name | |
| Test status | |
| Simulation time | 109881438 ps |
| CPU time | 8.21 seconds |
| Started | Aug 13 06:55:41 PM PDT 24 |
| Finished | Aug 13 06:55:49 PM PDT 24 |
| Peak memory | 573632 kb |
| Host | smart-f25b2b1e-434e-4624-b644-56aba1537c8a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=424292409 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 56.xbar_error_and_unmapped_addr .424292409 |
| Directory | /workspace/56.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/56.xbar_error_random.3742189858 |
| Short name | T2017 |
| Test name | |
| Test status | |
| Simulation time | 2166504765 ps |
| CPU time | 73.16 seconds |
| Started | Aug 13 06:55:43 PM PDT 24 |
| Finished | Aug 13 06:56:56 PM PDT 24 |
| Peak memory | 575760 kb |
| Host | smart-de7278a1-e4a7-46c0-9f81-92138b86a9b3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3742189858 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 56.xbar_error_random.3742189858 |
| Directory | /workspace/56.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/56.xbar_random.299022283 |
| Short name | T2013 |
| Test name | |
| Test status | |
| Simulation time | 320969091 ps |
| CPU time | 33.15 seconds |
| Started | Aug 13 06:55:41 PM PDT 24 |
| Finished | Aug 13 06:56:14 PM PDT 24 |
| Peak memory | 575500 kb |
| Host | smart-20c4da92-f59d-4fa9-9530-e45c394a9ea5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=299022283 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 56.xbar_random.299022283 |
| Directory | /workspace/56.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/56.xbar_random_slow_rsp.4087539181 |
| Short name | T1632 |
| Test name | |
| Test status | |
| Simulation time | 29930379451 ps |
| CPU time | 477.08 seconds |
| Started | Aug 13 06:55:40 PM PDT 24 |
| Finished | Aug 13 07:03:37 PM PDT 24 |
| Peak memory | 575700 kb |
| Host | smart-38243a71-f12f-4f66-88f7-1c3bcafbb16a |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4087539181 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 56.xbar_random_slow_rsp.4087539181 |
| Directory | /workspace/56.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/56.xbar_random_zero_delays.1265506709 |
| Short name | T1487 |
| Test name | |
| Test status | |
| Simulation time | 238606657 ps |
| CPU time | 21.8 seconds |
| Started | Aug 13 06:55:40 PM PDT 24 |
| Finished | Aug 13 06:56:02 PM PDT 24 |
| Peak memory | 575576 kb |
| Host | smart-47ed20c6-d1a0-470f-a204-b834a22c0046 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1265506709 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 56.xbar_random_zero_del ays.1265506709 |
| Directory | /workspace/56.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/56.xbar_same_source.1035412907 |
| Short name | T2082 |
| Test name | |
| Test status | |
| Simulation time | 2593842129 ps |
| CPU time | 77.64 seconds |
| Started | Aug 13 06:55:41 PM PDT 24 |
| Finished | Aug 13 06:56:58 PM PDT 24 |
| Peak memory | 575616 kb |
| Host | smart-8f5d5303-1026-4650-ba7e-f281daf79d84 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1035412907 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 56.xbar_same_source.1035412907 |
| Directory | /workspace/56.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/56.xbar_smoke.2256022863 |
| Short name | T1754 |
| Test name | |
| Test status | |
| Simulation time | 174349625 ps |
| CPU time | 7.92 seconds |
| Started | Aug 13 06:55:36 PM PDT 24 |
| Finished | Aug 13 06:55:44 PM PDT 24 |
| Peak memory | 573580 kb |
| Host | smart-e1d3bc56-a4df-426c-93bd-75629e2a9941 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2256022863 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 56.xbar_smoke.2256022863 |
| Directory | /workspace/56.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/56.xbar_smoke_large_delays.2768093133 |
| Short name | T1439 |
| Test name | |
| Test status | |
| Simulation time | 9118929401 ps |
| CPU time | 95.21 seconds |
| Started | Aug 13 06:55:41 PM PDT 24 |
| Finished | Aug 13 06:57:16 PM PDT 24 |
| Peak memory | 574340 kb |
| Host | smart-e768868b-79ad-4532-aec3-404829184fe2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2768093133 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 56.xbar_smoke_large_delays.2768093133 |
| Directory | /workspace/56.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/56.xbar_smoke_slow_rsp.1461295224 |
| Short name | T1608 |
| Test name | |
| Test status | |
| Simulation time | 3596518104 ps |
| CPU time | 60.15 seconds |
| Started | Aug 13 06:55:41 PM PDT 24 |
| Finished | Aug 13 06:56:41 PM PDT 24 |
| Peak memory | 573676 kb |
| Host | smart-21a1f337-4223-474c-b309-547753332554 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1461295224 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 56.xbar_smoke_slow_rsp.1461295224 |
| Directory | /workspace/56.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/56.xbar_smoke_zero_delays.1996208093 |
| Short name | T2573 |
| Test name | |
| Test status | |
| Simulation time | 49042012 ps |
| CPU time | 6.79 seconds |
| Started | Aug 13 06:55:33 PM PDT 24 |
| Finished | Aug 13 06:55:40 PM PDT 24 |
| Peak memory | 573548 kb |
| Host | smart-0e29d567-cf8e-481c-9c15-588ffb813874 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1996208093 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 56.xbar_smoke_zero_delay s.1996208093 |
| Directory | /workspace/56.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/56.xbar_stress_all.871122571 |
| Short name | T1983 |
| Test name | |
| Test status | |
| Simulation time | 2454178212 ps |
| CPU time | 245.19 seconds |
| Started | Aug 13 06:55:43 PM PDT 24 |
| Finished | Aug 13 06:59:49 PM PDT 24 |
| Peak memory | 576460 kb |
| Host | smart-df73cedf-7680-4081-93da-a28342943153 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=871122571 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 56.xbar_stress_all.871122571 |
| Directory | /workspace/56.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/56.xbar_stress_all_with_error.474799124 |
| Short name | T2940 |
| Test name | |
| Test status | |
| Simulation time | 7229884877 ps |
| CPU time | 285.94 seconds |
| Started | Aug 13 06:55:42 PM PDT 24 |
| Finished | Aug 13 07:00:28 PM PDT 24 |
| Peak memory | 576056 kb |
| Host | smart-f4dda778-95b4-42c1-951e-bc9d7ac476be |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=474799124 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 56.xbar_stress_all_with_error.474799124 |
| Directory | /workspace/56.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/56.xbar_stress_all_with_rand_reset.1932887462 |
| Short name | T1835 |
| Test name | |
| Test status | |
| Simulation time | 140636515 ps |
| CPU time | 62.44 seconds |
| Started | Aug 13 06:55:43 PM PDT 24 |
| Finished | Aug 13 06:56:45 PM PDT 24 |
| Peak memory | 575688 kb |
| Host | smart-f6f5e1ba-3504-4215-85df-fb177450fd00 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1932887462 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 56.xbar_stress_all _with_rand_reset.1932887462 |
| Directory | /workspace/56.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/56.xbar_stress_all_with_reset_error.1530856042 |
| Short name | T2556 |
| Test name | |
| Test status | |
| Simulation time | 6875849880 ps |
| CPU time | 633.91 seconds |
| Started | Aug 13 06:55:39 PM PDT 24 |
| Finished | Aug 13 07:06:14 PM PDT 24 |
| Peak memory | 579640 kb |
| Host | smart-538ac29d-1410-4809-8a96-75eed1beb9c2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1530856042 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 56.xbar_stress_al l_with_reset_error.1530856042 |
| Directory | /workspace/56.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/56.xbar_unmapped_addr.2467165556 |
| Short name | T645 |
| Test name | |
| Test status | |
| Simulation time | 1268476721 ps |
| CPU time | 57.59 seconds |
| Started | Aug 13 06:55:40 PM PDT 24 |
| Finished | Aug 13 06:56:38 PM PDT 24 |
| Peak memory | 575720 kb |
| Host | smart-51d42a79-788a-4c5a-a964-5d6793e3b37c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2467165556 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 56.xbar_unmapped_addr.2467165556 |
| Directory | /workspace/56.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/57.xbar_access_same_device.1895137221 |
| Short name | T476 |
| Test name | |
| Test status | |
| Simulation time | 1273147291 ps |
| CPU time | 50.03 seconds |
| Started | Aug 13 06:55:51 PM PDT 24 |
| Finished | Aug 13 06:56:41 PM PDT 24 |
| Peak memory | 575484 kb |
| Host | smart-da0dc4ae-8363-47a9-9d11-d23d514c9c22 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1895137221 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 57.xbar_access_same_device .1895137221 |
| Directory | /workspace/57.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/57.xbar_access_same_device_slow_rsp.521686412 |
| Short name | T882 |
| Test name | |
| Test status | |
| Simulation time | 27822222672 ps |
| CPU time | 470.62 seconds |
| Started | Aug 13 06:55:48 PM PDT 24 |
| Finished | Aug 13 07:03:39 PM PDT 24 |
| Peak memory | 575788 kb |
| Host | smart-1aadb52a-93ab-4208-a0c1-2cf4ca6330a8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=521686412 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 57.xbar_access_same_d evice_slow_rsp.521686412 |
| Directory | /workspace/57.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/57.xbar_error_and_unmapped_addr.1617353128 |
| Short name | T2196 |
| Test name | |
| Test status | |
| Simulation time | 122060148 ps |
| CPU time | 14.67 seconds |
| Started | Aug 13 06:55:48 PM PDT 24 |
| Finished | Aug 13 06:56:03 PM PDT 24 |
| Peak memory | 575688 kb |
| Host | smart-879b9f45-c94b-490f-affd-340efadc9d2f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1617353128 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 57.xbar_error_and_unmapped_add r.1617353128 |
| Directory | /workspace/57.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/57.xbar_error_random.1304535672 |
| Short name | T2943 |
| Test name | |
| Test status | |
| Simulation time | 38206657 ps |
| CPU time | 6.6 seconds |
| Started | Aug 13 06:55:48 PM PDT 24 |
| Finished | Aug 13 06:55:54 PM PDT 24 |
| Peak memory | 574188 kb |
| Host | smart-e8d490c7-7804-4a77-b537-0dbec57d27f6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1304535672 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 57.xbar_error_random.1304535672 |
| Directory | /workspace/57.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/57.xbar_random.437010048 |
| Short name | T2469 |
| Test name | |
| Test status | |
| Simulation time | 1190432862 ps |
| CPU time | 44.61 seconds |
| Started | Aug 13 06:55:51 PM PDT 24 |
| Finished | Aug 13 06:56:36 PM PDT 24 |
| Peak memory | 575484 kb |
| Host | smart-b51574e5-79a2-484c-aa5e-a69fd25cf4ba |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=437010048 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 57.xbar_random.437010048 |
| Directory | /workspace/57.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/57.xbar_random_large_delays.1442248785 |
| Short name | T699 |
| Test name | |
| Test status | |
| Simulation time | 82606429688 ps |
| CPU time | 929.91 seconds |
| Started | Aug 13 06:55:52 PM PDT 24 |
| Finished | Aug 13 07:11:23 PM PDT 24 |
| Peak memory | 575820 kb |
| Host | smart-16d0eaff-80a8-456c-a396-a78415e8c679 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1442248785 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 57.xbar_random_large_delays.1442248785 |
| Directory | /workspace/57.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/57.xbar_random_slow_rsp.3948909224 |
| Short name | T2788 |
| Test name | |
| Test status | |
| Simulation time | 62001370873 ps |
| CPU time | 1213.71 seconds |
| Started | Aug 13 06:55:48 PM PDT 24 |
| Finished | Aug 13 07:16:02 PM PDT 24 |
| Peak memory | 575668 kb |
| Host | smart-f43cca0a-9649-43be-aeac-bac69c6e3339 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3948909224 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 57.xbar_random_slow_rsp.3948909224 |
| Directory | /workspace/57.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/57.xbar_random_zero_delays.1195668932 |
| Short name | T522 |
| Test name | |
| Test status | |
| Simulation time | 467879527 ps |
| CPU time | 37.9 seconds |
| Started | Aug 13 06:55:50 PM PDT 24 |
| Finished | Aug 13 06:56:28 PM PDT 24 |
| Peak memory | 575604 kb |
| Host | smart-b924505d-c13d-498c-9450-838a62533f5b |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1195668932 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 57.xbar_random_zero_del ays.1195668932 |
| Directory | /workspace/57.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/57.xbar_same_source.628006540 |
| Short name | T2283 |
| Test name | |
| Test status | |
| Simulation time | 157095502 ps |
| CPU time | 14.37 seconds |
| Started | Aug 13 06:55:50 PM PDT 24 |
| Finished | Aug 13 06:56:04 PM PDT 24 |
| Peak memory | 575476 kb |
| Host | smart-350068bc-095b-432d-80a4-b8c2f1700259 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=628006540 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 57.xbar_same_source.628006540 |
| Directory | /workspace/57.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/57.xbar_smoke.833181922 |
| Short name | T1616 |
| Test name | |
| Test status | |
| Simulation time | 184824850 ps |
| CPU time | 8.52 seconds |
| Started | Aug 13 06:55:50 PM PDT 24 |
| Finished | Aug 13 06:55:59 PM PDT 24 |
| Peak memory | 573704 kb |
| Host | smart-a4981564-af48-441f-beba-4351b17427bf |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=833181922 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 57.xbar_smoke.833181922 |
| Directory | /workspace/57.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/57.xbar_smoke_large_delays.3582560833 |
| Short name | T2373 |
| Test name | |
| Test status | |
| Simulation time | 8941540669 ps |
| CPU time | 94.26 seconds |
| Started | Aug 13 06:55:49 PM PDT 24 |
| Finished | Aug 13 06:57:23 PM PDT 24 |
| Peak memory | 573632 kb |
| Host | smart-96a5eb74-89aa-498e-9916-0ebb983cda06 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3582560833 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 57.xbar_smoke_large_delays.3582560833 |
| Directory | /workspace/57.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/57.xbar_smoke_slow_rsp.1962086196 |
| Short name | T1855 |
| Test name | |
| Test status | |
| Simulation time | 5530410456 ps |
| CPU time | 97.53 seconds |
| Started | Aug 13 06:55:48 PM PDT 24 |
| Finished | Aug 13 06:57:26 PM PDT 24 |
| Peak memory | 573608 kb |
| Host | smart-1d315eff-ad36-47d9-86c7-2939c81ad353 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1962086196 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 57.xbar_smoke_slow_rsp.1962086196 |
| Directory | /workspace/57.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/57.xbar_smoke_zero_delays.2557064276 |
| Short name | T2464 |
| Test name | |
| Test status | |
| Simulation time | 50030549 ps |
| CPU time | 6.26 seconds |
| Started | Aug 13 06:55:48 PM PDT 24 |
| Finished | Aug 13 06:55:54 PM PDT 24 |
| Peak memory | 574240 kb |
| Host | smart-ca01d8a8-a79a-42c9-8866-1075c0b04847 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2557064276 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 57.xbar_smoke_zero_delay s.2557064276 |
| Directory | /workspace/57.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/57.xbar_stress_all.2907375614 |
| Short name | T2179 |
| Test name | |
| Test status | |
| Simulation time | 3600035493 ps |
| CPU time | 339.77 seconds |
| Started | Aug 13 06:55:51 PM PDT 24 |
| Finished | Aug 13 07:01:31 PM PDT 24 |
| Peak memory | 576532 kb |
| Host | smart-bee0af04-9eb6-4016-929b-bfb690d1670d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2907375614 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 57.xbar_stress_all.2907375614 |
| Directory | /workspace/57.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/57.xbar_stress_all_with_error.1190594158 |
| Short name | T2433 |
| Test name | |
| Test status | |
| Simulation time | 7224345721 ps |
| CPU time | 237.94 seconds |
| Started | Aug 13 06:55:50 PM PDT 24 |
| Finished | Aug 13 06:59:48 PM PDT 24 |
| Peak memory | 575700 kb |
| Host | smart-a72c31cf-fa37-44dd-8d63-eed4bdae66f6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1190594158 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 57.xbar_stress_all_with_error.1190594158 |
| Directory | /workspace/57.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/57.xbar_stress_all_with_rand_reset.92358292 |
| Short name | T934 |
| Test name | |
| Test status | |
| Simulation time | 157844246 ps |
| CPU time | 53.4 seconds |
| Started | Aug 13 06:55:52 PM PDT 24 |
| Finished | Aug 13 06:56:45 PM PDT 24 |
| Peak memory | 576444 kb |
| Host | smart-0a52c30c-80dc-4fa8-9f45-cae3f3e92bee |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=92358292 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_rese t_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 57.xbar_stress_all_w ith_rand_reset.92358292 |
| Directory | /workspace/57.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/57.xbar_stress_all_with_reset_error.1108744146 |
| Short name | T924 |
| Test name | |
| Test status | |
| Simulation time | 122079766 ps |
| CPU time | 51.2 seconds |
| Started | Aug 13 06:55:50 PM PDT 24 |
| Finished | Aug 13 06:56:41 PM PDT 24 |
| Peak memory | 576496 kb |
| Host | smart-a569d9a5-0225-45ea-b4ea-5e973204f82a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1108744146 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 57.xbar_stress_al l_with_reset_error.1108744146 |
| Directory | /workspace/57.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/57.xbar_unmapped_addr.998850475 |
| Short name | T2338 |
| Test name | |
| Test status | |
| Simulation time | 1236654613 ps |
| CPU time | 49.61 seconds |
| Started | Aug 13 06:55:50 PM PDT 24 |
| Finished | Aug 13 06:56:40 PM PDT 24 |
| Peak memory | 575728 kb |
| Host | smart-d139a992-9e46-480e-8ecc-42054e2d12de |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=998850475 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 57.xbar_unmapped_addr.998850475 |
| Directory | /workspace/57.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/58.xbar_access_same_device.1130771737 |
| Short name | T2827 |
| Test name | |
| Test status | |
| Simulation time | 342392301 ps |
| CPU time | 18.04 seconds |
| Started | Aug 13 06:55:56 PM PDT 24 |
| Finished | Aug 13 06:56:14 PM PDT 24 |
| Peak memory | 576332 kb |
| Host | smart-38472a85-1718-41d1-a37a-c98100888749 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1130771737 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 58.xbar_access_same_device .1130771737 |
| Directory | /workspace/58.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/58.xbar_access_same_device_slow_rsp.2580650459 |
| Short name | T1631 |
| Test name | |
| Test status | |
| Simulation time | 11129206544 ps |
| CPU time | 190.77 seconds |
| Started | Aug 13 06:55:56 PM PDT 24 |
| Finished | Aug 13 06:59:06 PM PDT 24 |
| Peak memory | 573624 kb |
| Host | smart-e7a998e0-f7e7-4632-a39e-2214f7b52cce |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2580650459 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 58.xbar_access_same_ device_slow_rsp.2580650459 |
| Directory | /workspace/58.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/58.xbar_error_and_unmapped_addr.740262223 |
| Short name | T1865 |
| Test name | |
| Test status | |
| Simulation time | 647579074 ps |
| CPU time | 31.24 seconds |
| Started | Aug 13 06:55:54 PM PDT 24 |
| Finished | Aug 13 06:56:26 PM PDT 24 |
| Peak memory | 575728 kb |
| Host | smart-f05b73d5-8a89-472b-a154-d4de6deee500 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=740262223 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 58.xbar_error_and_unmapped_addr .740262223 |
| Directory | /workspace/58.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/58.xbar_error_random.3887432103 |
| Short name | T2393 |
| Test name | |
| Test status | |
| Simulation time | 2671231035 ps |
| CPU time | 94.21 seconds |
| Started | Aug 13 06:55:55 PM PDT 24 |
| Finished | Aug 13 06:57:29 PM PDT 24 |
| Peak memory | 575772 kb |
| Host | smart-c9c032b1-0630-4350-afaa-bd9e590bb845 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3887432103 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 58.xbar_error_random.3887432103 |
| Directory | /workspace/58.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/58.xbar_random.1042071546 |
| Short name | T1601 |
| Test name | |
| Test status | |
| Simulation time | 99205014 ps |
| CPU time | 12.15 seconds |
| Started | Aug 13 06:55:54 PM PDT 24 |
| Finished | Aug 13 06:56:06 PM PDT 24 |
| Peak memory | 575604 kb |
| Host | smart-98f4f306-6040-4afa-8147-5403f534de3f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1042071546 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 58.xbar_random.1042071546 |
| Directory | /workspace/58.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/58.xbar_random_large_delays.2048477836 |
| Short name | T1551 |
| Test name | |
| Test status | |
| Simulation time | 68828782683 ps |
| CPU time | 709.18 seconds |
| Started | Aug 13 06:55:59 PM PDT 24 |
| Finished | Aug 13 07:07:48 PM PDT 24 |
| Peak memory | 575784 kb |
| Host | smart-55aa2ee9-97f4-4f08-8b0c-c2fad1ce7003 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2048477836 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 58.xbar_random_large_delays.2048477836 |
| Directory | /workspace/58.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/58.xbar_random_slow_rsp.2121782950 |
| Short name | T1722 |
| Test name | |
| Test status | |
| Simulation time | 66674087793 ps |
| CPU time | 1301.56 seconds |
| Started | Aug 13 06:55:58 PM PDT 24 |
| Finished | Aug 13 07:17:39 PM PDT 24 |
| Peak memory | 575608 kb |
| Host | smart-e45cd89b-15f8-429b-95b4-27f8c2ef216e |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2121782950 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 58.xbar_random_slow_rsp.2121782950 |
| Directory | /workspace/58.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/58.xbar_random_zero_delays.1892729025 |
| Short name | T2180 |
| Test name | |
| Test status | |
| Simulation time | 306683394 ps |
| CPU time | 25.97 seconds |
| Started | Aug 13 06:55:55 PM PDT 24 |
| Finished | Aug 13 06:56:21 PM PDT 24 |
| Peak memory | 575500 kb |
| Host | smart-5abc46c6-b007-4e6a-9824-569a35dff161 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1892729025 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 58.xbar_random_zero_del ays.1892729025 |
| Directory | /workspace/58.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/58.xbar_same_source.1718878075 |
| Short name | T2198 |
| Test name | |
| Test status | |
| Simulation time | 563524010 ps |
| CPU time | 37.9 seconds |
| Started | Aug 13 06:55:56 PM PDT 24 |
| Finished | Aug 13 06:56:34 PM PDT 24 |
| Peak memory | 575508 kb |
| Host | smart-97d44f6c-542c-44ca-be65-54a06ba1a7bd |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1718878075 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 58.xbar_same_source.1718878075 |
| Directory | /workspace/58.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/58.xbar_smoke.4120112613 |
| Short name | T1679 |
| Test name | |
| Test status | |
| Simulation time | 215129170 ps |
| CPU time | 9.15 seconds |
| Started | Aug 13 06:55:50 PM PDT 24 |
| Finished | Aug 13 06:55:59 PM PDT 24 |
| Peak memory | 574132 kb |
| Host | smart-a89f440f-650f-4c28-9ad5-1ba95130dccd |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4120112613 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 58.xbar_smoke.4120112613 |
| Directory | /workspace/58.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/58.xbar_smoke_large_delays.3853375459 |
| Short name | T1867 |
| Test name | |
| Test status | |
| Simulation time | 9553337083 ps |
| CPU time | 105.95 seconds |
| Started | Aug 13 06:55:55 PM PDT 24 |
| Finished | Aug 13 06:57:41 PM PDT 24 |
| Peak memory | 573648 kb |
| Host | smart-7d5b4767-45c7-4a2b-b9bb-478f496d0ea5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3853375459 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 58.xbar_smoke_large_delays.3853375459 |
| Directory | /workspace/58.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/58.xbar_smoke_slow_rsp.3445550965 |
| Short name | T1603 |
| Test name | |
| Test status | |
| Simulation time | 4987311411 ps |
| CPU time | 82.52 seconds |
| Started | Aug 13 06:55:55 PM PDT 24 |
| Finished | Aug 13 06:57:18 PM PDT 24 |
| Peak memory | 573648 kb |
| Host | smart-1002a50e-6d8a-4d99-95f2-0f1b467e8917 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3445550965 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 58.xbar_smoke_slow_rsp.3445550965 |
| Directory | /workspace/58.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/58.xbar_smoke_zero_delays.2018465940 |
| Short name | T682 |
| Test name | |
| Test status | |
| Simulation time | 47591609 ps |
| CPU time | 6.37 seconds |
| Started | Aug 13 06:55:49 PM PDT 24 |
| Finished | Aug 13 06:55:55 PM PDT 24 |
| Peak memory | 573536 kb |
| Host | smart-32d7dc2b-e11f-4670-88db-bf3e23aa162f |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2018465940 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 58.xbar_smoke_zero_delay s.2018465940 |
| Directory | /workspace/58.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/58.xbar_stress_all.3569673105 |
| Short name | T2187 |
| Test name | |
| Test status | |
| Simulation time | 11963950922 ps |
| CPU time | 464.22 seconds |
| Started | Aug 13 06:55:57 PM PDT 24 |
| Finished | Aug 13 07:03:41 PM PDT 24 |
| Peak memory | 576528 kb |
| Host | smart-3388b781-a9be-45c0-85cb-55bc1b63be8a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3569673105 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 58.xbar_stress_all.3569673105 |
| Directory | /workspace/58.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/58.xbar_stress_all_with_error.171226439 |
| Short name | T2301 |
| Test name | |
| Test status | |
| Simulation time | 10834462025 ps |
| CPU time | 413.23 seconds |
| Started | Aug 13 06:55:54 PM PDT 24 |
| Finished | Aug 13 07:02:47 PM PDT 24 |
| Peak memory | 575884 kb |
| Host | smart-70fbda1e-1a2a-4e33-aa40-554e55dc0bea |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=171226439 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 58.xbar_stress_all_with_error.171226439 |
| Directory | /workspace/58.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/58.xbar_stress_all_with_rand_reset.2331734767 |
| Short name | T1741 |
| Test name | |
| Test status | |
| Simulation time | 77406012 ps |
| CPU time | 20.83 seconds |
| Started | Aug 13 06:55:57 PM PDT 24 |
| Finished | Aug 13 06:56:18 PM PDT 24 |
| Peak memory | 575656 kb |
| Host | smart-3df8a63c-eeb3-4ff5-90d8-49a518414e0e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2331734767 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 58.xbar_stress_all _with_rand_reset.2331734767 |
| Directory | /workspace/58.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/58.xbar_stress_all_with_reset_error.4149869817 |
| Short name | T1916 |
| Test name | |
| Test status | |
| Simulation time | 4864436569 ps |
| CPU time | 258.91 seconds |
| Started | Aug 13 06:55:54 PM PDT 24 |
| Finished | Aug 13 07:00:13 PM PDT 24 |
| Peak memory | 576568 kb |
| Host | smart-a098d946-0c0c-486d-b3a3-f5ba31f856e1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4149869817 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 58.xbar_stress_al l_with_reset_error.4149869817 |
| Directory | /workspace/58.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/58.xbar_unmapped_addr.2239109083 |
| Short name | T2738 |
| Test name | |
| Test status | |
| Simulation time | 22753838 ps |
| CPU time | 5.84 seconds |
| Started | Aug 13 06:55:55 PM PDT 24 |
| Finished | Aug 13 06:56:01 PM PDT 24 |
| Peak memory | 573560 kb |
| Host | smart-e4a3ad41-c675-4c1c-a405-e1f2df4a5b9f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2239109083 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 58.xbar_unmapped_addr.2239109083 |
| Directory | /workspace/58.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/59.xbar_access_same_device.1463221038 |
| Short name | T1534 |
| Test name | |
| Test status | |
| Simulation time | 597604312 ps |
| CPU time | 63.84 seconds |
| Started | Aug 13 06:56:03 PM PDT 24 |
| Finished | Aug 13 06:57:06 PM PDT 24 |
| Peak memory | 575736 kb |
| Host | smart-4c6d8812-1afa-4bf4-8a20-980e35b99a5c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1463221038 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 59.xbar_access_same_device .1463221038 |
| Directory | /workspace/59.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/59.xbar_access_same_device_slow_rsp.3196847901 |
| Short name | T2349 |
| Test name | |
| Test status | |
| Simulation time | 26298986049 ps |
| CPU time | 480.07 seconds |
| Started | Aug 13 06:56:11 PM PDT 24 |
| Finished | Aug 13 07:04:12 PM PDT 24 |
| Peak memory | 575632 kb |
| Host | smart-332346d7-3702-4a82-8566-49f1edd950a9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3196847901 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 59.xbar_access_same_ device_slow_rsp.3196847901 |
| Directory | /workspace/59.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/59.xbar_error_and_unmapped_addr.1375423332 |
| Short name | T2376 |
| Test name | |
| Test status | |
| Simulation time | 252868481 ps |
| CPU time | 11.57 seconds |
| Started | Aug 13 06:56:13 PM PDT 24 |
| Finished | Aug 13 06:56:24 PM PDT 24 |
| Peak memory | 575724 kb |
| Host | smart-c6a30ad9-f59b-4721-9867-c2fdac1d9255 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1375423332 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 59.xbar_error_and_unmapped_add r.1375423332 |
| Directory | /workspace/59.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/59.xbar_error_random.306676042 |
| Short name | T2761 |
| Test name | |
| Test status | |
| Simulation time | 2592994758 ps |
| CPU time | 87.35 seconds |
| Started | Aug 13 06:56:08 PM PDT 24 |
| Finished | Aug 13 06:57:36 PM PDT 24 |
| Peak memory | 575744 kb |
| Host | smart-a475342a-749a-4f31-8ea9-8d9378804e6f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=306676042 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 59.xbar_error_random.306676042 |
| Directory | /workspace/59.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/59.xbar_random.3737367838 |
| Short name | T2278 |
| Test name | |
| Test status | |
| Simulation time | 2379369613 ps |
| CPU time | 85.83 seconds |
| Started | Aug 13 06:56:01 PM PDT 24 |
| Finished | Aug 13 06:57:27 PM PDT 24 |
| Peak memory | 575704 kb |
| Host | smart-7c2b8185-9038-40b0-9615-ef47b9f9b874 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3737367838 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 59.xbar_random.3737367838 |
| Directory | /workspace/59.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/59.xbar_random_large_delays.2023048865 |
| Short name | T2378 |
| Test name | |
| Test status | |
| Simulation time | 97137254925 ps |
| CPU time | 1051.94 seconds |
| Started | Aug 13 06:56:02 PM PDT 24 |
| Finished | Aug 13 07:13:34 PM PDT 24 |
| Peak memory | 575676 kb |
| Host | smart-892943cb-e99c-4d69-8bc8-94d3681f91fc |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2023048865 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 59.xbar_random_large_delays.2023048865 |
| Directory | /workspace/59.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/59.xbar_random_slow_rsp.1947550765 |
| Short name | T2833 |
| Test name | |
| Test status | |
| Simulation time | 31083848484 ps |
| CPU time | 556.69 seconds |
| Started | Aug 13 06:56:01 PM PDT 24 |
| Finished | Aug 13 07:05:18 PM PDT 24 |
| Peak memory | 575744 kb |
| Host | smart-1a7aa421-72d3-409d-b2e6-3b560b3030a1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1947550765 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 59.xbar_random_slow_rsp.1947550765 |
| Directory | /workspace/59.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/59.xbar_random_zero_delays.3942562567 |
| Short name | T2422 |
| Test name | |
| Test status | |
| Simulation time | 35612189 ps |
| CPU time | 5.84 seconds |
| Started | Aug 13 06:56:02 PM PDT 24 |
| Finished | Aug 13 06:56:08 PM PDT 24 |
| Peak memory | 574248 kb |
| Host | smart-0fca21a5-41ca-4712-938c-350b24764c21 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3942562567 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 59.xbar_random_zero_del ays.3942562567 |
| Directory | /workspace/59.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/59.xbar_same_source.3428399684 |
| Short name | T2146 |
| Test name | |
| Test status | |
| Simulation time | 2578732377 ps |
| CPU time | 79.27 seconds |
| Started | Aug 13 06:56:12 PM PDT 24 |
| Finished | Aug 13 06:57:31 PM PDT 24 |
| Peak memory | 575568 kb |
| Host | smart-b2dcb386-4c1a-4f67-86b7-aef3df0a2acb |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3428399684 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 59.xbar_same_source.3428399684 |
| Directory | /workspace/59.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/59.xbar_smoke.1087178279 |
| Short name | T1701 |
| Test name | |
| Test status | |
| Simulation time | 49221407 ps |
| CPU time | 6.41 seconds |
| Started | Aug 13 06:56:05 PM PDT 24 |
| Finished | Aug 13 06:56:11 PM PDT 24 |
| Peak memory | 574232 kb |
| Host | smart-7615e4cf-18af-4e70-87f7-22d0a61b0f0a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1087178279 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 59.xbar_smoke.1087178279 |
| Directory | /workspace/59.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/59.xbar_smoke_large_delays.1491420088 |
| Short name | T2941 |
| Test name | |
| Test status | |
| Simulation time | 7842465590 ps |
| CPU time | 83.18 seconds |
| Started | Aug 13 06:56:02 PM PDT 24 |
| Finished | Aug 13 06:57:25 PM PDT 24 |
| Peak memory | 574328 kb |
| Host | smart-9078eb71-3d94-4a1d-b221-a2beae12e62d |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1491420088 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 59.xbar_smoke_large_delays.1491420088 |
| Directory | /workspace/59.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/59.xbar_smoke_slow_rsp.285204523 |
| Short name | T1468 |
| Test name | |
| Test status | |
| Simulation time | 5641673773 ps |
| CPU time | 94.3 seconds |
| Started | Aug 13 06:56:01 PM PDT 24 |
| Finished | Aug 13 06:57:35 PM PDT 24 |
| Peak memory | 573708 kb |
| Host | smart-bfb326d7-631a-47b9-a7ed-678b7ac45a7c |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=285204523 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 59.xbar_smoke_slow_rsp.285204523 |
| Directory | /workspace/59.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/59.xbar_smoke_zero_delays.1924303812 |
| Short name | T1563 |
| Test name | |
| Test status | |
| Simulation time | 59112534 ps |
| CPU time | 7.05 seconds |
| Started | Aug 13 06:56:03 PM PDT 24 |
| Finished | Aug 13 06:56:10 PM PDT 24 |
| Peak memory | 573512 kb |
| Host | smart-58463c68-8cd2-4a32-b01b-0958c10d2951 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1924303812 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 59.xbar_smoke_zero_delay s.1924303812 |
| Directory | /workspace/59.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/59.xbar_stress_all.4134730662 |
| Short name | T2220 |
| Test name | |
| Test status | |
| Simulation time | 7739597647 ps |
| CPU time | 294.27 seconds |
| Started | Aug 13 06:56:13 PM PDT 24 |
| Finished | Aug 13 07:01:08 PM PDT 24 |
| Peak memory | 575720 kb |
| Host | smart-51769242-f589-4299-a4c7-70506dd0edb0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4134730662 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 59.xbar_stress_all.4134730662 |
| Directory | /workspace/59.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/59.xbar_stress_all_with_error.458298003 |
| Short name | T1578 |
| Test name | |
| Test status | |
| Simulation time | 1104741538 ps |
| CPU time | 82.88 seconds |
| Started | Aug 13 06:56:08 PM PDT 24 |
| Finished | Aug 13 06:57:31 PM PDT 24 |
| Peak memory | 576000 kb |
| Host | smart-dd83438e-4920-41b7-bc3d-54c1bf4d0c6d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=458298003 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 59.xbar_stress_all_with_error.458298003 |
| Directory | /workspace/59.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/59.xbar_stress_all_with_rand_reset.1738092097 |
| Short name | T2353 |
| Test name | |
| Test status | |
| Simulation time | 430506158 ps |
| CPU time | 200.55 seconds |
| Started | Aug 13 06:56:09 PM PDT 24 |
| Finished | Aug 13 06:59:30 PM PDT 24 |
| Peak memory | 575672 kb |
| Host | smart-e2d12d03-2453-42cf-b662-5b1f01c0fa49 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1738092097 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 59.xbar_stress_all _with_rand_reset.1738092097 |
| Directory | /workspace/59.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/59.xbar_stress_all_with_reset_error.1699275303 |
| Short name | T2075 |
| Test name | |
| Test status | |
| Simulation time | 3432644670 ps |
| CPU time | 280.18 seconds |
| Started | Aug 13 06:56:07 PM PDT 24 |
| Finished | Aug 13 07:00:48 PM PDT 24 |
| Peak memory | 575692 kb |
| Host | smart-7f38de0a-964b-426d-9ecc-cc7a32350be0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1699275303 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 59.xbar_stress_al l_with_reset_error.1699275303 |
| Directory | /workspace/59.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/59.xbar_unmapped_addr.3169389632 |
| Short name | T1640 |
| Test name | |
| Test status | |
| Simulation time | 135667341 ps |
| CPU time | 15.26 seconds |
| Started | Aug 13 06:56:09 PM PDT 24 |
| Finished | Aug 13 06:56:24 PM PDT 24 |
| Peak memory | 575568 kb |
| Host | smart-355a4713-0dbb-4f4c-9696-a54fb57ae88d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3169389632 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 59.xbar_unmapped_addr.3169389632 |
| Directory | /workspace/59.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/6.chip_csr_mem_rw_with_rand_reset.1528168512 |
| Short name | T466 |
| Test name | |
| Test status | |
| Simulation time | 9836258426 ps |
| CPU time | 788.72 seconds |
| Started | Aug 13 06:51:01 PM PDT 24 |
| Finished | Aug 13 07:04:10 PM PDT 24 |
| Peak memory | 652604 kb |
| Host | smart-f3795cf9-5db9-4f5a-bce2-d8444d5e0c67 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1528168512 -assert nopostproc + UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top .vdb -cm_log /dev/null -cm_name 6.chip_csr_mem_rw_with_rand_reset.1528168512 |
| Directory | /workspace/6.chip_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/6.chip_csr_rw.1682636367 |
| Short name | T2132 |
| Test name | |
| Test status | |
| Simulation time | 6217900990 ps |
| CPU time | 591.24 seconds |
| Started | Aug 13 06:51:08 PM PDT 24 |
| Finished | Aug 13 07:01:00 PM PDT 24 |
| Peak memory | 598696 kb |
| Host | smart-6f46e2aa-d21c-4499-933f-23b0fb48083c |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1682636367 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.chip_csr_rw.1682636367 |
| Directory | /workspace/6.chip_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/6.chip_same_csr_outstanding.1836831487 |
| Short name | T1536 |
| Test name | |
| Test status | |
| Simulation time | 16707244228 ps |
| CPU time | 1927.49 seconds |
| Started | Aug 13 06:51:02 PM PDT 24 |
| Finished | Aug 13 07:23:10 PM PDT 24 |
| Peak memory | 592920 kb |
| Host | smart-60f0832b-8242-4b9c-9943-700c70dc3db1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +run_same_csr_outstanding +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1836831487 -assert nopostproc +UVM_TE STNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb - cm_log /dev/null -cm_name 6.chip_same_csr_outstanding.1836831487 |
| Directory | /workspace/6.chip_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/6.chip_tl_errors.1594831435 |
| Short name | T2483 |
| Test name | |
| Test status | |
| Simulation time | 4252239120 ps |
| CPU time | 375.39 seconds |
| Started | Aug 13 06:51:00 PM PDT 24 |
| Finished | Aug 13 06:57:16 PM PDT 24 |
| Peak memory | 603376 kb |
| Host | smart-e36575fe-b188-401d-ac65-474919d31ac0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1594831435 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.chip_tl_errors.1594831435 |
| Directory | /workspace/6.chip_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/6.xbar_access_same_device.2324468187 |
| Short name | T2339 |
| Test name | |
| Test status | |
| Simulation time | 1859746172 ps |
| CPU time | 66.85 seconds |
| Started | Aug 13 06:50:53 PM PDT 24 |
| Finished | Aug 13 06:52:00 PM PDT 24 |
| Peak memory | 575712 kb |
| Host | smart-e0e791f6-71c0-4981-874a-ae86c68e777b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2324468187 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.xbar_access_same_device. 2324468187 |
| Directory | /workspace/6.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/6.xbar_access_same_device_slow_rsp.586162823 |
| Short name | T1707 |
| Test name | |
| Test status | |
| Simulation time | 75683944232 ps |
| CPU time | 1168.61 seconds |
| Started | Aug 13 06:51:00 PM PDT 24 |
| Finished | Aug 13 07:10:29 PM PDT 24 |
| Peak memory | 575788 kb |
| Host | smart-60a90252-b64c-4ef1-93d0-eae774840b95 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=586162823 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.xbar_access_same_de vice_slow_rsp.586162823 |
| Directory | /workspace/6.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/6.xbar_error_and_unmapped_addr.432019206 |
| Short name | T1587 |
| Test name | |
| Test status | |
| Simulation time | 756544293 ps |
| CPU time | 29.15 seconds |
| Started | Aug 13 06:50:55 PM PDT 24 |
| Finished | Aug 13 06:51:25 PM PDT 24 |
| Peak memory | 575696 kb |
| Host | smart-8e5562af-af28-409c-8b64-3da004058b47 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=432019206 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.xbar_error_and_unmapped_addr. 432019206 |
| Directory | /workspace/6.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/6.xbar_error_random.3968607233 |
| Short name | T1959 |
| Test name | |
| Test status | |
| Simulation time | 1793922092 ps |
| CPU time | 63.58 seconds |
| Started | Aug 13 06:50:49 PM PDT 24 |
| Finished | Aug 13 06:51:53 PM PDT 24 |
| Peak memory | 575716 kb |
| Host | smart-2252363d-9f0f-424a-a50c-d888ee41b89e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3968607233 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.xbar_error_random.3968607233 |
| Directory | /workspace/6.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/6.xbar_random.1251935585 |
| Short name | T2701 |
| Test name | |
| Test status | |
| Simulation time | 759352603 ps |
| CPU time | 30.13 seconds |
| Started | Aug 13 06:50:55 PM PDT 24 |
| Finished | Aug 13 06:51:26 PM PDT 24 |
| Peak memory | 575516 kb |
| Host | smart-099b1de5-1423-4f8b-b52c-e4c8bbd62bf1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1251935585 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.xbar_random.1251935585 |
| Directory | /workspace/6.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/6.xbar_random_large_delays.282907805 |
| Short name | T2838 |
| Test name | |
| Test status | |
| Simulation time | 31739975042 ps |
| CPU time | 307.58 seconds |
| Started | Aug 13 06:51:01 PM PDT 24 |
| Finished | Aug 13 06:56:09 PM PDT 24 |
| Peak memory | 575612 kb |
| Host | smart-bc2d7c51-6469-4d62-9c9e-3c7b0806378f |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=282907805 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.xbar_random_large_delays.282907805 |
| Directory | /workspace/6.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/6.xbar_random_slow_rsp.1999832394 |
| Short name | T2296 |
| Test name | |
| Test status | |
| Simulation time | 40075763796 ps |
| CPU time | 712.78 seconds |
| Started | Aug 13 06:50:56 PM PDT 24 |
| Finished | Aug 13 07:02:49 PM PDT 24 |
| Peak memory | 575796 kb |
| Host | smart-16d0249e-9e13-40c5-8622-9a59815c3aa0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1999832394 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.xbar_random_slow_rsp.1999832394 |
| Directory | /workspace/6.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/6.xbar_random_zero_delays.4031165984 |
| Short name | T643 |
| Test name | |
| Test status | |
| Simulation time | 506235792 ps |
| CPU time | 40.24 seconds |
| Started | Aug 13 06:50:56 PM PDT 24 |
| Finished | Aug 13 06:51:37 PM PDT 24 |
| Peak memory | 575656 kb |
| Host | smart-e1e8ebf2-0866-4d77-803f-4c6cfef23b46 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4031165984 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.xbar_random_zero_dela ys.4031165984 |
| Directory | /workspace/6.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/6.xbar_same_source.1810999656 |
| Short name | T718 |
| Test name | |
| Test status | |
| Simulation time | 1388132122 ps |
| CPU time | 39.5 seconds |
| Started | Aug 13 06:51:09 PM PDT 24 |
| Finished | Aug 13 06:51:49 PM PDT 24 |
| Peak memory | 575664 kb |
| Host | smart-e4a10857-0810-4514-8abb-ec651c08b764 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1810999656 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.xbar_same_source.1810999656 |
| Directory | /workspace/6.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/6.xbar_smoke.1411753177 |
| Short name | T1448 |
| Test name | |
| Test status | |
| Simulation time | 45449801 ps |
| CPU time | 5.55 seconds |
| Started | Aug 13 06:50:51 PM PDT 24 |
| Finished | Aug 13 06:50:57 PM PDT 24 |
| Peak memory | 573572 kb |
| Host | smart-1584622a-ad73-458b-8bc5-bcdef373f6f0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1411753177 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.xbar_smoke.1411753177 |
| Directory | /workspace/6.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/6.xbar_smoke_large_delays.864298673 |
| Short name | T1777 |
| Test name | |
| Test status | |
| Simulation time | 10271684762 ps |
| CPU time | 99.14 seconds |
| Started | Aug 13 06:50:43 PM PDT 24 |
| Finished | Aug 13 06:52:23 PM PDT 24 |
| Peak memory | 573648 kb |
| Host | smart-3f56b77c-0dbe-4f1f-b476-15b339b62ff7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=864298673 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.xbar_smoke_large_delays.864298673 |
| Directory | /workspace/6.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/6.xbar_smoke_slow_rsp.603674055 |
| Short name | T1980 |
| Test name | |
| Test status | |
| Simulation time | 5081419343 ps |
| CPU time | 80.74 seconds |
| Started | Aug 13 06:50:52 PM PDT 24 |
| Finished | Aug 13 06:52:13 PM PDT 24 |
| Peak memory | 574332 kb |
| Host | smart-275c1a04-2f05-47e2-8d11-69e70833525c |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=603674055 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.xbar_smoke_slow_rsp.603674055 |
| Directory | /workspace/6.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/6.xbar_smoke_zero_delays.3752028377 |
| Short name | T2767 |
| Test name | |
| Test status | |
| Simulation time | 51438659 ps |
| CPU time | 6.19 seconds |
| Started | Aug 13 06:50:54 PM PDT 24 |
| Finished | Aug 13 06:51:01 PM PDT 24 |
| Peak memory | 573588 kb |
| Host | smart-72a681c4-a38b-4c72-9c85-ffb85a4eff9d |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3752028377 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.xbar_smoke_zero_delays .3752028377 |
| Directory | /workspace/6.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/6.xbar_stress_all.1758795364 |
| Short name | T613 |
| Test name | |
| Test status | |
| Simulation time | 1455809487 ps |
| CPU time | 118.74 seconds |
| Started | Aug 13 06:50:57 PM PDT 24 |
| Finished | Aug 13 06:52:56 PM PDT 24 |
| Peak memory | 576412 kb |
| Host | smart-3ce46224-81cf-4d61-b416-2a73fc57642d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1758795364 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.xbar_stress_all.1758795364 |
| Directory | /workspace/6.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/6.xbar_stress_all_with_error.386126579 |
| Short name | T1467 |
| Test name | |
| Test status | |
| Simulation time | 2087423143 ps |
| CPU time | 166.55 seconds |
| Started | Aug 13 06:51:13 PM PDT 24 |
| Finished | Aug 13 06:54:00 PM PDT 24 |
| Peak memory | 576476 kb |
| Host | smart-cd4877e0-506d-4b5d-96e9-533090b54d4a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=386126579 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.xbar_stress_all_with_error.386126579 |
| Directory | /workspace/6.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/6.xbar_stress_all_with_rand_reset.1139243866 |
| Short name | T920 |
| Test name | |
| Test status | |
| Simulation time | 204948419 ps |
| CPU time | 84.29 seconds |
| Started | Aug 13 06:51:01 PM PDT 24 |
| Finished | Aug 13 06:52:26 PM PDT 24 |
| Peak memory | 576416 kb |
| Host | smart-b57f6010-729d-427d-9a5e-0cb9b4ba23c8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1139243866 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.xbar_stress_all_ with_rand_reset.1139243866 |
| Directory | /workspace/6.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/6.xbar_stress_all_with_reset_error.4158072418 |
| Short name | T620 |
| Test name | |
| Test status | |
| Simulation time | 18263298416 ps |
| CPU time | 847.74 seconds |
| Started | Aug 13 06:51:08 PM PDT 24 |
| Finished | Aug 13 07:05:16 PM PDT 24 |
| Peak memory | 576516 kb |
| Host | smart-ce672111-b3f0-4bd3-bd29-79c6614cb43c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4158072418 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.xbar_stress_all _with_reset_error.4158072418 |
| Directory | /workspace/6.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/6.xbar_unmapped_addr.3371071251 |
| Short name | T2531 |
| Test name | |
| Test status | |
| Simulation time | 266886895 ps |
| CPU time | 30.17 seconds |
| Started | Aug 13 06:51:04 PM PDT 24 |
| Finished | Aug 13 06:51:34 PM PDT 24 |
| Peak memory | 575740 kb |
| Host | smart-6023bcc9-d1ff-4cc5-a1d1-cd1258aa0f98 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3371071251 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.xbar_unmapped_addr.3371071251 |
| Directory | /workspace/6.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/60.xbar_access_same_device.2473777305 |
| Short name | T2564 |
| Test name | |
| Test status | |
| Simulation time | 1876669397 ps |
| CPU time | 72.05 seconds |
| Started | Aug 13 06:56:13 PM PDT 24 |
| Finished | Aug 13 06:57:25 PM PDT 24 |
| Peak memory | 576288 kb |
| Host | smart-c6146063-7d39-4fe4-9d96-984b2cd493ac |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2473777305 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 60.xbar_access_same_device .2473777305 |
| Directory | /workspace/60.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/60.xbar_access_same_device_slow_rsp.3601019644 |
| Short name | T1659 |
| Test name | |
| Test status | |
| Simulation time | 15349077400 ps |
| CPU time | 282.92 seconds |
| Started | Aug 13 06:56:13 PM PDT 24 |
| Finished | Aug 13 07:00:56 PM PDT 24 |
| Peak memory | 575740 kb |
| Host | smart-dd83c920-5916-41c0-9b3a-a84aba34760f |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3601019644 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 60.xbar_access_same_ device_slow_rsp.3601019644 |
| Directory | /workspace/60.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/60.xbar_error_and_unmapped_addr.1448695242 |
| Short name | T2272 |
| Test name | |
| Test status | |
| Simulation time | 1297494212 ps |
| CPU time | 50.48 seconds |
| Started | Aug 13 06:56:16 PM PDT 24 |
| Finished | Aug 13 06:57:07 PM PDT 24 |
| Peak memory | 575728 kb |
| Host | smart-b8626d36-57b4-4cb3-bded-fef369326f98 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1448695242 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 60.xbar_error_and_unmapped_add r.1448695242 |
| Directory | /workspace/60.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/60.xbar_error_random.3591168853 |
| Short name | T1533 |
| Test name | |
| Test status | |
| Simulation time | 225246285 ps |
| CPU time | 18.04 seconds |
| Started | Aug 13 06:56:13 PM PDT 24 |
| Finished | Aug 13 06:56:31 PM PDT 24 |
| Peak memory | 575612 kb |
| Host | smart-d4a1359a-cb47-41ed-b60d-23c632b0bd0f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3591168853 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 60.xbar_error_random.3591168853 |
| Directory | /workspace/60.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/60.xbar_random.2385534216 |
| Short name | T1620 |
| Test name | |
| Test status | |
| Simulation time | 288346464 ps |
| CPU time | 22.95 seconds |
| Started | Aug 13 06:56:11 PM PDT 24 |
| Finished | Aug 13 06:56:34 PM PDT 24 |
| Peak memory | 575480 kb |
| Host | smart-76250c9a-1c09-4443-ba2a-edde443c4834 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2385534216 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 60.xbar_random.2385534216 |
| Directory | /workspace/60.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/60.xbar_random_large_delays.2826333169 |
| Short name | T673 |
| Test name | |
| Test status | |
| Simulation time | 56751164357 ps |
| CPU time | 572.86 seconds |
| Started | Aug 13 06:56:09 PM PDT 24 |
| Finished | Aug 13 07:05:43 PM PDT 24 |
| Peak memory | 575724 kb |
| Host | smart-bbfbc237-8ebf-4d2d-a6a8-f3c82d7c2901 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2826333169 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 60.xbar_random_large_delays.2826333169 |
| Directory | /workspace/60.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/60.xbar_random_slow_rsp.4290984757 |
| Short name | T2656 |
| Test name | |
| Test status | |
| Simulation time | 54975923603 ps |
| CPU time | 930.91 seconds |
| Started | Aug 13 06:56:10 PM PDT 24 |
| Finished | Aug 13 07:11:41 PM PDT 24 |
| Peak memory | 575732 kb |
| Host | smart-a45db189-96a8-4950-a409-f534a0306795 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4290984757 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 60.xbar_random_slow_rsp.4290984757 |
| Directory | /workspace/60.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/60.xbar_random_zero_delays.3441919173 |
| Short name | T2396 |
| Test name | |
| Test status | |
| Simulation time | 251994823 ps |
| CPU time | 22 seconds |
| Started | Aug 13 06:56:12 PM PDT 24 |
| Finished | Aug 13 06:56:34 PM PDT 24 |
| Peak memory | 575680 kb |
| Host | smart-6230855b-3260-470e-9004-c12ba203c4c1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3441919173 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 60.xbar_random_zero_del ays.3441919173 |
| Directory | /workspace/60.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/60.xbar_same_source.2730968192 |
| Short name | T2113 |
| Test name | |
| Test status | |
| Simulation time | 1890513045 ps |
| CPU time | 58.6 seconds |
| Started | Aug 13 06:56:10 PM PDT 24 |
| Finished | Aug 13 06:57:09 PM PDT 24 |
| Peak memory | 575604 kb |
| Host | smart-693443da-7993-4f17-8d0b-ec48ff16b56b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2730968192 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 60.xbar_same_source.2730968192 |
| Directory | /workspace/60.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/60.xbar_smoke.479524524 |
| Short name | T1809 |
| Test name | |
| Test status | |
| Simulation time | 166663439 ps |
| CPU time | 8.61 seconds |
| Started | Aug 13 06:56:10 PM PDT 24 |
| Finished | Aug 13 06:56:19 PM PDT 24 |
| Peak memory | 573576 kb |
| Host | smart-782c3b59-faef-4571-a0be-a560ed426900 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=479524524 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 60.xbar_smoke.479524524 |
| Directory | /workspace/60.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/60.xbar_smoke_large_delays.1061104637 |
| Short name | T1783 |
| Test name | |
| Test status | |
| Simulation time | 7500175176 ps |
| CPU time | 79.14 seconds |
| Started | Aug 13 06:56:11 PM PDT 24 |
| Finished | Aug 13 06:57:30 PM PDT 24 |
| Peak memory | 574308 kb |
| Host | smart-688135b8-72a1-45a0-b7ab-78cb5da0878a |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1061104637 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 60.xbar_smoke_large_delays.1061104637 |
| Directory | /workspace/60.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/60.xbar_smoke_slow_rsp.117846466 |
| Short name | T2643 |
| Test name | |
| Test status | |
| Simulation time | 6016820989 ps |
| CPU time | 95.81 seconds |
| Started | Aug 13 06:56:10 PM PDT 24 |
| Finished | Aug 13 06:57:46 PM PDT 24 |
| Peak memory | 573676 kb |
| Host | smart-50c142ba-25de-46c2-8e6f-a0bae8863c1b |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=117846466 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 60.xbar_smoke_slow_rsp.117846466 |
| Directory | /workspace/60.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/60.xbar_smoke_zero_delays.3008368782 |
| Short name | T2215 |
| Test name | |
| Test status | |
| Simulation time | 41554072 ps |
| CPU time | 6.3 seconds |
| Started | Aug 13 06:56:10 PM PDT 24 |
| Finished | Aug 13 06:56:16 PM PDT 24 |
| Peak memory | 573596 kb |
| Host | smart-25bcc88e-1e62-4e04-9b80-f2199dfc4a79 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3008368782 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 60.xbar_smoke_zero_delay s.3008368782 |
| Directory | /workspace/60.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/60.xbar_stress_all.3203097294 |
| Short name | T470 |
| Test name | |
| Test status | |
| Simulation time | 10462787046 ps |
| CPU time | 388.45 seconds |
| Started | Aug 13 06:56:16 PM PDT 24 |
| Finished | Aug 13 07:02:44 PM PDT 24 |
| Peak memory | 576568 kb |
| Host | smart-267c77fa-7b5c-4d01-a57d-fe2feaaca2c4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3203097294 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 60.xbar_stress_all.3203097294 |
| Directory | /workspace/60.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/60.xbar_stress_all_with_error.805515883 |
| Short name | T2928 |
| Test name | |
| Test status | |
| Simulation time | 1321176495 ps |
| CPU time | 55.16 seconds |
| Started | Aug 13 06:56:15 PM PDT 24 |
| Finished | Aug 13 06:57:11 PM PDT 24 |
| Peak memory | 575716 kb |
| Host | smart-c649708f-d56d-425d-93c0-8b2df92c869f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=805515883 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 60.xbar_stress_all_with_error.805515883 |
| Directory | /workspace/60.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/60.xbar_stress_all_with_rand_reset.3592859986 |
| Short name | T2027 |
| Test name | |
| Test status | |
| Simulation time | 10637649436 ps |
| CPU time | 664.84 seconds |
| Started | Aug 13 06:56:17 PM PDT 24 |
| Finished | Aug 13 07:07:23 PM PDT 24 |
| Peak memory | 576516 kb |
| Host | smart-aaf6d596-e655-44ab-a43a-b1599ec0d231 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3592859986 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 60.xbar_stress_all _with_rand_reset.3592859986 |
| Directory | /workspace/60.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/60.xbar_stress_all_with_reset_error.1771091199 |
| Short name | T1879 |
| Test name | |
| Test status | |
| Simulation time | 2669408127 ps |
| CPU time | 245.97 seconds |
| Started | Aug 13 06:56:15 PM PDT 24 |
| Finished | Aug 13 07:00:21 PM PDT 24 |
| Peak memory | 576492 kb |
| Host | smart-7474e176-fe7e-4a12-abee-db849c7bfc5c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1771091199 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 60.xbar_stress_al l_with_reset_error.1771091199 |
| Directory | /workspace/60.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/60.xbar_unmapped_addr.2470939000 |
| Short name | T2446 |
| Test name | |
| Test status | |
| Simulation time | 735031619 ps |
| CPU time | 29.68 seconds |
| Started | Aug 13 06:56:29 PM PDT 24 |
| Finished | Aug 13 06:56:59 PM PDT 24 |
| Peak memory | 575464 kb |
| Host | smart-79fec18d-cee3-45bc-a310-98c125428c00 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2470939000 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 60.xbar_unmapped_addr.2470939000 |
| Directory | /workspace/60.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/61.xbar_access_same_device.955620894 |
| Short name | T2593 |
| Test name | |
| Test status | |
| Simulation time | 799096702 ps |
| CPU time | 37.81 seconds |
| Started | Aug 13 06:56:19 PM PDT 24 |
| Finished | Aug 13 06:56:56 PM PDT 24 |
| Peak memory | 575700 kb |
| Host | smart-593ba352-ab24-49d9-8a2c-f5d155388847 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=955620894 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 61.xbar_access_same_device. 955620894 |
| Directory | /workspace/61.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/61.xbar_access_same_device_slow_rsp.425579468 |
| Short name | T2699 |
| Test name | |
| Test status | |
| Simulation time | 19630486962 ps |
| CPU time | 344.38 seconds |
| Started | Aug 13 06:56:24 PM PDT 24 |
| Finished | Aug 13 07:02:09 PM PDT 24 |
| Peak memory | 575688 kb |
| Host | smart-708da1fd-ae1e-4a37-a383-c9bee946c0bf |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=425579468 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 61.xbar_access_same_d evice_slow_rsp.425579468 |
| Directory | /workspace/61.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/61.xbar_error_and_unmapped_addr.545457972 |
| Short name | T2542 |
| Test name | |
| Test status | |
| Simulation time | 685604952 ps |
| CPU time | 24.3 seconds |
| Started | Aug 13 06:56:14 PM PDT 24 |
| Finished | Aug 13 06:56:38 PM PDT 24 |
| Peak memory | 575684 kb |
| Host | smart-c2619b73-2f59-4fe8-8a0b-3fd7cece39c7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=545457972 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 61.xbar_error_and_unmapped_addr .545457972 |
| Directory | /workspace/61.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/61.xbar_error_random.2163958298 |
| Short name | T1636 |
| Test name | |
| Test status | |
| Simulation time | 256892935 ps |
| CPU time | 20.37 seconds |
| Started | Aug 13 06:56:17 PM PDT 24 |
| Finished | Aug 13 06:56:38 PM PDT 24 |
| Peak memory | 575720 kb |
| Host | smart-47e19ee2-52aa-49c7-a0b5-6accc2c6b83e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2163958298 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 61.xbar_error_random.2163958298 |
| Directory | /workspace/61.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/61.xbar_random.2508101030 |
| Short name | T2925 |
| Test name | |
| Test status | |
| Simulation time | 770720947 ps |
| CPU time | 28.94 seconds |
| Started | Aug 13 06:56:18 PM PDT 24 |
| Finished | Aug 13 06:56:47 PM PDT 24 |
| Peak memory | 575696 kb |
| Host | smart-6cbcd2f4-a8b1-4d99-84ae-e3041da4e425 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2508101030 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 61.xbar_random.2508101030 |
| Directory | /workspace/61.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/61.xbar_random_large_delays.3526974149 |
| Short name | T2615 |
| Test name | |
| Test status | |
| Simulation time | 102593646273 ps |
| CPU time | 1164.64 seconds |
| Started | Aug 13 06:56:25 PM PDT 24 |
| Finished | Aug 13 07:15:50 PM PDT 24 |
| Peak memory | 575672 kb |
| Host | smart-291dc184-fe13-4a9a-8835-d3e774064b9d |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3526974149 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 61.xbar_random_large_delays.3526974149 |
| Directory | /workspace/61.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/61.xbar_random_slow_rsp.2247256496 |
| Short name | T2202 |
| Test name | |
| Test status | |
| Simulation time | 20385560176 ps |
| CPU time | 329.6 seconds |
| Started | Aug 13 06:56:14 PM PDT 24 |
| Finished | Aug 13 07:01:44 PM PDT 24 |
| Peak memory | 575724 kb |
| Host | smart-8648d6da-db74-4948-9b47-fa3aad4eed15 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2247256496 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 61.xbar_random_slow_rsp.2247256496 |
| Directory | /workspace/61.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/61.xbar_random_zero_delays.1304276735 |
| Short name | T2818 |
| Test name | |
| Test status | |
| Simulation time | 344756422 ps |
| CPU time | 28.22 seconds |
| Started | Aug 13 06:56:19 PM PDT 24 |
| Finished | Aug 13 06:56:48 PM PDT 24 |
| Peak memory | 575596 kb |
| Host | smart-0b93c405-6d94-4f61-917d-9a29f0ef152c |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1304276735 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 61.xbar_random_zero_del ays.1304276735 |
| Directory | /workspace/61.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/61.xbar_same_source.617229374 |
| Short name | T649 |
| Test name | |
| Test status | |
| Simulation time | 2164766642 ps |
| CPU time | 69.35 seconds |
| Started | Aug 13 06:56:16 PM PDT 24 |
| Finished | Aug 13 06:57:26 PM PDT 24 |
| Peak memory | 575728 kb |
| Host | smart-e71cffa7-4912-423f-87bb-348b081c2b11 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=617229374 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 61.xbar_same_source.617229374 |
| Directory | /workspace/61.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/61.xbar_smoke.896950123 |
| Short name | T2259 |
| Test name | |
| Test status | |
| Simulation time | 41478592 ps |
| CPU time | 5.91 seconds |
| Started | Aug 13 06:56:26 PM PDT 24 |
| Finished | Aug 13 06:56:32 PM PDT 24 |
| Peak memory | 573560 kb |
| Host | smart-6a297aa6-af9c-4119-a99c-588f4b0c1e5c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=896950123 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 61.xbar_smoke.896950123 |
| Directory | /workspace/61.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/61.xbar_smoke_large_delays.3694927319 |
| Short name | T2444 |
| Test name | |
| Test status | |
| Simulation time | 9682548677 ps |
| CPU time | 106.3 seconds |
| Started | Aug 13 06:56:18 PM PDT 24 |
| Finished | Aug 13 06:58:05 PM PDT 24 |
| Peak memory | 574328 kb |
| Host | smart-0fee3548-1bcf-484c-85d9-f9d6c0b54bb8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3694927319 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 61.xbar_smoke_large_delays.3694927319 |
| Directory | /workspace/61.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/61.xbar_smoke_slow_rsp.2525349911 |
| Short name | T2280 |
| Test name | |
| Test status | |
| Simulation time | 4241014931 ps |
| CPU time | 71.58 seconds |
| Started | Aug 13 06:56:20 PM PDT 24 |
| Finished | Aug 13 06:57:32 PM PDT 24 |
| Peak memory | 573616 kb |
| Host | smart-c8a18518-79d3-40fb-92dc-60c26e8eabe5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2525349911 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 61.xbar_smoke_slow_rsp.2525349911 |
| Directory | /workspace/61.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/61.xbar_smoke_zero_delays.966986799 |
| Short name | T2125 |
| Test name | |
| Test status | |
| Simulation time | 41579463 ps |
| CPU time | 6.25 seconds |
| Started | Aug 13 06:56:25 PM PDT 24 |
| Finished | Aug 13 06:56:32 PM PDT 24 |
| Peak memory | 573612 kb |
| Host | smart-f4b0ab2d-28bc-4237-bb3b-b4379d622cab |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=966986799 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 61.xbar_smoke_zero_delays .966986799 |
| Directory | /workspace/61.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/61.xbar_stress_all.1272681610 |
| Short name | T2038 |
| Test name | |
| Test status | |
| Simulation time | 6264914329 ps |
| CPU time | 241.11 seconds |
| Started | Aug 13 06:56:31 PM PDT 24 |
| Finished | Aug 13 07:00:32 PM PDT 24 |
| Peak memory | 575708 kb |
| Host | smart-db6df213-dcf9-4be6-87b1-1274291b026b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1272681610 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 61.xbar_stress_all.1272681610 |
| Directory | /workspace/61.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/61.xbar_stress_all_with_error.3746215495 |
| Short name | T2724 |
| Test name | |
| Test status | |
| Simulation time | 3283754819 ps |
| CPU time | 249.82 seconds |
| Started | Aug 13 06:56:27 PM PDT 24 |
| Finished | Aug 13 07:00:37 PM PDT 24 |
| Peak memory | 576384 kb |
| Host | smart-7699d0d2-6c56-4af7-9964-79ac79988082 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3746215495 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 61.xbar_stress_all_with_error.3746215495 |
| Directory | /workspace/61.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/61.xbar_stress_all_with_rand_reset.2821348195 |
| Short name | T501 |
| Test name | |
| Test status | |
| Simulation time | 480787285 ps |
| CPU time | 213.42 seconds |
| Started | Aug 13 06:56:26 PM PDT 24 |
| Finished | Aug 13 07:00:00 PM PDT 24 |
| Peak memory | 576488 kb |
| Host | smart-6f815d25-70de-453d-ae3e-12749939e423 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2821348195 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 61.xbar_stress_all _with_rand_reset.2821348195 |
| Directory | /workspace/61.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/61.xbar_stress_all_with_reset_error.3225771546 |
| Short name | T2118 |
| Test name | |
| Test status | |
| Simulation time | 2194007081 ps |
| CPU time | 291.62 seconds |
| Started | Aug 13 06:56:27 PM PDT 24 |
| Finished | Aug 13 07:01:18 PM PDT 24 |
| Peak memory | 576524 kb |
| Host | smart-a6e9c99b-684d-4f8b-aedb-1381bd5b40ce |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3225771546 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 61.xbar_stress_al l_with_reset_error.3225771546 |
| Directory | /workspace/61.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/61.xbar_unmapped_addr.1336277613 |
| Short name | T2720 |
| Test name | |
| Test status | |
| Simulation time | 18168354 ps |
| CPU time | 5.51 seconds |
| Started | Aug 13 06:56:26 PM PDT 24 |
| Finished | Aug 13 06:56:32 PM PDT 24 |
| Peak memory | 573600 kb |
| Host | smart-341aa639-5039-4fcb-b639-0488105d0167 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1336277613 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 61.xbar_unmapped_addr.1336277613 |
| Directory | /workspace/61.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/62.xbar_access_same_device.2731236040 |
| Short name | T2203 |
| Test name | |
| Test status | |
| Simulation time | 615407346 ps |
| CPU time | 65.37 seconds |
| Started | Aug 13 06:56:25 PM PDT 24 |
| Finished | Aug 13 06:57:31 PM PDT 24 |
| Peak memory | 575704 kb |
| Host | smart-09d13dae-c022-4266-a857-d6d7a1a84677 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2731236040 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 62.xbar_access_same_device .2731236040 |
| Directory | /workspace/62.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/62.xbar_access_same_device_slow_rsp.366809538 |
| Short name | T2532 |
| Test name | |
| Test status | |
| Simulation time | 66334645759 ps |
| CPU time | 1206.62 seconds |
| Started | Aug 13 06:56:31 PM PDT 24 |
| Finished | Aug 13 07:16:38 PM PDT 24 |
| Peak memory | 575660 kb |
| Host | smart-fd7ddd7c-3412-4df5-b7fd-62477942d270 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=366809538 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 62.xbar_access_same_d evice_slow_rsp.366809538 |
| Directory | /workspace/62.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/62.xbar_error_and_unmapped_addr.1665149155 |
| Short name | T1489 |
| Test name | |
| Test status | |
| Simulation time | 41692745 ps |
| CPU time | 7.23 seconds |
| Started | Aug 13 06:56:33 PM PDT 24 |
| Finished | Aug 13 06:56:40 PM PDT 24 |
| Peak memory | 574244 kb |
| Host | smart-022cd3aa-d747-4cae-911c-9e45372574e9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1665149155 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 62.xbar_error_and_unmapped_add r.1665149155 |
| Directory | /workspace/62.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/62.xbar_error_random.4117104174 |
| Short name | T1930 |
| Test name | |
| Test status | |
| Simulation time | 566600611 ps |
| CPU time | 19.63 seconds |
| Started | Aug 13 06:56:30 PM PDT 24 |
| Finished | Aug 13 06:56:50 PM PDT 24 |
| Peak memory | 575364 kb |
| Host | smart-d833bb57-896b-45e2-a356-6865bedde2e1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4117104174 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 62.xbar_error_random.4117104174 |
| Directory | /workspace/62.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/62.xbar_random.2927303213 |
| Short name | T2578 |
| Test name | |
| Test status | |
| Simulation time | 271523936 ps |
| CPU time | 24.53 seconds |
| Started | Aug 13 06:56:25 PM PDT 24 |
| Finished | Aug 13 06:56:50 PM PDT 24 |
| Peak memory | 575740 kb |
| Host | smart-be883137-141f-415f-8f99-fef4e7caa8b0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2927303213 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 62.xbar_random.2927303213 |
| Directory | /workspace/62.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/62.xbar_random_large_delays.3403602762 |
| Short name | T2057 |
| Test name | |
| Test status | |
| Simulation time | 2922009434 ps |
| CPU time | 30.78 seconds |
| Started | Aug 13 06:56:28 PM PDT 24 |
| Finished | Aug 13 06:57:00 PM PDT 24 |
| Peak memory | 573624 kb |
| Host | smart-2578f0a5-11f2-409e-b5bc-e0ef4471b744 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3403602762 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 62.xbar_random_large_delays.3403602762 |
| Directory | /workspace/62.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/62.xbar_random_slow_rsp.3154729829 |
| Short name | T711 |
| Test name | |
| Test status | |
| Simulation time | 69602912344 ps |
| CPU time | 1231.42 seconds |
| Started | Aug 13 06:56:30 PM PDT 24 |
| Finished | Aug 13 07:17:02 PM PDT 24 |
| Peak memory | 575672 kb |
| Host | smart-267cdea8-ecc6-40b3-b00c-72cdd5e5e5dc |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3154729829 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 62.xbar_random_slow_rsp.3154729829 |
| Directory | /workspace/62.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/62.xbar_random_zero_delays.220027603 |
| Short name | T584 |
| Test name | |
| Test status | |
| Simulation time | 413765548 ps |
| CPU time | 31.12 seconds |
| Started | Aug 13 06:56:26 PM PDT 24 |
| Finished | Aug 13 06:56:57 PM PDT 24 |
| Peak memory | 575660 kb |
| Host | smart-d7c68e29-1b1d-4f66-a663-6a8490e568e9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=220027603 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 62.xbar_random_zero_dela ys.220027603 |
| Directory | /workspace/62.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/62.xbar_same_source.2218875984 |
| Short name | T2471 |
| Test name | |
| Test status | |
| Simulation time | 162974073 ps |
| CPU time | 14.02 seconds |
| Started | Aug 13 06:56:25 PM PDT 24 |
| Finished | Aug 13 06:56:39 PM PDT 24 |
| Peak memory | 575632 kb |
| Host | smart-27bff0d3-08f9-4836-8f49-9a9cd4de8176 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2218875984 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 62.xbar_same_source.2218875984 |
| Directory | /workspace/62.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/62.xbar_smoke.1250708105 |
| Short name | T1540 |
| Test name | |
| Test status | |
| Simulation time | 46961432 ps |
| CPU time | 6.19 seconds |
| Started | Aug 13 06:56:28 PM PDT 24 |
| Finished | Aug 13 06:56:34 PM PDT 24 |
| Peak memory | 574228 kb |
| Host | smart-6bbb8c7d-a358-48ad-a352-cf1ffd00503e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1250708105 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 62.xbar_smoke.1250708105 |
| Directory | /workspace/62.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/62.xbar_smoke_large_delays.2770048500 |
| Short name | T1560 |
| Test name | |
| Test status | |
| Simulation time | 9837464960 ps |
| CPU time | 99.68 seconds |
| Started | Aug 13 06:56:28 PM PDT 24 |
| Finished | Aug 13 06:58:08 PM PDT 24 |
| Peak memory | 574328 kb |
| Host | smart-097d0cbe-a773-483e-b211-fc9aa9475990 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2770048500 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 62.xbar_smoke_large_delays.2770048500 |
| Directory | /workspace/62.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/62.xbar_smoke_slow_rsp.3848556665 |
| Short name | T1651 |
| Test name | |
| Test status | |
| Simulation time | 5988125255 ps |
| CPU time | 94.63 seconds |
| Started | Aug 13 06:56:27 PM PDT 24 |
| Finished | Aug 13 06:58:02 PM PDT 24 |
| Peak memory | 573704 kb |
| Host | smart-99360709-8797-4659-a1b9-d84dc954f915 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3848556665 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 62.xbar_smoke_slow_rsp.3848556665 |
| Directory | /workspace/62.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/62.xbar_smoke_zero_delays.561330611 |
| Short name | T709 |
| Test name | |
| Test status | |
| Simulation time | 40431360 ps |
| CPU time | 6.04 seconds |
| Started | Aug 13 06:56:30 PM PDT 24 |
| Finished | Aug 13 06:56:36 PM PDT 24 |
| Peak memory | 573492 kb |
| Host | smart-ca7a51c6-bcaa-435b-9590-1936d74d795a |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=561330611 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 62.xbar_smoke_zero_delays .561330611 |
| Directory | /workspace/62.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/62.xbar_stress_all.3212329727 |
| Short name | T577 |
| Test name | |
| Test status | |
| Simulation time | 3645753084 ps |
| CPU time | 288.83 seconds |
| Started | Aug 13 06:56:36 PM PDT 24 |
| Finished | Aug 13 07:01:24 PM PDT 24 |
| Peak memory | 576576 kb |
| Host | smart-2d7c2c3c-759a-48a0-a91f-38f5311dbd84 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3212329727 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 62.xbar_stress_all.3212329727 |
| Directory | /workspace/62.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/62.xbar_stress_all_with_error.1309233880 |
| Short name | T1933 |
| Test name | |
| Test status | |
| Simulation time | 4239578530 ps |
| CPU time | 154.52 seconds |
| Started | Aug 13 06:56:35 PM PDT 24 |
| Finished | Aug 13 06:59:10 PM PDT 24 |
| Peak memory | 575832 kb |
| Host | smart-b8e435d4-5d83-457a-ac91-49c1d125fc2c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1309233880 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 62.xbar_stress_all_with_error.1309233880 |
| Directory | /workspace/62.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/62.xbar_stress_all_with_rand_reset.2048949626 |
| Short name | T906 |
| Test name | |
| Test status | |
| Simulation time | 562516742 ps |
| CPU time | 258.07 seconds |
| Started | Aug 13 06:56:35 PM PDT 24 |
| Finished | Aug 13 07:00:53 PM PDT 24 |
| Peak memory | 576516 kb |
| Host | smart-d352fbf5-b2ad-49f0-abb2-8fd1d7f2553f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2048949626 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 62.xbar_stress_all _with_rand_reset.2048949626 |
| Directory | /workspace/62.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/62.xbar_stress_all_with_reset_error.809746819 |
| Short name | T2470 |
| Test name | |
| Test status | |
| Simulation time | 17988750101 ps |
| CPU time | 878.07 seconds |
| Started | Aug 13 06:56:31 PM PDT 24 |
| Finished | Aug 13 07:11:09 PM PDT 24 |
| Peak memory | 576584 kb |
| Host | smart-e0ca9b59-5419-4275-997c-db8b300bb331 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=809746819 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 62.xbar_stress_all _with_reset_error.809746819 |
| Directory | /workspace/62.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/62.xbar_unmapped_addr.1456645684 |
| Short name | T2786 |
| Test name | |
| Test status | |
| Simulation time | 253730759 ps |
| CPU time | 29.6 seconds |
| Started | Aug 13 06:56:27 PM PDT 24 |
| Finished | Aug 13 06:56:56 PM PDT 24 |
| Peak memory | 575548 kb |
| Host | smart-e65083f2-6b4b-4bb3-8e28-901ceb92d013 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1456645684 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 62.xbar_unmapped_addr.1456645684 |
| Directory | /workspace/62.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/63.xbar_access_same_device.4058685263 |
| Short name | T1909 |
| Test name | |
| Test status | |
| Simulation time | 2460426485 ps |
| CPU time | 99.53 seconds |
| Started | Aug 13 06:56:40 PM PDT 24 |
| Finished | Aug 13 06:58:20 PM PDT 24 |
| Peak memory | 575624 kb |
| Host | smart-a574bc95-1bd9-412a-a3fb-ee6d6173930f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4058685263 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 63.xbar_access_same_device .4058685263 |
| Directory | /workspace/63.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/63.xbar_access_same_device_slow_rsp.2170982462 |
| Short name | T1821 |
| Test name | |
| Test status | |
| Simulation time | 81996351010 ps |
| CPU time | 1466 seconds |
| Started | Aug 13 06:56:37 PM PDT 24 |
| Finished | Aug 13 07:21:03 PM PDT 24 |
| Peak memory | 575568 kb |
| Host | smart-c9db7467-7a15-4a9e-998e-80545d95bed3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2170982462 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 63.xbar_access_same_ device_slow_rsp.2170982462 |
| Directory | /workspace/63.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/63.xbar_error_and_unmapped_addr.977182288 |
| Short name | T1480 |
| Test name | |
| Test status | |
| Simulation time | 250805427 ps |
| CPU time | 26.06 seconds |
| Started | Aug 13 06:56:37 PM PDT 24 |
| Finished | Aug 13 06:57:03 PM PDT 24 |
| Peak memory | 575640 kb |
| Host | smart-3f9e9f67-a8e7-4905-82bd-912878fbc746 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=977182288 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 63.xbar_error_and_unmapped_addr .977182288 |
| Directory | /workspace/63.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/63.xbar_error_random.2372284165 |
| Short name | T563 |
| Test name | |
| Test status | |
| Simulation time | 634322268 ps |
| CPU time | 20.87 seconds |
| Started | Aug 13 06:56:38 PM PDT 24 |
| Finished | Aug 13 06:56:59 PM PDT 24 |
| Peak memory | 575440 kb |
| Host | smart-bbca9e57-ea5e-4169-9997-8aa7dafe0db2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2372284165 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 63.xbar_error_random.2372284165 |
| Directory | /workspace/63.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/63.xbar_random.1664904457 |
| Short name | T2586 |
| Test name | |
| Test status | |
| Simulation time | 209289216 ps |
| CPU time | 21.74 seconds |
| Started | Aug 13 06:56:32 PM PDT 24 |
| Finished | Aug 13 06:56:54 PM PDT 24 |
| Peak memory | 575488 kb |
| Host | smart-04cc3ec9-4178-4d42-a9bf-c22136c5f16d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1664904457 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 63.xbar_random.1664904457 |
| Directory | /workspace/63.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/63.xbar_random_large_delays.2379483821 |
| Short name | T2391 |
| Test name | |
| Test status | |
| Simulation time | 63403306214 ps |
| CPU time | 747.97 seconds |
| Started | Aug 13 06:56:40 PM PDT 24 |
| Finished | Aug 13 07:09:08 PM PDT 24 |
| Peak memory | 575492 kb |
| Host | smart-08493c70-393d-49a0-bbfa-de53515411a5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2379483821 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 63.xbar_random_large_delays.2379483821 |
| Directory | /workspace/63.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/63.xbar_random_slow_rsp.1095614051 |
| Short name | T2204 |
| Test name | |
| Test status | |
| Simulation time | 2664330258 ps |
| CPU time | 42.36 seconds |
| Started | Aug 13 06:56:40 PM PDT 24 |
| Finished | Aug 13 06:57:22 PM PDT 24 |
| Peak memory | 574280 kb |
| Host | smart-f98aaf52-c25b-48ab-8333-8787b4748355 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1095614051 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 63.xbar_random_slow_rsp.1095614051 |
| Directory | /workspace/63.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/63.xbar_random_zero_delays.1198720157 |
| Short name | T2711 |
| Test name | |
| Test status | |
| Simulation time | 259611600 ps |
| CPU time | 25.71 seconds |
| Started | Aug 13 06:56:33 PM PDT 24 |
| Finished | Aug 13 06:56:59 PM PDT 24 |
| Peak memory | 575444 kb |
| Host | smart-3c58244a-2a27-457f-a8b0-57d7aed49dc3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1198720157 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 63.xbar_random_zero_del ays.1198720157 |
| Directory | /workspace/63.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/63.xbar_same_source.1246615247 |
| Short name | T2033 |
| Test name | |
| Test status | |
| Simulation time | 944704947 ps |
| CPU time | 24.41 seconds |
| Started | Aug 13 06:56:36 PM PDT 24 |
| Finished | Aug 13 06:57:01 PM PDT 24 |
| Peak memory | 575408 kb |
| Host | smart-294229b1-a5dd-41e4-abf1-3cd79bf6da0e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1246615247 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 63.xbar_same_source.1246615247 |
| Directory | /workspace/63.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/63.xbar_smoke.257247950 |
| Short name | T1730 |
| Test name | |
| Test status | |
| Simulation time | 46640228 ps |
| CPU time | 6.27 seconds |
| Started | Aug 13 06:56:32 PM PDT 24 |
| Finished | Aug 13 06:56:39 PM PDT 24 |
| Peak memory | 574244 kb |
| Host | smart-e7208406-a05e-4dc4-a489-6aaa27cd5d8c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=257247950 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 63.xbar_smoke.257247950 |
| Directory | /workspace/63.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/63.xbar_smoke_large_delays.1192940643 |
| Short name | T2232 |
| Test name | |
| Test status | |
| Simulation time | 10008327987 ps |
| CPU time | 109.65 seconds |
| Started | Aug 13 06:56:31 PM PDT 24 |
| Finished | Aug 13 06:58:21 PM PDT 24 |
| Peak memory | 573608 kb |
| Host | smart-abb987fd-9210-42c3-abb9-b30e2bbd0898 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1192940643 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 63.xbar_smoke_large_delays.1192940643 |
| Directory | /workspace/63.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/63.xbar_smoke_slow_rsp.1854504067 |
| Short name | T2722 |
| Test name | |
| Test status | |
| Simulation time | 5413292933 ps |
| CPU time | 84.2 seconds |
| Started | Aug 13 06:56:34 PM PDT 24 |
| Finished | Aug 13 06:57:59 PM PDT 24 |
| Peak memory | 574348 kb |
| Host | smart-47b586c2-6af9-4a33-8c73-5120abfcab17 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1854504067 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 63.xbar_smoke_slow_rsp.1854504067 |
| Directory | /workspace/63.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/63.xbar_smoke_zero_delays.1523114057 |
| Short name | T2052 |
| Test name | |
| Test status | |
| Simulation time | 50856322 ps |
| CPU time | 6.63 seconds |
| Started | Aug 13 06:56:33 PM PDT 24 |
| Finished | Aug 13 06:56:40 PM PDT 24 |
| Peak memory | 573560 kb |
| Host | smart-d7e4b91e-44e1-4592-9e3c-d430ec9d1348 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1523114057 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 63.xbar_smoke_zero_delay s.1523114057 |
| Directory | /workspace/63.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/63.xbar_stress_all.3952742519 |
| Short name | T2853 |
| Test name | |
| Test status | |
| Simulation time | 3089500933 ps |
| CPU time | 126.35 seconds |
| Started | Aug 13 06:56:37 PM PDT 24 |
| Finished | Aug 13 06:58:44 PM PDT 24 |
| Peak memory | 575844 kb |
| Host | smart-f8bdf28a-485a-4b59-b621-f7b2cae4275f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3952742519 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 63.xbar_stress_all.3952742519 |
| Directory | /workspace/63.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/63.xbar_stress_all_with_error.143604641 |
| Short name | T2177 |
| Test name | |
| Test status | |
| Simulation time | 2323881838 ps |
| CPU time | 167.8 seconds |
| Started | Aug 13 06:56:37 PM PDT 24 |
| Finished | Aug 13 06:59:25 PM PDT 24 |
| Peak memory | 575724 kb |
| Host | smart-53c60259-b62c-409a-89d6-cb5c53848601 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=143604641 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 63.xbar_stress_all_with_error.143604641 |
| Directory | /workspace/63.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/63.xbar_stress_all_with_rand_reset.4095932789 |
| Short name | T1908 |
| Test name | |
| Test status | |
| Simulation time | 48181201 ps |
| CPU time | 20.4 seconds |
| Started | Aug 13 06:56:38 PM PDT 24 |
| Finished | Aug 13 06:56:59 PM PDT 24 |
| Peak memory | 575748 kb |
| Host | smart-026efed5-3b0e-4bb3-8f6a-e68ddbf64d34 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4095932789 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 63.xbar_stress_all _with_rand_reset.4095932789 |
| Directory | /workspace/63.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/63.xbar_stress_all_with_reset_error.2207619903 |
| Short name | T2261 |
| Test name | |
| Test status | |
| Simulation time | 18216088972 ps |
| CPU time | 908.11 seconds |
| Started | Aug 13 06:56:38 PM PDT 24 |
| Finished | Aug 13 07:11:46 PM PDT 24 |
| Peak memory | 575728 kb |
| Host | smart-90071b99-ec3e-4af3-9709-d2cd6d75c2a0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2207619903 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 63.xbar_stress_al l_with_reset_error.2207619903 |
| Directory | /workspace/63.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/63.xbar_unmapped_addr.865339423 |
| Short name | T1723 |
| Test name | |
| Test status | |
| Simulation time | 895310135 ps |
| CPU time | 40.32 seconds |
| Started | Aug 13 06:56:38 PM PDT 24 |
| Finished | Aug 13 06:57:18 PM PDT 24 |
| Peak memory | 575664 kb |
| Host | smart-ee7ebf2c-f6fa-41df-9836-e78e8e419dfc |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=865339423 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 63.xbar_unmapped_addr.865339423 |
| Directory | /workspace/63.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/64.xbar_access_same_device.1480469090 |
| Short name | T1586 |
| Test name | |
| Test status | |
| Simulation time | 244872809 ps |
| CPU time | 27.86 seconds |
| Started | Aug 13 06:56:49 PM PDT 24 |
| Finished | Aug 13 06:57:17 PM PDT 24 |
| Peak memory | 575624 kb |
| Host | smart-8e92aed6-1329-4c68-9510-e7a0b47d2ec0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1480469090 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 64.xbar_access_same_device .1480469090 |
| Directory | /workspace/64.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/64.xbar_access_same_device_slow_rsp.4242079457 |
| Short name | T890 |
| Test name | |
| Test status | |
| Simulation time | 144635275909 ps |
| CPU time | 2682.91 seconds |
| Started | Aug 13 06:56:47 PM PDT 24 |
| Finished | Aug 13 07:41:30 PM PDT 24 |
| Peak memory | 575716 kb |
| Host | smart-5bcd1b4e-2137-4067-8c14-009957c16eed |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4242079457 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 64.xbar_access_same_ device_slow_rsp.4242079457 |
| Directory | /workspace/64.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/64.xbar_error_and_unmapped_addr.42850685 |
| Short name | T1971 |
| Test name | |
| Test status | |
| Simulation time | 149835038 ps |
| CPU time | 9.59 seconds |
| Started | Aug 13 06:56:48 PM PDT 24 |
| Finished | Aug 13 06:56:57 PM PDT 24 |
| Peak memory | 573676 kb |
| Host | smart-75265430-d827-47b6-9fbb-a2b0131d2526 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42850685 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 64.xbar_error_and_unmapped_addr.42850685 |
| Directory | /workspace/64.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/64.xbar_error_random.1143885314 |
| Short name | T2085 |
| Test name | |
| Test status | |
| Simulation time | 230272844 ps |
| CPU time | 19.16 seconds |
| Started | Aug 13 06:56:48 PM PDT 24 |
| Finished | Aug 13 06:57:08 PM PDT 24 |
| Peak memory | 575664 kb |
| Host | smart-62c87656-2fa4-410e-9166-028eef7b1db4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1143885314 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 64.xbar_error_random.1143885314 |
| Directory | /workspace/64.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/64.xbar_random.1127395531 |
| Short name | T2046 |
| Test name | |
| Test status | |
| Simulation time | 226699055 ps |
| CPU time | 11.99 seconds |
| Started | Aug 13 06:56:38 PM PDT 24 |
| Finished | Aug 13 06:56:50 PM PDT 24 |
| Peak memory | 575492 kb |
| Host | smart-3e8c3ebd-5a7c-4d5d-b614-6b0c65d96d8e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1127395531 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 64.xbar_random.1127395531 |
| Directory | /workspace/64.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/64.xbar_random_large_delays.1588875140 |
| Short name | T1633 |
| Test name | |
| Test status | |
| Simulation time | 62848751786 ps |
| CPU time | 732.4 seconds |
| Started | Aug 13 06:56:47 PM PDT 24 |
| Finished | Aug 13 07:08:59 PM PDT 24 |
| Peak memory | 575808 kb |
| Host | smart-35eb8b67-74b0-4026-a36c-e9fdfe88d80c |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1588875140 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 64.xbar_random_large_delays.1588875140 |
| Directory | /workspace/64.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/64.xbar_random_slow_rsp.2343030409 |
| Short name | T525 |
| Test name | |
| Test status | |
| Simulation time | 63810986048 ps |
| CPU time | 1133.31 seconds |
| Started | Aug 13 06:56:47 PM PDT 24 |
| Finished | Aug 13 07:15:41 PM PDT 24 |
| Peak memory | 575648 kb |
| Host | smart-f19d2372-57ba-4546-a231-ee8f108de75f |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2343030409 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 64.xbar_random_slow_rsp.2343030409 |
| Directory | /workspace/64.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/64.xbar_random_zero_delays.2680986307 |
| Short name | T1735 |
| Test name | |
| Test status | |
| Simulation time | 203709520 ps |
| CPU time | 20.56 seconds |
| Started | Aug 13 06:56:47 PM PDT 24 |
| Finished | Aug 13 06:57:08 PM PDT 24 |
| Peak memory | 575484 kb |
| Host | smart-bdd59c31-9564-4a51-8b31-cd18bd4b9420 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2680986307 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 64.xbar_random_zero_del ays.2680986307 |
| Directory | /workspace/64.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/64.xbar_same_source.202744751 |
| Short name | T654 |
| Test name | |
| Test status | |
| Simulation time | 1558247904 ps |
| CPU time | 47.99 seconds |
| Started | Aug 13 06:56:46 PM PDT 24 |
| Finished | Aug 13 06:57:34 PM PDT 24 |
| Peak memory | 575652 kb |
| Host | smart-04f94ba5-1395-4e6c-a96e-dcc607b50f0a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=202744751 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 64.xbar_same_source.202744751 |
| Directory | /workspace/64.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/64.xbar_smoke.75070371 |
| Short name | T2386 |
| Test name | |
| Test status | |
| Simulation time | 39073345 ps |
| CPU time | 5.93 seconds |
| Started | Aug 13 06:56:37 PM PDT 24 |
| Finished | Aug 13 06:56:43 PM PDT 24 |
| Peak memory | 574332 kb |
| Host | smart-c35d7820-c235-475f-a760-719ac0ac8494 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75070371 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 64.xbar_smoke.75070371 |
| Directory | /workspace/64.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/64.xbar_smoke_large_delays.3967502000 |
| Short name | T1625 |
| Test name | |
| Test status | |
| Simulation time | 7580284495 ps |
| CPU time | 74.76 seconds |
| Started | Aug 13 06:56:37 PM PDT 24 |
| Finished | Aug 13 06:57:52 PM PDT 24 |
| Peak memory | 574288 kb |
| Host | smart-46dbceee-14e4-4a05-bce3-8ccd3471454b |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3967502000 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 64.xbar_smoke_large_delays.3967502000 |
| Directory | /workspace/64.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/64.xbar_smoke_slow_rsp.462329435 |
| Short name | T529 |
| Test name | |
| Test status | |
| Simulation time | 4985542543 ps |
| CPU time | 88.74 seconds |
| Started | Aug 13 06:56:39 PM PDT 24 |
| Finished | Aug 13 06:58:08 PM PDT 24 |
| Peak memory | 573636 kb |
| Host | smart-1cacda8e-4cc2-4125-a3d5-7f6081338abf |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=462329435 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 64.xbar_smoke_slow_rsp.462329435 |
| Directory | /workspace/64.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/64.xbar_smoke_zero_delays.1809521086 |
| Short name | T2383 |
| Test name | |
| Test status | |
| Simulation time | 45509301 ps |
| CPU time | 6.87 seconds |
| Started | Aug 13 06:56:38 PM PDT 24 |
| Finished | Aug 13 06:56:45 PM PDT 24 |
| Peak memory | 574156 kb |
| Host | smart-d62334fe-a43c-4e98-bc85-de2e087f6ca7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1809521086 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 64.xbar_smoke_zero_delay s.1809521086 |
| Directory | /workspace/64.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/64.xbar_stress_all.1547522646 |
| Short name | T2367 |
| Test name | |
| Test status | |
| Simulation time | 5384335729 ps |
| CPU time | 181.52 seconds |
| Started | Aug 13 06:56:46 PM PDT 24 |
| Finished | Aug 13 06:59:48 PM PDT 24 |
| Peak memory | 575904 kb |
| Host | smart-9e2e7dc3-4f2e-4ddf-91d9-0cccebdf0336 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1547522646 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 64.xbar_stress_all.1547522646 |
| Directory | /workspace/64.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/64.xbar_stress_all_with_error.3569467218 |
| Short name | T1502 |
| Test name | |
| Test status | |
| Simulation time | 5379875798 ps |
| CPU time | 207.77 seconds |
| Started | Aug 13 06:56:46 PM PDT 24 |
| Finished | Aug 13 07:00:14 PM PDT 24 |
| Peak memory | 575684 kb |
| Host | smart-1aa75c01-f1fc-422c-b3d1-01ac67c95543 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3569467218 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 64.xbar_stress_all_with_error.3569467218 |
| Directory | /workspace/64.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/64.xbar_stress_all_with_rand_reset.451348138 |
| Short name | T2576 |
| Test name | |
| Test status | |
| Simulation time | 9445367139 ps |
| CPU time | 495.1 seconds |
| Started | Aug 13 06:56:46 PM PDT 24 |
| Finished | Aug 13 07:05:01 PM PDT 24 |
| Peak memory | 576532 kb |
| Host | smart-b5a34fa1-8b68-4c3d-b74c-aa0b1a88c314 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=451348138 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_res et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 64.xbar_stress_all_ with_rand_reset.451348138 |
| Directory | /workspace/64.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/64.xbar_stress_all_with_reset_error.3773742394 |
| Short name | T1774 |
| Test name | |
| Test status | |
| Simulation time | 4502533898 ps |
| CPU time | 189.33 seconds |
| Started | Aug 13 06:56:48 PM PDT 24 |
| Finished | Aug 13 06:59:57 PM PDT 24 |
| Peak memory | 575716 kb |
| Host | smart-adf38aa4-b9a4-4426-8cb2-95eb7b762a3d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3773742394 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 64.xbar_stress_al l_with_reset_error.3773742394 |
| Directory | /workspace/64.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/64.xbar_unmapped_addr.3076059294 |
| Short name | T652 |
| Test name | |
| Test status | |
| Simulation time | 901317109 ps |
| CPU time | 38.78 seconds |
| Started | Aug 13 06:56:45 PM PDT 24 |
| Finished | Aug 13 06:57:24 PM PDT 24 |
| Peak memory | 575708 kb |
| Host | smart-2af624e5-c51b-4ea8-b9ef-8fd317c1cc2d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3076059294 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 64.xbar_unmapped_addr.3076059294 |
| Directory | /workspace/64.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/65.xbar_access_same_device.2086151962 |
| Short name | T2243 |
| Test name | |
| Test status | |
| Simulation time | 919358988 ps |
| CPU time | 36.72 seconds |
| Started | Aug 13 06:56:52 PM PDT 24 |
| Finished | Aug 13 06:57:29 PM PDT 24 |
| Peak memory | 576368 kb |
| Host | smart-9fc48c74-05c7-4e52-babb-21747bdf40d9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2086151962 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 65.xbar_access_same_device .2086151962 |
| Directory | /workspace/65.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/65.xbar_access_same_device_slow_rsp.3334961789 |
| Short name | T2735 |
| Test name | |
| Test status | |
| Simulation time | 75870169837 ps |
| CPU time | 1306.38 seconds |
| Started | Aug 13 06:56:53 PM PDT 24 |
| Finished | Aug 13 07:18:39 PM PDT 24 |
| Peak memory | 575752 kb |
| Host | smart-ef652e20-b80d-41eb-b312-c84e93e5d96f |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3334961789 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 65.xbar_access_same_ device_slow_rsp.3334961789 |
| Directory | /workspace/65.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/65.xbar_error_and_unmapped_addr.2726395590 |
| Short name | T2894 |
| Test name | |
| Test status | |
| Simulation time | 178120433 ps |
| CPU time | 19.29 seconds |
| Started | Aug 13 06:56:54 PM PDT 24 |
| Finished | Aug 13 06:57:13 PM PDT 24 |
| Peak memory | 575696 kb |
| Host | smart-638bf241-bff6-479b-aec5-a03a6c3c4c71 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2726395590 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 65.xbar_error_and_unmapped_add r.2726395590 |
| Directory | /workspace/65.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/65.xbar_error_random.3302210648 |
| Short name | T2778 |
| Test name | |
| Test status | |
| Simulation time | 623012330 ps |
| CPU time | 21.18 seconds |
| Started | Aug 13 06:56:56 PM PDT 24 |
| Finished | Aug 13 06:57:17 PM PDT 24 |
| Peak memory | 575444 kb |
| Host | smart-75c50a5e-3252-458b-ac9c-e0cebef084ed |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3302210648 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 65.xbar_error_random.3302210648 |
| Directory | /workspace/65.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/65.xbar_random.3538703534 |
| Short name | T2298 |
| Test name | |
| Test status | |
| Simulation time | 177375916 ps |
| CPU time | 16.87 seconds |
| Started | Aug 13 06:56:48 PM PDT 24 |
| Finished | Aug 13 06:57:05 PM PDT 24 |
| Peak memory | 575512 kb |
| Host | smart-a98349bb-2932-4b73-a47b-b0da0e421579 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3538703534 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 65.xbar_random.3538703534 |
| Directory | /workspace/65.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/65.xbar_random_large_delays.1827995390 |
| Short name | T2252 |
| Test name | |
| Test status | |
| Simulation time | 87311519453 ps |
| CPU time | 978.59 seconds |
| Started | Aug 13 06:56:48 PM PDT 24 |
| Finished | Aug 13 07:13:07 PM PDT 24 |
| Peak memory | 575768 kb |
| Host | smart-410df56c-1567-4c97-ae6d-fd051e6327b1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1827995390 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 65.xbar_random_large_delays.1827995390 |
| Directory | /workspace/65.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/65.xbar_random_slow_rsp.2503143840 |
| Short name | T2149 |
| Test name | |
| Test status | |
| Simulation time | 40482495123 ps |
| CPU time | 623.89 seconds |
| Started | Aug 13 06:56:55 PM PDT 24 |
| Finished | Aug 13 07:07:19 PM PDT 24 |
| Peak memory | 575660 kb |
| Host | smart-b0237c86-484b-4892-a45f-9444536b4214 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2503143840 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 65.xbar_random_slow_rsp.2503143840 |
| Directory | /workspace/65.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/65.xbar_random_zero_delays.4231020191 |
| Short name | T2456 |
| Test name | |
| Test status | |
| Simulation time | 313244220 ps |
| CPU time | 32.05 seconds |
| Started | Aug 13 06:56:46 PM PDT 24 |
| Finished | Aug 13 06:57:18 PM PDT 24 |
| Peak memory | 575636 kb |
| Host | smart-58fed516-ae81-407c-bdb6-cea4b4e2b0c8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4231020191 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 65.xbar_random_zero_del ays.4231020191 |
| Directory | /workspace/65.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/65.xbar_same_source.2123694744 |
| Short name | T2096 |
| Test name | |
| Test status | |
| Simulation time | 171803618 ps |
| CPU time | 8.09 seconds |
| Started | Aug 13 06:56:52 PM PDT 24 |
| Finished | Aug 13 06:57:00 PM PDT 24 |
| Peak memory | 573532 kb |
| Host | smart-738ae236-68b2-4f8c-804a-07add3378e5d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2123694744 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 65.xbar_same_source.2123694744 |
| Directory | /workspace/65.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/65.xbar_smoke.3780271484 |
| Short name | T2385 |
| Test name | |
| Test status | |
| Simulation time | 35366932 ps |
| CPU time | 5.98 seconds |
| Started | Aug 13 06:56:47 PM PDT 24 |
| Finished | Aug 13 06:56:53 PM PDT 24 |
| Peak memory | 573508 kb |
| Host | smart-ac70e128-a1bd-4c64-bbc6-30052aeb74e4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3780271484 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 65.xbar_smoke.3780271484 |
| Directory | /workspace/65.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/65.xbar_smoke_large_delays.2711666364 |
| Short name | T1435 |
| Test name | |
| Test status | |
| Simulation time | 8569172745 ps |
| CPU time | 88.56 seconds |
| Started | Aug 13 06:56:46 PM PDT 24 |
| Finished | Aug 13 06:58:15 PM PDT 24 |
| Peak memory | 573668 kb |
| Host | smart-f08d1acb-2405-41ed-b5dc-3c68affb1b15 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2711666364 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 65.xbar_smoke_large_delays.2711666364 |
| Directory | /workspace/65.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/65.xbar_smoke_slow_rsp.355404682 |
| Short name | T2598 |
| Test name | |
| Test status | |
| Simulation time | 4871485635 ps |
| CPU time | 87.56 seconds |
| Started | Aug 13 06:56:47 PM PDT 24 |
| Finished | Aug 13 06:58:14 PM PDT 24 |
| Peak memory | 573652 kb |
| Host | smart-8493ce6d-7d6c-4bb4-9f7e-d8e665dfb9c4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=355404682 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 65.xbar_smoke_slow_rsp.355404682 |
| Directory | /workspace/65.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/65.xbar_smoke_zero_delays.1634084029 |
| Short name | T2044 |
| Test name | |
| Test status | |
| Simulation time | 45800183 ps |
| CPU time | 6.64 seconds |
| Started | Aug 13 06:56:48 PM PDT 24 |
| Finished | Aug 13 06:56:55 PM PDT 24 |
| Peak memory | 573552 kb |
| Host | smart-397a3682-e381-472d-9f61-ddd2fe2bb385 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1634084029 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 65.xbar_smoke_zero_delay s.1634084029 |
| Directory | /workspace/65.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/65.xbar_stress_all.276060720 |
| Short name | T2927 |
| Test name | |
| Test status | |
| Simulation time | 1867407091 ps |
| CPU time | 81.07 seconds |
| Started | Aug 13 06:56:55 PM PDT 24 |
| Finished | Aug 13 06:58:16 PM PDT 24 |
| Peak memory | 575604 kb |
| Host | smart-6513565b-5085-42a9-a917-c3b3a2d8edfa |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=276060720 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 65.xbar_stress_all.276060720 |
| Directory | /workspace/65.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/65.xbar_stress_all_with_error.845446064 |
| Short name | T2671 |
| Test name | |
| Test status | |
| Simulation time | 5234681616 ps |
| CPU time | 394.06 seconds |
| Started | Aug 13 06:56:54 PM PDT 24 |
| Finished | Aug 13 07:03:28 PM PDT 24 |
| Peak memory | 576536 kb |
| Host | smart-69577b48-2546-4b4c-9e45-1f6888d86ec0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=845446064 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 65.xbar_stress_all_with_error.845446064 |
| Directory | /workspace/65.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/65.xbar_stress_all_with_rand_reset.2828997829 |
| Short name | T2747 |
| Test name | |
| Test status | |
| Simulation time | 1383052063 ps |
| CPU time | 187.5 seconds |
| Started | Aug 13 06:56:53 PM PDT 24 |
| Finished | Aug 13 07:00:01 PM PDT 24 |
| Peak memory | 576468 kb |
| Host | smart-d389a245-0649-4b2b-b7a9-e9ca6422da3e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2828997829 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 65.xbar_stress_all _with_rand_reset.2828997829 |
| Directory | /workspace/65.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/65.xbar_stress_all_with_reset_error.1682218454 |
| Short name | T2939 |
| Test name | |
| Test status | |
| Simulation time | 21427891074 ps |
| CPU time | 1053.88 seconds |
| Started | Aug 13 06:56:55 PM PDT 24 |
| Finished | Aug 13 07:14:29 PM PDT 24 |
| Peak memory | 577588 kb |
| Host | smart-4648bd07-6bff-4ec8-ad95-e495d2a3bc76 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1682218454 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 65.xbar_stress_al l_with_reset_error.1682218454 |
| Directory | /workspace/65.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/65.xbar_unmapped_addr.549554699 |
| Short name | T578 |
| Test name | |
| Test status | |
| Simulation time | 269847494 ps |
| CPU time | 34.14 seconds |
| Started | Aug 13 06:56:54 PM PDT 24 |
| Finished | Aug 13 06:57:28 PM PDT 24 |
| Peak memory | 575704 kb |
| Host | smart-de29d4e8-36c6-4182-8d95-ca9cbcb43e55 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=549554699 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 65.xbar_unmapped_addr.549554699 |
| Directory | /workspace/65.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/66.xbar_access_same_device.3605991594 |
| Short name | T609 |
| Test name | |
| Test status | |
| Simulation time | 2984949724 ps |
| CPU time | 116.04 seconds |
| Started | Aug 13 06:56:52 PM PDT 24 |
| Finished | Aug 13 06:58:48 PM PDT 24 |
| Peak memory | 575592 kb |
| Host | smart-d70f9c09-7d6f-41b4-acc1-97479e43c61e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3605991594 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 66.xbar_access_same_device .3605991594 |
| Directory | /workspace/66.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/66.xbar_access_same_device_slow_rsp.2803337260 |
| Short name | T1890 |
| Test name | |
| Test status | |
| Simulation time | 129188074370 ps |
| CPU time | 2492.6 seconds |
| Started | Aug 13 06:57:02 PM PDT 24 |
| Finished | Aug 13 07:38:35 PM PDT 24 |
| Peak memory | 575784 kb |
| Host | smart-c5e57083-8994-4152-94bf-5a7d1397629a |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2803337260 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 66.xbar_access_same_ device_slow_rsp.2803337260 |
| Directory | /workspace/66.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/66.xbar_error_and_unmapped_addr.4168905456 |
| Short name | T1500 |
| Test name | |
| Test status | |
| Simulation time | 1267473147 ps |
| CPU time | 48.06 seconds |
| Started | Aug 13 06:57:00 PM PDT 24 |
| Finished | Aug 13 06:57:48 PM PDT 24 |
| Peak memory | 575484 kb |
| Host | smart-aa309fce-16e2-42d7-ace9-fb2ebbcf9cc9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4168905456 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 66.xbar_error_and_unmapped_add r.4168905456 |
| Directory | /workspace/66.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/66.xbar_error_random.919833047 |
| Short name | T1506 |
| Test name | |
| Test status | |
| Simulation time | 588620226 ps |
| CPU time | 49.05 seconds |
| Started | Aug 13 06:57:00 PM PDT 24 |
| Finished | Aug 13 06:57:49 PM PDT 24 |
| Peak memory | 575496 kb |
| Host | smart-ed9f7ac7-b493-488f-bb44-288717d9630a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=919833047 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 66.xbar_error_random.919833047 |
| Directory | /workspace/66.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/66.xbar_random.1092136891 |
| Short name | T2687 |
| Test name | |
| Test status | |
| Simulation time | 1649439697 ps |
| CPU time | 61.77 seconds |
| Started | Aug 13 06:56:55 PM PDT 24 |
| Finished | Aug 13 06:57:57 PM PDT 24 |
| Peak memory | 575656 kb |
| Host | smart-46576d3b-e6e2-4cc7-8aa4-b0d668f0145e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1092136891 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 66.xbar_random.1092136891 |
| Directory | /workspace/66.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/66.xbar_random_large_delays.1106303159 |
| Short name | T1582 |
| Test name | |
| Test status | |
| Simulation time | 15680381198 ps |
| CPU time | 169.58 seconds |
| Started | Aug 13 06:56:54 PM PDT 24 |
| Finished | Aug 13 06:59:44 PM PDT 24 |
| Peak memory | 575780 kb |
| Host | smart-64c86932-0860-4319-9a50-242a56a287e7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1106303159 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 66.xbar_random_large_delays.1106303159 |
| Directory | /workspace/66.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/66.xbar_random_slow_rsp.2929052487 |
| Short name | T1499 |
| Test name | |
| Test status | |
| Simulation time | 13054927597 ps |
| CPU time | 234.18 seconds |
| Started | Aug 13 06:56:53 PM PDT 24 |
| Finished | Aug 13 07:00:47 PM PDT 24 |
| Peak memory | 575824 kb |
| Host | smart-7c52fe87-1dd3-4bc9-b211-a15a5c444efa |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2929052487 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 66.xbar_random_slow_rsp.2929052487 |
| Directory | /workspace/66.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/66.xbar_random_zero_delays.741245875 |
| Short name | T1562 |
| Test name | |
| Test status | |
| Simulation time | 109284733 ps |
| CPU time | 11.52 seconds |
| Started | Aug 13 06:56:56 PM PDT 24 |
| Finished | Aug 13 06:57:07 PM PDT 24 |
| Peak memory | 575528 kb |
| Host | smart-4253e9ec-93b2-4bfa-a635-53a4949a1165 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=741245875 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 66.xbar_random_zero_dela ys.741245875 |
| Directory | /workspace/66.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/66.xbar_same_source.132062148 |
| Short name | T2406 |
| Test name | |
| Test status | |
| Simulation time | 1573122677 ps |
| CPU time | 46.3 seconds |
| Started | Aug 13 06:57:01 PM PDT 24 |
| Finished | Aug 13 06:57:48 PM PDT 24 |
| Peak memory | 575504 kb |
| Host | smart-c57ac777-173e-45ad-811b-c66e03bf9099 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=132062148 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 66.xbar_same_source.132062148 |
| Directory | /workspace/66.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/66.xbar_smoke.4210640671 |
| Short name | T638 |
| Test name | |
| Test status | |
| Simulation time | 220624535 ps |
| CPU time | 9.63 seconds |
| Started | Aug 13 06:56:54 PM PDT 24 |
| Finished | Aug 13 06:57:04 PM PDT 24 |
| Peak memory | 574220 kb |
| Host | smart-12885aa5-c3b8-403f-b5fb-d01f95b174d0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4210640671 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 66.xbar_smoke.4210640671 |
| Directory | /workspace/66.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/66.xbar_smoke_large_delays.2411071126 |
| Short name | T2335 |
| Test name | |
| Test status | |
| Simulation time | 8394331512 ps |
| CPU time | 89.47 seconds |
| Started | Aug 13 06:56:53 PM PDT 24 |
| Finished | Aug 13 06:58:22 PM PDT 24 |
| Peak memory | 573600 kb |
| Host | smart-41d044f8-626c-4acb-a16c-2bf40550325f |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2411071126 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 66.xbar_smoke_large_delays.2411071126 |
| Directory | /workspace/66.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/66.xbar_smoke_slow_rsp.3767463475 |
| Short name | T2412 |
| Test name | |
| Test status | |
| Simulation time | 5528945358 ps |
| CPU time | 93.38 seconds |
| Started | Aug 13 06:56:54 PM PDT 24 |
| Finished | Aug 13 06:58:28 PM PDT 24 |
| Peak memory | 573652 kb |
| Host | smart-75629971-5593-4267-b177-f5422a80510f |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3767463475 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 66.xbar_smoke_slow_rsp.3767463475 |
| Directory | /workspace/66.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/66.xbar_smoke_zero_delays.1111603049 |
| Short name | T1465 |
| Test name | |
| Test status | |
| Simulation time | 37356853 ps |
| CPU time | 6.17 seconds |
| Started | Aug 13 06:56:56 PM PDT 24 |
| Finished | Aug 13 06:57:02 PM PDT 24 |
| Peak memory | 573596 kb |
| Host | smart-fb6ffb88-364b-49cc-94b3-0ba8e44092db |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1111603049 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 66.xbar_smoke_zero_delay s.1111603049 |
| Directory | /workspace/66.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/66.xbar_stress_all.47248808 |
| Short name | T2744 |
| Test name | |
| Test status | |
| Simulation time | 6659449665 ps |
| CPU time | 226.34 seconds |
| Started | Aug 13 06:57:03 PM PDT 24 |
| Finished | Aug 13 07:00:49 PM PDT 24 |
| Peak memory | 575672 kb |
| Host | smart-154924df-200d-4dfd-a023-496a4188de80 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=47248808 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 66.xbar_stress_all.47248808 |
| Directory | /workspace/66.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/66.xbar_stress_all_with_error.4099766847 |
| Short name | T2235 |
| Test name | |
| Test status | |
| Simulation time | 3765723206 ps |
| CPU time | 294.67 seconds |
| Started | Aug 13 06:57:02 PM PDT 24 |
| Finished | Aug 13 07:01:56 PM PDT 24 |
| Peak memory | 576580 kb |
| Host | smart-ba84684a-6bae-482f-ab07-259212460798 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4099766847 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 66.xbar_stress_all_with_error.4099766847 |
| Directory | /workspace/66.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/66.xbar_stress_all_with_rand_reset.1464374048 |
| Short name | T1923 |
| Test name | |
| Test status | |
| Simulation time | 374290033 ps |
| CPU time | 150.72 seconds |
| Started | Aug 13 06:57:00 PM PDT 24 |
| Finished | Aug 13 06:59:31 PM PDT 24 |
| Peak memory | 576440 kb |
| Host | smart-c3112080-cd6a-47b1-9186-1c14b7c34605 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1464374048 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 66.xbar_stress_all _with_rand_reset.1464374048 |
| Directory | /workspace/66.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/66.xbar_stress_all_with_reset_error.901358969 |
| Short name | T1589 |
| Test name | |
| Test status | |
| Simulation time | 2022127326 ps |
| CPU time | 169.29 seconds |
| Started | Aug 13 06:57:02 PM PDT 24 |
| Finished | Aug 13 06:59:51 PM PDT 24 |
| Peak memory | 575676 kb |
| Host | smart-7dc6a81e-3619-45d5-a15e-7521120b4ddb |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=901358969 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 66.xbar_stress_all _with_reset_error.901358969 |
| Directory | /workspace/66.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/66.xbar_unmapped_addr.1305466247 |
| Short name | T658 |
| Test name | |
| Test status | |
| Simulation time | 1425283366 ps |
| CPU time | 52.36 seconds |
| Started | Aug 13 06:57:03 PM PDT 24 |
| Finished | Aug 13 06:57:55 PM PDT 24 |
| Peak memory | 575616 kb |
| Host | smart-4374f1d0-c681-45da-8a07-e6987e9419ae |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1305466247 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 66.xbar_unmapped_addr.1305466247 |
| Directory | /workspace/66.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/67.xbar_access_same_device.1131289037 |
| Short name | T1611 |
| Test name | |
| Test status | |
| Simulation time | 327806871 ps |
| CPU time | 28.6 seconds |
| Started | Aug 13 06:57:02 PM PDT 24 |
| Finished | Aug 13 06:57:30 PM PDT 24 |
| Peak memory | 575616 kb |
| Host | smart-0ed5e116-d664-47f6-8c88-66a07ebf0cfb |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1131289037 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 67.xbar_access_same_device .1131289037 |
| Directory | /workspace/67.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/67.xbar_error_and_unmapped_addr.3887954570 |
| Short name | T702 |
| Test name | |
| Test status | |
| Simulation time | 326745633 ps |
| CPU time | 15.84 seconds |
| Started | Aug 13 06:57:01 PM PDT 24 |
| Finished | Aug 13 06:57:17 PM PDT 24 |
| Peak memory | 575636 kb |
| Host | smart-2623ac72-a1a6-4a8f-81b5-5888ed788745 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3887954570 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 67.xbar_error_and_unmapped_add r.3887954570 |
| Directory | /workspace/67.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/67.xbar_error_random.2475520238 |
| Short name | T1686 |
| Test name | |
| Test status | |
| Simulation time | 143156194 ps |
| CPU time | 7.55 seconds |
| Started | Aug 13 06:57:02 PM PDT 24 |
| Finished | Aug 13 06:57:09 PM PDT 24 |
| Peak memory | 573660 kb |
| Host | smart-4c195fb9-3128-4b98-9a56-54b101b0de02 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2475520238 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 67.xbar_error_random.2475520238 |
| Directory | /workspace/67.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/67.xbar_random.2955592893 |
| Short name | T1810 |
| Test name | |
| Test status | |
| Simulation time | 136697229 ps |
| CPU time | 8.45 seconds |
| Started | Aug 13 06:57:01 PM PDT 24 |
| Finished | Aug 13 06:57:10 PM PDT 24 |
| Peak memory | 574280 kb |
| Host | smart-565142c6-e1e4-48de-95c8-7066de8cadc6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2955592893 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 67.xbar_random.2955592893 |
| Directory | /workspace/67.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/67.xbar_random_large_delays.1203367034 |
| Short name | T2748 |
| Test name | |
| Test status | |
| Simulation time | 21883904997 ps |
| CPU time | 217.9 seconds |
| Started | Aug 13 06:57:05 PM PDT 24 |
| Finished | Aug 13 07:00:43 PM PDT 24 |
| Peak memory | 575760 kb |
| Host | smart-3ae5c29e-7d87-4cc0-b27d-429c9b26717c |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1203367034 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 67.xbar_random_large_delays.1203367034 |
| Directory | /workspace/67.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/67.xbar_random_slow_rsp.138803917 |
| Short name | T2588 |
| Test name | |
| Test status | |
| Simulation time | 24173030555 ps |
| CPU time | 400.27 seconds |
| Started | Aug 13 06:57:05 PM PDT 24 |
| Finished | Aug 13 07:03:45 PM PDT 24 |
| Peak memory | 575796 kb |
| Host | smart-17a0fe31-234e-47b6-a38b-c1ab23926efe |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=138803917 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 67.xbar_random_slow_rsp.138803917 |
| Directory | /workspace/67.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/67.xbar_random_zero_delays.1535353103 |
| Short name | T1931 |
| Test name | |
| Test status | |
| Simulation time | 331516734 ps |
| CPU time | 29.62 seconds |
| Started | Aug 13 06:57:05 PM PDT 24 |
| Finished | Aug 13 06:57:35 PM PDT 24 |
| Peak memory | 575608 kb |
| Host | smart-2aa572e1-5225-4fa1-81ac-7b63dbe6cee8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1535353103 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 67.xbar_random_zero_del ays.1535353103 |
| Directory | /workspace/67.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/67.xbar_same_source.3232897616 |
| Short name | T2781 |
| Test name | |
| Test status | |
| Simulation time | 2728146207 ps |
| CPU time | 72.38 seconds |
| Started | Aug 13 06:57:03 PM PDT 24 |
| Finished | Aug 13 06:58:16 PM PDT 24 |
| Peak memory | 575756 kb |
| Host | smart-57f729a6-80e5-4a93-873f-06c4d892b0a6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3232897616 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 67.xbar_same_source.3232897616 |
| Directory | /workspace/67.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/67.xbar_smoke.242466937 |
| Short name | T2388 |
| Test name | |
| Test status | |
| Simulation time | 188467323 ps |
| CPU time | 9.08 seconds |
| Started | Aug 13 06:57:02 PM PDT 24 |
| Finished | Aug 13 06:57:11 PM PDT 24 |
| Peak memory | 573608 kb |
| Host | smart-5d1760cb-7288-4efd-afde-b81d092cd859 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=242466937 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 67.xbar_smoke.242466937 |
| Directory | /workspace/67.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/67.xbar_smoke_large_delays.914800838 |
| Short name | T2184 |
| Test name | |
| Test status | |
| Simulation time | 5981648502 ps |
| CPU time | 67.34 seconds |
| Started | Aug 13 06:57:03 PM PDT 24 |
| Finished | Aug 13 06:58:10 PM PDT 24 |
| Peak memory | 574236 kb |
| Host | smart-04d10fab-45de-41f2-bcb8-6940bea33fed |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=914800838 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 67.xbar_smoke_large_delays.914800838 |
| Directory | /workspace/67.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/67.xbar_smoke_slow_rsp.3422737013 |
| Short name | T2775 |
| Test name | |
| Test status | |
| Simulation time | 5346258953 ps |
| CPU time | 92.34 seconds |
| Started | Aug 13 06:57:00 PM PDT 24 |
| Finished | Aug 13 06:58:32 PM PDT 24 |
| Peak memory | 573684 kb |
| Host | smart-5f7755c8-d376-4a9a-ba45-180f8819103b |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3422737013 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 67.xbar_smoke_slow_rsp.3422737013 |
| Directory | /workspace/67.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/67.xbar_smoke_zero_delays.2855538119 |
| Short name | T2508 |
| Test name | |
| Test status | |
| Simulation time | 46795552 ps |
| CPU time | 6.45 seconds |
| Started | Aug 13 06:57:03 PM PDT 24 |
| Finished | Aug 13 06:57:09 PM PDT 24 |
| Peak memory | 574152 kb |
| Host | smart-24274c1b-6847-4b90-9f54-cd675a528905 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2855538119 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 67.xbar_smoke_zero_delay s.2855538119 |
| Directory | /workspace/67.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/67.xbar_stress_all.1840804645 |
| Short name | T2269 |
| Test name | |
| Test status | |
| Simulation time | 21109797057 ps |
| CPU time | 799.1 seconds |
| Started | Aug 13 06:57:03 PM PDT 24 |
| Finished | Aug 13 07:10:22 PM PDT 24 |
| Peak memory | 576584 kb |
| Host | smart-e26cae5a-e0c4-465c-94c9-cd0f3bd5a394 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1840804645 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 67.xbar_stress_all.1840804645 |
| Directory | /workspace/67.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/67.xbar_stress_all_with_error.4004758646 |
| Short name | T1552 |
| Test name | |
| Test status | |
| Simulation time | 3287673123 ps |
| CPU time | 245.97 seconds |
| Started | Aug 13 06:57:07 PM PDT 24 |
| Finished | Aug 13 07:01:13 PM PDT 24 |
| Peak memory | 576532 kb |
| Host | smart-910bb62d-bd7a-40a6-a762-82ff7f251312 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4004758646 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 67.xbar_stress_all_with_error.4004758646 |
| Directory | /workspace/67.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/67.xbar_stress_all_with_rand_reset.1159420333 |
| Short name | T1447 |
| Test name | |
| Test status | |
| Simulation time | 7731145 ps |
| CPU time | 5.96 seconds |
| Started | Aug 13 06:57:08 PM PDT 24 |
| Finished | Aug 13 06:57:14 PM PDT 24 |
| Peak memory | 574256 kb |
| Host | smart-f84ac368-4e01-4da2-875e-1e5d8d70c7db |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1159420333 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 67.xbar_stress_all _with_rand_reset.1159420333 |
| Directory | /workspace/67.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/67.xbar_stress_all_with_reset_error.3679566773 |
| Short name | T1710 |
| Test name | |
| Test status | |
| Simulation time | 638204453 ps |
| CPU time | 197.52 seconds |
| Started | Aug 13 06:57:09 PM PDT 24 |
| Finished | Aug 13 07:00:27 PM PDT 24 |
| Peak memory | 576504 kb |
| Host | smart-b58255af-ca19-4282-b47a-fd8ec03ec9c6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3679566773 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 67.xbar_stress_al l_with_reset_error.3679566773 |
| Directory | /workspace/67.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/67.xbar_unmapped_addr.884377264 |
| Short name | T2397 |
| Test name | |
| Test status | |
| Simulation time | 438097828 ps |
| CPU time | 19.04 seconds |
| Started | Aug 13 06:57:01 PM PDT 24 |
| Finished | Aug 13 06:57:20 PM PDT 24 |
| Peak memory | 575604 kb |
| Host | smart-463a109a-7e92-47c6-89ff-c8f4df62b95d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=884377264 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 67.xbar_unmapped_addr.884377264 |
| Directory | /workspace/67.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/68.xbar_access_same_device.780421453 |
| Short name | T1598 |
| Test name | |
| Test status | |
| Simulation time | 719426046 ps |
| CPU time | 68.52 seconds |
| Started | Aug 13 06:57:07 PM PDT 24 |
| Finished | Aug 13 06:58:15 PM PDT 24 |
| Peak memory | 575516 kb |
| Host | smart-106b0697-f885-4132-9729-ff1289653b21 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=780421453 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 68.xbar_access_same_device. 780421453 |
| Directory | /workspace/68.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/68.xbar_error_and_unmapped_addr.3330504239 |
| Short name | T1503 |
| Test name | |
| Test status | |
| Simulation time | 1040794257 ps |
| CPU time | 39.96 seconds |
| Started | Aug 13 06:57:20 PM PDT 24 |
| Finished | Aug 13 06:58:00 PM PDT 24 |
| Peak memory | 575684 kb |
| Host | smart-69777793-1784-4024-88b1-7cc563a316eb |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3330504239 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 68.xbar_error_and_unmapped_add r.3330504239 |
| Directory | /workspace/68.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/68.xbar_error_random.2617606668 |
| Short name | T2328 |
| Test name | |
| Test status | |
| Simulation time | 897738220 ps |
| CPU time | 31.4 seconds |
| Started | Aug 13 06:57:15 PM PDT 24 |
| Finished | Aug 13 06:57:46 PM PDT 24 |
| Peak memory | 575652 kb |
| Host | smart-5f31ca70-7ede-44d1-8041-b5e34939b134 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2617606668 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 68.xbar_error_random.2617606668 |
| Directory | /workspace/68.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/68.xbar_random.1387267876 |
| Short name | T1969 |
| Test name | |
| Test status | |
| Simulation time | 238714292 ps |
| CPU time | 24.36 seconds |
| Started | Aug 13 06:57:08 PM PDT 24 |
| Finished | Aug 13 06:57:33 PM PDT 24 |
| Peak memory | 575480 kb |
| Host | smart-83b240a0-a932-41bd-abad-cc4b4136d950 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1387267876 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 68.xbar_random.1387267876 |
| Directory | /workspace/68.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/68.xbar_random_large_delays.2586899423 |
| Short name | T2746 |
| Test name | |
| Test status | |
| Simulation time | 93144014096 ps |
| CPU time | 1004.54 seconds |
| Started | Aug 13 06:57:09 PM PDT 24 |
| Finished | Aug 13 07:13:53 PM PDT 24 |
| Peak memory | 575664 kb |
| Host | smart-3f89d24f-8bae-412a-a290-1a8fca61a0c0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2586899423 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 68.xbar_random_large_delays.2586899423 |
| Directory | /workspace/68.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/68.xbar_random_slow_rsp.87367684 |
| Short name | T2418 |
| Test name | |
| Test status | |
| Simulation time | 58953757463 ps |
| CPU time | 1079.89 seconds |
| Started | Aug 13 06:57:06 PM PDT 24 |
| Finished | Aug 13 07:15:06 PM PDT 24 |
| Peak memory | 575636 kb |
| Host | smart-d712f332-c127-4448-aadf-9c069cd1c671 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87367684 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 68.xbar_random_slow_rsp.87367684 |
| Directory | /workspace/68.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/68.xbar_random_zero_delays.315181073 |
| Short name | T2579 |
| Test name | |
| Test status | |
| Simulation time | 632888741 ps |
| CPU time | 49.78 seconds |
| Started | Aug 13 06:57:07 PM PDT 24 |
| Finished | Aug 13 06:57:57 PM PDT 24 |
| Peak memory | 575632 kb |
| Host | smart-66119e14-7933-4404-8689-1e79f84fd920 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=315181073 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 68.xbar_random_zero_dela ys.315181073 |
| Directory | /workspace/68.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/68.xbar_same_source.3492315207 |
| Short name | T2139 |
| Test name | |
| Test status | |
| Simulation time | 1429606984 ps |
| CPU time | 39.92 seconds |
| Started | Aug 13 06:57:14 PM PDT 24 |
| Finished | Aug 13 06:57:54 PM PDT 24 |
| Peak memory | 575632 kb |
| Host | smart-b4448f40-26be-4dda-bcf1-f4557629e8a8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3492315207 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 68.xbar_same_source.3492315207 |
| Directory | /workspace/68.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/68.xbar_smoke.4151833438 |
| Short name | T2158 |
| Test name | |
| Test status | |
| Simulation time | 204559890 ps |
| CPU time | 9.55 seconds |
| Started | Aug 13 06:57:05 PM PDT 24 |
| Finished | Aug 13 06:57:15 PM PDT 24 |
| Peak memory | 573436 kb |
| Host | smart-f87d915c-98cd-4351-8138-de597058f3e2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4151833438 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 68.xbar_smoke.4151833438 |
| Directory | /workspace/68.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/68.xbar_smoke_large_delays.2542777870 |
| Short name | T2237 |
| Test name | |
| Test status | |
| Simulation time | 9312344378 ps |
| CPU time | 103.06 seconds |
| Started | Aug 13 06:57:08 PM PDT 24 |
| Finished | Aug 13 06:58:52 PM PDT 24 |
| Peak memory | 573660 kb |
| Host | smart-15422ce0-2a60-45b6-b962-b6e5395b8133 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2542777870 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 68.xbar_smoke_large_delays.2542777870 |
| Directory | /workspace/68.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/68.xbar_smoke_slow_rsp.3755241440 |
| Short name | T2166 |
| Test name | |
| Test status | |
| Simulation time | 6509539597 ps |
| CPU time | 111.8 seconds |
| Started | Aug 13 06:57:08 PM PDT 24 |
| Finished | Aug 13 06:59:00 PM PDT 24 |
| Peak memory | 573756 kb |
| Host | smart-3fbbaa61-81b4-49b9-8800-7136ddcf52e2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3755241440 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 68.xbar_smoke_slow_rsp.3755241440 |
| Directory | /workspace/68.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/68.xbar_smoke_zero_delays.1807178624 |
| Short name | T1708 |
| Test name | |
| Test status | |
| Simulation time | 43492319 ps |
| CPU time | 6.41 seconds |
| Started | Aug 13 06:57:06 PM PDT 24 |
| Finished | Aug 13 06:57:12 PM PDT 24 |
| Peak memory | 574204 kb |
| Host | smart-fc3cdbf5-10d9-42e7-b342-6e9c7c2778fa |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1807178624 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 68.xbar_smoke_zero_delay s.1807178624 |
| Directory | /workspace/68.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/68.xbar_stress_all.242475933 |
| Short name | T1968 |
| Test name | |
| Test status | |
| Simulation time | 4866903814 ps |
| CPU time | 172.84 seconds |
| Started | Aug 13 06:57:14 PM PDT 24 |
| Finished | Aug 13 07:00:07 PM PDT 24 |
| Peak memory | 576148 kb |
| Host | smart-01bc290b-cbf0-488e-be70-648a6eaf11e6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=242475933 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 68.xbar_stress_all.242475933 |
| Directory | /workspace/68.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/68.xbar_stress_all_with_error.1045951177 |
| Short name | T1466 |
| Test name | |
| Test status | |
| Simulation time | 4272462293 ps |
| CPU time | 134.59 seconds |
| Started | Aug 13 06:57:15 PM PDT 24 |
| Finished | Aug 13 06:59:29 PM PDT 24 |
| Peak memory | 575760 kb |
| Host | smart-164841a1-b67a-4882-826c-2dcdbe350898 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1045951177 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 68.xbar_stress_all_with_error.1045951177 |
| Directory | /workspace/68.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/68.xbar_stress_all_with_rand_reset.3412411030 |
| Short name | T2140 |
| Test name | |
| Test status | |
| Simulation time | 505641807 ps |
| CPU time | 257.96 seconds |
| Started | Aug 13 06:57:20 PM PDT 24 |
| Finished | Aug 13 07:01:38 PM PDT 24 |
| Peak memory | 575664 kb |
| Host | smart-e57f8067-d87d-4615-9e55-631bf6fa251f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3412411030 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 68.xbar_stress_all _with_rand_reset.3412411030 |
| Directory | /workspace/68.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/68.xbar_stress_all_with_reset_error.2636817955 |
| Short name | T2597 |
| Test name | |
| Test status | |
| Simulation time | 56089417 ps |
| CPU time | 34 seconds |
| Started | Aug 13 06:57:14 PM PDT 24 |
| Finished | Aug 13 06:57:48 PM PDT 24 |
| Peak memory | 574372 kb |
| Host | smart-9c0e1604-321c-4b0a-bdd5-d3c396608a5f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2636817955 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 68.xbar_stress_al l_with_reset_error.2636817955 |
| Directory | /workspace/68.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/68.xbar_unmapped_addr.992628654 |
| Short name | T2224 |
| Test name | |
| Test status | |
| Simulation time | 1386195246 ps |
| CPU time | 58.58 seconds |
| Started | Aug 13 06:57:15 PM PDT 24 |
| Finished | Aug 13 06:58:14 PM PDT 24 |
| Peak memory | 575688 kb |
| Host | smart-4ad05763-198e-4826-94f4-121f411d8dac |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=992628654 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 68.xbar_unmapped_addr.992628654 |
| Directory | /workspace/68.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/69.xbar_access_same_device.1121591219 |
| Short name | T2642 |
| Test name | |
| Test status | |
| Simulation time | 443501858 ps |
| CPU time | 18.19 seconds |
| Started | Aug 13 06:57:22 PM PDT 24 |
| Finished | Aug 13 06:57:40 PM PDT 24 |
| Peak memory | 575524 kb |
| Host | smart-5c59359c-62b4-4e3f-ac74-326dead4d94b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1121591219 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 69.xbar_access_same_device .1121591219 |
| Directory | /workspace/69.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/69.xbar_access_same_device_slow_rsp.45162752 |
| Short name | T1903 |
| Test name | |
| Test status | |
| Simulation time | 33726686533 ps |
| CPU time | 664.09 seconds |
| Started | Aug 13 06:57:21 PM PDT 24 |
| Finished | Aug 13 07:08:25 PM PDT 24 |
| Peak memory | 575776 kb |
| Host | smart-fa0237e0-615c-4fb4-a1b5-b6aa34e2a535 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=45162752 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 69.xbar_access_same_de vice_slow_rsp.45162752 |
| Directory | /workspace/69.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/69.xbar_error_and_unmapped_addr.1268528796 |
| Short name | T1513 |
| Test name | |
| Test status | |
| Simulation time | 299016445 ps |
| CPU time | 31.49 seconds |
| Started | Aug 13 06:57:29 PM PDT 24 |
| Finished | Aug 13 06:58:00 PM PDT 24 |
| Peak memory | 575712 kb |
| Host | smart-ef251711-8c09-45f9-81f3-da98017a3444 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1268528796 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 69.xbar_error_and_unmapped_add r.1268528796 |
| Directory | /workspace/69.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/69.xbar_error_random.1377222017 |
| Short name | T2518 |
| Test name | |
| Test status | |
| Simulation time | 35588937 ps |
| CPU time | 6.23 seconds |
| Started | Aug 13 06:57:21 PM PDT 24 |
| Finished | Aug 13 06:57:27 PM PDT 24 |
| Peak memory | 573636 kb |
| Host | smart-307232dd-fc0b-4bfb-999c-e397c120858f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1377222017 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 69.xbar_error_random.1377222017 |
| Directory | /workspace/69.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/69.xbar_random.1001747142 |
| Short name | T2066 |
| Test name | |
| Test status | |
| Simulation time | 1828079541 ps |
| CPU time | 70.57 seconds |
| Started | Aug 13 06:57:22 PM PDT 24 |
| Finished | Aug 13 06:58:33 PM PDT 24 |
| Peak memory | 575640 kb |
| Host | smart-ae3a7879-83fb-4b3a-a4fc-a43698563b1c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1001747142 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 69.xbar_random.1001747142 |
| Directory | /workspace/69.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/69.xbar_random_large_delays.2323980052 |
| Short name | T2530 |
| Test name | |
| Test status | |
| Simulation time | 33187572402 ps |
| CPU time | 349.51 seconds |
| Started | Aug 13 06:57:21 PM PDT 24 |
| Finished | Aug 13 07:03:11 PM PDT 24 |
| Peak memory | 575816 kb |
| Host | smart-a920ddf1-2f3b-4975-a185-02222a148e7d |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2323980052 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 69.xbar_random_large_delays.2323980052 |
| Directory | /workspace/69.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/69.xbar_random_slow_rsp.2017361723 |
| Short name | T2310 |
| Test name | |
| Test status | |
| Simulation time | 28396954455 ps |
| CPU time | 465.24 seconds |
| Started | Aug 13 06:57:22 PM PDT 24 |
| Finished | Aug 13 07:05:07 PM PDT 24 |
| Peak memory | 575724 kb |
| Host | smart-14e4e2df-a9c0-429f-91f9-f3fa4bac47c8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2017361723 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 69.xbar_random_slow_rsp.2017361723 |
| Directory | /workspace/69.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/69.xbar_random_zero_delays.3751865782 |
| Short name | T676 |
| Test name | |
| Test status | |
| Simulation time | 436377764 ps |
| CPU time | 36.2 seconds |
| Started | Aug 13 06:57:20 PM PDT 24 |
| Finished | Aug 13 06:57:56 PM PDT 24 |
| Peak memory | 575512 kb |
| Host | smart-c4541eb3-3d6e-46bb-9915-d1cfef72e8d9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3751865782 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 69.xbar_random_zero_del ays.3751865782 |
| Directory | /workspace/69.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/69.xbar_same_source.109958156 |
| Short name | T2847 |
| Test name | |
| Test status | |
| Simulation time | 1620363054 ps |
| CPU time | 43.63 seconds |
| Started | Aug 13 06:57:21 PM PDT 24 |
| Finished | Aug 13 06:58:05 PM PDT 24 |
| Peak memory | 575500 kb |
| Host | smart-015eec29-665f-41bb-8cd9-1c236997bff2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=109958156 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 69.xbar_same_source.109958156 |
| Directory | /workspace/69.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/69.xbar_smoke.2106795661 |
| Short name | T1997 |
| Test name | |
| Test status | |
| Simulation time | 200385201 ps |
| CPU time | 8.32 seconds |
| Started | Aug 13 06:57:18 PM PDT 24 |
| Finished | Aug 13 06:57:26 PM PDT 24 |
| Peak memory | 573520 kb |
| Host | smart-706549db-da17-426e-823c-84d8b0bae649 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2106795661 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 69.xbar_smoke.2106795661 |
| Directory | /workspace/69.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/69.xbar_smoke_large_delays.3809702619 |
| Short name | T1644 |
| Test name | |
| Test status | |
| Simulation time | 7930235788 ps |
| CPU time | 88.99 seconds |
| Started | Aug 13 06:57:14 PM PDT 24 |
| Finished | Aug 13 06:58:43 PM PDT 24 |
| Peak memory | 573684 kb |
| Host | smart-005ea1ef-d36e-4edc-b9ee-82c02d29c954 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3809702619 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 69.xbar_smoke_large_delays.3809702619 |
| Directory | /workspace/69.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/69.xbar_smoke_slow_rsp.1927426440 |
| Short name | T2666 |
| Test name | |
| Test status | |
| Simulation time | 3302928849 ps |
| CPU time | 51.08 seconds |
| Started | Aug 13 06:57:19 PM PDT 24 |
| Finished | Aug 13 06:58:10 PM PDT 24 |
| Peak memory | 573644 kb |
| Host | smart-1993cf71-81c6-4b6c-a7f5-d85a1939ba46 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1927426440 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 69.xbar_smoke_slow_rsp.1927426440 |
| Directory | /workspace/69.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/69.xbar_smoke_zero_delays.1687513497 |
| Short name | T2525 |
| Test name | |
| Test status | |
| Simulation time | 38844561 ps |
| CPU time | 5.91 seconds |
| Started | Aug 13 06:57:15 PM PDT 24 |
| Finished | Aug 13 06:57:21 PM PDT 24 |
| Peak memory | 573528 kb |
| Host | smart-e186c39d-113a-4933-9b4a-b5ff739c1040 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1687513497 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 69.xbar_smoke_zero_delay s.1687513497 |
| Directory | /workspace/69.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/69.xbar_stress_all.778028760 |
| Short name | T583 |
| Test name | |
| Test status | |
| Simulation time | 1451576057 ps |
| CPU time | 107.18 seconds |
| Started | Aug 13 06:57:27 PM PDT 24 |
| Finished | Aug 13 06:59:14 PM PDT 24 |
| Peak memory | 575788 kb |
| Host | smart-22d3fc2b-581c-4d2c-b2c5-c5a5d0cc30ea |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=778028760 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 69.xbar_stress_all.778028760 |
| Directory | /workspace/69.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/69.xbar_stress_all_with_error.3729972564 |
| Short name | T2242 |
| Test name | |
| Test status | |
| Simulation time | 12613385383 ps |
| CPU time | 456.03 seconds |
| Started | Aug 13 06:57:28 PM PDT 24 |
| Finished | Aug 13 07:05:04 PM PDT 24 |
| Peak memory | 576408 kb |
| Host | smart-95245746-5caa-498c-bdce-d4975ecddddb |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3729972564 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 69.xbar_stress_all_with_error.3729972564 |
| Directory | /workspace/69.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/69.xbar_stress_all_with_rand_reset.3466052003 |
| Short name | T1871 |
| Test name | |
| Test status | |
| Simulation time | 409722298 ps |
| CPU time | 139.21 seconds |
| Started | Aug 13 06:57:28 PM PDT 24 |
| Finished | Aug 13 06:59:47 PM PDT 24 |
| Peak memory | 576480 kb |
| Host | smart-53e00581-9cc1-4b60-8861-7342b4dfc933 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3466052003 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 69.xbar_stress_all _with_rand_reset.3466052003 |
| Directory | /workspace/69.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/69.xbar_stress_all_with_reset_error.1789280062 |
| Short name | T1861 |
| Test name | |
| Test status | |
| Simulation time | 5267755814 ps |
| CPU time | 526.92 seconds |
| Started | Aug 13 06:57:30 PM PDT 24 |
| Finished | Aug 13 07:06:18 PM PDT 24 |
| Peak memory | 576552 kb |
| Host | smart-5d926c67-f43b-4275-b230-1c58272d6c90 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1789280062 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 69.xbar_stress_al l_with_reset_error.1789280062 |
| Directory | /workspace/69.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/69.xbar_unmapped_addr.1261436196 |
| Short name | T2845 |
| Test name | |
| Test status | |
| Simulation time | 171229804 ps |
| CPU time | 22.22 seconds |
| Started | Aug 13 06:57:27 PM PDT 24 |
| Finished | Aug 13 06:57:49 PM PDT 24 |
| Peak memory | 575700 kb |
| Host | smart-9e50e77e-55a9-4a41-a33c-b0a552e3d17c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1261436196 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 69.xbar_unmapped_addr.1261436196 |
| Directory | /workspace/69.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/7.chip_csr_mem_rw_with_rand_reset.3597453207 |
| Short name | T2112 |
| Test name | |
| Test status | |
| Simulation time | 11196636076 ps |
| CPU time | 887.37 seconds |
| Started | Aug 13 06:50:54 PM PDT 24 |
| Finished | Aug 13 07:05:41 PM PDT 24 |
| Peak memory | 652624 kb |
| Host | smart-b837d246-f1cc-48c5-9a03-1efb4a03a50e |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3597453207 -assert nopostproc + UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top .vdb -cm_log /dev/null -cm_name 7.chip_csr_mem_rw_with_rand_reset.3597453207 |
| Directory | /workspace/7.chip_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/7.chip_csr_rw.3449738971 |
| Short name | T1680 |
| Test name | |
| Test status | |
| Simulation time | 5682579180 ps |
| CPU time | 663.99 seconds |
| Started | Aug 13 06:51:02 PM PDT 24 |
| Finished | Aug 13 07:02:06 PM PDT 24 |
| Peak memory | 598368 kb |
| Host | smart-de46369e-b717-46bd-8bdf-ca7152512c4a |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3449738971 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.chip_csr_rw.3449738971 |
| Directory | /workspace/7.chip_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/7.chip_same_csr_outstanding.3431698650 |
| Short name | T2159 |
| Test name | |
| Test status | |
| Simulation time | 32676406572 ps |
| CPU time | 3627.49 seconds |
| Started | Aug 13 06:51:12 PM PDT 24 |
| Finished | Aug 13 07:51:41 PM PDT 24 |
| Peak memory | 592988 kb |
| Host | smart-c2b49489-707a-441b-a6e9-bf59fdbabd5a |
| User | root |
| Command | /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +run_same_csr_outstanding +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3431698650 -assert nopostproc +UVM_TE STNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb - cm_log /dev/null -cm_name 7.chip_same_csr_outstanding.3431698650 |
| Directory | /workspace/7.chip_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/7.chip_tl_errors.4225450812 |
| Short name | T732 |
| Test name | |
| Test status | |
| Simulation time | 4302899000 ps |
| CPU time | 336.69 seconds |
| Started | Aug 13 06:50:55 PM PDT 24 |
| Finished | Aug 13 06:56:31 PM PDT 24 |
| Peak memory | 603388 kb |
| Host | smart-d81ab62a-a4c7-4a0f-89eb-9a812b1005d9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4225450812 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.chip_tl_errors.4225450812 |
| Directory | /workspace/7.chip_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/7.xbar_access_same_device.1275599283 |
| Short name | T1766 |
| Test name | |
| Test status | |
| Simulation time | 1859407588 ps |
| CPU time | 67.77 seconds |
| Started | Aug 13 06:50:53 PM PDT 24 |
| Finished | Aug 13 06:52:01 PM PDT 24 |
| Peak memory | 575688 kb |
| Host | smart-e9a646d3-ca49-417e-9617-b687a7120cf7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1275599283 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.xbar_access_same_device. 1275599283 |
| Directory | /workspace/7.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/7.xbar_access_same_device_slow_rsp.2095834426 |
| Short name | T2686 |
| Test name | |
| Test status | |
| Simulation time | 2675644015 ps |
| CPU time | 45.65 seconds |
| Started | Aug 13 06:50:58 PM PDT 24 |
| Finished | Aug 13 06:51:44 PM PDT 24 |
| Peak memory | 574372 kb |
| Host | smart-8f21dc7e-bcf5-43e9-b7a4-951ef1fb50b9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2095834426 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.xbar_access_same_d evice_slow_rsp.2095834426 |
| Directory | /workspace/7.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/7.xbar_error_and_unmapped_addr.3441422936 |
| Short name | T1420 |
| Test name | |
| Test status | |
| Simulation time | 432589788 ps |
| CPU time | 17.66 seconds |
| Started | Aug 13 06:51:04 PM PDT 24 |
| Finished | Aug 13 06:51:22 PM PDT 24 |
| Peak memory | 575732 kb |
| Host | smart-577bbe2d-ed72-480f-bac7-9b134dc75e24 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3441422936 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.xbar_error_and_unmapped_addr .3441422936 |
| Directory | /workspace/7.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/7.xbar_error_random.4096151640 |
| Short name | T1498 |
| Test name | |
| Test status | |
| Simulation time | 413448159 ps |
| CPU time | 32.71 seconds |
| Started | Aug 13 06:51:01 PM PDT 24 |
| Finished | Aug 13 06:51:34 PM PDT 24 |
| Peak memory | 575504 kb |
| Host | smart-1ec63666-11b5-48a8-975f-7a7848cabd88 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4096151640 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.xbar_error_random.4096151640 |
| Directory | /workspace/7.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/7.xbar_random.3209541756 |
| Short name | T1524 |
| Test name | |
| Test status | |
| Simulation time | 125464559 ps |
| CPU time | 7.22 seconds |
| Started | Aug 13 06:50:55 PM PDT 24 |
| Finished | Aug 13 06:51:02 PM PDT 24 |
| Peak memory | 573600 kb |
| Host | smart-56ee7c80-b171-4b08-807b-49781b5fe73a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3209541756 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.xbar_random.3209541756 |
| Directory | /workspace/7.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/7.xbar_random_large_delays.2400053802 |
| Short name | T1763 |
| Test name | |
| Test status | |
| Simulation time | 56421904537 ps |
| CPU time | 584.86 seconds |
| Started | Aug 13 06:50:56 PM PDT 24 |
| Finished | Aug 13 07:00:41 PM PDT 24 |
| Peak memory | 575644 kb |
| Host | smart-71026538-c327-46a8-96ea-7c97a9b5ade8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2400053802 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.xbar_random_large_delays.2400053802 |
| Directory | /workspace/7.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/7.xbar_random_slow_rsp.4032054357 |
| Short name | T2244 |
| Test name | |
| Test status | |
| Simulation time | 52375272773 ps |
| CPU time | 946.99 seconds |
| Started | Aug 13 06:51:06 PM PDT 24 |
| Finished | Aug 13 07:06:53 PM PDT 24 |
| Peak memory | 575732 kb |
| Host | smart-fec9d585-96d9-486e-b04a-9e2301ea4807 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4032054357 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.xbar_random_slow_rsp.4032054357 |
| Directory | /workspace/7.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/7.xbar_random_zero_delays.3982571487 |
| Short name | T2127 |
| Test name | |
| Test status | |
| Simulation time | 188362924 ps |
| CPU time | 17.98 seconds |
| Started | Aug 13 06:51:11 PM PDT 24 |
| Finished | Aug 13 06:51:29 PM PDT 24 |
| Peak memory | 575604 kb |
| Host | smart-abccd38f-1545-48f5-b959-089bc98f7838 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3982571487 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.xbar_random_zero_dela ys.3982571487 |
| Directory | /workspace/7.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/7.xbar_same_source.2369537398 |
| Short name | T437 |
| Test name | |
| Test status | |
| Simulation time | 525946182 ps |
| CPU time | 33.32 seconds |
| Started | Aug 13 06:51:07 PM PDT 24 |
| Finished | Aug 13 06:51:40 PM PDT 24 |
| Peak memory | 575624 kb |
| Host | smart-57a8fcb4-2ed9-4d51-847c-37796bb9b1e8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2369537398 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.xbar_same_source.2369537398 |
| Directory | /workspace/7.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/7.xbar_smoke.962399577 |
| Short name | T520 |
| Test name | |
| Test status | |
| Simulation time | 182125280 ps |
| CPU time | 8.85 seconds |
| Started | Aug 13 06:50:57 PM PDT 24 |
| Finished | Aug 13 06:51:06 PM PDT 24 |
| Peak memory | 573576 kb |
| Host | smart-0db6f435-ca92-4ed5-ae2f-c8b8371c33e3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=962399577 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.xbar_smoke.962399577 |
| Directory | /workspace/7.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/7.xbar_smoke_large_delays.2907776920 |
| Short name | T2263 |
| Test name | |
| Test status | |
| Simulation time | 7272163435 ps |
| CPU time | 74.82 seconds |
| Started | Aug 13 06:51:06 PM PDT 24 |
| Finished | Aug 13 06:52:21 PM PDT 24 |
| Peak memory | 573636 kb |
| Host | smart-c3989095-af5f-42f2-ac08-1ad5e81e9331 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2907776920 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.xbar_smoke_large_delays.2907776920 |
| Directory | /workspace/7.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/7.xbar_smoke_slow_rsp.295991976 |
| Short name | T2670 |
| Test name | |
| Test status | |
| Simulation time | 4831647722 ps |
| CPU time | 73.38 seconds |
| Started | Aug 13 06:50:58 PM PDT 24 |
| Finished | Aug 13 06:52:11 PM PDT 24 |
| Peak memory | 574280 kb |
| Host | smart-65699106-b8c5-4366-97c3-a04e123a616d |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=295991976 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.xbar_smoke_slow_rsp.295991976 |
| Directory | /workspace/7.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/7.xbar_smoke_zero_delays.3213132287 |
| Short name | T2567 |
| Test name | |
| Test status | |
| Simulation time | 35923534 ps |
| CPU time | 5.77 seconds |
| Started | Aug 13 06:51:06 PM PDT 24 |
| Finished | Aug 13 06:51:12 PM PDT 24 |
| Peak memory | 574176 kb |
| Host | smart-937beb96-bc4b-4214-b69d-d83cfadebdb8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3213132287 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.xbar_smoke_zero_delays .3213132287 |
| Directory | /workspace/7.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/7.xbar_stress_all.3028104317 |
| Short name | T510 |
| Test name | |
| Test status | |
| Simulation time | 12471837295 ps |
| CPU time | 470.33 seconds |
| Started | Aug 13 06:51:13 PM PDT 24 |
| Finished | Aug 13 06:59:03 PM PDT 24 |
| Peak memory | 576540 kb |
| Host | smart-21e1548d-a9cd-42e7-9630-138c352f31f7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3028104317 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.xbar_stress_all.3028104317 |
| Directory | /workspace/7.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/7.xbar_stress_all_with_error.3482711762 |
| Short name | T1938 |
| Test name | |
| Test status | |
| Simulation time | 10179246249 ps |
| CPU time | 389.76 seconds |
| Started | Aug 13 06:50:57 PM PDT 24 |
| Finished | Aug 13 06:57:27 PM PDT 24 |
| Peak memory | 576580 kb |
| Host | smart-50358cab-cda7-4330-8c9d-6241925f2a1d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3482711762 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.xbar_stress_all_with_error.3482711762 |
| Directory | /workspace/7.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/7.xbar_stress_all_with_rand_reset.1556162908 |
| Short name | T2884 |
| Test name | |
| Test status | |
| Simulation time | 6017055806 ps |
| CPU time | 691.61 seconds |
| Started | Aug 13 06:51:01 PM PDT 24 |
| Finished | Aug 13 07:02:33 PM PDT 24 |
| Peak memory | 578636 kb |
| Host | smart-94e3cc61-ef0f-4c62-bc91-ac9edb96950e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1556162908 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.xbar_stress_all_ with_rand_reset.1556162908 |
| Directory | /workspace/7.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/7.xbar_stress_all_with_reset_error.1735588339 |
| Short name | T2330 |
| Test name | |
| Test status | |
| Simulation time | 5748681149 ps |
| CPU time | 289.62 seconds |
| Started | Aug 13 06:50:59 PM PDT 24 |
| Finished | Aug 13 06:55:49 PM PDT 24 |
| Peak memory | 576548 kb |
| Host | smart-bb32c8e2-53c9-4fd4-bf92-c8fb942c3de6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1735588339 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.xbar_stress_all _with_reset_error.1735588339 |
| Directory | /workspace/7.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/7.xbar_unmapped_addr.3721420234 |
| Short name | T2210 |
| Test name | |
| Test status | |
| Simulation time | 805642805 ps |
| CPU time | 36.37 seconds |
| Started | Aug 13 06:51:11 PM PDT 24 |
| Finished | Aug 13 06:51:48 PM PDT 24 |
| Peak memory | 575656 kb |
| Host | smart-9928ebfe-582e-4759-b432-17551cf564e4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3721420234 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.xbar_unmapped_addr.3721420234 |
| Directory | /workspace/7.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/70.xbar_access_same_device.2961128951 |
| Short name | T1668 |
| Test name | |
| Test status | |
| Simulation time | 337431941 ps |
| CPU time | 15.29 seconds |
| Started | Aug 13 06:57:31 PM PDT 24 |
| Finished | Aug 13 06:57:46 PM PDT 24 |
| Peak memory | 575596 kb |
| Host | smart-3d431dae-bdb9-4e40-8332-507c4ba13bfc |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2961128951 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 70.xbar_access_same_device .2961128951 |
| Directory | /workspace/70.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/70.xbar_access_same_device_slow_rsp.1237482617 |
| Short name | T560 |
| Test name | |
| Test status | |
| Simulation time | 89146560147 ps |
| CPU time | 1656.65 seconds |
| Started | Aug 13 06:57:28 PM PDT 24 |
| Finished | Aug 13 07:25:05 PM PDT 24 |
| Peak memory | 575756 kb |
| Host | smart-671ba88e-77fb-4fae-9e28-81fee50cb679 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1237482617 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 70.xbar_access_same_ device_slow_rsp.1237482617 |
| Directory | /workspace/70.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/70.xbar_error_and_unmapped_addr.4070219232 |
| Short name | T1486 |
| Test name | |
| Test status | |
| Simulation time | 215553400 ps |
| CPU time | 24.38 seconds |
| Started | Aug 13 06:57:35 PM PDT 24 |
| Finished | Aug 13 06:57:59 PM PDT 24 |
| Peak memory | 575632 kb |
| Host | smart-af050430-f9fd-4a4f-9cf0-648afe5bb982 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4070219232 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 70.xbar_error_and_unmapped_add r.4070219232 |
| Directory | /workspace/70.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/70.xbar_error_random.3368640031 |
| Short name | T1955 |
| Test name | |
| Test status | |
| Simulation time | 328000544 ps |
| CPU time | 28.38 seconds |
| Started | Aug 13 06:57:28 PM PDT 24 |
| Finished | Aug 13 06:57:57 PM PDT 24 |
| Peak memory | 575724 kb |
| Host | smart-eee040ed-4db4-4698-b739-2a8d38297cd7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3368640031 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 70.xbar_error_random.3368640031 |
| Directory | /workspace/70.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/70.xbar_random.2288101239 |
| Short name | T537 |
| Test name | |
| Test status | |
| Simulation time | 581403504 ps |
| CPU time | 50.81 seconds |
| Started | Aug 13 06:57:29 PM PDT 24 |
| Finished | Aug 13 06:58:20 PM PDT 24 |
| Peak memory | 575716 kb |
| Host | smart-0a20ddfa-43fb-4a4f-bdb9-f1f1668ff3db |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2288101239 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 70.xbar_random.2288101239 |
| Directory | /workspace/70.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/70.xbar_random_large_delays.4025332637 |
| Short name | T1900 |
| Test name | |
| Test status | |
| Simulation time | 110064575046 ps |
| CPU time | 1353.65 seconds |
| Started | Aug 13 06:57:28 PM PDT 24 |
| Finished | Aug 13 07:20:02 PM PDT 24 |
| Peak memory | 575764 kb |
| Host | smart-2f0a002c-cc6b-4668-89f1-f8f937548104 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4025332637 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 70.xbar_random_large_delays.4025332637 |
| Directory | /workspace/70.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/70.xbar_random_slow_rsp.1277024164 |
| Short name | T1529 |
| Test name | |
| Test status | |
| Simulation time | 20355510964 ps |
| CPU time | 323.23 seconds |
| Started | Aug 13 06:57:28 PM PDT 24 |
| Finished | Aug 13 07:02:51 PM PDT 24 |
| Peak memory | 575780 kb |
| Host | smart-c2d7f8c0-522c-40ed-bcf0-ef07f69992f9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1277024164 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 70.xbar_random_slow_rsp.1277024164 |
| Directory | /workspace/70.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/70.xbar_random_zero_delays.1713865254 |
| Short name | T2056 |
| Test name | |
| Test status | |
| Simulation time | 368477726 ps |
| CPU time | 31.45 seconds |
| Started | Aug 13 06:57:29 PM PDT 24 |
| Finished | Aug 13 06:58:01 PM PDT 24 |
| Peak memory | 575784 kb |
| Host | smart-9bb9d98d-fb9d-4b8b-b4c9-20db0b5202bf |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1713865254 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 70.xbar_random_zero_del ays.1713865254 |
| Directory | /workspace/70.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/70.xbar_same_source.297927721 |
| Short name | T1731 |
| Test name | |
| Test status | |
| Simulation time | 138871436 ps |
| CPU time | 11.48 seconds |
| Started | Aug 13 06:57:28 PM PDT 24 |
| Finished | Aug 13 06:57:39 PM PDT 24 |
| Peak memory | 575568 kb |
| Host | smart-e9dbdbd7-be33-4116-9aec-5911c64711bd |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=297927721 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 70.xbar_same_source.297927721 |
| Directory | /workspace/70.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/70.xbar_smoke.2349077366 |
| Short name | T1459 |
| Test name | |
| Test status | |
| Simulation time | 169526150 ps |
| CPU time | 8.6 seconds |
| Started | Aug 13 06:57:26 PM PDT 24 |
| Finished | Aug 13 06:57:35 PM PDT 24 |
| Peak memory | 574236 kb |
| Host | smart-28e359b7-7aa5-4aa3-9f10-68a02cb2c1b9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2349077366 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 70.xbar_smoke.2349077366 |
| Directory | /workspace/70.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/70.xbar_smoke_large_delays.3282003559 |
| Short name | T2546 |
| Test name | |
| Test status | |
| Simulation time | 6511281843 ps |
| CPU time | 69.06 seconds |
| Started | Aug 13 06:57:31 PM PDT 24 |
| Finished | Aug 13 06:58:40 PM PDT 24 |
| Peak memory | 574252 kb |
| Host | smart-9f24a670-9d94-4c40-906e-f4992b24216c |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3282003559 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 70.xbar_smoke_large_delays.3282003559 |
| Directory | /workspace/70.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/70.xbar_smoke_slow_rsp.1678012215 |
| Short name | T1537 |
| Test name | |
| Test status | |
| Simulation time | 6021695268 ps |
| CPU time | 97.93 seconds |
| Started | Aug 13 06:57:31 PM PDT 24 |
| Finished | Aug 13 06:59:09 PM PDT 24 |
| Peak memory | 574308 kb |
| Host | smart-89795517-d7d9-4f02-aee2-ded88c5e5f87 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1678012215 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 70.xbar_smoke_slow_rsp.1678012215 |
| Directory | /workspace/70.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/70.xbar_smoke_zero_delays.3236080825 |
| Short name | T2931 |
| Test name | |
| Test status | |
| Simulation time | 53118438 ps |
| CPU time | 6.53 seconds |
| Started | Aug 13 06:57:30 PM PDT 24 |
| Finished | Aug 13 06:57:37 PM PDT 24 |
| Peak memory | 573460 kb |
| Host | smart-84efb421-f159-44ca-8726-284526f608fa |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3236080825 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 70.xbar_smoke_zero_delay s.3236080825 |
| Directory | /workspace/70.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/70.xbar_stress_all.3632704583 |
| Short name | T2873 |
| Test name | |
| Test status | |
| Simulation time | 10785499746 ps |
| CPU time | 365.66 seconds |
| Started | Aug 13 06:57:36 PM PDT 24 |
| Finished | Aug 13 07:03:42 PM PDT 24 |
| Peak memory | 575724 kb |
| Host | smart-41512234-4658-4844-bea4-4934ec24b3dc |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3632704583 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 70.xbar_stress_all.3632704583 |
| Directory | /workspace/70.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/70.xbar_stress_all_with_error.2199732366 |
| Short name | T1681 |
| Test name | |
| Test status | |
| Simulation time | 7996711818 ps |
| CPU time | 244.73 seconds |
| Started | Aug 13 06:57:37 PM PDT 24 |
| Finished | Aug 13 07:01:41 PM PDT 24 |
| Peak memory | 575884 kb |
| Host | smart-9345d06f-a58b-47d0-88d7-cc55dd8a18f8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2199732366 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 70.xbar_stress_all_with_error.2199732366 |
| Directory | /workspace/70.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/70.xbar_stress_all_with_rand_reset.2734192660 |
| Short name | T669 |
| Test name | |
| Test status | |
| Simulation time | 180211000 ps |
| CPU time | 71.11 seconds |
| Started | Aug 13 06:57:36 PM PDT 24 |
| Finished | Aug 13 06:58:47 PM PDT 24 |
| Peak memory | 575672 kb |
| Host | smart-f933623e-77e0-44cf-84fb-9404fdbd8165 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2734192660 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 70.xbar_stress_all _with_rand_reset.2734192660 |
| Directory | /workspace/70.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/70.xbar_stress_all_with_reset_error.2347306488 |
| Short name | T901 |
| Test name | |
| Test status | |
| Simulation time | 862614613 ps |
| CPU time | 227.89 seconds |
| Started | Aug 13 06:57:37 PM PDT 24 |
| Finished | Aug 13 07:01:25 PM PDT 24 |
| Peak memory | 576512 kb |
| Host | smart-9f442a26-1e41-4da1-ad37-d15b10367148 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2347306488 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 70.xbar_stress_al l_with_reset_error.2347306488 |
| Directory | /workspace/70.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/70.xbar_unmapped_addr.3998352426 |
| Short name | T2936 |
| Test name | |
| Test status | |
| Simulation time | 1013088317 ps |
| CPU time | 40.26 seconds |
| Started | Aug 13 06:57:34 PM PDT 24 |
| Finished | Aug 13 06:58:15 PM PDT 24 |
| Peak memory | 575712 kb |
| Host | smart-8e5fa2ac-41ab-4881-90e4-1d0d9570dae9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3998352426 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 70.xbar_unmapped_addr.3998352426 |
| Directory | /workspace/70.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/71.xbar_access_same_device.4106493103 |
| Short name | T2866 |
| Test name | |
| Test status | |
| Simulation time | 693486855 ps |
| CPU time | 33.57 seconds |
| Started | Aug 13 06:57:35 PM PDT 24 |
| Finished | Aug 13 06:58:09 PM PDT 24 |
| Peak memory | 575540 kb |
| Host | smart-3138321c-cd0b-4aa8-9539-0d86e7da6769 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4106493103 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 71.xbar_access_same_device .4106493103 |
| Directory | /workspace/71.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/71.xbar_access_same_device_slow_rsp.1450321481 |
| Short name | T632 |
| Test name | |
| Test status | |
| Simulation time | 29554923478 ps |
| CPU time | 516.84 seconds |
| Started | Aug 13 06:57:36 PM PDT 24 |
| Finished | Aug 13 07:06:14 PM PDT 24 |
| Peak memory | 576496 kb |
| Host | smart-fa8911ff-8443-4bae-9d5f-ddefb6796e38 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1450321481 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 71.xbar_access_same_ device_slow_rsp.1450321481 |
| Directory | /workspace/71.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/71.xbar_error_and_unmapped_addr.2511036352 |
| Short name | T2081 |
| Test name | |
| Test status | |
| Simulation time | 781251812 ps |
| CPU time | 32.28 seconds |
| Started | Aug 13 06:57:46 PM PDT 24 |
| Finished | Aug 13 06:58:18 PM PDT 24 |
| Peak memory | 575676 kb |
| Host | smart-0145f238-838f-4da1-bf6c-2c23c9a92e64 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2511036352 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 71.xbar_error_and_unmapped_add r.2511036352 |
| Directory | /workspace/71.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/71.xbar_error_random.1697861920 |
| Short name | T1816 |
| Test name | |
| Test status | |
| Simulation time | 756708601 ps |
| CPU time | 31.41 seconds |
| Started | Aug 13 06:57:43 PM PDT 24 |
| Finished | Aug 13 06:58:14 PM PDT 24 |
| Peak memory | 575708 kb |
| Host | smart-7e5e75e8-5e3d-49b0-83b6-09a1f91e8373 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1697861920 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 71.xbar_error_random.1697861920 |
| Directory | /workspace/71.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/71.xbar_random.4218161084 |
| Short name | T2451 |
| Test name | |
| Test status | |
| Simulation time | 156171353 ps |
| CPU time | 14.21 seconds |
| Started | Aug 13 06:57:35 PM PDT 24 |
| Finished | Aug 13 06:57:49 PM PDT 24 |
| Peak memory | 575600 kb |
| Host | smart-a0dce24f-56bc-4365-afe9-33ce976a0d7d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4218161084 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 71.xbar_random.4218161084 |
| Directory | /workspace/71.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/71.xbar_random_large_delays.1894575181 |
| Short name | T655 |
| Test name | |
| Test status | |
| Simulation time | 60066825996 ps |
| CPU time | 695.55 seconds |
| Started | Aug 13 06:57:33 PM PDT 24 |
| Finished | Aug 13 07:09:09 PM PDT 24 |
| Peak memory | 575564 kb |
| Host | smart-34c59657-cd03-4de5-be14-d4b8c0563259 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1894575181 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 71.xbar_random_large_delays.1894575181 |
| Directory | /workspace/71.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/71.xbar_random_slow_rsp.1126457992 |
| Short name | T2051 |
| Test name | |
| Test status | |
| Simulation time | 44009850761 ps |
| CPU time | 790.82 seconds |
| Started | Aug 13 06:57:35 PM PDT 24 |
| Finished | Aug 13 07:10:46 PM PDT 24 |
| Peak memory | 575636 kb |
| Host | smart-a3b908e6-2e2a-46c4-b495-b317ec637552 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1126457992 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 71.xbar_random_slow_rsp.1126457992 |
| Directory | /workspace/71.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/71.xbar_random_zero_delays.1934132098 |
| Short name | T2414 |
| Test name | |
| Test status | |
| Simulation time | 562018321 ps |
| CPU time | 55.27 seconds |
| Started | Aug 13 06:57:35 PM PDT 24 |
| Finished | Aug 13 06:58:31 PM PDT 24 |
| Peak memory | 575524 kb |
| Host | smart-d08ffd7d-e038-489d-a4f8-96fb15db4810 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1934132098 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 71.xbar_random_zero_del ays.1934132098 |
| Directory | /workspace/71.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/71.xbar_same_source.3760623187 |
| Short name | T2569 |
| Test name | |
| Test status | |
| Simulation time | 186296705 ps |
| CPU time | 17.08 seconds |
| Started | Aug 13 06:57:35 PM PDT 24 |
| Finished | Aug 13 06:57:53 PM PDT 24 |
| Peak memory | 575560 kb |
| Host | smart-f8cfa25c-c514-4f9d-b662-30b260518478 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3760623187 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 71.xbar_same_source.3760623187 |
| Directory | /workspace/71.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/71.xbar_smoke.3916063371 |
| Short name | T1614 |
| Test name | |
| Test status | |
| Simulation time | 45039661 ps |
| CPU time | 6.56 seconds |
| Started | Aug 13 06:57:34 PM PDT 24 |
| Finished | Aug 13 06:57:41 PM PDT 24 |
| Peak memory | 573548 kb |
| Host | smart-aa1db326-9ee5-4eaa-9410-1fff3f312f5d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3916063371 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 71.xbar_smoke.3916063371 |
| Directory | /workspace/71.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/71.xbar_smoke_large_delays.945209052 |
| Short name | T1935 |
| Test name | |
| Test status | |
| Simulation time | 7658438391 ps |
| CPU time | 77.32 seconds |
| Started | Aug 13 06:57:36 PM PDT 24 |
| Finished | Aug 13 06:58:54 PM PDT 24 |
| Peak memory | 573696 kb |
| Host | smart-bd27e51f-ce4b-4adc-9e2f-013691b3a46c |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=945209052 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 71.xbar_smoke_large_delays.945209052 |
| Directory | /workspace/71.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/71.xbar_smoke_slow_rsp.2966052391 |
| Short name | T2128 |
| Test name | |
| Test status | |
| Simulation time | 4813543919 ps |
| CPU time | 77.49 seconds |
| Started | Aug 13 06:57:36 PM PDT 24 |
| Finished | Aug 13 06:58:53 PM PDT 24 |
| Peak memory | 573688 kb |
| Host | smart-ddd839af-d9c5-46c5-ba62-b85707e1c3a8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2966052391 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 71.xbar_smoke_slow_rsp.2966052391 |
| Directory | /workspace/71.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/71.xbar_smoke_zero_delays.3176186197 |
| Short name | T2441 |
| Test name | |
| Test status | |
| Simulation time | 41224540 ps |
| CPU time | 5.93 seconds |
| Started | Aug 13 06:57:37 PM PDT 24 |
| Finished | Aug 13 06:57:43 PM PDT 24 |
| Peak memory | 573496 kb |
| Host | smart-6da00836-4a7f-466b-8813-e4ef30f626ea |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3176186197 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 71.xbar_smoke_zero_delay s.3176186197 |
| Directory | /workspace/71.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/71.xbar_stress_all.2802507207 |
| Short name | T2561 |
| Test name | |
| Test status | |
| Simulation time | 1323278451 ps |
| CPU time | 55.13 seconds |
| Started | Aug 13 06:57:43 PM PDT 24 |
| Finished | Aug 13 06:58:38 PM PDT 24 |
| Peak memory | 575628 kb |
| Host | smart-7393e2a5-0750-4094-a536-ce7bba5ea63f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2802507207 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 71.xbar_stress_all.2802507207 |
| Directory | /workspace/71.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/71.xbar_stress_all_with_error.4235038730 |
| Short name | T773 |
| Test name | |
| Test status | |
| Simulation time | 10923820220 ps |
| CPU time | 344.26 seconds |
| Started | Aug 13 06:57:42 PM PDT 24 |
| Finished | Aug 13 07:03:26 PM PDT 24 |
| Peak memory | 575864 kb |
| Host | smart-1f67df27-93a7-4cfe-8391-676a8bb4e257 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4235038730 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 71.xbar_stress_all_with_error.4235038730 |
| Directory | /workspace/71.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/71.xbar_stress_all_with_rand_reset.2877259064 |
| Short name | T2793 |
| Test name | |
| Test status | |
| Simulation time | 11347579603 ps |
| CPU time | 575.05 seconds |
| Started | Aug 13 06:57:45 PM PDT 24 |
| Finished | Aug 13 07:07:21 PM PDT 24 |
| Peak memory | 576508 kb |
| Host | smart-32b99dbb-66c6-4c07-9d89-ba0ab98a5fd9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2877259064 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 71.xbar_stress_all _with_rand_reset.2877259064 |
| Directory | /workspace/71.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/71.xbar_stress_all_with_reset_error.26408059 |
| Short name | T2028 |
| Test name | |
| Test status | |
| Simulation time | 538918881 ps |
| CPU time | 56.85 seconds |
| Started | Aug 13 06:57:44 PM PDT 24 |
| Finished | Aug 13 06:58:41 PM PDT 24 |
| Peak memory | 575660 kb |
| Host | smart-568b1502-f631-4e31-8608-b98fbf7052bb |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26408059 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_res et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 71.xbar_stress_all_ with_reset_error.26408059 |
| Directory | /workspace/71.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/71.xbar_unmapped_addr.3367447850 |
| Short name | T2913 |
| Test name | |
| Test status | |
| Simulation time | 225031914 ps |
| CPU time | 11.89 seconds |
| Started | Aug 13 06:57:44 PM PDT 24 |
| Finished | Aug 13 06:57:56 PM PDT 24 |
| Peak memory | 575576 kb |
| Host | smart-57821d9d-a740-4113-a4f7-55ccb94c0993 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3367447850 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 71.xbar_unmapped_addr.3367447850 |
| Directory | /workspace/71.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/72.xbar_access_same_device.4286633984 |
| Short name | T2121 |
| Test name | |
| Test status | |
| Simulation time | 722684670 ps |
| CPU time | 67.82 seconds |
| Started | Aug 13 06:57:42 PM PDT 24 |
| Finished | Aug 13 06:58:50 PM PDT 24 |
| Peak memory | 575716 kb |
| Host | smart-06474788-d7c0-41e9-973d-22a928db8118 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4286633984 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 72.xbar_access_same_device .4286633984 |
| Directory | /workspace/72.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/72.xbar_access_same_device_slow_rsp.2467188178 |
| Short name | T879 |
| Test name | |
| Test status | |
| Simulation time | 27663086541 ps |
| CPU time | 494.59 seconds |
| Started | Aug 13 06:57:43 PM PDT 24 |
| Finished | Aug 13 07:05:58 PM PDT 24 |
| Peak memory | 575604 kb |
| Host | smart-e7e44f2f-4699-4ac8-bdd9-5f7760893a40 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2467188178 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 72.xbar_access_same_ device_slow_rsp.2467188178 |
| Directory | /workspace/72.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/72.xbar_error_and_unmapped_addr.2033710755 |
| Short name | T1508 |
| Test name | |
| Test status | |
| Simulation time | 107047550 ps |
| CPU time | 12.81 seconds |
| Started | Aug 13 06:57:46 PM PDT 24 |
| Finished | Aug 13 06:57:59 PM PDT 24 |
| Peak memory | 575684 kb |
| Host | smart-f6400723-5f2f-4777-a534-d438fedc5ae0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2033710755 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 72.xbar_error_and_unmapped_add r.2033710755 |
| Directory | /workspace/72.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/72.xbar_error_random.3109927340 |
| Short name | T1444 |
| Test name | |
| Test status | |
| Simulation time | 1736907933 ps |
| CPU time | 57.31 seconds |
| Started | Aug 13 06:57:46 PM PDT 24 |
| Finished | Aug 13 06:58:43 PM PDT 24 |
| Peak memory | 575744 kb |
| Host | smart-55f8abe1-ad77-4fff-b2d8-e863e3312425 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3109927340 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 72.xbar_error_random.3109927340 |
| Directory | /workspace/72.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/72.xbar_random.2621859739 |
| Short name | T2234 |
| Test name | |
| Test status | |
| Simulation time | 240828562 ps |
| CPU time | 24.32 seconds |
| Started | Aug 13 06:57:43 PM PDT 24 |
| Finished | Aug 13 06:58:08 PM PDT 24 |
| Peak memory | 575600 kb |
| Host | smart-d6618464-9a7b-4ee3-ba5b-a76a1a7c60ef |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2621859739 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 72.xbar_random.2621859739 |
| Directory | /workspace/72.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/72.xbar_random_large_delays.2305675435 |
| Short name | T2737 |
| Test name | |
| Test status | |
| Simulation time | 73675405014 ps |
| CPU time | 820.08 seconds |
| Started | Aug 13 06:57:43 PM PDT 24 |
| Finished | Aug 13 07:11:24 PM PDT 24 |
| Peak memory | 575796 kb |
| Host | smart-eb552b87-d44e-489d-8362-226497bb9f3a |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2305675435 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 72.xbar_random_large_delays.2305675435 |
| Directory | /workspace/72.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/72.xbar_random_slow_rsp.3414420148 |
| Short name | T1920 |
| Test name | |
| Test status | |
| Simulation time | 25377766362 ps |
| CPU time | 468.62 seconds |
| Started | Aug 13 06:57:45 PM PDT 24 |
| Finished | Aug 13 07:05:34 PM PDT 24 |
| Peak memory | 575692 kb |
| Host | smart-93acd452-9afe-49a9-aa19-afdb907ef0a3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3414420148 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 72.xbar_random_slow_rsp.3414420148 |
| Directory | /workspace/72.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/72.xbar_random_zero_delays.91327841 |
| Short name | T2581 |
| Test name | |
| Test status | |
| Simulation time | 330231879 ps |
| CPU time | 29.95 seconds |
| Started | Aug 13 06:57:44 PM PDT 24 |
| Finished | Aug 13 06:58:14 PM PDT 24 |
| Peak memory | 575480 kb |
| Host | smart-2476be78-2cf2-475b-a264-c27f37e33e43 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=91327841 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 72.xbar_random_zero_delay s.91327841 |
| Directory | /workspace/72.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/72.xbar_same_source.2107659146 |
| Short name | T2105 |
| Test name | |
| Test status | |
| Simulation time | 118949326 ps |
| CPU time | 11.95 seconds |
| Started | Aug 13 06:57:44 PM PDT 24 |
| Finished | Aug 13 06:57:56 PM PDT 24 |
| Peak memory | 575572 kb |
| Host | smart-6857d780-ff09-4e46-b6ec-375926e486ef |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2107659146 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 72.xbar_same_source.2107659146 |
| Directory | /workspace/72.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/72.xbar_smoke.3396926254 |
| Short name | T2120 |
| Test name | |
| Test status | |
| Simulation time | 233661482 ps |
| CPU time | 9.97 seconds |
| Started | Aug 13 06:57:43 PM PDT 24 |
| Finished | Aug 13 06:57:53 PM PDT 24 |
| Peak memory | 573508 kb |
| Host | smart-27935249-5c05-48e2-a6a3-baadda1664ed |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3396926254 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 72.xbar_smoke.3396926254 |
| Directory | /workspace/72.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/72.xbar_smoke_large_delays.3029704850 |
| Short name | T2484 |
| Test name | |
| Test status | |
| Simulation time | 10258865293 ps |
| CPU time | 104.05 seconds |
| Started | Aug 13 06:57:51 PM PDT 24 |
| Finished | Aug 13 06:59:35 PM PDT 24 |
| Peak memory | 573596 kb |
| Host | smart-976195a6-c787-485b-aba0-7a3a5165a91e |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3029704850 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 72.xbar_smoke_large_delays.3029704850 |
| Directory | /workspace/72.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/72.xbar_smoke_slow_rsp.2946415473 |
| Short name | T2308 |
| Test name | |
| Test status | |
| Simulation time | 4552952749 ps |
| CPU time | 77.95 seconds |
| Started | Aug 13 06:57:43 PM PDT 24 |
| Finished | Aug 13 06:59:01 PM PDT 24 |
| Peak memory | 573632 kb |
| Host | smart-3258949a-e0f2-40c5-9b4d-32f5fbdb4293 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2946415473 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 72.xbar_smoke_slow_rsp.2946415473 |
| Directory | /workspace/72.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/72.xbar_smoke_zero_delays.1656601371 |
| Short name | T687 |
| Test name | |
| Test status | |
| Simulation time | 53327714 ps |
| CPU time | 6.39 seconds |
| Started | Aug 13 06:57:52 PM PDT 24 |
| Finished | Aug 13 06:57:58 PM PDT 24 |
| Peak memory | 574200 kb |
| Host | smart-b965ee1c-66ee-436f-ba2a-ad760d9f4eb7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1656601371 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 72.xbar_smoke_zero_delay s.1656601371 |
| Directory | /workspace/72.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/72.xbar_stress_all.2242866528 |
| Short name | T642 |
| Test name | |
| Test status | |
| Simulation time | 1055443293 ps |
| CPU time | 83.3 seconds |
| Started | Aug 13 06:57:44 PM PDT 24 |
| Finished | Aug 13 06:59:07 PM PDT 24 |
| Peak memory | 576144 kb |
| Host | smart-f830e4f3-8c4f-43c1-be53-d39bb71d571a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2242866528 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 72.xbar_stress_all.2242866528 |
| Directory | /workspace/72.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/72.xbar_stress_all_with_error.3656771909 |
| Short name | T2317 |
| Test name | |
| Test status | |
| Simulation time | 11522841975 ps |
| CPU time | 379.8 seconds |
| Started | Aug 13 06:57:42 PM PDT 24 |
| Finished | Aug 13 07:04:02 PM PDT 24 |
| Peak memory | 576564 kb |
| Host | smart-6f4eaec5-8828-4f7a-946d-fda5b1c5ad08 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3656771909 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 72.xbar_stress_all_with_error.3656771909 |
| Directory | /workspace/72.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/72.xbar_stress_all_with_rand_reset.2561156753 |
| Short name | T2703 |
| Test name | |
| Test status | |
| Simulation time | 2116002613 ps |
| CPU time | 308.34 seconds |
| Started | Aug 13 06:57:44 PM PDT 24 |
| Finished | Aug 13 07:02:52 PM PDT 24 |
| Peak memory | 576480 kb |
| Host | smart-1acc48e2-7061-45fa-b607-8ea233d3956d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2561156753 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 72.xbar_stress_all _with_rand_reset.2561156753 |
| Directory | /workspace/72.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/72.xbar_unmapped_addr.3902741368 |
| Short name | T2706 |
| Test name | |
| Test status | |
| Simulation time | 606103556 ps |
| CPU time | 24.19 seconds |
| Started | Aug 13 06:57:51 PM PDT 24 |
| Finished | Aug 13 06:58:16 PM PDT 24 |
| Peak memory | 575696 kb |
| Host | smart-147d28cf-e23e-4941-8edb-7d6d7e156be0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3902741368 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 72.xbar_unmapped_addr.3902741368 |
| Directory | /workspace/72.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/73.xbar_access_same_device.229098994 |
| Short name | T2465 |
| Test name | |
| Test status | |
| Simulation time | 215051296 ps |
| CPU time | 22.8 seconds |
| Started | Aug 13 06:57:49 PM PDT 24 |
| Finished | Aug 13 06:58:12 PM PDT 24 |
| Peak memory | 575712 kb |
| Host | smart-c5bc6d0f-3229-4c05-ba81-edc13a7b8fd2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=229098994 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 73.xbar_access_same_device. 229098994 |
| Directory | /workspace/73.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/73.xbar_access_same_device_slow_rsp.4239199205 |
| Short name | T551 |
| Test name | |
| Test status | |
| Simulation time | 61243533789 ps |
| CPU time | 1236.91 seconds |
| Started | Aug 13 06:57:49 PM PDT 24 |
| Finished | Aug 13 07:18:26 PM PDT 24 |
| Peak memory | 575788 kb |
| Host | smart-b6f296ce-6cab-4a8b-956d-1aa645e1cd9d |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4239199205 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 73.xbar_access_same_ device_slow_rsp.4239199205 |
| Directory | /workspace/73.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/73.xbar_error_and_unmapped_addr.3494525359 |
| Short name | T2279 |
| Test name | |
| Test status | |
| Simulation time | 1342950154 ps |
| CPU time | 52.35 seconds |
| Started | Aug 13 06:57:51 PM PDT 24 |
| Finished | Aug 13 06:58:43 PM PDT 24 |
| Peak memory | 575608 kb |
| Host | smart-b42c0b75-d287-4e34-be76-50f01f86ceb1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3494525359 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 73.xbar_error_and_unmapped_add r.3494525359 |
| Directory | /workspace/73.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/73.xbar_error_random.392164074 |
| Short name | T2904 |
| Test name | |
| Test status | |
| Simulation time | 1938093050 ps |
| CPU time | 75.66 seconds |
| Started | Aug 13 06:57:49 PM PDT 24 |
| Finished | Aug 13 06:59:05 PM PDT 24 |
| Peak memory | 575528 kb |
| Host | smart-e2fef59a-085c-4759-8c19-06d440d2b063 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=392164074 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 73.xbar_error_random.392164074 |
| Directory | /workspace/73.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/73.xbar_random.2171852864 |
| Short name | T2499 |
| Test name | |
| Test status | |
| Simulation time | 134533493 ps |
| CPU time | 13.61 seconds |
| Started | Aug 13 06:57:53 PM PDT 24 |
| Finished | Aug 13 06:58:06 PM PDT 24 |
| Peak memory | 575676 kb |
| Host | smart-dc369289-ede8-4bf3-b9fb-247665f9eb3d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2171852864 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 73.xbar_random.2171852864 |
| Directory | /workspace/73.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/73.xbar_random_large_delays.1887925216 |
| Short name | T2416 |
| Test name | |
| Test status | |
| Simulation time | 10881620160 ps |
| CPU time | 107.88 seconds |
| Started | Aug 13 06:57:50 PM PDT 24 |
| Finished | Aug 13 06:59:38 PM PDT 24 |
| Peak memory | 575760 kb |
| Host | smart-b2820aea-46b3-42df-9767-c457ce173b89 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1887925216 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 73.xbar_random_large_delays.1887925216 |
| Directory | /workspace/73.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/73.xbar_random_slow_rsp.2788279347 |
| Short name | T621 |
| Test name | |
| Test status | |
| Simulation time | 55095203220 ps |
| CPU time | 1013.57 seconds |
| Started | Aug 13 06:57:50 PM PDT 24 |
| Finished | Aug 13 07:14:44 PM PDT 24 |
| Peak memory | 575560 kb |
| Host | smart-7ed32194-8128-4fc3-8ec3-ffd43f41bd72 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2788279347 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 73.xbar_random_slow_rsp.2788279347 |
| Directory | /workspace/73.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/73.xbar_random_zero_delays.3892721909 |
| Short name | T600 |
| Test name | |
| Test status | |
| Simulation time | 227449217 ps |
| CPU time | 23.95 seconds |
| Started | Aug 13 06:57:49 PM PDT 24 |
| Finished | Aug 13 06:58:13 PM PDT 24 |
| Peak memory | 575664 kb |
| Host | smart-8c0caa10-bb53-4895-ad7b-c62389951faf |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3892721909 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 73.xbar_random_zero_del ays.3892721909 |
| Directory | /workspace/73.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/73.xbar_same_source.2760557985 |
| Short name | T586 |
| Test name | |
| Test status | |
| Simulation time | 2243320297 ps |
| CPU time | 66.36 seconds |
| Started | Aug 13 06:57:49 PM PDT 24 |
| Finished | Aug 13 06:58:56 PM PDT 24 |
| Peak memory | 575576 kb |
| Host | smart-9bfcc65f-48c7-4b22-9733-a9d3837aeb43 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2760557985 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 73.xbar_same_source.2760557985 |
| Directory | /workspace/73.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/73.xbar_smoke.3411045175 |
| Short name | T564 |
| Test name | |
| Test status | |
| Simulation time | 214014040 ps |
| CPU time | 9.59 seconds |
| Started | Aug 13 06:57:45 PM PDT 24 |
| Finished | Aug 13 06:57:55 PM PDT 24 |
| Peak memory | 574228 kb |
| Host | smart-e9c71ee2-8d78-43ec-a021-bf4df18afaf2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3411045175 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 73.xbar_smoke.3411045175 |
| Directory | /workspace/73.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/73.xbar_smoke_large_delays.571717617 |
| Short name | T694 |
| Test name | |
| Test status | |
| Simulation time | 7536279729 ps |
| CPU time | 79.67 seconds |
| Started | Aug 13 06:57:55 PM PDT 24 |
| Finished | Aug 13 06:59:15 PM PDT 24 |
| Peak memory | 574336 kb |
| Host | smart-d5e1dc53-d0db-4c46-bf1e-5c9561bdce90 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=571717617 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 73.xbar_smoke_large_delays.571717617 |
| Directory | /workspace/73.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/73.xbar_smoke_slow_rsp.633929818 |
| Short name | T2055 |
| Test name | |
| Test status | |
| Simulation time | 4990108381 ps |
| CPU time | 84.67 seconds |
| Started | Aug 13 06:57:51 PM PDT 24 |
| Finished | Aug 13 06:59:16 PM PDT 24 |
| Peak memory | 573708 kb |
| Host | smart-57b2ac35-feaa-4306-8c9d-ecb7c41c371a |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=633929818 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 73.xbar_smoke_slow_rsp.633929818 |
| Directory | /workspace/73.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/73.xbar_smoke_zero_delays.3322775932 |
| Short name | T1782 |
| Test name | |
| Test status | |
| Simulation time | 46238101 ps |
| CPU time | 6.02 seconds |
| Started | Aug 13 06:57:49 PM PDT 24 |
| Finished | Aug 13 06:57:55 PM PDT 24 |
| Peak memory | 573508 kb |
| Host | smart-f1f36528-0584-483f-afa6-e7c4adf2b15c |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3322775932 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 73.xbar_smoke_zero_delay s.3322775932 |
| Directory | /workspace/73.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/73.xbar_stress_all.3931722798 |
| Short name | T530 |
| Test name | |
| Test status | |
| Simulation time | 10321416287 ps |
| CPU time | 365.85 seconds |
| Started | Aug 13 06:57:52 PM PDT 24 |
| Finished | Aug 13 07:03:58 PM PDT 24 |
| Peak memory | 575832 kb |
| Host | smart-04c2ecc2-b0b5-47fb-a09a-6d539cbf763a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3931722798 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 73.xbar_stress_all.3931722798 |
| Directory | /workspace/73.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/73.xbar_stress_all_with_error.1993442085 |
| Short name | T2634 |
| Test name | |
| Test status | |
| Simulation time | 2775010883 ps |
| CPU time | 230.85 seconds |
| Started | Aug 13 06:57:51 PM PDT 24 |
| Finished | Aug 13 07:01:42 PM PDT 24 |
| Peak memory | 575684 kb |
| Host | smart-134ab8fa-6183-40df-838a-bda84040b354 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1993442085 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 73.xbar_stress_all_with_error.1993442085 |
| Directory | /workspace/73.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/73.xbar_stress_all_with_rand_reset.3700585558 |
| Short name | T608 |
| Test name | |
| Test status | |
| Simulation time | 3152800194 ps |
| CPU time | 417.33 seconds |
| Started | Aug 13 06:57:52 PM PDT 24 |
| Finished | Aug 13 07:04:50 PM PDT 24 |
| Peak memory | 576556 kb |
| Host | smart-41b963cb-eb3f-4e44-b6c2-33eec46184af |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3700585558 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 73.xbar_stress_all _with_rand_reset.3700585558 |
| Directory | /workspace/73.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/73.xbar_stress_all_with_reset_error.2030618039 |
| Short name | T2565 |
| Test name | |
| Test status | |
| Simulation time | 7834860 ps |
| CPU time | 10.43 seconds |
| Started | Aug 13 06:57:49 PM PDT 24 |
| Finished | Aug 13 06:58:00 PM PDT 24 |
| Peak memory | 574256 kb |
| Host | smart-b6a3ad70-7133-4f9d-ac03-06d903d5ca27 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2030618039 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 73.xbar_stress_al l_with_reset_error.2030618039 |
| Directory | /workspace/73.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/73.xbar_unmapped_addr.1454916705 |
| Short name | T2562 |
| Test name | |
| Test status | |
| Simulation time | 1128580355 ps |
| CPU time | 52.13 seconds |
| Started | Aug 13 06:57:50 PM PDT 24 |
| Finished | Aug 13 06:58:42 PM PDT 24 |
| Peak memory | 575672 kb |
| Host | smart-e2281ef4-55ac-4ce7-82a8-e47f0885143d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1454916705 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 73.xbar_unmapped_addr.1454916705 |
| Directory | /workspace/73.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/74.xbar_access_same_device.2037269938 |
| Short name | T2155 |
| Test name | |
| Test status | |
| Simulation time | 104445714 ps |
| CPU time | 11.2 seconds |
| Started | Aug 13 06:57:59 PM PDT 24 |
| Finished | Aug 13 06:58:10 PM PDT 24 |
| Peak memory | 576360 kb |
| Host | smart-559456a6-8402-43c6-9a5b-65b8df109ad3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2037269938 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 74.xbar_access_same_device .2037269938 |
| Directory | /workspace/74.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/74.xbar_access_same_device_slow_rsp.2649698306 |
| Short name | T1995 |
| Test name | |
| Test status | |
| Simulation time | 177799153808 ps |
| CPU time | 3242.81 seconds |
| Started | Aug 13 06:57:57 PM PDT 24 |
| Finished | Aug 13 07:52:01 PM PDT 24 |
| Peak memory | 575956 kb |
| Host | smart-263f7d83-e6ca-4cc2-8fc8-58038883768a |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2649698306 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 74.xbar_access_same_ device_slow_rsp.2649698306 |
| Directory | /workspace/74.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/74.xbar_error_and_unmapped_addr.3877257892 |
| Short name | T1768 |
| Test name | |
| Test status | |
| Simulation time | 841587075 ps |
| CPU time | 32.49 seconds |
| Started | Aug 13 06:58:03 PM PDT 24 |
| Finished | Aug 13 06:58:35 PM PDT 24 |
| Peak memory | 575708 kb |
| Host | smart-01088b05-3117-4af4-a7f6-16daa69bd413 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3877257892 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 74.xbar_error_and_unmapped_add r.3877257892 |
| Directory | /workspace/74.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/74.xbar_error_random.316778860 |
| Short name | T1427 |
| Test name | |
| Test status | |
| Simulation time | 36414771 ps |
| CPU time | 6.34 seconds |
| Started | Aug 13 06:58:03 PM PDT 24 |
| Finished | Aug 13 06:58:09 PM PDT 24 |
| Peak memory | 573536 kb |
| Host | smart-36421653-0ec1-4acd-b1ad-5c8c1d4b7faf |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=316778860 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 74.xbar_error_random.316778860 |
| Directory | /workspace/74.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/74.xbar_random.2464539308 |
| Short name | T2712 |
| Test name | |
| Test status | |
| Simulation time | 571213650 ps |
| CPU time | 56.26 seconds |
| Started | Aug 13 06:57:57 PM PDT 24 |
| Finished | Aug 13 06:58:54 PM PDT 24 |
| Peak memory | 575516 kb |
| Host | smart-d0f41ecf-e00c-40ce-b5c4-746dfe01e8af |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2464539308 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 74.xbar_random.2464539308 |
| Directory | /workspace/74.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/74.xbar_random_large_delays.1338267689 |
| Short name | T1910 |
| Test name | |
| Test status | |
| Simulation time | 83901246277 ps |
| CPU time | 839.71 seconds |
| Started | Aug 13 06:58:01 PM PDT 24 |
| Finished | Aug 13 07:12:01 PM PDT 24 |
| Peak memory | 575648 kb |
| Host | smart-b3388397-a4a8-4a98-b0c1-f80a1802bcdf |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1338267689 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 74.xbar_random_large_delays.1338267689 |
| Directory | /workspace/74.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/74.xbar_random_slow_rsp.3459311844 |
| Short name | T1642 |
| Test name | |
| Test status | |
| Simulation time | 26567188833 ps |
| CPU time | 485.05 seconds |
| Started | Aug 13 06:57:57 PM PDT 24 |
| Finished | Aug 13 07:06:02 PM PDT 24 |
| Peak memory | 575576 kb |
| Host | smart-70efdb55-ffc3-4138-9adb-4f5863a41931 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3459311844 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 74.xbar_random_slow_rsp.3459311844 |
| Directory | /workspace/74.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/74.xbar_random_zero_delays.1297630821 |
| Short name | T2304 |
| Test name | |
| Test status | |
| Simulation time | 398548663 ps |
| CPU time | 35.67 seconds |
| Started | Aug 13 06:57:59 PM PDT 24 |
| Finished | Aug 13 06:58:35 PM PDT 24 |
| Peak memory | 575528 kb |
| Host | smart-4ca212d5-6d21-4015-92f1-dce9136da7ff |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1297630821 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 74.xbar_random_zero_del ays.1297630821 |
| Directory | /workspace/74.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/74.xbar_same_source.1676087946 |
| Short name | T2358 |
| Test name | |
| Test status | |
| Simulation time | 136171479 ps |
| CPU time | 12.5 seconds |
| Started | Aug 13 06:58:09 PM PDT 24 |
| Finished | Aug 13 06:58:21 PM PDT 24 |
| Peak memory | 575588 kb |
| Host | smart-80dc744e-d814-4a3a-939e-29d378a2df3e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1676087946 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 74.xbar_same_source.1676087946 |
| Directory | /workspace/74.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/74.xbar_smoke.2302199953 |
| Short name | T1588 |
| Test name | |
| Test status | |
| Simulation time | 48116591 ps |
| CPU time | 5.96 seconds |
| Started | Aug 13 06:58:01 PM PDT 24 |
| Finished | Aug 13 06:58:07 PM PDT 24 |
| Peak memory | 574236 kb |
| Host | smart-4afb5c0a-9298-4b38-a2a2-1f3590e7ea96 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2302199953 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 74.xbar_smoke.2302199953 |
| Directory | /workspace/74.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/74.xbar_smoke_large_delays.4104519387 |
| Short name | T2350 |
| Test name | |
| Test status | |
| Simulation time | 9634724576 ps |
| CPU time | 106.7 seconds |
| Started | Aug 13 06:57:57 PM PDT 24 |
| Finished | Aug 13 06:59:44 PM PDT 24 |
| Peak memory | 573576 kb |
| Host | smart-0b553e19-2d84-4de1-a85a-e3e831b29366 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4104519387 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 74.xbar_smoke_large_delays.4104519387 |
| Directory | /workspace/74.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/74.xbar_smoke_slow_rsp.4145245473 |
| Short name | T1438 |
| Test name | |
| Test status | |
| Simulation time | 6194332462 ps |
| CPU time | 102.45 seconds |
| Started | Aug 13 06:57:56 PM PDT 24 |
| Finished | Aug 13 06:59:38 PM PDT 24 |
| Peak memory | 573616 kb |
| Host | smart-1f5636cf-aa9a-4b89-ba28-241bc0d54e74 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4145245473 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 74.xbar_smoke_slow_rsp.4145245473 |
| Directory | /workspace/74.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/74.xbar_smoke_zero_delays.1455450535 |
| Short name | T604 |
| Test name | |
| Test status | |
| Simulation time | 53115750 ps |
| CPU time | 6.82 seconds |
| Started | Aug 13 06:57:59 PM PDT 24 |
| Finished | Aug 13 06:58:06 PM PDT 24 |
| Peak memory | 574200 kb |
| Host | smart-37c973f5-432b-4714-88a3-ffa7868c6012 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1455450535 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 74.xbar_smoke_zero_delay s.1455450535 |
| Directory | /workspace/74.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/74.xbar_stress_all.2635782700 |
| Short name | T630 |
| Test name | |
| Test status | |
| Simulation time | 492122217 ps |
| CPU time | 45.87 seconds |
| Started | Aug 13 06:58:04 PM PDT 24 |
| Finished | Aug 13 06:58:50 PM PDT 24 |
| Peak memory | 575796 kb |
| Host | smart-70057072-1ddb-4ab1-a955-82f4fe8393fa |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2635782700 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 74.xbar_stress_all.2635782700 |
| Directory | /workspace/74.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/74.xbar_stress_all_with_error.817313275 |
| Short name | T558 |
| Test name | |
| Test status | |
| Simulation time | 476586756 ps |
| CPU time | 35.79 seconds |
| Started | Aug 13 06:58:04 PM PDT 24 |
| Finished | Aug 13 06:58:40 PM PDT 24 |
| Peak memory | 575596 kb |
| Host | smart-3fd61abb-a4b7-4499-8f80-2c66c6ea52d1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=817313275 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 74.xbar_stress_all_with_error.817313275 |
| Directory | /workspace/74.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/74.xbar_stress_all_with_rand_reset.1640886059 |
| Short name | T2849 |
| Test name | |
| Test status | |
| Simulation time | 169619932 ps |
| CPU time | 130.2 seconds |
| Started | Aug 13 06:58:08 PM PDT 24 |
| Finished | Aug 13 07:00:19 PM PDT 24 |
| Peak memory | 576452 kb |
| Host | smart-28cb9a50-445e-46d6-a2ec-9f318be08777 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1640886059 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 74.xbar_stress_all _with_rand_reset.1640886059 |
| Directory | /workspace/74.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/74.xbar_stress_all_with_reset_error.3326957830 |
| Short name | T929 |
| Test name | |
| Test status | |
| Simulation time | 5410068809 ps |
| CPU time | 220.22 seconds |
| Started | Aug 13 06:58:03 PM PDT 24 |
| Finished | Aug 13 07:01:43 PM PDT 24 |
| Peak memory | 575720 kb |
| Host | smart-566fb5c5-b2f4-4808-a4b0-7aeae4578b9e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3326957830 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 74.xbar_stress_al l_with_reset_error.3326957830 |
| Directory | /workspace/74.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/74.xbar_unmapped_addr.1127080462 |
| Short name | T2930 |
| Test name | |
| Test status | |
| Simulation time | 362463344 ps |
| CPU time | 18.19 seconds |
| Started | Aug 13 06:58:04 PM PDT 24 |
| Finished | Aug 13 06:58:22 PM PDT 24 |
| Peak memory | 575548 kb |
| Host | smart-48a51b37-f7e3-442d-ab56-c5d21d542ed9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1127080462 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 74.xbar_unmapped_addr.1127080462 |
| Directory | /workspace/74.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/75.xbar_access_same_device.1828655475 |
| Short name | T1584 |
| Test name | |
| Test status | |
| Simulation time | 2624794659 ps |
| CPU time | 97.9 seconds |
| Started | Aug 13 06:58:07 PM PDT 24 |
| Finished | Aug 13 06:59:45 PM PDT 24 |
| Peak memory | 575692 kb |
| Host | smart-7597ff5a-da5e-4f50-a4cf-5c9bd47eb1a9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1828655475 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 75.xbar_access_same_device .1828655475 |
| Directory | /workspace/75.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/75.xbar_access_same_device_slow_rsp.2049133478 |
| Short name | T2000 |
| Test name | |
| Test status | |
| Simulation time | 152438040328 ps |
| CPU time | 2939.05 seconds |
| Started | Aug 13 06:58:08 PM PDT 24 |
| Finished | Aug 13 07:47:08 PM PDT 24 |
| Peak memory | 575708 kb |
| Host | smart-20bdd91e-7171-4a06-a0f3-cbac68bc5613 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2049133478 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 75.xbar_access_same_ device_slow_rsp.2049133478 |
| Directory | /workspace/75.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/75.xbar_error_and_unmapped_addr.3957487129 |
| Short name | T1828 |
| Test name | |
| Test status | |
| Simulation time | 97380678 ps |
| CPU time | 13.18 seconds |
| Started | Aug 13 06:58:10 PM PDT 24 |
| Finished | Aug 13 06:58:23 PM PDT 24 |
| Peak memory | 575520 kb |
| Host | smart-79f4aab3-d042-4933-8cd2-ce449fa3d8ab |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3957487129 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 75.xbar_error_and_unmapped_add r.3957487129 |
| Directory | /workspace/75.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/75.xbar_error_random.123374849 |
| Short name | T2935 |
| Test name | |
| Test status | |
| Simulation time | 662374009 ps |
| CPU time | 25.48 seconds |
| Started | Aug 13 06:58:04 PM PDT 24 |
| Finished | Aug 13 06:58:29 PM PDT 24 |
| Peak memory | 575644 kb |
| Host | smart-5f09478b-cddb-46a7-9f58-98819045f0f9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=123374849 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 75.xbar_error_random.123374849 |
| Directory | /workspace/75.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/75.xbar_random.168752979 |
| Short name | T2657 |
| Test name | |
| Test status | |
| Simulation time | 995371408 ps |
| CPU time | 35.35 seconds |
| Started | Aug 13 06:58:02 PM PDT 24 |
| Finished | Aug 13 06:58:38 PM PDT 24 |
| Peak memory | 575708 kb |
| Host | smart-26a3846e-c259-48f3-a3a7-c099429e9be6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=168752979 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 75.xbar_random.168752979 |
| Directory | /workspace/75.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/75.xbar_random_large_delays.3238775111 |
| Short name | T2923 |
| Test name | |
| Test status | |
| Simulation time | 72648893176 ps |
| CPU time | 799.58 seconds |
| Started | Aug 13 06:58:03 PM PDT 24 |
| Finished | Aug 13 07:11:23 PM PDT 24 |
| Peak memory | 575804 kb |
| Host | smart-dfb46f3b-c240-49de-8d4d-88189996539e |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3238775111 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 75.xbar_random_large_delays.3238775111 |
| Directory | /workspace/75.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/75.xbar_random_slow_rsp.3308768267 |
| Short name | T553 |
| Test name | |
| Test status | |
| Simulation time | 42256295740 ps |
| CPU time | 742.86 seconds |
| Started | Aug 13 06:58:01 PM PDT 24 |
| Finished | Aug 13 07:10:25 PM PDT 24 |
| Peak memory | 575596 kb |
| Host | smart-e50ef561-0771-465c-b2ef-6ed369b6149a |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3308768267 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 75.xbar_random_slow_rsp.3308768267 |
| Directory | /workspace/75.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/75.xbar_random_zero_delays.4119395153 |
| Short name | T2025 |
| Test name | |
| Test status | |
| Simulation time | 440046627 ps |
| CPU time | 37.7 seconds |
| Started | Aug 13 06:58:09 PM PDT 24 |
| Finished | Aug 13 06:58:47 PM PDT 24 |
| Peak memory | 575700 kb |
| Host | smart-60f5b2f3-5522-4924-b0bc-7eb7818f1b9c |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4119395153 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 75.xbar_random_zero_del ays.4119395153 |
| Directory | /workspace/75.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/75.xbar_same_source.1771642160 |
| Short name | T539 |
| Test name | |
| Test status | |
| Simulation time | 2278601302 ps |
| CPU time | 62.64 seconds |
| Started | Aug 13 06:58:02 PM PDT 24 |
| Finished | Aug 13 06:59:05 PM PDT 24 |
| Peak memory | 575724 kb |
| Host | smart-eee12d10-e59f-4655-9b61-1158cdff7e38 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1771642160 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 75.xbar_same_source.1771642160 |
| Directory | /workspace/75.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/75.xbar_smoke.3414954478 |
| Short name | T1848 |
| Test name | |
| Test status | |
| Simulation time | 56028489 ps |
| CPU time | 6.99 seconds |
| Started | Aug 13 06:58:05 PM PDT 24 |
| Finished | Aug 13 06:58:12 PM PDT 24 |
| Peak memory | 573496 kb |
| Host | smart-dbe6ba8c-36d5-4320-b00b-8bf4499bbf97 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3414954478 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 75.xbar_smoke.3414954478 |
| Directory | /workspace/75.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/75.xbar_smoke_large_delays.2973550756 |
| Short name | T2003 |
| Test name | |
| Test status | |
| Simulation time | 9289859391 ps |
| CPU time | 101.96 seconds |
| Started | Aug 13 06:58:08 PM PDT 24 |
| Finished | Aug 13 06:59:50 PM PDT 24 |
| Peak memory | 574236 kb |
| Host | smart-12c3c93b-4062-465a-811f-64e7757ff045 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2973550756 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 75.xbar_smoke_large_delays.2973550756 |
| Directory | /workspace/75.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/75.xbar_smoke_slow_rsp.2859347542 |
| Short name | T1612 |
| Test name | |
| Test status | |
| Simulation time | 5160576315 ps |
| CPU time | 90.21 seconds |
| Started | Aug 13 06:58:07 PM PDT 24 |
| Finished | Aug 13 06:59:38 PM PDT 24 |
| Peak memory | 574236 kb |
| Host | smart-19e12f19-0c06-45cd-9000-1dc965d08a03 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2859347542 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 75.xbar_smoke_slow_rsp.2859347542 |
| Directory | /workspace/75.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/75.xbar_smoke_zero_delays.2471250209 |
| Short name | T1688 |
| Test name | |
| Test status | |
| Simulation time | 54358281 ps |
| CPU time | 6.11 seconds |
| Started | Aug 13 06:58:05 PM PDT 24 |
| Finished | Aug 13 06:58:11 PM PDT 24 |
| Peak memory | 574216 kb |
| Host | smart-65192cc7-a8ce-4905-9ca8-ec3f2537d14f |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2471250209 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 75.xbar_smoke_zero_delay s.2471250209 |
| Directory | /workspace/75.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/75.xbar_stress_all.3331215152 |
| Short name | T2618 |
| Test name | |
| Test status | |
| Simulation time | 6961182308 ps |
| CPU time | 255.24 seconds |
| Started | Aug 13 06:58:11 PM PDT 24 |
| Finished | Aug 13 07:02:26 PM PDT 24 |
| Peak memory | 575672 kb |
| Host | smart-57773990-f31e-48b0-be3d-d953fe8691b3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3331215152 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 75.xbar_stress_all.3331215152 |
| Directory | /workspace/75.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/75.xbar_stress_all_with_error.3343832248 |
| Short name | T1815 |
| Test name | |
| Test status | |
| Simulation time | 13239017366 ps |
| CPU time | 453.82 seconds |
| Started | Aug 13 06:58:09 PM PDT 24 |
| Finished | Aug 13 07:05:44 PM PDT 24 |
| Peak memory | 575864 kb |
| Host | smart-123089b8-335b-454d-87c7-781fef402e9d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3343832248 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 75.xbar_stress_all_with_error.3343832248 |
| Directory | /workspace/75.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/75.xbar_stress_all_with_rand_reset.764447410 |
| Short name | T1514 |
| Test name | |
| Test status | |
| Simulation time | 155047831 ps |
| CPU time | 87.35 seconds |
| Started | Aug 13 06:58:13 PM PDT 24 |
| Finished | Aug 13 06:59:40 PM PDT 24 |
| Peak memory | 576472 kb |
| Host | smart-86826837-c42f-464b-b28f-d518d1f9fc3a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=764447410 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_res et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 75.xbar_stress_all_ with_rand_reset.764447410 |
| Directory | /workspace/75.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/75.xbar_stress_all_with_reset_error.4191214877 |
| Short name | T2161 |
| Test name | |
| Test status | |
| Simulation time | 2333399060 ps |
| CPU time | 353.1 seconds |
| Started | Aug 13 06:58:15 PM PDT 24 |
| Finished | Aug 13 07:04:09 PM PDT 24 |
| Peak memory | 575732 kb |
| Host | smart-689edb75-1ea9-47e4-87fc-5c3b80f40806 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4191214877 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 75.xbar_stress_al l_with_reset_error.4191214877 |
| Directory | /workspace/75.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/75.xbar_unmapped_addr.2013027833 |
| Short name | T1953 |
| Test name | |
| Test status | |
| Simulation time | 62273339 ps |
| CPU time | 9.48 seconds |
| Started | Aug 13 06:58:04 PM PDT 24 |
| Finished | Aug 13 06:58:14 PM PDT 24 |
| Peak memory | 575560 kb |
| Host | smart-e6ae2197-d471-4eea-824b-f04878778c4b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2013027833 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 75.xbar_unmapped_addr.2013027833 |
| Directory | /workspace/75.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/76.xbar_access_same_device.3253064414 |
| Short name | T1652 |
| Test name | |
| Test status | |
| Simulation time | 3318790599 ps |
| CPU time | 132.38 seconds |
| Started | Aug 13 06:58:15 PM PDT 24 |
| Finished | Aug 13 07:00:28 PM PDT 24 |
| Peak memory | 575740 kb |
| Host | smart-515026c7-81f1-492c-a7a8-af60623162de |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3253064414 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 76.xbar_access_same_device .3253064414 |
| Directory | /workspace/76.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/76.xbar_access_same_device_slow_rsp.3667105889 |
| Short name | T2481 |
| Test name | |
| Test status | |
| Simulation time | 9724987058 ps |
| CPU time | 151.25 seconds |
| Started | Aug 13 06:58:17 PM PDT 24 |
| Finished | Aug 13 07:00:48 PM PDT 24 |
| Peak memory | 573668 kb |
| Host | smart-ee5bb796-b269-4e18-ad18-3844ba319824 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3667105889 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 76.xbar_access_same_ device_slow_rsp.3667105889 |
| Directory | /workspace/76.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/76.xbar_error_and_unmapped_addr.310499591 |
| Short name | T1507 |
| Test name | |
| Test status | |
| Simulation time | 744153560 ps |
| CPU time | 28.4 seconds |
| Started | Aug 13 06:58:21 PM PDT 24 |
| Finished | Aug 13 06:58:50 PM PDT 24 |
| Peak memory | 575628 kb |
| Host | smart-9d34ab5c-92f0-4631-8d41-8cf27a89ffd4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=310499591 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 76.xbar_error_and_unmapped_addr .310499591 |
| Directory | /workspace/76.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/76.xbar_error_random.3711903268 |
| Short name | T2048 |
| Test name | |
| Test status | |
| Simulation time | 282718340 ps |
| CPU time | 11.89 seconds |
| Started | Aug 13 06:58:14 PM PDT 24 |
| Finished | Aug 13 06:58:27 PM PDT 24 |
| Peak memory | 575436 kb |
| Host | smart-1b1d5c8c-dad1-41d0-b61e-d2cea1f4a23a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3711903268 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 76.xbar_error_random.3711903268 |
| Directory | /workspace/76.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/76.xbar_random.2910575199 |
| Short name | T2183 |
| Test name | |
| Test status | |
| Simulation time | 528633444 ps |
| CPU time | 18.99 seconds |
| Started | Aug 13 06:58:14 PM PDT 24 |
| Finished | Aug 13 06:58:33 PM PDT 24 |
| Peak memory | 575668 kb |
| Host | smart-36837396-c02e-4219-8e75-6a67e48c141e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2910575199 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 76.xbar_random.2910575199 |
| Directory | /workspace/76.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/76.xbar_random_large_delays.3388644720 |
| Short name | T2796 |
| Test name | |
| Test status | |
| Simulation time | 48514961597 ps |
| CPU time | 490.59 seconds |
| Started | Aug 13 06:58:11 PM PDT 24 |
| Finished | Aug 13 07:06:22 PM PDT 24 |
| Peak memory | 575740 kb |
| Host | smart-fe2f8087-49f7-4804-b81c-b1cc974d2541 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3388644720 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 76.xbar_random_large_delays.3388644720 |
| Directory | /workspace/76.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/76.xbar_random_slow_rsp.1573710431 |
| Short name | T1734 |
| Test name | |
| Test status | |
| Simulation time | 48200096284 ps |
| CPU time | 903.08 seconds |
| Started | Aug 13 06:58:12 PM PDT 24 |
| Finished | Aug 13 07:13:15 PM PDT 24 |
| Peak memory | 575792 kb |
| Host | smart-c10f3c95-d6dc-4acc-95fe-8460b2955d20 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1573710431 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 76.xbar_random_slow_rsp.1573710431 |
| Directory | /workspace/76.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/76.xbar_random_zero_delays.1967987256 |
| Short name | T538 |
| Test name | |
| Test status | |
| Simulation time | 167304732 ps |
| CPU time | 16.2 seconds |
| Started | Aug 13 06:58:13 PM PDT 24 |
| Finished | Aug 13 06:58:30 PM PDT 24 |
| Peak memory | 575496 kb |
| Host | smart-a0a42e95-d09d-47c6-90a4-0058d5d60d25 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1967987256 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 76.xbar_random_zero_del ays.1967987256 |
| Directory | /workspace/76.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/76.xbar_same_source.1589163004 |
| Short name | T2751 |
| Test name | |
| Test status | |
| Simulation time | 1792267566 ps |
| CPU time | 52.37 seconds |
| Started | Aug 13 06:58:10 PM PDT 24 |
| Finished | Aug 13 06:59:03 PM PDT 24 |
| Peak memory | 575656 kb |
| Host | smart-33fee0a7-0148-4daa-a59b-678b08d48435 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1589163004 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 76.xbar_same_source.1589163004 |
| Directory | /workspace/76.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/76.xbar_smoke.2933783652 |
| Short name | T2901 |
| Test name | |
| Test status | |
| Simulation time | 39826821 ps |
| CPU time | 5.87 seconds |
| Started | Aug 13 06:58:12 PM PDT 24 |
| Finished | Aug 13 06:58:18 PM PDT 24 |
| Peak memory | 573520 kb |
| Host | smart-077157b6-f7f1-461c-a200-ed53ed206379 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2933783652 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 76.xbar_smoke.2933783652 |
| Directory | /workspace/76.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/76.xbar_smoke_large_delays.3178541100 |
| Short name | T2644 |
| Test name | |
| Test status | |
| Simulation time | 8202186171 ps |
| CPU time | 84.34 seconds |
| Started | Aug 13 06:58:13 PM PDT 24 |
| Finished | Aug 13 06:59:37 PM PDT 24 |
| Peak memory | 574340 kb |
| Host | smart-8ea8ae80-62e9-4f51-b712-6616f6cb4d18 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3178541100 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 76.xbar_smoke_large_delays.3178541100 |
| Directory | /workspace/76.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/76.xbar_smoke_slow_rsp.3257045929 |
| Short name | T2836 |
| Test name | |
| Test status | |
| Simulation time | 4969821709 ps |
| CPU time | 79.62 seconds |
| Started | Aug 13 06:58:11 PM PDT 24 |
| Finished | Aug 13 06:59:31 PM PDT 24 |
| Peak memory | 573604 kb |
| Host | smart-d11d8224-3095-48b5-a516-baee0fccb272 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3257045929 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 76.xbar_smoke_slow_rsp.3257045929 |
| Directory | /workspace/76.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/76.xbar_smoke_zero_delays.554244326 |
| Short name | T1462 |
| Test name | |
| Test status | |
| Simulation time | 54364075 ps |
| CPU time | 6.49 seconds |
| Started | Aug 13 06:58:16 PM PDT 24 |
| Finished | Aug 13 06:58:23 PM PDT 24 |
| Peak memory | 574248 kb |
| Host | smart-2cf9bec6-bb73-4180-8d2d-a8391a5a68ed |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=554244326 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 76.xbar_smoke_zero_delays .554244326 |
| Directory | /workspace/76.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/76.xbar_stress_all.1775157616 |
| Short name | T1840 |
| Test name | |
| Test status | |
| Simulation time | 3131185387 ps |
| CPU time | 238.71 seconds |
| Started | Aug 13 06:58:23 PM PDT 24 |
| Finished | Aug 13 07:02:22 PM PDT 24 |
| Peak memory | 576552 kb |
| Host | smart-4bb49af5-0949-4f34-a178-c1afaa4c439f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1775157616 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 76.xbar_stress_all.1775157616 |
| Directory | /workspace/76.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/76.xbar_stress_all_with_error.590325973 |
| Short name | T1592 |
| Test name | |
| Test status | |
| Simulation time | 11664417566 ps |
| CPU time | 451.76 seconds |
| Started | Aug 13 06:58:21 PM PDT 24 |
| Finished | Aug 13 07:05:53 PM PDT 24 |
| Peak memory | 575860 kb |
| Host | smart-ebb44650-22df-4ca6-b243-35ad516393c8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=590325973 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 76.xbar_stress_all_with_error.590325973 |
| Directory | /workspace/76.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/76.xbar_stress_all_with_rand_reset.2609629558 |
| Short name | T908 |
| Test name | |
| Test status | |
| Simulation time | 83363520 ps |
| CPU time | 44.44 seconds |
| Started | Aug 13 06:58:20 PM PDT 24 |
| Finished | Aug 13 06:59:05 PM PDT 24 |
| Peak memory | 576420 kb |
| Host | smart-ef6f919f-9f33-49b7-bbb6-ae9712c6906d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2609629558 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 76.xbar_stress_all _with_rand_reset.2609629558 |
| Directory | /workspace/76.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/76.xbar_stress_all_with_reset_error.2875308070 |
| Short name | T2236 |
| Test name | |
| Test status | |
| Simulation time | 4064426593 ps |
| CPU time | 374.4 seconds |
| Started | Aug 13 06:58:21 PM PDT 24 |
| Finished | Aug 13 07:04:35 PM PDT 24 |
| Peak memory | 575688 kb |
| Host | smart-1bbdeaf7-6f42-48f3-a521-3ef7d4ad3e89 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2875308070 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 76.xbar_stress_al l_with_reset_error.2875308070 |
| Directory | /workspace/76.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/76.xbar_unmapped_addr.1697434148 |
| Short name | T2585 |
| Test name | |
| Test status | |
| Simulation time | 35402766 ps |
| CPU time | 7.08 seconds |
| Started | Aug 13 06:58:12 PM PDT 24 |
| Finished | Aug 13 06:58:19 PM PDT 24 |
| Peak memory | 573704 kb |
| Host | smart-bb6cd3c6-b7ea-4b40-9512-634164d56918 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1697434148 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 76.xbar_unmapped_addr.1697434148 |
| Directory | /workspace/76.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/77.xbar_access_same_device.693867830 |
| Short name | T1970 |
| Test name | |
| Test status | |
| Simulation time | 2663719463 ps |
| CPU time | 104.66 seconds |
| Started | Aug 13 06:58:22 PM PDT 24 |
| Finished | Aug 13 07:00:07 PM PDT 24 |
| Peak memory | 576456 kb |
| Host | smart-5504eab0-51b0-41a1-8f6a-d6e6c6131add |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=693867830 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 77.xbar_access_same_device. 693867830 |
| Directory | /workspace/77.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/77.xbar_access_same_device_slow_rsp.2048924627 |
| Short name | T887 |
| Test name | |
| Test status | |
| Simulation time | 46473869777 ps |
| CPU time | 893.86 seconds |
| Started | Aug 13 06:58:20 PM PDT 24 |
| Finished | Aug 13 07:13:14 PM PDT 24 |
| Peak memory | 576476 kb |
| Host | smart-8ffb71a0-6c8a-4825-b7f5-d133a32c5bb2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2048924627 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 77.xbar_access_same_ device_slow_rsp.2048924627 |
| Directory | /workspace/77.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/77.xbar_error_and_unmapped_addr.269092916 |
| Short name | T2442 |
| Test name | |
| Test status | |
| Simulation time | 19969128 ps |
| CPU time | 5.27 seconds |
| Started | Aug 13 06:58:29 PM PDT 24 |
| Finished | Aug 13 06:58:34 PM PDT 24 |
| Peak memory | 574156 kb |
| Host | smart-cfec3fa8-47c8-4a0a-b508-4dc235a75e9d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=269092916 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 77.xbar_error_and_unmapped_addr .269092916 |
| Directory | /workspace/77.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/77.xbar_error_random.1246297009 |
| Short name | T1597 |
| Test name | |
| Test status | |
| Simulation time | 1911388873 ps |
| CPU time | 70.26 seconds |
| Started | Aug 13 06:58:20 PM PDT 24 |
| Finished | Aug 13 06:59:31 PM PDT 24 |
| Peak memory | 575488 kb |
| Host | smart-2ae89682-fb17-4e18-82ad-1e21679893f6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1246297009 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 77.xbar_error_random.1246297009 |
| Directory | /workspace/77.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/77.xbar_random.3999855520 |
| Short name | T704 |
| Test name | |
| Test status | |
| Simulation time | 473725991 ps |
| CPU time | 44.29 seconds |
| Started | Aug 13 06:58:21 PM PDT 24 |
| Finished | Aug 13 06:59:05 PM PDT 24 |
| Peak memory | 575732 kb |
| Host | smart-b94840cd-7a52-48dd-9664-78ba4fe0e260 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3999855520 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 77.xbar_random.3999855520 |
| Directory | /workspace/77.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/77.xbar_random_large_delays.4248442284 |
| Short name | T2914 |
| Test name | |
| Test status | |
| Simulation time | 93870771635 ps |
| CPU time | 1061.51 seconds |
| Started | Aug 13 06:58:21 PM PDT 24 |
| Finished | Aug 13 07:16:03 PM PDT 24 |
| Peak memory | 575604 kb |
| Host | smart-3016b4fc-7a57-499a-9d70-1b86ee1aa390 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4248442284 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 77.xbar_random_large_delays.4248442284 |
| Directory | /workspace/77.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/77.xbar_random_slow_rsp.611889967 |
| Short name | T1638 |
| Test name | |
| Test status | |
| Simulation time | 5713314382 ps |
| CPU time | 104.92 seconds |
| Started | Aug 13 06:58:23 PM PDT 24 |
| Finished | Aug 13 07:00:08 PM PDT 24 |
| Peak memory | 575760 kb |
| Host | smart-4baf2968-ebdb-4199-910a-06662962db47 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=611889967 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 77.xbar_random_slow_rsp.611889967 |
| Directory | /workspace/77.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/77.xbar_random_zero_delays.1524162304 |
| Short name | T2363 |
| Test name | |
| Test status | |
| Simulation time | 90388917 ps |
| CPU time | 11.57 seconds |
| Started | Aug 13 06:58:20 PM PDT 24 |
| Finished | Aug 13 06:58:31 PM PDT 24 |
| Peak memory | 575664 kb |
| Host | smart-797568ed-850b-41fa-91ce-d65f8d6098f0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1524162304 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 77.xbar_random_zero_del ays.1524162304 |
| Directory | /workspace/77.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/77.xbar_same_source.271421330 |
| Short name | T690 |
| Test name | |
| Test status | |
| Simulation time | 117829499 ps |
| CPU time | 11.47 seconds |
| Started | Aug 13 06:58:22 PM PDT 24 |
| Finished | Aug 13 06:58:34 PM PDT 24 |
| Peak memory | 575672 kb |
| Host | smart-a45749dd-b1e9-4a10-8c98-46c109c23c1f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=271421330 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 77.xbar_same_source.271421330 |
| Directory | /workspace/77.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/77.xbar_smoke.1513086128 |
| Short name | T685 |
| Test name | |
| Test status | |
| Simulation time | 178744343 ps |
| CPU time | 8.02 seconds |
| Started | Aug 13 06:58:25 PM PDT 24 |
| Finished | Aug 13 06:58:33 PM PDT 24 |
| Peak memory | 573532 kb |
| Host | smart-b8a34c3b-283f-4167-8a15-955f31cbd45a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1513086128 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 77.xbar_smoke.1513086128 |
| Directory | /workspace/77.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/77.xbar_smoke_large_delays.905725669 |
| Short name | T545 |
| Test name | |
| Test status | |
| Simulation time | 9232266039 ps |
| CPU time | 93.55 seconds |
| Started | Aug 13 06:58:20 PM PDT 24 |
| Finished | Aug 13 06:59:53 PM PDT 24 |
| Peak memory | 574224 kb |
| Host | smart-bfcfe752-59b2-49a0-818a-6d63ce9f165f |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=905725669 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 77.xbar_smoke_large_delays.905725669 |
| Directory | /workspace/77.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/77.xbar_smoke_slow_rsp.2313657084 |
| Short name | T1543 |
| Test name | |
| Test status | |
| Simulation time | 5524939068 ps |
| CPU time | 92.99 seconds |
| Started | Aug 13 06:58:23 PM PDT 24 |
| Finished | Aug 13 06:59:56 PM PDT 24 |
| Peak memory | 573572 kb |
| Host | smart-ec9a6fe8-9d0d-44ec-a4c4-8395b018dab2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2313657084 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 77.xbar_smoke_slow_rsp.2313657084 |
| Directory | /workspace/77.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/77.xbar_smoke_zero_delays.4234292938 |
| Short name | T2436 |
| Test name | |
| Test status | |
| Simulation time | 50009805 ps |
| CPU time | 6.77 seconds |
| Started | Aug 13 06:58:20 PM PDT 24 |
| Finished | Aug 13 06:58:27 PM PDT 24 |
| Peak memory | 573520 kb |
| Host | smart-3859af2b-4c3c-4c2e-94dc-d9ef4f5eb811 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4234292938 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 77.xbar_smoke_zero_delay s.4234292938 |
| Directory | /workspace/77.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/77.xbar_stress_all.130242535 |
| Short name | T1814 |
| Test name | |
| Test status | |
| Simulation time | 4311050526 ps |
| CPU time | 342.57 seconds |
| Started | Aug 13 06:58:27 PM PDT 24 |
| Finished | Aug 13 07:04:10 PM PDT 24 |
| Peak memory | 576552 kb |
| Host | smart-763dd1b7-470c-4878-bb3f-d7957ab1d40e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=130242535 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 77.xbar_stress_all.130242535 |
| Directory | /workspace/77.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/77.xbar_stress_all_with_error.424150622 |
| Short name | T2355 |
| Test name | |
| Test status | |
| Simulation time | 1525819243 ps |
| CPU time | 58.69 seconds |
| Started | Aug 13 06:58:27 PM PDT 24 |
| Finished | Aug 13 06:59:26 PM PDT 24 |
| Peak memory | 575548 kb |
| Host | smart-42ac1a54-5377-4fa5-96cb-0e0aa9c2b65f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=424150622 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 77.xbar_stress_all_with_error.424150622 |
| Directory | /workspace/77.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/77.xbar_stress_all_with_rand_reset.2948918897 |
| Short name | T913 |
| Test name | |
| Test status | |
| Simulation time | 5573084790 ps |
| CPU time | 386.97 seconds |
| Started | Aug 13 06:58:31 PM PDT 24 |
| Finished | Aug 13 07:04:59 PM PDT 24 |
| Peak memory | 576540 kb |
| Host | smart-40655d55-2c79-4866-90b5-551ada67c4ae |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2948918897 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 77.xbar_stress_all _with_rand_reset.2948918897 |
| Directory | /workspace/77.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/77.xbar_stress_all_with_reset_error.386838717 |
| Short name | T2145 |
| Test name | |
| Test status | |
| Simulation time | 650604075 ps |
| CPU time | 220.14 seconds |
| Started | Aug 13 06:58:29 PM PDT 24 |
| Finished | Aug 13 07:02:09 PM PDT 24 |
| Peak memory | 576508 kb |
| Host | smart-9000ce03-de27-4c0c-9ed1-60e6d557ddf1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=386838717 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 77.xbar_stress_all _with_reset_error.386838717 |
| Directory | /workspace/77.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/77.xbar_unmapped_addr.730258706 |
| Short name | T594 |
| Test name | |
| Test status | |
| Simulation time | 1349598681 ps |
| CPU time | 60.9 seconds |
| Started | Aug 13 06:58:19 PM PDT 24 |
| Finished | Aug 13 06:59:20 PM PDT 24 |
| Peak memory | 575752 kb |
| Host | smart-e78d21fe-8ccc-42ad-bbae-9a81608f633c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=730258706 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 77.xbar_unmapped_addr.730258706 |
| Directory | /workspace/77.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/78.xbar_access_same_device.1430791695 |
| Short name | T1757 |
| Test name | |
| Test status | |
| Simulation time | 3173536254 ps |
| CPU time | 117.5 seconds |
| Started | Aug 13 06:58:27 PM PDT 24 |
| Finished | Aug 13 07:00:25 PM PDT 24 |
| Peak memory | 576512 kb |
| Host | smart-ab11afb5-f602-4cda-9939-18f9ca3e9d2e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1430791695 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 78.xbar_access_same_device .1430791695 |
| Directory | /workspace/78.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/78.xbar_access_same_device_slow_rsp.3601306334 |
| Short name | T1827 |
| Test name | |
| Test status | |
| Simulation time | 118047924661 ps |
| CPU time | 1971.81 seconds |
| Started | Aug 13 06:58:28 PM PDT 24 |
| Finished | Aug 13 07:31:20 PM PDT 24 |
| Peak memory | 575684 kb |
| Host | smart-053d79f3-f823-43b6-8558-a317304349e4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3601306334 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 78.xbar_access_same_ device_slow_rsp.3601306334 |
| Directory | /workspace/78.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/78.xbar_error_and_unmapped_addr.789092782 |
| Short name | T2498 |
| Test name | |
| Test status | |
| Simulation time | 82653286 ps |
| CPU time | 12.01 seconds |
| Started | Aug 13 06:58:36 PM PDT 24 |
| Finished | Aug 13 06:58:48 PM PDT 24 |
| Peak memory | 575464 kb |
| Host | smart-210ae414-93ab-4c4b-89ee-c2f85136c8e7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=789092782 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 78.xbar_error_and_unmapped_addr .789092782 |
| Directory | /workspace/78.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/78.xbar_error_random.1969023284 |
| Short name | T2100 |
| Test name | |
| Test status | |
| Simulation time | 847158499 ps |
| CPU time | 29.11 seconds |
| Started | Aug 13 06:58:27 PM PDT 24 |
| Finished | Aug 13 06:58:56 PM PDT 24 |
| Peak memory | 575708 kb |
| Host | smart-3967a27c-99ab-432d-9c44-53954967e0f5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1969023284 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 78.xbar_error_random.1969023284 |
| Directory | /workspace/78.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/78.xbar_random.2343322165 |
| Short name | T2805 |
| Test name | |
| Test status | |
| Simulation time | 170760086 ps |
| CPU time | 8.56 seconds |
| Started | Aug 13 06:58:29 PM PDT 24 |
| Finished | Aug 13 06:58:37 PM PDT 24 |
| Peak memory | 573568 kb |
| Host | smart-7b1d270f-6afe-4867-a8ab-217fbf0d5eec |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2343322165 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 78.xbar_random.2343322165 |
| Directory | /workspace/78.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/78.xbar_random_large_delays.72057374 |
| Short name | T2609 |
| Test name | |
| Test status | |
| Simulation time | 47624660672 ps |
| CPU time | 503.38 seconds |
| Started | Aug 13 06:58:33 PM PDT 24 |
| Finished | Aug 13 07:06:57 PM PDT 24 |
| Peak memory | 575620 kb |
| Host | smart-1a27fa43-575c-42fa-a27e-db3895e89a67 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=72057374 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 78.xbar_random_large_delays.72057374 |
| Directory | /workspace/78.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/78.xbar_random_slow_rsp.636329840 |
| Short name | T2143 |
| Test name | |
| Test status | |
| Simulation time | 13767270054 ps |
| CPU time | 221.58 seconds |
| Started | Aug 13 06:58:29 PM PDT 24 |
| Finished | Aug 13 07:02:10 PM PDT 24 |
| Peak memory | 575804 kb |
| Host | smart-e1e0b6e3-ec72-4fb0-a83d-e69608466765 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=636329840 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 78.xbar_random_slow_rsp.636329840 |
| Directory | /workspace/78.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/78.xbar_random_zero_delays.3922885894 |
| Short name | T2909 |
| Test name | |
| Test status | |
| Simulation time | 198816441 ps |
| CPU time | 18.94 seconds |
| Started | Aug 13 06:58:28 PM PDT 24 |
| Finished | Aug 13 06:58:47 PM PDT 24 |
| Peak memory | 575560 kb |
| Host | smart-dd33f593-6a1d-4f54-9d7c-c660a54fbb50 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3922885894 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 78.xbar_random_zero_del ays.3922885894 |
| Directory | /workspace/78.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/78.xbar_same_source.3445485759 |
| Short name | T716 |
| Test name | |
| Test status | |
| Simulation time | 1061711629 ps |
| CPU time | 33.34 seconds |
| Started | Aug 13 06:58:27 PM PDT 24 |
| Finished | Aug 13 06:59:00 PM PDT 24 |
| Peak memory | 575520 kb |
| Host | smart-10447ac5-40b1-4ac8-905b-82a6bf8c835c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3445485759 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 78.xbar_same_source.3445485759 |
| Directory | /workspace/78.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/78.xbar_smoke.1821855254 |
| Short name | T2829 |
| Test name | |
| Test status | |
| Simulation time | 243901716 ps |
| CPU time | 9.51 seconds |
| Started | Aug 13 06:58:27 PM PDT 24 |
| Finished | Aug 13 06:58:37 PM PDT 24 |
| Peak memory | 574248 kb |
| Host | smart-a6ce8bf7-5c30-47d3-b5d2-9d7c3bd61513 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1821855254 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 78.xbar_smoke.1821855254 |
| Directory | /workspace/78.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/78.xbar_smoke_large_delays.4077290229 |
| Short name | T2679 |
| Test name | |
| Test status | |
| Simulation time | 8056060994 ps |
| CPU time | 89.23 seconds |
| Started | Aug 13 06:58:27 PM PDT 24 |
| Finished | Aug 13 06:59:57 PM PDT 24 |
| Peak memory | 573688 kb |
| Host | smart-e2121135-4d26-4bdb-a488-ffd3afbc1ad5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4077290229 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 78.xbar_smoke_large_delays.4077290229 |
| Directory | /workspace/78.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/78.xbar_smoke_slow_rsp.3503195868 |
| Short name | T2704 |
| Test name | |
| Test status | |
| Simulation time | 5376826965 ps |
| CPU time | 95.31 seconds |
| Started | Aug 13 06:58:27 PM PDT 24 |
| Finished | Aug 13 07:00:03 PM PDT 24 |
| Peak memory | 573636 kb |
| Host | smart-cf2b8d98-04eb-4834-ac08-805f89b2bbf3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3503195868 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 78.xbar_smoke_slow_rsp.3503195868 |
| Directory | /workspace/78.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/78.xbar_smoke_zero_delays.2963153830 |
| Short name | T1617 |
| Test name | |
| Test status | |
| Simulation time | 45767397 ps |
| CPU time | 6.09 seconds |
| Started | Aug 13 06:58:27 PM PDT 24 |
| Finished | Aug 13 06:58:33 PM PDT 24 |
| Peak memory | 573604 kb |
| Host | smart-939018cf-4150-476d-a35b-5e62d7e69102 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2963153830 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 78.xbar_smoke_zero_delay s.2963153830 |
| Directory | /workspace/78.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/78.xbar_stress_all.583772928 |
| Short name | T1760 |
| Test name | |
| Test status | |
| Simulation time | 12064631045 ps |
| CPU time | 468.28 seconds |
| Started | Aug 13 06:58:35 PM PDT 24 |
| Finished | Aug 13 07:06:24 PM PDT 24 |
| Peak memory | 575728 kb |
| Host | smart-5c9d66b7-cc92-4629-b045-45ecc60938fd |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=583772928 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 78.xbar_stress_all.583772928 |
| Directory | /workspace/78.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/78.xbar_stress_all_with_error.1505116241 |
| Short name | T2583 |
| Test name | |
| Test status | |
| Simulation time | 3309390467 ps |
| CPU time | 116.76 seconds |
| Started | Aug 13 06:58:38 PM PDT 24 |
| Finished | Aug 13 07:00:35 PM PDT 24 |
| Peak memory | 575768 kb |
| Host | smart-6625904b-038d-47ef-8d5e-f2ed60edd3ff |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1505116241 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 78.xbar_stress_all_with_error.1505116241 |
| Directory | /workspace/78.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/78.xbar_stress_all_with_rand_reset.1977586035 |
| Short name | T2439 |
| Test name | |
| Test status | |
| Simulation time | 487097005 ps |
| CPU time | 235.36 seconds |
| Started | Aug 13 06:58:39 PM PDT 24 |
| Finished | Aug 13 07:02:35 PM PDT 24 |
| Peak memory | 576472 kb |
| Host | smart-fb9b75b3-7bf3-4dfd-a362-908b33eca945 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1977586035 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 78.xbar_stress_all _with_rand_reset.1977586035 |
| Directory | /workspace/78.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/78.xbar_stress_all_with_reset_error.3647838396 |
| Short name | T1572 |
| Test name | |
| Test status | |
| Simulation time | 114544479 ps |
| CPU time | 32.74 seconds |
| Started | Aug 13 06:58:39 PM PDT 24 |
| Finished | Aug 13 06:59:11 PM PDT 24 |
| Peak memory | 575764 kb |
| Host | smart-c75c4ebd-381f-4745-9a47-46df6998aee4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3647838396 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 78.xbar_stress_al l_with_reset_error.3647838396 |
| Directory | /workspace/78.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/78.xbar_unmapped_addr.2810642165 |
| Short name | T2343 |
| Test name | |
| Test status | |
| Simulation time | 1055082398 ps |
| CPU time | 47.23 seconds |
| Started | Aug 13 06:58:36 PM PDT 24 |
| Finished | Aug 13 06:59:23 PM PDT 24 |
| Peak memory | 575584 kb |
| Host | smart-8cdfeade-efc7-4203-8d4d-67d3ba6a5450 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2810642165 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 78.xbar_unmapped_addr.2810642165 |
| Directory | /workspace/78.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/79.xbar_access_same_device.2722250242 |
| Short name | T1797 |
| Test name | |
| Test status | |
| Simulation time | 453762566 ps |
| CPU time | 31.61 seconds |
| Started | Aug 13 06:58:36 PM PDT 24 |
| Finished | Aug 13 06:59:07 PM PDT 24 |
| Peak memory | 575692 kb |
| Host | smart-2cd1f2cc-9a7a-4305-a479-6c24db73f9d7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2722250242 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 79.xbar_access_same_device .2722250242 |
| Directory | /workspace/79.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/79.xbar_access_same_device_slow_rsp.214220247 |
| Short name | T885 |
| Test name | |
| Test status | |
| Simulation time | 80959879261 ps |
| CPU time | 1562.27 seconds |
| Started | Aug 13 06:58:36 PM PDT 24 |
| Finished | Aug 13 07:24:38 PM PDT 24 |
| Peak memory | 575684 kb |
| Host | smart-2ebfb268-5c4b-46b1-b80b-e25027080d5e |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=214220247 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 79.xbar_access_same_d evice_slow_rsp.214220247 |
| Directory | /workspace/79.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/79.xbar_error_and_unmapped_addr.1172417197 |
| Short name | T1456 |
| Test name | |
| Test status | |
| Simulation time | 93535168 ps |
| CPU time | 11.25 seconds |
| Started | Aug 13 06:58:36 PM PDT 24 |
| Finished | Aug 13 06:58:47 PM PDT 24 |
| Peak memory | 575400 kb |
| Host | smart-48277c78-fd71-4c6a-8b7a-fa67cf2c19df |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1172417197 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 79.xbar_error_and_unmapped_add r.1172417197 |
| Directory | /workspace/79.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/79.xbar_error_random.359226548 |
| Short name | T1682 |
| Test name | |
| Test status | |
| Simulation time | 115168950 ps |
| CPU time | 11.25 seconds |
| Started | Aug 13 06:58:37 PM PDT 24 |
| Finished | Aug 13 06:58:48 PM PDT 24 |
| Peak memory | 575624 kb |
| Host | smart-01e7da23-25e9-430d-a3d1-e5f6783d3ceb |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=359226548 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 79.xbar_error_random.359226548 |
| Directory | /workspace/79.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/79.xbar_random.3911397496 |
| Short name | T1538 |
| Test name | |
| Test status | |
| Simulation time | 180553714 ps |
| CPU time | 18.78 seconds |
| Started | Aug 13 06:58:36 PM PDT 24 |
| Finished | Aug 13 06:58:55 PM PDT 24 |
| Peak memory | 575640 kb |
| Host | smart-70153eeb-c7d1-4aee-b4c7-2841eacdb078 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3911397496 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 79.xbar_random.3911397496 |
| Directory | /workspace/79.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/79.xbar_random_large_delays.2127224933 |
| Short name | T2676 |
| Test name | |
| Test status | |
| Simulation time | 4760840342 ps |
| CPU time | 50.52 seconds |
| Started | Aug 13 06:58:39 PM PDT 24 |
| Finished | Aug 13 06:59:30 PM PDT 24 |
| Peak memory | 574356 kb |
| Host | smart-ba953a77-8a72-41de-b921-04d9b8641ec8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2127224933 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 79.xbar_random_large_delays.2127224933 |
| Directory | /workspace/79.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/79.xbar_random_slow_rsp.1713252446 |
| Short name | T2423 |
| Test name | |
| Test status | |
| Simulation time | 33758141483 ps |
| CPU time | 591.66 seconds |
| Started | Aug 13 06:58:39 PM PDT 24 |
| Finished | Aug 13 07:08:31 PM PDT 24 |
| Peak memory | 575560 kb |
| Host | smart-572e740c-a526-4bc0-a569-3332282ef14c |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1713252446 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 79.xbar_random_slow_rsp.1713252446 |
| Directory | /workspace/79.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/79.xbar_random_zero_delays.3667565795 |
| Short name | T1703 |
| Test name | |
| Test status | |
| Simulation time | 390186061 ps |
| CPU time | 30.1 seconds |
| Started | Aug 13 06:58:37 PM PDT 24 |
| Finished | Aug 13 06:59:07 PM PDT 24 |
| Peak memory | 575472 kb |
| Host | smart-83390295-0f2f-4f03-8f0b-3da976bd5de2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3667565795 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 79.xbar_random_zero_del ays.3667565795 |
| Directory | /workspace/79.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/79.xbar_same_source.4101172928 |
| Short name | T2303 |
| Test name | |
| Test status | |
| Simulation time | 722622482 ps |
| CPU time | 22.56 seconds |
| Started | Aug 13 06:58:38 PM PDT 24 |
| Finished | Aug 13 06:59:01 PM PDT 24 |
| Peak memory | 575596 kb |
| Host | smart-88ebe015-2d8f-4253-84de-22b48022a09a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4101172928 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 79.xbar_same_source.4101172928 |
| Directory | /workspace/79.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/79.xbar_smoke.8829433 |
| Short name | T2886 |
| Test name | |
| Test status | |
| Simulation time | 50969374 ps |
| CPU time | 6.53 seconds |
| Started | Aug 13 06:58:36 PM PDT 24 |
| Finished | Aug 13 06:58:42 PM PDT 24 |
| Peak memory | 573544 kb |
| Host | smart-489280a3-e845-46af-89b3-bf9d1a2bf67f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=8829433 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 79.xbar_smoke.8829433 |
| Directory | /workspace/79.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/79.xbar_smoke_large_delays.2341437683 |
| Short name | T2430 |
| Test name | |
| Test status | |
| Simulation time | 9919792389 ps |
| CPU time | 111.06 seconds |
| Started | Aug 13 06:58:37 PM PDT 24 |
| Finished | Aug 13 07:00:28 PM PDT 24 |
| Peak memory | 574308 kb |
| Host | smart-af731fe7-fc8e-41b9-82ec-812f9c0d8ead |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2341437683 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 79.xbar_smoke_large_delays.2341437683 |
| Directory | /workspace/79.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/79.xbar_smoke_slow_rsp.2995361741 |
| Short name | T2877 |
| Test name | |
| Test status | |
| Simulation time | 4624360014 ps |
| CPU time | 72.16 seconds |
| Started | Aug 13 06:58:36 PM PDT 24 |
| Finished | Aug 13 06:59:48 PM PDT 24 |
| Peak memory | 573680 kb |
| Host | smart-f7dfc5b6-f23c-4b39-b797-47a9db8035c8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2995361741 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 79.xbar_smoke_slow_rsp.2995361741 |
| Directory | /workspace/79.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/79.xbar_smoke_zero_delays.2626911802 |
| Short name | T708 |
| Test name | |
| Test status | |
| Simulation time | 42926829 ps |
| CPU time | 6.01 seconds |
| Started | Aug 13 06:58:36 PM PDT 24 |
| Finished | Aug 13 06:58:42 PM PDT 24 |
| Peak memory | 573536 kb |
| Host | smart-f4c8b97e-9e46-447c-9284-26f9828b3c2e |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2626911802 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 79.xbar_smoke_zero_delay s.2626911802 |
| Directory | /workspace/79.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/79.xbar_stress_all.3139148218 |
| Short name | T2933 |
| Test name | |
| Test status | |
| Simulation time | 23482281995 ps |
| CPU time | 915.46 seconds |
| Started | Aug 13 06:58:36 PM PDT 24 |
| Finished | Aug 13 07:13:52 PM PDT 24 |
| Peak memory | 575704 kb |
| Host | smart-70504329-e36d-43df-bedd-edbdeb44f9bf |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3139148218 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 79.xbar_stress_all.3139148218 |
| Directory | /workspace/79.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/79.xbar_stress_all_with_error.3009169700 |
| Short name | T2122 |
| Test name | |
| Test status | |
| Simulation time | 13073158159 ps |
| CPU time | 439.01 seconds |
| Started | Aug 13 06:58:36 PM PDT 24 |
| Finished | Aug 13 07:05:55 PM PDT 24 |
| Peak memory | 576584 kb |
| Host | smart-6d30b406-fb61-4716-8620-b9988796e691 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3009169700 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 79.xbar_stress_all_with_error.3009169700 |
| Directory | /workspace/79.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/79.xbar_stress_all_with_rand_reset.1086621401 |
| Short name | T607 |
| Test name | |
| Test status | |
| Simulation time | 1253405126 ps |
| CPU time | 161.49 seconds |
| Started | Aug 13 06:58:37 PM PDT 24 |
| Finished | Aug 13 07:01:19 PM PDT 24 |
| Peak memory | 575720 kb |
| Host | smart-ce7a082e-6f4c-4e1d-b8c7-4a208a8609dc |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1086621401 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 79.xbar_stress_all _with_rand_reset.1086621401 |
| Directory | /workspace/79.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/79.xbar_stress_all_with_reset_error.991510549 |
| Short name | T2440 |
| Test name | |
| Test status | |
| Simulation time | 2268958854 ps |
| CPU time | 283.41 seconds |
| Started | Aug 13 06:58:35 PM PDT 24 |
| Finished | Aug 13 07:03:19 PM PDT 24 |
| Peak memory | 575740 kb |
| Host | smart-6b31c988-8c91-4cd9-81b3-ea036f12e586 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=991510549 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 79.xbar_stress_all _with_reset_error.991510549 |
| Directory | /workspace/79.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/79.xbar_unmapped_addr.3319976345 |
| Short name | T623 |
| Test name | |
| Test status | |
| Simulation time | 1010920579 ps |
| CPU time | 39.98 seconds |
| Started | Aug 13 06:58:39 PM PDT 24 |
| Finished | Aug 13 06:59:19 PM PDT 24 |
| Peak memory | 575716 kb |
| Host | smart-4e2d4a4f-1d2a-4a0a-bda5-f088842cb37f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3319976345 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 79.xbar_unmapped_addr.3319976345 |
| Directory | /workspace/79.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/8.chip_csr_mem_rw_with_rand_reset.4025491123 |
| Short name | T2273 |
| Test name | |
| Test status | |
| Simulation time | 9293266622 ps |
| CPU time | 876.56 seconds |
| Started | Aug 13 06:51:14 PM PDT 24 |
| Finished | Aug 13 07:05:51 PM PDT 24 |
| Peak memory | 652696 kb |
| Host | smart-8cf8a721-8bab-4527-9ca2-d2ed23cd3bb5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4025491123 -assert nopostproc + UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top .vdb -cm_log /dev/null -cm_name 8.chip_csr_mem_rw_with_rand_reset.4025491123 |
| Directory | /workspace/8.chip_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/8.chip_csr_rw.3099863788 |
| Short name | T391 |
| Test name | |
| Test status | |
| Simulation time | 4577930725 ps |
| CPU time | 343.37 seconds |
| Started | Aug 13 06:50:56 PM PDT 24 |
| Finished | Aug 13 06:56:40 PM PDT 24 |
| Peak memory | 597048 kb |
| Host | smart-988ae3a1-5967-45a9-96e0-5cdc2445cc27 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3099863788 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.chip_csr_rw.3099863788 |
| Directory | /workspace/8.chip_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/8.chip_same_csr_outstanding.895841686 |
| Short name | T2325 |
| Test name | |
| Test status | |
| Simulation time | 14899689154 ps |
| CPU time | 1566.53 seconds |
| Started | Aug 13 06:50:49 PM PDT 24 |
| Finished | Aug 13 07:16:55 PM PDT 24 |
| Peak memory | 592920 kb |
| Host | smart-7100805e-edbf-4a60-8c93-757bb383dfb6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +run_same_csr_outstanding +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=895841686 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c m_log /dev/null -cm_name 8.chip_same_csr_outstanding.895841686 |
| Directory | /workspace/8.chip_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/8.chip_tl_errors.1101006438 |
| Short name | T2840 |
| Test name | |
| Test status | |
| Simulation time | 3652835600 ps |
| CPU time | 253.58 seconds |
| Started | Aug 13 06:51:10 PM PDT 24 |
| Finished | Aug 13 06:55:24 PM PDT 24 |
| Peak memory | 603464 kb |
| Host | smart-32eae84e-abf8-4ebc-83e1-125e4d6ff0af |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1101006438 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.chip_tl_errors.1101006438 |
| Directory | /workspace/8.chip_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/8.xbar_access_same_device.29983136 |
| Short name | T2745 |
| Test name | |
| Test status | |
| Simulation time | 2685948651 ps |
| CPU time | 117.01 seconds |
| Started | Aug 13 06:51:08 PM PDT 24 |
| Finished | Aug 13 06:53:05 PM PDT 24 |
| Peak memory | 575572 kb |
| Host | smart-dcfddfa6-eb9d-4223-8d62-a8a9c4e528c6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29983136 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.xbar_access_same_device.29983136 |
| Directory | /workspace/8.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/8.xbar_access_same_device_slow_rsp.3213253921 |
| Short name | T1599 |
| Test name | |
| Test status | |
| Simulation time | 31654754256 ps |
| CPU time | 533.21 seconds |
| Started | Aug 13 06:51:10 PM PDT 24 |
| Finished | Aug 13 07:00:04 PM PDT 24 |
| Peak memory | 575544 kb |
| Host | smart-666989b8-68ed-471e-ad95-9f60c2a97d08 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3213253921 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.xbar_access_same_d evice_slow_rsp.3213253921 |
| Directory | /workspace/8.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/8.xbar_error_and_unmapped_addr.2201852330 |
| Short name | T1580 |
| Test name | |
| Test status | |
| Simulation time | 922094821 ps |
| CPU time | 35.38 seconds |
| Started | Aug 13 06:51:06 PM PDT 24 |
| Finished | Aug 13 06:51:42 PM PDT 24 |
| Peak memory | 575504 kb |
| Host | smart-23513ffb-69e3-498b-8d9b-61f23c0c9596 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2201852330 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.xbar_error_and_unmapped_addr .2201852330 |
| Directory | /workspace/8.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/8.xbar_error_random.3551110260 |
| Short name | T1826 |
| Test name | |
| Test status | |
| Simulation time | 241137189 ps |
| CPU time | 11.84 seconds |
| Started | Aug 13 06:51:09 PM PDT 24 |
| Finished | Aug 13 06:51:21 PM PDT 24 |
| Peak memory | 575480 kb |
| Host | smart-e3bca22e-0b93-40c1-9cc8-058eaea8415d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3551110260 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.xbar_error_random.3551110260 |
| Directory | /workspace/8.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/8.xbar_random.4213534106 |
| Short name | T2825 |
| Test name | |
| Test status | |
| Simulation time | 146761281 ps |
| CPU time | 8.17 seconds |
| Started | Aug 13 06:51:10 PM PDT 24 |
| Finished | Aug 13 06:51:19 PM PDT 24 |
| Peak memory | 573528 kb |
| Host | smart-c8db64c5-6904-4313-b67f-4913c532dee3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4213534106 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.xbar_random.4213534106 |
| Directory | /workspace/8.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/8.xbar_random_large_delays.2348418701 |
| Short name | T2067 |
| Test name | |
| Test status | |
| Simulation time | 58956120072 ps |
| CPU time | 637.04 seconds |
| Started | Aug 13 06:51:13 PM PDT 24 |
| Finished | Aug 13 07:01:50 PM PDT 24 |
| Peak memory | 575728 kb |
| Host | smart-ff1de380-1b47-4407-93cb-b2a126107c1b |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2348418701 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.xbar_random_large_delays.2348418701 |
| Directory | /workspace/8.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/8.xbar_random_slow_rsp.4056731672 |
| Short name | T514 |
| Test name | |
| Test status | |
| Simulation time | 11603608609 ps |
| CPU time | 200.13 seconds |
| Started | Aug 13 06:51:14 PM PDT 24 |
| Finished | Aug 13 06:54:35 PM PDT 24 |
| Peak memory | 575800 kb |
| Host | smart-9f336c69-c8ea-4ad7-8692-dd08d33857e9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4056731672 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.xbar_random_slow_rsp.4056731672 |
| Directory | /workspace/8.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/8.xbar_random_zero_delays.1995742008 |
| Short name | T2365 |
| Test name | |
| Test status | |
| Simulation time | 250384298 ps |
| CPU time | 20.91 seconds |
| Started | Aug 13 06:50:59 PM PDT 24 |
| Finished | Aug 13 06:51:20 PM PDT 24 |
| Peak memory | 575484 kb |
| Host | smart-11f53f5d-8bae-4674-9281-deeb9419a34f |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1995742008 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.xbar_random_zero_dela ys.1995742008 |
| Directory | /workspace/8.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/8.xbar_same_source.3303498799 |
| Short name | T2050 |
| Test name | |
| Test status | |
| Simulation time | 563154102 ps |
| CPU time | 39.77 seconds |
| Started | Aug 13 06:51:05 PM PDT 24 |
| Finished | Aug 13 06:51:45 PM PDT 24 |
| Peak memory | 575508 kb |
| Host | smart-f79618e4-0eff-4b4d-874c-040949b00a7e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3303498799 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.xbar_same_source.3303498799 |
| Directory | /workspace/8.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/8.xbar_smoke.593361648 |
| Short name | T1791 |
| Test name | |
| Test status | |
| Simulation time | 195319864 ps |
| CPU time | 9.21 seconds |
| Started | Aug 13 06:51:10 PM PDT 24 |
| Finished | Aug 13 06:51:20 PM PDT 24 |
| Peak memory | 573604 kb |
| Host | smart-5114a5e0-29f9-4066-ab45-3772d669a815 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=593361648 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.xbar_smoke.593361648 |
| Directory | /workspace/8.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/8.xbar_smoke_large_delays.2085126547 |
| Short name | T1431 |
| Test name | |
| Test status | |
| Simulation time | 8301450148 ps |
| CPU time | 81.86 seconds |
| Started | Aug 13 06:50:58 PM PDT 24 |
| Finished | Aug 13 06:52:20 PM PDT 24 |
| Peak memory | 573668 kb |
| Host | smart-8e03a249-7571-433b-ac9d-51bb214572bf |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2085126547 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.xbar_smoke_large_delays.2085126547 |
| Directory | /workspace/8.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/8.xbar_smoke_slow_rsp.4059473106 |
| Short name | T2621 |
| Test name | |
| Test status | |
| Simulation time | 4515447551 ps |
| CPU time | 75.49 seconds |
| Started | Aug 13 06:51:10 PM PDT 24 |
| Finished | Aug 13 06:52:26 PM PDT 24 |
| Peak memory | 574332 kb |
| Host | smart-eda944ca-b1aa-4f2d-a555-8d677ca95a35 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4059473106 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.xbar_smoke_slow_rsp.4059473106 |
| Directory | /workspace/8.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/8.xbar_smoke_zero_delays.2389719500 |
| Short name | T2167 |
| Test name | |
| Test status | |
| Simulation time | 54825916 ps |
| CPU time | 6.49 seconds |
| Started | Aug 13 06:50:59 PM PDT 24 |
| Finished | Aug 13 06:51:05 PM PDT 24 |
| Peak memory | 574248 kb |
| Host | smart-eb146ffa-57ce-49c0-8bf5-53b5c93595d3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2389719500 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.xbar_smoke_zero_delays .2389719500 |
| Directory | /workspace/8.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/8.xbar_stress_all.813368851 |
| Short name | T2289 |
| Test name | |
| Test status | |
| Simulation time | 10626733338 ps |
| CPU time | 321.01 seconds |
| Started | Aug 13 06:51:11 PM PDT 24 |
| Finished | Aug 13 06:56:32 PM PDT 24 |
| Peak memory | 576556 kb |
| Host | smart-a86eef1a-b0f2-40c6-9db7-f7e5c83b4a1b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=813368851 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.xbar_stress_all.813368851 |
| Directory | /workspace/8.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/8.xbar_stress_all_with_error.1891057937 |
| Short name | T2069 |
| Test name | |
| Test status | |
| Simulation time | 3288259987 ps |
| CPU time | 264.81 seconds |
| Started | Aug 13 06:50:57 PM PDT 24 |
| Finished | Aug 13 06:55:22 PM PDT 24 |
| Peak memory | 576568 kb |
| Host | smart-edcced66-4566-44d9-a594-b6ef94472409 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1891057937 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.xbar_stress_all_with_error.1891057937 |
| Directory | /workspace/8.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/8.xbar_stress_all_with_rand_reset.1327854714 |
| Short name | T2500 |
| Test name | |
| Test status | |
| Simulation time | 3960975309 ps |
| CPU time | 263.53 seconds |
| Started | Aug 13 06:51:09 PM PDT 24 |
| Finished | Aug 13 06:55:33 PM PDT 24 |
| Peak memory | 575732 kb |
| Host | smart-61dd7503-a13c-4a93-bd8e-5e1844377b88 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1327854714 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.xbar_stress_all_ with_rand_reset.1327854714 |
| Directory | /workspace/8.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/8.xbar_stress_all_with_reset_error.685425289 |
| Short name | T1650 |
| Test name | |
| Test status | |
| Simulation time | 331886903 ps |
| CPU time | 95.3 seconds |
| Started | Aug 13 06:51:07 PM PDT 24 |
| Finished | Aug 13 06:52:42 PM PDT 24 |
| Peak memory | 575432 kb |
| Host | smart-fbaaf1de-0628-4782-8a75-5997432c7929 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=685425289 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.xbar_stress_all_ with_reset_error.685425289 |
| Directory | /workspace/8.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/8.xbar_unmapped_addr.1175910648 |
| Short name | T2435 |
| Test name | |
| Test status | |
| Simulation time | 327527665 ps |
| CPU time | 14.69 seconds |
| Started | Aug 13 06:51:05 PM PDT 24 |
| Finished | Aug 13 06:51:20 PM PDT 24 |
| Peak memory | 575692 kb |
| Host | smart-5f3ce1ff-2f2a-4f64-ab19-7fd74d048f64 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1175910648 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.xbar_unmapped_addr.1175910648 |
| Directory | /workspace/8.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/80.xbar_access_same_device.4041323996 |
| Short name | T2728 |
| Test name | |
| Test status | |
| Simulation time | 148768478 ps |
| CPU time | 19.58 seconds |
| Started | Aug 13 06:58:43 PM PDT 24 |
| Finished | Aug 13 06:59:03 PM PDT 24 |
| Peak memory | 575668 kb |
| Host | smart-4c422b86-e40d-4a09-bfa4-8fbf5ac51093 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4041323996 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 80.xbar_access_same_device .4041323996 |
| Directory | /workspace/80.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/80.xbar_access_same_device_slow_rsp.2745117299 |
| Short name | T2743 |
| Test name | |
| Test status | |
| Simulation time | 36765746476 ps |
| CPU time | 667.74 seconds |
| Started | Aug 13 06:58:41 PM PDT 24 |
| Finished | Aug 13 07:09:49 PM PDT 24 |
| Peak memory | 575816 kb |
| Host | smart-9433fbd1-78c3-45ac-a2ca-f3c1290a86ef |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2745117299 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 80.xbar_access_same_ device_slow_rsp.2745117299 |
| Directory | /workspace/80.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/80.xbar_error_and_unmapped_addr.2951613051 |
| Short name | T1577 |
| Test name | |
| Test status | |
| Simulation time | 308753110 ps |
| CPU time | 13.95 seconds |
| Started | Aug 13 06:58:51 PM PDT 24 |
| Finished | Aug 13 06:59:05 PM PDT 24 |
| Peak memory | 575728 kb |
| Host | smart-9b114b41-2af6-4529-84f7-b96a7c9723d1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2951613051 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 80.xbar_error_and_unmapped_add r.2951613051 |
| Directory | /workspace/80.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/80.xbar_error_random.415992668 |
| Short name | T1550 |
| Test name | |
| Test status | |
| Simulation time | 460199399 ps |
| CPU time | 31.95 seconds |
| Started | Aug 13 06:58:48 PM PDT 24 |
| Finished | Aug 13 06:59:20 PM PDT 24 |
| Peak memory | 575624 kb |
| Host | smart-c7963fb2-e53d-45f8-ac00-82d4e471e910 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=415992668 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 80.xbar_error_random.415992668 |
| Directory | /workspace/80.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/80.xbar_random.2925127798 |
| Short name | T2004 |
| Test name | |
| Test status | |
| Simulation time | 785393224 ps |
| CPU time | 29.57 seconds |
| Started | Aug 13 06:58:42 PM PDT 24 |
| Finished | Aug 13 06:59:11 PM PDT 24 |
| Peak memory | 575516 kb |
| Host | smart-9f9512ce-bfe3-4808-94a4-c8bbdb9db519 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2925127798 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 80.xbar_random.2925127798 |
| Directory | /workspace/80.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/80.xbar_random_large_delays.1084261887 |
| Short name | T2911 |
| Test name | |
| Test status | |
| Simulation time | 102348734449 ps |
| CPU time | 1256.58 seconds |
| Started | Aug 13 06:58:51 PM PDT 24 |
| Finished | Aug 13 07:19:48 PM PDT 24 |
| Peak memory | 575680 kb |
| Host | smart-d8bc4d6f-ba8b-47ac-b299-83f474875dd0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1084261887 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 80.xbar_random_large_delays.1084261887 |
| Directory | /workspace/80.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/80.xbar_random_slow_rsp.501184975 |
| Short name | T705 |
| Test name | |
| Test status | |
| Simulation time | 18329745801 ps |
| CPU time | 326.63 seconds |
| Started | Aug 13 06:58:42 PM PDT 24 |
| Finished | Aug 13 07:04:09 PM PDT 24 |
| Peak memory | 575736 kb |
| Host | smart-9f5a5d99-6da0-41ec-9243-4e2a04f64d77 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=501184975 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 80.xbar_random_slow_rsp.501184975 |
| Directory | /workspace/80.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/80.xbar_random_zero_delays.4008863567 |
| Short name | T541 |
| Test name | |
| Test status | |
| Simulation time | 461934758 ps |
| CPU time | 41.4 seconds |
| Started | Aug 13 06:58:45 PM PDT 24 |
| Finished | Aug 13 06:59:26 PM PDT 24 |
| Peak memory | 575460 kb |
| Host | smart-749cfa3a-ce9c-493c-87b0-08a961a59481 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4008863567 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 80.xbar_random_zero_del ays.4008863567 |
| Directory | /workspace/80.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/80.xbar_same_source.3389018596 |
| Short name | T2043 |
| Test name | |
| Test status | |
| Simulation time | 195701716 ps |
| CPU time | 13.5 seconds |
| Started | Aug 13 06:58:41 PM PDT 24 |
| Finished | Aug 13 06:58:54 PM PDT 24 |
| Peak memory | 575684 kb |
| Host | smart-cfec0a20-068f-43b9-8dca-a5f2f1f6bc63 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3389018596 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 80.xbar_same_source.3389018596 |
| Directory | /workspace/80.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/80.xbar_smoke.1118873506 |
| Short name | T2395 |
| Test name | |
| Test status | |
| Simulation time | 45828883 ps |
| CPU time | 6.7 seconds |
| Started | Aug 13 06:58:42 PM PDT 24 |
| Finished | Aug 13 06:58:48 PM PDT 24 |
| Peak memory | 573556 kb |
| Host | smart-8a0f7bb7-95f9-42e2-9d2f-c403b88d7e98 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1118873506 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 80.xbar_smoke.1118873506 |
| Directory | /workspace/80.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/80.xbar_smoke_large_delays.1977062889 |
| Short name | T1796 |
| Test name | |
| Test status | |
| Simulation time | 6675636483 ps |
| CPU time | 72.39 seconds |
| Started | Aug 13 06:58:41 PM PDT 24 |
| Finished | Aug 13 06:59:54 PM PDT 24 |
| Peak memory | 573636 kb |
| Host | smart-93ebc2b5-6d51-4758-ad6d-c29b916ec06f |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1977062889 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 80.xbar_smoke_large_delays.1977062889 |
| Directory | /workspace/80.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/80.xbar_smoke_slow_rsp.480381722 |
| Short name | T1759 |
| Test name | |
| Test status | |
| Simulation time | 5482534351 ps |
| CPU time | 92.37 seconds |
| Started | Aug 13 06:58:44 PM PDT 24 |
| Finished | Aug 13 07:00:16 PM PDT 24 |
| Peak memory | 574352 kb |
| Host | smart-b9705c2b-3800-4c8a-8752-0c507f91c20a |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=480381722 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 80.xbar_smoke_slow_rsp.480381722 |
| Directory | /workspace/80.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/80.xbar_smoke_zero_delays.2409492199 |
| Short name | T1695 |
| Test name | |
| Test status | |
| Simulation time | 47769928 ps |
| CPU time | 6.51 seconds |
| Started | Aug 13 06:58:43 PM PDT 24 |
| Finished | Aug 13 06:58:50 PM PDT 24 |
| Peak memory | 574228 kb |
| Host | smart-a01c1be5-b754-4a3a-9da3-e2ba9ea5d382 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2409492199 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 80.xbar_smoke_zero_delay s.2409492199 |
| Directory | /workspace/80.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/80.xbar_stress_all.3081764199 |
| Short name | T2492 |
| Test name | |
| Test status | |
| Simulation time | 1237948092 ps |
| CPU time | 85.31 seconds |
| Started | Aug 13 06:58:43 PM PDT 24 |
| Finished | Aug 13 07:00:08 PM PDT 24 |
| Peak memory | 575700 kb |
| Host | smart-2a0cd177-0422-4660-939f-a00141917cc9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3081764199 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 80.xbar_stress_all.3081764199 |
| Directory | /workspace/80.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/80.xbar_stress_all_with_error.1293782960 |
| Short name | T2710 |
| Test name | |
| Test status | |
| Simulation time | 15027857792 ps |
| CPU time | 518.3 seconds |
| Started | Aug 13 06:58:44 PM PDT 24 |
| Finished | Aug 13 07:07:23 PM PDT 24 |
| Peak memory | 576516 kb |
| Host | smart-1d21c2f8-d379-4a4c-bc5f-98d16d33dd2a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1293782960 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 80.xbar_stress_all_with_error.1293782960 |
| Directory | /workspace/80.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/80.xbar_stress_all_with_rand_reset.3254532531 |
| Short name | T1891 |
| Test name | |
| Test status | |
| Simulation time | 1464292943 ps |
| CPU time | 192.94 seconds |
| Started | Aug 13 06:58:49 PM PDT 24 |
| Finished | Aug 13 07:02:02 PM PDT 24 |
| Peak memory | 575632 kb |
| Host | smart-beb9bc6d-de63-47dc-98af-d9e3f7bc4ecf |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3254532531 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 80.xbar_stress_all _with_rand_reset.3254532531 |
| Directory | /workspace/80.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/80.xbar_stress_all_with_reset_error.1023917438 |
| Short name | T916 |
| Test name | |
| Test status | |
| Simulation time | 4115261413 ps |
| CPU time | 308.96 seconds |
| Started | Aug 13 06:58:43 PM PDT 24 |
| Finished | Aug 13 07:03:52 PM PDT 24 |
| Peak memory | 576576 kb |
| Host | smart-a0bfc353-1b9d-44e2-81d2-8674e48bd458 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1023917438 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 80.xbar_stress_al l_with_reset_error.1023917438 |
| Directory | /workspace/80.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/80.xbar_unmapped_addr.3698094588 |
| Short name | T518 |
| Test name | |
| Test status | |
| Simulation time | 196057450 ps |
| CPU time | 21.1 seconds |
| Started | Aug 13 06:58:51 PM PDT 24 |
| Finished | Aug 13 06:59:12 PM PDT 24 |
| Peak memory | 575740 kb |
| Host | smart-b7353906-91e9-4df9-bff7-f497e78cecd3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3698094588 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 80.xbar_unmapped_addr.3698094588 |
| Directory | /workspace/80.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/81.xbar_access_same_device.2588536293 |
| Short name | T1795 |
| Test name | |
| Test status | |
| Simulation time | 3103711380 ps |
| CPU time | 115.77 seconds |
| Started | Aug 13 06:59:01 PM PDT 24 |
| Finished | Aug 13 07:00:56 PM PDT 24 |
| Peak memory | 575560 kb |
| Host | smart-3637dbb4-62b9-4c2c-bc3f-8ac43229b2a1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2588536293 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 81.xbar_access_same_device .2588536293 |
| Directory | /workspace/81.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/81.xbar_access_same_device_slow_rsp.3930064398 |
| Short name | T1898 |
| Test name | |
| Test status | |
| Simulation time | 113955638108 ps |
| CPU time | 2029.28 seconds |
| Started | Aug 13 06:58:53 PM PDT 24 |
| Finished | Aug 13 07:32:43 PM PDT 24 |
| Peak memory | 576532 kb |
| Host | smart-bc591d14-4288-4f05-a4d4-0659bda7d0c0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3930064398 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 81.xbar_access_same_ device_slow_rsp.3930064398 |
| Directory | /workspace/81.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/81.xbar_error_and_unmapped_addr.3789161621 |
| Short name | T1613 |
| Test name | |
| Test status | |
| Simulation time | 152281632 ps |
| CPU time | 17.01 seconds |
| Started | Aug 13 06:58:58 PM PDT 24 |
| Finished | Aug 13 06:59:15 PM PDT 24 |
| Peak memory | 575680 kb |
| Host | smart-dbcd98e7-b5e7-45b1-93cb-b883420e2066 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3789161621 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 81.xbar_error_and_unmapped_add r.3789161621 |
| Directory | /workspace/81.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/81.xbar_random.2443651656 |
| Short name | T540 |
| Test name | |
| Test status | |
| Simulation time | 569356918 ps |
| CPU time | 49.94 seconds |
| Started | Aug 13 06:58:50 PM PDT 24 |
| Finished | Aug 13 06:59:40 PM PDT 24 |
| Peak memory | 575712 kb |
| Host | smart-84a7016d-842f-463f-9eed-0dc2e9f9e068 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2443651656 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 81.xbar_random.2443651656 |
| Directory | /workspace/81.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/81.xbar_random_large_delays.2152258913 |
| Short name | T2021 |
| Test name | |
| Test status | |
| Simulation time | 25524374761 ps |
| CPU time | 277.44 seconds |
| Started | Aug 13 06:58:57 PM PDT 24 |
| Finished | Aug 13 07:03:35 PM PDT 24 |
| Peak memory | 575776 kb |
| Host | smart-6a01be9c-60e4-4376-a751-c8abef45daa9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2152258913 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 81.xbar_random_large_delays.2152258913 |
| Directory | /workspace/81.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/81.xbar_random_slow_rsp.466375167 |
| Short name | T2207 |
| Test name | |
| Test status | |
| Simulation time | 9657924641 ps |
| CPU time | 155.58 seconds |
| Started | Aug 13 06:58:55 PM PDT 24 |
| Finished | Aug 13 07:01:30 PM PDT 24 |
| Peak memory | 575576 kb |
| Host | smart-4e12389a-220d-43c1-bd74-9470656c7abe |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=466375167 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 81.xbar_random_slow_rsp.466375167 |
| Directory | /workspace/81.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/81.xbar_random_zero_delays.1109569687 |
| Short name | T2607 |
| Test name | |
| Test status | |
| Simulation time | 83557387 ps |
| CPU time | 9.77 seconds |
| Started | Aug 13 06:59:00 PM PDT 24 |
| Finished | Aug 13 06:59:10 PM PDT 24 |
| Peak memory | 575624 kb |
| Host | smart-5affa2b9-55ff-4d71-829a-f8717c377d57 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1109569687 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 81.xbar_random_zero_del ays.1109569687 |
| Directory | /workspace/81.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/81.xbar_same_source.2776884500 |
| Short name | T2458 |
| Test name | |
| Test status | |
| Simulation time | 128946911 ps |
| CPU time | 12 seconds |
| Started | Aug 13 06:58:54 PM PDT 24 |
| Finished | Aug 13 06:59:06 PM PDT 24 |
| Peak memory | 575508 kb |
| Host | smart-bf67d2d2-46b6-44b5-b816-304bd5c2ce9b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2776884500 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 81.xbar_same_source.2776884500 |
| Directory | /workspace/81.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/81.xbar_smoke.1942183790 |
| Short name | T2723 |
| Test name | |
| Test status | |
| Simulation time | 53211494 ps |
| CPU time | 6.32 seconds |
| Started | Aug 13 06:58:44 PM PDT 24 |
| Finished | Aug 13 06:58:50 PM PDT 24 |
| Peak memory | 573572 kb |
| Host | smart-368c3671-3dca-4e6b-ad4c-1980af656086 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1942183790 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 81.xbar_smoke.1942183790 |
| Directory | /workspace/81.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/81.xbar_smoke_large_delays.1401409090 |
| Short name | T661 |
| Test name | |
| Test status | |
| Simulation time | 7751066205 ps |
| CPU time | 85.87 seconds |
| Started | Aug 13 06:58:50 PM PDT 24 |
| Finished | Aug 13 07:00:16 PM PDT 24 |
| Peak memory | 573544 kb |
| Host | smart-bc3b44e5-71b5-49f4-89fa-14ecd8b7d36f |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1401409090 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 81.xbar_smoke_large_delays.1401409090 |
| Directory | /workspace/81.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/81.xbar_smoke_slow_rsp.3768988551 |
| Short name | T2169 |
| Test name | |
| Test status | |
| Simulation time | 5294641379 ps |
| CPU time | 82.48 seconds |
| Started | Aug 13 06:58:54 PM PDT 24 |
| Finished | Aug 13 07:00:17 PM PDT 24 |
| Peak memory | 574328 kb |
| Host | smart-29e07602-c12d-45e7-82f0-3f479b160f9c |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3768988551 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 81.xbar_smoke_slow_rsp.3768988551 |
| Directory | /workspace/81.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/81.xbar_smoke_zero_delays.996802341 |
| Short name | T2898 |
| Test name | |
| Test status | |
| Simulation time | 51103670 ps |
| CPU time | 7.01 seconds |
| Started | Aug 13 06:58:57 PM PDT 24 |
| Finished | Aug 13 06:59:04 PM PDT 24 |
| Peak memory | 573596 kb |
| Host | smart-4c8b4705-b88f-4d3f-914f-376cb9904adf |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=996802341 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 81.xbar_smoke_zero_delays .996802341 |
| Directory | /workspace/81.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/81.xbar_stress_all_with_error.3874302816 |
| Short name | T2285 |
| Test name | |
| Test status | |
| Simulation time | 5741354116 ps |
| CPU time | 168.53 seconds |
| Started | Aug 13 06:59:10 PM PDT 24 |
| Finished | Aug 13 07:01:58 PM PDT 24 |
| Peak memory | 574520 kb |
| Host | smart-a3e8cffe-7a2c-4691-ad27-5965111b6c4a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3874302816 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 81.xbar_stress_all_with_error.3874302816 |
| Directory | /workspace/81.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/81.xbar_stress_all_with_reset_error.2355081998 |
| Short name | T1753 |
| Test name | |
| Test status | |
| Simulation time | 1876482096 ps |
| CPU time | 166.85 seconds |
| Started | Aug 13 06:59:19 PM PDT 24 |
| Finished | Aug 13 07:02:06 PM PDT 24 |
| Peak memory | 576512 kb |
| Host | smart-044213af-77f5-4b13-8327-5e000a591928 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2355081998 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 81.xbar_stress_al l_with_reset_error.2355081998 |
| Directory | /workspace/81.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/81.xbar_unmapped_addr.2105240942 |
| Short name | T1982 |
| Test name | |
| Test status | |
| Simulation time | 72022539 ps |
| CPU time | 6.26 seconds |
| Started | Aug 13 06:58:57 PM PDT 24 |
| Finished | Aug 13 06:59:04 PM PDT 24 |
| Peak memory | 573588 kb |
| Host | smart-4eccb9d3-8f52-4029-a311-2073f93c2118 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2105240942 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 81.xbar_unmapped_addr.2105240942 |
| Directory | /workspace/81.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/82.xbar_access_same_device.3643586054 |
| Short name | T880 |
| Test name | |
| Test status | |
| Simulation time | 460057462 ps |
| CPU time | 18.4 seconds |
| Started | Aug 13 06:59:19 PM PDT 24 |
| Finished | Aug 13 06:59:37 PM PDT 24 |
| Peak memory | 575672 kb |
| Host | smart-ac2a4b5c-1312-4737-83c3-86f791238d77 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3643586054 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 82.xbar_access_same_device .3643586054 |
| Directory | /workspace/82.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/82.xbar_access_same_device_slow_rsp.3788376077 |
| Short name | T1846 |
| Test name | |
| Test status | |
| Simulation time | 93794531132 ps |
| CPU time | 1715.61 seconds |
| Started | Aug 13 06:58:57 PM PDT 24 |
| Finished | Aug 13 07:27:33 PM PDT 24 |
| Peak memory | 575728 kb |
| Host | smart-5a457b3f-4f65-4d31-8822-62a35a631605 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3788376077 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 82.xbar_access_same_ device_slow_rsp.3788376077 |
| Directory | /workspace/82.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/82.xbar_error_and_unmapped_addr.2835957525 |
| Short name | T2611 |
| Test name | |
| Test status | |
| Simulation time | 1092485786 ps |
| CPU time | 43.01 seconds |
| Started | Aug 13 06:59:08 PM PDT 24 |
| Finished | Aug 13 06:59:51 PM PDT 24 |
| Peak memory | 575668 kb |
| Host | smart-002c8670-cd7a-4bcf-af00-1eb56a06ce87 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2835957525 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 82.xbar_error_and_unmapped_add r.2835957525 |
| Directory | /workspace/82.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/82.xbar_error_random.4071173051 |
| Short name | T2176 |
| Test name | |
| Test status | |
| Simulation time | 1071411086 ps |
| CPU time | 34.13 seconds |
| Started | Aug 13 06:59:18 PM PDT 24 |
| Finished | Aug 13 06:59:52 PM PDT 24 |
| Peak memory | 575676 kb |
| Host | smart-e8e7df45-52bf-4660-82f2-5054d75d81e5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4071173051 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 82.xbar_error_random.4071173051 |
| Directory | /workspace/82.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/82.xbar_random.942239259 |
| Short name | T517 |
| Test name | |
| Test status | |
| Simulation time | 1775655973 ps |
| CPU time | 59.64 seconds |
| Started | Aug 13 06:59:09 PM PDT 24 |
| Finished | Aug 13 07:00:09 PM PDT 24 |
| Peak memory | 574300 kb |
| Host | smart-cd49642d-ce66-4dbb-a40a-f9ab7870a4b9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=942239259 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 82.xbar_random.942239259 |
| Directory | /workspace/82.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/82.xbar_random_large_delays.3961790309 |
| Short name | T507 |
| Test name | |
| Test status | |
| Simulation time | 109133245528 ps |
| CPU time | 1232.08 seconds |
| Started | Aug 13 06:59:19 PM PDT 24 |
| Finished | Aug 13 07:19:51 PM PDT 24 |
| Peak memory | 575716 kb |
| Host | smart-ee4d0ee6-38f4-4b61-857e-1a0f331632d3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3961790309 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 82.xbar_random_large_delays.3961790309 |
| Directory | /workspace/82.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/82.xbar_random_slow_rsp.531018710 |
| Short name | T1693 |
| Test name | |
| Test status | |
| Simulation time | 8063326586 ps |
| CPU time | 139.56 seconds |
| Started | Aug 13 06:58:57 PM PDT 24 |
| Finished | Aug 13 07:01:17 PM PDT 24 |
| Peak memory | 575752 kb |
| Host | smart-d4117ffe-166d-4ed5-877b-438a8c84ad31 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=531018710 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 82.xbar_random_slow_rsp.531018710 |
| Directory | /workspace/82.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/82.xbar_random_zero_delays.996823147 |
| Short name | T1819 |
| Test name | |
| Test status | |
| Simulation time | 404932271 ps |
| CPU time | 32.2 seconds |
| Started | Aug 13 06:59:10 PM PDT 24 |
| Finished | Aug 13 06:59:42 PM PDT 24 |
| Peak memory | 574284 kb |
| Host | smart-cf73abab-e49c-431e-87a1-4b923267a97d |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=996823147 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 82.xbar_random_zero_dela ys.996823147 |
| Directory | /workspace/82.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/82.xbar_same_source.549883954 |
| Short name | T2667 |
| Test name | |
| Test status | |
| Simulation time | 568966532 ps |
| CPU time | 38.05 seconds |
| Started | Aug 13 06:59:19 PM PDT 24 |
| Finished | Aug 13 06:59:57 PM PDT 24 |
| Peak memory | 575668 kb |
| Host | smart-9b8ee0e1-9c18-42da-bae1-49759172a81a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=549883954 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 82.xbar_same_source.549883954 |
| Directory | /workspace/82.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/82.xbar_smoke.45521174 |
| Short name | T2076 |
| Test name | |
| Test status | |
| Simulation time | 191257233 ps |
| CPU time | 9.01 seconds |
| Started | Aug 13 06:59:00 PM PDT 24 |
| Finished | Aug 13 06:59:09 PM PDT 24 |
| Peak memory | 573572 kb |
| Host | smart-bf68768e-205c-45c6-bd9c-e60cf1235a50 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=45521174 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 82.xbar_smoke.45521174 |
| Directory | /workspace/82.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/82.xbar_smoke_large_delays.1467581503 |
| Short name | T2410 |
| Test name | |
| Test status | |
| Simulation time | 8429206967 ps |
| CPU time | 80.47 seconds |
| Started | Aug 13 06:59:19 PM PDT 24 |
| Finished | Aug 13 07:00:39 PM PDT 24 |
| Peak memory | 574348 kb |
| Host | smart-1551b774-881c-4c60-8105-7184fe7be5cc |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1467581503 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 82.xbar_smoke_large_delays.1467581503 |
| Directory | /workspace/82.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/82.xbar_smoke_slow_rsp.2100141925 |
| Short name | T2715 |
| Test name | |
| Test status | |
| Simulation time | 6176358625 ps |
| CPU time | 103.7 seconds |
| Started | Aug 13 06:59:18 PM PDT 24 |
| Finished | Aug 13 07:01:01 PM PDT 24 |
| Peak memory | 573684 kb |
| Host | smart-957338db-4f16-4d86-957d-c968c9d7a23a |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2100141925 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 82.xbar_smoke_slow_rsp.2100141925 |
| Directory | /workspace/82.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/82.xbar_smoke_zero_delays.2278103633 |
| Short name | T1476 |
| Test name | |
| Test status | |
| Simulation time | 51038472 ps |
| CPU time | 6.48 seconds |
| Started | Aug 13 06:58:58 PM PDT 24 |
| Finished | Aug 13 06:59:04 PM PDT 24 |
| Peak memory | 573484 kb |
| Host | smart-64d0a896-6e82-4d53-bc6a-8ef84a5a393e |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2278103633 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 82.xbar_smoke_zero_delay s.2278103633 |
| Directory | /workspace/82.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/82.xbar_stress_all.2742970813 |
| Short name | T2520 |
| Test name | |
| Test status | |
| Simulation time | 790508075 ps |
| CPU time | 59.3 seconds |
| Started | Aug 13 06:59:11 PM PDT 24 |
| Finished | Aug 13 07:00:11 PM PDT 24 |
| Peak memory | 575532 kb |
| Host | smart-141c128a-3c48-4be3-9c0c-8170150634b2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2742970813 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 82.xbar_stress_all.2742970813 |
| Directory | /workspace/82.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/82.xbar_stress_all_with_error.735144200 |
| Short name | T2489 |
| Test name | |
| Test status | |
| Simulation time | 2921641295 ps |
| CPU time | 219.71 seconds |
| Started | Aug 13 06:59:08 PM PDT 24 |
| Finished | Aug 13 07:02:47 PM PDT 24 |
| Peak memory | 576212 kb |
| Host | smart-1e9b8c66-081e-4a34-9be3-5ba2fc2e87b3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=735144200 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 82.xbar_stress_all_with_error.735144200 |
| Directory | /workspace/82.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/82.xbar_stress_all_with_rand_reset.2076130380 |
| Short name | T2777 |
| Test name | |
| Test status | |
| Simulation time | 2004184558 ps |
| CPU time | 242.88 seconds |
| Started | Aug 13 06:59:07 PM PDT 24 |
| Finished | Aug 13 07:03:10 PM PDT 24 |
| Peak memory | 576500 kb |
| Host | smart-934f707d-8f6e-4a32-9d1f-c668f804fb14 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2076130380 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 82.xbar_stress_all _with_rand_reset.2076130380 |
| Directory | /workspace/82.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/82.xbar_stress_all_with_reset_error.188402221 |
| Short name | T2275 |
| Test name | |
| Test status | |
| Simulation time | 4569932082 ps |
| CPU time | 527.66 seconds |
| Started | Aug 13 06:59:06 PM PDT 24 |
| Finished | Aug 13 07:07:54 PM PDT 24 |
| Peak memory | 578584 kb |
| Host | smart-e6bbf8e8-779f-401a-a0db-e913ca16435d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=188402221 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 82.xbar_stress_all _with_reset_error.188402221 |
| Directory | /workspace/82.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/82.xbar_unmapped_addr.3691776685 |
| Short name | T512 |
| Test name | |
| Test status | |
| Simulation time | 167766132 ps |
| CPU time | 20.75 seconds |
| Started | Aug 13 06:59:07 PM PDT 24 |
| Finished | Aug 13 06:59:27 PM PDT 24 |
| Peak memory | 575676 kb |
| Host | smart-3a49d74b-7536-481f-b9a3-df41c2ed66ff |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3691776685 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 82.xbar_unmapped_addr.3691776685 |
| Directory | /workspace/82.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/83.xbar_access_same_device.3533358648 |
| Short name | T1868 |
| Test name | |
| Test status | |
| Simulation time | 2342975290 ps |
| CPU time | 93.56 seconds |
| Started | Aug 13 06:59:16 PM PDT 24 |
| Finished | Aug 13 07:00:50 PM PDT 24 |
| Peak memory | 575540 kb |
| Host | smart-081a5778-bbfe-44fa-8a5b-97f875eafa3d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3533358648 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 83.xbar_access_same_device .3533358648 |
| Directory | /workspace/83.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/83.xbar_access_same_device_slow_rsp.62733598 |
| Short name | T2506 |
| Test name | |
| Test status | |
| Simulation time | 77578582028 ps |
| CPU time | 1438.45 seconds |
| Started | Aug 13 06:59:14 PM PDT 24 |
| Finished | Aug 13 07:23:12 PM PDT 24 |
| Peak memory | 575832 kb |
| Host | smart-b89a7670-1d9d-4314-a5cc-a87371029874 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=62733598 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 83.xbar_access_same_de vice_slow_rsp.62733598 |
| Directory | /workspace/83.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/83.xbar_error_random.2068994664 |
| Short name | T2156 |
| Test name | |
| Test status | |
| Simulation time | 554673501 ps |
| CPU time | 44.72 seconds |
| Started | Aug 13 06:59:15 PM PDT 24 |
| Finished | Aug 13 07:00:00 PM PDT 24 |
| Peak memory | 575488 kb |
| Host | smart-e41be8a1-b873-46a0-9836-e9aad95eee8e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2068994664 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 83.xbar_error_random.2068994664 |
| Directory | /workspace/83.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/83.xbar_random.1216982709 |
| Short name | T639 |
| Test name | |
| Test status | |
| Simulation time | 2535873915 ps |
| CPU time | 84.92 seconds |
| Started | Aug 13 06:59:09 PM PDT 24 |
| Finished | Aug 13 07:00:34 PM PDT 24 |
| Peak memory | 575552 kb |
| Host | smart-cd3e3a96-917a-4782-900d-6e380ffaf7a1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1216982709 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 83.xbar_random.1216982709 |
| Directory | /workspace/83.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/83.xbar_random_large_delays.1561182479 |
| Short name | T2554 |
| Test name | |
| Test status | |
| Simulation time | 80447548132 ps |
| CPU time | 893.69 seconds |
| Started | Aug 13 06:59:05 PM PDT 24 |
| Finished | Aug 13 07:13:59 PM PDT 24 |
| Peak memory | 575720 kb |
| Host | smart-7a4d8f38-abe2-43cd-b66b-9d92c222d1ec |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1561182479 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 83.xbar_random_large_delays.1561182479 |
| Directory | /workspace/83.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/83.xbar_random_slow_rsp.464723901 |
| Short name | T2675 |
| Test name | |
| Test status | |
| Simulation time | 29260308191 ps |
| CPU time | 566.46 seconds |
| Started | Aug 13 06:59:07 PM PDT 24 |
| Finished | Aug 13 07:08:34 PM PDT 24 |
| Peak memory | 575700 kb |
| Host | smart-be61bbc7-f76b-4e55-a787-fd32a979a016 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=464723901 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 83.xbar_random_slow_rsp.464723901 |
| Directory | /workspace/83.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/83.xbar_random_zero_delays.1700387504 |
| Short name | T593 |
| Test name | |
| Test status | |
| Simulation time | 98174696 ps |
| CPU time | 9.98 seconds |
| Started | Aug 13 06:59:06 PM PDT 24 |
| Finished | Aug 13 06:59:16 PM PDT 24 |
| Peak memory | 575636 kb |
| Host | smart-cc53edd4-1d54-4f97-8f9f-c33dacbfd758 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1700387504 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 83.xbar_random_zero_del ays.1700387504 |
| Directory | /workspace/83.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/83.xbar_same_source.397396937 |
| Short name | T2461 |
| Test name | |
| Test status | |
| Simulation time | 154277054 ps |
| CPU time | 11.67 seconds |
| Started | Aug 13 06:59:31 PM PDT 24 |
| Finished | Aug 13 06:59:42 PM PDT 24 |
| Peak memory | 575596 kb |
| Host | smart-9f973f54-3909-4619-9876-c5743a9748d1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=397396937 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 83.xbar_same_source.397396937 |
| Directory | /workspace/83.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/83.xbar_smoke.1380708836 |
| Short name | T2026 |
| Test name | |
| Test status | |
| Simulation time | 51326356 ps |
| CPU time | 6.71 seconds |
| Started | Aug 13 06:59:10 PM PDT 24 |
| Finished | Aug 13 06:59:17 PM PDT 24 |
| Peak memory | 574228 kb |
| Host | smart-6e84b5d3-b0e9-43c3-87e5-573552d6f1c7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1380708836 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 83.xbar_smoke.1380708836 |
| Directory | /workspace/83.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/83.xbar_smoke_large_delays.3922512194 |
| Short name | T2651 |
| Test name | |
| Test status | |
| Simulation time | 8415079606 ps |
| CPU time | 81.2 seconds |
| Started | Aug 13 06:59:06 PM PDT 24 |
| Finished | Aug 13 07:00:27 PM PDT 24 |
| Peak memory | 573696 kb |
| Host | smart-ddd42444-8af7-48f7-8ab7-a970992bdb4b |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3922512194 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 83.xbar_smoke_large_delays.3922512194 |
| Directory | /workspace/83.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/83.xbar_smoke_slow_rsp.4207015440 |
| Short name | T2707 |
| Test name | |
| Test status | |
| Simulation time | 6450012513 ps |
| CPU time | 112.33 seconds |
| Started | Aug 13 06:59:08 PM PDT 24 |
| Finished | Aug 13 07:01:00 PM PDT 24 |
| Peak memory | 574332 kb |
| Host | smart-16b92f7e-a681-4d91-a826-ea2430f74efc |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4207015440 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 83.xbar_smoke_slow_rsp.4207015440 |
| Directory | /workspace/83.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/83.xbar_smoke_zero_delays.3076170983 |
| Short name | T1521 |
| Test name | |
| Test status | |
| Simulation time | 41384503 ps |
| CPU time | 6.08 seconds |
| Started | Aug 13 06:59:05 PM PDT 24 |
| Finished | Aug 13 06:59:11 PM PDT 24 |
| Peak memory | 574336 kb |
| Host | smart-ea62ccdc-aacf-42be-b043-cce034f437cf |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3076170983 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 83.xbar_smoke_zero_delay s.3076170983 |
| Directory | /workspace/83.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/83.xbar_stress_all.4049549411 |
| Short name | T2674 |
| Test name | |
| Test status | |
| Simulation time | 3710430678 ps |
| CPU time | 152.1 seconds |
| Started | Aug 13 06:59:14 PM PDT 24 |
| Finished | Aug 13 07:01:46 PM PDT 24 |
| Peak memory | 575852 kb |
| Host | smart-017aff1b-5b9e-4642-a72d-fe83f3d50668 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4049549411 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 83.xbar_stress_all.4049549411 |
| Directory | /workspace/83.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/83.xbar_stress_all_with_error.4203995207 |
| Short name | T1570 |
| Test name | |
| Test status | |
| Simulation time | 6380699 ps |
| CPU time | 3.76 seconds |
| Started | Aug 13 06:59:14 PM PDT 24 |
| Finished | Aug 13 06:59:18 PM PDT 24 |
| Peak memory | 565180 kb |
| Host | smart-a178726f-5581-41f5-b428-5863f0cb9cbb |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4203995207 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 83.xbar_stress_all_with_error.4203995207 |
| Directory | /workspace/83.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/83.xbar_stress_all_with_rand_reset.1186563451 |
| Short name | T2907 |
| Test name | |
| Test status | |
| Simulation time | 2352903989 ps |
| CPU time | 335.14 seconds |
| Started | Aug 13 06:59:14 PM PDT 24 |
| Finished | Aug 13 07:04:49 PM PDT 24 |
| Peak memory | 575704 kb |
| Host | smart-436f8029-07e0-4551-9244-af658471bfd5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1186563451 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 83.xbar_stress_all _with_rand_reset.1186563451 |
| Directory | /workspace/83.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/83.xbar_stress_all_with_reset_error.696685877 |
| Short name | T2854 |
| Test name | |
| Test status | |
| Simulation time | 5719511828 ps |
| CPU time | 436.59 seconds |
| Started | Aug 13 06:59:13 PM PDT 24 |
| Finished | Aug 13 07:06:30 PM PDT 24 |
| Peak memory | 576584 kb |
| Host | smart-4d82d458-f780-4b7c-a2ec-00a3a4938cec |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=696685877 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 83.xbar_stress_all _with_reset_error.696685877 |
| Directory | /workspace/83.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/83.xbar_unmapped_addr.4021771935 |
| Short name | T2594 |
| Test name | |
| Test status | |
| Simulation time | 1113407114 ps |
| CPU time | 48.13 seconds |
| Started | Aug 13 06:59:19 PM PDT 24 |
| Finished | Aug 13 07:00:07 PM PDT 24 |
| Peak memory | 575664 kb |
| Host | smart-f866ebd8-5463-46dd-8296-a38f05577615 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4021771935 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 83.xbar_unmapped_addr.4021771935 |
| Directory | /workspace/83.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/84.xbar_access_same_device.3198535915 |
| Short name | T2287 |
| Test name | |
| Test status | |
| Simulation time | 2750724122 ps |
| CPU time | 102.33 seconds |
| Started | Aug 13 06:59:31 PM PDT 24 |
| Finished | Aug 13 07:01:13 PM PDT 24 |
| Peak memory | 575584 kb |
| Host | smart-8c6e4dc3-640a-4a30-853e-c5ab7fce0944 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3198535915 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 84.xbar_access_same_device .3198535915 |
| Directory | /workspace/84.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/84.xbar_access_same_device_slow_rsp.691722327 |
| Short name | T2307 |
| Test name | |
| Test status | |
| Simulation time | 44556079329 ps |
| CPU time | 799.23 seconds |
| Started | Aug 13 06:59:14 PM PDT 24 |
| Finished | Aug 13 07:12:34 PM PDT 24 |
| Peak memory | 575816 kb |
| Host | smart-90441a8c-2bd4-4439-81a8-f5be97d4e12c |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=691722327 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 84.xbar_access_same_d evice_slow_rsp.691722327 |
| Directory | /workspace/84.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/84.xbar_error_and_unmapped_addr.3458470204 |
| Short name | T2247 |
| Test name | |
| Test status | |
| Simulation time | 1247962363 ps |
| CPU time | 47.97 seconds |
| Started | Aug 13 06:59:22 PM PDT 24 |
| Finished | Aug 13 07:00:10 PM PDT 24 |
| Peak memory | 575496 kb |
| Host | smart-bf28bec8-c2fe-4a6e-b54d-1fbee9552598 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3458470204 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 84.xbar_error_and_unmapped_add r.3458470204 |
| Directory | /workspace/84.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/84.xbar_error_random.4036900697 |
| Short name | T2842 |
| Test name | |
| Test status | |
| Simulation time | 2300547445 ps |
| CPU time | 82.7 seconds |
| Started | Aug 13 06:59:15 PM PDT 24 |
| Finished | Aug 13 07:00:37 PM PDT 24 |
| Peak memory | 575756 kb |
| Host | smart-2d8f6e57-c10b-46d2-a2ad-0ecdafadfc84 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4036900697 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 84.xbar_error_random.4036900697 |
| Directory | /workspace/84.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/84.xbar_random.3065293249 |
| Short name | T2922 |
| Test name | |
| Test status | |
| Simulation time | 421884061 ps |
| CPU time | 37.8 seconds |
| Started | Aug 13 06:59:29 PM PDT 24 |
| Finished | Aug 13 07:00:07 PM PDT 24 |
| Peak memory | 575592 kb |
| Host | smart-e79a8c2e-69ae-4231-baac-eb586e673887 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3065293249 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 84.xbar_random.3065293249 |
| Directory | /workspace/84.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/84.xbar_random_large_delays.1060858184 |
| Short name | T1705 |
| Test name | |
| Test status | |
| Simulation time | 43980942983 ps |
| CPU time | 471.83 seconds |
| Started | Aug 13 06:59:16 PM PDT 24 |
| Finished | Aug 13 07:07:08 PM PDT 24 |
| Peak memory | 575600 kb |
| Host | smart-9ff44c9a-c98d-4c6e-b342-dfb880882e39 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1060858184 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 84.xbar_random_large_delays.1060858184 |
| Directory | /workspace/84.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/84.xbar_random_slow_rsp.1328393001 |
| Short name | T1832 |
| Test name | |
| Test status | |
| Simulation time | 55497811429 ps |
| CPU time | 984.02 seconds |
| Started | Aug 13 06:59:15 PM PDT 24 |
| Finished | Aug 13 07:15:39 PM PDT 24 |
| Peak memory | 575780 kb |
| Host | smart-177ca819-eba2-4289-a506-bd0b4b25bbd6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1328393001 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 84.xbar_random_slow_rsp.1328393001 |
| Directory | /workspace/84.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/84.xbar_random_zero_delays.3940064510 |
| Short name | T2860 |
| Test name | |
| Test status | |
| Simulation time | 98134285 ps |
| CPU time | 11.28 seconds |
| Started | Aug 13 06:59:13 PM PDT 24 |
| Finished | Aug 13 06:59:25 PM PDT 24 |
| Peak memory | 575600 kb |
| Host | smart-66662ed5-9cce-42d1-943e-4cba51b2a26d |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3940064510 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 84.xbar_random_zero_del ays.3940064510 |
| Directory | /workspace/84.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/84.xbar_same_source.2525527519 |
| Short name | T1758 |
| Test name | |
| Test status | |
| Simulation time | 508916290 ps |
| CPU time | 38.6 seconds |
| Started | Aug 13 06:59:12 PM PDT 24 |
| Finished | Aug 13 06:59:51 PM PDT 24 |
| Peak memory | 575652 kb |
| Host | smart-e88f4e50-e709-4c9e-8611-e5bd88a3d81a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2525527519 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 84.xbar_same_source.2525527519 |
| Directory | /workspace/84.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/84.xbar_smoke.1865638491 |
| Short name | T1991 |
| Test name | |
| Test status | |
| Simulation time | 48388608 ps |
| CPU time | 6.51 seconds |
| Started | Aug 13 06:59:18 PM PDT 24 |
| Finished | Aug 13 06:59:25 PM PDT 24 |
| Peak memory | 574224 kb |
| Host | smart-46d1c3b1-3464-4275-be1a-32c4ee07bb55 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1865638491 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 84.xbar_smoke.1865638491 |
| Directory | /workspace/84.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/84.xbar_smoke_large_delays.405944397 |
| Short name | T1901 |
| Test name | |
| Test status | |
| Simulation time | 7688165064 ps |
| CPU time | 83.78 seconds |
| Started | Aug 13 06:59:14 PM PDT 24 |
| Finished | Aug 13 07:00:38 PM PDT 24 |
| Peak memory | 573560 kb |
| Host | smart-440d412e-cb4d-4c58-95d3-7bbfb6e7be0e |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=405944397 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 84.xbar_smoke_large_delays.405944397 |
| Directory | /workspace/84.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/84.xbar_smoke_slow_rsp.2463056622 |
| Short name | T2650 |
| Test name | |
| Test status | |
| Simulation time | 4546188814 ps |
| CPU time | 80.78 seconds |
| Started | Aug 13 06:59:13 PM PDT 24 |
| Finished | Aug 13 07:00:34 PM PDT 24 |
| Peak memory | 574340 kb |
| Host | smart-2278415d-c7e3-499e-86f8-a6beb73a54d6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2463056622 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 84.xbar_smoke_slow_rsp.2463056622 |
| Directory | /workspace/84.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/84.xbar_smoke_zero_delays.1038002521 |
| Short name | T1596 |
| Test name | |
| Test status | |
| Simulation time | 38847692 ps |
| CPU time | 5.47 seconds |
| Started | Aug 13 06:59:29 PM PDT 24 |
| Finished | Aug 13 06:59:35 PM PDT 24 |
| Peak memory | 573532 kb |
| Host | smart-63c87c8b-b8bf-4719-a4f8-0977f7e77a05 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1038002521 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 84.xbar_smoke_zero_delay s.1038002521 |
| Directory | /workspace/84.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/84.xbar_stress_all.571155223 |
| Short name | T592 |
| Test name | |
| Test status | |
| Simulation time | 1731524408 ps |
| CPU time | 142.15 seconds |
| Started | Aug 13 06:59:24 PM PDT 24 |
| Finished | Aug 13 07:01:47 PM PDT 24 |
| Peak memory | 575632 kb |
| Host | smart-99117af6-c37b-41d8-984b-a65529ef3d6a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=571155223 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 84.xbar_stress_all.571155223 |
| Directory | /workspace/84.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/84.xbar_stress_all_with_error.171197186 |
| Short name | T2144 |
| Test name | |
| Test status | |
| Simulation time | 4434686839 ps |
| CPU time | 152.48 seconds |
| Started | Aug 13 06:59:23 PM PDT 24 |
| Finished | Aug 13 07:01:56 PM PDT 24 |
| Peak memory | 576304 kb |
| Host | smart-d6ece0c4-7a51-44cc-ac8d-bbe5c29fcf76 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=171197186 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 84.xbar_stress_all_with_error.171197186 |
| Directory | /workspace/84.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/84.xbar_stress_all_with_rand_reset.1828597793 |
| Short name | T567 |
| Test name | |
| Test status | |
| Simulation time | 3877860719 ps |
| CPU time | 507.54 seconds |
| Started | Aug 13 06:59:25 PM PDT 24 |
| Finished | Aug 13 07:07:53 PM PDT 24 |
| Peak memory | 575708 kb |
| Host | smart-886f800a-d821-40b4-b061-07b202616bf3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1828597793 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 84.xbar_stress_all _with_rand_reset.1828597793 |
| Directory | /workspace/84.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/84.xbar_stress_all_with_reset_error.2692046147 |
| Short name | T1504 |
| Test name | |
| Test status | |
| Simulation time | 4321643469 ps |
| CPU time | 161.81 seconds |
| Started | Aug 13 06:59:21 PM PDT 24 |
| Finished | Aug 13 07:02:03 PM PDT 24 |
| Peak memory | 575928 kb |
| Host | smart-2faa9896-35b3-41ee-b548-085264f3b91a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2692046147 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 84.xbar_stress_al l_with_reset_error.2692046147 |
| Directory | /workspace/84.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/84.xbar_unmapped_addr.211066064 |
| Short name | T1697 |
| Test name | |
| Test status | |
| Simulation time | 242803127 ps |
| CPU time | 12.51 seconds |
| Started | Aug 13 06:59:24 PM PDT 24 |
| Finished | Aug 13 06:59:37 PM PDT 24 |
| Peak memory | 575652 kb |
| Host | smart-985e7a4e-8e6b-4c3a-bad6-2f2278244ba9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=211066064 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 84.xbar_unmapped_addr.211066064 |
| Directory | /workspace/84.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/85.xbar_access_same_device.2929350480 |
| Short name | T2601 |
| Test name | |
| Test status | |
| Simulation time | 1691781748 ps |
| CPU time | 68.23 seconds |
| Started | Aug 13 06:59:22 PM PDT 24 |
| Finished | Aug 13 07:00:30 PM PDT 24 |
| Peak memory | 576412 kb |
| Host | smart-a7df801b-c7d4-4609-bf60-bf6614f3e650 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2929350480 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 85.xbar_access_same_device .2929350480 |
| Directory | /workspace/85.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/85.xbar_access_same_device_slow_rsp.67952953 |
| Short name | T1907 |
| Test name | |
| Test status | |
| Simulation time | 56863741688 ps |
| CPU time | 1027.94 seconds |
| Started | Aug 13 06:59:21 PM PDT 24 |
| Finished | Aug 13 07:16:30 PM PDT 24 |
| Peak memory | 575632 kb |
| Host | smart-71fcad64-df8e-42ee-b715-196657bab316 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=67952953 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 85.xbar_access_same_de vice_slow_rsp.67952953 |
| Directory | /workspace/85.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/85.xbar_error_and_unmapped_addr.2927828639 |
| Short name | T2476 |
| Test name | |
| Test status | |
| Simulation time | 443604775 ps |
| CPU time | 19.89 seconds |
| Started | Aug 13 06:59:23 PM PDT 24 |
| Finished | Aug 13 06:59:43 PM PDT 24 |
| Peak memory | 575708 kb |
| Host | smart-79bb4368-010b-4eca-9cb3-2d6c0cf18289 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2927828639 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 85.xbar_error_and_unmapped_add r.2927828639 |
| Directory | /workspace/85.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/85.xbar_error_random.1651714140 |
| Short name | T2228 |
| Test name | |
| Test status | |
| Simulation time | 2060500568 ps |
| CPU time | 67.39 seconds |
| Started | Aug 13 06:59:24 PM PDT 24 |
| Finished | Aug 13 07:00:31 PM PDT 24 |
| Peak memory | 575684 kb |
| Host | smart-8d93ff74-ea85-4550-a56c-bf08f9f62fb5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1651714140 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 85.xbar_error_random.1651714140 |
| Directory | /workspace/85.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/85.xbar_random.347752931 |
| Short name | T628 |
| Test name | |
| Test status | |
| Simulation time | 1666105529 ps |
| CPU time | 54.86 seconds |
| Started | Aug 13 06:59:24 PM PDT 24 |
| Finished | Aug 13 07:00:19 PM PDT 24 |
| Peak memory | 575496 kb |
| Host | smart-c66ed35d-0eb5-4637-bb2c-55a271862b8a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=347752931 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 85.xbar_random.347752931 |
| Directory | /workspace/85.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/85.xbar_random_large_delays.3799120819 |
| Short name | T1838 |
| Test name | |
| Test status | |
| Simulation time | 98365990947 ps |
| CPU time | 1128.62 seconds |
| Started | Aug 13 06:59:21 PM PDT 24 |
| Finished | Aug 13 07:18:10 PM PDT 24 |
| Peak memory | 575608 kb |
| Host | smart-47de9631-8230-459d-9872-45c7d864ae67 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3799120819 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 85.xbar_random_large_delays.3799120819 |
| Directory | /workspace/85.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/85.xbar_random_slow_rsp.3979531870 |
| Short name | T2111 |
| Test name | |
| Test status | |
| Simulation time | 5913979697 ps |
| CPU time | 99.37 seconds |
| Started | Aug 13 06:59:25 PM PDT 24 |
| Finished | Aug 13 07:01:04 PM PDT 24 |
| Peak memory | 575704 kb |
| Host | smart-379e1d90-0232-4663-a53a-09550756830e |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3979531870 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 85.xbar_random_slow_rsp.3979531870 |
| Directory | /workspace/85.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/85.xbar_random_zero_delays.1539651126 |
| Short name | T444 |
| Test name | |
| Test status | |
| Simulation time | 381638450 ps |
| CPU time | 35.6 seconds |
| Started | Aug 13 06:59:22 PM PDT 24 |
| Finished | Aug 13 06:59:58 PM PDT 24 |
| Peak memory | 575632 kb |
| Host | smart-2e1eb7c8-bbf5-46ec-a54f-f24fa619089d |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1539651126 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 85.xbar_random_zero_del ays.1539651126 |
| Directory | /workspace/85.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/85.xbar_same_source.3796195265 |
| Short name | T2921 |
| Test name | |
| Test status | |
| Simulation time | 487114373 ps |
| CPU time | 34.09 seconds |
| Started | Aug 13 06:59:22 PM PDT 24 |
| Finished | Aug 13 06:59:56 PM PDT 24 |
| Peak memory | 575512 kb |
| Host | smart-96d67004-d93b-4720-b0a9-bdbf7a0fe3f8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3796195265 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 85.xbar_same_source.3796195265 |
| Directory | /workspace/85.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/85.xbar_smoke.2766040269 |
| Short name | T2291 |
| Test name | |
| Test status | |
| Simulation time | 51935831 ps |
| CPU time | 6.77 seconds |
| Started | Aug 13 06:59:22 PM PDT 24 |
| Finished | Aug 13 06:59:29 PM PDT 24 |
| Peak memory | 573544 kb |
| Host | smart-e3a89fd9-11bd-4a6f-ab3d-3b1a00410f90 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2766040269 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 85.xbar_smoke.2766040269 |
| Directory | /workspace/85.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/85.xbar_smoke_large_delays.1910203452 |
| Short name | T2872 |
| Test name | |
| Test status | |
| Simulation time | 10136811371 ps |
| CPU time | 110.06 seconds |
| Started | Aug 13 06:59:22 PM PDT 24 |
| Finished | Aug 13 07:01:12 PM PDT 24 |
| Peak memory | 573632 kb |
| Host | smart-2755c09c-f8a9-4c32-96f3-26df3925b8ab |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1910203452 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 85.xbar_smoke_large_delays.1910203452 |
| Directory | /workspace/85.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/85.xbar_smoke_slow_rsp.881144359 |
| Short name | T1787 |
| Test name | |
| Test status | |
| Simulation time | 4261656020 ps |
| CPU time | 74.68 seconds |
| Started | Aug 13 06:59:20 PM PDT 24 |
| Finished | Aug 13 07:00:35 PM PDT 24 |
| Peak memory | 573624 kb |
| Host | smart-0baccf21-95db-46d9-a9a6-12200949c414 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=881144359 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 85.xbar_smoke_slow_rsp.881144359 |
| Directory | /workspace/85.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/85.xbar_smoke_zero_delays.4266035210 |
| Short name | T2910 |
| Test name | |
| Test status | |
| Simulation time | 36102536 ps |
| CPU time | 5.75 seconds |
| Started | Aug 13 06:59:25 PM PDT 24 |
| Finished | Aug 13 06:59:30 PM PDT 24 |
| Peak memory | 573592 kb |
| Host | smart-9eb11ab8-c0da-4e24-97d3-8ca0879b9b2a |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4266035210 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 85.xbar_smoke_zero_delay s.4266035210 |
| Directory | /workspace/85.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/85.xbar_stress_all.3614787576 |
| Short name | T2230 |
| Test name | |
| Test status | |
| Simulation time | 2706455796 ps |
| CPU time | 266.69 seconds |
| Started | Aug 13 06:59:21 PM PDT 24 |
| Finished | Aug 13 07:03:48 PM PDT 24 |
| Peak memory | 575724 kb |
| Host | smart-4f907c21-dde7-40c9-a961-063fd5111e08 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3614787576 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 85.xbar_stress_all.3614787576 |
| Directory | /workspace/85.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/85.xbar_stress_all_with_error.3263793830 |
| Short name | T742 |
| Test name | |
| Test status | |
| Simulation time | 1720408946 ps |
| CPU time | 118.33 seconds |
| Started | Aug 13 06:59:20 PM PDT 24 |
| Finished | Aug 13 07:01:19 PM PDT 24 |
| Peak memory | 576392 kb |
| Host | smart-95c959de-9ae0-4393-a438-08be28ec1bc1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3263793830 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 85.xbar_stress_all_with_error.3263793830 |
| Directory | /workspace/85.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/85.xbar_stress_all_with_rand_reset.821838404 |
| Short name | T2188 |
| Test name | |
| Test status | |
| Simulation time | 777314670 ps |
| CPU time | 214.16 seconds |
| Started | Aug 13 06:59:30 PM PDT 24 |
| Finished | Aug 13 07:03:05 PM PDT 24 |
| Peak memory | 575604 kb |
| Host | smart-4efe7d97-1eb3-40e6-8196-a94f8042f62e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=821838404 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_res et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 85.xbar_stress_all_ with_rand_reset.821838404 |
| Directory | /workspace/85.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/85.xbar_stress_all_with_reset_error.3610078109 |
| Short name | T2326 |
| Test name | |
| Test status | |
| Simulation time | 280756887 ps |
| CPU time | 47.53 seconds |
| Started | Aug 13 06:59:29 PM PDT 24 |
| Finished | Aug 13 07:00:16 PM PDT 24 |
| Peak memory | 576212 kb |
| Host | smart-a91c90ae-7aa8-4520-9201-a267c7041f27 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3610078109 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 85.xbar_stress_al l_with_reset_error.3610078109 |
| Directory | /workspace/85.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/85.xbar_unmapped_addr.958753833 |
| Short name | T2497 |
| Test name | |
| Test status | |
| Simulation time | 76785387 ps |
| CPU time | 10.61 seconds |
| Started | Aug 13 06:59:25 PM PDT 24 |
| Finished | Aug 13 06:59:36 PM PDT 24 |
| Peak memory | 575736 kb |
| Host | smart-7e9024b2-259a-4583-bdb4-33fe300f9cbd |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=958753833 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 85.xbar_unmapped_addr.958753833 |
| Directory | /workspace/85.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/86.xbar_access_same_device.2201786717 |
| Short name | T868 |
| Test name | |
| Test status | |
| Simulation time | 2430109671 ps |
| CPU time | 100.12 seconds |
| Started | Aug 13 06:59:29 PM PDT 24 |
| Finished | Aug 13 07:01:10 PM PDT 24 |
| Peak memory | 575760 kb |
| Host | smart-471b7e0d-0613-42b6-a292-9e42fa5f55ac |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2201786717 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 86.xbar_access_same_device .2201786717 |
| Directory | /workspace/86.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/86.xbar_access_same_device_slow_rsp.3414524906 |
| Short name | T891 |
| Test name | |
| Test status | |
| Simulation time | 36462727274 ps |
| CPU time | 638.78 seconds |
| Started | Aug 13 06:59:31 PM PDT 24 |
| Finished | Aug 13 07:10:10 PM PDT 24 |
| Peak memory | 575796 kb |
| Host | smart-171b4a0a-6eda-47f0-ac49-25791eb736fd |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3414524906 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 86.xbar_access_same_ device_slow_rsp.3414524906 |
| Directory | /workspace/86.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/86.xbar_error_and_unmapped_addr.1912439782 |
| Short name | T1738 |
| Test name | |
| Test status | |
| Simulation time | 73698540 ps |
| CPU time | 9.44 seconds |
| Started | Aug 13 06:59:37 PM PDT 24 |
| Finished | Aug 13 06:59:46 PM PDT 24 |
| Peak memory | 575700 kb |
| Host | smart-40511fdb-3feb-431f-97c5-7cb5cfc2d676 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1912439782 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 86.xbar_error_and_unmapped_add r.1912439782 |
| Directory | /workspace/86.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/86.xbar_error_random.2204902346 |
| Short name | T2427 |
| Test name | |
| Test status | |
| Simulation time | 1833791773 ps |
| CPU time | 57.33 seconds |
| Started | Aug 13 06:59:47 PM PDT 24 |
| Finished | Aug 13 07:00:44 PM PDT 24 |
| Peak memory | 575672 kb |
| Host | smart-9dc31d9f-b419-49a7-bdaa-1a2cf0fcb6f2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2204902346 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 86.xbar_error_random.2204902346 |
| Directory | /workspace/86.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/86.xbar_random.3203456403 |
| Short name | T2663 |
| Test name | |
| Test status | |
| Simulation time | 247908152 ps |
| CPU time | 21.06 seconds |
| Started | Aug 13 06:59:29 PM PDT 24 |
| Finished | Aug 13 06:59:50 PM PDT 24 |
| Peak memory | 575720 kb |
| Host | smart-2b21a1f4-7135-414e-b1e8-93cfe4f020b3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3203456403 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 86.xbar_random.3203456403 |
| Directory | /workspace/86.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/86.xbar_random_large_delays.3149292232 |
| Short name | T2371 |
| Test name | |
| Test status | |
| Simulation time | 81703091617 ps |
| CPU time | 905.11 seconds |
| Started | Aug 13 06:59:31 PM PDT 24 |
| Finished | Aug 13 07:14:36 PM PDT 24 |
| Peak memory | 575812 kb |
| Host | smart-042eda14-2123-464b-abea-bd3f4dc0f997 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3149292232 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 86.xbar_random_large_delays.3149292232 |
| Directory | /workspace/86.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/86.xbar_random_slow_rsp.1624516383 |
| Short name | T582 |
| Test name | |
| Test status | |
| Simulation time | 31720766767 ps |
| CPU time | 500.26 seconds |
| Started | Aug 13 06:59:35 PM PDT 24 |
| Finished | Aug 13 07:07:56 PM PDT 24 |
| Peak memory | 575772 kb |
| Host | smart-e60fe6ab-c829-455f-bd27-cee770687d8f |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1624516383 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 86.xbar_random_slow_rsp.1624516383 |
| Directory | /workspace/86.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/86.xbar_random_zero_delays.1339704328 |
| Short name | T644 |
| Test name | |
| Test status | |
| Simulation time | 526119904 ps |
| CPU time | 45.94 seconds |
| Started | Aug 13 06:59:29 PM PDT 24 |
| Finished | Aug 13 07:00:15 PM PDT 24 |
| Peak memory | 575672 kb |
| Host | smart-4b039ca2-9c72-48c3-8b0e-2a780a020f76 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1339704328 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 86.xbar_random_zero_del ays.1339704328 |
| Directory | /workspace/86.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/86.xbar_same_source.628751911 |
| Short name | T1673 |
| Test name | |
| Test status | |
| Simulation time | 507297318 ps |
| CPU time | 16.02 seconds |
| Started | Aug 13 06:59:36 PM PDT 24 |
| Finished | Aug 13 06:59:52 PM PDT 24 |
| Peak memory | 575636 kb |
| Host | smart-89dadd38-4bc0-4f35-8428-7cb4f6e73c68 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=628751911 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 86.xbar_same_source.628751911 |
| Directory | /workspace/86.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/86.xbar_smoke.3390774280 |
| Short name | T2869 |
| Test name | |
| Test status | |
| Simulation time | 258227955 ps |
| CPU time | 11.43 seconds |
| Started | Aug 13 06:59:30 PM PDT 24 |
| Finished | Aug 13 06:59:41 PM PDT 24 |
| Peak memory | 573608 kb |
| Host | smart-3c635793-9ff4-4e39-93a8-9e52a423c880 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3390774280 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 86.xbar_smoke.3390774280 |
| Directory | /workspace/86.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/86.xbar_smoke_large_delays.1220960872 |
| Short name | T2254 |
| Test name | |
| Test status | |
| Simulation time | 9395490331 ps |
| CPU time | 102.42 seconds |
| Started | Aug 13 06:59:29 PM PDT 24 |
| Finished | Aug 13 07:01:11 PM PDT 24 |
| Peak memory | 573688 kb |
| Host | smart-cbb62f6a-160b-41da-89f8-82522c9db6e9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1220960872 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 86.xbar_smoke_large_delays.1220960872 |
| Directory | /workspace/86.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/86.xbar_smoke_slow_rsp.4198466216 |
| Short name | T2903 |
| Test name | |
| Test status | |
| Simulation time | 5013401477 ps |
| CPU time | 82.55 seconds |
| Started | Aug 13 06:59:29 PM PDT 24 |
| Finished | Aug 13 07:00:52 PM PDT 24 |
| Peak memory | 574304 kb |
| Host | smart-b00bd3d4-551b-44fd-a984-7d4364bec23b |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4198466216 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 86.xbar_smoke_slow_rsp.4198466216 |
| Directory | /workspace/86.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/86.xbar_smoke_zero_delays.761445481 |
| Short name | T2274 |
| Test name | |
| Test status | |
| Simulation time | 47149946 ps |
| CPU time | 6.45 seconds |
| Started | Aug 13 06:59:30 PM PDT 24 |
| Finished | Aug 13 06:59:36 PM PDT 24 |
| Peak memory | 574244 kb |
| Host | smart-09fd83c0-b5ac-483f-9b84-ab008f2232f7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=761445481 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 86.xbar_smoke_zero_delays .761445481 |
| Directory | /workspace/86.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/86.xbar_stress_all.2446003431 |
| Short name | T2897 |
| Test name | |
| Test status | |
| Simulation time | 4357736183 ps |
| CPU time | 161.54 seconds |
| Started | Aug 13 06:59:36 PM PDT 24 |
| Finished | Aug 13 07:02:17 PM PDT 24 |
| Peak memory | 575620 kb |
| Host | smart-4a5c4798-261b-4532-9ce0-f657fd470ef6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2446003431 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 86.xbar_stress_all.2446003431 |
| Directory | /workspace/86.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/86.xbar_stress_all_with_reset_error.1695709181 |
| Short name | T2061 |
| Test name | |
| Test status | |
| Simulation time | 13761513266 ps |
| CPU time | 821.5 seconds |
| Started | Aug 13 06:59:40 PM PDT 24 |
| Finished | Aug 13 07:13:22 PM PDT 24 |
| Peak memory | 582660 kb |
| Host | smart-c04ccc1e-5aa0-435b-baa3-a6b8e505bca8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1695709181 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 86.xbar_stress_al l_with_reset_error.1695709181 |
| Directory | /workspace/86.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/86.xbar_unmapped_addr.1553117136 |
| Short name | T2763 |
| Test name | |
| Test status | |
| Simulation time | 323542554 ps |
| CPU time | 37.65 seconds |
| Started | Aug 13 06:59:40 PM PDT 24 |
| Finished | Aug 13 07:00:18 PM PDT 24 |
| Peak memory | 575744 kb |
| Host | smart-d942a76b-2be6-4e4e-aef8-7b9c3249130a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1553117136 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 86.xbar_unmapped_addr.1553117136 |
| Directory | /workspace/86.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/87.xbar_access_same_device.119286457 |
| Short name | T1894 |
| Test name | |
| Test status | |
| Simulation time | 426186690 ps |
| CPU time | 37.65 seconds |
| Started | Aug 13 06:59:40 PM PDT 24 |
| Finished | Aug 13 07:00:18 PM PDT 24 |
| Peak memory | 576432 kb |
| Host | smart-7e957473-8112-4987-b5ec-614aa502708a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=119286457 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 87.xbar_access_same_device. 119286457 |
| Directory | /workspace/87.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/87.xbar_access_same_device_slow_rsp.671025250 |
| Short name | T2516 |
| Test name | |
| Test status | |
| Simulation time | 122935419210 ps |
| CPU time | 2201.54 seconds |
| Started | Aug 13 06:59:36 PM PDT 24 |
| Finished | Aug 13 07:36:18 PM PDT 24 |
| Peak memory | 575868 kb |
| Host | smart-b851a136-e61b-411d-b431-1352d147d87c |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=671025250 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 87.xbar_access_same_d evice_slow_rsp.671025250 |
| Directory | /workspace/87.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/87.xbar_error_and_unmapped_addr.2454416155 |
| Short name | T1491 |
| Test name | |
| Test status | |
| Simulation time | 727362502 ps |
| CPU time | 29.73 seconds |
| Started | Aug 13 06:59:43 PM PDT 24 |
| Finished | Aug 13 07:00:13 PM PDT 24 |
| Peak memory | 575736 kb |
| Host | smart-b29f98d8-7c04-4cd8-974d-46704b665379 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2454416155 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 87.xbar_error_and_unmapped_add r.2454416155 |
| Directory | /workspace/87.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/87.xbar_error_random.3023038338 |
| Short name | T1558 |
| Test name | |
| Test status | |
| Simulation time | 137714057 ps |
| CPU time | 7.79 seconds |
| Started | Aug 13 06:59:42 PM PDT 24 |
| Finished | Aug 13 06:59:50 PM PDT 24 |
| Peak memory | 573664 kb |
| Host | smart-e4529a1e-e7d0-4c2b-9213-cf0352cde079 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3023038338 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 87.xbar_error_random.3023038338 |
| Directory | /workspace/87.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/87.xbar_random.941799216 |
| Short name | T2683 |
| Test name | |
| Test status | |
| Simulation time | 536108591 ps |
| CPU time | 46.51 seconds |
| Started | Aug 13 06:59:37 PM PDT 24 |
| Finished | Aug 13 07:00:24 PM PDT 24 |
| Peak memory | 575540 kb |
| Host | smart-356b03a7-499c-4508-803d-e1a5bd46ba79 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=941799216 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 87.xbar_random.941799216 |
| Directory | /workspace/87.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/87.xbar_random_large_delays.106674330 |
| Short name | T1839 |
| Test name | |
| Test status | |
| Simulation time | 5567846390 ps |
| CPU time | 59.38 seconds |
| Started | Aug 13 06:59:47 PM PDT 24 |
| Finished | Aug 13 07:00:47 PM PDT 24 |
| Peak memory | 573648 kb |
| Host | smart-db88dd3d-44e7-4368-a973-0df9b508daee |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=106674330 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 87.xbar_random_large_delays.106674330 |
| Directory | /workspace/87.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/87.xbar_random_slow_rsp.2575860774 |
| Short name | T2560 |
| Test name | |
| Test status | |
| Simulation time | 44364737132 ps |
| CPU time | 786.94 seconds |
| Started | Aug 13 06:59:40 PM PDT 24 |
| Finished | Aug 13 07:12:47 PM PDT 24 |
| Peak memory | 575620 kb |
| Host | smart-50509566-78e3-4aa9-af1c-cad3821f116c |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2575860774 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 87.xbar_random_slow_rsp.2575860774 |
| Directory | /workspace/87.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/87.xbar_random_zero_delays.1267759141 |
| Short name | T2382 |
| Test name | |
| Test status | |
| Simulation time | 424435150 ps |
| CPU time | 36.38 seconds |
| Started | Aug 13 06:59:37 PM PDT 24 |
| Finished | Aug 13 07:00:13 PM PDT 24 |
| Peak memory | 575512 kb |
| Host | smart-73fbf4b6-ca96-4d47-8f95-74a6ce33af20 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1267759141 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 87.xbar_random_zero_del ays.1267759141 |
| Directory | /workspace/87.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/87.xbar_same_source.87237613 |
| Short name | T573 |
| Test name | |
| Test status | |
| Simulation time | 329056500 ps |
| CPU time | 25.72 seconds |
| Started | Aug 13 06:59:36 PM PDT 24 |
| Finished | Aug 13 07:00:02 PM PDT 24 |
| Peak memory | 575572 kb |
| Host | smart-cf07ba60-f5c7-4781-8fcc-b3841dd31113 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87237613 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 87.xbar_same_source.87237613 |
| Directory | /workspace/87.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/87.xbar_smoke.273533637 |
| Short name | T2255 |
| Test name | |
| Test status | |
| Simulation time | 249526545 ps |
| CPU time | 9.62 seconds |
| Started | Aug 13 06:59:39 PM PDT 24 |
| Finished | Aug 13 06:59:49 PM PDT 24 |
| Peak memory | 573600 kb |
| Host | smart-02681c21-f243-4ddd-865d-92d56d936475 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=273533637 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 87.xbar_smoke.273533637 |
| Directory | /workspace/87.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/87.xbar_smoke_large_delays.2084940347 |
| Short name | T2359 |
| Test name | |
| Test status | |
| Simulation time | 10105126056 ps |
| CPU time | 103.17 seconds |
| Started | Aug 13 06:59:36 PM PDT 24 |
| Finished | Aug 13 07:01:20 PM PDT 24 |
| Peak memory | 574332 kb |
| Host | smart-16377cf3-e5bc-4117-9f0e-b1e054cb16d5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2084940347 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 87.xbar_smoke_large_delays.2084940347 |
| Directory | /workspace/87.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/87.xbar_smoke_slow_rsp.2204699116 |
| Short name | T2313 |
| Test name | |
| Test status | |
| Simulation time | 6686138776 ps |
| CPU time | 110.97 seconds |
| Started | Aug 13 06:59:37 PM PDT 24 |
| Finished | Aug 13 07:01:28 PM PDT 24 |
| Peak memory | 574272 kb |
| Host | smart-5be94942-a7c5-4e67-9249-f39013b7062e |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2204699116 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 87.xbar_smoke_slow_rsp.2204699116 |
| Directory | /workspace/87.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/87.xbar_smoke_zero_delays.3205549543 |
| Short name | T2437 |
| Test name | |
| Test status | |
| Simulation time | 40225611 ps |
| CPU time | 5.96 seconds |
| Started | Aug 13 06:59:37 PM PDT 24 |
| Finished | Aug 13 06:59:43 PM PDT 24 |
| Peak memory | 574180 kb |
| Host | smart-fa879bcb-f1d7-4e8b-afe6-f3d929e326da |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3205549543 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 87.xbar_smoke_zero_delay s.3205549543 |
| Directory | /workspace/87.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/87.xbar_stress_all.4114694454 |
| Short name | T656 |
| Test name | |
| Test status | |
| Simulation time | 2184928690 ps |
| CPU time | 180.45 seconds |
| Started | Aug 13 06:59:44 PM PDT 24 |
| Finished | Aug 13 07:02:45 PM PDT 24 |
| Peak memory | 576492 kb |
| Host | smart-05faa95a-3889-4f1e-a25c-e5fc43902600 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4114694454 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 87.xbar_stress_all.4114694454 |
| Directory | /workspace/87.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/87.xbar_stress_all_with_error.3685755985 |
| Short name | T2908 |
| Test name | |
| Test status | |
| Simulation time | 14609356643 ps |
| CPU time | 572.88 seconds |
| Started | Aug 13 06:59:44 PM PDT 24 |
| Finished | Aug 13 07:09:17 PM PDT 24 |
| Peak memory | 576524 kb |
| Host | smart-8a7e920d-d57f-417b-8dd5-c609d4eddcb6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3685755985 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 87.xbar_stress_all_with_error.3685755985 |
| Directory | /workspace/87.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/87.xbar_stress_all_with_rand_reset.4230254131 |
| Short name | T1746 |
| Test name | |
| Test status | |
| Simulation time | 191195528 ps |
| CPU time | 45.92 seconds |
| Started | Aug 13 06:59:47 PM PDT 24 |
| Finished | Aug 13 07:00:33 PM PDT 24 |
| Peak memory | 576468 kb |
| Host | smart-6c0ec60b-8987-4c52-9f75-efc941e6d62c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4230254131 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 87.xbar_stress_all _with_rand_reset.4230254131 |
| Directory | /workspace/87.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/87.xbar_stress_all_with_reset_error.763987709 |
| Short name | T1975 |
| Test name | |
| Test status | |
| Simulation time | 3345717904 ps |
| CPU time | 419.07 seconds |
| Started | Aug 13 06:59:44 PM PDT 24 |
| Finished | Aug 13 07:06:44 PM PDT 24 |
| Peak memory | 576500 kb |
| Host | smart-d2b29405-c82e-42da-a857-c29ae16c31d9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=763987709 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 87.xbar_stress_all _with_reset_error.763987709 |
| Directory | /workspace/87.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/87.xbar_unmapped_addr.3777220668 |
| Short name | T2649 |
| Test name | |
| Test status | |
| Simulation time | 815728018 ps |
| CPU time | 36.59 seconds |
| Started | Aug 13 06:59:43 PM PDT 24 |
| Finished | Aug 13 07:00:20 PM PDT 24 |
| Peak memory | 575752 kb |
| Host | smart-28dc69cd-481f-4ba6-84b1-0741b952c82d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3777220668 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 87.xbar_unmapped_addr.3777220668 |
| Directory | /workspace/87.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/88.xbar_access_same_device.1477201217 |
| Short name | T1845 |
| Test name | |
| Test status | |
| Simulation time | 929451017 ps |
| CPU time | 42.38 seconds |
| Started | Aug 13 06:59:47 PM PDT 24 |
| Finished | Aug 13 07:00:30 PM PDT 24 |
| Peak memory | 575524 kb |
| Host | smart-df74be74-3365-45d5-8b77-dd854837c69e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1477201217 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 88.xbar_access_same_device .1477201217 |
| Directory | /workspace/88.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/88.xbar_access_same_device_slow_rsp.1904900170 |
| Short name | T2772 |
| Test name | |
| Test status | |
| Simulation time | 23383890579 ps |
| CPU time | 397.18 seconds |
| Started | Aug 13 06:59:46 PM PDT 24 |
| Finished | Aug 13 07:06:23 PM PDT 24 |
| Peak memory | 575808 kb |
| Host | smart-3475798b-41c1-4db6-9c11-12a40cb43a4a |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1904900170 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 88.xbar_access_same_ device_slow_rsp.1904900170 |
| Directory | /workspace/88.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/88.xbar_error_random.1044570051 |
| Short name | T2625 |
| Test name | |
| Test status | |
| Simulation time | 147874553 ps |
| CPU time | 9.13 seconds |
| Started | Aug 13 06:59:55 PM PDT 24 |
| Finished | Aug 13 07:00:05 PM PDT 24 |
| Peak memory | 574140 kb |
| Host | smart-8f9a996f-81b6-486e-b55f-1ff85a0f3145 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1044570051 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 88.xbar_error_random.1044570051 |
| Directory | /workspace/88.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/88.xbar_random.1589762383 |
| Short name | T2324 |
| Test name | |
| Test status | |
| Simulation time | 505883223 ps |
| CPU time | 42.28 seconds |
| Started | Aug 13 06:59:47 PM PDT 24 |
| Finished | Aug 13 07:00:29 PM PDT 24 |
| Peak memory | 575612 kb |
| Host | smart-98990d3e-849c-4d06-9d6b-85b399d37824 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1589762383 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 88.xbar_random.1589762383 |
| Directory | /workspace/88.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/88.xbar_random_large_delays.1554965270 |
| Short name | T2938 |
| Test name | |
| Test status | |
| Simulation time | 31211111124 ps |
| CPU time | 319.55 seconds |
| Started | Aug 13 06:59:45 PM PDT 24 |
| Finished | Aug 13 07:05:05 PM PDT 24 |
| Peak memory | 575564 kb |
| Host | smart-8fe62e84-7bd4-4a47-bc2c-45c0da082ba6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1554965270 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 88.xbar_random_large_delays.1554965270 |
| Directory | /workspace/88.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/88.xbar_random_slow_rsp.3876055883 |
| Short name | T509 |
| Test name | |
| Test status | |
| Simulation time | 43350075331 ps |
| CPU time | 806.16 seconds |
| Started | Aug 13 06:59:44 PM PDT 24 |
| Finished | Aug 13 07:13:10 PM PDT 24 |
| Peak memory | 575592 kb |
| Host | smart-ba74a1bb-57dd-45d7-8ff2-b46e00569ce4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3876055883 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 88.xbar_random_slow_rsp.3876055883 |
| Directory | /workspace/88.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/88.xbar_random_zero_delays.891798087 |
| Short name | T2015 |
| Test name | |
| Test status | |
| Simulation time | 502814069 ps |
| CPU time | 42.69 seconds |
| Started | Aug 13 06:59:50 PM PDT 24 |
| Finished | Aug 13 07:00:33 PM PDT 24 |
| Peak memory | 575592 kb |
| Host | smart-6eb27dee-be8f-430a-a42b-a847c71510db |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=891798087 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 88.xbar_random_zero_dela ys.891798087 |
| Directory | /workspace/88.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/88.xbar_same_source.1947043537 |
| Short name | T615 |
| Test name | |
| Test status | |
| Simulation time | 1105752549 ps |
| CPU time | 30.02 seconds |
| Started | Aug 13 06:59:44 PM PDT 24 |
| Finished | Aug 13 07:00:14 PM PDT 24 |
| Peak memory | 575672 kb |
| Host | smart-91cf69fc-49d2-44ed-8494-3d304ef01e52 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1947043537 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 88.xbar_same_source.1947043537 |
| Directory | /workspace/88.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/88.xbar_smoke.1043819900 |
| Short name | T693 |
| Test name | |
| Test status | |
| Simulation time | 206524659 ps |
| CPU time | 9.22 seconds |
| Started | Aug 13 06:59:49 PM PDT 24 |
| Finished | Aug 13 06:59:58 PM PDT 24 |
| Peak memory | 573484 kb |
| Host | smart-297ddcc9-65a9-427d-bd2f-baf8d76a46c3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1043819900 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 88.xbar_smoke.1043819900 |
| Directory | /workspace/88.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/88.xbar_smoke_large_delays.568895933 |
| Short name | T1818 |
| Test name | |
| Test status | |
| Simulation time | 8199994321 ps |
| CPU time | 83.95 seconds |
| Started | Aug 13 06:59:48 PM PDT 24 |
| Finished | Aug 13 07:01:12 PM PDT 24 |
| Peak memory | 573680 kb |
| Host | smart-9eb69c9f-00f8-4ef8-b0f9-33977fc8b619 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=568895933 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 88.xbar_smoke_large_delays.568895933 |
| Directory | /workspace/88.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/88.xbar_smoke_slow_rsp.526143393 |
| Short name | T2037 |
| Test name | |
| Test status | |
| Simulation time | 7209268529 ps |
| CPU time | 128.25 seconds |
| Started | Aug 13 06:59:45 PM PDT 24 |
| Finished | Aug 13 07:01:53 PM PDT 24 |
| Peak memory | 573680 kb |
| Host | smart-6ff91bff-3c56-4c06-9fa8-6e2469d08b51 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=526143393 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 88.xbar_smoke_slow_rsp.526143393 |
| Directory | /workspace/88.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/88.xbar_smoke_zero_delays.4093077550 |
| Short name | T2463 |
| Test name | |
| Test status | |
| Simulation time | 40245337 ps |
| CPU time | 6.5 seconds |
| Started | Aug 13 06:59:46 PM PDT 24 |
| Finished | Aug 13 06:59:53 PM PDT 24 |
| Peak memory | 573536 kb |
| Host | smart-c7ab7616-fe83-45b7-a64a-dd54b8e4e14b |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4093077550 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 88.xbar_smoke_zero_delay s.4093077550 |
| Directory | /workspace/88.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/88.xbar_stress_all.2384181972 |
| Short name | T581 |
| Test name | |
| Test status | |
| Simulation time | 9135725604 ps |
| CPU time | 345.71 seconds |
| Started | Aug 13 06:59:57 PM PDT 24 |
| Finished | Aug 13 07:05:43 PM PDT 24 |
| Peak memory | 576560 kb |
| Host | smart-470c8c47-15f6-4b8e-916f-360f15ba91c0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2384181972 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 88.xbar_stress_all.2384181972 |
| Directory | /workspace/88.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/88.xbar_stress_all_with_error.53965763 |
| Short name | T2862 |
| Test name | |
| Test status | |
| Simulation time | 794750497 ps |
| CPU time | 58.1 seconds |
| Started | Aug 13 06:59:57 PM PDT 24 |
| Finished | Aug 13 07:00:55 PM PDT 24 |
| Peak memory | 575724 kb |
| Host | smart-faff75b2-2da6-41c1-b3c3-8651b9fcd71a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=53965763 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 88.xbar_stress_all_with_error.53965763 |
| Directory | /workspace/88.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/88.xbar_stress_all_with_reset_error.494632069 |
| Short name | T1670 |
| Test name | |
| Test status | |
| Simulation time | 7190384387 ps |
| CPU time | 300.88 seconds |
| Started | Aug 13 06:59:54 PM PDT 24 |
| Finished | Aug 13 07:04:55 PM PDT 24 |
| Peak memory | 576480 kb |
| Host | smart-b34a4473-d882-4d5e-a079-a9c51b3781d3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=494632069 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 88.xbar_stress_all _with_reset_error.494632069 |
| Directory | /workspace/88.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/88.xbar_unmapped_addr.1026789843 |
| Short name | T439 |
| Test name | |
| Test status | |
| Simulation time | 120624903 ps |
| CPU time | 14.54 seconds |
| Started | Aug 13 06:59:57 PM PDT 24 |
| Finished | Aug 13 07:00:11 PM PDT 24 |
| Peak memory | 575688 kb |
| Host | smart-f10998b8-7b4d-4900-88fc-2040fd68e308 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1026789843 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 88.xbar_unmapped_addr.1026789843 |
| Directory | /workspace/88.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/89.xbar_access_same_device.128483296 |
| Short name | T1728 |
| Test name | |
| Test status | |
| Simulation time | 602338425 ps |
| CPU time | 25.42 seconds |
| Started | Aug 13 06:59:59 PM PDT 24 |
| Finished | Aug 13 07:00:25 PM PDT 24 |
| Peak memory | 576340 kb |
| Host | smart-f649f957-7b88-4fe4-a628-95f67b1baf54 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=128483296 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 89.xbar_access_same_device. 128483296 |
| Directory | /workspace/89.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/89.xbar_access_same_device_slow_rsp.4150552247 |
| Short name | T2603 |
| Test name | |
| Test status | |
| Simulation time | 132999940165 ps |
| CPU time | 2532.76 seconds |
| Started | Aug 13 06:59:54 PM PDT 24 |
| Finished | Aug 13 07:42:07 PM PDT 24 |
| Peak memory | 575796 kb |
| Host | smart-5a7a669a-1a0b-43f8-8b04-013ce47a5fae |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4150552247 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 89.xbar_access_same_ device_slow_rsp.4150552247 |
| Directory | /workspace/89.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/89.xbar_error_and_unmapped_addr.2003974346 |
| Short name | T2725 |
| Test name | |
| Test status | |
| Simulation time | 332140287 ps |
| CPU time | 34.01 seconds |
| Started | Aug 13 06:59:54 PM PDT 24 |
| Finished | Aug 13 07:00:28 PM PDT 24 |
| Peak memory | 575724 kb |
| Host | smart-c8cf0fe6-3a60-4c29-93f7-628fbfa2e581 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2003974346 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 89.xbar_error_and_unmapped_add r.2003974346 |
| Directory | /workspace/89.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/89.xbar_error_random.3465800635 |
| Short name | T2799 |
| Test name | |
| Test status | |
| Simulation time | 1199985771 ps |
| CPU time | 37.77 seconds |
| Started | Aug 13 06:59:59 PM PDT 24 |
| Finished | Aug 13 07:00:36 PM PDT 24 |
| Peak memory | 575664 kb |
| Host | smart-da877209-6719-4250-8005-6b7c0a2097c1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3465800635 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 89.xbar_error_random.3465800635 |
| Directory | /workspace/89.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/89.xbar_random.3066563400 |
| Short name | T1715 |
| Test name | |
| Test status | |
| Simulation time | 216799180 ps |
| CPU time | 21.37 seconds |
| Started | Aug 13 06:59:57 PM PDT 24 |
| Finished | Aug 13 07:00:18 PM PDT 24 |
| Peak memory | 575676 kb |
| Host | smart-a76bf4b2-914c-4c41-934f-9f3795732676 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3066563400 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 89.xbar_random.3066563400 |
| Directory | /workspace/89.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/89.xbar_random_large_delays.1804804958 |
| Short name | T2906 |
| Test name | |
| Test status | |
| Simulation time | 6019911277 ps |
| CPU time | 60.17 seconds |
| Started | Aug 13 06:59:56 PM PDT 24 |
| Finished | Aug 13 07:00:56 PM PDT 24 |
| Peak memory | 573716 kb |
| Host | smart-873cc28c-1374-47e2-b47d-90ca69dbdd1d |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1804804958 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 89.xbar_random_large_delays.1804804958 |
| Directory | /workspace/89.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/89.xbar_random_slow_rsp.1863655272 |
| Short name | T2590 |
| Test name | |
| Test status | |
| Simulation time | 42339348324 ps |
| CPU time | 842.99 seconds |
| Started | Aug 13 06:59:54 PM PDT 24 |
| Finished | Aug 13 07:13:57 PM PDT 24 |
| Peak memory | 575804 kb |
| Host | smart-f1c6e3d9-40dc-4d22-82c9-af83296a912c |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1863655272 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 89.xbar_random_slow_rsp.1863655272 |
| Directory | /workspace/89.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/89.xbar_random_zero_delays.1890305845 |
| Short name | T1657 |
| Test name | |
| Test status | |
| Simulation time | 290479053 ps |
| CPU time | 28.41 seconds |
| Started | Aug 13 06:59:58 PM PDT 24 |
| Finished | Aug 13 07:00:26 PM PDT 24 |
| Peak memory | 575600 kb |
| Host | smart-a29f33ca-a2ce-4a30-8086-2fd4723358ce |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1890305845 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 89.xbar_random_zero_del ays.1890305845 |
| Directory | /workspace/89.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/89.xbar_same_source.3338265705 |
| Short name | T2527 |
| Test name | |
| Test status | |
| Simulation time | 1859206763 ps |
| CPU time | 54.13 seconds |
| Started | Aug 13 06:59:53 PM PDT 24 |
| Finished | Aug 13 07:00:48 PM PDT 24 |
| Peak memory | 575412 kb |
| Host | smart-cc731a29-fd03-41df-a40a-f5d219bcb8f6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3338265705 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 89.xbar_same_source.3338265705 |
| Directory | /workspace/89.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/89.xbar_smoke.3553492668 |
| Short name | T2760 |
| Test name | |
| Test status | |
| Simulation time | 44199244 ps |
| CPU time | 5.98 seconds |
| Started | Aug 13 06:59:56 PM PDT 24 |
| Finished | Aug 13 07:00:02 PM PDT 24 |
| Peak memory | 574256 kb |
| Host | smart-33759dd1-5634-41a2-9822-2d5ff623f410 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3553492668 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 89.xbar_smoke.3553492668 |
| Directory | /workspace/89.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/89.xbar_smoke_large_delays.1921147245 |
| Short name | T1481 |
| Test name | |
| Test status | |
| Simulation time | 10380953974 ps |
| CPU time | 112.51 seconds |
| Started | Aug 13 06:59:56 PM PDT 24 |
| Finished | Aug 13 07:01:48 PM PDT 24 |
| Peak memory | 574424 kb |
| Host | smart-54b281b9-0691-41ba-ad60-69f90689b304 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1921147245 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 89.xbar_smoke_large_delays.1921147245 |
| Directory | /workspace/89.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/89.xbar_smoke_slow_rsp.3486847881 |
| Short name | T667 |
| Test name | |
| Test status | |
| Simulation time | 6173644806 ps |
| CPU time | 103.21 seconds |
| Started | Aug 13 06:59:59 PM PDT 24 |
| Finished | Aug 13 07:01:43 PM PDT 24 |
| Peak memory | 573676 kb |
| Host | smart-41222e4b-1e87-4592-97ce-10737e97efbd |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3486847881 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 89.xbar_smoke_slow_rsp.3486847881 |
| Directory | /workspace/89.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/89.xbar_smoke_zero_delays.541310975 |
| Short name | T1706 |
| Test name | |
| Test status | |
| Simulation time | 48421369 ps |
| CPU time | 6.59 seconds |
| Started | Aug 13 06:59:55 PM PDT 24 |
| Finished | Aug 13 07:00:01 PM PDT 24 |
| Peak memory | 573524 kb |
| Host | smart-d2fd80b6-93b5-425f-aaa9-431976cceb82 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=541310975 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 89.xbar_smoke_zero_delays .541310975 |
| Directory | /workspace/89.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/89.xbar_stress_all.983364922 |
| Short name | T2352 |
| Test name | |
| Test status | |
| Simulation time | 1805077517 ps |
| CPU time | 138.89 seconds |
| Started | Aug 13 06:59:56 PM PDT 24 |
| Finished | Aug 13 07:02:15 PM PDT 24 |
| Peak memory | 576480 kb |
| Host | smart-1c2deaa8-b58a-49f0-8177-a918e2a07282 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=983364922 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 89.xbar_stress_all.983364922 |
| Directory | /workspace/89.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/89.xbar_stress_all_with_error.2793278127 |
| Short name | T727 |
| Test name | |
| Test status | |
| Simulation time | 1471239352 ps |
| CPU time | 125.1 seconds |
| Started | Aug 13 06:59:54 PM PDT 24 |
| Finished | Aug 13 07:01:59 PM PDT 24 |
| Peak memory | 575656 kb |
| Host | smart-163153a7-8b06-4e80-ac0f-100ba8ffa107 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2793278127 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 89.xbar_stress_all_with_error.2793278127 |
| Directory | /workspace/89.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/89.xbar_stress_all_with_rand_reset.244024866 |
| Short name | T2482 |
| Test name | |
| Test status | |
| Simulation time | 9367301242 ps |
| CPU time | 520.17 seconds |
| Started | Aug 13 06:59:58 PM PDT 24 |
| Finished | Aug 13 07:08:39 PM PDT 24 |
| Peak memory | 576548 kb |
| Host | smart-61d28f88-2e4d-4305-859c-71eae4372762 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=244024866 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_res et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 89.xbar_stress_all_ with_rand_reset.244024866 |
| Directory | /workspace/89.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/89.xbar_stress_all_with_reset_error.443690960 |
| Short name | T1546 |
| Test name | |
| Test status | |
| Simulation time | 126381574 ps |
| CPU time | 71.24 seconds |
| Started | Aug 13 07:00:03 PM PDT 24 |
| Finished | Aug 13 07:01:17 PM PDT 24 |
| Peak memory | 576496 kb |
| Host | smart-89f7c2bd-0d34-45aa-8df4-db772b871d98 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=443690960 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 89.xbar_stress_all _with_reset_error.443690960 |
| Directory | /workspace/89.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/89.xbar_unmapped_addr.3209729464 |
| Short name | T2384 |
| Test name | |
| Test status | |
| Simulation time | 264299763 ps |
| CPU time | 29.8 seconds |
| Started | Aug 13 06:59:54 PM PDT 24 |
| Finished | Aug 13 07:00:24 PM PDT 24 |
| Peak memory | 575572 kb |
| Host | smart-006792bf-feb3-4187-b7d6-3a21550bae61 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3209729464 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 89.xbar_unmapped_addr.3209729464 |
| Directory | /workspace/89.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/9.chip_csr_mem_rw_with_rand_reset.3466144561 |
| Short name | T430 |
| Test name | |
| Test status | |
| Simulation time | 11670058689 ps |
| CPU time | 853.52 seconds |
| Started | Aug 13 06:51:02 PM PDT 24 |
| Finished | Aug 13 07:05:16 PM PDT 24 |
| Peak memory | 652448 kb |
| Host | smart-8584650b-a87a-48ac-bad8-86a9350750f3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3466144561 -assert nopostproc + UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top .vdb -cm_log /dev/null -cm_name 9.chip_csr_mem_rw_with_rand_reset.3466144561 |
| Directory | /workspace/9.chip_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/9.chip_csr_rw.4241500461 |
| Short name | T2784 |
| Test name | |
| Test status | |
| Simulation time | 5031703640 ps |
| CPU time | 516.77 seconds |
| Started | Aug 13 06:51:01 PM PDT 24 |
| Finished | Aug 13 06:59:38 PM PDT 24 |
| Peak memory | 598844 kb |
| Host | smart-4c087833-6788-474c-bcf3-566119fd7da2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4241500461 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.chip_csr_rw.4241500461 |
| Directory | /workspace/9.chip_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/9.chip_same_csr_outstanding.2569904952 |
| Short name | T389 |
| Test name | |
| Test status | |
| Simulation time | 16089981274 ps |
| CPU time | 1997.84 seconds |
| Started | Aug 13 06:50:58 PM PDT 24 |
| Finished | Aug 13 07:24:16 PM PDT 24 |
| Peak memory | 592636 kb |
| Host | smart-49bda38a-1ae8-4fbf-b750-b313cef0d9c9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +run_same_csr_outstanding +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2569904952 -assert nopostproc +UVM_TE STNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb - cm_log /dev/null -cm_name 9.chip_same_csr_outstanding.2569904952 |
| Directory | /workspace/9.chip_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/9.chip_tl_errors.3897534917 |
| Short name | T751 |
| Test name | |
| Test status | |
| Simulation time | 3295440000 ps |
| CPU time | 169.05 seconds |
| Started | Aug 13 06:50:57 PM PDT 24 |
| Finished | Aug 13 06:53:46 PM PDT 24 |
| Peak memory | 603484 kb |
| Host | smart-c195fc9a-62c0-40f6-90fb-c555264c50c7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3897534917 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.chip_tl_errors.3897534917 |
| Directory | /workspace/9.chip_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/9.xbar_access_same_device.1977889631 |
| Short name | T1837 |
| Test name | |
| Test status | |
| Simulation time | 2391274332 ps |
| CPU time | 84.28 seconds |
| Started | Aug 13 06:51:15 PM PDT 24 |
| Finished | Aug 13 06:52:40 PM PDT 24 |
| Peak memory | 575820 kb |
| Host | smart-64e65b59-9ba9-4de1-9e89-52acf60f2cee |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1977889631 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.xbar_access_same_device. 1977889631 |
| Directory | /workspace/9.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/9.xbar_access_same_device_slow_rsp.2107636378 |
| Short name | T895 |
| Test name | |
| Test status | |
| Simulation time | 2964789653 ps |
| CPU time | 53.9 seconds |
| Started | Aug 13 06:51:19 PM PDT 24 |
| Finished | Aug 13 06:52:13 PM PDT 24 |
| Peak memory | 574272 kb |
| Host | smart-17e57152-f471-4714-bdd4-febf0621bca9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2107636378 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.xbar_access_same_d evice_slow_rsp.2107636378 |
| Directory | /workspace/9.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/9.xbar_error_and_unmapped_addr.242765404 |
| Short name | T2110 |
| Test name | |
| Test status | |
| Simulation time | 297959914 ps |
| CPU time | 27.94 seconds |
| Started | Aug 13 06:50:58 PM PDT 24 |
| Finished | Aug 13 06:51:26 PM PDT 24 |
| Peak memory | 575528 kb |
| Host | smart-2e7bee56-fc7f-4bfb-8f92-39b52a828dd5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=242765404 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.xbar_error_and_unmapped_addr. 242765404 |
| Directory | /workspace/9.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/9.xbar_error_random.15780728 |
| Short name | T2684 |
| Test name | |
| Test status | |
| Simulation time | 165205795 ps |
| CPU time | 14.59 seconds |
| Started | Aug 13 06:51:14 PM PDT 24 |
| Finished | Aug 13 06:51:29 PM PDT 24 |
| Peak memory | 575448 kb |
| Host | smart-24333b80-9c21-4d7a-af33-2556cf6a3197 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15780728 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.xbar_error_random.15780728 |
| Directory | /workspace/9.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/9.xbar_random.4058038876 |
| Short name | T2054 |
| Test name | |
| Test status | |
| Simulation time | 513683804 ps |
| CPU time | 39.77 seconds |
| Started | Aug 13 06:51:03 PM PDT 24 |
| Finished | Aug 13 06:51:43 PM PDT 24 |
| Peak memory | 575712 kb |
| Host | smart-7a01fae5-6743-46f3-b6b2-5f869f6fb438 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4058038876 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.xbar_random.4058038876 |
| Directory | /workspace/9.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/9.xbar_random_large_delays.2136015610 |
| Short name | T579 |
| Test name | |
| Test status | |
| Simulation time | 79048457665 ps |
| CPU time | 870.04 seconds |
| Started | Aug 13 06:51:08 PM PDT 24 |
| Finished | Aug 13 07:05:38 PM PDT 24 |
| Peak memory | 575636 kb |
| Host | smart-162e3e1e-c17f-43fc-937d-4fe1935bfdee |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2136015610 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.xbar_random_large_delays.2136015610 |
| Directory | /workspace/9.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/9.xbar_random_slow_rsp.2990334742 |
| Short name | T606 |
| Test name | |
| Test status | |
| Simulation time | 40812097193 ps |
| CPU time | 623.74 seconds |
| Started | Aug 13 06:51:12 PM PDT 24 |
| Finished | Aug 13 07:01:36 PM PDT 24 |
| Peak memory | 575604 kb |
| Host | smart-9b93fc81-77cc-4dc8-9b1f-a566cebb852c |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2990334742 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.xbar_random_slow_rsp.2990334742 |
| Directory | /workspace/9.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/9.xbar_random_zero_delays.1767132464 |
| Short name | T2661 |
| Test name | |
| Test status | |
| Simulation time | 289984332 ps |
| CPU time | 24.8 seconds |
| Started | Aug 13 06:51:12 PM PDT 24 |
| Finished | Aug 13 06:51:37 PM PDT 24 |
| Peak memory | 575608 kb |
| Host | smart-49508368-cdb4-480d-80b2-c0d203c250f9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1767132464 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.xbar_random_zero_dela ys.1767132464 |
| Directory | /workspace/9.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/9.xbar_same_source.4016126300 |
| Short name | T1872 |
| Test name | |
| Test status | |
| Simulation time | 343494063 ps |
| CPU time | 12.8 seconds |
| Started | Aug 13 06:51:03 PM PDT 24 |
| Finished | Aug 13 06:51:16 PM PDT 24 |
| Peak memory | 575636 kb |
| Host | smart-e3121590-150e-4667-afe2-eeab5d1807d0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4016126300 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.xbar_same_source.4016126300 |
| Directory | /workspace/9.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/9.xbar_smoke.322683260 |
| Short name | T2477 |
| Test name | |
| Test status | |
| Simulation time | 211621642 ps |
| CPU time | 9.4 seconds |
| Started | Aug 13 06:50:56 PM PDT 24 |
| Finished | Aug 13 06:51:05 PM PDT 24 |
| Peak memory | 574168 kb |
| Host | smart-302a8791-1c6f-4b8e-a902-4faba30a8f52 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=322683260 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.xbar_smoke.322683260 |
| Directory | /workspace/9.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/9.xbar_smoke_large_delays.2529034812 |
| Short name | T1564 |
| Test name | |
| Test status | |
| Simulation time | 5896391003 ps |
| CPU time | 60.68 seconds |
| Started | Aug 13 06:51:14 PM PDT 24 |
| Finished | Aug 13 06:52:15 PM PDT 24 |
| Peak memory | 573680 kb |
| Host | smart-fc9fcb96-6fc9-4709-9368-8980029c4905 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2529034812 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.xbar_smoke_large_delays.2529034812 |
| Directory | /workspace/9.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/9.xbar_smoke_slow_rsp.827881411 |
| Short name | T1436 |
| Test name | |
| Test status | |
| Simulation time | 4015713684 ps |
| CPU time | 63.84 seconds |
| Started | Aug 13 06:51:07 PM PDT 24 |
| Finished | Aug 13 06:52:11 PM PDT 24 |
| Peak memory | 573568 kb |
| Host | smart-02a77c4c-33ca-4817-bc07-698153cd4e3e |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=827881411 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.xbar_smoke_slow_rsp.827881411 |
| Directory | /workspace/9.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/9.xbar_smoke_zero_delays.268387312 |
| Short name | T2368 |
| Test name | |
| Test status | |
| Simulation time | 40566665 ps |
| CPU time | 5.75 seconds |
| Started | Aug 13 06:51:12 PM PDT 24 |
| Finished | Aug 13 06:51:18 PM PDT 24 |
| Peak memory | 573492 kb |
| Host | smart-8c91ab2e-2b51-4de5-8a09-f4959e754577 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=268387312 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.xbar_smoke_zero_delays. 268387312 |
| Directory | /workspace/9.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/9.xbar_stress_all.2361174984 |
| Short name | T2094 |
| Test name | |
| Test status | |
| Simulation time | 1597295095 ps |
| CPU time | 144.59 seconds |
| Started | Aug 13 06:51:12 PM PDT 24 |
| Finished | Aug 13 06:53:36 PM PDT 24 |
| Peak memory | 576424 kb |
| Host | smart-cba462ce-338c-424a-a7a8-5f2d909afacc |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2361174984 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.xbar_stress_all.2361174984 |
| Directory | /workspace/9.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/9.xbar_stress_all_with_error.1622983258 |
| Short name | T2568 |
| Test name | |
| Test status | |
| Simulation time | 3039621399 ps |
| CPU time | 199.34 seconds |
| Started | Aug 13 06:51:08 PM PDT 24 |
| Finished | Aug 13 06:54:28 PM PDT 24 |
| Peak memory | 575732 kb |
| Host | smart-871ff4ed-5c76-40ae-afc5-6ff03c3f4fc2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1622983258 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.xbar_stress_all_with_error.1622983258 |
| Directory | /workspace/9.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/9.xbar_stress_all_with_rand_reset.1583708876 |
| Short name | T925 |
| Test name | |
| Test status | |
| Simulation time | 53953709 ps |
| CPU time | 20.45 seconds |
| Started | Aug 13 06:51:12 PM PDT 24 |
| Finished | Aug 13 06:51:33 PM PDT 24 |
| Peak memory | 573676 kb |
| Host | smart-e1587820-658e-4ce0-ac9c-94d1ce7d915f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1583708876 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.xbar_stress_all_ with_rand_reset.1583708876 |
| Directory | /workspace/9.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/9.xbar_stress_all_with_reset_error.3163317744 |
| Short name | T2293 |
| Test name | |
| Test status | |
| Simulation time | 2445777212 ps |
| CPU time | 331.19 seconds |
| Started | Aug 13 06:51:04 PM PDT 24 |
| Finished | Aug 13 06:56:36 PM PDT 24 |
| Peak memory | 576540 kb |
| Host | smart-1d9f7a31-af8a-4db0-8365-8b4b1b89ec6c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3163317744 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.xbar_stress_all _with_reset_error.3163317744 |
| Directory | /workspace/9.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/9.xbar_unmapped_addr.2759344889 |
| Short name | T2831 |
| Test name | |
| Test status | |
| Simulation time | 20385352 ps |
| CPU time | 5.06 seconds |
| Started | Aug 13 06:51:09 PM PDT 24 |
| Finished | Aug 13 06:51:15 PM PDT 24 |
| Peak memory | 574280 kb |
| Host | smart-ff07a8e8-92a4-4074-8ddd-717fd928bf17 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2759344889 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.xbar_unmapped_addr.2759344889 |
| Directory | /workspace/9.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/90.xbar_access_same_device.514444832 |
| Short name | T2168 |
| Test name | |
| Test status | |
| Simulation time | 757305311 ps |
| CPU time | 54.27 seconds |
| Started | Aug 13 07:00:03 PM PDT 24 |
| Finished | Aug 13 07:01:00 PM PDT 24 |
| Peak memory | 575744 kb |
| Host | smart-04a39001-436a-4b84-8d4b-606719a25fa1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=514444832 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 90.xbar_access_same_device. 514444832 |
| Directory | /workspace/90.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/90.xbar_access_same_device_slow_rsp.2385484709 |
| Short name | T2503 |
| Test name | |
| Test status | |
| Simulation time | 56110878062 ps |
| CPU time | 1004.46 seconds |
| Started | Aug 13 07:00:01 PM PDT 24 |
| Finished | Aug 13 07:16:46 PM PDT 24 |
| Peak memory | 575664 kb |
| Host | smart-dc7a575e-c57e-4aea-b145-e1f51c37d9dd |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2385484709 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 90.xbar_access_same_ device_slow_rsp.2385484709 |
| Directory | /workspace/90.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/90.xbar_error_and_unmapped_addr.2428056740 |
| Short name | T2617 |
| Test name | |
| Test status | |
| Simulation time | 914120611 ps |
| CPU time | 39.03 seconds |
| Started | Aug 13 07:00:02 PM PDT 24 |
| Finished | Aug 13 07:00:45 PM PDT 24 |
| Peak memory | 575692 kb |
| Host | smart-9e8f3fcb-e9c1-4e04-8277-5b693d132c6b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2428056740 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 90.xbar_error_and_unmapped_add r.2428056740 |
| Directory | /workspace/90.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/90.xbar_error_random.1529536171 |
| Short name | T1943 |
| Test name | |
| Test status | |
| Simulation time | 855881163 ps |
| CPU time | 28.28 seconds |
| Started | Aug 13 07:00:05 PM PDT 24 |
| Finished | Aug 13 07:00:34 PM PDT 24 |
| Peak memory | 575716 kb |
| Host | smart-8779df18-2208-48be-9149-616189c3d3b2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1529536171 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 90.xbar_error_random.1529536171 |
| Directory | /workspace/90.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/90.xbar_random.2786067773 |
| Short name | T2063 |
| Test name | |
| Test status | |
| Simulation time | 1689993855 ps |
| CPU time | 61.32 seconds |
| Started | Aug 13 07:00:02 PM PDT 24 |
| Finished | Aug 13 07:01:07 PM PDT 24 |
| Peak memory | 575704 kb |
| Host | smart-0ae15392-455b-4af1-8b76-cda23a58d58d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2786067773 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 90.xbar_random.2786067773 |
| Directory | /workspace/90.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/90.xbar_random_large_delays.3122838448 |
| Short name | T498 |
| Test name | |
| Test status | |
| Simulation time | 40149416321 ps |
| CPU time | 462.71 seconds |
| Started | Aug 13 07:00:04 PM PDT 24 |
| Finished | Aug 13 07:07:49 PM PDT 24 |
| Peak memory | 575792 kb |
| Host | smart-0c9ad9f3-3349-408b-9dd5-44f247c91c60 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3122838448 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 90.xbar_random_large_delays.3122838448 |
| Directory | /workspace/90.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/90.xbar_random_slow_rsp.2641251925 |
| Short name | T2655 |
| Test name | |
| Test status | |
| Simulation time | 7643378519 ps |
| CPU time | 133.92 seconds |
| Started | Aug 13 07:00:04 PM PDT 24 |
| Finished | Aug 13 07:02:20 PM PDT 24 |
| Peak memory | 575740 kb |
| Host | smart-5113c74c-d36b-45d5-9064-04f9439ab7b2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2641251925 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 90.xbar_random_slow_rsp.2641251925 |
| Directory | /workspace/90.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/90.xbar_random_zero_delays.1623447399 |
| Short name | T2190 |
| Test name | |
| Test status | |
| Simulation time | 260638474 ps |
| CPU time | 24.19 seconds |
| Started | Aug 13 07:00:02 PM PDT 24 |
| Finished | Aug 13 07:00:30 PM PDT 24 |
| Peak memory | 575600 kb |
| Host | smart-1608a995-b3cf-429a-af66-c8be4f00a59d |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1623447399 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 90.xbar_random_zero_del ays.1623447399 |
| Directory | /workspace/90.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/90.xbar_same_source.2280983726 |
| Short name | T2543 |
| Test name | |
| Test status | |
| Simulation time | 1457219777 ps |
| CPU time | 43.38 seconds |
| Started | Aug 13 07:00:01 PM PDT 24 |
| Finished | Aug 13 07:00:44 PM PDT 24 |
| Peak memory | 575544 kb |
| Host | smart-3276ce34-0cd1-4fd9-912c-abcecf295ce4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2280983726 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 90.xbar_same_source.2280983726 |
| Directory | /workspace/90.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/90.xbar_smoke.2887943168 |
| Short name | T2089 |
| Test name | |
| Test status | |
| Simulation time | 45250246 ps |
| CPU time | 6.8 seconds |
| Started | Aug 13 07:00:02 PM PDT 24 |
| Finished | Aug 13 07:00:12 PM PDT 24 |
| Peak memory | 574236 kb |
| Host | smart-de951c57-d759-4a41-8a9c-5e9833d5f6f9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2887943168 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 90.xbar_smoke.2887943168 |
| Directory | /workspace/90.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/90.xbar_smoke_large_delays.3250134064 |
| Short name | T1593 |
| Test name | |
| Test status | |
| Simulation time | 6934292932 ps |
| CPU time | 74.25 seconds |
| Started | Aug 13 07:00:05 PM PDT 24 |
| Finished | Aug 13 07:01:20 PM PDT 24 |
| Peak memory | 574328 kb |
| Host | smart-7f2dc2bb-5743-4667-8ca4-4c62df8ee3e9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3250134064 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 90.xbar_smoke_large_delays.3250134064 |
| Directory | /workspace/90.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/90.xbar_smoke_slow_rsp.1068175419 |
| Short name | T2401 |
| Test name | |
| Test status | |
| Simulation time | 4814254309 ps |
| CPU time | 78.49 seconds |
| Started | Aug 13 07:00:09 PM PDT 24 |
| Finished | Aug 13 07:01:27 PM PDT 24 |
| Peak memory | 574292 kb |
| Host | smart-e703539a-54c3-46b8-834c-9d9c52161258 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1068175419 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 90.xbar_smoke_slow_rsp.1068175419 |
| Directory | /workspace/90.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/90.xbar_smoke_zero_delays.3224401382 |
| Short name | T487 |
| Test name | |
| Test status | |
| Simulation time | 50463466 ps |
| CPU time | 6.32 seconds |
| Started | Aug 13 07:00:08 PM PDT 24 |
| Finished | Aug 13 07:00:14 PM PDT 24 |
| Peak memory | 573564 kb |
| Host | smart-250426b8-6590-4cd8-b267-3f9837ff757a |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3224401382 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 90.xbar_smoke_zero_delay s.3224401382 |
| Directory | /workspace/90.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/90.xbar_stress_all.2391154451 |
| Short name | T2468 |
| Test name | |
| Test status | |
| Simulation time | 638334200 ps |
| CPU time | 59.48 seconds |
| Started | Aug 13 07:00:13 PM PDT 24 |
| Finished | Aug 13 07:01:13 PM PDT 24 |
| Peak memory | 575676 kb |
| Host | smart-bb30b18d-0036-4a9b-9d6f-109bb4b09b2b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2391154451 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 90.xbar_stress_all.2391154451 |
| Directory | /workspace/90.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/90.xbar_stress_all_with_error.2964613116 |
| Short name | T2846 |
| Test name | |
| Test status | |
| Simulation time | 6576276906 ps |
| CPU time | 216.9 seconds |
| Started | Aug 13 07:00:13 PM PDT 24 |
| Finished | Aug 13 07:03:50 PM PDT 24 |
| Peak memory | 575684 kb |
| Host | smart-0d0f5522-fa7e-4ab8-848e-760765076a6a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2964613116 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 90.xbar_stress_all_with_error.2964613116 |
| Directory | /workspace/90.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/90.xbar_stress_all_with_rand_reset.1571961263 |
| Short name | T1941 |
| Test name | |
| Test status | |
| Simulation time | 3217697094 ps |
| CPU time | 494.72 seconds |
| Started | Aug 13 07:00:09 PM PDT 24 |
| Finished | Aug 13 07:08:24 PM PDT 24 |
| Peak memory | 576580 kb |
| Host | smart-921a501f-5241-4bd4-8ad3-2d9edb8c9d28 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1571961263 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 90.xbar_stress_all _with_rand_reset.1571961263 |
| Directory | /workspace/90.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/90.xbar_unmapped_addr.4093505859 |
| Short name | T2638 |
| Test name | |
| Test status | |
| Simulation time | 71690783 ps |
| CPU time | 10.91 seconds |
| Started | Aug 13 07:00:03 PM PDT 24 |
| Finished | Aug 13 07:00:17 PM PDT 24 |
| Peak memory | 575572 kb |
| Host | smart-191a9af6-5586-4af1-9321-7673fe7843ec |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4093505859 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 90.xbar_unmapped_addr.4093505859 |
| Directory | /workspace/90.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/91.xbar_access_same_device.1490103511 |
| Short name | T863 |
| Test name | |
| Test status | |
| Simulation time | 1062754517 ps |
| CPU time | 82.32 seconds |
| Started | Aug 13 07:00:17 PM PDT 24 |
| Finished | Aug 13 07:01:39 PM PDT 24 |
| Peak memory | 575664 kb |
| Host | smart-c7a3bc61-a555-4c8b-9021-c92a6c4749a6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1490103511 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 91.xbar_access_same_device .1490103511 |
| Directory | /workspace/91.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/91.xbar_access_same_device_slow_rsp.1957141618 |
| Short name | T1823 |
| Test name | |
| Test status | |
| Simulation time | 110828538044 ps |
| CPU time | 2054.31 seconds |
| Started | Aug 13 07:00:17 PM PDT 24 |
| Finished | Aug 13 07:34:32 PM PDT 24 |
| Peak memory | 575676 kb |
| Host | smart-6c374fd3-b53f-4f7f-aa83-7cb368ffec38 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1957141618 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 91.xbar_access_same_ device_slow_rsp.1957141618 |
| Directory | /workspace/91.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/91.xbar_error_and_unmapped_addr.1963039491 |
| Short name | T2673 |
| Test name | |
| Test status | |
| Simulation time | 1023954453 ps |
| CPU time | 40.82 seconds |
| Started | Aug 13 07:00:13 PM PDT 24 |
| Finished | Aug 13 07:00:54 PM PDT 24 |
| Peak memory | 575492 kb |
| Host | smart-4027022c-f7b8-407f-ace7-e761d16dc331 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1963039491 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 91.xbar_error_and_unmapped_add r.1963039491 |
| Directory | /workspace/91.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/91.xbar_error_random.2176690826 |
| Short name | T2290 |
| Test name | |
| Test status | |
| Simulation time | 392385279 ps |
| CPU time | 32.35 seconds |
| Started | Aug 13 07:00:17 PM PDT 24 |
| Finished | Aug 13 07:00:49 PM PDT 24 |
| Peak memory | 575472 kb |
| Host | smart-5f40cca3-80b1-49c0-9fb0-ff97df37db6b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2176690826 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 91.xbar_error_random.2176690826 |
| Directory | /workspace/91.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/91.xbar_random.2010469436 |
| Short name | T1531 |
| Test name | |
| Test status | |
| Simulation time | 184372832 ps |
| CPU time | 16.83 seconds |
| Started | Aug 13 07:00:11 PM PDT 24 |
| Finished | Aug 13 07:00:28 PM PDT 24 |
| Peak memory | 575524 kb |
| Host | smart-6410118d-607a-42d2-9369-8272aea51731 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2010469436 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 91.xbar_random.2010469436 |
| Directory | /workspace/91.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/91.xbar_random_large_delays.1528348403 |
| Short name | T2344 |
| Test name | |
| Test status | |
| Simulation time | 48580993357 ps |
| CPU time | 557.18 seconds |
| Started | Aug 13 07:00:09 PM PDT 24 |
| Finished | Aug 13 07:09:26 PM PDT 24 |
| Peak memory | 575816 kb |
| Host | smart-cb341a93-90ce-4fe1-8b64-058274a66775 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1528348403 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 91.xbar_random_large_delays.1528348403 |
| Directory | /workspace/91.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/91.xbar_random_slow_rsp.1533408636 |
| Short name | T1888 |
| Test name | |
| Test status | |
| Simulation time | 5400839156 ps |
| CPU time | 89.03 seconds |
| Started | Aug 13 07:00:11 PM PDT 24 |
| Finished | Aug 13 07:01:40 PM PDT 24 |
| Peak memory | 573716 kb |
| Host | smart-49a336fe-1a83-489b-a86a-f44428cd35fe |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1533408636 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 91.xbar_random_slow_rsp.1533408636 |
| Directory | /workspace/91.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/91.xbar_random_zero_delays.60096757 |
| Short name | T1641 |
| Test name | |
| Test status | |
| Simulation time | 395897988 ps |
| CPU time | 37 seconds |
| Started | Aug 13 07:00:09 PM PDT 24 |
| Finished | Aug 13 07:00:46 PM PDT 24 |
| Peak memory | 575632 kb |
| Host | smart-0ef818d9-d9c7-4ce6-b956-1b099c74979f |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=60096757 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 91.xbar_random_zero_delay s.60096757 |
| Directory | /workspace/91.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/91.xbar_same_source.4265438948 |
| Short name | T1750 |
| Test name | |
| Test status | |
| Simulation time | 884294890 ps |
| CPU time | 27.45 seconds |
| Started | Aug 13 07:00:10 PM PDT 24 |
| Finished | Aug 13 07:00:37 PM PDT 24 |
| Peak memory | 575508 kb |
| Host | smart-5822b116-b17c-4716-bcfb-46646b936eec |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4265438948 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 91.xbar_same_source.4265438948 |
| Directory | /workspace/91.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/91.xbar_smoke.465779370 |
| Short name | T2182 |
| Test name | |
| Test status | |
| Simulation time | 52541025 ps |
| CPU time | 6.68 seconds |
| Started | Aug 13 07:00:11 PM PDT 24 |
| Finished | Aug 13 07:00:17 PM PDT 24 |
| Peak memory | 573560 kb |
| Host | smart-b9cff2be-7de3-4c38-829b-4d14a4c63eca |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=465779370 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 91.xbar_smoke.465779370 |
| Directory | /workspace/91.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/91.xbar_smoke_large_delays.1212545253 |
| Short name | T2117 |
| Test name | |
| Test status | |
| Simulation time | 7288977283 ps |
| CPU time | 74.43 seconds |
| Started | Aug 13 07:00:09 PM PDT 24 |
| Finished | Aug 13 07:01:24 PM PDT 24 |
| Peak memory | 573680 kb |
| Host | smart-5e751dfa-dd6a-4c1b-84c1-72e893660a5d |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1212545253 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 91.xbar_smoke_large_delays.1212545253 |
| Directory | /workspace/91.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/91.xbar_smoke_slow_rsp.1987377718 |
| Short name | T2387 |
| Test name | |
| Test status | |
| Simulation time | 3565226670 ps |
| CPU time | 56 seconds |
| Started | Aug 13 07:00:09 PM PDT 24 |
| Finished | Aug 13 07:01:05 PM PDT 24 |
| Peak memory | 573608 kb |
| Host | smart-d6dab144-fa48-4018-a723-f66d0b7933f9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1987377718 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 91.xbar_smoke_slow_rsp.1987377718 |
| Directory | /workspace/91.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/91.xbar_smoke_zero_delays.1599217369 |
| Short name | T2197 |
| Test name | |
| Test status | |
| Simulation time | 45718879 ps |
| CPU time | 6.12 seconds |
| Started | Aug 13 07:00:11 PM PDT 24 |
| Finished | Aug 13 07:00:17 PM PDT 24 |
| Peak memory | 574232 kb |
| Host | smart-f091ae16-4c8c-484b-ab39-8d2c9e75568e |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1599217369 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 91.xbar_smoke_zero_delay s.1599217369 |
| Directory | /workspace/91.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/91.xbar_stress_all.1986783645 |
| Short name | T2627 |
| Test name | |
| Test status | |
| Simulation time | 8015636315 ps |
| CPU time | 311.23 seconds |
| Started | Aug 13 07:00:11 PM PDT 24 |
| Finished | Aug 13 07:05:23 PM PDT 24 |
| Peak memory | 576508 kb |
| Host | smart-60cb644d-e30b-40db-994b-f2778d59056a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1986783645 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 91.xbar_stress_all.1986783645 |
| Directory | /workspace/91.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/91.xbar_stress_all_with_error.1850930552 |
| Short name | T2752 |
| Test name | |
| Test status | |
| Simulation time | 7316844675 ps |
| CPU time | 260 seconds |
| Started | Aug 13 07:00:10 PM PDT 24 |
| Finished | Aug 13 07:04:30 PM PDT 24 |
| Peak memory | 576512 kb |
| Host | smart-21a62a28-3e66-4642-b1c5-57bb4de11fbe |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1850930552 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 91.xbar_stress_all_with_error.1850930552 |
| Directory | /workspace/91.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/91.xbar_stress_all_with_rand_reset.1118185283 |
| Short name | T472 |
| Test name | |
| Test status | |
| Simulation time | 686922036 ps |
| CPU time | 259.25 seconds |
| Started | Aug 13 07:00:10 PM PDT 24 |
| Finished | Aug 13 07:04:29 PM PDT 24 |
| Peak memory | 575760 kb |
| Host | smart-4a7bcd95-2b66-4313-ad80-983fe2d480e8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1118185283 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 91.xbar_stress_all _with_rand_reset.1118185283 |
| Directory | /workspace/91.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/91.xbar_stress_all_with_reset_error.3146475969 |
| Short name | T2357 |
| Test name | |
| Test status | |
| Simulation time | 3754501556 ps |
| CPU time | 468.85 seconds |
| Started | Aug 13 07:00:12 PM PDT 24 |
| Finished | Aug 13 07:08:02 PM PDT 24 |
| Peak memory | 577564 kb |
| Host | smart-a3bc28a8-44a9-4e46-9919-5a99a2d653bb |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3146475969 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 91.xbar_stress_al l_with_reset_error.3146475969 |
| Directory | /workspace/91.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/91.xbar_unmapped_addr.1526738191 |
| Short name | T1994 |
| Test name | |
| Test status | |
| Simulation time | 26591765 ps |
| CPU time | 5.81 seconds |
| Started | Aug 13 07:00:16 PM PDT 24 |
| Finished | Aug 13 07:00:22 PM PDT 24 |
| Peak memory | 573688 kb |
| Host | smart-239a8ec9-faa5-4867-a0f0-c9ec406a9376 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1526738191 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 91.xbar_unmapped_addr.1526738191 |
| Directory | /workspace/91.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/92.xbar_access_same_device.998531061 |
| Short name | T2194 |
| Test name | |
| Test status | |
| Simulation time | 640243751 ps |
| CPU time | 56.92 seconds |
| Started | Aug 13 07:00:16 PM PDT 24 |
| Finished | Aug 13 07:01:13 PM PDT 24 |
| Peak memory | 575696 kb |
| Host | smart-e1787a32-1522-4fc3-804d-9a43773f526e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=998531061 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 92.xbar_access_same_device. 998531061 |
| Directory | /workspace/92.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/92.xbar_access_same_device_slow_rsp.259907454 |
| Short name | T1946 |
| Test name | |
| Test status | |
| Simulation time | 157387193435 ps |
| CPU time | 2658.18 seconds |
| Started | Aug 13 07:00:20 PM PDT 24 |
| Finished | Aug 13 07:44:38 PM PDT 24 |
| Peak memory | 575696 kb |
| Host | smart-a59246c2-4cc2-4b3e-84cb-559900eb607e |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=259907454 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 92.xbar_access_same_d evice_slow_rsp.259907454 |
| Directory | /workspace/92.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/92.xbar_error_and_unmapped_addr.500380151 |
| Short name | T2454 |
| Test name | |
| Test status | |
| Simulation time | 239760524 ps |
| CPU time | 11.48 seconds |
| Started | Aug 13 07:00:16 PM PDT 24 |
| Finished | Aug 13 07:00:27 PM PDT 24 |
| Peak memory | 575820 kb |
| Host | smart-ed560e24-2531-4b1b-87bf-96347cc0195f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=500380151 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 92.xbar_error_and_unmapped_addr .500380151 |
| Directory | /workspace/92.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/92.xbar_error_random.1729019353 |
| Short name | T2665 |
| Test name | |
| Test status | |
| Simulation time | 2176492691 ps |
| CPU time | 66.26 seconds |
| Started | Aug 13 07:00:23 PM PDT 24 |
| Finished | Aug 13 07:01:29 PM PDT 24 |
| Peak memory | 575732 kb |
| Host | smart-0261a5a4-ab62-4e6b-99cd-6c1cd1a37f46 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1729019353 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 92.xbar_error_random.1729019353 |
| Directory | /workspace/92.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/92.xbar_random.3567406659 |
| Short name | T497 |
| Test name | |
| Test status | |
| Simulation time | 1377038999 ps |
| CPU time | 42.97 seconds |
| Started | Aug 13 07:00:16 PM PDT 24 |
| Finished | Aug 13 07:00:59 PM PDT 24 |
| Peak memory | 575628 kb |
| Host | smart-7b7fb6cb-82d3-4fe0-9788-01d4e1a48e31 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3567406659 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 92.xbar_random.3567406659 |
| Directory | /workspace/92.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/92.xbar_random_large_delays.1004585605 |
| Short name | T2466 |
| Test name | |
| Test status | |
| Simulation time | 68088714007 ps |
| CPU time | 771.45 seconds |
| Started | Aug 13 07:00:16 PM PDT 24 |
| Finished | Aug 13 07:13:08 PM PDT 24 |
| Peak memory | 575772 kb |
| Host | smart-47286ccb-866c-48f2-9b27-b712bb843002 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1004585605 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 92.xbar_random_large_delays.1004585605 |
| Directory | /workspace/92.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/92.xbar_random_slow_rsp.1063004977 |
| Short name | T2479 |
| Test name | |
| Test status | |
| Simulation time | 47558801968 ps |
| CPU time | 964.28 seconds |
| Started | Aug 13 07:00:18 PM PDT 24 |
| Finished | Aug 13 07:16:22 PM PDT 24 |
| Peak memory | 575680 kb |
| Host | smart-76889ee9-1e24-4bec-b6ae-082dcf5fbf42 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1063004977 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 92.xbar_random_slow_rsp.1063004977 |
| Directory | /workspace/92.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/92.xbar_random_zero_delays.3722276690 |
| Short name | T1954 |
| Test name | |
| Test status | |
| Simulation time | 380087171 ps |
| CPU time | 35.98 seconds |
| Started | Aug 13 07:00:17 PM PDT 24 |
| Finished | Aug 13 07:00:53 PM PDT 24 |
| Peak memory | 575484 kb |
| Host | smart-99052887-e4cc-4929-82a5-035a32ce3770 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3722276690 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 92.xbar_random_zero_del ays.3722276690 |
| Directory | /workspace/92.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/92.xbar_same_source.506207063 |
| Short name | T1696 |
| Test name | |
| Test status | |
| Simulation time | 2253205172 ps |
| CPU time | 60.99 seconds |
| Started | Aug 13 07:00:17 PM PDT 24 |
| Finished | Aug 13 07:01:19 PM PDT 24 |
| Peak memory | 575704 kb |
| Host | smart-563891e5-e160-400c-b658-8fba71fd0e5b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=506207063 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 92.xbar_same_source.506207063 |
| Directory | /workspace/92.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/92.xbar_smoke.4041643190 |
| Short name | T629 |
| Test name | |
| Test status | |
| Simulation time | 214530388 ps |
| CPU time | 9.07 seconds |
| Started | Aug 13 07:00:17 PM PDT 24 |
| Finished | Aug 13 07:00:26 PM PDT 24 |
| Peak memory | 573608 kb |
| Host | smart-cd4bcc1c-ffc4-46a4-8dcf-c8f43524c9dd |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4041643190 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 92.xbar_smoke.4041643190 |
| Directory | /workspace/92.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/92.xbar_smoke_large_delays.811314067 |
| Short name | T1721 |
| Test name | |
| Test status | |
| Simulation time | 9811787802 ps |
| CPU time | 103.66 seconds |
| Started | Aug 13 07:00:13 PM PDT 24 |
| Finished | Aug 13 07:01:56 PM PDT 24 |
| Peak memory | 573648 kb |
| Host | smart-f9fefc13-f2e5-421b-901b-7888250c7301 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=811314067 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 92.xbar_smoke_large_delays.811314067 |
| Directory | /workspace/92.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/92.xbar_smoke_slow_rsp.2956498651 |
| Short name | T1817 |
| Test name | |
| Test status | |
| Simulation time | 2669345476 ps |
| CPU time | 43.82 seconds |
| Started | Aug 13 07:00:16 PM PDT 24 |
| Finished | Aug 13 07:01:00 PM PDT 24 |
| Peak memory | 574316 kb |
| Host | smart-2c181d56-a789-4bd3-bf1d-43d5cd6f109d |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2956498651 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 92.xbar_smoke_slow_rsp.2956498651 |
| Directory | /workspace/92.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/92.xbar_smoke_zero_delays.303887569 |
| Short name | T1517 |
| Test name | |
| Test status | |
| Simulation time | 34979460 ps |
| CPU time | 5.81 seconds |
| Started | Aug 13 07:00:09 PM PDT 24 |
| Finished | Aug 13 07:00:15 PM PDT 24 |
| Peak memory | 573572 kb |
| Host | smart-69cb8559-b9dd-4146-a500-52105490bc09 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=303887569 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 92.xbar_smoke_zero_delays .303887569 |
| Directory | /workspace/92.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/92.xbar_stress_all.3611391032 |
| Short name | T2319 |
| Test name | |
| Test status | |
| Simulation time | 9192230550 ps |
| CPU time | 364.11 seconds |
| Started | Aug 13 07:00:16 PM PDT 24 |
| Finished | Aug 13 07:06:20 PM PDT 24 |
| Peak memory | 575684 kb |
| Host | smart-3a23aa19-7276-4c8e-ae3d-4e3b1179001c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3611391032 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 92.xbar_stress_all.3611391032 |
| Directory | /workspace/92.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/92.xbar_stress_all_with_error.942236016 |
| Short name | T1509 |
| Test name | |
| Test status | |
| Simulation time | 2684364299 ps |
| CPU time | 217.3 seconds |
| Started | Aug 13 07:00:17 PM PDT 24 |
| Finished | Aug 13 07:03:54 PM PDT 24 |
| Peak memory | 576548 kb |
| Host | smart-57917c31-5023-4002-bbef-dfe25f1e06bf |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=942236016 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 92.xbar_stress_all_with_error.942236016 |
| Directory | /workspace/92.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/92.xbar_stress_all_with_rand_reset.402240296 |
| Short name | T575 |
| Test name | |
| Test status | |
| Simulation time | 12141657039 ps |
| CPU time | 789.24 seconds |
| Started | Aug 13 07:00:18 PM PDT 24 |
| Finished | Aug 13 07:13:27 PM PDT 24 |
| Peak memory | 575732 kb |
| Host | smart-883665b6-2ad2-4900-be9e-85e57a40d20c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=402240296 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_res et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 92.xbar_stress_all_ with_rand_reset.402240296 |
| Directory | /workspace/92.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/92.xbar_stress_all_with_reset_error.2015473375 |
| Short name | T2090 |
| Test name | |
| Test status | |
| Simulation time | 4157403938 ps |
| CPU time | 285.86 seconds |
| Started | Aug 13 07:00:23 PM PDT 24 |
| Finished | Aug 13 07:05:09 PM PDT 24 |
| Peak memory | 576560 kb |
| Host | smart-6b37ecf6-c341-4f3d-bc51-f0c38f8bac1d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2015473375 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 92.xbar_stress_al l_with_reset_error.2015473375 |
| Directory | /workspace/92.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/92.xbar_unmapped_addr.3945654758 |
| Short name | T2548 |
| Test name | |
| Test status | |
| Simulation time | 33625419 ps |
| CPU time | 6.44 seconds |
| Started | Aug 13 07:00:17 PM PDT 24 |
| Finished | Aug 13 07:00:23 PM PDT 24 |
| Peak memory | 573656 kb |
| Host | smart-7860ec20-c164-4d98-acfe-c1d54d71b11f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3945654758 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 92.xbar_unmapped_addr.3945654758 |
| Directory | /workspace/92.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/93.xbar_access_same_device.2161208713 |
| Short name | T2212 |
| Test name | |
| Test status | |
| Simulation time | 618222760 ps |
| CPU time | 43.97 seconds |
| Started | Aug 13 07:00:23 PM PDT 24 |
| Finished | Aug 13 07:01:07 PM PDT 24 |
| Peak memory | 575672 kb |
| Host | smart-042c8fe5-cb15-49b5-bdbb-d982054d680d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2161208713 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 93.xbar_access_same_device .2161208713 |
| Directory | /workspace/93.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/93.xbar_error_and_unmapped_addr.290957391 |
| Short name | T1522 |
| Test name | |
| Test status | |
| Simulation time | 1419114691 ps |
| CPU time | 58.78 seconds |
| Started | Aug 13 07:00:34 PM PDT 24 |
| Finished | Aug 13 07:01:33 PM PDT 24 |
| Peak memory | 575684 kb |
| Host | smart-8980cf39-9aaa-402e-af48-b3a13809e38d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=290957391 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 93.xbar_error_and_unmapped_addr .290957391 |
| Directory | /workspace/93.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/93.xbar_error_random.1112043526 |
| Short name | T1912 |
| Test name | |
| Test status | |
| Simulation time | 76060093 ps |
| CPU time | 8.58 seconds |
| Started | Aug 13 07:00:30 PM PDT 24 |
| Finished | Aug 13 07:00:39 PM PDT 24 |
| Peak memory | 575432 kb |
| Host | smart-4d7bddac-be22-46b5-add6-34280a1ecdd9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1112043526 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 93.xbar_error_random.1112043526 |
| Directory | /workspace/93.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/93.xbar_random.1431418463 |
| Short name | T2364 |
| Test name | |
| Test status | |
| Simulation time | 995892636 ps |
| CPU time | 33.61 seconds |
| Started | Aug 13 07:00:29 PM PDT 24 |
| Finished | Aug 13 07:01:03 PM PDT 24 |
| Peak memory | 575492 kb |
| Host | smart-66d6a7b7-7c15-4fbd-9414-02108765b462 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1431418463 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 93.xbar_random.1431418463 |
| Directory | /workspace/93.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/93.xbar_random_large_delays.541003292 |
| Short name | T2658 |
| Test name | |
| Test status | |
| Simulation time | 83425800566 ps |
| CPU time | 948.37 seconds |
| Started | Aug 13 07:00:24 PM PDT 24 |
| Finished | Aug 13 07:16:12 PM PDT 24 |
| Peak memory | 575732 kb |
| Host | smart-ef8dbdd8-f4b2-4cee-94fe-f8fedafb3652 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=541003292 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 93.xbar_random_large_delays.541003292 |
| Directory | /workspace/93.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/93.xbar_random_slow_rsp.2768661574 |
| Short name | T2354 |
| Test name | |
| Test status | |
| Simulation time | 43329946272 ps |
| CPU time | 774.84 seconds |
| Started | Aug 13 07:00:23 PM PDT 24 |
| Finished | Aug 13 07:13:18 PM PDT 24 |
| Peak memory | 575784 kb |
| Host | smart-83f124f8-5df8-4538-a71e-4f8dd842f8b6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2768661574 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 93.xbar_random_slow_rsp.2768661574 |
| Directory | /workspace/93.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/93.xbar_random_zero_delays.3813526542 |
| Short name | T2810 |
| Test name | |
| Test status | |
| Simulation time | 97654163 ps |
| CPU time | 11 seconds |
| Started | Aug 13 07:00:25 PM PDT 24 |
| Finished | Aug 13 07:00:36 PM PDT 24 |
| Peak memory | 575516 kb |
| Host | smart-ea5a66e6-4488-4109-a7a9-5405ebf6e782 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3813526542 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 93.xbar_random_zero_del ays.3813526542 |
| Directory | /workspace/93.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/93.xbar_same_source.1910739465 |
| Short name | T2864 |
| Test name | |
| Test status | |
| Simulation time | 2115675203 ps |
| CPU time | 64.25 seconds |
| Started | Aug 13 07:00:23 PM PDT 24 |
| Finished | Aug 13 07:01:27 PM PDT 24 |
| Peak memory | 575504 kb |
| Host | smart-d82fee1f-7844-4bd7-a650-19df167e4c92 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1910739465 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 93.xbar_same_source.1910739465 |
| Directory | /workspace/93.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/93.xbar_smoke.520149754 |
| Short name | T2890 |
| Test name | |
| Test status | |
| Simulation time | 162516677 ps |
| CPU time | 8.05 seconds |
| Started | Aug 13 07:00:22 PM PDT 24 |
| Finished | Aug 13 07:00:31 PM PDT 24 |
| Peak memory | 574180 kb |
| Host | smart-8ac00400-3225-4cfa-854b-179dd950ef2a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=520149754 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 93.xbar_smoke.520149754 |
| Directory | /workspace/93.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/93.xbar_smoke_large_delays.935022907 |
| Short name | T1523 |
| Test name | |
| Test status | |
| Simulation time | 7451291907 ps |
| CPU time | 77.32 seconds |
| Started | Aug 13 07:00:22 PM PDT 24 |
| Finished | Aug 13 07:01:39 PM PDT 24 |
| Peak memory | 573524 kb |
| Host | smart-b890e94d-a4b7-4bb6-9bf8-22dacab6e26f |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=935022907 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 93.xbar_smoke_large_delays.935022907 |
| Directory | /workspace/93.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/93.xbar_smoke_slow_rsp.2966481435 |
| Short name | T2558 |
| Test name | |
| Test status | |
| Simulation time | 3920474892 ps |
| CPU time | 71.04 seconds |
| Started | Aug 13 07:00:23 PM PDT 24 |
| Finished | Aug 13 07:01:34 PM PDT 24 |
| Peak memory | 574276 kb |
| Host | smart-ec160ea8-ea0c-4543-b156-0cf2444f2375 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2966481435 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 93.xbar_smoke_slow_rsp.2966481435 |
| Directory | /workspace/93.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/93.xbar_smoke_zero_delays.152754016 |
| Short name | T1549 |
| Test name | |
| Test status | |
| Simulation time | 45547357 ps |
| CPU time | 6.25 seconds |
| Started | Aug 13 07:00:23 PM PDT 24 |
| Finished | Aug 13 07:00:30 PM PDT 24 |
| Peak memory | 573488 kb |
| Host | smart-fbe5eb50-54bb-40c6-aea5-e49cafd00433 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=152754016 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 93.xbar_smoke_zero_delays .152754016 |
| Directory | /workspace/93.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/93.xbar_stress_all.2011793727 |
| Short name | T2534 |
| Test name | |
| Test status | |
| Simulation time | 2310403241 ps |
| CPU time | 199.8 seconds |
| Started | Aug 13 07:00:34 PM PDT 24 |
| Finished | Aug 13 07:03:54 PM PDT 24 |
| Peak memory | 576560 kb |
| Host | smart-192c14d1-c6f2-45c8-bb49-0762c3e7d5e6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2011793727 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 93.xbar_stress_all.2011793727 |
| Directory | /workspace/93.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/93.xbar_stress_all_with_error.1430406595 |
| Short name | T1590 |
| Test name | |
| Test status | |
| Simulation time | 2543135051 ps |
| CPU time | 172.08 seconds |
| Started | Aug 13 07:00:33 PM PDT 24 |
| Finished | Aug 13 07:03:25 PM PDT 24 |
| Peak memory | 576424 kb |
| Host | smart-2af6c80e-1d26-4b23-8df4-caa99e024fa9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1430406595 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 93.xbar_stress_all_with_error.1430406595 |
| Directory | /workspace/93.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/93.xbar_stress_all_with_rand_reset.3756235853 |
| Short name | T2633 |
| Test name | |
| Test status | |
| Simulation time | 599594501 ps |
| CPU time | 212.2 seconds |
| Started | Aug 13 07:00:33 PM PDT 24 |
| Finished | Aug 13 07:04:06 PM PDT 24 |
| Peak memory | 575644 kb |
| Host | smart-7c9f1cdc-6516-462b-b611-a6978cb40426 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3756235853 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 93.xbar_stress_all _with_rand_reset.3756235853 |
| Directory | /workspace/93.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/93.xbar_stress_all_with_reset_error.4116245372 |
| Short name | T931 |
| Test name | |
| Test status | |
| Simulation time | 100621150 ps |
| CPU time | 16.83 seconds |
| Started | Aug 13 07:00:29 PM PDT 24 |
| Finished | Aug 13 07:00:46 PM PDT 24 |
| Peak memory | 573760 kb |
| Host | smart-e56e789e-0ddc-4b8d-bd9e-0ed92fd65cd8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4116245372 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 93.xbar_stress_al l_with_reset_error.4116245372 |
| Directory | /workspace/93.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/93.xbar_unmapped_addr.2159731721 |
| Short name | T1899 |
| Test name | |
| Test status | |
| Simulation time | 762130262 ps |
| CPU time | 30.64 seconds |
| Started | Aug 13 07:00:29 PM PDT 24 |
| Finished | Aug 13 07:01:00 PM PDT 24 |
| Peak memory | 575668 kb |
| Host | smart-9fcc9c20-2d48-4235-9203-175d230439cd |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2159731721 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 93.xbar_unmapped_addr.2159731721 |
| Directory | /workspace/93.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/94.xbar_access_same_device.1655898843 |
| Short name | T2802 |
| Test name | |
| Test status | |
| Simulation time | 370271158 ps |
| CPU time | 34.93 seconds |
| Started | Aug 13 07:00:44 PM PDT 24 |
| Finished | Aug 13 07:01:19 PM PDT 24 |
| Peak memory | 575660 kb |
| Host | smart-588b71ee-bc18-4b09-806c-3d8ddc0fd261 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1655898843 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 94.xbar_access_same_device .1655898843 |
| Directory | /workspace/94.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/94.xbar_access_same_device_slow_rsp.1974023853 |
| Short name | T2172 |
| Test name | |
| Test status | |
| Simulation time | 84922051763 ps |
| CPU time | 1501.74 seconds |
| Started | Aug 13 07:00:41 PM PDT 24 |
| Finished | Aug 13 07:25:43 PM PDT 24 |
| Peak memory | 575672 kb |
| Host | smart-7be6bae9-32d8-42a3-8ba4-d3855f33e18f |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1974023853 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 94.xbar_access_same_ device_slow_rsp.1974023853 |
| Directory | /workspace/94.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/94.xbar_error_and_unmapped_addr.327506813 |
| Short name | T2281 |
| Test name | |
| Test status | |
| Simulation time | 726288301 ps |
| CPU time | 34.25 seconds |
| Started | Aug 13 07:00:41 PM PDT 24 |
| Finished | Aug 13 07:01:15 PM PDT 24 |
| Peak memory | 575676 kb |
| Host | smart-c6923492-a66e-4de4-85ad-20b8a7c7b999 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=327506813 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 94.xbar_error_and_unmapped_addr .327506813 |
| Directory | /workspace/94.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/94.xbar_error_random.389265159 |
| Short name | T1478 |
| Test name | |
| Test status | |
| Simulation time | 402879973 ps |
| CPU time | 30.68 seconds |
| Started | Aug 13 07:00:38 PM PDT 24 |
| Finished | Aug 13 07:01:09 PM PDT 24 |
| Peak memory | 575688 kb |
| Host | smart-ee2e3a66-1056-42fc-8a9c-0d0ee107a344 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=389265159 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 94.xbar_error_random.389265159 |
| Directory | /workspace/94.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/94.xbar_random.125142573 |
| Short name | T2078 |
| Test name | |
| Test status | |
| Simulation time | 42213939 ps |
| CPU time | 6.41 seconds |
| Started | Aug 13 07:00:30 PM PDT 24 |
| Finished | Aug 13 07:00:36 PM PDT 24 |
| Peak memory | 573600 kb |
| Host | smart-0332420c-8d79-4014-8aa4-f3651c500085 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=125142573 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 94.xbar_random.125142573 |
| Directory | /workspace/94.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/94.xbar_random_large_delays.3165698607 |
| Short name | T1830 |
| Test name | |
| Test status | |
| Simulation time | 88823697315 ps |
| CPU time | 1014.65 seconds |
| Started | Aug 13 07:00:38 PM PDT 24 |
| Finished | Aug 13 07:17:33 PM PDT 24 |
| Peak memory | 575780 kb |
| Host | smart-f00c4423-5843-4f94-a7c9-278578ef8600 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3165698607 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 94.xbar_random_large_delays.3165698607 |
| Directory | /workspace/94.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/94.xbar_random_slow_rsp.169137941 |
| Short name | T542 |
| Test name | |
| Test status | |
| Simulation time | 23246151430 ps |
| CPU time | 416.26 seconds |
| Started | Aug 13 07:00:38 PM PDT 24 |
| Finished | Aug 13 07:07:35 PM PDT 24 |
| Peak memory | 575736 kb |
| Host | smart-773675a2-4c32-4b61-bc79-f1918b8e473c |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=169137941 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 94.xbar_random_slow_rsp.169137941 |
| Directory | /workspace/94.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/94.xbar_random_zero_delays.399532238 |
| Short name | T2222 |
| Test name | |
| Test status | |
| Simulation time | 409486012 ps |
| CPU time | 33.74 seconds |
| Started | Aug 13 07:00:30 PM PDT 24 |
| Finished | Aug 13 07:01:04 PM PDT 24 |
| Peak memory | 575496 kb |
| Host | smart-84ce333b-b36e-4052-9d16-59b6567eac32 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=399532238 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 94.xbar_random_zero_dela ys.399532238 |
| Directory | /workspace/94.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/94.xbar_same_source.3239261954 |
| Short name | T2151 |
| Test name | |
| Test status | |
| Simulation time | 476702274 ps |
| CPU time | 36.82 seconds |
| Started | Aug 13 07:00:40 PM PDT 24 |
| Finished | Aug 13 07:01:16 PM PDT 24 |
| Peak memory | 575616 kb |
| Host | smart-4b79eb80-368b-4595-8947-bc81cd154829 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3239261954 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 94.xbar_same_source.3239261954 |
| Directory | /workspace/94.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/94.xbar_smoke.2707272008 |
| Short name | T1751 |
| Test name | |
| Test status | |
| Simulation time | 46121417 ps |
| CPU time | 6.21 seconds |
| Started | Aug 13 07:00:29 PM PDT 24 |
| Finished | Aug 13 07:00:35 PM PDT 24 |
| Peak memory | 573532 kb |
| Host | smart-910c564a-281f-474a-a902-af98dfd28641 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2707272008 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 94.xbar_smoke.2707272008 |
| Directory | /workspace/94.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/94.xbar_smoke_large_delays.701198699 |
| Short name | T2457 |
| Test name | |
| Test status | |
| Simulation time | 9528169894 ps |
| CPU time | 96.6 seconds |
| Started | Aug 13 07:00:30 PM PDT 24 |
| Finished | Aug 13 07:02:07 PM PDT 24 |
| Peak memory | 574292 kb |
| Host | smart-7bb49687-0b2f-46c6-9b0b-ed3ebcc3052f |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=701198699 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 94.xbar_smoke_large_delays.701198699 |
| Directory | /workspace/94.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/94.xbar_smoke_slow_rsp.3057532534 |
| Short name | T1880 |
| Test name | |
| Test status | |
| Simulation time | 5327281638 ps |
| CPU time | 88.21 seconds |
| Started | Aug 13 07:00:28 PM PDT 24 |
| Finished | Aug 13 07:01:57 PM PDT 24 |
| Peak memory | 573568 kb |
| Host | smart-ca64cdbf-cced-4950-aa89-b26da4c54c46 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3057532534 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 94.xbar_smoke_slow_rsp.3057532534 |
| Directory | /workspace/94.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/94.xbar_smoke_zero_delays.2208556366 |
| Short name | T1520 |
| Test name | |
| Test status | |
| Simulation time | 36204171 ps |
| CPU time | 6.1 seconds |
| Started | Aug 13 07:00:31 PM PDT 24 |
| Finished | Aug 13 07:00:38 PM PDT 24 |
| Peak memory | 573484 kb |
| Host | smart-cb5fbf89-aa42-4c04-9f52-5ab35ce86ec1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2208556366 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 94.xbar_smoke_zero_delay s.2208556366 |
| Directory | /workspace/94.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/94.xbar_stress_all.1793423612 |
| Short name | T2672 |
| Test name | |
| Test status | |
| Simulation time | 2841120816 ps |
| CPU time | 234.6 seconds |
| Started | Aug 13 07:00:39 PM PDT 24 |
| Finished | Aug 13 07:04:34 PM PDT 24 |
| Peak memory | 575756 kb |
| Host | smart-be21249b-897e-4f49-9198-ab7691d1063e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1793423612 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 94.xbar_stress_all.1793423612 |
| Directory | /workspace/94.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/94.xbar_stress_all_with_error.2604263196 |
| Short name | T2245 |
| Test name | |
| Test status | |
| Simulation time | 2334407113 ps |
| CPU time | 198.75 seconds |
| Started | Aug 13 07:00:38 PM PDT 24 |
| Finished | Aug 13 07:03:57 PM PDT 24 |
| Peak memory | 576540 kb |
| Host | smart-7c8f03b2-cffa-4e21-8a07-fd586c791198 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2604263196 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 94.xbar_stress_all_with_error.2604263196 |
| Directory | /workspace/94.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/94.xbar_stress_all_with_rand_reset.656024259 |
| Short name | T2320 |
| Test name | |
| Test status | |
| Simulation time | 11061686728 ps |
| CPU time | 644.24 seconds |
| Started | Aug 13 07:00:40 PM PDT 24 |
| Finished | Aug 13 07:11:25 PM PDT 24 |
| Peak memory | 575664 kb |
| Host | smart-f8c6345f-f832-45d1-9670-3f52416a9045 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=656024259 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_res et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 94.xbar_stress_all_ with_rand_reset.656024259 |
| Directory | /workspace/94.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/94.xbar_stress_all_with_reset_error.369185605 |
| Short name | T2032 |
| Test name | |
| Test status | |
| Simulation time | 8588283968 ps |
| CPU time | 394.26 seconds |
| Started | Aug 13 07:00:39 PM PDT 24 |
| Finished | Aug 13 07:07:13 PM PDT 24 |
| Peak memory | 576544 kb |
| Host | smart-138e62f5-37ad-4664-93e5-9dd83500dff0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=369185605 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 94.xbar_stress_all _with_reset_error.369185605 |
| Directory | /workspace/94.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/94.xbar_unmapped_addr.1112949139 |
| Short name | T2185 |
| Test name | |
| Test status | |
| Simulation time | 424677349 ps |
| CPU time | 20.96 seconds |
| Started | Aug 13 07:00:39 PM PDT 24 |
| Finished | Aug 13 07:01:00 PM PDT 24 |
| Peak memory | 575720 kb |
| Host | smart-d7fcde74-7654-440f-99d1-869d1d297460 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1112949139 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 94.xbar_unmapped_addr.1112949139 |
| Directory | /workspace/94.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/95.xbar_access_same_device.2937504440 |
| Short name | T2362 |
| Test name | |
| Test status | |
| Simulation time | 2947581500 ps |
| CPU time | 118.16 seconds |
| Started | Aug 13 07:00:45 PM PDT 24 |
| Finished | Aug 13 07:02:43 PM PDT 24 |
| Peak memory | 575712 kb |
| Host | smart-cec8528c-22ad-489e-a671-f391a2511d7b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2937504440 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 95.xbar_access_same_device .2937504440 |
| Directory | /workspace/95.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/95.xbar_access_same_device_slow_rsp.2289025977 |
| Short name | T2749 |
| Test name | |
| Test status | |
| Simulation time | 104074172851 ps |
| CPU time | 1854.2 seconds |
| Started | Aug 13 07:00:46 PM PDT 24 |
| Finished | Aug 13 07:31:40 PM PDT 24 |
| Peak memory | 575860 kb |
| Host | smart-0755bf62-1d23-4d1e-a2cc-4e6c59aeee51 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2289025977 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 95.xbar_access_same_ device_slow_rsp.2289025977 |
| Directory | /workspace/95.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/95.xbar_error_and_unmapped_addr.2177668018 |
| Short name | T1451 |
| Test name | |
| Test status | |
| Simulation time | 1382825752 ps |
| CPU time | 55.34 seconds |
| Started | Aug 13 07:00:47 PM PDT 24 |
| Finished | Aug 13 07:01:43 PM PDT 24 |
| Peak memory | 575700 kb |
| Host | smart-a606d8d5-b56c-4ffb-aa45-69547be93821 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2177668018 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 95.xbar_error_and_unmapped_add r.2177668018 |
| Directory | /workspace/95.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/95.xbar_error_random.3690730811 |
| Short name | T1477 |
| Test name | |
| Test status | |
| Simulation time | 2225122875 ps |
| CPU time | 64.3 seconds |
| Started | Aug 13 07:00:45 PM PDT 24 |
| Finished | Aug 13 07:01:49 PM PDT 24 |
| Peak memory | 575744 kb |
| Host | smart-d7898354-866b-4a11-98a0-8262df09bb22 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3690730811 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 95.xbar_error_random.3690730811 |
| Directory | /workspace/95.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/95.xbar_random.2542184134 |
| Short name | T580 |
| Test name | |
| Test status | |
| Simulation time | 354456138 ps |
| CPU time | 31.81 seconds |
| Started | Aug 13 07:00:48 PM PDT 24 |
| Finished | Aug 13 07:01:20 PM PDT 24 |
| Peak memory | 575492 kb |
| Host | smart-025ec7f6-5e80-41ea-b5d2-a66b9c106262 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2542184134 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 95.xbar_random.2542184134 |
| Directory | /workspace/95.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/95.xbar_random_large_delays.136802052 |
| Short name | T659 |
| Test name | |
| Test status | |
| Simulation time | 122636091168 ps |
| CPU time | 1284.5 seconds |
| Started | Aug 13 07:00:47 PM PDT 24 |
| Finished | Aug 13 07:22:11 PM PDT 24 |
| Peak memory | 575812 kb |
| Host | smart-c90d91e4-66a2-42c1-bd99-7432f0515906 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=136802052 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 95.xbar_random_large_delays.136802052 |
| Directory | /workspace/95.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/95.xbar_random_slow_rsp.813916416 |
| Short name | T1745 |
| Test name | |
| Test status | |
| Simulation time | 52311761297 ps |
| CPU time | 984.39 seconds |
| Started | Aug 13 07:00:44 PM PDT 24 |
| Finished | Aug 13 07:17:09 PM PDT 24 |
| Peak memory | 575604 kb |
| Host | smart-d927f5a1-d46b-49fc-93e6-7016a5c25141 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=813916416 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 95.xbar_random_slow_rsp.813916416 |
| Directory | /workspace/95.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/95.xbar_random_zero_delays.258506844 |
| Short name | T1800 |
| Test name | |
| Test status | |
| Simulation time | 170713082 ps |
| CPU time | 15.11 seconds |
| Started | Aug 13 07:00:45 PM PDT 24 |
| Finished | Aug 13 07:01:00 PM PDT 24 |
| Peak memory | 575652 kb |
| Host | smart-5d72befd-c49e-4eba-9dfa-efc203f94da4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=258506844 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 95.xbar_random_zero_dela ys.258506844 |
| Directory | /workspace/95.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/95.xbar_same_source.1556731568 |
| Short name | T2668 |
| Test name | |
| Test status | |
| Simulation time | 989520991 ps |
| CPU time | 27.99 seconds |
| Started | Aug 13 07:00:45 PM PDT 24 |
| Finished | Aug 13 07:01:13 PM PDT 24 |
| Peak memory | 575520 kb |
| Host | smart-5fbadb95-31f4-4ec4-a31d-1f9ed331c360 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1556731568 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 95.xbar_same_source.1556731568 |
| Directory | /workspace/95.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/95.xbar_smoke.1913061744 |
| Short name | T2008 |
| Test name | |
| Test status | |
| Simulation time | 164186362 ps |
| CPU time | 8.58 seconds |
| Started | Aug 13 07:00:37 PM PDT 24 |
| Finished | Aug 13 07:00:46 PM PDT 24 |
| Peak memory | 574248 kb |
| Host | smart-94392b30-71ff-4e8c-97ea-ad42669e13b6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1913061744 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 95.xbar_smoke.1913061744 |
| Directory | /workspace/95.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/95.xbar_smoke_large_delays.2483179864 |
| Short name | T2480 |
| Test name | |
| Test status | |
| Simulation time | 8509450975 ps |
| CPU time | 93.27 seconds |
| Started | Aug 13 07:00:38 PM PDT 24 |
| Finished | Aug 13 07:02:11 PM PDT 24 |
| Peak memory | 574340 kb |
| Host | smart-48049746-578f-4ef4-9704-906847e1bdcb |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2483179864 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 95.xbar_smoke_large_delays.2483179864 |
| Directory | /workspace/95.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/95.xbar_smoke_slow_rsp.3360841153 |
| Short name | T1556 |
| Test name | |
| Test status | |
| Simulation time | 4221463665 ps |
| CPU time | 69.38 seconds |
| Started | Aug 13 07:00:46 PM PDT 24 |
| Finished | Aug 13 07:01:56 PM PDT 24 |
| Peak memory | 573636 kb |
| Host | smart-3b283d1a-fdc2-4280-885a-71da8b3520f4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3360841153 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 95.xbar_smoke_slow_rsp.3360841153 |
| Directory | /workspace/95.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/95.xbar_smoke_zero_delays.3522650501 |
| Short name | T2192 |
| Test name | |
| Test status | |
| Simulation time | 44205563 ps |
| CPU time | 5.78 seconds |
| Started | Aug 13 07:00:41 PM PDT 24 |
| Finished | Aug 13 07:00:47 PM PDT 24 |
| Peak memory | 573536 kb |
| Host | smart-4d388af7-dbae-4fcf-b0f4-095b29eaf99d |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3522650501 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 95.xbar_smoke_zero_delay s.3522650501 |
| Directory | /workspace/95.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/95.xbar_stress_all.764846246 |
| Short name | T2883 |
| Test name | |
| Test status | |
| Simulation time | 3915637708 ps |
| CPU time | 132.35 seconds |
| Started | Aug 13 07:00:45 PM PDT 24 |
| Finished | Aug 13 07:02:58 PM PDT 24 |
| Peak memory | 575856 kb |
| Host | smart-452b0d75-5832-4bf3-9250-9d8a479019ed |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=764846246 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 95.xbar_stress_all.764846246 |
| Directory | /workspace/95.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/95.xbar_stress_all_with_error.2713350178 |
| Short name | T2011 |
| Test name | |
| Test status | |
| Simulation time | 2317806138 ps |
| CPU time | 215.99 seconds |
| Started | Aug 13 07:00:45 PM PDT 24 |
| Finished | Aug 13 07:04:21 PM PDT 24 |
| Peak memory | 576564 kb |
| Host | smart-d41b426b-48e3-41bc-b8f3-df89e84567f6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2713350178 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 95.xbar_stress_all_with_error.2713350178 |
| Directory | /workspace/95.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/95.xbar_stress_all_with_rand_reset.1369850035 |
| Short name | T1858 |
| Test name | |
| Test status | |
| Simulation time | 4908071919 ps |
| CPU time | 739.15 seconds |
| Started | Aug 13 07:00:47 PM PDT 24 |
| Finished | Aug 13 07:13:07 PM PDT 24 |
| Peak memory | 575692 kb |
| Host | smart-6c2d0e59-0ae7-412d-8403-1bc991bb75ab |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1369850035 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 95.xbar_stress_all _with_rand_reset.1369850035 |
| Directory | /workspace/95.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/95.xbar_stress_all_with_reset_error.1127739669 |
| Short name | T1802 |
| Test name | |
| Test status | |
| Simulation time | 6769760227 ps |
| CPU time | 394.58 seconds |
| Started | Aug 13 07:00:43 PM PDT 24 |
| Finished | Aug 13 07:07:18 PM PDT 24 |
| Peak memory | 575740 kb |
| Host | smart-48ed7553-7365-44fa-a3d5-404d2461ac9d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1127739669 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 95.xbar_stress_al l_with_reset_error.1127739669 |
| Directory | /workspace/95.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/95.xbar_unmapped_addr.699449747 |
| Short name | T1512 |
| Test name | |
| Test status | |
| Simulation time | 237565732 ps |
| CPU time | 11.39 seconds |
| Started | Aug 13 07:00:48 PM PDT 24 |
| Finished | Aug 13 07:01:00 PM PDT 24 |
| Peak memory | 575664 kb |
| Host | smart-38151e84-ef65-4e5c-bec5-ee35c2d452ab |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=699449747 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 95.xbar_unmapped_addr.699449747 |
| Directory | /workspace/95.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/96.xbar_access_same_device.169493739 |
| Short name | T1569 |
| Test name | |
| Test status | |
| Simulation time | 2427044485 ps |
| CPU time | 100.28 seconds |
| Started | Aug 13 07:00:53 PM PDT 24 |
| Finished | Aug 13 07:02:34 PM PDT 24 |
| Peak memory | 575768 kb |
| Host | smart-33f985b9-3543-4a96-beec-fdbf7ccf99bd |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=169493739 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 96.xbar_access_same_device. 169493739 |
| Directory | /workspace/96.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/96.xbar_error_and_unmapped_addr.3501803187 |
| Short name | T1622 |
| Test name | |
| Test status | |
| Simulation time | 583927364 ps |
| CPU time | 23.31 seconds |
| Started | Aug 13 07:00:52 PM PDT 24 |
| Finished | Aug 13 07:01:15 PM PDT 24 |
| Peak memory | 575736 kb |
| Host | smart-5adf6918-bff9-4013-94ac-b89181e36e32 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3501803187 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 96.xbar_error_and_unmapped_add r.3501803187 |
| Directory | /workspace/96.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/96.xbar_error_random.2678670458 |
| Short name | T1629 |
| Test name | |
| Test status | |
| Simulation time | 2178370110 ps |
| CPU time | 64.16 seconds |
| Started | Aug 13 07:00:54 PM PDT 24 |
| Finished | Aug 13 07:01:59 PM PDT 24 |
| Peak memory | 575512 kb |
| Host | smart-ae3595ec-5935-42f8-9b96-b94ff7c2ce73 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2678670458 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 96.xbar_error_random.2678670458 |
| Directory | /workspace/96.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/96.xbar_random.832774410 |
| Short name | T2774 |
| Test name | |
| Test status | |
| Simulation time | 272761252 ps |
| CPU time | 12.14 seconds |
| Started | Aug 13 07:00:45 PM PDT 24 |
| Finished | Aug 13 07:00:57 PM PDT 24 |
| Peak memory | 575696 kb |
| Host | smart-d17eda11-e33c-48d9-b320-3f23d247bc44 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=832774410 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 96.xbar_random.832774410 |
| Directory | /workspace/96.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/96.xbar_random_large_delays.2845458909 |
| Short name | T596 |
| Test name | |
| Test status | |
| Simulation time | 94966350344 ps |
| CPU time | 1083.32 seconds |
| Started | Aug 13 07:00:55 PM PDT 24 |
| Finished | Aug 13 07:18:58 PM PDT 24 |
| Peak memory | 575692 kb |
| Host | smart-5d37ca99-4d93-43c8-a24b-35000b8f9fea |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2845458909 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 96.xbar_random_large_delays.2845458909 |
| Directory | /workspace/96.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/96.xbar_random_slow_rsp.2867529548 |
| Short name | T626 |
| Test name | |
| Test status | |
| Simulation time | 11481522575 ps |
| CPU time | 202.65 seconds |
| Started | Aug 13 07:00:52 PM PDT 24 |
| Finished | Aug 13 07:04:15 PM PDT 24 |
| Peak memory | 575580 kb |
| Host | smart-a5211a17-9498-4749-8cc6-d32413e4e17d |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2867529548 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 96.xbar_random_slow_rsp.2867529548 |
| Directory | /workspace/96.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/96.xbar_random_zero_delays.2585013347 |
| Short name | T2403 |
| Test name | |
| Test status | |
| Simulation time | 104362919 ps |
| CPU time | 11.42 seconds |
| Started | Aug 13 07:00:45 PM PDT 24 |
| Finished | Aug 13 07:00:56 PM PDT 24 |
| Peak memory | 575664 kb |
| Host | smart-082a69a4-4cb0-4370-995f-863f28ba718d |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2585013347 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 96.xbar_random_zero_del ays.2585013347 |
| Directory | /workspace/96.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/96.xbar_same_source.4108472462 |
| Short name | T2284 |
| Test name | |
| Test status | |
| Simulation time | 943073626 ps |
| CPU time | 29.28 seconds |
| Started | Aug 13 07:00:51 PM PDT 24 |
| Finished | Aug 13 07:01:21 PM PDT 24 |
| Peak memory | 575672 kb |
| Host | smart-41f65cbb-b4b8-4bd8-a52a-dc578ff568c8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4108472462 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 96.xbar_same_source.4108472462 |
| Directory | /workspace/96.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/96.xbar_smoke.958782068 |
| Short name | T1869 |
| Test name | |
| Test status | |
| Simulation time | 40941538 ps |
| CPU time | 6.06 seconds |
| Started | Aug 13 07:00:44 PM PDT 24 |
| Finished | Aug 13 07:00:51 PM PDT 24 |
| Peak memory | 573492 kb |
| Host | smart-0591f62c-699e-4e5e-a4dc-f8ef6f5778a7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=958782068 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 96.xbar_smoke.958782068 |
| Directory | /workspace/96.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/96.xbar_smoke_large_delays.3971746633 |
| Short name | T2918 |
| Test name | |
| Test status | |
| Simulation time | 10316457424 ps |
| CPU time | 109.45 seconds |
| Started | Aug 13 07:00:44 PM PDT 24 |
| Finished | Aug 13 07:02:34 PM PDT 24 |
| Peak memory | 573544 kb |
| Host | smart-916e4a68-e5ad-4f3e-a809-da06b8e2fa06 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3971746633 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 96.xbar_smoke_large_delays.3971746633 |
| Directory | /workspace/96.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/96.xbar_smoke_slow_rsp.3741114448 |
| Short name | T1542 |
| Test name | |
| Test status | |
| Simulation time | 4098313870 ps |
| CPU time | 68.45 seconds |
| Started | Aug 13 07:00:46 PM PDT 24 |
| Finished | Aug 13 07:01:55 PM PDT 24 |
| Peak memory | 573572 kb |
| Host | smart-645ab87d-46be-454c-8c46-67d84c1bf9f4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3741114448 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 96.xbar_smoke_slow_rsp.3741114448 |
| Directory | /workspace/96.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/96.xbar_smoke_zero_delays.127717882 |
| Short name | T2045 |
| Test name | |
| Test status | |
| Simulation time | 41938645 ps |
| CPU time | 6.15 seconds |
| Started | Aug 13 07:00:45 PM PDT 24 |
| Finished | Aug 13 07:00:51 PM PDT 24 |
| Peak memory | 574192 kb |
| Host | smart-f1544b9d-46a8-49a1-b772-cc1d3ff7073d |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=127717882 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 96.xbar_smoke_zero_delays .127717882 |
| Directory | /workspace/96.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/96.xbar_stress_all.3316148575 |
| Short name | T598 |
| Test name | |
| Test status | |
| Simulation time | 3658855290 ps |
| CPU time | 287.18 seconds |
| Started | Aug 13 07:00:53 PM PDT 24 |
| Finished | Aug 13 07:05:41 PM PDT 24 |
| Peak memory | 575748 kb |
| Host | smart-6be4d98d-f9a0-4a93-8d85-5109083ccc7d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3316148575 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 96.xbar_stress_all.3316148575 |
| Directory | /workspace/96.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/96.xbar_stress_all_with_error.534967954 |
| Short name | T884 |
| Test name | |
| Test status | |
| Simulation time | 19007850130 ps |
| CPU time | 675.9 seconds |
| Started | Aug 13 07:00:51 PM PDT 24 |
| Finished | Aug 13 07:12:07 PM PDT 24 |
| Peak memory | 576556 kb |
| Host | smart-873089e8-0588-4aa0-b756-bff100b67c5c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=534967954 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 96.xbar_stress_all_with_error.534967954 |
| Directory | /workspace/96.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/96.xbar_stress_all_with_rand_reset.1750753368 |
| Short name | T918 |
| Test name | |
| Test status | |
| Simulation time | 373946558 ps |
| CPU time | 144.91 seconds |
| Started | Aug 13 07:00:53 PM PDT 24 |
| Finished | Aug 13 07:03:18 PM PDT 24 |
| Peak memory | 576512 kb |
| Host | smart-ce51d22d-4774-4b4b-aeae-de4ddaf215f8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1750753368 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 96.xbar_stress_all _with_rand_reset.1750753368 |
| Directory | /workspace/96.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/96.xbar_stress_all_with_reset_error.156523642 |
| Short name | T2708 |
| Test name | |
| Test status | |
| Simulation time | 2875840930 ps |
| CPU time | 262.99 seconds |
| Started | Aug 13 07:00:53 PM PDT 24 |
| Finished | Aug 13 07:05:16 PM PDT 24 |
| Peak memory | 575640 kb |
| Host | smart-6b48a953-abfa-4860-98e2-8bbef65c02cd |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=156523642 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 96.xbar_stress_all _with_reset_error.156523642 |
| Directory | /workspace/96.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/96.xbar_unmapped_addr.1325648847 |
| Short name | T1854 |
| Test name | |
| Test status | |
| Simulation time | 518927069 ps |
| CPU time | 24.18 seconds |
| Started | Aug 13 07:00:55 PM PDT 24 |
| Finished | Aug 13 07:01:19 PM PDT 24 |
| Peak memory | 575632 kb |
| Host | smart-0e03e5d0-1348-4027-9a93-bbbb20d5328d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1325648847 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 96.xbar_unmapped_addr.1325648847 |
| Directory | /workspace/96.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/97.xbar_access_same_device.2744387119 |
| Short name | T2629 |
| Test name | |
| Test status | |
| Simulation time | 1330936892 ps |
| CPU time | 46.36 seconds |
| Started | Aug 13 07:01:03 PM PDT 24 |
| Finished | Aug 13 07:01:49 PM PDT 24 |
| Peak memory | 575676 kb |
| Host | smart-2dfafeb3-42b5-4be6-bff4-0886b50e0de9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2744387119 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 97.xbar_access_same_device .2744387119 |
| Directory | /workspace/97.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/97.xbar_access_same_device_slow_rsp.1225013958 |
| Short name | T2316 |
| Test name | |
| Test status | |
| Simulation time | 87326313524 ps |
| CPU time | 1755.72 seconds |
| Started | Aug 13 07:01:01 PM PDT 24 |
| Finished | Aug 13 07:30:17 PM PDT 24 |
| Peak memory | 575608 kb |
| Host | smart-814ddd8f-6950-460d-b660-84128db09bc7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1225013958 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 97.xbar_access_same_ device_slow_rsp.1225013958 |
| Directory | /workspace/97.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/97.xbar_error_and_unmapped_addr.2070057506 |
| Short name | T1667 |
| Test name | |
| Test status | |
| Simulation time | 263486308 ps |
| CPU time | 27.88 seconds |
| Started | Aug 13 07:01:02 PM PDT 24 |
| Finished | Aug 13 07:01:30 PM PDT 24 |
| Peak memory | 575508 kb |
| Host | smart-ffd51479-ee2a-4bf6-86f4-814a0c19e8dc |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2070057506 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 97.xbar_error_and_unmapped_add r.2070057506 |
| Directory | /workspace/97.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/97.xbar_error_random.1001264283 |
| Short name | T2152 |
| Test name | |
| Test status | |
| Simulation time | 2119935495 ps |
| CPU time | 72.63 seconds |
| Started | Aug 13 07:00:58 PM PDT 24 |
| Finished | Aug 13 07:02:11 PM PDT 24 |
| Peak memory | 575664 kb |
| Host | smart-e7a63eac-b3d2-408d-aa23-95261679114f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1001264283 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 97.xbar_error_random.1001264283 |
| Directory | /workspace/97.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/97.xbar_random.880032496 |
| Short name | T2474 |
| Test name | |
| Test status | |
| Simulation time | 512579010 ps |
| CPU time | 21.19 seconds |
| Started | Aug 13 07:00:59 PM PDT 24 |
| Finished | Aug 13 07:01:20 PM PDT 24 |
| Peak memory | 575636 kb |
| Host | smart-ebc20a65-dd28-4030-9fa6-e57cc0a4d72b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=880032496 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 97.xbar_random.880032496 |
| Directory | /workspace/97.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/97.xbar_random_large_delays.1474432544 |
| Short name | T475 |
| Test name | |
| Test status | |
| Simulation time | 96647442013 ps |
| CPU time | 1045.01 seconds |
| Started | Aug 13 07:00:59 PM PDT 24 |
| Finished | Aug 13 07:18:24 PM PDT 24 |
| Peak memory | 575716 kb |
| Host | smart-6720c65f-9b01-41fa-a5ed-63357c224dcb |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1474432544 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 97.xbar_random_large_delays.1474432544 |
| Directory | /workspace/97.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/97.xbar_random_slow_rsp.653473504 |
| Short name | T616 |
| Test name | |
| Test status | |
| Simulation time | 53187035928 ps |
| CPU time | 1015.53 seconds |
| Started | Aug 13 07:01:00 PM PDT 24 |
| Finished | Aug 13 07:17:56 PM PDT 24 |
| Peak memory | 575644 kb |
| Host | smart-9d98207f-6320-4c35-871b-30fd0ec02829 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=653473504 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 97.xbar_random_slow_rsp.653473504 |
| Directory | /workspace/97.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/97.xbar_random_zero_delays.3535642362 |
| Short name | T1769 |
| Test name | |
| Test status | |
| Simulation time | 503580537 ps |
| CPU time | 46.65 seconds |
| Started | Aug 13 07:00:58 PM PDT 24 |
| Finished | Aug 13 07:01:45 PM PDT 24 |
| Peak memory | 575664 kb |
| Host | smart-b4c19e9f-7afa-49df-a07f-d36089854658 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3535642362 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 97.xbar_random_zero_del ays.3535642362 |
| Directory | /workspace/97.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/97.xbar_same_source.1200703336 |
| Short name | T2205 |
| Test name | |
| Test status | |
| Simulation time | 128020444 ps |
| CPU time | 10.82 seconds |
| Started | Aug 13 07:00:59 PM PDT 24 |
| Finished | Aug 13 07:01:10 PM PDT 24 |
| Peak memory | 575420 kb |
| Host | smart-b25206ed-8b1f-41af-935b-0cf47fb11b82 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1200703336 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 97.xbar_same_source.1200703336 |
| Directory | /workspace/97.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/97.xbar_smoke.536909448 |
| Short name | T2018 |
| Test name | |
| Test status | |
| Simulation time | 180077306 ps |
| CPU time | 8.69 seconds |
| Started | Aug 13 07:00:52 PM PDT 24 |
| Finished | Aug 13 07:01:01 PM PDT 24 |
| Peak memory | 574152 kb |
| Host | smart-c2c986f8-dc28-4885-9143-6b1fca7709e3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=536909448 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 97.xbar_smoke.536909448 |
| Directory | /workspace/97.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/97.xbar_smoke_large_delays.3057965234 |
| Short name | T1902 |
| Test name | |
| Test status | |
| Simulation time | 8024374911 ps |
| CPU time | 90.77 seconds |
| Started | Aug 13 07:01:02 PM PDT 24 |
| Finished | Aug 13 07:02:32 PM PDT 24 |
| Peak memory | 574332 kb |
| Host | smart-0256b793-8c13-4252-b806-aa3ff2fb0eca |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3057965234 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 97.xbar_smoke_large_delays.3057965234 |
| Directory | /workspace/97.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/97.xbar_smoke_slow_rsp.3260255147 |
| Short name | T1450 |
| Test name | |
| Test status | |
| Simulation time | 4399720649 ps |
| CPU time | 74.86 seconds |
| Started | Aug 13 07:01:01 PM PDT 24 |
| Finished | Aug 13 07:02:16 PM PDT 24 |
| Peak memory | 574292 kb |
| Host | smart-43d40ab6-d502-497e-b82e-8027989051f4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3260255147 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 97.xbar_smoke_slow_rsp.3260255147 |
| Directory | /workspace/97.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/97.xbar_smoke_zero_delays.2837580657 |
| Short name | T1561 |
| Test name | |
| Test status | |
| Simulation time | 49474831 ps |
| CPU time | 6.56 seconds |
| Started | Aug 13 07:00:52 PM PDT 24 |
| Finished | Aug 13 07:00:58 PM PDT 24 |
| Peak memory | 574236 kb |
| Host | smart-d21f069c-36ba-42cf-8240-155e777daa7a |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2837580657 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 97.xbar_smoke_zero_delay s.2837580657 |
| Directory | /workspace/97.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/97.xbar_stress_all.2929778233 |
| Short name | T2459 |
| Test name | |
| Test status | |
| Simulation time | 3955183062 ps |
| CPU time | 129.6 seconds |
| Started | Aug 13 07:01:00 PM PDT 24 |
| Finished | Aug 13 07:03:09 PM PDT 24 |
| Peak memory | 575812 kb |
| Host | smart-a6732822-c201-4fa3-bf0c-b11ac5960d3c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2929778233 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 97.xbar_stress_all.2929778233 |
| Directory | /workspace/97.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/97.xbar_stress_all_with_error.2186928243 |
| Short name | T2652 |
| Test name | |
| Test status | |
| Simulation time | 9493874732 ps |
| CPU time | 316.13 seconds |
| Started | Aug 13 07:01:02 PM PDT 24 |
| Finished | Aug 13 07:06:18 PM PDT 24 |
| Peak memory | 575732 kb |
| Host | smart-b270a9b7-eb75-496d-9c75-6ee286b4e56f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2186928243 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 97.xbar_stress_all_with_error.2186928243 |
| Directory | /workspace/97.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/97.xbar_stress_all_with_rand_reset.373992207 |
| Short name | T2736 |
| Test name | |
| Test status | |
| Simulation time | 4043037309 ps |
| CPU time | 430.84 seconds |
| Started | Aug 13 07:01:03 PM PDT 24 |
| Finished | Aug 13 07:08:14 PM PDT 24 |
| Peak memory | 575748 kb |
| Host | smart-bdfd41b2-7800-487b-8012-0fee7050c236 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=373992207 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_res et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 97.xbar_stress_all_ with_rand_reset.373992207 |
| Directory | /workspace/97.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/97.xbar_unmapped_addr.2912583305 |
| Short name | T2511 |
| Test name | |
| Test status | |
| Simulation time | 242128865 ps |
| CPU time | 27.32 seconds |
| Started | Aug 13 07:00:58 PM PDT 24 |
| Finished | Aug 13 07:01:26 PM PDT 24 |
| Peak memory | 575584 kb |
| Host | smart-3d52ad65-d6ba-4232-a3da-6b9c59326224 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2912583305 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 97.xbar_unmapped_addr.2912583305 |
| Directory | /workspace/97.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/98.xbar_access_same_device.1713377888 |
| Short name | T2892 |
| Test name | |
| Test status | |
| Simulation time | 1019889868 ps |
| CPU time | 36.44 seconds |
| Started | Aug 13 07:01:12 PM PDT 24 |
| Finished | Aug 13 07:01:49 PM PDT 24 |
| Peak memory | 575608 kb |
| Host | smart-a4c08301-a771-4cfb-8850-be03b3197f77 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1713377888 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 98.xbar_access_same_device .1713377888 |
| Directory | /workspace/98.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/98.xbar_access_same_device_slow_rsp.3446943165 |
| Short name | T865 |
| Test name | |
| Test status | |
| Simulation time | 81118861727 ps |
| CPU time | 1626.15 seconds |
| Started | Aug 13 07:01:11 PM PDT 24 |
| Finished | Aug 13 07:28:18 PM PDT 24 |
| Peak memory | 575716 kb |
| Host | smart-208477a1-5b7f-4963-a24a-cada24981de1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3446943165 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 98.xbar_access_same_ device_slow_rsp.3446943165 |
| Directory | /workspace/98.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/98.xbar_error_and_unmapped_addr.887433546 |
| Short name | T1897 |
| Test name | |
| Test status | |
| Simulation time | 1246812534 ps |
| CPU time | 45.28 seconds |
| Started | Aug 13 07:01:12 PM PDT 24 |
| Finished | Aug 13 07:01:57 PM PDT 24 |
| Peak memory | 575740 kb |
| Host | smart-d2d8f08f-57c5-44cc-be42-233dbe0f3580 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=887433546 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 98.xbar_error_and_unmapped_addr .887433546 |
| Directory | /workspace/98.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/98.xbar_error_random.2721825873 |
| Short name | T2408 |
| Test name | |
| Test status | |
| Simulation time | 1827385852 ps |
| CPU time | 64.15 seconds |
| Started | Aug 13 07:01:12 PM PDT 24 |
| Finished | Aug 13 07:02:16 PM PDT 24 |
| Peak memory | 575632 kb |
| Host | smart-b01c1ef4-209f-48b4-ae40-7ce958d5d823 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2721825873 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 98.xbar_error_random.2721825873 |
| Directory | /workspace/98.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/98.xbar_random.1011246203 |
| Short name | T2302 |
| Test name | |
| Test status | |
| Simulation time | 189895590 ps |
| CPU time | 17.48 seconds |
| Started | Aug 13 07:01:06 PM PDT 24 |
| Finished | Aug 13 07:01:24 PM PDT 24 |
| Peak memory | 575712 kb |
| Host | smart-6f64874a-be79-4f50-aa29-3c5378030baa |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1011246203 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 98.xbar_random.1011246203 |
| Directory | /workspace/98.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/98.xbar_random_large_delays.2577130311 |
| Short name | T2257 |
| Test name | |
| Test status | |
| Simulation time | 70716692648 ps |
| CPU time | 766.69 seconds |
| Started | Aug 13 07:01:05 PM PDT 24 |
| Finished | Aug 13 07:13:52 PM PDT 24 |
| Peak memory | 575600 kb |
| Host | smart-bc20d9fc-1398-40b3-9e32-22cb47011ea3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2577130311 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 98.xbar_random_large_delays.2577130311 |
| Directory | /workspace/98.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/98.xbar_random_slow_rsp.2721795445 |
| Short name | T502 |
| Test name | |
| Test status | |
| Simulation time | 59550893242 ps |
| CPU time | 1077.63 seconds |
| Started | Aug 13 07:01:12 PM PDT 24 |
| Finished | Aug 13 07:19:10 PM PDT 24 |
| Peak memory | 575736 kb |
| Host | smart-b993b677-0a68-4ba1-920c-3d1c681ba63a |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2721795445 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 98.xbar_random_slow_rsp.2721795445 |
| Directory | /workspace/98.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/98.xbar_random_zero_delays.487801407 |
| Short name | T1575 |
| Test name | |
| Test status | |
| Simulation time | 476109494 ps |
| CPU time | 38.37 seconds |
| Started | Aug 13 07:01:05 PM PDT 24 |
| Finished | Aug 13 07:01:43 PM PDT 24 |
| Peak memory | 575676 kb |
| Host | smart-14490175-9631-41f4-ac74-0c9a1ceef445 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=487801407 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 98.xbar_random_zero_dela ys.487801407 |
| Directory | /workspace/98.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/98.xbar_same_source.3492533608 |
| Short name | T2134 |
| Test name | |
| Test status | |
| Simulation time | 2491237023 ps |
| CPU time | 73.35 seconds |
| Started | Aug 13 07:01:13 PM PDT 24 |
| Finished | Aug 13 07:02:26 PM PDT 24 |
| Peak memory | 575672 kb |
| Host | smart-36348c57-5231-4096-b911-7a8975c6aac3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3492533608 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 98.xbar_same_source.3492533608 |
| Directory | /workspace/98.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/98.xbar_smoke.1179032382 |
| Short name | T1724 |
| Test name | |
| Test status | |
| Simulation time | 43331960 ps |
| CPU time | 5.81 seconds |
| Started | Aug 13 07:01:01 PM PDT 24 |
| Finished | Aug 13 07:01:07 PM PDT 24 |
| Peak memory | 573536 kb |
| Host | smart-d591741d-68b6-462b-9cb0-f273eb370b33 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1179032382 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 98.xbar_smoke.1179032382 |
| Directory | /workspace/98.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/98.xbar_smoke_large_delays.336411362 |
| Short name | T2372 |
| Test name | |
| Test status | |
| Simulation time | 9591928589 ps |
| CPU time | 95.08 seconds |
| Started | Aug 13 07:01:07 PM PDT 24 |
| Finished | Aug 13 07:02:43 PM PDT 24 |
| Peak memory | 574332 kb |
| Host | smart-93135ae4-8ced-4221-8c9d-57321d7c2323 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=336411362 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 98.xbar_smoke_large_delays.336411362 |
| Directory | /workspace/98.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/98.xbar_smoke_slow_rsp.966287482 |
| Short name | T2361 |
| Test name | |
| Test status | |
| Simulation time | 6120930606 ps |
| CPU time | 93.93 seconds |
| Started | Aug 13 07:01:07 PM PDT 24 |
| Finished | Aug 13 07:02:41 PM PDT 24 |
| Peak memory | 574336 kb |
| Host | smart-be34a239-be59-4e04-86b7-ef1b6be37464 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=966287482 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 98.xbar_smoke_slow_rsp.966287482 |
| Directory | /workspace/98.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/98.xbar_smoke_zero_delays.741572276 |
| Short name | T1922 |
| Test name | |
| Test status | |
| Simulation time | 37848878 ps |
| CPU time | 5.51 seconds |
| Started | Aug 13 07:01:06 PM PDT 24 |
| Finished | Aug 13 07:01:11 PM PDT 24 |
| Peak memory | 573536 kb |
| Host | smart-422d56d7-b403-4c62-8165-4da99114c12d |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=741572276 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 98.xbar_smoke_zero_delays .741572276 |
| Directory | /workspace/98.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/98.xbar_stress_all.2055347283 |
| Short name | T2826 |
| Test name | |
| Test status | |
| Simulation time | 14016315987 ps |
| CPU time | 566.61 seconds |
| Started | Aug 13 07:01:13 PM PDT 24 |
| Finished | Aug 13 07:10:40 PM PDT 24 |
| Peak memory | 576448 kb |
| Host | smart-9d8caca1-6894-48ee-8b49-8077cc81c2d1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2055347283 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 98.xbar_stress_all.2055347283 |
| Directory | /workspace/98.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/98.xbar_stress_all_with_rand_reset.2892430086 |
| Short name | T2900 |
| Test name | |
| Test status | |
| Simulation time | 114014313 ps |
| CPU time | 37.37 seconds |
| Started | Aug 13 07:01:15 PM PDT 24 |
| Finished | Aug 13 07:01:52 PM PDT 24 |
| Peak memory | 575756 kb |
| Host | smart-0a9de5f4-6863-4fc9-aafd-8d4f3fce634d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2892430086 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 98.xbar_stress_all _with_rand_reset.2892430086 |
| Directory | /workspace/98.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/98.xbar_stress_all_with_reset_error.2409696056 |
| Short name | T1479 |
| Test name | |
| Test status | |
| Simulation time | 210083837 ps |
| CPU time | 48.4 seconds |
| Started | Aug 13 07:01:11 PM PDT 24 |
| Finished | Aug 13 07:02:00 PM PDT 24 |
| Peak memory | 575668 kb |
| Host | smart-7d4ebc17-eaf2-42f2-a6f8-8a11e0178202 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2409696056 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 98.xbar_stress_al l_with_reset_error.2409696056 |
| Directory | /workspace/98.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/98.xbar_unmapped_addr.3389539640 |
| Short name | T2141 |
| Test name | |
| Test status | |
| Simulation time | 849803941 ps |
| CPU time | 40.47 seconds |
| Started | Aug 13 07:01:13 PM PDT 24 |
| Finished | Aug 13 07:01:54 PM PDT 24 |
| Peak memory | 575752 kb |
| Host | smart-1fd24582-cc83-4f9e-8687-d258ac8918dc |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3389539640 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 98.xbar_unmapped_addr.3389539640 |
| Directory | /workspace/98.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/99.xbar_access_same_device.95934290 |
| Short name | T2447 |
| Test name | |
| Test status | |
| Simulation time | 881851159 ps |
| CPU time | 41.46 seconds |
| Started | Aug 13 07:01:12 PM PDT 24 |
| Finished | Aug 13 07:01:54 PM PDT 24 |
| Peak memory | 575520 kb |
| Host | smart-e9316fd1-0e48-46ab-99bf-71be97fd0dd6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=95934290 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 99.xbar_access_same_device.95934290 |
| Directory | /workspace/99.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/99.xbar_access_same_device_slow_rsp.485148029 |
| Short name | T2741 |
| Test name | |
| Test status | |
| Simulation time | 10688211349 ps |
| CPU time | 180.58 seconds |
| Started | Aug 13 07:01:16 PM PDT 24 |
| Finished | Aug 13 07:04:17 PM PDT 24 |
| Peak memory | 573580 kb |
| Host | smart-9f318b7e-22f4-4081-9486-0ca78c84eb1c |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=485148029 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 99.xbar_access_same_d evice_slow_rsp.485148029 |
| Directory | /workspace/99.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/99.xbar_error_and_unmapped_addr.1224230704 |
| Short name | T2010 |
| Test name | |
| Test status | |
| Simulation time | 270379002 ps |
| CPU time | 27.04 seconds |
| Started | Aug 13 07:01:20 PM PDT 24 |
| Finished | Aug 13 07:01:47 PM PDT 24 |
| Peak memory | 575744 kb |
| Host | smart-27d69460-78e0-4179-a6a2-1bd3e1537aab |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1224230704 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 99.xbar_error_and_unmapped_add r.1224230704 |
| Directory | /workspace/99.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/99.xbar_error_random.3224739596 |
| Short name | T2587 |
| Test name | |
| Test status | |
| Simulation time | 1743618001 ps |
| CPU time | 56.39 seconds |
| Started | Aug 13 07:01:18 PM PDT 24 |
| Finished | Aug 13 07:02:14 PM PDT 24 |
| Peak memory | 575644 kb |
| Host | smart-60d513f3-34f1-4021-afb7-0742ebb77821 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3224739596 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 99.xbar_error_random.3224739596 |
| Directory | /workspace/99.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/99.xbar_random.2234816064 |
| Short name | T1756 |
| Test name | |
| Test status | |
| Simulation time | 1502741693 ps |
| CPU time | 52.21 seconds |
| Started | Aug 13 07:01:12 PM PDT 24 |
| Finished | Aug 13 07:02:04 PM PDT 24 |
| Peak memory | 575728 kb |
| Host | smart-16d9b4a2-13a1-44d4-ab41-4571374a59ff |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2234816064 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 99.xbar_random.2234816064 |
| Directory | /workspace/99.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/99.xbar_random_large_delays.3604478045 |
| Short name | T587 |
| Test name | |
| Test status | |
| Simulation time | 53760271410 ps |
| CPU time | 605.32 seconds |
| Started | Aug 13 07:01:12 PM PDT 24 |
| Finished | Aug 13 07:11:18 PM PDT 24 |
| Peak memory | 575592 kb |
| Host | smart-2ae92fb7-2083-474a-8a2c-bcf3983bbe7a |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3604478045 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 99.xbar_random_large_delays.3604478045 |
| Directory | /workspace/99.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/99.xbar_random_slow_rsp.2710654705 |
| Short name | T492 |
| Test name | |
| Test status | |
| Simulation time | 61914430228 ps |
| CPU time | 1229.03 seconds |
| Started | Aug 13 07:01:12 PM PDT 24 |
| Finished | Aug 13 07:21:42 PM PDT 24 |
| Peak memory | 575708 kb |
| Host | smart-8a709207-786c-4653-8743-aca6b81331c7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2710654705 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 99.xbar_random_slow_rsp.2710654705 |
| Directory | /workspace/99.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/99.xbar_random_zero_delays.2090467961 |
| Short name | T1747 |
| Test name | |
| Test status | |
| Simulation time | 56962704 ps |
| CPU time | 8.17 seconds |
| Started | Aug 13 07:01:11 PM PDT 24 |
| Finished | Aug 13 07:01:19 PM PDT 24 |
| Peak memory | 574268 kb |
| Host | smart-c08bda63-de61-4013-9bf7-442ec746d7a7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2090467961 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 99.xbar_random_zero_del ays.2090467961 |
| Directory | /workspace/99.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/99.xbar_same_source.2732502205 |
| Short name | T688 |
| Test name | |
| Test status | |
| Simulation time | 242763641 ps |
| CPU time | 20 seconds |
| Started | Aug 13 07:01:25 PM PDT 24 |
| Finished | Aug 13 07:01:45 PM PDT 24 |
| Peak memory | 575648 kb |
| Host | smart-90b6e211-9262-416f-8e3e-81a2d864f84d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2732502205 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 99.xbar_same_source.2732502205 |
| Directory | /workspace/99.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/99.xbar_smoke.636172577 |
| Short name | T2523 |
| Test name | |
| Test status | |
| Simulation time | 184325397 ps |
| CPU time | 8.06 seconds |
| Started | Aug 13 07:01:14 PM PDT 24 |
| Finished | Aug 13 07:01:22 PM PDT 24 |
| Peak memory | 573564 kb |
| Host | smart-6ad1d5ba-51c3-4dfd-83ce-aba142a7a63e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=636172577 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 99.xbar_smoke.636172577 |
| Directory | /workspace/99.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/99.xbar_smoke_large_delays.3414794711 |
| Short name | T1726 |
| Test name | |
| Test status | |
| Simulation time | 7793649210 ps |
| CPU time | 84.97 seconds |
| Started | Aug 13 07:01:13 PM PDT 24 |
| Finished | Aug 13 07:02:38 PM PDT 24 |
| Peak memory | 574312 kb |
| Host | smart-6c7b4f99-bda6-4ae5-a42b-0d0d8f0b3ae5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3414794711 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 99.xbar_smoke_large_delays.3414794711 |
| Directory | /workspace/99.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/99.xbar_smoke_slow_rsp.3356858179 |
| Short name | T760 |
| Test name | |
| Test status | |
| Simulation time | 5437670036 ps |
| CPU time | 95.87 seconds |
| Started | Aug 13 07:01:16 PM PDT 24 |
| Finished | Aug 13 07:02:52 PM PDT 24 |
| Peak memory | 574272 kb |
| Host | smart-35eef72e-cb9a-4bf9-adfe-30ec8c9173cd |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3356858179 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 99.xbar_smoke_slow_rsp.3356858179 |
| Directory | /workspace/99.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/99.xbar_smoke_zero_delays.2321106736 |
| Short name | T1639 |
| Test name | |
| Test status | |
| Simulation time | 43425138 ps |
| CPU time | 6.33 seconds |
| Started | Aug 13 07:01:12 PM PDT 24 |
| Finished | Aug 13 07:01:18 PM PDT 24 |
| Peak memory | 573568 kb |
| Host | smart-f5d4f95d-51d2-42af-95eb-eb74dad3d931 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2321106736 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 99.xbar_smoke_zero_delay s.2321106736 |
| Directory | /workspace/99.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/99.xbar_stress_all.123895405 |
| Short name | T2882 |
| Test name | |
| Test status | |
| Simulation time | 8995519672 ps |
| CPU time | 320.08 seconds |
| Started | Aug 13 07:01:20 PM PDT 24 |
| Finished | Aug 13 07:06:40 PM PDT 24 |
| Peak memory | 575684 kb |
| Host | smart-03fb77ed-5b88-459f-b021-2a5b3ab72411 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=123895405 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 99.xbar_stress_all.123895405 |
| Directory | /workspace/99.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/99.xbar_stress_all_with_error.3290914201 |
| Short name | T2174 |
| Test name | |
| Test status | |
| Simulation time | 2284094645 ps |
| CPU time | 155.03 seconds |
| Started | Aug 13 07:01:20 PM PDT 24 |
| Finished | Aug 13 07:03:56 PM PDT 24 |
| Peak memory | 576184 kb |
| Host | smart-7041b4e1-a98f-490a-a36c-82238a5fba84 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3290914201 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 99.xbar_stress_all_with_error.3290914201 |
| Directory | /workspace/99.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/99.xbar_stress_all_with_rand_reset.3748159573 |
| Short name | T914 |
| Test name | |
| Test status | |
| Simulation time | 153806759 ps |
| CPU time | 45.64 seconds |
| Started | Aug 13 07:01:20 PM PDT 24 |
| Finished | Aug 13 07:02:06 PM PDT 24 |
| Peak memory | 575664 kb |
| Host | smart-dee7ec86-f261-4a0b-a82e-7273ecf20749 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3748159573 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 99.xbar_stress_all _with_rand_reset.3748159573 |
| Directory | /workspace/99.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/99.xbar_stress_all_with_reset_error.2045145845 |
| Short name | T2248 |
| Test name | |
| Test status | |
| Simulation time | 152994965 ps |
| CPU time | 37.81 seconds |
| Started | Aug 13 07:01:18 PM PDT 24 |
| Finished | Aug 13 07:01:56 PM PDT 24 |
| Peak memory | 576420 kb |
| Host | smart-e709ca8d-81f6-4541-b328-7e85cf58e098 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2045145845 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 99.xbar_stress_al l_with_reset_error.2045145845 |
| Directory | /workspace/99.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/99.xbar_unmapped_addr.1633478394 |
| Short name | T2062 |
| Test name | |
| Test status | |
| Simulation time | 88774589 ps |
| CPU time | 12.21 seconds |
| Started | Aug 13 07:01:19 PM PDT 24 |
| Finished | Aug 13 07:01:31 PM PDT 24 |
| Peak memory | 575656 kb |
| Host | smart-8893ec12-65b4-4b05-afce-bc0f5a814af5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1633478394 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 99.xbar_unmapped_addr.1633478394 |
| Directory | /workspace/99.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/default/0.chip_jtag_mem_access.3705459394 |
| Short name | T75 |
| Test name | |
| Test status | |
| Simulation time | 13389976140 ps |
| CPU time | 1679.01 seconds |
| Started | Aug 13 07:02:58 PM PDT 24 |
| Finished | Aug 13 07:30:58 PM PDT 24 |
| Peak memory | 608460 kb |
| Host | smart-e229eddc-8737-4215-b96d-228b7bf36579 |
| User | root |
| Command | /workspace/default/simv +create_jtag_riscv_map=1 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3705459394 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_jtag_ mem_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_jtag_mem_access.3 705459394 |
| Directory | /workspace/0.chip_jtag_mem_access/latest |
| Test location | /workspace/coverage/default/0.chip_sival_flash_info_access.95892008 |
| Short name | T315 |
| Test name | |
| Test status | |
| Simulation time | 2369763280 ps |
| CPU time | 316.31 seconds |
| Started | Aug 13 07:10:19 PM PDT 24 |
| Finished | Aug 13 07:15:35 PM PDT 24 |
| Peak memory | 610724 kb |
| Host | smart-ed44f4bb-719e-4866-a53e-558f96c925a6 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStTestUnlocked0 +sw_build_device=sim_dv +sw_images=flash_ctrl_info_access_lc:1:new_rules,test_rom:0 +c dc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_s eed=95892008 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sival_flash_info_access.95892008 |
| Directory | /workspace/0.chip_sival_flash_info_access/latest |
| Test location | /workspace/coverage/default/0.chip_sw_adc_ctrl_sleep_debug_cable_wakeup.2942963076 |
| Short name | T361 |
| Test name | |
| Test status | |
| Simulation time | 18143013864 ps |
| CPU time | 644.08 seconds |
| Started | Aug 13 07:13:08 PM PDT 24 |
| Finished | Aug 13 07:23:52 PM PDT 24 |
| Peak memory | 624572 kb |
| Host | smart-87044cc8-7b80-48f3-b43b-8560a17076f6 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=adc_ctrl_sleep_debug_cable_wakeup_test:1:new_rules,test_rom: 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand om_seed=2942963076 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_adc_ctrl_sleep_debug_cable_wakeup_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_adc_ctrl_sleep_debug_cable_wakeup.2942963076 |
| Directory | /workspace/0.chip_sw_adc_ctrl_sleep_debug_cable_wakeup/latest |
| Test location | /workspace/coverage/default/0.chip_sw_aes_enc.81592331 |
| Short name | T1079 |
| Test name | |
| Test status | |
| Simulation time | 2778699080 ps |
| CPU time | 254.75 seconds |
| Started | Aug 13 07:08:42 PM PDT 24 |
| Finished | Aug 13 07:12:57 PM PDT 24 |
| Peak memory | 610500 kb |
| Host | smart-390910af-c49b-46e4-8b39-4033e44abf0b |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=22_000_000 +sw_build_device=sim_dv +sw_images=aes_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=81592331 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/ default.vdb -cm_log /dev/null -cm_name 0.chip_sw_aes_enc.81592331 |
| Directory | /workspace/0.chip_sw_aes_enc/latest |
| Test location | /workspace/coverage/default/0.chip_sw_aes_enc_jitter_en.2290662538 |
| Short name | T1390 |
| Test name | |
| Test status | |
| Simulation time | 3057172386 ps |
| CPU time | 324.29 seconds |
| Started | Aug 13 07:10:03 PM PDT 24 |
| Finished | Aug 13 07:15:28 PM PDT 24 |
| Peak memory | 610536 kb |
| Host | smart-0e416207-f7b4-4ffb-b212-323cb2dff43b |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=26_000_000 +en_jitter=1 +sw_build_device=sim_dv +sw_images=aes_smoketest:1:new_rules,test_rom:0 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2290 662538 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work space/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_aes_enc_jitter_en.2290662538 |
| Directory | /workspace/0.chip_sw_aes_enc_jitter_en/latest |
| Test location | /workspace/coverage/default/0.chip_sw_aes_enc_jitter_en_reduced_freq.202937335 |
| Short name | T1317 |
| Test name | |
| Test status | |
| Simulation time | 2610762511 ps |
| CPU time | 255.52 seconds |
| Started | Aug 13 07:12:34 PM PDT 24 |
| Finished | Aug 13 07:16:51 PM PDT 24 |
| Peak memory | 610452 kb |
| Host | smart-c5b6a00e-c848-45fa-b554-45e0dfb40846 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=26_000_000 +en_jitter=1 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=aes_smoketest:1:new_rules, test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=202937335 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_aes_enc_jitter_en_reduced_freq.202937335 |
| Directory | /workspace/0.chip_sw_aes_enc_jitter_en_reduced_freq/latest |
| Test location | /workspace/coverage/default/0.chip_sw_aes_entropy.352922633 |
| Short name | T1172 |
| Test name | |
| Test status | |
| Simulation time | 2084267338 ps |
| CPU time | 219.02 seconds |
| Started | Aug 13 07:12:03 PM PDT 24 |
| Finished | Aug 13 07:15:43 PM PDT 24 |
| Peak memory | 610332 kb |
| Host | smart-12072639-ffd7-4cc8-8a8f-f67f36636eb3 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=15_000_000 +sw_build_device=sim_dv +sw_images=aes_entropy_test:1:new_rules,test_rom:0 +cdc_instrumentation _enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=352922633 -ass ert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_aes_entropy.352922633 |
| Directory | /workspace/0.chip_sw_aes_entropy/latest |
| Test location | /workspace/coverage/default/0.chip_sw_aes_idle.1750582516 |
| Short name | T386 |
| Test name | |
| Test status | |
| Simulation time | 3143590400 ps |
| CPU time | 356.67 seconds |
| Started | Aug 13 07:10:25 PM PDT 24 |
| Finished | Aug 13 07:16:22 PM PDT 24 |
| Peak memory | 609828 kb |
| Host | smart-dc229100-7216-4b28-be0c-6006a605cd41 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=25_000_000 +sw_build_device=sim_dv +sw_images=aes_idle_test:1:new_rules,test_rom:0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1750582516 -asser t nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag e/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_aes_idle.1750582516 |
| Directory | /workspace/0.chip_sw_aes_idle/latest |
| Test location | /workspace/coverage/default/0.chip_sw_aes_masking_off.2668602734 |
| Short name | T1033 |
| Test name | |
| Test status | |
| Simulation time | 2726646602 ps |
| CPU time | 344.75 seconds |
| Started | Aug 13 07:09:18 PM PDT 24 |
| Finished | Aug 13 07:15:04 PM PDT 24 |
| Peak memory | 609888 kb |
| Host | smart-984da378-be85-4ccd-81fa-d19f1824caca |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=aes_masking_off_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2668602734 -assert nopostproc +UVM_TESTNA ME=chip_base_test +UVM_TEST_SEQ=chip_sw_aes_masking_off_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_aes_masking_off.2668602734 |
| Directory | /workspace/0.chip_sw_aes_masking_off/latest |
| Test location | /workspace/coverage/default/0.chip_sw_aes_smoketest.956642086 |
| Short name | T959 |
| Test name | |
| Test status | |
| Simulation time | 3059137976 ps |
| CPU time | 335.53 seconds |
| Started | Aug 13 07:18:44 PM PDT 24 |
| Finished | Aug 13 07:24:20 PM PDT 24 |
| Peak memory | 610436 kb |
| Host | smart-83846f60-b84a-402e-a5a1-62e6d070209c |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=aes_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=956642086 -assert nopostproc +UVM_TESTNAME=chip_ base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_aes_smoketest.956642086 |
| Directory | /workspace/0.chip_sw_aes_smoketest/latest |
| Test location | /workspace/coverage/default/0.chip_sw_alert_handler_escalation.4041577951 |
| Short name | T1005 |
| Test name | |
| Test status | |
| Simulation time | 5560957596 ps |
| CPU time | 706.68 seconds |
| Started | Aug 13 07:11:31 PM PDT 24 |
| Finished | Aug 13 07:23:18 PM PDT 24 |
| Peak memory | 620280 kb |
| Host | smart-afa4401b-ca14-4714-91f7-6092e1c61a66 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=alert_handler_escalation_test:1:new_rules,test _rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb _random_seed=4041577951 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_alert_handler_escalation_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_alert_handler_escalation.4041577951 |
| Directory | /workspace/0.chip_sw_alert_handler_escalation/latest |
| Test location | /workspace/coverage/default/0.chip_sw_alert_handler_lpg_clkoff.4238689609 |
| Short name | T1199 |
| Test name | |
| Test status | |
| Simulation time | 5726214784 ps |
| CPU time | 1179.38 seconds |
| Started | Aug 13 07:13:14 PM PDT 24 |
| Finished | Aug 13 07:32:54 PM PDT 24 |
| Peak memory | 610884 kb |
| Host | smart-4fa78c2e-69d9-441c-abf6-a06c766bdca0 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +sw_build_device=sim_dv +sw_images=alert_handler_lpg_clkoff_test:1:new_rules,test_r om:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r andom_seed=4238689609 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_alert_handler_lpg_clkoff_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_alert_handler_lpg_clkoff.4238689609 |
| Directory | /workspace/0.chip_sw_alert_handler_lpg_clkoff/latest |
| Test location | /workspace/coverage/default/0.chip_sw_alert_handler_lpg_reset_toggle.2978609967 |
| Short name | T1069 |
| Test name | |
| Test status | |
| Simulation time | 7881291528 ps |
| CPU time | 1735.85 seconds |
| Started | Aug 13 07:10:01 PM PDT 24 |
| Finished | Aug 13 07:38:58 PM PDT 24 |
| Peak memory | 610948 kb |
| Host | smart-1ae670bc-17f9-4653-865f-f90b2049498a |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +sw_build_device=sim_dv +sw_images=alert_handler_lpg_reset_toggle_test:1:new_rules, test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2978609967 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_alert_handler_shorten_ping_wait_cycle_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_alert_handler_lpg_reset_togg le.2978609967 |
| Directory | /workspace/0.chip_sw_alert_handler_lpg_reset_toggle/latest |
| Test location | /workspace/coverage/default/0.chip_sw_alert_handler_lpg_sleep_mode_pings.2224929408 |
| Short name | T166 |
| Test name | |
| Test status | |
| Simulation time | 10881194520 ps |
| CPU time | 1411.85 seconds |
| Started | Aug 13 07:11:12 PM PDT 24 |
| Finished | Aug 13 07:34:45 PM PDT 24 |
| Peak memory | 611672 kb |
| Host | smart-ea32f384-e1ee-4ac9-8dd8-84ab0d6b7927 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=alert_handler _lpg_sleep_mode_pings_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2224929408 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_alert_han dler_shorten_ping_wait_cycle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_alert_handler_lpg_sleep_mode_pings.2224929408 |
| Directory | /workspace/0.chip_sw_alert_handler_lpg_sleep_mode_pings/latest |
| Test location | /workspace/coverage/default/0.chip_sw_alert_handler_ping_ok.2119673625 |
| Short name | T776 |
| Test name | |
| Test status | |
| Simulation time | 8369183520 ps |
| CPU time | 1566.68 seconds |
| Started | Aug 13 07:10:21 PM PDT 24 |
| Finished | Aug 13 07:36:28 PM PDT 24 |
| Peak memory | 609732 kb |
| Host | smart-7ebe494a-b5ef-449c-9fb2-122af16de1d7 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=24000000 +sw_build_device=sim_dv +sw_images=alert_handler_ping_ok_test:1:new_rules,test_rom:0 +c dc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_s eed=2119673625 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_alert_handler_ping_ok.2119673625 |
| Directory | /workspace/0.chip_sw_alert_handler_ping_ok/latest |
| Test location | /workspace/coverage/default/0.chip_sw_alert_handler_ping_timeout.2756508398 |
| Short name | T1243 |
| Test name | |
| Test status | |
| Simulation time | 3641366784 ps |
| CPU time | 452.36 seconds |
| Started | Aug 13 07:11:13 PM PDT 24 |
| Finished | Aug 13 07:18:45 PM PDT 24 |
| Peak memory | 610240 kb |
| Host | smart-0c9ce07e-b7a4-4194-b156-6df0f5fef830 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=24000000 +sw_build_device=sim_dv +sw_images=alert_handler_ping_timeout_test:1:new_rules,test_rom :0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=2756508398 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_alert_handler_ping_timeout.2756508398 |
| Directory | /workspace/0.chip_sw_alert_handler_ping_timeout/latest |
| Test location | /workspace/coverage/default/0.chip_sw_alert_handler_reverse_ping_in_deep_sleep.3753982037 |
| Short name | T163 |
| Test name | |
| Test status | |
| Simulation time | 255010870016 ps |
| CPU time | 12131.3 seconds |
| Started | Aug 13 07:11:20 PM PDT 24 |
| Finished | Aug 13 10:33:32 PM PDT 24 |
| Peak memory | 611528 kb |
| Host | smart-cca6f882-1fab-45f2-b796-4336027f5259 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=300_000_000 +sw_build_device=sim_dv +sw_images=alert_handler_reverse_ping_in_deep_sleep_test:1:n ew_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3753982037 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_alert_handler_reverse_ping_in_deep_sleep.3753982037 |
| Directory | /workspace/0.chip_sw_alert_handler_reverse_ping_in_deep_sleep/latest |
| Test location | /workspace/coverage/default/0.chip_sw_alert_test.3165483738 |
| Short name | T47 |
| Test name | |
| Test status | |
| Simulation time | 3169782200 ps |
| CPU time | 287.02 seconds |
| Started | Aug 13 07:09:59 PM PDT 24 |
| Finished | Aug 13 07:14:47 PM PDT 24 |
| Peak memory | 610404 kb |
| Host | smart-a38dde3b-75e2-466e-87b2-4f2e8d655d72 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=alert_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3165483738 -assert nopostproc +UVM_TESTNAME=chip_ba se_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 0.chip_sw_alert_test.3165483738 |
| Directory | /workspace/0.chip_sw_alert_test/latest |
| Test location | /workspace/coverage/default/0.chip_sw_aon_timer_irq.736960856 |
| Short name | T952 |
| Test name | |
| Test status | |
| Simulation time | 4588914434 ps |
| CPU time | 421.84 seconds |
| Started | Aug 13 07:09:34 PM PDT 24 |
| Finished | Aug 13 07:16:36 PM PDT 24 |
| Peak memory | 610520 kb |
| Host | smart-b856022e-0a2d-41b4-95a6-aac6f017721b |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=aon_timer_irq_test:1:new_rules,test_rom:0 +cdc_instrumentati on_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=736960856 -a ssert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov erage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_aon_timer_irq.736960856 |
| Directory | /workspace/0.chip_sw_aon_timer_irq/latest |
| Test location | /workspace/coverage/default/0.chip_sw_aon_timer_sleep_wdog_sleep_pause.2031519903 |
| Short name | T1316 |
| Test name | |
| Test status | |
| Simulation time | 6794106300 ps |
| CPU time | 311.48 seconds |
| Started | Aug 13 07:10:33 PM PDT 24 |
| Finished | Aug 13 07:15:44 PM PDT 24 |
| Peak memory | 611180 kb |
| Host | smart-05c0d0f4-5a45-438e-80b5-3937c1d5835e |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=aon_timer_sleep_wdog_sleep_pause_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=2031519903 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_aon_timer_sleep_wdog_sleep_pause.2031519903 |
| Directory | /workspace/0.chip_sw_aon_timer_sleep_wdog_sleep_pause/latest |
| Test location | /workspace/coverage/default/0.chip_sw_aon_timer_smoketest.2554377944 |
| Short name | T1202 |
| Test name | |
| Test status | |
| Simulation time | 2674086528 ps |
| CPU time | 351.09 seconds |
| Started | Aug 13 07:17:55 PM PDT 24 |
| Finished | Aug 13 07:23:47 PM PDT 24 |
| Peak memory | 609904 kb |
| Host | smart-6b6bf5b9-bebb-4d88-9bd2-56422d26dfd9 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=aon_timer_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2554377944 -assert nopostproc +UVM_TESTNAM E=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 0.chip_sw_aon_timer_smoketest.2554377944 |
| Directory | /workspace/0.chip_sw_aon_timer_smoketest/latest |
| Test location | /workspace/coverage/default/0.chip_sw_aon_timer_wdog_bite_reset.3768554737 |
| Short name | T1347 |
| Test name | |
| Test status | |
| Simulation time | 7462942520 ps |
| CPU time | 798.01 seconds |
| Started | Aug 13 07:12:04 PM PDT 24 |
| Finished | Aug 13 07:25:23 PM PDT 24 |
| Peak memory | 611200 kb |
| Host | smart-afaa3d58-8fdf-42dd-96c3-4a8baceb76bc |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=aon_timer_wdog_bite_reset_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 3768554737 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_aon_timer_wdog_bite_reset.3768554737 |
| Directory | /workspace/0.chip_sw_aon_timer_wdog_bite_reset/latest |
| Test location | /workspace/coverage/default/0.chip_sw_aon_timer_wdog_lc_escalate.1849356602 |
| Short name | T1222 |
| Test name | |
| Test status | |
| Simulation time | 5916004990 ps |
| CPU time | 746.08 seconds |
| Started | Aug 13 07:10:24 PM PDT 24 |
| Finished | Aug 13 07:22:50 PM PDT 24 |
| Peak memory | 611424 kb |
| Host | smart-3e2c405f-f41e-4c1a-9eaa-30415c13f22f |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=aon_timer_wdog_lc_escalate_test:1:new_rules,test_rom:0 +cdc_ instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed =1849356602 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_aon_timer_wdog_lc_escalate.1849356602 |
| Directory | /workspace/0.chip_sw_aon_timer_wdog_lc_escalate/latest |
| Test location | /workspace/coverage/default/0.chip_sw_ast_clk_outputs.301370446 |
| Short name | T1200 |
| Test name | |
| Test status | |
| Simulation time | 6860390840 ps |
| CPU time | 889.6 seconds |
| Started | Aug 13 07:12:02 PM PDT 24 |
| Finished | Aug 13 07:26:52 PM PDT 24 |
| Peak memory | 617808 kb |
| Host | smart-5cadfc95-2015-4efb-9d92-fc33a793acd9 |
| User | root |
| Command | /workspace/default/simv +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=ast_clk_outs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled= 1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=301370446 -assert nopos tproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_ast_clk_outputs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov erage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_ast_clk_outputs.301370446 |
| Directory | /workspace/0.chip_sw_ast_clk_outputs/latest |
| Test location | /workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_lc.4224198855 |
| Short name | T1127 |
| Test name | |
| Test status | |
| Simulation time | 9979204429 ps |
| CPU time | 963.87 seconds |
| Started | Aug 13 07:13:15 PM PDT 24 |
| Finished | Aug 13 07:29:19 PM PDT 24 |
| Peak memory | 621992 kb |
| Host | smart-52401e9e-4158-4ba4-9b63-216b9481d09d |
| User | root |
| Command | /workspace/default/simv +chip_clock_source=ChipClockSourceExternal48Mhz +sw_build_device=sim_dv +sw_images=clkmgr_external_clk_src_for_lc_test:1:new_r ules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim .tcl +ntb_random_seed=4224198855 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_transition_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_clkmgr_external_clk_src_for_lc.4224198855 |
| Directory | /workspace/0.chip_sw_clkmgr_external_clk_src_for_lc/latest |
| Test location | /workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_fast_dev.489461014 |
| Short name | T123 |
| Test name | |
| Test status | |
| Simulation time | 3639910872 ps |
| CPU time | 574.4 seconds |
| Started | Aug 13 07:10:40 PM PDT 24 |
| Finished | Aug 13 07:20:15 PM PDT 24 |
| Peak memory | 614880 kb |
| Host | smart-14c2b328-961c-4b2c-b298-60076a939773 |
| User | root |
| Command | /workspace/default/simv +chip_clock_source=ChipClockSourceExternal96Mhz +calibrate_usb_clk=1 +src_dec_state=DecLcStDev +sw_build_device=sim_dv +sw_ima ges=clkmgr_external_clk_src_for_sw_fast_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=489461014 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ= chip_sw_lc_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_cl kmgr_external_clk_src_for_sw_fast_dev.489461014 |
| Directory | /workspace/0.chip_sw_clkmgr_external_clk_src_for_sw_fast_dev/latest |
| Test location | /workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_fast_rma.3781886778 |
| Short name | T1308 |
| Test name | |
| Test status | |
| Simulation time | 4401045250 ps |
| CPU time | 696.58 seconds |
| Started | Aug 13 07:11:56 PM PDT 24 |
| Finished | Aug 13 07:23:34 PM PDT 24 |
| Peak memory | 613948 kb |
| Host | smart-0ab2375c-5c52-4ff8-b795-9f824e7e02fd |
| User | root |
| Command | /workspace/default/simv +chip_clock_source=ChipClockSourceExternal96Mhz +calibrate_usb_clk=1 +src_dec_state=DecLcStRma +sw_build_device=sim_dv +sw_ima ges=clkmgr_external_clk_src_for_sw_fast_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3781886778 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ =chip_sw_lc_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_c lkmgr_external_clk_src_for_sw_fast_rma.3781886778 |
| Directory | /workspace/0.chip_sw_clkmgr_external_clk_src_for_sw_fast_rma/latest |
| Test location | /workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0.3522127182 |
| Short name | T1095 |
| Test name | |
| Test status | |
| Simulation time | 3976938134 ps |
| CPU time | 725.74 seconds |
| Started | Aug 13 07:12:01 PM PDT 24 |
| Finished | Aug 13 07:24:08 PM PDT 24 |
| Peak memory | 614700 kb |
| Host | smart-a43d49f6-7eaa-48cf-af45-883c1d45a7c4 |
| User | root |
| Command | /workspace/default/simv +chip_clock_source=ChipClockSourceExternal96Mhz +calibrate_usb_clk=1 +src_dec_state=DecLcStTestUnlocked0 +sw_build_device=sim_ dv +sw_images=clkmgr_external_clk_src_for_sw_fast_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3522127182 -assert nopostproc +UVM_TESTNAME=chip_base_test +UV M_TEST_SEQ=chip_sw_lc_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0 .chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0.3522127182 |
| Directory | /workspace/0.chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0/latest |
| Test location | /workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_slow_dev.1278205055 |
| Short name | T1074 |
| Test name | |
| Test status | |
| Simulation time | 4748181406 ps |
| CPU time | 833.72 seconds |
| Started | Aug 13 07:12:43 PM PDT 24 |
| Finished | Aug 13 07:26:38 PM PDT 24 |
| Peak memory | 614620 kb |
| Host | smart-f4ecca2d-e086-4a14-9999-6878e7327474 |
| User | root |
| Command | /workspace/default/simv +chip_clock_source=ChipClockSourceExternal48Mhz +calibrate_usb_clk=1 +src_dec_state=DecLcStDev +sw_build_device=sim_dv +sw_ima ges=clkmgr_external_clk_src_for_sw_slow_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1278205055 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ =chip_sw_lc_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_c lkmgr_external_clk_src_for_sw_slow_dev.1278205055 |
| Directory | /workspace/0.chip_sw_clkmgr_external_clk_src_for_sw_slow_dev/latest |
| Test location | /workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0.2598704844 |
| Short name | T1334 |
| Test name | |
| Test status | |
| Simulation time | 5328480528 ps |
| CPU time | 726.14 seconds |
| Started | Aug 13 07:09:38 PM PDT 24 |
| Finished | Aug 13 07:21:45 PM PDT 24 |
| Peak memory | 614736 kb |
| Host | smart-bbfd9cf4-4004-4b41-a2f9-d901c1d1d4fb |
| User | root |
| Command | /workspace/default/simv +chip_clock_source=ChipClockSourceExternal48Mhz +calibrate_usb_clk=1 +src_dec_state=DecLcStTestUnlocked0 +sw_build_device=sim_ dv +sw_images=clkmgr_external_clk_src_for_sw_slow_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2598704844 -assert nopostproc +UVM_TESTNAME=chip_base_test +UV M_TEST_SEQ=chip_sw_lc_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0 .chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0.2598704844 |
| Directory | /workspace/0.chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0/latest |
| Test location | /workspace/coverage/default/0.chip_sw_clkmgr_jitter.1500978226 |
| Short name | T1274 |
| Test name | |
| Test status | |
| Simulation time | 3028268911 ps |
| CPU time | 313.13 seconds |
| Started | Aug 13 07:12:11 PM PDT 24 |
| Finished | Aug 13 07:17:24 PM PDT 24 |
| Peak memory | 610432 kb |
| Host | smart-8936b6d9-c989-4a8a-82d8-aa95a0294f77 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=clkmgr_jitter_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1500978226 -assert nopostproc +UVM_TESTNAME =chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 0.chip_sw_clkmgr_jitter.1500978226 |
| Directory | /workspace/0.chip_sw_clkmgr_jitter/latest |
| Test location | /workspace/coverage/default/0.chip_sw_clkmgr_jitter_frequency.455239240 |
| Short name | T1006 |
| Test name | |
| Test status | |
| Simulation time | 3944260030 ps |
| CPU time | 470.38 seconds |
| Started | Aug 13 07:13:08 PM PDT 24 |
| Finished | Aug 13 07:20:59 PM PDT 24 |
| Peak memory | 610572 kb |
| Host | smart-d05659af-c514-421f-ab72-f82c2601e391 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=clkmgr_jitter_frequency_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=455239240 -assert nopostproc +UVM _TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm _log /dev/null -cm_name 0.chip_sw_clkmgr_jitter_frequency.455239240 |
| Directory | /workspace/0.chip_sw_clkmgr_jitter_frequency/latest |
| Test location | /workspace/coverage/default/0.chip_sw_clkmgr_jitter_reduced_freq.1536023979 |
| Short name | T950 |
| Test name | |
| Test status | |
| Simulation time | 2355170360 ps |
| CPU time | 180.73 seconds |
| Started | Aug 13 07:11:05 PM PDT 24 |
| Finished | Aug 13 07:14:06 PM PDT 24 |
| Peak memory | 610340 kb |
| Host | smart-433985a9-8cf4-4d36-85c3-df3bfa05734d |
| User | root |
| Command | /workspace/default/simv +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=clkmgr_jitter_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1536023979 -assert nop ostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def ault.vdb -cm_log /dev/null -cm_name 0.chip_sw_clkmgr_jitter_reduced_freq.1536023979 |
| Directory | /workspace/0.chip_sw_clkmgr_jitter_reduced_freq/latest |
| Test location | /workspace/coverage/default/0.chip_sw_clkmgr_off_aes_trans.3480367144 |
| Short name | T1356 |
| Test name | |
| Test status | |
| Simulation time | 5860966632 ps |
| CPU time | 656.86 seconds |
| Started | Aug 13 07:13:02 PM PDT 24 |
| Finished | Aug 13 07:23:59 PM PDT 24 |
| Peak memory | 610348 kb |
| Host | smart-1c623fc6-6aee-4e77-9895-2b5fa9a2f60b |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=clkmgr_off_aes_trans_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3480367144 -assert nopostproc +UVM_T ESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l og /dev/null -cm_name 0.chip_sw_clkmgr_off_aes_trans.3480367144 |
| Directory | /workspace/0.chip_sw_clkmgr_off_aes_trans/latest |
| Test location | /workspace/coverage/default/0.chip_sw_clkmgr_off_hmac_trans.500115292 |
| Short name | T1400 |
| Test name | |
| Test status | |
| Simulation time | 4182935944 ps |
| CPU time | 414.29 seconds |
| Started | Aug 13 07:11:44 PM PDT 24 |
| Finished | Aug 13 07:18:38 PM PDT 24 |
| Peak memory | 609880 kb |
| Host | smart-a458d3f8-acc8-41ed-bd56-1924177bec1c |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=clkmgr_off_hmac_trans_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=500115292 -assert nopostproc +UVM_T ESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l og /dev/null -cm_name 0.chip_sw_clkmgr_off_hmac_trans.500115292 |
| Directory | /workspace/0.chip_sw_clkmgr_off_hmac_trans/latest |
| Test location | /workspace/coverage/default/0.chip_sw_clkmgr_off_kmac_trans.3019144295 |
| Short name | T956 |
| Test name | |
| Test status | |
| Simulation time | 4667859052 ps |
| CPU time | 578.79 seconds |
| Started | Aug 13 07:13:31 PM PDT 24 |
| Finished | Aug 13 07:23:10 PM PDT 24 |
| Peak memory | 610344 kb |
| Host | smart-5dfd93d6-e917-4f32-89ca-216ae27748fc |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=clkmgr_off_kmac_trans_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3019144295 -assert nopostproc +UVM_ TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_ log /dev/null -cm_name 0.chip_sw_clkmgr_off_kmac_trans.3019144295 |
| Directory | /workspace/0.chip_sw_clkmgr_off_kmac_trans/latest |
| Test location | /workspace/coverage/default/0.chip_sw_clkmgr_off_otbn_trans.2516293109 |
| Short name | T317 |
| Test name | |
| Test status | |
| Simulation time | 5216984336 ps |
| CPU time | 596.75 seconds |
| Started | Aug 13 07:11:52 PM PDT 24 |
| Finished | Aug 13 07:21:49 PM PDT 24 |
| Peak memory | 611184 kb |
| Host | smart-c317ca85-4aa3-4054-93df-0956f2709d14 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=clkmgr_off_otbn_trans_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2516293109 -assert nopostproc +UVM_ TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_ log /dev/null -cm_name 0.chip_sw_clkmgr_off_otbn_trans.2516293109 |
| Directory | /workspace/0.chip_sw_clkmgr_off_otbn_trans/latest |
| Test location | /workspace/coverage/default/0.chip_sw_clkmgr_off_peri.2459114332 |
| Short name | T1298 |
| Test name | |
| Test status | |
| Simulation time | 8308054790 ps |
| CPU time | 1069.02 seconds |
| Started | Aug 13 07:10:05 PM PDT 24 |
| Finished | Aug 13 07:27:55 PM PDT 24 |
| Peak memory | 611288 kb |
| Host | smart-d8922c32-c56b-44d1-a2fe-0a96110a8b28 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=30_000_000 +sw_build_device=sim_dv +sw_images=clkmgr_off_peri_test:1:new_rules,test_rom:0 +cdc_instrumenta tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2459114332 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/ coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_clkmgr_off_peri.2459114332 |
| Directory | /workspace/0.chip_sw_clkmgr_off_peri/latest |
| Test location | /workspace/coverage/default/0.chip_sw_clkmgr_reset_frequency.1995004178 |
| Short name | T763 |
| Test name | |
| Test status | |
| Simulation time | 3917569096 ps |
| CPU time | 329.18 seconds |
| Started | Aug 13 07:13:06 PM PDT 24 |
| Finished | Aug 13 07:18:35 PM PDT 24 |
| Peak memory | 610044 kb |
| Host | smart-cfe2721e-ba49-4a2f-881a-d9bdc7a7e3ec |
| User | root |
| Command | /workspace/default/simv +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=clkmgr_reset_frequency_test:1:new_rules,test_rom:0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1995004178 -a ssert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov erage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_clkmgr_reset_frequency.1995004178 |
| Directory | /workspace/0.chip_sw_clkmgr_reset_frequency/latest |
| Test location | /workspace/coverage/default/0.chip_sw_clkmgr_sleep_frequency.2639489797 |
| Short name | T1126 |
| Test name | |
| Test status | |
| Simulation time | 5008953504 ps |
| CPU time | 736.65 seconds |
| Started | Aug 13 07:13:07 PM PDT 24 |
| Finished | Aug 13 07:25:24 PM PDT 24 |
| Peak memory | 610744 kb |
| Host | smart-d9371916-61d9-4171-a572-eea29e495148 |
| User | root |
| Command | /workspace/default/simv +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=clkmgr_sleep_frequency_test:1:new_rules,test_rom:0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2639489797 -a ssert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov erage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_clkmgr_sleep_frequency.2639489797 |
| Directory | /workspace/0.chip_sw_clkmgr_sleep_frequency/latest |
| Test location | /workspace/coverage/default/0.chip_sw_clkmgr_smoketest.3602140667 |
| Short name | T1380 |
| Test name | |
| Test status | |
| Simulation time | 2799946040 ps |
| CPU time | 349.7 seconds |
| Started | Aug 13 07:16:21 PM PDT 24 |
| Finished | Aug 13 07:22:11 PM PDT 24 |
| Peak memory | 610200 kb |
| Host | smart-de0dddc3-aeea-467b-8272-ea7e279d27a2 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=clkmgr_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3602140667 -assert nopostproc +UVM_TESTNAME=c hip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n ull -cm_name 0.chip_sw_clkmgr_smoketest.3602140667 |
| Directory | /workspace/0.chip_sw_clkmgr_smoketest/latest |
| Test location | /workspace/coverage/default/0.chip_sw_coremark.1566844186 |
| Short name | T1061 |
| Test name | |
| Test status | |
| Simulation time | 72257685352 ps |
| CPU time | 15062.4 seconds |
| Started | Aug 13 07:11:36 PM PDT 24 |
| Finished | Aug 13 11:22:41 PM PDT 24 |
| Peak memory | 612316 kb |
| Host | smart-4e1bdd5b-df70-432c-a0b6-54b4a6ad7512 |
| User | root |
| Command | /workspace/default/simv +en_uart_logger=1 +sw_test_timeout_ns=200_000_000 +sw_build_device=sim_dv +sw_images=coremark_test:1:new_rules,test_rom:0 +cdc _instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see d=1566844186 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_coremark.1566844186 |
| Directory | /workspace/0.chip_sw_coremark/latest |
| Test location | /workspace/coverage/default/0.chip_sw_csrng_edn_concurrency.4223579262 |
| Short name | T1397 |
| Test name | |
| Test status | |
| Simulation time | 27266334120 ps |
| CPU time | 6255.12 seconds |
| Started | Aug 13 07:13:18 PM PDT 24 |
| Finished | Aug 13 08:57:35 PM PDT 24 |
| Peak memory | 611180 kb |
| Host | smart-9d268acb-58e8-40ba-9f31-951e5b021fea |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=140_000_000 +rng_srate_value_min=15 +rng_srate_value_max=20 +accelerate_cold_power_up_time=3 +accelerate_r egulators_power_up_time=2 +sw_build_device=sim_dv +sw_images=csrng_edn_concurrency_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4223579262 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd b -cm_log /dev/null -cm_name 0.chip_sw_csrng_edn_concurrency.4223579262 |
| Directory | /workspace/0.chip_sw_csrng_edn_concurrency/latest |
| Test location | /workspace/coverage/default/0.chip_sw_csrng_edn_concurrency_reduced_freq.2636707032 |
| Short name | T721 |
| Test name | |
| Test status | |
| Simulation time | 37788459140 ps |
| CPU time | 6041.57 seconds |
| Started | Aug 13 07:12:18 PM PDT 24 |
| Finished | Aug 13 08:53:00 PM PDT 24 |
| Peak memory | 611164 kb |
| Host | smart-09db8ec7-e8de-4557-9ca6-a36649de6305 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=360_000_000 +rng_srate_value_min=15 +rng_srate_value_max=20 +cal_sys_clk_70mhz=1 +en_jitter=1 +accelerate_ cold_power_up_time=3 +accelerate_regulators_power_up_time=2 +sw_build_device=sim_dv +sw_images=csrng_edn_concurrency_test:1:new_rules,test_rom:0 + cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_ seed=2636707032 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_csrng_edn_concurrency_reduced_freq.2636707032 |
| Directory | /workspace/0.chip_sw_csrng_edn_concurrency_reduced_freq/latest |
| Test location | /workspace/coverage/default/0.chip_sw_csrng_kat_test.1377293099 |
| Short name | T1155 |
| Test name | |
| Test status | |
| Simulation time | 3343612384 ps |
| CPU time | 242.77 seconds |
| Started | Aug 13 07:12:38 PM PDT 24 |
| Finished | Aug 13 07:16:41 PM PDT 24 |
| Peak memory | 610352 kb |
| Host | smart-162702dd-5c4c-4b36-bd74-2e88f7cf72d7 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=csrng_kat_test:1:new_rules,test_rom:0 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1377293099 -asse rt nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera ge/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_csrng_kat_test.1377293099 |
| Directory | /workspace/0.chip_sw_csrng_kat_test/latest |
| Test location | /workspace/coverage/default/0.chip_sw_csrng_lc_hw_debug_en_test.830855224 |
| Short name | T1182 |
| Test name | |
| Test status | |
| Simulation time | 6820002288 ps |
| CPU time | 622.81 seconds |
| Started | Aug 13 07:11:51 PM PDT 24 |
| Finished | Aug 13 07:22:14 PM PDT 24 |
| Peak memory | 611556 kb |
| Host | smart-3c9543f3-cc7e-48ad-8169-45a8d719de7f |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=15_000_000 +rng_srate_value_min=15 +use_otp_image=OtpTypeLcStTestUnlocked0 +sw_build_device=sim_dv +sw_ima ges=csrng_lc_hw_debug_en_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=830855224 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_csrng_l c_hw_debug_en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_csrn g_lc_hw_debug_en_test.830855224 |
| Directory | /workspace/0.chip_sw_csrng_lc_hw_debug_en_test/latest |
| Test location | /workspace/coverage/default/0.chip_sw_csrng_smoketest.3280446484 |
| Short name | T383 |
| Test name | |
| Test status | |
| Simulation time | 2959456336 ps |
| CPU time | 185.47 seconds |
| Started | Aug 13 07:11:39 PM PDT 24 |
| Finished | Aug 13 07:14:45 PM PDT 24 |
| Peak memory | 610352 kb |
| Host | smart-0287a9b2-e3f7-4835-8ce5-147d41e0f2f1 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=csrng_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3280446484 -assert nopostproc +UVM_TESTNAME=ch ip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu ll -cm_name 0.chip_sw_csrng_smoketest.3280446484 |
| Directory | /workspace/0.chip_sw_csrng_smoketest/latest |
| Test location | /workspace/coverage/default/0.chip_sw_edn_auto_mode.1400449301 |
| Short name | T1226 |
| Test name | |
| Test status | |
| Simulation time | 4831179050 ps |
| CPU time | 1261.11 seconds |
| Started | Aug 13 07:11:22 PM PDT 24 |
| Finished | Aug 13 07:32:24 PM PDT 24 |
| Peak memory | 610944 kb |
| Host | smart-3ae46dec-2fb4-4232-af47-159c763a3363 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +rng_srate_value=5 +accelerate_cold_power_up_time=3 +accelerate_regulators_power_up_time=2 +sw_ build_device=sim_dv +sw_images=edn_auto_mode:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1400449301 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ =chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_edn_ auto_mode.1400449301 |
| Directory | /workspace/0.chip_sw_edn_auto_mode/latest |
| Test location | /workspace/coverage/default/0.chip_sw_edn_entropy_reqs.2786999767 |
| Short name | T463 |
| Test name | |
| Test status | |
| Simulation time | 8302357288 ps |
| CPU time | 1533.81 seconds |
| Started | Aug 13 07:11:18 PM PDT 24 |
| Finished | Aug 13 07:36:52 PM PDT 24 |
| Peak memory | 611648 kb |
| Host | smart-b33c4f62-60ce-48ed-8e17-9c0157213798 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=15000000 +rng_srate_value_min=15 +rng_srate_value_max=30 +sw_build_device=sim_dv +sw_images=entropy_src_ed n_reqs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2786999767 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_edn_entropy_reqs.2786999767 |
| Directory | /workspace/0.chip_sw_edn_entropy_reqs/latest |
| Test location | /workspace/coverage/default/0.chip_sw_edn_entropy_reqs_jitter.2597285872 |
| Short name | T1103 |
| Test name | |
| Test status | |
| Simulation time | 7680520951 ps |
| CPU time | 969.12 seconds |
| Started | Aug 13 07:12:28 PM PDT 24 |
| Finished | Aug 13 07:28:38 PM PDT 24 |
| Peak memory | 610396 kb |
| Host | smart-4f80890f-9e5d-41df-8cc0-f3c8bac0baf2 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=15000000 +rng_srate_value_min=15 +rng_srate_value_max=30 +en_jitter=1 +sw_build_device=sim_dv +sw_images=e ntropy_src_edn_reqs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2597285872 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_edn_entropy_reqs_jitter.2597285872 |
| Directory | /workspace/0.chip_sw_edn_entropy_reqs_jitter/latest |
| Test location | /workspace/coverage/default/0.chip_sw_edn_kat.2790792713 |
| Short name | T1075 |
| Test name | |
| Test status | |
| Simulation time | 3181943560 ps |
| CPU time | 696.45 seconds |
| Started | Aug 13 07:10:59 PM PDT 24 |
| Finished | Aug 13 07:22:36 PM PDT 24 |
| Peak memory | 617216 kb |
| Host | smart-894f298f-9d5b-4afd-be56-e6ee35c94332 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +rng_srate_value=5 +disable_assert_edn_output_diff_from_prev=1 +accelerate_cold_power_up_time=3 +accelerate_regulators_power_up_time=2 +sw_build_device=sim_dv +sw_images=edn_kat:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2790792713 -assert nopostproc +UVM _TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm _log /dev/null -cm_name 0.chip_sw_edn_kat.2790792713 |
| Directory | /workspace/0.chip_sw_edn_kat/latest |
| Test location | /workspace/coverage/default/0.chip_sw_edn_sw_mode.277239843 |
| Short name | T1275 |
| Test name | |
| Test status | |
| Simulation time | 9449639744 ps |
| CPU time | 2522.68 seconds |
| Started | Aug 13 07:10:44 PM PDT 24 |
| Finished | Aug 13 07:52:47 PM PDT 24 |
| Peak memory | 610400 kb |
| Host | smart-647a139c-f6c7-4682-926c-0256bcd4920c |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=edn_sw_mode:1:new_rules,test_rom:0 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=277239843 -assert n opostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/d efault.vdb -cm_log /dev/null -cm_name 0.chip_sw_edn_sw_mode.277239843 |
| Directory | /workspace/0.chip_sw_edn_sw_mode/latest |
| Test location | /workspace/coverage/default/0.chip_sw_entropy_src_ast_rng_req.3353421966 |
| Short name | T1391 |
| Test name | |
| Test status | |
| Simulation time | 2433894966 ps |
| CPU time | 349.24 seconds |
| Started | Aug 13 07:12:43 PM PDT 24 |
| Finished | Aug 13 07:18:32 PM PDT 24 |
| Peak memory | 610420 kb |
| Host | smart-4046eea5-ca02-4d6e-b0fc-a08c8218e865 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=15_000_000 +sw_build_device=sim_dv +sw_images=entropy_src_ast_rng_req_test:1:new_rules,test_rom:0 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33 53421966 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_entropy_src_ast_rng_req.3353421966 |
| Directory | /workspace/0.chip_sw_entropy_src_ast_rng_req/latest |
| Test location | /workspace/coverage/default/0.chip_sw_entropy_src_kat_test.3755551269 |
| Short name | T1406 |
| Test name | |
| Test status | |
| Simulation time | 2329596238 ps |
| CPU time | 227.88 seconds |
| Started | Aug 13 07:10:28 PM PDT 24 |
| Finished | Aug 13 07:14:16 PM PDT 24 |
| Peak memory | 610344 kb |
| Host | smart-691185d2-09d3-4671-a8f2-2ce1eeca0761 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=entropy_src_kat_test:1:new_rules,test_rom:0 +cdc_instrumenta tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3755551269 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/ coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_entropy_src_kat_test.3755551269 |
| Directory | /workspace/0.chip_sw_entropy_src_kat_test/latest |
| Test location | /workspace/coverage/default/0.chip_sw_entropy_src_smoketest.2286668703 |
| Short name | T1028 |
| Test name | |
| Test status | |
| Simulation time | 2916593432 ps |
| CPU time | 449.53 seconds |
| Started | Aug 13 07:14:34 PM PDT 24 |
| Finished | Aug 13 07:22:05 PM PDT 24 |
| Peak memory | 610492 kb |
| Host | smart-c73383e1-c7af-4d8a-95c0-8563288d8b15 |
| User | root |
| Command | /workspace/default/simv +rng_srate_value_min=15 +rng_srate_value_max=30 +sw_build_device=sim_dv +sw_images=entropy_src_smoketest:1:new_rules,test_rom: 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand om_seed=2286668703 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_entropy_src_smoketest.2286668703 |
| Directory | /workspace/0.chip_sw_entropy_src_smoketest/latest |
| Test location | /workspace/coverage/default/0.chip_sw_example_concurrency.2556745628 |
| Short name | T946 |
| Test name | |
| Test status | |
| Simulation time | 3107847854 ps |
| CPU time | 299.43 seconds |
| Started | Aug 13 07:11:05 PM PDT 24 |
| Finished | Aug 13 07:16:05 PM PDT 24 |
| Peak memory | 610464 kb |
| Host | smart-c9c57875-6ca9-4bba-8bef-c418f0772e0d |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=example_concurrency_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2556745628 -assert nopostproc +UVM_TE STNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_lo g /dev/null -cm_name 0.chip_sw_example_concurrency.2556745628 |
| Directory | /workspace/0.chip_sw_example_concurrency/latest |
| Test location | /workspace/coverage/default/0.chip_sw_example_flash.3287768585 |
| Short name | T1270 |
| Test name | |
| Test status | |
| Simulation time | 2880276436 ps |
| CPU time | 241.98 seconds |
| Started | Aug 13 07:09:41 PM PDT 24 |
| Finished | Aug 13 07:13:44 PM PDT 24 |
| Peak memory | 610112 kb |
| Host | smart-2dce0f0c-723c-402e-b58b-48aa902d104b |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=example_test_from_flash:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3287768585 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_example_flash.3287768585 |
| Directory | /workspace/0.chip_sw_example_flash/latest |
| Test location | /workspace/coverage/default/0.chip_sw_example_manufacturer.2258273960 |
| Short name | T1301 |
| Test name | |
| Test status | |
| Simulation time | 2576324688 ps |
| CPU time | 168.24 seconds |
| Started | Aug 13 07:08:40 PM PDT 24 |
| Finished | Aug 13 07:11:29 PM PDT 24 |
| Peak memory | 610532 kb |
| Host | smart-6bea0125-176c-4d39-a664-5f5c596b684b |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=example_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2258273960 -assert nopostproc +UVM_TESTNAME=chip_ base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_example_manufacturer.2258273960 |
| Directory | /workspace/0.chip_sw_example_manufacturer/latest |
| Test location | /workspace/coverage/default/0.chip_sw_example_rom.2339520577 |
| Short name | T972 |
| Test name | |
| Test status | |
| Simulation time | 2809286824 ps |
| CPU time | 129.76 seconds |
| Started | Aug 13 07:08:57 PM PDT 24 |
| Finished | Aug 13 07:11:07 PM PDT 24 |
| Peak memory | 610004 kb |
| Host | smart-a487a58f-9703-4407-a2bd-96fbf809dc89 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=example_test_from_rom:0:test_in_rom:new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2339520577 -assert nopostproc +UVM_TEST NAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_example_rom.2339520577 |
| Directory | /workspace/0.chip_sw_example_rom/latest |
| Test location | /workspace/coverage/default/0.chip_sw_exit_test_unlocked_bootstrap.1956142946 |
| Short name | T1393 |
| Test name | |
| Test status | |
| Simulation time | 59320722087 ps |
| CPU time | 11684.8 seconds |
| Started | Aug 13 07:09:31 PM PDT 24 |
| Finished | Aug 13 10:24:18 PM PDT 24 |
| Peak memory | 625212 kb |
| Host | smart-97e28073-07d5-47cb-9f83-51db4df94eea |
| User | root |
| Command | /workspace/default/simv +flash_program_latency=5 +sw_test_timeout_ns=150_000_000 +sw_build_device=sim_dv +sw_images=exit_test_unlocked_bootstrap:1:new _rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/s im.tcl +ntb_random_seed=1956142946 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_exit_test_unlocked_bootstrap_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_exit_test_unlocked_bootstrap.1956142946 |
| Directory | /workspace/0.chip_sw_exit_test_unlocked_bootstrap/latest |
| Test location | /workspace/coverage/default/0.chip_sw_flash_crash_alert.510878610 |
| Short name | T1016 |
| Test name | |
| Test status | |
| Simulation time | 5271511614 ps |
| CPU time | 826.62 seconds |
| Started | Aug 13 07:12:36 PM PDT 24 |
| Finished | Aug 13 07:26:23 PM PDT 24 |
| Peak memory | 611836 kb |
| Host | smart-eb7fade2-14ad-4d2d-8467-00dd5511f9dd |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=8_000_000 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1: new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tool s/sim.tcl +ntb_random_seed=510878610 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_flash_host_gnt_err_inj_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_flash_crash_alert.510878610 |
| Directory | /workspace/0.chip_sw_flash_crash_alert/latest |
| Test location | /workspace/coverage/default/0.chip_sw_flash_ctrl_access.1663098514 |
| Short name | T975 |
| Test name | |
| Test status | |
| Simulation time | 5759738548 ps |
| CPU time | 1131.37 seconds |
| Started | Aug 13 07:09:52 PM PDT 24 |
| Finished | Aug 13 07:28:43 PM PDT 24 |
| Peak memory | 610852 kb |
| Host | smart-c5b0ba95-1e70-4d2e-a4fa-497f417a2ffe |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=flash_ctrl_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1663098514 -assert nopostproc +UVM_TESTNAME=ch ip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu ll -cm_name 0.chip_sw_flash_ctrl_access.1663098514 |
| Directory | /workspace/0.chip_sw_flash_ctrl_access/latest |
| Test location | /workspace/coverage/default/0.chip_sw_flash_ctrl_access_jitter_en.3940332175 |
| Short name | T103 |
| Test name | |
| Test status | |
| Simulation time | 5858277001 ps |
| CPU time | 1336.7 seconds |
| Started | Aug 13 07:10:10 PM PDT 24 |
| Finished | Aug 13 07:32:27 PM PDT 24 |
| Peak memory | 610864 kb |
| Host | smart-79a83b6e-5dc0-4dbf-8529-e5f89ddfe40f |
| User | root |
| Command | /workspace/default/simv +en_jitter=1 +sw_build_device=sim_dv +sw_images=flash_ctrl_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3940332175 -assert nopostproc +UV M_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -c m_log /dev/null -cm_name 0.chip_sw_flash_ctrl_access_jitter_en.3940332175 |
| Directory | /workspace/0.chip_sw_flash_ctrl_access_jitter_en/latest |
| Test location | /workspace/coverage/default/0.chip_sw_flash_ctrl_access_jitter_en_reduced_freq.4250563388 |
| Short name | T1131 |
| Test name | |
| Test status | |
| Simulation time | 7107148330 ps |
| CPU time | 1203.07 seconds |
| Started | Aug 13 07:14:36 PM PDT 24 |
| Finished | Aug 13 07:34:40 PM PDT 24 |
| Peak memory | 610844 kb |
| Host | smart-772f8d3b-9863-4ba6-ac42-8c202bcd4777 |
| User | root |
| Command | /workspace/default/simv +en_jitter=1 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=flash_ctrl_test:1:new_rules,test_rom:0 +cdc_instrumentati on_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4250563388 - assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co verage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_flash_ctrl_access_jitter_en_reduced_freq.4250563388 |
| Directory | /workspace/0.chip_sw_flash_ctrl_access_jitter_en_reduced_freq/latest |
| Test location | /workspace/coverage/default/0.chip_sw_flash_ctrl_clock_freqs.1358570221 |
| Short name | T308 |
| Test name | |
| Test status | |
| Simulation time | 5067871893 ps |
| CPU time | 1127.6 seconds |
| Started | Aug 13 07:11:06 PM PDT 24 |
| Finished | Aug 13 07:29:54 PM PDT 24 |
| Peak memory | 610792 kb |
| Host | smart-c03f9dc0-1447-4438-837b-0bad7fa157cd |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=flash_ctrl_clock_freqs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1358570221 -assert nopostproc +UVM _TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm _log /dev/null -cm_name 0.chip_sw_flash_ctrl_clock_freqs.1358570221 |
| Directory | /workspace/0.chip_sw_flash_ctrl_clock_freqs/latest |
| Test location | /workspace/coverage/default/0.chip_sw_flash_ctrl_idle_low_power.845493284 |
| Short name | T345 |
| Test name | |
| Test status | |
| Simulation time | 3691971792 ps |
| CPU time | 359.06 seconds |
| Started | Aug 13 07:08:49 PM PDT 24 |
| Finished | Aug 13 07:14:48 PM PDT 24 |
| Peak memory | 610424 kb |
| Host | smart-3cfb037c-2081-420d-b98b-4b879901e2f6 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=flash_ctrl_idle_low_power_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=845493284 -assert nopostproc +U VM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb - cm_log /dev/null -cm_name 0.chip_sw_flash_ctrl_idle_low_power.845493284 |
| Directory | /workspace/0.chip_sw_flash_ctrl_idle_low_power/latest |
| Test location | /workspace/coverage/default/0.chip_sw_flash_ctrl_lc_rw_en.4238421970 |
| Short name | T246 |
| Test name | |
| Test status | |
| Simulation time | 4898017404 ps |
| CPU time | 610.42 seconds |
| Started | Aug 13 07:10:30 PM PDT 24 |
| Finished | Aug 13 07:20:42 PM PDT 24 |
| Peak memory | 611608 kb |
| Host | smart-16951dc5-6c05-4657-b093-477323bd6857 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=flash_ctrl_lc_rw_en_test:1:new_rules,test_rom:0 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42 38421970 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_flash_ctrl_lc_rw_en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_flash_ctrl_lc_rw_en.4238421970 |
| Directory | /workspace/0.chip_sw_flash_ctrl_lc_rw_en/latest |
| Test location | /workspace/coverage/default/0.chip_sw_flash_ctrl_mem_protection.3636850547 |
| Short name | T1096 |
| Test name | |
| Test status | |
| Simulation time | 5322981078 ps |
| CPU time | 1266.41 seconds |
| Started | Aug 13 07:12:49 PM PDT 24 |
| Finished | Aug 13 07:33:56 PM PDT 24 |
| Peak memory | 610408 kb |
| Host | smart-d64772cb-1fa6-4e7a-b4a0-8417c4e91e9c |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=flash_ctrl_mem_protection_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3636850547 -assert nopostproc + UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_flash_ctrl_mem_protection.3636850547 |
| Directory | /workspace/0.chip_sw_flash_ctrl_mem_protection/latest |
| Test location | /workspace/coverage/default/0.chip_sw_flash_ctrl_ops.94912478 |
| Short name | T1229 |
| Test name | |
| Test status | |
| Simulation time | 3871943464 ps |
| CPU time | 541.71 seconds |
| Started | Aug 13 07:08:44 PM PDT 24 |
| Finished | Aug 13 07:17:46 PM PDT 24 |
| Peak memory | 610516 kb |
| Host | smart-16b83147-85f9-49e1-93aa-4fe55e4cc003 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=50_000_000 +sw_build_device=sim_dv +sw_images=flash_ctrl_ops_test:1:new_rules,test_rom:0 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=94912478 -a ssert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov erage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_flash_ctrl_ops.94912478 |
| Directory | /workspace/0.chip_sw_flash_ctrl_ops/latest |
| Test location | /workspace/coverage/default/0.chip_sw_flash_ctrl_ops_jitter_en.2536306144 |
| Short name | T352 |
| Test name | |
| Test status | |
| Simulation time | 4249531793 ps |
| CPU time | 574.67 seconds |
| Started | Aug 13 07:09:04 PM PDT 24 |
| Finished | Aug 13 07:18:39 PM PDT 24 |
| Peak memory | 610580 kb |
| Host | smart-01e6c923-db26-499a-b02c-693291c05bac |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=50_000_000 +en_jitter=1 +sw_build_device=sim_dv +sw_images=flash_ctrl_ops_test:1:new_rules,test_rom:0 +cdc _instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see d=2536306144 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_flash_ctrl_ops_jitter_en.2536306144 |
| Directory | /workspace/0.chip_sw_flash_ctrl_ops_jitter_en/latest |
| Test location | /workspace/coverage/default/0.chip_sw_flash_ctrl_write_clear.3515269809 |
| Short name | T1022 |
| Test name | |
| Test status | |
| Simulation time | 3199251678 ps |
| CPU time | 372.98 seconds |
| Started | Aug 13 07:14:55 PM PDT 24 |
| Finished | Aug 13 07:21:09 PM PDT 24 |
| Peak memory | 610512 kb |
| Host | smart-3b028392-8986-4e78-b939-4fc0e5ffdae8 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=8_000_000 +sw_build_device=sim_dv +sw_images=flash_ctrl_write_clear_test:1:new_rules,test_rom:0 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3515269 809 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ce/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_flash_ctrl_write_clear.3515269809 |
| Directory | /workspace/0.chip_sw_flash_ctrl_write_clear/latest |
| Test location | /workspace/coverage/default/0.chip_sw_flash_init.135681589 |
| Short name | T1277 |
| Test name | |
| Test status | |
| Simulation time | 19533234900 ps |
| CPU time | 2126.69 seconds |
| Started | Aug 13 07:11:48 PM PDT 24 |
| Finished | Aug 13 07:47:17 PM PDT 24 |
| Peak memory | 613996 kb |
| Host | smart-ceb3cf36-25f8-49fc-b505-1e705d8692b5 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=25_000_000 +sw_build_device=sim_dv +sw_images=flash_init_test:0:test_in_rom:new_rules +cdc_instrumentation _enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=135681589 -ass ert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_flash_init_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace /coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_flash_init.135681589 |
| Directory | /workspace/0.chip_sw_flash_init/latest |
| Test location | /workspace/coverage/default/0.chip_sw_flash_init_reduced_freq.1988946607 |
| Short name | T241 |
| Test name | |
| Test status | |
| Simulation time | 21524222495 ps |
| CPU time | 2498 seconds |
| Started | Aug 13 07:11:55 PM PDT 24 |
| Finished | Aug 13 07:53:34 PM PDT 24 |
| Peak memory | 614544 kb |
| Host | smart-ef2e6abe-8783-4e1a-b2fe-719d1e61f530 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=25_000_000 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=flash_init_test:0:test_in_rom:new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=1988946607 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_flash_init_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_flash_init_reduced_freq.1988946607 |
| Directory | /workspace/0.chip_sw_flash_init_reduced_freq/latest |
| Test location | /workspace/coverage/default/0.chip_sw_flash_scrambling_smoketest.1152918100 |
| Short name | T94 |
| Test name | |
| Test status | |
| Simulation time | 2891668740 ps |
| CPU time | 258.59 seconds |
| Started | Aug 13 07:18:18 PM PDT 24 |
| Finished | Aug 13 07:22:37 PM PDT 24 |
| Peak memory | 609812 kb |
| Host | smart-9daceb99-15c5-4a08-9cc7-3592e79a4540 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=flash_scrambling_smoketest:1:new_rules,flash_scrambling_smoket est_otp_img_rma:4,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=1152918100 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_flash_scrambling_smoketest.1152918100 |
| Directory | /workspace/0.chip_sw_flash_scrambling_smoketest/latest |
| Test location | /workspace/coverage/default/0.chip_sw_gpio_smoketest.3084905782 |
| Short name | T1237 |
| Test name | |
| Test status | |
| Simulation time | 3095902708 ps |
| CPU time | 357.38 seconds |
| Started | Aug 13 07:14:51 PM PDT 24 |
| Finished | Aug 13 07:20:49 PM PDT 24 |
| Peak memory | 610560 kb |
| Host | smart-16e86a75-ed36-40d8-b81e-b0fd388edf34 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=gpio_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3084905782 -assert nopostproc +UVM_TESTNAME=chi p_base_test +UVM_TEST_SEQ=chip_sw_gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 0.chip_sw_gpio_smoketest.3084905782 |
| Directory | /workspace/0.chip_sw_gpio_smoketest/latest |
| Test location | /workspace/coverage/default/0.chip_sw_hmac_enc.2323492618 |
| Short name | T1204 |
| Test name | |
| Test status | |
| Simulation time | 2994102504 ps |
| CPU time | 231.2 seconds |
| Started | Aug 13 07:11:28 PM PDT 24 |
| Finished | Aug 13 07:15:19 PM PDT 24 |
| Peak memory | 610340 kb |
| Host | smart-215ad8e8-56ed-444c-971a-1bfc925eaa62 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=hmac_enc_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2323492618 -assert nopostproc +UVM_TESTNAME=chip _base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_hmac_enc.2323492618 |
| Directory | /workspace/0.chip_sw_hmac_enc/latest |
| Test location | /workspace/coverage/default/0.chip_sw_hmac_enc_idle.292300125 |
| Short name | T1156 |
| Test name | |
| Test status | |
| Simulation time | 3300903898 ps |
| CPU time | 328.13 seconds |
| Started | Aug 13 07:11:39 PM PDT 24 |
| Finished | Aug 13 07:17:08 PM PDT 24 |
| Peak memory | 610388 kb |
| Host | smart-52e54a92-278c-41cf-91e7-0386d4e83b51 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=hmac_enc_idle_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=292300125 -assert nopostproc +UVM_TESTNAME= chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/ null -cm_name 0.chip_sw_hmac_enc_idle.292300125 |
| Directory | /workspace/0.chip_sw_hmac_enc_idle/latest |
| Test location | /workspace/coverage/default/0.chip_sw_hmac_enc_jitter_en.3198058969 |
| Short name | T372 |
| Test name | |
| Test status | |
| Simulation time | 3482107510 ps |
| CPU time | 319.69 seconds |
| Started | Aug 13 07:10:53 PM PDT 24 |
| Finished | Aug 13 07:16:13 PM PDT 24 |
| Peak memory | 610244 kb |
| Host | smart-093845eb-5c7d-4f45-80b7-1eee1725ccdb |
| User | root |
| Command | /workspace/default/simv +en_jitter=1 +sw_build_device=sim_dv +sw_images=hmac_enc_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3198058969 -assert nopostproc +UVM_ TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_ log /dev/null -cm_name 0.chip_sw_hmac_enc_jitter_en.3198058969 |
| Directory | /workspace/0.chip_sw_hmac_enc_jitter_en/latest |
| Test location | /workspace/coverage/default/0.chip_sw_hmac_enc_jitter_en_reduced_freq.1350242791 |
| Short name | T1413 |
| Test name | |
| Test status | |
| Simulation time | 3691657905 ps |
| CPU time | 241.37 seconds |
| Started | Aug 13 07:09:55 PM PDT 24 |
| Finished | Aug 13 07:13:57 PM PDT 24 |
| Peak memory | 609200 kb |
| Host | smart-7d89aef9-3d39-4b6b-9f97-4eba18c926cf |
| User | root |
| Command | /workspace/default/simv +en_jitter=1 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=hmac_enc_test:1:new_rules,test_rom:0 +cdc_instrumentation _enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1350242791 -as sert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove rage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_hmac_enc_jitter_en_reduced_freq.1350242791 |
| Directory | /workspace/0.chip_sw_hmac_enc_jitter_en_reduced_freq/latest |
| Test location | /workspace/coverage/default/0.chip_sw_hmac_multistream.1767787349 |
| Short name | T1253 |
| Test name | |
| Test status | |
| Simulation time | 7557643370 ps |
| CPU time | 2019.62 seconds |
| Started | Aug 13 07:12:05 PM PDT 24 |
| Finished | Aug 13 07:45:45 PM PDT 24 |
| Peak memory | 610836 kb |
| Host | smart-60d7a621-5951-4135-b3ca-5880c07b229f |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=hmac_multistream_functest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1767787349 -assert nopostproc +UVM_T ESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l og /dev/null -cm_name 0.chip_sw_hmac_multistream.1767787349 |
| Directory | /workspace/0.chip_sw_hmac_multistream/latest |
| Test location | /workspace/coverage/default/0.chip_sw_hmac_oneshot.1320371491 |
| Short name | T1027 |
| Test name | |
| Test status | |
| Simulation time | 3530891624 ps |
| CPU time | 396.58 seconds |
| Started | Aug 13 07:11:25 PM PDT 24 |
| Finished | Aug 13 07:18:02 PM PDT 24 |
| Peak memory | 610300 kb |
| Host | smart-49e7d3cd-1661-45b9-990f-2676f7924e3a |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=hmac_functest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1320371491 -assert nopostproc +UVM_TESTNAME=chip _base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_hmac_oneshot.1320371491 |
| Directory | /workspace/0.chip_sw_hmac_oneshot/latest |
| Test location | /workspace/coverage/default/0.chip_sw_hmac_smoketest.2676612251 |
| Short name | T940 |
| Test name | |
| Test status | |
| Simulation time | 2841538668 ps |
| CPU time | 316.64 seconds |
| Started | Aug 13 07:18:28 PM PDT 24 |
| Finished | Aug 13 07:23:45 PM PDT 24 |
| Peak memory | 610292 kb |
| Host | smart-53c046d1-15eb-4a8a-b8f0-f940e71ac6a1 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=hmac_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2676612251 -assert nopostproc +UVM_TESTNAME=chi p_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul l -cm_name 0.chip_sw_hmac_smoketest.2676612251 |
| Directory | /workspace/0.chip_sw_hmac_smoketest/latest |
| Test location | /workspace/coverage/default/0.chip_sw_i2c_device_tx_rx.31263571 |
| Short name | T344 |
| Test name | |
| Test status | |
| Simulation time | 4294978152 ps |
| CPU time | 579.89 seconds |
| Started | Aug 13 07:12:32 PM PDT 24 |
| Finished | Aug 13 07:22:14 PM PDT 24 |
| Peak memory | 610552 kb |
| Host | smart-f20557b5-6865-4de3-93c5-132c9b092672 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=i2c_device_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31263571 -assert nopostproc +UVM_TESTNAM E=chip_base_test +UVM_TEST_SEQ=chip_sw_i2c_device_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_i2c_device_tx_rx.31263571 |
| Directory | /workspace/0.chip_sw_i2c_device_tx_rx/latest |
| Test location | /workspace/coverage/default/0.chip_sw_i2c_host_tx_rx.2448701711 |
| Short name | T1366 |
| Test name | |
| Test status | |
| Simulation time | 5711630408 ps |
| CPU time | 631.41 seconds |
| Started | Aug 13 07:08:31 PM PDT 24 |
| Finished | Aug 13 07:19:02 PM PDT 24 |
| Peak memory | 611000 kb |
| Host | smart-32e17607-dcf9-4fb9-af05-7e776aabeb89 |
| User | root |
| Command | /workspace/default/simv +i2c_idx=0 +sw_build_device=sim_dv +sw_images=i2c_host_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2448701711 -assert nopostproc + UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_i2c_host_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de fault.vdb -cm_log /dev/null -cm_name 0.chip_sw_i2c_host_tx_rx.2448701711 |
| Directory | /workspace/0.chip_sw_i2c_host_tx_rx/latest |
| Test location | /workspace/coverage/default/0.chip_sw_i2c_host_tx_rx_idx2.1405249709 |
| Short name | T1231 |
| Test name | |
| Test status | |
| Simulation time | 5499608890 ps |
| CPU time | 1049.08 seconds |
| Started | Aug 13 07:10:22 PM PDT 24 |
| Finished | Aug 13 07:27:52 PM PDT 24 |
| Peak memory | 610992 kb |
| Host | smart-c3105c65-1454-404c-821f-47ff4ccfe18a |
| User | root |
| Command | /workspace/default/simv +i2c_idx=2 +sw_build_device=sim_dv +sw_images=i2c_host_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1405249709 -assert nopostproc + UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_i2c_host_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de fault.vdb -cm_log /dev/null -cm_name 0.chip_sw_i2c_host_tx_rx_idx2.1405249709 |
| Directory | /workspace/0.chip_sw_i2c_host_tx_rx_idx2/latest |
| Test location | /workspace/coverage/default/0.chip_sw_inject_scramble_seed.486269286 |
| Short name | T82 |
| Test name | |
| Test status | |
| Simulation time | 63871535909 ps |
| CPU time | 11808.2 seconds |
| Started | Aug 13 07:12:00 PM PDT 24 |
| Finished | Aug 13 10:28:50 PM PDT 24 |
| Peak memory | 625240 kb |
| Host | smart-1f16b108-08b8-41d7-bc8a-f5020a5f37cc |
| User | root |
| Command | /workspace/default/simv +lc_at_prod=1 +flash_program_latency=5 +sw_test_timeout_ns=150_000_000 +sw_build_device=sim_dv +sw_images=inject_scramble_seed :1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=486269286 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_inject_scramble_seed_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_inject_scramble_seed.486269286 |
| Directory | /workspace/0.chip_sw_inject_scramble_seed/latest |
| Test location | /workspace/coverage/default/0.chip_sw_keymgr_key_derivation.3920202911 |
| Short name | T1177 |
| Test name | |
| Test status | |
| Simulation time | 8375225590 ps |
| CPU time | 1633.46 seconds |
| Started | Aug 13 07:11:04 PM PDT 24 |
| Finished | Aug 13 07:38:18 PM PDT 24 |
| Peak memory | 618468 kb |
| Host | smart-29a56c30-8d74-41af-aa1d-b42388289e08 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=20_000_000 +sw_build_device=sim_dv +sw_images=keymgr_key_derivation_test:1:new_rules,test_rom:0 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3920 202911 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_keymgr_key_derivation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_keymgr_key_derivation.3920202911 |
| Directory | /workspace/0.chip_sw_keymgr_key_derivation/latest |
| Test location | /workspace/coverage/default/0.chip_sw_keymgr_key_derivation_jitter_en.3449042425 |
| Short name | T448 |
| Test name | |
| Test status | |
| Simulation time | 9292006373 ps |
| CPU time | 1407.73 seconds |
| Started | Aug 13 07:12:43 PM PDT 24 |
| Finished | Aug 13 07:36:12 PM PDT 24 |
| Peak memory | 618508 kb |
| Host | smart-1494b73c-aa11-4d81-a117-56e3d80f6e1b |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=20_000_000 +en_jitter=1 +sw_build_device=sim_dv +sw_images=keymgr_key_derivation_test:1:new_rules,test_rom :0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=3449042425 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_keymgr_key_derivation_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_keymgr_key_derivation_jitter_en.3449042425 |
| Directory | /workspace/0.chip_sw_keymgr_key_derivation_jitter_en/latest |
| Test location | /workspace/coverage/default/0.chip_sw_keymgr_key_derivation_jitter_en_reduced_freq.3035741685 |
| Short name | T1138 |
| Test name | |
| Test status | |
| Simulation time | 12804439506 ps |
| CPU time | 2203.26 seconds |
| Started | Aug 13 07:15:43 PM PDT 24 |
| Finished | Aug 13 07:52:26 PM PDT 24 |
| Peak memory | 618564 kb |
| Host | smart-9d095ecf-da3d-4238-96b7-f66b35b11d42 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=20_000_000 +en_jitter=1 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=keymgr_key_derivation_test :1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=3035741685 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_keymgr_key_derivation_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_keymgr_key_derivation_jitter_en _reduced_freq.3035741685 |
| Directory | /workspace/0.chip_sw_keymgr_key_derivation_jitter_en_reduced_freq/latest |
| Test location | /workspace/coverage/default/0.chip_sw_keymgr_key_derivation_prod.98491058 |
| Short name | T1409 |
| Test name | |
| Test status | |
| Simulation time | 6469787232 ps |
| CPU time | 1061.59 seconds |
| Started | Aug 13 07:10:53 PM PDT 24 |
| Finished | Aug 13 07:28:35 PM PDT 24 |
| Peak memory | 618800 kb |
| Host | smart-a553ac62-40c3-4eb1-868b-7afa2255f2c4 |
| User | root |
| Command | /workspace/default/simv +lc_at_prod=1 +sw_test_timeout_ns=20_000_000 +sw_build_device=sim_dv +sw_images=keymgr_key_derivation_test:1:new_rules,test_ro m:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=98491058 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_keymgr_key_derivation_vseq +en_cov=1 -cm line+cond+fsm+tg l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_keymgr_key_derivation_prod.98491058 |
| Directory | /workspace/0.chip_sw_keymgr_key_derivation_prod/latest |
| Test location | /workspace/coverage/default/0.chip_sw_keymgr_sideload_kmac.2143932197 |
| Short name | T1259 |
| Test name | |
| Test status | |
| Simulation time | 7218777904 ps |
| CPU time | 1178.24 seconds |
| Started | Aug 13 07:14:10 PM PDT 24 |
| Finished | Aug 13 07:33:49 PM PDT 24 |
| Peak memory | 611984 kb |
| Host | smart-1df70499-c455-4110-82dc-4e0332e2e6f4 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=20_000_000 +sw_build_device=sim_dv +sw_images=keymgr_sideload_kmac_test:1:new_rules,test_rom:0 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21439 32197 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_keymgr_sideload_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_keymgr_sideload_kmac.2143932197 |
| Directory | /workspace/0.chip_sw_keymgr_sideload_kmac/latest |
| Test location | /workspace/coverage/default/0.chip_sw_kmac_app_rom.51141491 |
| Short name | T1145 |
| Test name | |
| Test status | |
| Simulation time | 3103807736 ps |
| CPU time | 260.27 seconds |
| Started | Aug 13 07:10:12 PM PDT 24 |
| Finished | Aug 13 07:14:33 PM PDT 24 |
| Peak memory | 610308 kb |
| Host | smart-d237478a-29a3-4356-97f5-4285fc296a0b |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=kmac_app_rom_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=51141491 -assert nopostproc +UVM_TESTNAME=ch ip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu ll -cm_name 0.chip_sw_kmac_app_rom.51141491 |
| Directory | /workspace/0.chip_sw_kmac_app_rom/latest |
| Test location | /workspace/coverage/default/0.chip_sw_kmac_entropy.79686893 |
| Short name | T1315 |
| Test name | |
| Test status | |
| Simulation time | 3465352160 ps |
| CPU time | 352.45 seconds |
| Started | Aug 13 07:10:17 PM PDT 24 |
| Finished | Aug 13 07:16:10 PM PDT 24 |
| Peak memory | 610216 kb |
| Host | smart-701b30e1-a7cd-4986-bdf5-c8f1b22c3767 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=kmac_entropy_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=79686893 -assert nopostproc +UVM_TESTNAME=ch ip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu ll -cm_name 0.chip_sw_kmac_entropy.79686893 |
| Directory | /workspace/0.chip_sw_kmac_entropy/latest |
| Test location | /workspace/coverage/default/0.chip_sw_kmac_mode_cshake.3120819251 |
| Short name | T995 |
| Test name | |
| Test status | |
| Simulation time | 3622805102 ps |
| CPU time | 278.62 seconds |
| Started | Aug 13 07:09:34 PM PDT 24 |
| Finished | Aug 13 07:14:13 PM PDT 24 |
| Peak memory | 610444 kb |
| Host | smart-13c44cc0-b968-491e-a620-e3e196f2935c |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=kmac_mode_cshake_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3120819251 -assert nopostproc +UVM_TESTN AME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log / dev/null -cm_name 0.chip_sw_kmac_mode_cshake.3120819251 |
| Directory | /workspace/0.chip_sw_kmac_mode_cshake/latest |
| Test location | /workspace/coverage/default/0.chip_sw_kmac_mode_kmac.1239960274 |
| Short name | T459 |
| Test name | |
| Test status | |
| Simulation time | 3104325066 ps |
| CPU time | 312.49 seconds |
| Started | Aug 13 07:10:51 PM PDT 24 |
| Finished | Aug 13 07:16:04 PM PDT 24 |
| Peak memory | 610296 kb |
| Host | smart-cf9365b5-b9b6-4344-ac00-e4863b9608cc |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=kmac_mode_kmac_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1239960274 -assert nopostproc +UVM_TESTNAM E=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 0.chip_sw_kmac_mode_kmac.1239960274 |
| Directory | /workspace/0.chip_sw_kmac_mode_kmac/latest |
| Test location | /workspace/coverage/default/0.chip_sw_kmac_mode_kmac_jitter_en.3233563242 |
| Short name | T1055 |
| Test name | |
| Test status | |
| Simulation time | 2934190520 ps |
| CPU time | 280.24 seconds |
| Started | Aug 13 07:10:10 PM PDT 24 |
| Finished | Aug 13 07:14:50 PM PDT 24 |
| Peak memory | 610284 kb |
| Host | smart-ea4472e0-d1c2-44c6-a01e-3ba6c182395c |
| User | root |
| Command | /workspace/default/simv +en_jitter=1 +sw_build_device=sim_dv +sw_images=kmac_mode_kmac_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3233563242 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd b -cm_log /dev/null -cm_name 0.chip_sw_kmac_mode_kmac_jitter_en.3233563242 |
| Directory | /workspace/0.chip_sw_kmac_mode_kmac_jitter_en/latest |
| Test location | /workspace/coverage/default/0.chip_sw_kmac_mode_kmac_jitter_en_reduced_freq.3539671539 |
| Short name | T1043 |
| Test name | |
| Test status | |
| Simulation time | 2804075132 ps |
| CPU time | 366.01 seconds |
| Started | Aug 13 07:15:16 PM PDT 24 |
| Finished | Aug 13 07:21:23 PM PDT 24 |
| Peak memory | 610468 kb |
| Host | smart-99ff84c9-3980-45ad-a375-c19e314b7cae |
| User | root |
| Command | /workspace/default/simv +en_jitter=1 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=kmac_mode_kmac_test:1:new_rules,test_rom:0 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35396715 39 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac e/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_kmac_mode_kmac_jitter_en_reduced_freq.3539671539 |
| Directory | /workspace/0.chip_sw_kmac_mode_kmac_jitter_en_reduced_freq/latest |
| Test location | /workspace/coverage/default/0.chip_sw_kmac_smoketest.2899789272 |
| Short name | T1235 |
| Test name | |
| Test status | |
| Simulation time | 3850810956 ps |
| CPU time | 370.38 seconds |
| Started | Aug 13 07:13:53 PM PDT 24 |
| Finished | Aug 13 07:20:04 PM PDT 24 |
| Peak memory | 610500 kb |
| Host | smart-39616c7c-93ed-45e2-98ce-7617fe676c03 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=kmac_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2899789272 -assert nopostproc +UVM_TESTNAME=chi p_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul l -cm_name 0.chip_sw_kmac_smoketest.2899789272 |
| Directory | /workspace/0.chip_sw_kmac_smoketest/latest |
| Test location | /workspace/coverage/default/0.chip_sw_lc_ctrl_otp_hw_cfg0.631347338 |
| Short name | T1266 |
| Test name | |
| Test status | |
| Simulation time | 3273801610 ps |
| CPU time | 378.23 seconds |
| Started | Aug 13 07:10:51 PM PDT 24 |
| Finished | Aug 13 07:17:10 PM PDT 24 |
| Peak memory | 610308 kb |
| Host | smart-070c32b3-c7c1-4c57-98af-4a96631c3f6b |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=lc_ctrl_otp_hw_cfg0_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=631347338 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_lc_ctrl_otp_hw_cfg0.631347338 |
| Directory | /workspace/0.chip_sw_lc_ctrl_otp_hw_cfg0/latest |
| Test location | /workspace/coverage/default/0.chip_sw_lc_ctrl_rand_to_scrap.2443521123 |
| Short name | T1186 |
| Test name | |
| Test status | |
| Simulation time | 2876609857 ps |
| CPU time | 157.19 seconds |
| Started | Aug 13 07:09:03 PM PDT 24 |
| Finished | Aug 13 07:11:41 PM PDT 24 |
| Peak memory | 621708 kb |
| Host | smart-db75dbac-7a40-4eeb-b896-74e07bcfdc18 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=lc_ctrl_scrap_test:1:new_rules,test_rom:0 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24435211 23 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_scrap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_lc_ctrl_rand_to_scrap.2443521123 |
| Directory | /workspace/0.chip_sw_lc_ctrl_rand_to_scrap/latest |
| Test location | /workspace/coverage/default/0.chip_sw_lc_ctrl_rma_to_scrap.3439678057 |
| Short name | T1218 |
| Test name | |
| Test status | |
| Simulation time | 3894103090 ps |
| CPU time | 235.04 seconds |
| Started | Aug 13 07:14:20 PM PDT 24 |
| Finished | Aug 13 07:18:16 PM PDT 24 |
| Peak memory | 622084 kb |
| Host | smart-d65e2d68-860c-470f-99c4-e66e7c488d93 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +src_dec_state=DecLcStRma +sw_build_device=sim_dv +sw_images=lc_ctrl_scrap_test:1:new_rules ,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3439678057 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_scrap_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_lc_ctrl_rma_to_scrap.3439678057 |
| Directory | /workspace/0.chip_sw_lc_ctrl_rma_to_scrap/latest |
| Test location | /workspace/coverage/default/0.chip_sw_lc_ctrl_test_locked0_to_scrap.1404012372 |
| Short name | T431 |
| Test name | |
| Test status | |
| Simulation time | 3870863912 ps |
| CPU time | 162.93 seconds |
| Started | Aug 13 07:16:40 PM PDT 24 |
| Finished | Aug 13 07:19:24 PM PDT 24 |
| Peak memory | 620520 kb |
| Host | smart-d95dfeaa-eacd-439e-b653-6ee8f7b60731 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +src_dec_state=DecLcStTestLocked0 +sw_build_device=sim_dv +sw_images=lc_ctrl_scrap_test:1:n ew_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1404012372 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_scrap_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_lc_ctrl_test_locked0_to_scrap.1404012372 |
| Directory | /workspace/0.chip_sw_lc_ctrl_test_locked0_to_scrap/latest |
| Test location | /workspace/coverage/default/0.chip_sw_lc_ctrl_transition.826196953 |
| Short name | T1059 |
| Test name | |
| Test status | |
| Simulation time | 4954438953 ps |
| CPU time | 488.71 seconds |
| Started | Aug 13 07:09:03 PM PDT 24 |
| Finished | Aug 13 07:17:13 PM PDT 24 |
| Peak memory | 622128 kb |
| Host | smart-15d9ec10-f66c-4065-8e34-49799af241eb |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=lc_ctrl_transition_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=826196953 -assert nopostproc +UVM_TEST NAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_transition_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul t.vdb -cm_log /dev/null -cm_name 0.chip_sw_lc_ctrl_transition.826196953 |
| Directory | /workspace/0.chip_sw_lc_ctrl_transition/latest |
| Test location | /workspace/coverage/default/0.chip_sw_lc_ctrl_volatile_raw_unlock.520596336 |
| Short name | T304 |
| Test name | |
| Test status | |
| Simulation time | 2513061555 ps |
| CPU time | 116.34 seconds |
| Started | Aug 13 07:10:15 PM PDT 24 |
| Finished | Aug 13 07:12:12 PM PDT 24 |
| Peak memory | 617500 kb |
| Host | smart-2fa2193f-a2f9-4877-bb0d-98bdac73923c |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStRaw +exp_volatile_raw_unlock_en=0 +sw_build_device=sim_dv +sw_images=lc_ctrl_volatile_raw_unlock_tes t:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/ tools/sim.tcl +ntb_random_seed=520596336 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_volatile_raw_unlock_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_lc_ctrl_volatile_raw_unlock.520596336 |
| Directory | /workspace/0.chip_sw_lc_ctrl_volatile_raw_unlock/latest |
| Test location | /workspace/coverage/default/0.chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz.4185564306 |
| Short name | T279 |
| Test name | |
| Test status | |
| Simulation time | 2208449149 ps |
| CPU time | 122.53 seconds |
| Started | Aug 13 07:11:58 PM PDT 24 |
| Finished | Aug 13 07:14:01 PM PDT 24 |
| Peak memory | 618292 kb |
| Host | smart-d621176f-f545-47db-8615-62d071c04769 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStRaw +chip_clock_source=ChipClockSourceExternal48Mhz +exp_volatile_raw_unlock_en=0 +sw_build_device=s im_dv +sw_images=lc_ctrl_volatile_raw_unlock_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4185564306 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TES T_SEQ=chip_sw_lc_volatile_raw_unlock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz.4185564306 |
| Directory | /workspace/0.chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz/latest |
| Test location | /workspace/coverage/default/0.chip_sw_lc_walkthrough_dev.630080962 |
| Short name | T242 |
| Test name | |
| Test status | |
| Simulation time | 46603760665 ps |
| CPU time | 5058.63 seconds |
| Started | Aug 13 07:09:52 PM PDT 24 |
| Finished | Aug 13 08:34:11 PM PDT 24 |
| Peak memory | 621196 kb |
| Host | smart-9e71f490-d371-43c9-a0df-a6f2436e3cd1 |
| User | root |
| Command | /workspace/default/simv +flash_program_latency=5 +use_otp_image=OtpTypeLcStRaw +dest_dec_state=DecLcStDev +sw_test_timeout_ns=200_000_000 +sw_build_de vice=sim_dv +sw_images=lc_walkthrough_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=630080962 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=ch ip_sw_lc_walkthrough_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_ sw_lc_walkthrough_dev.630080962 |
| Directory | /workspace/0.chip_sw_lc_walkthrough_dev/latest |
| Test location | /workspace/coverage/default/0.chip_sw_lc_walkthrough_prodend.4145702295 |
| Short name | T1312 |
| Test name | |
| Test status | |
| Simulation time | 9191810680 ps |
| CPU time | 1236.53 seconds |
| Started | Aug 13 07:15:20 PM PDT 24 |
| Finished | Aug 13 07:35:58 PM PDT 24 |
| Peak memory | 619828 kb |
| Host | smart-9706d480-ef0a-4f2d-a775-c91337bcf302 |
| User | root |
| Command | /workspace/default/simv +flash_program_latency=5 +use_otp_image=OtpTypeLcStRaw +dest_dec_state=DecLcStProdEnd +sw_build_device=sim_dv +sw_images=lc_wa lkthrough_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=4145702295 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_walkthrough_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_lc_walkthrough_prodend.4145702295 |
| Directory | /workspace/0.chip_sw_lc_walkthrough_prodend/latest |
| Test location | /workspace/coverage/default/0.chip_sw_lc_walkthrough_rma.3787615670 |
| Short name | T244 |
| Test name | |
| Test status | |
| Simulation time | 46444846487 ps |
| CPU time | 5658.99 seconds |
| Started | Aug 13 07:09:15 PM PDT 24 |
| Finished | Aug 13 08:43:35 PM PDT 24 |
| Peak memory | 620860 kb |
| Host | smart-aca6e1b9-a383-4bc5-85fe-8fb0a0c9f1a4 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStRaw +dest_dec_state=DecLcStRma +flash_program_latency=5 +sw_test_timeout_ns=200_000_000 +sw_build_de vice=sim_dv +sw_images=lc_walkthrough_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3787615670 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=c hip_sw_lc_walkthrough_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip _sw_lc_walkthrough_rma.3787615670 |
| Directory | /workspace/0.chip_sw_lc_walkthrough_rma/latest |
| Test location | /workspace/coverage/default/0.chip_sw_lc_walkthrough_testunlocks.1307058667 |
| Short name | T1190 |
| Test name | |
| Test status | |
| Simulation time | 30561222207 ps |
| CPU time | 2490.06 seconds |
| Started | Aug 13 07:09:55 PM PDT 24 |
| Finished | Aug 13 07:51:26 PM PDT 24 |
| Peak memory | 624736 kb |
| Host | smart-0cf34269-8546-4361-b9ee-c09fcb7c5fdd |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStRaw +dest_dec_state=DecLcStTestUnlock7 +sw_build_device=sim_dv +sw_images=lc_walkthrough_testunlocks _test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=1307058667 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_walkthrough_testunlocks_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_lc_walkthrough_testun locks.1307058667 |
| Directory | /workspace/0.chip_sw_lc_walkthrough_testunlocks/latest |
| Test location | /workspace/coverage/default/0.chip_sw_otbn_ecdsa_op_irq_jitter_en.2200118632 |
| Short name | T1280 |
| Test name | |
| Test status | |
| Simulation time | 18333817098 ps |
| CPU time | 3557.77 seconds |
| Started | Aug 13 07:09:52 PM PDT 24 |
| Finished | Aug 13 08:09:10 PM PDT 24 |
| Peak memory | 611064 kb |
| Host | smart-b3cf78dc-fbf4-43b9-936a-be627d945be5 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=33_000_000 +rng_srate_value=30 +en_jitter=1 +sw_build_device=sim_dv +sw_images=otbn_ecdsa_op_irq_test:1:ne w_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/ sim.tcl +ntb_random_seed=2200118632 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tg l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_otbn_ecdsa_op_irq_jitter_en.2200118632 |
| Directory | /workspace/0.chip_sw_otbn_ecdsa_op_irq_jitter_en/latest |
| Test location | /workspace/coverage/default/0.chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq.3388433656 |
| Short name | T722 |
| Test name | |
| Test status | |
| Simulation time | 25573099326 ps |
| CPU time | 3536.58 seconds |
| Started | Aug 13 07:13:55 PM PDT 24 |
| Finished | Aug 13 08:12:52 PM PDT 24 |
| Peak memory | 611148 kb |
| Host | smart-e3072932-5b6f-4578-8d17-9ab71c8d6723 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=33_000_000 +rng_srate_value=30 +en_jitter=1 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=otbn_e cdsa_op_irq_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/ repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3388433656 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_otbn_ecdsa_op_irq_jitter_en_redu ced_freq.3388433656 |
| Directory | /workspace/0.chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq/latest |
| Test location | /workspace/coverage/default/0.chip_sw_otbn_mem_scramble.1829849622 |
| Short name | T275 |
| Test name | |
| Test status | |
| Simulation time | 3236018894 ps |
| CPU time | 565.78 seconds |
| Started | Aug 13 07:11:17 PM PDT 24 |
| Finished | Aug 13 07:20:43 PM PDT 24 |
| Peak memory | 610632 kb |
| Host | smart-74154076-34b4-4905-b4fa-96ed25ea4ba6 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=15_000_000 +en_scb_tl_err_chk=0 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=otbn _mem_scramble_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1829849622 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_otbn_mem_scramble.1829849622 |
| Directory | /workspace/0.chip_sw_otbn_mem_scramble/latest |
| Test location | /workspace/coverage/default/0.chip_sw_otbn_randomness.3230109066 |
| Short name | T410 |
| Test name | |
| Test status | |
| Simulation time | 5983304292 ps |
| CPU time | 1023.62 seconds |
| Started | Aug 13 07:12:08 PM PDT 24 |
| Finished | Aug 13 07:29:13 PM PDT 24 |
| Peak memory | 610992 kb |
| Host | smart-d8e273c9-ce32-418d-a44b-50ef54681fa9 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +rng_srate_value=30 +sw_build_device=sim_dv +sw_images=otbn_randomness_test:1:new_rules,test_ro m:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=3230109066 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_otbn_randomness.3230109066 |
| Directory | /workspace/0.chip_sw_otbn_randomness/latest |
| Test location | /workspace/coverage/default/0.chip_sw_otbn_smoketest.3643223263 |
| Short name | T1295 |
| Test name | |
| Test status | |
| Simulation time | 8175203010 ps |
| CPU time | 1795.37 seconds |
| Started | Aug 13 07:19:17 PM PDT 24 |
| Finished | Aug 13 07:49:13 PM PDT 24 |
| Peak memory | 610604 kb |
| Host | smart-b89e720b-a1e7-4502-92b1-3ec17f570d47 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=otbn_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3643223263 -assert nopostproc +UVM_TESTNAME=chi p_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul l -cm_name 0.chip_sw_otbn_smoketest.3643223263 |
| Directory | /workspace/0.chip_sw_otbn_smoketest/latest |
| Test location | /workspace/coverage/default/0.chip_sw_otp_ctrl_dai_lock.3667940200 |
| Short name | T1071 |
| Test name | |
| Test status | |
| Simulation time | 27460005204 ps |
| CPU time | 5603.2 seconds |
| Started | Aug 13 07:09:56 PM PDT 24 |
| Finished | Aug 13 08:43:20 PM PDT 24 |
| Peak memory | 611088 kb |
| Host | smart-3ba36033-62c3-43b2-b59f-22dc5e59b1f4 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=30_000_000 +sw_build_device=sim_dv +sw_images=otp_ctrl_mem_access_test:1:new_rules,test_rom:0 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=366794 0200 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_otp_ctrl_dai_lock.3667940200 |
| Directory | /workspace/0.chip_sw_otp_ctrl_dai_lock/latest |
| Test location | /workspace/coverage/default/0.chip_sw_otp_ctrl_ecc_error_vendor_test.3514573706 |
| Short name | T1214 |
| Test name | |
| Test status | |
| Simulation time | 2900416519 ps |
| CPU time | 233.68 seconds |
| Started | Aug 13 07:13:57 PM PDT 24 |
| Finished | Aug 13 07:17:52 PM PDT 24 |
| Peak memory | 610516 kb |
| Host | smart-294aa6a1-6412-4ff0-acf7-f7d4ae75f6eb |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=otp_ctrl_vendor_test_ecc_error_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3514573706 -assert nopostp roc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_otp_ctrl_vendor_test_ecc_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_otp_ctrl_ecc_error_vendor_test.3514573706 |
| Directory | /workspace/0.chip_sw_otp_ctrl_ecc_error_vendor_test/latest |
| Test location | /workspace/coverage/default/0.chip_sw_otp_ctrl_escalation.1864554285 |
| Short name | T171 |
| Test name | |
| Test status | |
| Simulation time | 5749379538 ps |
| CPU time | 619.4 seconds |
| Started | Aug 13 07:16:44 PM PDT 24 |
| Finished | Aug 13 07:27:04 PM PDT 24 |
| Peak memory | 611928 kb |
| Host | smart-eca9c2d0-c461-48c9-ac1d-62942630a341 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 1864554285 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_otp_ctrl_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_otp_ctrl_escalation.1864554285 |
| Directory | /workspace/0.chip_sw_otp_ctrl_escalation/latest |
| Test location | /workspace/coverage/default/0.chip_sw_otp_ctrl_lc_signals_dev.817098536 |
| Short name | T1217 |
| Test name | |
| Test status | |
| Simulation time | 8398322616 ps |
| CPU time | 1388.07 seconds |
| Started | Aug 13 07:14:16 PM PDT 24 |
| Finished | Aug 13 07:37:24 PM PDT 24 |
| Peak memory | 611332 kb |
| Host | smart-97ec3d79-d90d-4771-a4b6-ed6daefa17bc |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStDev +otp_clear_secret2=1 +sw_build_device=sim_dv +sw_images=otp_ctrl_lc_signals_test:1:new_rules,tes t_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +nt b_random_seed=817098536 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_otp_ctrl_lc_signals_dev.817098536 |
| Directory | /workspace/0.chip_sw_otp_ctrl_lc_signals_dev/latest |
| Test location | /workspace/coverage/default/0.chip_sw_otp_ctrl_lc_signals_prod.4112545995 |
| Short name | T1078 |
| Test name | |
| Test status | |
| Simulation time | 7584674588 ps |
| CPU time | 1517.49 seconds |
| Started | Aug 13 07:11:40 PM PDT 24 |
| Finished | Aug 13 07:36:58 PM PDT 24 |
| Peak memory | 611376 kb |
| Host | smart-1d485b43-9546-4d36-b984-64fc47518138 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStProd +otp_clear_secret2=1 +sw_build_device=sim_dv +sw_images=otp_ctrl_lc_signals_test:1:new_rules,te st_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n tb_random_seed=4112545995 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_otp_ctrl_lc_signals_prod.4112545995 |
| Directory | /workspace/0.chip_sw_otp_ctrl_lc_signals_prod/latest |
| Test location | /workspace/coverage/default/0.chip_sw_otp_ctrl_lc_signals_rma.939520753 |
| Short name | T1077 |
| Test name | |
| Test status | |
| Simulation time | 8626870300 ps |
| CPU time | 1734.98 seconds |
| Started | Aug 13 07:13:04 PM PDT 24 |
| Finished | Aug 13 07:42:00 PM PDT 24 |
| Peak memory | 611084 kb |
| Host | smart-d124e776-d288-4905-b740-35c70bec2f5b |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStRma +otp_clear_secret2=1 +sw_build_device=sim_dv +sw_images=otp_ctrl_lc_signals_test:1:new_rules,tes t_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +nt b_random_seed=939520753 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_otp_ctrl_lc_signals_rma.939520753 |
| Directory | /workspace/0.chip_sw_otp_ctrl_lc_signals_rma/latest |
| Test location | /workspace/coverage/default/0.chip_sw_otp_ctrl_lc_signals_test_unlocked0.1875653270 |
| Short name | T991 |
| Test name | |
| Test status | |
| Simulation time | 5151767394 ps |
| CPU time | 668.64 seconds |
| Started | Aug 13 07:09:05 PM PDT 24 |
| Finished | Aug 13 07:20:14 PM PDT 24 |
| Peak memory | 610496 kb |
| Host | smart-73180058-c731-430c-84ed-d213b749a9b7 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStTestUnlocked0 +otp_clear_secret2=1 +sw_build_device=sim_dv +sw_images=otp_ctrl_lc_signals_test:1:new _rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/s im.tcl +ntb_random_seed=1875653270 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_otp_ctrl_lc_signals_test_unlocked0.1875653270 |
| Directory | /workspace/0.chip_sw_otp_ctrl_lc_signals_test_unlocked0/latest |
| Test location | /workspace/coverage/default/0.chip_sw_otp_ctrl_smoketest.3162067684 |
| Short name | T1415 |
| Test name | |
| Test status | |
| Simulation time | 3013602628 ps |
| CPU time | 323.3 seconds |
| Started | Aug 13 07:17:28 PM PDT 24 |
| Finished | Aug 13 07:22:52 PM PDT 24 |
| Peak memory | 610408 kb |
| Host | smart-0f26a072-1854-423e-8abf-c32f29094283 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=otp_ctrl_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3162067684 -assert nopostproc +UVM_TESTNAME =chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 0.chip_sw_otp_ctrl_smoketest.3162067684 |
| Directory | /workspace/0.chip_sw_otp_ctrl_smoketest/latest |
| Test location | /workspace/coverage/default/0.chip_sw_pattgen_ios.2394178238 |
| Short name | T227 |
| Test name | |
| Test status | |
| Simulation time | 3570499600 ps |
| CPU time | 257.45 seconds |
| Started | Aug 13 07:09:31 PM PDT 24 |
| Finished | Aug 13 07:13:50 PM PDT 24 |
| Peak memory | 614188 kb |
| Host | smart-3cdd6864-dc17-478e-8489-ccbd48ec2c09 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=5_000_000 +sw_build_device=sim_dv +sw_images=pattgen_ios_test:1:new_rules,test_rom:0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2394178238 -ass ert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_patt_ios_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/c overage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_pattgen_ios.2394178238 |
| Directory | /workspace/0.chip_sw_pattgen_ios/latest |
| Test location | /workspace/coverage/default/0.chip_sw_plic_sw_irq.2710893468 |
| Short name | T255 |
| Test name | |
| Test status | |
| Simulation time | 2185657584 ps |
| CPU time | 203.95 seconds |
| Started | Aug 13 07:12:15 PM PDT 24 |
| Finished | Aug 13 07:15:40 PM PDT 24 |
| Peak memory | 610488 kb |
| Host | smart-af3869af-bca0-4564-b594-18cd5957f978 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=plic_sw_irq_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2710893468 -assert nopostproc +UVM_TESTNAME=c hip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n ull -cm_name 0.chip_sw_plic_sw_irq.2710893468 |
| Directory | /workspace/0.chip_sw_plic_sw_irq/latest |
| Test location | /workspace/coverage/default/0.chip_sw_power_idle_load.2882609737 |
| Short name | T1314 |
| Test name | |
| Test status | |
| Simulation time | 4192999562 ps |
| CPU time | 590.02 seconds |
| Started | Aug 13 07:14:17 PM PDT 24 |
| Finished | Aug 13 07:24:09 PM PDT 24 |
| Peak memory | 610908 kb |
| Host | smart-94a78a44-9257-488d-a3fb-6ed7ecf58afd |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=chip_power_idle_load:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2882609737 -assert nopostproc +UVM_TESTNA ME=chip_base_test +UVM_TEST_SEQ=chip_sw_power_idle_load_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_power_idle_load.2882609737 |
| Directory | /workspace/0.chip_sw_power_idle_load/latest |
| Test location | /workspace/coverage/default/0.chip_sw_power_virus.3639263427 |
| Short name | T207 |
| Test name | |
| Test status | |
| Simulation time | 5542764328 ps |
| CPU time | 1598.96 seconds |
| Started | Aug 13 07:17:17 PM PDT 24 |
| Finished | Aug 13 07:43:57 PM PDT 24 |
| Peak memory | 625444 kb |
| Host | smart-d7091988-71fc-4f45-9755-4bcc7eaec8fc |
| User | root |
| Command | /workspace/default/simv +rng_srate_value_min=15 +rng_srate_value_max=20 +sw_test_timeout_ns=400_000_000 +use_otp_image=OtpTypeCustom +accelerate_cold_ power_up_time=3 +accelerate_regulators_power_up_time=2 +sw_build_device=sim_dv +sw_images=power_virus_systemtest:1:new_rules,power_virus_systemtes t_otp_img_rma:4,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d v/tools/sim.tcl +ntb_random_seed=3639263427 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_power_virus_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_power_virus.3639263427 |
| Directory | /workspace/0.chip_sw_power_virus/latest |
| Test location | /workspace/coverage/default/0.chip_sw_pwrmgr_all_reset_reqs.2358839119 |
| Short name | T549 |
| Test name | |
| Test status | |
| Simulation time | 12007848767 ps |
| CPU time | 1568.87 seconds |
| Started | Aug 13 07:10:03 PM PDT 24 |
| Finished | Aug 13 07:36:13 PM PDT 24 |
| Peak memory | 612152 kb |
| Host | smart-b4211300-71bd-4417-bd09-96bc8a1b322c |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=50_000_000 +sw_build_device=sim_dv +sw_images=pwrmgr_all_reset_reqs_test:1:new_rules,test_rom:0 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2358 839119 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_deep_sleep_all_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_pwrmgr_all_reset_reqs.2358839119 |
| Directory | /workspace/0.chip_sw_pwrmgr_all_reset_reqs/latest |
| Test location | /workspace/coverage/default/0.chip_sw_pwrmgr_b2b_sleep_reset_req.1160169906 |
| Short name | T992 |
| Test name | |
| Test status | |
| Simulation time | 21122654530 ps |
| CPU time | 2332.04 seconds |
| Started | Aug 13 07:16:57 PM PDT 24 |
| Finished | Aug 13 07:55:50 PM PDT 24 |
| Peak memory | 611860 kb |
| Host | smart-c77e4083-4fdf-4b8d-8f5e-9fcfec3f271e |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=35_000_000 +sw_build_device=sim_dv +sw_images=pwrmgr_b2b_sleep_reset_test:1:new_rules,test_rom:0 +cdc_inst rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=116 0169906 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_repeat_reset_wkup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_pwrmgr_b2b_sleep_reset_req.1160169906 |
| Directory | /workspace/0.chip_sw_pwrmgr_b2b_sleep_reset_req/latest |
| Test location | /workspace/coverage/default/0.chip_sw_pwrmgr_deep_sleep_all_reset_reqs.2585119360 |
| Short name | T1174 |
| Test name | |
| Test status | |
| Simulation time | 14056150195 ps |
| CPU time | 1295.75 seconds |
| Started | Aug 13 07:10:49 PM PDT 24 |
| Finished | Aug 13 07:32:26 PM PDT 24 |
| Peak memory | 611948 kb |
| Host | smart-00c29eb4-cbc7-442a-9e06-4034f9d43f81 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=50_000_000 +sw_build_device=sim_dv +sw_images=pwrmgr_deep_sleep_all_reset_reqs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=2585119360 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_deep_sleep_all_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_pwrmgr_deep_sleep_all_reset_reqs.2585119360 |
| Directory | /workspace/0.chip_sw_pwrmgr_deep_sleep_all_reset_reqs/latest |
| Test location | /workspace/coverage/default/0.chip_sw_pwrmgr_deep_sleep_all_wake_ups.1397030329 |
| Short name | T57 |
| Test name | |
| Test status | |
| Simulation time | 20101163560 ps |
| CPU time | 1416.24 seconds |
| Started | Aug 13 07:11:00 PM PDT 24 |
| Finished | Aug 13 07:34:36 PM PDT 24 |
| Peak memory | 611500 kb |
| Host | smart-0dba13f9-a5ea-4770-94da-9241bbd3fc74 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=pwrmgr_deep_sleep_all_wake_ups:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 1397030329 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_pwrmgr_deep_sleep_all_wake_ups_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_pwrmgr_deep_sleep_all_wake_ups.1397030329 |
| Directory | /workspace/0.chip_sw_pwrmgr_deep_sleep_all_wake_ups/latest |
| Test location | /workspace/coverage/default/0.chip_sw_pwrmgr_deep_sleep_por_reset.1346036317 |
| Short name | T734 |
| Test name | |
| Test status | |
| Simulation time | 9503355620 ps |
| CPU time | 671.42 seconds |
| Started | Aug 13 07:09:33 PM PDT 24 |
| Finished | Aug 13 07:20:45 PM PDT 24 |
| Peak memory | 611604 kb |
| Host | smart-2c61eece-a30b-4382-874d-d92efddf0ffd |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_deep_sleep_por_reset_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1346036317 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sleep_por_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage /default.vdb -cm_log /dev/null -cm_name 0.chip_sw_pwrmgr_deep_sleep_por_reset.1346036317 |
| Directory | /workspace/0.chip_sw_pwrmgr_deep_sleep_por_reset/latest |
| Test location | /workspace/coverage/default/0.chip_sw_pwrmgr_main_power_glitch_reset.787901694 |
| Short name | T311 |
| Test name | |
| Test status | |
| Simulation time | 4168376500 ps |
| CPU time | 450.77 seconds |
| Started | Aug 13 07:11:43 PM PDT 24 |
| Finished | Aug 13 07:19:14 PM PDT 24 |
| Peak memory | 617944 kb |
| Host | smart-09d36c75-9e1d-4d91-8e8f-c7bc58ca824d |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=pwrmgr_main_power_glitch_test:1:new_rules,test_rom:0 +cd c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se ed=787901694 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_main_power_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_pwrmgr_main_power_glitch_reset.787901694 |
| Directory | /workspace/0.chip_sw_pwrmgr_main_power_glitch_reset/latest |
| Test location | /workspace/coverage/default/0.chip_sw_pwrmgr_normal_sleep_all_reset_reqs.3186572759 |
| Short name | T1210 |
| Test name | |
| Test status | |
| Simulation time | 10004909622 ps |
| CPU time | 1418.07 seconds |
| Started | Aug 13 07:14:31 PM PDT 24 |
| Finished | Aug 13 07:38:09 PM PDT 24 |
| Peak memory | 612180 kb |
| Host | smart-1c4cefa1-1da6-421d-a63d-8a99795240df |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_normal_sleep_all_reset_reqs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3186572759 -assert nop ostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_deep_sleep_all_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_pwrmgr_normal_sleep_all_reset_reqs.3186572759 |
| Directory | /workspace/0.chip_sw_pwrmgr_normal_sleep_all_reset_reqs/latest |
| Test location | /workspace/coverage/default/0.chip_sw_pwrmgr_normal_sleep_all_wake_ups.4171051529 |
| Short name | T101 |
| Test name | |
| Test status | |
| Simulation time | 7715936952 ps |
| CPU time | 461.38 seconds |
| Started | Aug 13 07:14:31 PM PDT 24 |
| Finished | Aug 13 07:22:12 PM PDT 24 |
| Peak memory | 611072 kb |
| Host | smart-9fc0c70a-2e4b-4f2c-b752-617df2745cbd |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_normal_sleep_all_wake_ups:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4171051529 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_pwrmgr_deep_sleep_all_wake_ups_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_pwrmgr_normal_sleep_all_wake_ups.4171051529 |
| Directory | /workspace/0.chip_sw_pwrmgr_normal_sleep_all_wake_ups/latest |
| Test location | /workspace/coverage/default/0.chip_sw_pwrmgr_normal_sleep_por_reset.706951989 |
| Short name | T467 |
| Test name | |
| Test status | |
| Simulation time | 7081288865 ps |
| CPU time | 550.37 seconds |
| Started | Aug 13 07:10:35 PM PDT 24 |
| Finished | Aug 13 07:19:46 PM PDT 24 |
| Peak memory | 611288 kb |
| Host | smart-e69dae08-80e7-416e-8971-bf347fa98caf |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_normal_sleep_por_reset_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=706951989 -assert nopostpro c +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sleep_por_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag e/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_pwrmgr_normal_sleep_por_reset.706951989 |
| Directory | /workspace/0.chip_sw_pwrmgr_normal_sleep_por_reset/latest |
| Test location | /workspace/coverage/default/0.chip_sw_pwrmgr_random_sleep_all_reset_reqs.86079738 |
| Short name | T1183 |
| Test name | |
| Test status | |
| Simulation time | 24553078487 ps |
| CPU time | 2292.63 seconds |
| Started | Aug 13 07:09:50 PM PDT 24 |
| Finished | Aug 13 07:48:04 PM PDT 24 |
| Peak memory | 611900 kb |
| Host | smart-f6777765-b48e-4cfe-8517-c81c71fbbd34 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=50_000_000 +sw_build_device=sim_dv +sw_images=pwrmgr_random_sleep_all_reset_reqs_test:1:new_rules,test_rom :0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=86079738 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_deep_sleep_all_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_pwrmgr_random_sleep_all_reset_reqs.86079738 |
| Directory | /workspace/0.chip_sw_pwrmgr_random_sleep_all_reset_reqs/latest |
| Test location | /workspace/coverage/default/0.chip_sw_pwrmgr_random_sleep_all_wake_ups.1798126911 |
| Short name | T438 |
| Test name | |
| Test status | |
| Simulation time | 21466810446 ps |
| CPU time | 1437.23 seconds |
| Started | Aug 13 07:10:31 PM PDT 24 |
| Finished | Aug 13 07:34:28 PM PDT 24 |
| Peak memory | 611368 kb |
| Host | smart-34fba72c-3d2f-47e2-b2e8-ed638f73a5d8 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +do_random=1 +sw_build_device=sim_dv +sw_images=pwrmgr_random_sleep_all_wake_ups:1:new_rules,te st_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n tb_random_seed=1798126911 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_pwrmgr_deep_sleep_all_wake_ups_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_pwrmgr_random_sleep_all_wake_ups.1798126911 |
| Directory | /workspace/0.chip_sw_pwrmgr_random_sleep_all_wake_ups/latest |
| Test location | /workspace/coverage/default/0.chip_sw_pwrmgr_random_sleep_power_glitch_reset.1434842022 |
| Short name | T1233 |
| Test name | |
| Test status | |
| Simulation time | 27936622584 ps |
| CPU time | 2492.93 seconds |
| Started | Aug 13 07:12:03 PM PDT 24 |
| Finished | Aug 13 07:53:36 PM PDT 24 |
| Peak memory | 612172 kb |
| Host | smart-2db67313-dece-4ec9-8e3a-12c5fe5d6f79 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_test_timeout_ns=24_000_000 +sw_build_device=sim_dv +sw_images=pwrmgr_random_sleep_power _glitch_reset_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1434842022 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_random_power_glit ch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_pwrmgr_random_s leep_power_glitch_reset.1434842022 |
| Directory | /workspace/0.chip_sw_pwrmgr_random_sleep_power_glitch_reset/latest |
| Test location | /workspace/coverage/default/0.chip_sw_pwrmgr_sleep_disabled.3129460055 |
| Short name | T1362 |
| Test name | |
| Test status | |
| Simulation time | 2919362304 ps |
| CPU time | 289.96 seconds |
| Started | Aug 13 07:12:14 PM PDT 24 |
| Finished | Aug 13 07:17:04 PM PDT 24 |
| Peak memory | 610456 kb |
| Host | smart-db201c31-1f88-4d6e-8474-0ec598fdd14a |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_sleep_disabled_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3129460055 -assert nopostproc +UVM_ TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_ log /dev/null -cm_name 0.chip_sw_pwrmgr_sleep_disabled.3129460055 |
| Directory | /workspace/0.chip_sw_pwrmgr_sleep_disabled/latest |
| Test location | /workspace/coverage/default/0.chip_sw_pwrmgr_sleep_power_glitch_reset.426027113 |
| Short name | T1142 |
| Test name | |
| Test status | |
| Simulation time | 5819466856 ps |
| CPU time | 411.52 seconds |
| Started | Aug 13 07:14:21 PM PDT 24 |
| Finished | Aug 13 07:21:13 PM PDT 24 |
| Peak memory | 618408 kb |
| Host | smart-31a0c685-f4bb-4b98-8871-bfe6ee098e6d |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=pwrmgr_sleep_power_glitch_test:1:new_rules,test_rom:0 +c dc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_s eed=426027113 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_main_power_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_pwrmgr_sleep_power_glitch_reset.426027113 |
| Directory | /workspace/0.chip_sw_pwrmgr_sleep_power_glitch_reset/latest |
| Test location | /workspace/coverage/default/0.chip_sw_pwrmgr_sleep_wake_5_bug.361549912 |
| Short name | T955 |
| Test name | |
| Test status | |
| Simulation time | 6120688730 ps |
| CPU time | 372.37 seconds |
| Started | Aug 13 07:13:13 PM PDT 24 |
| Finished | Aug 13 07:19:26 PM PDT 24 |
| Peak memory | 611468 kb |
| Host | smart-b369c620-ad10-47ca-b663-f4e5b241df5a |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +do_random=1 +sw_build_device=sim_dv +sw_images=pwrmgr_sleep_wake_5_bug_test:1:new_rules,test_r om:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r andom_seed=361549912 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_pwrmgr_sleep_wake_5_bug.361549912 |
| Directory | /workspace/0.chip_sw_pwrmgr_sleep_wake_5_bug/latest |
| Test location | /workspace/coverage/default/0.chip_sw_pwrmgr_smoketest.4179892753 |
| Short name | T1102 |
| Test name | |
| Test status | |
| Simulation time | 4827049896 ps |
| CPU time | 433.47 seconds |
| Started | Aug 13 07:13:36 PM PDT 24 |
| Finished | Aug 13 07:20:49 PM PDT 24 |
| Peak memory | 611256 kb |
| Host | smart-05f69ada-dc1e-44f2-9191-367630e65433 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=10000000 +sw_build_device=sim_dv +sw_images=pwrmgr_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4179892753 -asse rt nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera ge/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_pwrmgr_smoketest.4179892753 |
| Directory | /workspace/0.chip_sw_pwrmgr_smoketest/latest |
| Test location | /workspace/coverage/default/0.chip_sw_pwrmgr_sysrst_ctrl_reset.2810582920 |
| Short name | T1327 |
| Test name | |
| Test status | |
| Simulation time | 8147326132 ps |
| CPU time | 1121.54 seconds |
| Started | Aug 13 07:11:44 PM PDT 24 |
| Finished | Aug 13 07:30:27 PM PDT 24 |
| Peak memory | 611380 kb |
| Host | smart-36f9bf70-bace-4d6a-af73-71df00e38dab |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_sysrst_ctrl_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2810582920 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sysrst_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_pwrmgr_sysrst_ctrl_reset.2810582920 |
| Directory | /workspace/0.chip_sw_pwrmgr_sysrst_ctrl_reset/latest |
| Test location | /workspace/coverage/default/0.chip_sw_pwrmgr_usb_clk_disabled_when_active.3183261264 |
| Short name | T1389 |
| Test name | |
| Test status | |
| Simulation time | 4973593456 ps |
| CPU time | 436.63 seconds |
| Started | Aug 13 07:13:40 PM PDT 24 |
| Finished | Aug 13 07:20:58 PM PDT 24 |
| Peak memory | 611180 kb |
| Host | smart-914e173e-d450-47b6-96b8-ecfb008e2fb6 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_usb_clk_disabled_when_active_test:1:new_rules,test_rom:0 +cdc_instrumentation_enable d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3183261264 -assert no postproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de fault.vdb -cm_log /dev/null -cm_name 0.chip_sw_pwrmgr_usb_clk_disabled_when_active.3183261264 |
| Directory | /workspace/0.chip_sw_pwrmgr_usb_clk_disabled_when_active/latest |
| Test location | /workspace/coverage/default/0.chip_sw_pwrmgr_usbdev_smoketest.3894125588 |
| Short name | T420 |
| Test name | |
| Test status | |
| Simulation time | 5140106300 ps |
| CPU time | 379.77 seconds |
| Started | Aug 13 07:12:18 PM PDT 24 |
| Finished | Aug 13 07:18:38 PM PDT 24 |
| Peak memory | 610960 kb |
| Host | smart-bb446b44-e516-4558-8f89-8c7be56a491b |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_usbdev_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3894125588 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_pwrmgr_usbdev_smoketest.3894125588 |
| Directory | /workspace/0.chip_sw_pwrmgr_usbdev_smoketest/latest |
| Test location | /workspace/coverage/default/0.chip_sw_pwrmgr_wdog_reset.3759296901 |
| Short name | T262 |
| Test name | |
| Test status | |
| Simulation time | 4493407176 ps |
| CPU time | 631.49 seconds |
| Started | Aug 13 07:13:11 PM PDT 24 |
| Finished | Aug 13 07:23:42 PM PDT 24 |
| Peak memory | 611280 kb |
| Host | smart-ddef5981-0475-4046-a4e5-918521b1d692 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=pwrmgr_wdog_reset_reqs_test:1:new_rules,test_rom:0 +cdc_inst rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=375 9296901 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_pwrmgr_wdog_reset.3759296901 |
| Directory | /workspace/0.chip_sw_pwrmgr_wdog_reset/latest |
| Test location | /workspace/coverage/default/0.chip_sw_rom_ctrl_integrity_check.686773698 |
| Short name | T1189 |
| Test name | |
| Test status | |
| Simulation time | 9691757241 ps |
| CPU time | 758.63 seconds |
| Started | Aug 13 07:13:17 PM PDT 24 |
| Finished | Aug 13 07:25:56 PM PDT 24 |
| Peak memory | 624688 kb |
| Host | smart-ea78221a-4210-448a-a095-739752b1c528 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=rom_ctrl_integrity_check_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=686773698 -assert nopostproc +UV M_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rom_ctrl_integrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov erage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_rom_ctrl_integrity_check.686773698 |
| Directory | /workspace/0.chip_sw_rom_ctrl_integrity_check/latest |
| Test location | /workspace/coverage/default/0.chip_sw_rstmgr_rst_cnsty_escalation.1993127491 |
| Short name | T1136 |
| Test name | |
| Test status | |
| Simulation time | 5715715400 ps |
| CPU time | 739.85 seconds |
| Started | Aug 13 07:10:05 PM PDT 24 |
| Finished | Aug 13 07:22:26 PM PDT 24 |
| Peak memory | 642208 kb |
| Host | smart-fc0e0bed-4069-4bbc-869f-4069af7cbe98 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 1993127491 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rstmgr_cnsty_fault_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_rstmgr_rst_cnsty_escalation.1993127491 |
| Directory | /workspace/0.chip_sw_rstmgr_rst_cnsty_escalation/latest |
| Test location | /workspace/coverage/default/0.chip_sw_rstmgr_smoketest.1439778251 |
| Short name | T1408 |
| Test name | |
| Test status | |
| Simulation time | 3280159920 ps |
| CPU time | 256.13 seconds |
| Started | Aug 13 07:14:10 PM PDT 24 |
| Finished | Aug 13 07:18:27 PM PDT 24 |
| Peak memory | 610496 kb |
| Host | smart-7011d068-fe55-4ddb-a4ec-f2b0fdd98817 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=rstmgr_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1439778251 -assert nopostproc +UVM_TESTNAME=c hip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n ull -cm_name 0.chip_sw_rstmgr_smoketest.1439778251 |
| Directory | /workspace/0.chip_sw_rstmgr_smoketest/latest |
| Test location | /workspace/coverage/default/0.chip_sw_rstmgr_sw_req.106419846 |
| Short name | T937 |
| Test name | |
| Test status | |
| Simulation time | 4494040448 ps |
| CPU time | 356.37 seconds |
| Started | Aug 13 07:16:49 PM PDT 24 |
| Finished | Aug 13 07:22:45 PM PDT 24 |
| Peak memory | 609912 kb |
| Host | smart-4310457f-fa6d-483b-a9cf-5a395d45c182 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=rstmgr_sw_req_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=106419846 -assert nopostproc +UVM_TESTNAME= chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/ null -cm_name 0.chip_sw_rstmgr_sw_req.106419846 |
| Directory | /workspace/0.chip_sw_rstmgr_sw_req/latest |
| Test location | /workspace/coverage/default/0.chip_sw_rstmgr_sw_rst.870049003 |
| Short name | T1288 |
| Test name | |
| Test status | |
| Simulation time | 2053902396 ps |
| CPU time | 182.49 seconds |
| Started | Aug 13 07:10:24 PM PDT 24 |
| Finished | Aug 13 07:13:27 PM PDT 24 |
| Peak memory | 610272 kb |
| Host | smart-32b0b40b-4924-4594-972a-391e31fe6af5 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=rstmgr_sw_rst_ctrl_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=870049003 -assert nopostproc +UVM_TEST NAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_rstmgr_sw_rst.870049003 |
| Directory | /workspace/0.chip_sw_rstmgr_sw_rst/latest |
| Test location | /workspace/coverage/default/0.chip_sw_rv_core_ibex_icache_invalidate.3040429713 |
| Short name | T303 |
| Test name | |
| Test status | |
| Simulation time | 2778515686 ps |
| CPU time | 281.97 seconds |
| Started | Aug 13 07:12:15 PM PDT 24 |
| Finished | Aug 13 07:16:58 PM PDT 24 |
| Peak memory | 609164 kb |
| Host | smart-f202b2b7-7d91-4444-aff9-9354d3b73227 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=rv_core_ibex_icache_invalidate_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3040429713 -assert nopostp roc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rv_core_ibex_icache_invalidate_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_rv_core_ibex_icache_invalidate.3040429713 |
| Directory | /workspace/0.chip_sw_rv_core_ibex_icache_invalidate/latest |
| Test location | /workspace/coverage/default/0.chip_sw_rv_core_ibex_rnd.3330554334 |
| Short name | T1021 |
| Test name | |
| Test status | |
| Simulation time | 5393228870 ps |
| CPU time | 1104.74 seconds |
| Started | Aug 13 07:11:28 PM PDT 24 |
| Finished | Aug 13 07:29:54 PM PDT 24 |
| Peak memory | 609392 kb |
| Host | smart-e27543b6-3bb2-4af9-841d-c10e01320372 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=20_000_000 +rng_srate_value_max=32 +sw_build_device=sim_dv +sw_images=rv_core_ibex_rnd_test:1:new_rules,te st_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n tb_random_seed=3330554334 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_rv_core_ibex_rnd.3330554334 |
| Directory | /workspace/0.chip_sw_rv_core_ibex_rnd/latest |
| Test location | /workspace/coverage/default/0.chip_sw_rv_dm_access_after_wakeup.2911040381 |
| Short name | T66 |
| Test name | |
| Test status | |
| Simulation time | 6584916640 ps |
| CPU time | 611.06 seconds |
| Started | Aug 13 07:15:26 PM PDT 24 |
| Finished | Aug 13 07:25:38 PM PDT 24 |
| Peak memory | 620456 kb |
| Host | smart-f21f2734-3396-45cd-a77b-dec7a5f5bd92 |
| User | root |
| Command | /workspace/default/simv +use_jtag_dmi=1 +sw_build_device=sim_dv +sw_images=rv_dm_access_after_wakeup_rma:1:new_rules,test_rom:0 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2911040381 -asse rt nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rv_dm_access_after_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_rv_dm_access_after_wakeup.2911040381 |
| Directory | /workspace/0.chip_sw_rv_dm_access_after_wakeup/latest |
| Test location | /workspace/coverage/default/0.chip_sw_rv_dm_ndm_reset_req_when_cpu_halted.3284561919 |
| Short name | T319 |
| Test name | |
| Test status | |
| Simulation time | 3829736888 ps |
| CPU time | 466.42 seconds |
| Started | Aug 13 07:14:59 PM PDT 24 |
| Finished | Aug 13 07:22:46 PM PDT 24 |
| Peak memory | 620596 kb |
| Host | smart-cd1952f0-528f-45e0-ac71-7d08cb16cdcd |
| User | root |
| Command | /workspace/default/simv +use_jtag_dmi=1 +sw_build_device=sim_dv +sw_images=rv_dm_ndm_reset_req_when_cpu_halted_rma:1:new_rules,test_rom:0 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=328456 1919 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rv_dm_ndm_reset_when_cpu_halted_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_rv_dm_ndm_reset_req_when_cpu_halted.3284561919 |
| Directory | /workspace/0.chip_sw_rv_dm_ndm_reset_req_when_cpu_halted/latest |
| Test location | /workspace/coverage/default/0.chip_sw_rv_plic_smoketest.2017250318 |
| Short name | T1193 |
| Test name | |
| Test status | |
| Simulation time | 2699650142 ps |
| CPU time | 262.32 seconds |
| Started | Aug 13 07:13:32 PM PDT 24 |
| Finished | Aug 13 07:17:55 PM PDT 24 |
| Peak memory | 610176 kb |
| Host | smart-186f22cb-1618-447b-b050-81aa8d2627e0 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=rv_plic_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2017250318 -assert nopostproc +UVM_TESTNAME= chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/ null -cm_name 0.chip_sw_rv_plic_smoketest.2017250318 |
| Directory | /workspace/0.chip_sw_rv_plic_smoketest/latest |
| Test location | /workspace/coverage/default/0.chip_sw_rv_timer_irq.3835593746 |
| Short name | T1323 |
| Test name | |
| Test status | |
| Simulation time | 3072896512 ps |
| CPU time | 293.84 seconds |
| Started | Aug 13 07:10:26 PM PDT 24 |
| Finished | Aug 13 07:15:21 PM PDT 24 |
| Peak memory | 610384 kb |
| Host | smart-1a2e22b6-967a-436a-89fb-7112446a51fa |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=rv_timer_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3835593746 -assert nopostproc +UVM_TESTNAME =chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 0.chip_sw_rv_timer_irq.3835593746 |
| Directory | /workspace/0.chip_sw_rv_timer_irq/latest |
| Test location | /workspace/coverage/default/0.chip_sw_rv_timer_smoketest.3175135669 |
| Short name | T257 |
| Test name | |
| Test status | |
| Simulation time | 2889398470 ps |
| CPU time | 262.33 seconds |
| Started | Aug 13 07:11:23 PM PDT 24 |
| Finished | Aug 13 07:15:46 PM PDT 24 |
| Peak memory | 610456 kb |
| Host | smart-ee8ef2fb-af80-454c-86d3-979fc28e22ab |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=rv_timer_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3175135669 -assert nopostproc +UVM_TESTNAME =chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 0.chip_sw_rv_timer_smoketest.3175135669 |
| Directory | /workspace/0.chip_sw_rv_timer_smoketest/latest |
| Test location | /workspace/coverage/default/0.chip_sw_sensor_ctrl_status.1182734063 |
| Short name | T362 |
| Test name | |
| Test status | |
| Simulation time | 3136100893 ps |
| CPU time | 313.68 seconds |
| Started | Aug 13 07:12:56 PM PDT 24 |
| Finished | Aug 13 07:18:10 PM PDT 24 |
| Peak memory | 611524 kb |
| Host | smart-9b9ee89c-a98a-449b-9a93-8799c11009a5 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=40_000_000 +sw_build_device=sim_dv +sw_images=sensor_ctrl_status_test:1:new_rules,test_rom:0 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1182734 063 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sensor_ctrl_status_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_sensor_ctrl_status.1182734063 |
| Directory | /workspace/0.chip_sw_sensor_ctrl_status/latest |
| Test location | /workspace/coverage/default/0.chip_sw_sleep_pwm_pulses.197691153 |
| Short name | T1273 |
| Test name | |
| Test status | |
| Simulation time | 8827432238 ps |
| CPU time | 1371.52 seconds |
| Started | Aug 13 07:11:47 PM PDT 24 |
| Finished | Aug 13 07:34:39 PM PDT 24 |
| Peak memory | 611556 kb |
| Host | smart-a7318888-8e3e-46d5-8168-788f2f7875fe |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=sleep_pwm_pulses_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=197691153 -assert nopostproc +UVM_TESTNA ME=chip_base_test +UVM_TEST_SEQ=chip_sw_pwm_pulses_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_ log /dev/null -cm_name 0.chip_sw_sleep_pwm_pulses.197691153 |
| Directory | /workspace/0.chip_sw_sleep_pwm_pulses/latest |
| Test location | /workspace/coverage/default/0.chip_sw_sleep_sram_ret_contents_no_scramble.1673893285 |
| Short name | T105 |
| Test name | |
| Test status | |
| Simulation time | 8039510352 ps |
| CPU time | 532.76 seconds |
| Started | Aug 13 07:11:53 PM PDT 24 |
| Finished | Aug 13 07:20:46 PM PDT 24 |
| Peak memory | 611328 kb |
| Host | smart-77d7bca5-38b2-49a1-9be0-78d02ec4f94f |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=20_000_000 +en_scb_tl_err_chk=0 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=sram _ctrl_sleep_sram_ret_contents_no_scramble_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1673893285 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_S EQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_sl eep_sram_ret_contents_no_scramble.1673893285 |
| Directory | /workspace/0.chip_sw_sleep_sram_ret_contents_no_scramble/latest |
| Test location | /workspace/coverage/default/0.chip_sw_sleep_sram_ret_contents_scramble.3288537025 |
| Short name | T1245 |
| Test name | |
| Test status | |
| Simulation time | 7095571164 ps |
| CPU time | 582.2 seconds |
| Started | Aug 13 07:10:40 PM PDT 24 |
| Finished | Aug 13 07:20:22 PM PDT 24 |
| Peak memory | 611060 kb |
| Host | smart-b6f85a59-5676-4f52-9a14-89c7832a7d65 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=20_000_000 +en_scb_tl_err_chk=0 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=sram _ctrl_sleep_sram_ret_contents_scramble_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3288537025 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ= chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_sleep _sram_ret_contents_scramble.3288537025 |
| Directory | /workspace/0.chip_sw_sleep_sram_ret_contents_scramble/latest |
| Test location | /workspace/coverage/default/0.chip_sw_spi_device_pass_through.609893116 |
| Short name | T205 |
| Test name | |
| Test status | |
| Simulation time | 6188358862 ps |
| CPU time | 734.71 seconds |
| Started | Aug 13 07:09:10 PM PDT 24 |
| Finished | Aug 13 07:21:26 PM PDT 24 |
| Peak memory | 625352 kb |
| Host | smart-f72e3beb-92f2-4ed0-aae1-850b17c60690 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=spi_passthrough_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=609893116 -assert nopostproc +UVM_TESTNAM E=chip_base_test +UVM_TEST_SEQ=chip_sw_spi_passthrough_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_spi_device_pass_through.609893116 |
| Directory | /workspace/0.chip_sw_spi_device_pass_through/latest |
| Test location | /workspace/coverage/default/0.chip_sw_spi_device_tpm.4007820703 |
| Short name | T38 |
| Test name | |
| Test status | |
| Simulation time | 3805564139 ps |
| CPU time | 437.13 seconds |
| Started | Aug 13 07:10:15 PM PDT 24 |
| Finished | Aug 13 07:17:32 PM PDT 24 |
| Peak memory | 623952 kb |
| Host | smart-8ce8afdd-1ba1-41c3-8d48-cfd5ef9b8557 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=spi_device_tpm_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4007820703 -assert nopostproc +UVM_T ESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_spi_device_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default .vdb -cm_log /dev/null -cm_name 0.chip_sw_spi_device_tpm.4007820703 |
| Directory | /workspace/0.chip_sw_spi_device_tpm/latest |
| Test location | /workspace/coverage/default/0.chip_sw_sram_ctrl_scrambled_access.3658349115 |
| Short name | T294 |
| Test name | |
| Test status | |
| Simulation time | 5897314732 ps |
| CPU time | 637.2 seconds |
| Started | Aug 13 07:10:51 PM PDT 24 |
| Finished | Aug 13 07:21:29 PM PDT 24 |
| Peak memory | 611860 kb |
| Host | smart-ac714135-2bce-4381-b17d-80407329cb75 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=12_000_000 +en_scb_tl_err_chk=0 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=sram _ctrl_scrambled_access_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3658349115 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sram_ctr l_scrambled_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw _sram_ctrl_scrambled_access.3658349115 |
| Directory | /workspace/0.chip_sw_sram_ctrl_scrambled_access/latest |
| Test location | /workspace/coverage/default/0.chip_sw_sram_ctrl_scrambled_access_jitter_en.2147299548 |
| Short name | T120 |
| Test name | |
| Test status | |
| Simulation time | 5365251409 ps |
| CPU time | 475.34 seconds |
| Started | Aug 13 07:10:29 PM PDT 24 |
| Finished | Aug 13 07:18:25 PM PDT 24 |
| Peak memory | 610728 kb |
| Host | smart-7d051078-0547-46fe-be7a-751f6b6ddab3 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=12_000_000 +bypass_alert_ready_to_end_check=1 +en_jitter=1 +en_scb_tl_err_chk=0 +sw_build_device=sim_dv +s w_images=sram_ctrl_scrambled_access_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2147299548 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chi p_sw_sram_ctrl_scrambled_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n ame 0.chip_sw_sram_ctrl_scrambled_access_jitter_en.2147299548 |
| Directory | /workspace/0.chip_sw_sram_ctrl_scrambled_access_jitter_en/latest |
| Test location | /workspace/coverage/default/0.chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq.3135498550 |
| Short name | T119 |
| Test name | |
| Test status | |
| Simulation time | 4780006739 ps |
| CPU time | 560.69 seconds |
| Started | Aug 13 07:11:51 PM PDT 24 |
| Finished | Aug 13 07:21:12 PM PDT 24 |
| Peak memory | 610524 kb |
| Host | smart-cd2ead3d-beab-4b13-a682-7f781f83be44 |
| User | root |
| Command | /workspace/default/simv +mem_sel=main +sw_test_timeout_ns=12_000_000 +bypass_alert_ready_to_end_check=1 +en_jitter=1 +en_scb_tl_err_chk=0 +cal_sys_clk _70mhz=1 +sw_build_device=sim_dv +sw_images=sram_ctrl_scrambled_access_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3135498550 -assert nopostproc +UVM_TESTNA ME=chip_base_test +UVM_TEST_SEQ=chip_sw_sram_ctrl_scrambled_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/ default.vdb -cm_log /dev/null -cm_name 0.chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq.3135498550 |
| Directory | /workspace/0.chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq/latest |
| Test location | /workspace/coverage/default/0.chip_sw_sram_ctrl_smoketest.1342102781 |
| Short name | T1289 |
| Test name | |
| Test status | |
| Simulation time | 2772426936 ps |
| CPU time | 288.13 seconds |
| Started | Aug 13 07:12:41 PM PDT 24 |
| Finished | Aug 13 07:17:30 PM PDT 24 |
| Peak memory | 609892 kb |
| Host | smart-b2c0b1ab-3a22-4bf9-bde7-27852d163740 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=sram_ctrl_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1342102781 -assert nopostproc +UVM_TESTNAM E=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 0.chip_sw_sram_ctrl_smoketest.1342102781 |
| Directory | /workspace/0.chip_sw_sram_ctrl_smoketest/latest |
| Test location | /workspace/coverage/default/0.chip_sw_sysrst_ctrl_inputs.3691474146 |
| Short name | T215 |
| Test name | |
| Test status | |
| Simulation time | 2875704416 ps |
| CPU time | 240.83 seconds |
| Started | Aug 13 07:12:05 PM PDT 24 |
| Finished | Aug 13 07:16:08 PM PDT 24 |
| Peak memory | 613548 kb |
| Host | smart-da216e1f-05eb-4bc3-b76b-3d806d3dd2e9 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=sysrst_ctrl_inputs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3691474146 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sysrst_ctrl_inputs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau lt.vdb -cm_log /dev/null -cm_name 0.chip_sw_sysrst_ctrl_inputs.3691474146 |
| Directory | /workspace/0.chip_sw_sysrst_ctrl_inputs/latest |
| Test location | /workspace/coverage/default/0.chip_sw_sysrst_ctrl_outputs.3477751219 |
| Short name | T21 |
| Test name | |
| Test status | |
| Simulation time | 3868096142 ps |
| CPU time | 328.84 seconds |
| Started | Aug 13 07:10:22 PM PDT 24 |
| Finished | Aug 13 07:15:51 PM PDT 24 |
| Peak memory | 610332 kb |
| Host | smart-e657114f-647d-49a2-9f36-277cf41accbb |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=sysrst_ctrl_outputs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3477751219 -assert nopostproc +UVM_TE STNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sysrst_ctrl_outputs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def ault.vdb -cm_log /dev/null -cm_name 0.chip_sw_sysrst_ctrl_outputs.3477751219 |
| Directory | /workspace/0.chip_sw_sysrst_ctrl_outputs/latest |
| Test location | /workspace/coverage/default/0.chip_sw_sysrst_ctrl_reset.1041346815 |
| Short name | T1244 |
| Test name | |
| Test status | |
| Simulation time | 25182566254 ps |
| CPU time | 1947.48 seconds |
| Started | Aug 13 07:10:29 PM PDT 24 |
| Finished | Aug 13 07:42:58 PM PDT 24 |
| Peak memory | 615944 kb |
| Host | smart-717494bf-3503-401f-af44-9eec4b2680ff |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=36_000_000 +sw_build_device=sim_dv +sw_images=sysrst_ctrl_reset_test:1:new_rules,test_rom:0 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10413468 15 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sysrst_ctrl_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_sysrst_ctrl_reset.1041346815 |
| Directory | /workspace/0.chip_sw_sysrst_ctrl_reset/latest |
| Test location | /workspace/coverage/default/0.chip_sw_sysrst_ctrl_ulp_z3_wakeup.1091545667 |
| Short name | T35 |
| Test name | |
| Test status | |
| Simulation time | 5259059580 ps |
| CPU time | 602.32 seconds |
| Started | Aug 13 07:08:37 PM PDT 24 |
| Finished | Aug 13 07:18:40 PM PDT 24 |
| Peak memory | 611528 kb |
| Host | smart-4ecbe915-27e7-422a-909a-b168b8779ef4 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=sysrst_ctrl_ulp_z3_wakeup_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1091545667 -assert nopostproc + UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sysrst_ctrl_ulp_z3_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/ coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_sysrst_ctrl_ulp_z3_wakeup.1091545667 |
| Directory | /workspace/0.chip_sw_sysrst_ctrl_ulp_z3_wakeup/latest |
| Test location | /workspace/coverage/default/0.chip_sw_uart_rand_baudrate.2966376333 |
| Short name | T434 |
| Test name | |
| Test status | |
| Simulation time | 4604261180 ps |
| CPU time | 662.05 seconds |
| Started | Aug 13 07:12:04 PM PDT 24 |
| Finished | Aug 13 07:23:08 PM PDT 24 |
| Peak memory | 620144 kb |
| Host | smart-398324f0-6ee9-4f2d-bfac-d1073b279c8d |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random _seed=2966376333 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_uart_rand_baudrate.2966376333 |
| Directory | /workspace/0.chip_sw_uart_rand_baudrate/latest |
| Test location | /workspace/coverage/default/0.chip_sw_uart_smoketest.1950575114 |
| Short name | T1192 |
| Test name | |
| Test status | |
| Simulation time | 2512612084 ps |
| CPU time | 282.53 seconds |
| Started | Aug 13 07:17:39 PM PDT 24 |
| Finished | Aug 13 07:22:22 PM PDT 24 |
| Peak memory | 612756 kb |
| Host | smart-05826767-4659-4118-937c-99355d47f8cf |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=uart_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1950575114 -assert nopostproc +UVM_TESTNAME=chi p_base_test +UVM_TEST_SEQ=chip_sw_uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 0.chip_sw_uart_smoketest.1950575114 |
| Directory | /workspace/0.chip_sw_uart_smoketest/latest |
| Test location | /workspace/coverage/default/0.chip_sw_uart_tx_rx.1616709251 |
| Short name | T229 |
| Test name | |
| Test status | |
| Simulation time | 4735883280 ps |
| CPU time | 703.73 seconds |
| Started | Aug 13 07:09:58 PM PDT 24 |
| Finished | Aug 13 07:21:43 PM PDT 24 |
| Peak memory | 620764 kb |
| Host | smart-e8a0e514-a2ac-4cad-b187-bdc9f9b38675 |
| User | root |
| Command | /workspace/default/simv +uart_idx=0 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1616709251 -a ssert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ce/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_uart_tx_rx.1616709251 |
| Directory | /workspace/0.chip_sw_uart_tx_rx/latest |
| Test location | /workspace/coverage/default/0.chip_sw_uart_tx_rx_alt_clk_freq.825937735 |
| Short name | T1261 |
| Test name | |
| Test status | |
| Simulation time | 12893214873 ps |
| CPU time | 2819.65 seconds |
| Started | Aug 13 07:09:00 PM PDT 24 |
| Finished | Aug 13 07:56:01 PM PDT 24 |
| Peak memory | 619464 kb |
| Host | smart-90bf60ff-ad3e-4960-aba1-f88720551b3b |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=80_000_000 +chip_clock_source=ChipClockSourceExternal96Mhz +calibrate_usb_clk=1 +sw_build_device=sim_dv +s w_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=825937735 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_ba udrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_uart_tx_rx_ alt_clk_freq.825937735 |
| Directory | /workspace/0.chip_sw_uart_tx_rx_alt_clk_freq/latest |
| Test location | /workspace/coverage/default/0.chip_sw_uart_tx_rx_alt_clk_freq_low_speed.807034353 |
| Short name | T340 |
| Test name | |
| Test status | |
| Simulation time | 4761345949 ps |
| CPU time | 498.96 seconds |
| Started | Aug 13 07:09:45 PM PDT 24 |
| Finished | Aug 13 07:18:05 PM PDT 24 |
| Peak memory | 625024 kb |
| Host | smart-bee666bf-e8c3-4039-9141-0329c2646819 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +chip_clock_source=ChipClockSourceExternal48Mhz +sw_build_device=sim_dv +s w_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=807034353 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_ba udrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_uart_tx_rx_ alt_clk_freq_low_speed.807034353 |
| Directory | /workspace/0.chip_sw_uart_tx_rx_alt_clk_freq_low_speed/latest |
| Test location | /workspace/coverage/default/0.chip_sw_uart_tx_rx_bootstrap.1637550807 |
| Short name | T1153 |
| Test name | |
| Test status | |
| Simulation time | 78930149201 ps |
| CPU time | 15179.4 seconds |
| Started | Aug 13 07:09:14 PM PDT 24 |
| Finished | Aug 13 11:22:16 PM PDT 24 |
| Peak memory | 635492 kb |
| Host | smart-76d3696a-c1cc-430a-8c62-daaacc2277aa |
| User | root |
| Command | /workspace/default/simv +use_spi_load_bootstrap=1 +calibrate_usb_clk=1 +test_timeout_ns=160_000_000 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test :1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=1637550807 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_uart_tx_rx_bootstrap.1637550807 |
| Directory | /workspace/0.chip_sw_uart_tx_rx_bootstrap/latest |
| Test location | /workspace/coverage/default/0.chip_sw_uart_tx_rx_idx2.2604464167 |
| Short name | T336 |
| Test name | |
| Test status | |
| Simulation time | 3939554240 ps |
| CPU time | 710.06 seconds |
| Started | Aug 13 07:10:42 PM PDT 24 |
| Finished | Aug 13 07:22:34 PM PDT 24 |
| Peak memory | 620536 kb |
| Host | smart-825ca610-f20a-4d13-aaba-c6f9f33aed5a |
| User | root |
| Command | /workspace/default/simv +uart_idx=2 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2604464167 -a ssert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ce/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_uart_tx_rx_idx2.2604464167 |
| Directory | /workspace/0.chip_sw_uart_tx_rx_idx2/latest |
| Test location | /workspace/coverage/default/0.chip_sw_usb_ast_clk_calib.1658167344 |
| Short name | T421 |
| Test name | |
| Test status | |
| Simulation time | 3168705863 ps |
| CPU time | 323.23 seconds |
| Started | Aug 13 07:12:42 PM PDT 24 |
| Finished | Aug 13 07:18:06 PM PDT 24 |
| Peak memory | 610384 kb |
| Host | smart-491e4cd9-0e15-49c6-a299-7a94f9d6c95b |
| User | root |
| Command | /workspace/default/simv +usb_max_drift=1 +usb_fast_sof=1 +sw_build_device=sim_dv +sw_images=ast_usb_clk_calib:1:new_rules,test_rom:0 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1658167344 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_usb_ast_clk_calib_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_usb_ast_clk_calib.1658167344 |
| Directory | /workspace/0.chip_sw_usb_ast_clk_calib/latest |
| Test location | /workspace/coverage/default/0.chip_sw_usbdev_config_host.3318897896 |
| Short name | T19 |
| Test name | |
| Test status | |
| Simulation time | 7878184338 ps |
| CPU time | 2063.82 seconds |
| Started | Aug 13 07:10:12 PM PDT 24 |
| Finished | Aug 13 07:44:37 PM PDT 24 |
| Peak memory | 609452 kb |
| Host | smart-eb577199-bd87-4e18-aaf5-2fcfeade985e |
| User | root |
| Command | /workspace/default/simv +uart_idx=0 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=usbdev_config_host_test:1:new_rules,test_rom:0 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33188 97896 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_usbdev_dpi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_usbdev_config_host.3318897896 |
| Directory | /workspace/0.chip_sw_usbdev_config_host/latest |
| Test location | /workspace/coverage/default/0.chip_sw_usbdev_dpi.4285688475 |
| Short name | T1125 |
| Test name | |
| Test status | |
| Simulation time | 11813533162 ps |
| CPU time | 3189.15 seconds |
| Started | Aug 13 07:08:36 PM PDT 24 |
| Finished | Aug 13 08:01:46 PM PDT 24 |
| Peak memory | 610900 kb |
| Host | smart-87a17e5f-ceb9-402d-b1b5-b6e8ab47199f |
| User | root |
| Command | /workspace/default/simv +uart_idx=0 +calibrate_usb_clk=1 +sw_test_timeout_ns=30_000_000 +sw_build_device=sim_dv +sw_images=usbdev_test:1:new_rules,tes t_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +nt b_random_seed=4285688475 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_usbdev_dpi_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_usbdev_dpi.4285688475 |
| Directory | /workspace/0.chip_sw_usbdev_dpi/latest |
| Test location | /workspace/coverage/default/0.chip_sw_usbdev_pincfg.719634895 |
| Short name | T23 |
| Test name | |
| Test status | |
| Simulation time | 31507363216 ps |
| CPU time | 6905.28 seconds |
| Started | Aug 13 07:11:56 PM PDT 24 |
| Finished | Aug 13 09:07:02 PM PDT 24 |
| Peak memory | 610828 kb |
| Host | smart-6fc6446f-0cc5-4a44-8a35-0e91beaefcc6 |
| User | root |
| Command | /workspace/default/simv +uart_idx=0 +calibrate_usb_clk=1 +sw_test_timeout_ns=100_000_000 +sw_build_device=sim_dv +sw_images=usbdev_pincfg_test:1:new_r ules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim .tcl +ntb_random_seed=719634895 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_usbdev_dpi_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_usbdev_pincfg.719634895 |
| Directory | /workspace/0.chip_sw_usbdev_pincfg/latest |
| Test location | /workspace/coverage/default/0.chip_sw_usbdev_pullup.1642289554 |
| Short name | T69 |
| Test name | |
| Test status | |
| Simulation time | 3129063940 ps |
| CPU time | 327.75 seconds |
| Started | Aug 13 07:10:32 PM PDT 24 |
| Finished | Aug 13 07:16:00 PM PDT 24 |
| Peak memory | 609212 kb |
| Host | smart-1bbac09e-a3e2-4fab-a163-a338886029e5 |
| User | root |
| Command | /workspace/default/simv +uart_idx=0 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=usbdev_pullup_test:1:new_rules,test_rom:0 +cdc_instrumenta tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1642289554 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_usbdev_dpi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work space/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_usbdev_pullup.1642289554 |
| Directory | /workspace/0.chip_sw_usbdev_pullup/latest |
| Test location | /workspace/coverage/default/0.chip_sw_usbdev_stream.1435486028 |
| Short name | T1227 |
| Test name | |
| Test status | |
| Simulation time | 18885537332 ps |
| CPU time | 4748.98 seconds |
| Started | Aug 13 07:08:27 PM PDT 24 |
| Finished | Aug 13 08:27:37 PM PDT 24 |
| Peak memory | 611016 kb |
| Host | smart-8797c26a-9b05-4967-aa8c-81e965456868 |
| User | root |
| Command | /workspace/default/simv +uart_idx=0 +calibrate_usb_clk=1 +sw_test_timeout_ns=60_000_000 +sw_build_device=sim_dv +sw_images=usbdev_stream_test:1:new_ru les,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim. tcl +ntb_random_seed=1435486028 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_usbdev_stream_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_usbdev_stream.1435486028 |
| Directory | /workspace/0.chip_sw_usbdev_stream/latest |
| Test location | /workspace/coverage/default/0.chip_sw_usbdev_vbus.1182956443 |
| Short name | T1364 |
| Test name | |
| Test status | |
| Simulation time | 3456644570 ps |
| CPU time | 280.96 seconds |
| Started | Aug 13 07:08:24 PM PDT 24 |
| Finished | Aug 13 07:13:06 PM PDT 24 |
| Peak memory | 610520 kb |
| Host | smart-4dbccdfe-c29c-4add-8626-9b225304a346 |
| User | root |
| Command | /workspace/default/simv +uart_idx=0 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=usbdev_vbus_test:1:new_rules,test_rom:0 +cdc_instrumentati on_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1182956443 - assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_usbdev_dpi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_usbdev_vbus.1182956443 |
| Directory | /workspace/0.chip_sw_usbdev_vbus/latest |
| Test location | /workspace/coverage/default/0.chip_tap_straps_prod.2494144085 |
| Short name | T1072 |
| Test name | |
| Test status | |
| Simulation time | 2436698014 ps |
| CPU time | 139.01 seconds |
| Started | Aug 13 07:14:36 PM PDT 24 |
| Finished | Aug 13 07:16:57 PM PDT 24 |
| Peak memory | 624876 kb |
| Host | smart-c4502a6d-035b-4e25-92f7-a16d71e94e2f |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStProd +create_jtag_riscv_map=1 +sw_build_device=sim_dv +sw_images=example_test_from_rom:0:test_in_rom :new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2494144085 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_tap_straps_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_tap_straps_prod.2494144085 |
| Directory | /workspace/0.chip_tap_straps_prod/latest |
| Test location | /workspace/coverage/default/0.chip_tap_straps_testunlock0.3796503244 |
| Short name | T436 |
| Test name | |
| Test status | |
| Simulation time | 3761926328 ps |
| CPU time | 307.6 seconds |
| Started | Aug 13 07:10:57 PM PDT 24 |
| Finished | Aug 13 07:16:06 PM PDT 24 |
| Peak memory | 625708 kb |
| Host | smart-4ec592f2-9aba-435d-9931-7b50b6f367b6 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStTestUnlocked0 +create_jtag_riscv_map=1 +sw_build_device=sim_dv +sw_images=example_test_from_rom:0:te st_in_rom:new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3796503244 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_tap_straps_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_tap_straps_testunlock0.3796503244 |
| Directory | /workspace/0.chip_tap_straps_testunlock0/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_asm_init_dev.3636813418 |
| Short name | T1091 |
| Test name | |
| Test status | |
| Simulation time | 15344054008 ps |
| CPU time | 3784.12 seconds |
| Started | Aug 13 07:16:46 PM PDT 24 |
| Finished | Aug 13 08:19:51 PM PDT 24 |
| Peak memory | 610820 kb |
| Host | smart-9b1a6468-0a97-4a44-9de0-4e28de098f71 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeCustom +sw_test_timeout_ns=20000000 +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_prod _key_0:1:ot_flash_binary,otp_img_e2e_bootstrap_entry_dev:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3636813418 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_S EQ=chip_sw_rom_e2e_asm_init_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_asm_init_dev.3636813418 |
| Directory | /workspace/0.rom_e2e_asm_init_dev/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_asm_init_prod.746766819 |
| Short name | T1051 |
| Test name | |
| Test status | |
| Simulation time | 15550492267 ps |
| CPU time | 4868.42 seconds |
| Started | Aug 13 07:20:25 PM PDT 24 |
| Finished | Aug 13 08:41:34 PM PDT 24 |
| Peak memory | 610728 kb |
| Host | smart-678a20fa-de41-403b-8492-03e9b1b75093 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeCustom +sw_test_timeout_ns=20000000 +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_prod _key_0:1:ot_flash_binary,otp_img_e2e_bootstrap_entry_prod:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=746766819 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_S EQ=chip_sw_rom_e2e_asm_init_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_asm_init_prod.746766819 |
| Directory | /workspace/0.rom_e2e_asm_init_prod/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_asm_init_prod_end.560912238 |
| Short name | T1325 |
| Test name | |
| Test status | |
| Simulation time | 15353815534 ps |
| CPU time | 4563.01 seconds |
| Started | Aug 13 07:19:30 PM PDT 24 |
| Finished | Aug 13 08:35:34 PM PDT 24 |
| Peak memory | 610596 kb |
| Host | smart-e6979f89-899a-449c-a5b1-1e526fb4bb2e |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeCustom +sw_test_timeout_ns=20000000 +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_prod _key_0:1:ot_flash_binary,otp_img_e2e_bootstrap_entry_prod_end:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=560912238 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TE ST_SEQ=chip_sw_rom_e2e_asm_init_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n ame 0.rom_e2e_asm_init_prod_end.560912238 |
| Directory | /workspace/0.rom_e2e_asm_init_prod_end/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_asm_init_rma.4259014027 |
| Short name | T1130 |
| Test name | |
| Test status | |
| Simulation time | 14422536540 ps |
| CPU time | 3824.13 seconds |
| Started | Aug 13 07:17:51 PM PDT 24 |
| Finished | Aug 13 08:21:37 PM PDT 24 |
| Peak memory | 610840 kb |
| Host | smart-edede733-c5b5-4ff4-af60-7a3b0e4da450 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeCustom +sw_test_timeout_ns=20000000 +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_prod _key_0:1:ot_flash_binary,otp_img_e2e_bootstrap_entry_rma:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4259014027 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_S EQ=chip_sw_rom_e2e_asm_init_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_asm_init_rma.4259014027 |
| Directory | /workspace/0.rom_e2e_asm_init_rma/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_asm_init_test_unlocked0.1218046398 |
| Short name | T976 |
| Test name | |
| Test status | |
| Simulation time | 11586264336 ps |
| CPU time | 3018.71 seconds |
| Started | Aug 13 07:18:36 PM PDT 24 |
| Finished | Aug 13 08:08:55 PM PDT 24 |
| Peak memory | 610536 kb |
| Host | smart-c393ff65-bd82-47b2-b79a-2524eb9e593b |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeCustom +sw_test_timeout_ns=410_000_000 +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_p rod_key_0:1:ot_flash_binary,otp_img_e2e_bootstrap_entry_test_unlocked0:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY =UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1218046398 -assert nopostproc +UVM_TESTNAME=chip_base_te st +UVM_TEST_SEQ=chip_sw_rom_e2e_asm_init_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/ null -cm_name 0.rom_e2e_asm_init_test_unlocked0.1218046398 |
| Directory | /workspace/0.rom_e2e_asm_init_test_unlocked0/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_bad_b_good_prod.4197272829 |
| Short name | T402 |
| Test name | |
| Test status | |
| Simulation time | 23976352456 ps |
| CPU time | 5605.09 seconds |
| Started | Aug 13 07:18:52 PM PDT 24 |
| Finished | Aug 13 08:52:17 PM PDT 24 |
| Peak memory | 611364 kb |
| Host | smart-bc9d10a8-f362-477d-b176-270bbcb5869f |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=100_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_corrupted:1: ot_flash_binary:signed:fake_ecdsa_prod_key_0,empty_test_slot_b_fake_ecdsa_prod_key_0:2:ot_flash_binary,otp_img_boot_policy_valid_prod:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=4197272829 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_boot_policy_valid_a_bad_b_good_prod.4197272829 |
| Directory | /workspace/0.rom_e2e_boot_policy_valid_a_bad_b_good_prod/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_bad_b_good_prod_end.3329662608 |
| Short name | T1396 |
| Test name | |
| Test status | |
| Simulation time | 24413603266 ps |
| CPU time | 6315.3 seconds |
| Started | Aug 13 07:21:22 PM PDT 24 |
| Finished | Aug 13 09:06:38 PM PDT 24 |
| Peak memory | 610636 kb |
| Host | smart-c2d09ce4-b55b-4bc3-a35a-f8f6dc2040db |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=100_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_corrupted:1: ot_flash_binary:signed:fake_ecdsa_prod_key_0,empty_test_slot_b_fake_ecdsa_prod_key_0:2:ot_flash_binary,otp_img_boot_policy_valid_prod_end:4,mask_r om:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r andom_seed=3329662608 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_boot_policy_valid_a_bad_b_good_prod_end.3329662608 |
| Directory | /workspace/0.rom_e2e_boot_policy_valid_a_bad_b_good_prod_end/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_bad_b_good_rma.1854359425 |
| Short name | T403 |
| Test name | |
| Test status | |
| Simulation time | 23093395184 ps |
| CPU time | 5951.21 seconds |
| Started | Aug 13 07:15:11 PM PDT 24 |
| Finished | Aug 13 08:54:23 PM PDT 24 |
| Peak memory | 611496 kb |
| Host | smart-f7227bfc-9178-4a5b-b05c-71946abbc187 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=100_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_corrupted:1: ot_flash_binary:signed:fake_ecdsa_prod_key_0,empty_test_slot_b_fake_ecdsa_prod_key_0:2:ot_flash_binary,otp_img_boot_policy_valid_rma:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random _seed=1854359425 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_boot_policy_valid_a_bad_b_good_rma.1854359425 |
| Directory | /workspace/0.rom_e2e_boot_policy_valid_a_bad_b_good_rma/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0.3514648136 |
| Short name | T296 |
| Test name | |
| Test status | |
| Simulation time | 18248379768 ps |
| CPU time | 4577.54 seconds |
| Started | Aug 13 07:18:43 PM PDT 24 |
| Finished | Aug 13 08:35:01 PM PDT 24 |
| Peak memory | 611480 kb |
| Host | smart-5041b59b-e2b5-4061-aa0d-eb551ab2e3fb |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=410_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_corrupted:1: ot_flash_binary:signed:fake_ecdsa_prod_key_0,empty_test_slot_b_fake_ecdsa_prod_key_0:2:ot_flash_binary,otp_img_boot_policy_valid_test_unlocked0:4, mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3514648136 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0.3514648136 |
| Directory | /workspace/0.rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_bad_dev.1816356133 |
| Short name | T1294 |
| Test name | |
| Test status | |
| Simulation time | 15224516912 ps |
| CPU time | 3543.69 seconds |
| Started | Aug 13 07:19:33 PM PDT 24 |
| Finished | Aug 13 08:18:38 PM PDT 24 |
| Peak memory | 610592 kb |
| Host | smart-565ced1c-724c-42d5-aadd-1484a48e5ab1 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=100_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_p rod_key_0:1:ot_flash_binary,empty_test_slot_b_corrupted:2:ot_flash_binary:signed:fake_ecdsa_prod_key_0,otp_img_boot_policy_valid_dev:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random _seed=1816356133 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_boot_policy_valid_a_good_b_bad_dev.1816356133 |
| Directory | /workspace/0.rom_e2e_boot_policy_valid_a_good_b_bad_dev/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_bad_prod.76070130 |
| Short name | T1067 |
| Test name | |
| Test status | |
| Simulation time | 16070511996 ps |
| CPU time | 3951.53 seconds |
| Started | Aug 13 07:18:14 PM PDT 24 |
| Finished | Aug 13 08:24:06 PM PDT 24 |
| Peak memory | 611488 kb |
| Host | smart-b5d8dc6e-ce29-4f90-ac43-b6f151f94685 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=100_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_p rod_key_0:1:ot_flash_binary,empty_test_slot_b_corrupted:2:ot_flash_binary:signed:fake_ecdsa_prod_key_0,otp_img_boot_policy_valid_prod:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=76070130 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_boot_policy_valid_a_good_b_bad_prod.76070130 |
| Directory | /workspace/0.rom_e2e_boot_policy_valid_a_good_b_bad_prod/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_bad_prod_end.331851546 |
| Short name | T1097 |
| Test name | |
| Test status | |
| Simulation time | 15450897924 ps |
| CPU time | 4697.66 seconds |
| Started | Aug 13 07:21:17 PM PDT 24 |
| Finished | Aug 13 08:39:35 PM PDT 24 |
| Peak memory | 611536 kb |
| Host | smart-d9d8c427-d8ea-4c5d-95c9-1d472d316357 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=100_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_p rod_key_0:1:ot_flash_binary,empty_test_slot_b_corrupted:2:ot_flash_binary:signed:fake_ecdsa_prod_key_0,otp_img_boot_policy_valid_prod_end:4,mask_r om:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r andom_seed=331851546 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_boot_policy_valid_a_good_b_bad_prod_end.331851546 |
| Directory | /workspace/0.rom_e2e_boot_policy_valid_a_good_b_bad_prod_end/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_bad_rma.2340602863 |
| Short name | T1195 |
| Test name | |
| Test status | |
| Simulation time | 14524781768 ps |
| CPU time | 3899.87 seconds |
| Started | Aug 13 07:16:38 PM PDT 24 |
| Finished | Aug 13 08:21:38 PM PDT 24 |
| Peak memory | 611508 kb |
| Host | smart-90dcbf46-d8d1-4d75-aed0-9b911e8c6afc |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=100_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_p rod_key_0:1:ot_flash_binary,empty_test_slot_b_corrupted:2:ot_flash_binary:signed:fake_ecdsa_prod_key_0,otp_img_boot_policy_valid_rma:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random _seed=2340602863 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_boot_policy_valid_a_good_b_bad_rma.2340602863 |
| Directory | /workspace/0.rom_e2e_boot_policy_valid_a_good_b_bad_rma/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0.351627935 |
| Short name | T1330 |
| Test name | |
| Test status | |
| Simulation time | 10802147148 ps |
| CPU time | 2949.88 seconds |
| Started | Aug 13 07:19:23 PM PDT 24 |
| Finished | Aug 13 08:08:34 PM PDT 24 |
| Peak memory | 611412 kb |
| Host | smart-52fd4e51-2eab-4edf-8a96-ef7cc0d0f80b |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=410_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_p rod_key_0:1:ot_flash_binary,empty_test_slot_b_corrupted:2:ot_flash_binary:signed:fake_ecdsa_prod_key_0,otp_img_boot_policy_valid_test_unlocked0:4, mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=351627935 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0.351627935 |
| Directory | /workspace/0.rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_good_dev.604887706 |
| Short name | T397 |
| Test name | |
| Test status | |
| Simulation time | 15789994640 ps |
| CPU time | 3793.56 seconds |
| Started | Aug 13 07:18:36 PM PDT 24 |
| Finished | Aug 13 08:21:50 PM PDT 24 |
| Peak memory | 611520 kb |
| Host | smart-b1c382a5-7d16-4798-8772-3c906c1b9e16 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=100_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_p rod_key_0:1:ot_flash_binary,empty_test_slot_b_fake_ecdsa_prod_key_0:2:ot_flash_binary,otp_img_boot_policy_valid_dev:4,mask_rom:0 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=604887706 - assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co verage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_boot_policy_valid_a_good_b_good_dev.604887706 |
| Directory | /workspace/0.rom_e2e_boot_policy_valid_a_good_b_good_dev/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_good_prod.962581447 |
| Short name | T1053 |
| Test name | |
| Test status | |
| Simulation time | 15421756540 ps |
| CPU time | 4147.94 seconds |
| Started | Aug 13 07:18:50 PM PDT 24 |
| Finished | Aug 13 08:27:59 PM PDT 24 |
| Peak memory | 611448 kb |
| Host | smart-864524fa-f71f-4981-9be7-873093d9ad34 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=100_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_p rod_key_0:1:ot_flash_binary,empty_test_slot_b_fake_ecdsa_prod_key_0:2:ot_flash_binary,otp_img_boot_policy_valid_prod:4,mask_rom:0 +cdc_instrumenta tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=962581447 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/c overage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_boot_policy_valid_a_good_b_good_prod.962581447 |
| Directory | /workspace/0.rom_e2e_boot_policy_valid_a_good_b_good_prod/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_good_prod_end.2078423180 |
| Short name | T1269 |
| Test name | |
| Test status | |
| Simulation time | 15719528484 ps |
| CPU time | 4350.7 seconds |
| Started | Aug 13 07:18:57 PM PDT 24 |
| Finished | Aug 13 08:31:28 PM PDT 24 |
| Peak memory | 611544 kb |
| Host | smart-137c3720-1fd9-4686-85ef-3f04af8e09ae |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=100_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_p rod_key_0:1:ot_flash_binary,empty_test_slot_b_fake_ecdsa_prod_key_0:2:ot_flash_binary,otp_img_boot_policy_valid_prod_end:4,mask_rom:0 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=207842 3180 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_boot_policy_valid_a_good_b_good_prod_end.2078423180 |
| Directory | /workspace/0.rom_e2e_boot_policy_valid_a_good_b_good_prod_end/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_good_rma.4045134425 |
| Short name | T1230 |
| Test name | |
| Test status | |
| Simulation time | 15217328500 ps |
| CPU time | 4400.21 seconds |
| Started | Aug 13 07:17:59 PM PDT 24 |
| Finished | Aug 13 08:31:19 PM PDT 24 |
| Peak memory | 611468 kb |
| Host | smart-6bc74a91-c177-4fa0-82b6-44fb220d5b65 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=100_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_p rod_key_0:1:ot_flash_binary,empty_test_slot_b_fake_ecdsa_prod_key_0:2:ot_flash_binary,otp_img_boot_policy_valid_rma:4,mask_rom:0 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4045134425 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/c overage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_boot_policy_valid_a_good_b_good_rma.4045134425 |
| Directory | /workspace/0.rom_e2e_boot_policy_valid_a_good_b_good_rma/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_good_test_unlocked0.854495801 |
| Short name | T1076 |
| Test name | |
| Test status | |
| Simulation time | 11344489476 ps |
| CPU time | 2725.05 seconds |
| Started | Aug 13 07:17:12 PM PDT 24 |
| Finished | Aug 13 08:02:38 PM PDT 24 |
| Peak memory | 611532 kb |
| Host | smart-2245a1a0-10c4-4c68-aeb2-f2c1bf3f5fe0 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=410_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_p rod_key_0:1:ot_flash_binary,empty_test_slot_b_fake_ecdsa_prod_key_0:2:ot_flash_binary,otp_img_boot_policy_valid_test_unlocked0:4,mask_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 854495801 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_boot_policy_valid_a_good_b_good_test_unlocked0.854495801 |
| Directory | /workspace/0.rom_e2e_boot_policy_valid_a_good_b_good_test_unlocked0/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_jtag_debug_rma.700011178 |
| Short name | T765 |
| Test name | |
| Test status | |
| Simulation time | 10803864154 ps |
| CPU time | 2265.79 seconds |
| Started | Aug 13 07:13:23 PM PDT 24 |
| Finished | Aug 13 07:51:10 PM PDT 24 |
| Peak memory | 625192 kb |
| Host | smart-8ad1da94-e445-4f39-b3ff-c833dede9930 |
| User | root |
| Command | /workspace/default/simv +use_jtag_dmi=1 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=img_rma_exec_disabled:4,mask_rom:0 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=70001 1178 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rom_e2e_jtag_debug_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_jtag_debug_rma.700011178 |
| Directory | /workspace/0.rom_e2e_jtag_debug_rma/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_jtag_debug_test_unlocked0.3490218186 |
| Short name | T263 |
| Test name | |
| Test status | |
| Simulation time | 11291066626 ps |
| CPU time | 1997.38 seconds |
| Started | Aug 13 07:11:56 PM PDT 24 |
| Finished | Aug 13 07:45:14 PM PDT 24 |
| Peak memory | 624612 kb |
| Host | smart-1bfc2983-5621-437b-8698-a2cb887c0037 |
| User | root |
| Command | /workspace/default/simv +use_jtag_dmi=1 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=img_test_unlocked0_exec_disabled:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random _seed=3490218186 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rom_e2e_jtag_debug_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_jtag_debug_test_unlocked0.3490218186 |
| Directory | /workspace/0.rom_e2e_jtag_debug_test_unlocked0/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_jtag_inject_dev.2190769712 |
| Short name | T766 |
| Test name | |
| Test status | |
| Simulation time | 34077551820 ps |
| CPU time | 2533.87 seconds |
| Started | Aug 13 07:12:38 PM PDT 24 |
| Finished | Aug 13 07:54:52 PM PDT 24 |
| Peak memory | 619832 kb |
| Host | smart-f2d29941-f91e-4ae9-8213-a054248f1002 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=40_000_000 +use_jtag_dmi=1 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=img_dev_exec_di sabled:4,sram_program:5,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2190769712 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rom_e2e_jtag_inject_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_jtag_inject_dev.2190769712 |
| Directory | /workspace/0.rom_e2e_jtag_inject_dev/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_jtag_inject_rma.2112163891 |
| Short name | T265 |
| Test name | |
| Test status | |
| Simulation time | 24767927271 ps |
| CPU time | 2153.74 seconds |
| Started | Aug 13 07:14:44 PM PDT 24 |
| Finished | Aug 13 07:50:38 PM PDT 24 |
| Peak memory | 619512 kb |
| Host | smart-bdb3142a-7c29-4894-a961-7e5c261fbdb8 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=40_000_000 +use_jtag_dmi=1 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=img_rma_exec_di sabled:4,sram_program:5,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2112163891 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rom_e2e_jtag_inject_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_jtag_inject_rma.2112163891 |
| Directory | /workspace/0.rom_e2e_jtag_inject_rma/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_jtag_inject_test_unlocked0.3198889396 |
| Short name | T1232 |
| Test name | |
| Test status | |
| Simulation time | 24388347746 ps |
| CPU time | 3086.19 seconds |
| Started | Aug 13 07:12:37 PM PDT 24 |
| Finished | Aug 13 08:04:04 PM PDT 24 |
| Peak memory | 619504 kb |
| Host | smart-3c0d7f4e-d281-43c0-a8b9-78b4aff8d8a3 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=40_000_000 +use_jtag_dmi=1 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=img_test_unlock ed0_exec_disabled:4,sram_program:5,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3198889396 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rom_e2e_jtag_ inject_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_jtag_inject _test_unlocked0.3198889396 |
| Directory | /workspace/0.rom_e2e_jtag_inject_test_unlocked0/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_keymgr_init_rom_ext_invalid_meas.182627269 |
| Short name | T1093 |
| Test name | |
| Test status | |
| Simulation time | 14823320040 ps |
| CPU time | 4366.62 seconds |
| Started | Aug 13 07:19:17 PM PDT 24 |
| Finished | Aug 13 08:32:04 PM PDT 24 |
| Peak memory | 610868 kb |
| Host | smart-14216bea-0514-43b7-a447-af484a279ea3 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=40_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=rom_e2e_keymgr_init_otp_invalid _meas:1:new_rules,otp_img_keymgr_otp_invalid_meas:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=182627269 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_ sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_keymgr_ini t_rom_ext_invalid_meas.182627269 |
| Directory | /workspace/0.rom_e2e_keymgr_init_rom_ext_invalid_meas/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_keymgr_init_rom_ext_meas.988532653 |
| Short name | T1169 |
| Test name | |
| Test status | |
| Simulation time | 15082454492 ps |
| CPU time | 3109.4 seconds |
| Started | Aug 13 07:21:46 PM PDT 24 |
| Finished | Aug 13 08:13:36 PM PDT 24 |
| Peak memory | 610812 kb |
| Host | smart-6c1b6207-1ca4-439e-b67c-dc46a37f0833 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=40_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=rom_e2e_keymgr_init_otp_meas:1: new_rules,otp_img_keymgr_otp_meas:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=988532653 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_keymgr_init_rom_ext_meas.988532653 |
| Directory | /workspace/0.rom_e2e_keymgr_init_rom_ext_meas/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_keymgr_init_rom_ext_no_meas.4148333984 |
| Short name | T43 |
| Test name | |
| Test status | |
| Simulation time | 14894785438 ps |
| CPU time | 2859.74 seconds |
| Started | Aug 13 07:15:19 PM PDT 24 |
| Finished | Aug 13 08:02:59 PM PDT 24 |
| Peak memory | 610748 kb |
| Host | smart-681b95b1-ea91-4801-a16a-030db6866c2a |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=40_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=rom_e2e_keymgr_init_otp_no_meas :1:new_rules,otp_img_keymgr_otp_no_meas:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4148333984 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_keymgr_init_rom_ext _no_meas.4148333984 |
| Directory | /workspace/0.rom_e2e_keymgr_init_rom_ext_no_meas/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_self_hash.2942807354 |
| Short name | T997 |
| Test name | |
| Test status | |
| Simulation time | 26230287744 ps |
| CPU time | 6567.8 seconds |
| Started | Aug 13 07:22:45 PM PDT 24 |
| Finished | Aug 13 09:12:14 PM PDT 24 |
| Peak memory | 610744 kb |
| Host | smart-d8284673-c618-468e-ad83-8ad7a8c4c99c |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=200_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=rom_e2e_self_hash_test:1:new_r ules,otp_img_sigverify_spx_prod:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2942807354 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_self_hash.2942807354 |
| Directory | /workspace/0.rom_e2e_self_hash/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_shutdown_exception_c.75465293 |
| Short name | T1163 |
| Test name | |
| Test status | |
| Simulation time | 15040098400 ps |
| CPU time | 3466.85 seconds |
| Started | Aug 13 07:16:31 PM PDT 24 |
| Finished | Aug 13 08:14:19 PM PDT 24 |
| Peak memory | 611076 kb |
| Host | smart-f1beac23-69b6-4b44-a192-3e067d53da9e |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=40000000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=rom_e2e_shutdown_exception_c:1:ne w_rules,otp_img_secret2_locked_rma:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75465293 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rom_e2e_shutd own_exception_c_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_sh utdown_exception_c.75465293 |
| Directory | /workspace/0.rom_e2e_shutdown_exception_c/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_shutdown_output.4106821308 |
| Short name | T183 |
| Test name | |
| Test status | |
| Simulation time | 24870461732 ps |
| CPU time | 3781.91 seconds |
| Started | Aug 13 07:15:19 PM PDT 24 |
| Finished | Aug 13 08:18:21 PM PDT 24 |
| Peak memory | 612172 kb |
| Host | smart-fc4293ed-b04c-4cd7-a96a-2f190eb65e69 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=20000000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_unsigned:1:ot_f lash_binary,otp_img_shutdown_output_test_unlocked0:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4106821308 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chi p_sw_rom_e2e_shutdown_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_shutdown_output.4106821308 |
| Directory | /workspace/0.rom_e2e_shutdown_output/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_bad_dev.2840755550 |
| Short name | T1141 |
| Test name | |
| Test status | |
| Simulation time | 22901234245 ps |
| CPU time | 5774.49 seconds |
| Started | Aug 13 07:17:13 PM PDT 24 |
| Finished | Aug 13 08:53:28 PM PDT 24 |
| Peak memory | 610544 kb |
| Host | smart-8d500fde-ea0e-4af6-ab96-4b2177d275b2 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=100_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_corrupted:1: ot_flash_binary:signed:fake_ecdsa_dev_key_0,empty_test_slot_b_corrupted:2:ot_flash_binary:signed:fake_ecdsa_dev_key_0,otp_img_sigverify_always_dev :4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t cl +ntb_random_seed=2840755550 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rom_e2e_sigverify_always_a_bad_b_bad_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_sigverify_always_a_bad_b_b ad_dev.2840755550 |
| Directory | /workspace/0.rom_e2e_sigverify_always_a_bad_b_bad_dev/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_bad_prod.3204287678 |
| Short name | T1410 |
| Test name | |
| Test status | |
| Simulation time | 23204027000 ps |
| CPU time | 5771.44 seconds |
| Started | Aug 13 07:17:07 PM PDT 24 |
| Finished | Aug 13 08:53:19 PM PDT 24 |
| Peak memory | 611620 kb |
| Host | smart-250a97af-9e30-423d-b419-1ddd48e8b988 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=100_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_corrupted:1: ot_flash_binary:signed:fake_ecdsa_prod_key_0,empty_test_slot_b_corrupted:2:ot_flash_binary:signed:fake_ecdsa_prod_key_0,otp_img_sigverify_always_p rod:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si m.tcl +ntb_random_seed=3204287678 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rom_e2e_sigverify_always_a_bad_b_bad_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_sigverify_always_a_bad_ b_bad_prod.3204287678 |
| Directory | /workspace/0.rom_e2e_sigverify_always_a_bad_b_bad_prod/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_bad_prod_end.3128347691 |
| Short name | T1252 |
| Test name | |
| Test status | |
| Simulation time | 23289396197 ps |
| CPU time | 6469.28 seconds |
| Started | Aug 13 07:20:08 PM PDT 24 |
| Finished | Aug 13 09:07:58 PM PDT 24 |
| Peak memory | 610488 kb |
| Host | smart-665dceb3-5f2b-4768-a1bb-ea9ea0e7ca45 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=100_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_corrupted:1: ot_flash_binary:signed:fake_ecdsa_prod_key_0,empty_test_slot_b_corrupted:2:ot_flash_binary:signed:fake_ecdsa_prod_key_0,otp_img_sigverify_always_p rod_end:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tool s/sim.tcl +ntb_random_seed=3128347691 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rom_e2e_sigverify_always_a_bad_b_bad_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_sigverify_always_a_ bad_b_bad_prod_end.3128347691 |
| Directory | /workspace/0.rom_e2e_sigverify_always_a_bad_b_bad_prod_end/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_bad_rma.2910400193 |
| Short name | T310 |
| Test name | |
| Test status | |
| Simulation time | 22129036296 ps |
| CPU time | 5253.68 seconds |
| Started | Aug 13 07:17:41 PM PDT 24 |
| Finished | Aug 13 08:45:16 PM PDT 24 |
| Peak memory | 611332 kb |
| Host | smart-9c59de94-ed30-421f-a391-c17fb3b31342 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=100_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_corrupted:1: ot_flash_binary:signed:fake_ecdsa_prod_key_0,empty_test_slot_b_corrupted:2:ot_flash_binary:signed:fake_ecdsa_prod_key_0,otp_img_sigverify_always_r ma:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim .tcl +ntb_random_seed=2910400193 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rom_e2e_sigverify_always_a_bad_b_bad_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_sigverify_always_a_bad_b _bad_rma.2910400193 |
| Directory | /workspace/0.rom_e2e_sigverify_always_a_bad_b_bad_rma/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0.2681057385 |
| Short name | T1073 |
| Test name | |
| Test status | |
| Simulation time | 18040822033 ps |
| CPU time | 5265.45 seconds |
| Started | Aug 13 07:20:07 PM PDT 24 |
| Finished | Aug 13 08:47:53 PM PDT 24 |
| Peak memory | 611188 kb |
| Host | smart-adc4e04a-4f32-4246-91d3-1ec44cc74b47 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=600_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_corrupted:1: ot_flash_binary:signed:fake_ecdsa_test_key_0,empty_test_slot_b_corrupted:2:ot_flash_binary:signed:fake_ecdsa_test_key_0,otp_img_sigverify_always_t est_unlocked0:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d v/tools/sim.tcl +ntb_random_seed=2681057385 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rom_e2e_sigverify_always_a_bad_b _bad_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_sigverify_alw ays_a_bad_b_bad_test_unlocked0.2681057385 |
| Directory | /workspace/0.rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_nothing_dev.1694203603 |
| Short name | T1352 |
| Test name | |
| Test status | |
| Simulation time | 15340942071 ps |
| CPU time | 3190.76 seconds |
| Started | Aug 13 07:16:44 PM PDT 24 |
| Finished | Aug 13 08:09:56 PM PDT 24 |
| Peak memory | 610524 kb |
| Host | smart-4b1c588d-2c41-4c2d-9b05-8a26ae76139e |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=100_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_corrupted:1: ot_flash_binary:signed:fake_ecdsa_dev_key_0,otp_img_sigverify_always_dev:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1694203603 -assert nopostproc +UVM_TESTNAME=chip_base_ test +UVM_TEST_SEQ=chip_sw_rom_e2e_sigverify_always_a_bad_b_bad_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def ault.vdb -cm_log /dev/null -cm_name 0.rom_e2e_sigverify_always_a_bad_b_nothing_dev.1694203603 |
| Directory | /workspace/0.rom_e2e_sigverify_always_a_bad_b_nothing_dev/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_nothing_prod.1335590471 |
| Short name | T1340 |
| Test name | |
| Test status | |
| Simulation time | 13967346446 ps |
| CPU time | 3462.68 seconds |
| Started | Aug 13 07:18:03 PM PDT 24 |
| Finished | Aug 13 08:15:47 PM PDT 24 |
| Peak memory | 610892 kb |
| Host | smart-a69554ee-8fc4-4072-b186-8ed739a157a1 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=100_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_corrupted:1: ot_flash_binary:signed:fake_ecdsa_prod_key_0,otp_img_sigverify_always_prod:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1335590471 -assert nopostproc +UVM_TESTNAME=chip_bas e_test +UVM_TEST_SEQ=chip_sw_rom_e2e_sigverify_always_a_bad_b_bad_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/d efault.vdb -cm_log /dev/null -cm_name 0.rom_e2e_sigverify_always_a_bad_b_nothing_prod.1335590471 |
| Directory | /workspace/0.rom_e2e_sigverify_always_a_bad_b_nothing_prod/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_nothing_prod_end.3560517141 |
| Short name | T984 |
| Test name | |
| Test status | |
| Simulation time | 15233971320 ps |
| CPU time | 4079.07 seconds |
| Started | Aug 13 07:18:37 PM PDT 24 |
| Finished | Aug 13 08:26:36 PM PDT 24 |
| Peak memory | 610864 kb |
| Host | smart-f62956b8-fc06-4526-9185-e7fcacb4b38d |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=100_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_corrupted:1: ot_flash_binary:signed:fake_ecdsa_prod_key_0,otp_img_sigverify_always_prod_end:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3560517141 -assert nopostproc +UVM_TESTNAME=chip _base_test +UVM_TEST_SEQ=chip_sw_rom_e2e_sigverify_always_a_bad_b_bad_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera ge/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_sigverify_always_a_bad_b_nothing_prod_end.3560517141 |
| Directory | /workspace/0.rom_e2e_sigverify_always_a_bad_b_nothing_prod_end/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0.3605981678 |
| Short name | T42 |
| Test name | |
| Test status | |
| Simulation time | 11243798684 ps |
| CPU time | 2944.39 seconds |
| Started | Aug 13 07:14:49 PM PDT 24 |
| Finished | Aug 13 08:03:54 PM PDT 24 |
| Peak memory | 611360 kb |
| Host | smart-f697c3ec-6a2f-40b1-a71a-72d7244513ce |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=410_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_corrupted:1: ot_flash_binary:signed:fake_ecdsa_test_key_0:new_rules,otp_img_sigverify_always_test_unlocked0:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3605981678 -assert nopostproc +U VM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rom_e2e_sigverify_always_a_bad_b_bad_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0.3605981678 |
| Directory | /workspace/0.rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_sigverify_always_a_nothing_b_bad_dev.2653015833 |
| Short name | T1161 |
| Test name | |
| Test status | |
| Simulation time | 14860596382 ps |
| CPU time | 3565.74 seconds |
| Started | Aug 13 07:17:07 PM PDT 24 |
| Finished | Aug 13 08:16:34 PM PDT 24 |
| Peak memory | 610528 kb |
| Host | smart-f7d456ec-b1ee-4b22-89d0-10f8c5efc182 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=100_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_b_corrupted:1: ot_flash_binary:signed:fake_ecdsa_dev_key_0,otp_img_sigverify_always_dev:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2653015833 -assert nopostproc +UVM_TESTNAME=chip_base_ test +UVM_TEST_SEQ=chip_sw_rom_e2e_sigverify_always_a_bad_b_bad_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def ault.vdb -cm_log /dev/null -cm_name 0.rom_e2e_sigverify_always_a_nothing_b_bad_dev.2653015833 |
| Directory | /workspace/0.rom_e2e_sigverify_always_a_nothing_b_bad_dev/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_sigverify_always_a_nothing_b_bad_prod.1746019871 |
| Short name | T1359 |
| Test name | |
| Test status | |
| Simulation time | 15111437032 ps |
| CPU time | 4333.38 seconds |
| Started | Aug 13 07:20:32 PM PDT 24 |
| Finished | Aug 13 08:32:47 PM PDT 24 |
| Peak memory | 611880 kb |
| Host | smart-be31e365-9d9e-4a04-bbbb-0ed42eb3c6eb |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=100_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_b_corrupted:1: ot_flash_binary:signed:fake_ecdsa_prod_key_0,otp_img_sigverify_always_prod:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1746019871 -assert nopostproc +UVM_TESTNAME=chip_bas e_test +UVM_TEST_SEQ=chip_sw_rom_e2e_sigverify_always_a_bad_b_bad_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/d efault.vdb -cm_log /dev/null -cm_name 0.rom_e2e_sigverify_always_a_nothing_b_bad_prod.1746019871 |
| Directory | /workspace/0.rom_e2e_sigverify_always_a_nothing_b_bad_prod/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_sigverify_always_a_nothing_b_bad_prod_end.2838020770 |
| Short name | T1324 |
| Test name | |
| Test status | |
| Simulation time | 15377592427 ps |
| CPU time | 4260.17 seconds |
| Started | Aug 13 07:21:09 PM PDT 24 |
| Finished | Aug 13 08:32:10 PM PDT 24 |
| Peak memory | 611176 kb |
| Host | smart-29fd68ea-5383-4e4f-ae11-5587a7389b10 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=100_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_b_corrupted:1: ot_flash_binary:signed:fake_ecdsa_prod_key_0,otp_img_sigverify_always_prod_end:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2838020770 -assert nopostproc +UVM_TESTNAME=chip _base_test +UVM_TEST_SEQ=chip_sw_rom_e2e_sigverify_always_a_bad_b_bad_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera ge/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_sigverify_always_a_nothing_b_bad_prod_end.2838020770 |
| Directory | /workspace/0.rom_e2e_sigverify_always_a_nothing_b_bad_prod_end/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_sigverify_always_a_nothing_b_bad_rma.728121737 |
| Short name | T1150 |
| Test name | |
| Test status | |
| Simulation time | 13963969726 ps |
| CPU time | 3171.82 seconds |
| Started | Aug 13 07:18:31 PM PDT 24 |
| Finished | Aug 13 08:11:23 PM PDT 24 |
| Peak memory | 610512 kb |
| Host | smart-39ad4ee5-1658-481a-a887-53b33513e435 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=100_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_b_corrupted:1: ot_flash_binary:signed:fake_ecdsa_prod_key_0,otp_img_sigverify_always_rma:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=728121737 -assert nopostproc +UVM_TESTNAME=chip_base_ test +UVM_TEST_SEQ=chip_sw_rom_e2e_sigverify_always_a_bad_b_bad_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def ault.vdb -cm_log /dev/null -cm_name 0.rom_e2e_sigverify_always_a_nothing_b_bad_rma.728121737 |
| Directory | /workspace/0.rom_e2e_sigverify_always_a_nothing_b_bad_rma/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0.1543149323 |
| Short name | T1017 |
| Test name | |
| Test status | |
| Simulation time | 10661470138 ps |
| CPU time | 3027.6 seconds |
| Started | Aug 13 07:21:23 PM PDT 24 |
| Finished | Aug 13 08:11:51 PM PDT 24 |
| Peak memory | 610560 kb |
| Host | smart-c212ecf9-8aee-4aa9-9068-7c92eb435ce4 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=410_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_b_corrupted:1: ot_flash_binary:signed:fake_ecdsa_test_key_0,otp_img_sigverify_always_test_unlocked0:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1543149323 -assert nopostproc +UVM_TESTNAM E=chip_base_test +UVM_TEST_SEQ=chip_sw_rom_e2e_sigverify_always_a_bad_b_bad_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/ coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0.1543149323 |
| Directory | /workspace/0.rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_smoke.1085143252 |
| Short name | T1106 |
| Test name | |
| Test status | |
| Simulation time | 14459574488 ps |
| CPU time | 3996.85 seconds |
| Started | Aug 13 07:16:20 PM PDT 24 |
| Finished | Aug 13 08:22:57 PM PDT 24 |
| Peak memory | 610860 kb |
| Host | smart-72f1d488-46d8-424b-83a3-f658327f0595 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=40000000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=rom_e2e_smoke:1:new_rules,otp_img _secret2_locked_rma:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_to p/hw/dv/tools/sim.tcl +ntb_random_seed=1085143252 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_smoke.1085143252 |
| Directory | /workspace/0.rom_e2e_smoke/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_static_critical.802519285 |
| Short name | T419 |
| Test name | |
| Test status | |
| Simulation time | 17106133800 ps |
| CPU time | 4432.3 seconds |
| Started | Aug 13 07:18:51 PM PDT 24 |
| Finished | Aug 13 08:32:44 PM PDT 24 |
| Peak memory | 610812 kb |
| Host | smart-630b3f1e-f79c-4c54-9bbd-dde0f816a0b6 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=40000000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=rom_e2e_static_critical:1:new_rul es,otp_img_secret2_locked_rma:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=802519285 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_static_critical.802519285 |
| Directory | /workspace/0.rom_e2e_static_critical/latest |
| Test location | /workspace/coverage/default/0.rom_keymgr_functest.3846739878 |
| Short name | T1003 |
| Test name | |
| Test status | |
| Simulation time | 4609362338 ps |
| CPU time | 431.28 seconds |
| Started | Aug 13 07:10:53 PM PDT 24 |
| Finished | Aug 13 07:18:04 PM PDT 24 |
| Peak memory | 611364 kb |
| Host | smart-0ad30e5f-dee4-4177-9ce6-296aa62f07c7 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=10_000_000 +sw_build_device=sim_dv +sw_images=keymgr_functest:1:new_rules,test_rom:0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3846739878 -ass ert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 0.rom_keymgr_functest.3846739878 |
| Directory | /workspace/0.rom_keymgr_functest/latest |
| Test location | /workspace/coverage/default/0.rom_raw_unlock.4231788822 |
| Short name | T157 |
| Test name | |
| Test status | |
| Simulation time | 6897980462 ps |
| CPU time | 341.59 seconds |
| Started | Aug 13 07:15:25 PM PDT 24 |
| Finished | Aug 13 07:21:08 PM PDT 24 |
| Peak memory | 620064 kb |
| Host | smart-01e8bdd7-9b62-41e3-9e9a-0353db1f1ec4 |
| User | root |
| Command | /workspace/default/simv +do_creator_sw_cfg_ast_cfg=0 +sw_test_timeout_ns=200_000_000 +use_otp_image=OtpTypeLcStRaw +chip_clock_source=ChipClockSourceE xternal48Mhz +rom_prod_mode=1 +use_jtag_dmi=1 +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_test_key_0:1:ot_flash_binary,mask_ro m:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=4231788822 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_raw_unlock_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_raw_unlock.4231788822 |
| Directory | /workspace/0.rom_raw_unlock/latest |
| Test location | /workspace/coverage/default/0.rom_volatile_raw_unlock.3492245668 |
| Short name | T60 |
| Test name | |
| Test status | |
| Simulation time | 2499245143 ps |
| CPU time | 135.6 seconds |
| Started | Aug 13 07:17:31 PM PDT 24 |
| Finished | Aug 13 07:19:47 PM PDT 24 |
| Peak memory | 618188 kb |
| Host | smart-730eea1b-c623-49f4-8bcc-3b0d277b1841 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=200_000_000 +use_otp_image=OtpTypeLcStRaw +chip_clock_source=ChipClockSourceExternal48Mhz +rom_prod_mode=1 +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_test_key_0:1:ot_flash_binary,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3492245668 -assert nopostproc +UVM_ TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_volatile_raw_unlock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag e/default.vdb -cm_log /dev/null -cm_name 0.rom_volatile_raw_unlock.3492245668 |
| Directory | /workspace/0.rom_volatile_raw_unlock/latest |
| Test location | /workspace/coverage/default/1.chip_jtag_csr_rw.1428579487 |
| Short name | T76 |
| Test name | |
| Test status | |
| Simulation time | 12691913900 ps |
| CPU time | 1783.93 seconds |
| Started | Aug 13 07:11:52 PM PDT 24 |
| Finished | Aug 13 07:41:36 PM PDT 24 |
| Peak memory | 608464 kb |
| Host | smart-ba746450-f7ff-4a0a-8822-31bf4b45473e |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +csr_rw +create_jtag_riscv_map=1 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1428579487 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_T EST_SEQ=chip_jtag_csr_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.c hip_jtag_csr_rw.1428579487 |
| Directory | /workspace/1.chip_jtag_csr_rw/latest |
| Test location | /workspace/coverage/default/1.chip_jtag_mem_access.2836148419 |
| Short name | T211 |
| Test name | |
| Test status | |
| Simulation time | 13307483048 ps |
| CPU time | 1758.81 seconds |
| Started | Aug 13 07:11:26 PM PDT 24 |
| Finished | Aug 13 07:40:45 PM PDT 24 |
| Peak memory | 608500 kb |
| Host | smart-d99a2974-c42e-4f42-8652-b8da477406fd |
| User | root |
| Command | /workspace/default/simv +create_jtag_riscv_map=1 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2836148419 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_jtag_ mem_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_jtag_mem_access.2 836148419 |
| Directory | /workspace/1.chip_jtag_mem_access/latest |
| Test location | /workspace/coverage/default/1.chip_rv_dm_ndm_reset_req.3272352363 |
| Short name | T108 |
| Test name | |
| Test status | |
| Simulation time | 4399740832 ps |
| CPU time | 539.37 seconds |
| Started | Aug 13 07:19:05 PM PDT 24 |
| Finished | Aug 13 07:28:04 PM PDT 24 |
| Peak memory | 620328 kb |
| Host | smart-1f49d7ba-3ae4-4422-9e4c-4dc4d104a285 |
| User | root |
| Command | /workspace/default/simv +en_scb_tl_err_chk=0 +use_jtag_dmi=1 +sw_build_device=sim_dv +sw_images=rv_dm_ndm_reset_req_rma:1:new_rules,test_rom:0 +cdc_in strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3 272352363 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_rv_dm_ndm_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_rv_dm_ndm_reset_req.3272352363 |
| Directory | /workspace/1.chip_rv_dm_ndm_reset_req/latest |
| Test location | /workspace/coverage/default/1.chip_sival_flash_info_access.3452226269 |
| Short name | T363 |
| Test name | |
| Test status | |
| Simulation time | 2784129432 ps |
| CPU time | 259.9 seconds |
| Started | Aug 13 07:13:03 PM PDT 24 |
| Finished | Aug 13 07:17:23 PM PDT 24 |
| Peak memory | 609904 kb |
| Host | smart-d11101da-8a4f-4b34-8bdd-5f8b1867367b |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStTestUnlocked0 +sw_build_device=sim_dv +sw_images=flash_ctrl_info_access_lc:1:new_rules,test_rom:0 +c dc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_s eed=3452226269 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sival_flash_info_access.3452226269 |
| Directory | /workspace/1.chip_sival_flash_info_access/latest |
| Test location | /workspace/coverage/default/1.chip_sw_adc_ctrl_sleep_debug_cable_wakeup.481965285 |
| Short name | T1238 |
| Test name | |
| Test status | |
| Simulation time | 18598127600 ps |
| CPU time | 568.54 seconds |
| Started | Aug 13 07:17:13 PM PDT 24 |
| Finished | Aug 13 07:26:42 PM PDT 24 |
| Peak memory | 619992 kb |
| Host | smart-8ee4b7e8-debe-466c-9427-59f70080b21c |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=adc_ctrl_sleep_debug_cable_wakeup_test:1:new_rules,test_rom: 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand om_seed=481965285 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_adc_ctrl_sleep_debug_cable_wakeup_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_adc_ctrl_sleep_debug_cable_wakeup.481965285 |
| Directory | /workspace/1.chip_sw_adc_ctrl_sleep_debug_cable_wakeup/latest |
| Test location | /workspace/coverage/default/1.chip_sw_aes_enc.3652087894 |
| Short name | T983 |
| Test name | |
| Test status | |
| Simulation time | 3399135680 ps |
| CPU time | 345.9 seconds |
| Started | Aug 13 07:17:05 PM PDT 24 |
| Finished | Aug 13 07:22:51 PM PDT 24 |
| Peak memory | 610456 kb |
| Host | smart-cfcc1992-c822-414f-9fcc-d53e1b5be4eb |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=22_000_000 +sw_build_device=sim_dv +sw_images=aes_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3652087894 -asser t nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag e/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_aes_enc.3652087894 |
| Directory | /workspace/1.chip_sw_aes_enc/latest |
| Test location | /workspace/coverage/default/1.chip_sw_aes_enc_jitter_en.3241634558 |
| Short name | T1242 |
| Test name | |
| Test status | |
| Simulation time | 2660034345 ps |
| CPU time | 237.79 seconds |
| Started | Aug 13 07:15:56 PM PDT 24 |
| Finished | Aug 13 07:19:55 PM PDT 24 |
| Peak memory | 610432 kb |
| Host | smart-ecd17e1c-7175-4b79-bef9-b992ee8232f9 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=26_000_000 +en_jitter=1 +sw_build_device=sim_dv +sw_images=aes_smoketest:1:new_rules,test_rom:0 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3241 634558 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work space/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_aes_enc_jitter_en.3241634558 |
| Directory | /workspace/1.chip_sw_aes_enc_jitter_en/latest |
| Test location | /workspace/coverage/default/1.chip_sw_aes_enc_jitter_en_reduced_freq.2280545879 |
| Short name | T1018 |
| Test name | |
| Test status | |
| Simulation time | 2770039015 ps |
| CPU time | 255.19 seconds |
| Started | Aug 13 07:21:49 PM PDT 24 |
| Finished | Aug 13 07:26:04 PM PDT 24 |
| Peak memory | 609188 kb |
| Host | smart-465fa597-fc2a-4c64-9807-d3515d127c9a |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=26_000_000 +en_jitter=1 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=aes_smoketest:1:new_rules, test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2280545879 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_aes_enc_jitter_en_reduced_freq.2280545879 |
| Directory | /workspace/1.chip_sw_aes_enc_jitter_en_reduced_freq/latest |
| Test location | /workspace/coverage/default/1.chip_sw_aes_entropy.913990249 |
| Short name | T967 |
| Test name | |
| Test status | |
| Simulation time | 3382532136 ps |
| CPU time | 222.43 seconds |
| Started | Aug 13 07:21:12 PM PDT 24 |
| Finished | Aug 13 07:24:55 PM PDT 24 |
| Peak memory | 610420 kb |
| Host | smart-05aae63e-9b1b-484e-a05c-ea22a748e903 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=15_000_000 +sw_build_device=sim_dv +sw_images=aes_entropy_test:1:new_rules,test_rom:0 +cdc_instrumentation _enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=913990249 -ass ert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_aes_entropy.913990249 |
| Directory | /workspace/1.chip_sw_aes_entropy/latest |
| Test location | /workspace/coverage/default/1.chip_sw_aes_idle.3586279157 |
| Short name | T1336 |
| Test name | |
| Test status | |
| Simulation time | 2660698800 ps |
| CPU time | 244.24 seconds |
| Started | Aug 13 07:18:05 PM PDT 24 |
| Finished | Aug 13 07:22:09 PM PDT 24 |
| Peak memory | 610456 kb |
| Host | smart-384a1a03-5e29-4c99-864c-4abaa1335314 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=25_000_000 +sw_build_device=sim_dv +sw_images=aes_idle_test:1:new_rules,test_rom:0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3586279157 -asser t nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag e/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_aes_idle.3586279157 |
| Directory | /workspace/1.chip_sw_aes_idle/latest |
| Test location | /workspace/coverage/default/1.chip_sw_aes_masking_off.151120717 |
| Short name | T295 |
| Test name | |
| Test status | |
| Simulation time | 2829631180 ps |
| CPU time | 323.22 seconds |
| Started | Aug 13 07:18:39 PM PDT 24 |
| Finished | Aug 13 07:24:03 PM PDT 24 |
| Peak memory | 610396 kb |
| Host | smart-53af67c1-0d37-4ad3-acc0-647ec64553cd |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=aes_masking_off_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=151120717 -assert nopostproc +UVM_TESTNAM E=chip_base_test +UVM_TEST_SEQ=chip_sw_aes_masking_off_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_aes_masking_off.151120717 |
| Directory | /workspace/1.chip_sw_aes_masking_off/latest |
| Test location | /workspace/coverage/default/1.chip_sw_aes_smoketest.2432527183 |
| Short name | T942 |
| Test name | |
| Test status | |
| Simulation time | 2913256360 ps |
| CPU time | 253.13 seconds |
| Started | Aug 13 07:22:23 PM PDT 24 |
| Finished | Aug 13 07:26:36 PM PDT 24 |
| Peak memory | 609812 kb |
| Host | smart-b597173d-8a66-42fd-8c76-67e88311e411 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=aes_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2432527183 -assert nopostproc +UVM_TESTNAME=chip _base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_aes_smoketest.2432527183 |
| Directory | /workspace/1.chip_sw_aes_smoketest/latest |
| Test location | /workspace/coverage/default/1.chip_sw_alert_handler_entropy.784144359 |
| Short name | T1319 |
| Test name | |
| Test status | |
| Simulation time | 3451390148 ps |
| CPU time | 363.2 seconds |
| Started | Aug 13 07:14:52 PM PDT 24 |
| Finished | Aug 13 07:20:56 PM PDT 24 |
| Peak memory | 610384 kb |
| Host | smart-7aa5a718-4fc0-43cf-9de7-1fb9b023cadb |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=alert_handler_entropy_test:1:new_rules,test_ro m:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=784144359 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_alert_handler_entropy.784144359 |
| Directory | /workspace/1.chip_sw_alert_handler_entropy/latest |
| Test location | /workspace/coverage/default/1.chip_sw_alert_handler_escalation.2812274646 |
| Short name | T1023 |
| Test name | |
| Test status | |
| Simulation time | 4888886206 ps |
| CPU time | 522.14 seconds |
| Started | Aug 13 07:16:22 PM PDT 24 |
| Finished | Aug 13 07:25:04 PM PDT 24 |
| Peak memory | 620368 kb |
| Host | smart-ec3659b5-83a9-44b6-a48f-50609727288e |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=alert_handler_escalation_test:1:new_rules,test _rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb _random_seed=2812274646 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_alert_handler_escalation_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_alert_handler_escalation.2812274646 |
| Directory | /workspace/1.chip_sw_alert_handler_escalation/latest |
| Test location | /workspace/coverage/default/1.chip_sw_alert_handler_lpg_clkoff.1384882732 |
| Short name | T1110 |
| Test name | |
| Test status | |
| Simulation time | 7967867768 ps |
| CPU time | 2211.3 seconds |
| Started | Aug 13 07:18:59 PM PDT 24 |
| Finished | Aug 13 07:55:51 PM PDT 24 |
| Peak memory | 610876 kb |
| Host | smart-086fc449-a218-4d84-98b4-330979539de6 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +sw_build_device=sim_dv +sw_images=alert_handler_lpg_clkoff_test:1:new_rules,test_r om:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r andom_seed=1384882732 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_alert_handler_lpg_clkoff_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_alert_handler_lpg_clkoff.1384882732 |
| Directory | /workspace/1.chip_sw_alert_handler_lpg_clkoff/latest |
| Test location | /workspace/coverage/default/1.chip_sw_alert_handler_lpg_reset_toggle.137019784 |
| Short name | T1355 |
| Test name | |
| Test status | |
| Simulation time | 7008941540 ps |
| CPU time | 1693.25 seconds |
| Started | Aug 13 07:16:12 PM PDT 24 |
| Finished | Aug 13 07:44:25 PM PDT 24 |
| Peak memory | 610864 kb |
| Host | smart-39161aa0-10f2-449b-ba2c-0e8696d2a0c2 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +sw_build_device=sim_dv +sw_images=alert_handler_lpg_reset_toggle_test:1:new_rules, test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=137019784 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_alert_handler_shorten_ping_wait_cycle_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_alert_handler_lpg_reset_toggle.137019784 |
| Directory | /workspace/1.chip_sw_alert_handler_lpg_reset_toggle/latest |
| Test location | /workspace/coverage/default/1.chip_sw_alert_handler_lpg_sleep_mode_pings.668773397 |
| Short name | T81 |
| Test name | |
| Test status | |
| Simulation time | 12595202376 ps |
| CPU time | 1344.31 seconds |
| Started | Aug 13 07:18:18 PM PDT 24 |
| Finished | Aug 13 07:40:42 PM PDT 24 |
| Peak memory | 611652 kb |
| Host | smart-8884f862-943f-4ae8-9e13-e8009fb7e56b |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=alert_handler _lpg_sleep_mode_pings_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=668773397 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_alert_hand ler_shorten_ping_wait_cycle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_alert_handler_lpg_sleep_mode_pings.668773397 |
| Directory | /workspace/1.chip_sw_alert_handler_lpg_sleep_mode_pings/latest |
| Test location | /workspace/coverage/default/1.chip_sw_alert_handler_ping_ok.3467825074 |
| Short name | T1224 |
| Test name | |
| Test status | |
| Simulation time | 8658145324 ps |
| CPU time | 1560.37 seconds |
| Started | Aug 13 07:18:42 PM PDT 24 |
| Finished | Aug 13 07:44:43 PM PDT 24 |
| Peak memory | 609624 kb |
| Host | smart-7b873f6e-9083-45d7-8151-a2df7545d57c |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=24000000 +sw_build_device=sim_dv +sw_images=alert_handler_ping_ok_test:1:new_rules,test_rom:0 +c dc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_s eed=3467825074 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_alert_handler_ping_ok.3467825074 |
| Directory | /workspace/1.chip_sw_alert_handler_ping_ok/latest |
| Test location | /workspace/coverage/default/1.chip_sw_alert_handler_ping_timeout.441478119 |
| Short name | T299 |
| Test name | |
| Test status | |
| Simulation time | 3767073884 ps |
| CPU time | 391.42 seconds |
| Started | Aug 13 07:18:55 PM PDT 24 |
| Finished | Aug 13 07:25:27 PM PDT 24 |
| Peak memory | 610368 kb |
| Host | smart-72d5d44f-a5fd-424d-a393-8f90e1913551 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=24000000 +sw_build_device=sim_dv +sw_images=alert_handler_ping_timeout_test:1:new_rules,test_rom :0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=441478119 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_alert_handler_ping_timeout.441478119 |
| Directory | /workspace/1.chip_sw_alert_handler_ping_timeout/latest |
| Test location | /workspace/coverage/default/1.chip_sw_alert_handler_reverse_ping_in_deep_sleep.3617885446 |
| Short name | T78 |
| Test name | |
| Test status | |
| Simulation time | 255044445204 ps |
| CPU time | 11158.4 seconds |
| Started | Aug 13 07:18:24 PM PDT 24 |
| Finished | Aug 13 10:24:24 PM PDT 24 |
| Peak memory | 611468 kb |
| Host | smart-6a2dbfe6-3459-44e4-bce9-13ee94375d50 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=300_000_000 +sw_build_device=sim_dv +sw_images=alert_handler_reverse_ping_in_deep_sleep_test:1:n ew_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3617885446 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_alert_handler_reverse_ping_in_deep_sleep.3617885446 |
| Directory | /workspace/1.chip_sw_alert_handler_reverse_ping_in_deep_sleep/latest |
| Test location | /workspace/coverage/default/1.chip_sw_aon_timer_irq.1450212422 |
| Short name | T1303 |
| Test name | |
| Test status | |
| Simulation time | 4048957216 ps |
| CPU time | 284.48 seconds |
| Started | Aug 13 07:16:15 PM PDT 24 |
| Finished | Aug 13 07:20:59 PM PDT 24 |
| Peak memory | 610432 kb |
| Host | smart-da679c3e-31ba-4d4f-96a7-7294188c0142 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=aon_timer_irq_test:1:new_rules,test_rom:0 +cdc_instrumentati on_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1450212422 - assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co verage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_aon_timer_irq.1450212422 |
| Directory | /workspace/1.chip_sw_aon_timer_irq/latest |
| Test location | /workspace/coverage/default/1.chip_sw_aon_timer_sleep_wdog_sleep_pause.3712693437 |
| Short name | T1306 |
| Test name | |
| Test status | |
| Simulation time | 7010287408 ps |
| CPU time | 631 seconds |
| Started | Aug 13 07:15:15 PM PDT 24 |
| Finished | Aug 13 07:25:47 PM PDT 24 |
| Peak memory | 609924 kb |
| Host | smart-af928ce5-bf25-48a7-bdac-873b650a7cef |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=aon_timer_sleep_wdog_sleep_pause_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=3712693437 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_aon_timer_sleep_wdog_sleep_pause.3712693437 |
| Directory | /workspace/1.chip_sw_aon_timer_sleep_wdog_sleep_pause/latest |
| Test location | /workspace/coverage/default/1.chip_sw_aon_timer_smoketest.3982826290 |
| Short name | T944 |
| Test name | |
| Test status | |
| Simulation time | 3426262280 ps |
| CPU time | 365.69 seconds |
| Started | Aug 13 07:22:40 PM PDT 24 |
| Finished | Aug 13 07:28:46 PM PDT 24 |
| Peak memory | 610480 kb |
| Host | smart-f3e06e3f-c954-49a7-95b8-eb3c248d0042 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=aon_timer_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3982826290 -assert nopostproc +UVM_TESTNAM E=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 1.chip_sw_aon_timer_smoketest.3982826290 |
| Directory | /workspace/1.chip_sw_aon_timer_smoketest/latest |
| Test location | /workspace/coverage/default/1.chip_sw_aon_timer_wdog_bite_reset.1076602893 |
| Short name | T1012 |
| Test name | |
| Test status | |
| Simulation time | 8682225688 ps |
| CPU time | 926.93 seconds |
| Started | Aug 13 07:18:44 PM PDT 24 |
| Finished | Aug 13 07:34:12 PM PDT 24 |
| Peak memory | 610912 kb |
| Host | smart-e57ea548-dad5-4dac-8b62-806009d54212 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=aon_timer_wdog_bite_reset_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 1076602893 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_aon_timer_wdog_bite_reset.1076602893 |
| Directory | /workspace/1.chip_sw_aon_timer_wdog_bite_reset/latest |
| Test location | /workspace/coverage/default/1.chip_sw_aon_timer_wdog_lc_escalate.3358183600 |
| Short name | T1344 |
| Test name | |
| Test status | |
| Simulation time | 5662661200 ps |
| CPU time | 562.75 seconds |
| Started | Aug 13 07:20:51 PM PDT 24 |
| Finished | Aug 13 07:30:14 PM PDT 24 |
| Peak memory | 611384 kb |
| Host | smart-9d48e46d-f32a-42b7-9ec3-5447c2854d4e |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=aon_timer_wdog_lc_escalate_test:1:new_rules,test_rom:0 +cdc_ instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed =3358183600 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_aon_timer_wdog_lc_escalate.3358183600 |
| Directory | /workspace/1.chip_sw_aon_timer_wdog_lc_escalate/latest |
| Test location | /workspace/coverage/default/1.chip_sw_ast_clk_outputs.2924976863 |
| Short name | T762 |
| Test name | |
| Test status | |
| Simulation time | 8041623720 ps |
| CPU time | 941.23 seconds |
| Started | Aug 13 07:20:20 PM PDT 24 |
| Finished | Aug 13 07:36:01 PM PDT 24 |
| Peak memory | 617808 kb |
| Host | smart-9850f6e2-b7e7-4b79-ade6-620d59f8828f |
| User | root |
| Command | /workspace/default/simv +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=ast_clk_outs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled= 1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2924976863 -assert nopo stproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_ast_clk_outputs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co verage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_ast_clk_outputs.2924976863 |
| Directory | /workspace/1.chip_sw_ast_clk_outputs/latest |
| Test location | /workspace/coverage/default/1.chip_sw_ast_clk_rst_inputs.1969541645 |
| Short name | T145 |
| Test name | |
| Test status | |
| Simulation time | 25453688715 ps |
| CPU time | 3575.44 seconds |
| Started | Aug 13 07:23:17 PM PDT 24 |
| Finished | Aug 13 08:22:54 PM PDT 24 |
| Peak memory | 611752 kb |
| Host | smart-b76f6d9a-b8e3-43b9-a861-3fd3a047d4a2 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=200_000_000 +sw_build_device=sim_dv +sw_images=ast_clk_rst_inputs:1:new_rules,test_rom:0 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1969541645 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_ast_clk_rst_inputs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_ast_clk_rst_inputs.1969541645 |
| Directory | /workspace/1.chip_sw_ast_clk_rst_inputs/latest |
| Test location | /workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_lc.1608810588 |
| Short name | T1338 |
| Test name | |
| Test status | |
| Simulation time | 12810256288 ps |
| CPU time | 1463.39 seconds |
| Started | Aug 13 07:18:18 PM PDT 24 |
| Finished | Aug 13 07:42:42 PM PDT 24 |
| Peak memory | 622036 kb |
| Host | smart-6f72b588-dbda-4966-b110-f489669977ff |
| User | root |
| Command | /workspace/default/simv +chip_clock_source=ChipClockSourceExternal48Mhz +sw_build_device=sim_dv +sw_images=clkmgr_external_clk_src_for_lc_test:1:new_r ules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim .tcl +ntb_random_seed=1608810588 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_transition_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_clkmgr_external_clk_src_for_lc.1608810588 |
| Directory | /workspace/1.chip_sw_clkmgr_external_clk_src_for_lc/latest |
| Test location | /workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_fast_dev.1240020502 |
| Short name | T1173 |
| Test name | |
| Test status | |
| Simulation time | 3426572132 ps |
| CPU time | 578.19 seconds |
| Started | Aug 13 07:20:06 PM PDT 24 |
| Finished | Aug 13 07:29:44 PM PDT 24 |
| Peak memory | 614868 kb |
| Host | smart-a1ff896c-966c-4f42-abae-c2011cf2e5dd |
| User | root |
| Command | /workspace/default/simv +chip_clock_source=ChipClockSourceExternal96Mhz +calibrate_usb_clk=1 +src_dec_state=DecLcStDev +sw_build_device=sim_dv +sw_ima ges=clkmgr_external_clk_src_for_sw_fast_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1240020502 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ =chip_sw_lc_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_c lkmgr_external_clk_src_for_sw_fast_dev.1240020502 |
| Directory | /workspace/1.chip_sw_clkmgr_external_clk_src_for_sw_fast_dev/latest |
| Test location | /workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_fast_rma.1753085340 |
| Short name | T1114 |
| Test name | |
| Test status | |
| Simulation time | 4629625736 ps |
| CPU time | 730.3 seconds |
| Started | Aug 13 07:22:45 PM PDT 24 |
| Finished | Aug 13 07:34:56 PM PDT 24 |
| Peak memory | 614676 kb |
| Host | smart-21b3f526-69e0-40e4-99fc-8971d733ddd5 |
| User | root |
| Command | /workspace/default/simv +chip_clock_source=ChipClockSourceExternal96Mhz +calibrate_usb_clk=1 +src_dec_state=DecLcStRma +sw_build_device=sim_dv +sw_ima ges=clkmgr_external_clk_src_for_sw_fast_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1753085340 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ =chip_sw_lc_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_c lkmgr_external_clk_src_for_sw_fast_rma.1753085340 |
| Directory | /workspace/1.chip_sw_clkmgr_external_clk_src_for_sw_fast_rma/latest |
| Test location | /workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0.969349058 |
| Short name | T1025 |
| Test name | |
| Test status | |
| Simulation time | 3981752600 ps |
| CPU time | 702.19 seconds |
| Started | Aug 13 07:18:47 PM PDT 24 |
| Finished | Aug 13 07:30:29 PM PDT 24 |
| Peak memory | 614844 kb |
| Host | smart-f707070a-a20c-4918-8a1d-32aad9a2c88c |
| User | root |
| Command | /workspace/default/simv +chip_clock_source=ChipClockSourceExternal96Mhz +calibrate_usb_clk=1 +src_dec_state=DecLcStTestUnlocked0 +sw_build_device=sim_ dv +sw_images=clkmgr_external_clk_src_for_sw_fast_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=969349058 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM _TEST_SEQ=chip_sw_lc_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1. chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0.969349058 |
| Directory | /workspace/1.chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0/latest |
| Test location | /workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_slow_dev.376733611 |
| Short name | T271 |
| Test name | |
| Test status | |
| Simulation time | 5222194074 ps |
| CPU time | 679.03 seconds |
| Started | Aug 13 07:21:36 PM PDT 24 |
| Finished | Aug 13 07:32:56 PM PDT 24 |
| Peak memory | 614640 kb |
| Host | smart-4f4212bb-cb7e-40ae-94bc-214805448566 |
| User | root |
| Command | /workspace/default/simv +chip_clock_source=ChipClockSourceExternal48Mhz +calibrate_usb_clk=1 +src_dec_state=DecLcStDev +sw_build_device=sim_dv +sw_ima ges=clkmgr_external_clk_src_for_sw_slow_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=376733611 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ= chip_sw_lc_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_cl kmgr_external_clk_src_for_sw_slow_dev.376733611 |
| Directory | /workspace/1.chip_sw_clkmgr_external_clk_src_for_sw_slow_dev/latest |
| Test location | /workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_slow_rma.67567194 |
| Short name | T1258 |
| Test name | |
| Test status | |
| Simulation time | 4030502382 ps |
| CPU time | 547.26 seconds |
| Started | Aug 13 07:20:41 PM PDT 24 |
| Finished | Aug 13 07:29:48 PM PDT 24 |
| Peak memory | 614856 kb |
| Host | smart-f0413d02-c8a3-4bf9-a921-e67a6164589c |
| User | root |
| Command | /workspace/default/simv +chip_clock_source=ChipClockSourceExternal48Mhz +calibrate_usb_clk=1 +src_dec_state=DecLcStRma +sw_build_device=sim_dv +sw_ima ges=clkmgr_external_clk_src_for_sw_slow_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=67567194 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=c hip_sw_lc_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_clk mgr_external_clk_src_for_sw_slow_rma.67567194 |
| Directory | /workspace/1.chip_sw_clkmgr_external_clk_src_for_sw_slow_rma/latest |
| Test location | /workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0.3123727500 |
| Short name | T1100 |
| Test name | |
| Test status | |
| Simulation time | 4540856862 ps |
| CPU time | 641.9 seconds |
| Started | Aug 13 07:20:08 PM PDT 24 |
| Finished | Aug 13 07:30:50 PM PDT 24 |
| Peak memory | 614936 kb |
| Host | smart-bad20314-6fc7-4da9-969e-5e1253774d73 |
| User | root |
| Command | /workspace/default/simv +chip_clock_source=ChipClockSourceExternal48Mhz +calibrate_usb_clk=1 +src_dec_state=DecLcStTestUnlocked0 +sw_build_device=sim_ dv +sw_images=clkmgr_external_clk_src_for_sw_slow_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3123727500 -assert nopostproc +UVM_TESTNAME=chip_base_test +UV M_TEST_SEQ=chip_sw_lc_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1 .chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0.3123727500 |
| Directory | /workspace/1.chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0/latest |
| Test location | /workspace/coverage/default/1.chip_sw_clkmgr_jitter.4281658534 |
| Short name | T945 |
| Test name | |
| Test status | |
| Simulation time | 2281573001 ps |
| CPU time | 250.38 seconds |
| Started | Aug 13 07:17:47 PM PDT 24 |
| Finished | Aug 13 07:21:57 PM PDT 24 |
| Peak memory | 610044 kb |
| Host | smart-9f8f230f-0103-4b5e-9142-15d50c7e6345 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=clkmgr_jitter_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4281658534 -assert nopostproc +UVM_TESTNAME =chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 1.chip_sw_clkmgr_jitter.4281658534 |
| Directory | /workspace/1.chip_sw_clkmgr_jitter/latest |
| Test location | /workspace/coverage/default/1.chip_sw_clkmgr_jitter_frequency.2926017525 |
| Short name | T970 |
| Test name | |
| Test status | |
| Simulation time | 3410795516 ps |
| CPU time | 346.94 seconds |
| Started | Aug 13 07:18:44 PM PDT 24 |
| Finished | Aug 13 07:24:31 PM PDT 24 |
| Peak memory | 610392 kb |
| Host | smart-4ae78746-43a8-4490-8019-4018f1ef72cf |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=clkmgr_jitter_frequency_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2926017525 -assert nopostproc +UV M_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -c m_log /dev/null -cm_name 1.chip_sw_clkmgr_jitter_frequency.2926017525 |
| Directory | /workspace/1.chip_sw_clkmgr_jitter_frequency/latest |
| Test location | /workspace/coverage/default/1.chip_sw_clkmgr_jitter_reduced_freq.3551900204 |
| Short name | T442 |
| Test name | |
| Test status | |
| Simulation time | 2821754520 ps |
| CPU time | 240.57 seconds |
| Started | Aug 13 07:20:43 PM PDT 24 |
| Finished | Aug 13 07:24:44 PM PDT 24 |
| Peak memory | 610456 kb |
| Host | smart-2307422c-0499-4623-ab70-44fb102f7f03 |
| User | root |
| Command | /workspace/default/simv +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=clkmgr_jitter_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3551900204 -assert nop ostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def ault.vdb -cm_log /dev/null -cm_name 1.chip_sw_clkmgr_jitter_reduced_freq.3551900204 |
| Directory | /workspace/1.chip_sw_clkmgr_jitter_reduced_freq/latest |
| Test location | /workspace/coverage/default/1.chip_sw_clkmgr_off_aes_trans.4209642114 |
| Short name | T993 |
| Test name | |
| Test status | |
| Simulation time | 4247399340 ps |
| CPU time | 563.98 seconds |
| Started | Aug 13 07:20:11 PM PDT 24 |
| Finished | Aug 13 07:29:35 PM PDT 24 |
| Peak memory | 609840 kb |
| Host | smart-07eedba0-babf-4848-90be-914180c619f2 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=clkmgr_off_aes_trans_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4209642114 -assert nopostproc +UVM_T ESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l og /dev/null -cm_name 1.chip_sw_clkmgr_off_aes_trans.4209642114 |
| Directory | /workspace/1.chip_sw_clkmgr_off_aes_trans/latest |
| Test location | /workspace/coverage/default/1.chip_sw_clkmgr_off_hmac_trans.3979714268 |
| Short name | T1296 |
| Test name | |
| Test status | |
| Simulation time | 4288324250 ps |
| CPU time | 441.89 seconds |
| Started | Aug 13 07:17:35 PM PDT 24 |
| Finished | Aug 13 07:24:57 PM PDT 24 |
| Peak memory | 610960 kb |
| Host | smart-907bc604-2267-469d-b9e6-94ed2f62b617 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=clkmgr_off_hmac_trans_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3979714268 -assert nopostproc +UVM_ TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_ log /dev/null -cm_name 1.chip_sw_clkmgr_off_hmac_trans.3979714268 |
| Directory | /workspace/1.chip_sw_clkmgr_off_hmac_trans/latest |
| Test location | /workspace/coverage/default/1.chip_sw_clkmgr_off_kmac_trans.1204175776 |
| Short name | T1385 |
| Test name | |
| Test status | |
| Simulation time | 4661438556 ps |
| CPU time | 372.48 seconds |
| Started | Aug 13 07:17:32 PM PDT 24 |
| Finished | Aug 13 07:23:45 PM PDT 24 |
| Peak memory | 610352 kb |
| Host | smart-ef51ce74-d81b-4e35-ba9a-08d079b89f5a |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=clkmgr_off_kmac_trans_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1204175776 -assert nopostproc +UVM_ TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_ log /dev/null -cm_name 1.chip_sw_clkmgr_off_kmac_trans.1204175776 |
| Directory | /workspace/1.chip_sw_clkmgr_off_kmac_trans/latest |
| Test location | /workspace/coverage/default/1.chip_sw_clkmgr_off_otbn_trans.945300062 |
| Short name | T1381 |
| Test name | |
| Test status | |
| Simulation time | 5211977680 ps |
| CPU time | 485.94 seconds |
| Started | Aug 13 07:19:58 PM PDT 24 |
| Finished | Aug 13 07:28:04 PM PDT 24 |
| Peak memory | 611184 kb |
| Host | smart-1c30b1cc-88cd-44a6-974f-f89f484ab9f2 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=clkmgr_off_otbn_trans_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=945300062 -assert nopostproc +UVM_T ESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l og /dev/null -cm_name 1.chip_sw_clkmgr_off_otbn_trans.945300062 |
| Directory | /workspace/1.chip_sw_clkmgr_off_otbn_trans/latest |
| Test location | /workspace/coverage/default/1.chip_sw_clkmgr_off_peri.343408047 |
| Short name | T1049 |
| Test name | |
| Test status | |
| Simulation time | 8156460638 ps |
| CPU time | 1263.69 seconds |
| Started | Aug 13 07:18:01 PM PDT 24 |
| Finished | Aug 13 07:39:05 PM PDT 24 |
| Peak memory | 611200 kb |
| Host | smart-6abcabca-1491-4c7d-a90e-a8ac8ff98fb9 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=30_000_000 +sw_build_device=sim_dv +sw_images=clkmgr_off_peri_test:1:new_rules,test_rom:0 +cdc_instrumenta tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=343408047 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/c overage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_clkmgr_off_peri.343408047 |
| Directory | /workspace/1.chip_sw_clkmgr_off_peri/latest |
| Test location | /workspace/coverage/default/1.chip_sw_clkmgr_reset_frequency.3128271032 |
| Short name | T1386 |
| Test name | |
| Test status | |
| Simulation time | 3892543128 ps |
| CPU time | 413.53 seconds |
| Started | Aug 13 07:20:19 PM PDT 24 |
| Finished | Aug 13 07:27:30 PM PDT 24 |
| Peak memory | 610692 kb |
| Host | smart-329abce3-d5cc-44b7-816d-27af4b5bf69f |
| User | root |
| Command | /workspace/default/simv +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=clkmgr_reset_frequency_test:1:new_rules,test_rom:0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3128271032 -a ssert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov erage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_clkmgr_reset_frequency.3128271032 |
| Directory | /workspace/1.chip_sw_clkmgr_reset_frequency/latest |
| Test location | /workspace/coverage/default/1.chip_sw_clkmgr_sleep_frequency.3492273517 |
| Short name | T1001 |
| Test name | |
| Test status | |
| Simulation time | 4231937806 ps |
| CPU time | 618.73 seconds |
| Started | Aug 13 07:19:42 PM PDT 24 |
| Finished | Aug 13 07:30:01 PM PDT 24 |
| Peak memory | 610724 kb |
| Host | smart-9f62cdc5-e959-4ec7-996c-048549dca203 |
| User | root |
| Command | /workspace/default/simv +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=clkmgr_sleep_frequency_test:1:new_rules,test_rom:0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3492273517 -a ssert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov erage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_clkmgr_sleep_frequency.3492273517 |
| Directory | /workspace/1.chip_sw_clkmgr_sleep_frequency/latest |
| Test location | /workspace/coverage/default/1.chip_sw_clkmgr_smoketest.1110382477 |
| Short name | T939 |
| Test name | |
| Test status | |
| Simulation time | 2540023280 ps |
| CPU time | 194.41 seconds |
| Started | Aug 13 07:23:24 PM PDT 24 |
| Finished | Aug 13 07:26:38 PM PDT 24 |
| Peak memory | 610524 kb |
| Host | smart-69f195c8-139b-4395-87ab-608d5748d350 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=clkmgr_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1110382477 -assert nopostproc +UVM_TESTNAME=c hip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n ull -cm_name 1.chip_sw_clkmgr_smoketest.1110382477 |
| Directory | /workspace/1.chip_sw_clkmgr_smoketest/latest |
| Test location | /workspace/coverage/default/1.chip_sw_csrng_edn_concurrency.2806487825 |
| Short name | T979 |
| Test name | |
| Test status | |
| Simulation time | 23506357090 ps |
| CPU time | 5045.22 seconds |
| Started | Aug 13 07:18:01 PM PDT 24 |
| Finished | Aug 13 08:42:08 PM PDT 24 |
| Peak memory | 611056 kb |
| Host | smart-aa4b8de2-d28c-4eb5-bcff-12982b66c2de |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=140_000_000 +rng_srate_value_min=15 +rng_srate_value_max=20 +accelerate_cold_power_up_time=3 +accelerate_r egulators_power_up_time=2 +sw_build_device=sim_dv +sw_images=csrng_edn_concurrency_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2806487825 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd b -cm_log /dev/null -cm_name 1.chip_sw_csrng_edn_concurrency.2806487825 |
| Directory | /workspace/1.chip_sw_csrng_edn_concurrency/latest |
| Test location | /workspace/coverage/default/1.chip_sw_csrng_fuse_en_sw_app_read_test.3634825570 |
| Short name | T195 |
| Test name | |
| Test status | |
| Simulation time | 3420925038 ps |
| CPU time | 399.57 seconds |
| Started | Aug 13 07:18:31 PM PDT 24 |
| Finished | Aug 13 07:25:11 PM PDT 24 |
| Peak memory | 611160 kb |
| Host | smart-afb1d82f-700d-4bde-a283-5f06156c790e |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=15_000_000 +sw_build_device=sim_dv +sw_images=csrng_fuse_en_sw_app_read:1:new_rules,test_rom:0 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36348 25570 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_entropy_src_fuse_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_csrng_fuse_en_sw_app_read_test.3634825570 |
| Directory | /workspace/1.chip_sw_csrng_fuse_en_sw_app_read_test/latest |
| Test location | /workspace/coverage/default/1.chip_sw_csrng_kat_test.2409760293 |
| Short name | T413 |
| Test name | |
| Test status | |
| Simulation time | 2530726820 ps |
| CPU time | 318.09 seconds |
| Started | Aug 13 07:16:57 PM PDT 24 |
| Finished | Aug 13 07:22:15 PM PDT 24 |
| Peak memory | 610168 kb |
| Host | smart-c67dfe9a-42b8-4cae-987c-f06743bcdd7b |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=csrng_kat_test:1:new_rules,test_rom:0 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2409760293 -asse rt nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera ge/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_csrng_kat_test.2409760293 |
| Directory | /workspace/1.chip_sw_csrng_kat_test/latest |
| Test location | /workspace/coverage/default/1.chip_sw_csrng_smoketest.1039063997 |
| Short name | T1088 |
| Test name | |
| Test status | |
| Simulation time | 2898884976 ps |
| CPU time | 290.38 seconds |
| Started | Aug 13 07:21:40 PM PDT 24 |
| Finished | Aug 13 07:26:31 PM PDT 24 |
| Peak memory | 610216 kb |
| Host | smart-7dfaaeba-6061-40ca-a939-4fd840d9e88d |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=csrng_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1039063997 -assert nopostproc +UVM_TESTNAME=ch ip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu ll -cm_name 1.chip_sw_csrng_smoketest.1039063997 |
| Directory | /workspace/1.chip_sw_csrng_smoketest/latest |
| Test location | /workspace/coverage/default/1.chip_sw_data_integrity_escalation.2399223468 |
| Short name | T285 |
| Test name | |
| Test status | |
| Simulation time | 5410756644 ps |
| CPU time | 829.25 seconds |
| Started | Aug 13 07:15:42 PM PDT 24 |
| Finished | Aug 13 07:29:32 PM PDT 24 |
| Peak memory | 611852 kb |
| Host | smart-2c7652e3-61dc-4ce7-a1ac-0ecc87141ec4 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=data_integrity_escalation_reset_test:1:new_rules,test_ro m:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=2399223468 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_data_integrity_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_data_integrity_escalation.2399223468 |
| Directory | /workspace/1.chip_sw_data_integrity_escalation/latest |
| Test location | /workspace/coverage/default/1.chip_sw_edn_auto_mode.2593385757 |
| Short name | T1137 |
| Test name | |
| Test status | |
| Simulation time | 4461246624 ps |
| CPU time | 1169.77 seconds |
| Started | Aug 13 07:17:28 PM PDT 24 |
| Finished | Aug 13 07:36:58 PM PDT 24 |
| Peak memory | 610600 kb |
| Host | smart-454b0609-f808-436f-baa7-dda835a38667 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +rng_srate_value=5 +accelerate_cold_power_up_time=3 +accelerate_regulators_power_up_time=2 +sw_ build_device=sim_dv +sw_images=edn_auto_mode:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2593385757 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ =chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_edn_ auto_mode.2593385757 |
| Directory | /workspace/1.chip_sw_edn_auto_mode/latest |
| Test location | /workspace/coverage/default/1.chip_sw_edn_boot_mode.165731274 |
| Short name | T400 |
| Test name | |
| Test status | |
| Simulation time | 3373053630 ps |
| CPU time | 562.36 seconds |
| Started | Aug 13 07:16:45 PM PDT 24 |
| Finished | Aug 13 07:26:08 PM PDT 24 |
| Peak memory | 610408 kb |
| Host | smart-7f947ed7-8e05-47a7-b5f2-a237540c122e |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +rng_srate_value=5 +accelerate_cold_power_up_time=3 +accelerate_regulators_power_up_time=2 +sw_ build_device=sim_dv +sw_images=edn_boot_mode:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=165731274 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ= chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_edn_b oot_mode.165731274 |
| Directory | /workspace/1.chip_sw_edn_boot_mode/latest |
| Test location | /workspace/coverage/default/1.chip_sw_edn_entropy_reqs.3408701814 |
| Short name | T1318 |
| Test name | |
| Test status | |
| Simulation time | 7787880216 ps |
| CPU time | 1069.18 seconds |
| Started | Aug 13 07:15:48 PM PDT 24 |
| Finished | Aug 13 07:33:37 PM PDT 24 |
| Peak memory | 611352 kb |
| Host | smart-f8f70cf5-142e-415a-92a1-339da783d9e9 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=15000000 +rng_srate_value_min=15 +rng_srate_value_max=30 +sw_build_device=sim_dv +sw_images=entropy_src_ed n_reqs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3408701814 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_edn_entropy_reqs.3408701814 |
| Directory | /workspace/1.chip_sw_edn_entropy_reqs/latest |
| Test location | /workspace/coverage/default/1.chip_sw_edn_kat.3648771842 |
| Short name | T1208 |
| Test name | |
| Test status | |
| Simulation time | 3649621230 ps |
| CPU time | 616.86 seconds |
| Started | Aug 13 07:16:46 PM PDT 24 |
| Finished | Aug 13 07:27:03 PM PDT 24 |
| Peak memory | 615892 kb |
| Host | smart-e273163c-425b-4bae-b64f-25cefb508b5d |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +rng_srate_value=5 +disable_assert_edn_output_diff_from_prev=1 +accelerate_cold_power_up_time=3 +accelerate_regulators_power_up_time=2 +sw_build_device=sim_dv +sw_images=edn_kat:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3648771842 -assert nopostproc +UVM _TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm _log /dev/null -cm_name 1.chip_sw_edn_kat.3648771842 |
| Directory | /workspace/1.chip_sw_edn_kat/latest |
| Test location | /workspace/coverage/default/1.chip_sw_edn_sw_mode.3478683652 |
| Short name | T1139 |
| Test name | |
| Test status | |
| Simulation time | 6397040240 ps |
| CPU time | 1349.87 seconds |
| Started | Aug 13 07:18:38 PM PDT 24 |
| Finished | Aug 13 07:41:08 PM PDT 24 |
| Peak memory | 610300 kb |
| Host | smart-d9192c4b-4561-449e-975f-2ae81c8d7ada |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=edn_sw_mode:1:new_rules,test_rom:0 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3478683652 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/ default.vdb -cm_log /dev/null -cm_name 1.chip_sw_edn_sw_mode.3478683652 |
| Directory | /workspace/1.chip_sw_edn_sw_mode/latest |
| Test location | /workspace/coverage/default/1.chip_sw_entropy_src_ast_rng_req.1720134117 |
| Short name | T965 |
| Test name | |
| Test status | |
| Simulation time | 3366102090 ps |
| CPU time | 289.37 seconds |
| Started | Aug 13 07:16:55 PM PDT 24 |
| Finished | Aug 13 07:21:44 PM PDT 24 |
| Peak memory | 610176 kb |
| Host | smart-296819be-3cd9-4795-89e1-c7397a551317 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=15_000_000 +sw_build_device=sim_dv +sw_images=entropy_src_ast_rng_req_test:1:new_rules,test_rom:0 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17 20134117 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_entropy_src_ast_rng_req.1720134117 |
| Directory | /workspace/1.chip_sw_entropy_src_ast_rng_req/latest |
| Test location | /workspace/coverage/default/1.chip_sw_entropy_src_csrng.4209304873 |
| Short name | T125 |
| Test name | |
| Test status | |
| Simulation time | 6599710056 ps |
| CPU time | 1541.63 seconds |
| Started | Aug 13 07:18:29 PM PDT 24 |
| Finished | Aug 13 07:44:11 PM PDT 24 |
| Peak memory | 610960 kb |
| Host | smart-49c65615-3cd1-40b1-8f86-6cad5e81da22 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=50_000_000 +rng_srate_value_min=15 +rng_srate_value_max=30 +sw_build_device=sim_dv +sw_images=entropy_src_ csrng_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=4209304873 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_entropy_src_csrng.4209304873 |
| Directory | /workspace/1.chip_sw_entropy_src_csrng/latest |
| Test location | /workspace/coverage/default/1.chip_sw_entropy_src_kat_test.49615086 |
| Short name | T1152 |
| Test name | |
| Test status | |
| Simulation time | 3183915150 ps |
| CPU time | 195.16 seconds |
| Started | Aug 13 07:19:02 PM PDT 24 |
| Finished | Aug 13 07:22:18 PM PDT 24 |
| Peak memory | 609092 kb |
| Host | smart-7cdb4226-5cb7-417e-9c3b-9e0b849f1d26 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=entropy_src_kat_test:1:new_rules,test_rom:0 +cdc_instrumenta tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49615086 - assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co verage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_entropy_src_kat_test.49615086 |
| Directory | /workspace/1.chip_sw_entropy_src_kat_test/latest |
| Test location | /workspace/coverage/default/1.chip_sw_entropy_src_smoketest.1443698457 |
| Short name | T969 |
| Test name | |
| Test status | |
| Simulation time | 3764562184 ps |
| CPU time | 555.12 seconds |
| Started | Aug 13 07:21:39 PM PDT 24 |
| Finished | Aug 13 07:30:54 PM PDT 24 |
| Peak memory | 609904 kb |
| Host | smart-a16e647a-f198-47ae-a842-2a515bce0a0a |
| User | root |
| Command | /workspace/default/simv +rng_srate_value_min=15 +rng_srate_value_max=30 +sw_build_device=sim_dv +sw_images=entropy_src_smoketest:1:new_rules,test_rom: 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand om_seed=1443698457 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_entropy_src_smoketest.1443698457 |
| Directory | /workspace/1.chip_sw_entropy_src_smoketest/latest |
| Test location | /workspace/coverage/default/1.chip_sw_example_concurrency.3356352425 |
| Short name | T1285 |
| Test name | |
| Test status | |
| Simulation time | 3174099198 ps |
| CPU time | 270.07 seconds |
| Started | Aug 13 07:15:36 PM PDT 24 |
| Finished | Aug 13 07:20:06 PM PDT 24 |
| Peak memory | 610444 kb |
| Host | smart-877f870b-9276-4729-8e37-2b0134c4dc21 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=example_concurrency_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3356352425 -assert nopostproc +UVM_TE STNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_lo g /dev/null -cm_name 1.chip_sw_example_concurrency.3356352425 |
| Directory | /workspace/1.chip_sw_example_concurrency/latest |
| Test location | /workspace/coverage/default/1.chip_sw_example_flash.1501143058 |
| Short name | T451 |
| Test name | |
| Test status | |
| Simulation time | 2864784184 ps |
| CPU time | 300.1 seconds |
| Started | Aug 13 07:15:53 PM PDT 24 |
| Finished | Aug 13 07:20:53 PM PDT 24 |
| Peak memory | 610320 kb |
| Host | smart-91ca72f8-f01c-487f-9692-f41555a1fabc |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=example_test_from_flash:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1501143058 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_example_flash.1501143058 |
| Directory | /workspace/1.chip_sw_example_flash/latest |
| Test location | /workspace/coverage/default/1.chip_sw_example_manufacturer.3118204151 |
| Short name | T1311 |
| Test name | |
| Test status | |
| Simulation time | 2707374860 ps |
| CPU time | 213.31 seconds |
| Started | Aug 13 07:15:59 PM PDT 24 |
| Finished | Aug 13 07:19:33 PM PDT 24 |
| Peak memory | 610336 kb |
| Host | smart-3c91d193-eb84-403c-9204-98d20eb480e4 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=example_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3118204151 -assert nopostproc +UVM_TESTNAME=chip_ base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_example_manufacturer.3118204151 |
| Directory | /workspace/1.chip_sw_example_manufacturer/latest |
| Test location | /workspace/coverage/default/1.chip_sw_example_rom.785380963 |
| Short name | T947 |
| Test name | |
| Test status | |
| Simulation time | 2899259960 ps |
| CPU time | 121.56 seconds |
| Started | Aug 13 07:13:48 PM PDT 24 |
| Finished | Aug 13 07:15:50 PM PDT 24 |
| Peak memory | 609516 kb |
| Host | smart-1b4cb458-67b4-4f96-ad34-a8df0c21f628 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=example_test_from_rom:0:test_in_rom:new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=785380963 -assert nopostproc +UVM_TESTN AME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log / dev/null -cm_name 1.chip_sw_example_rom.785380963 |
| Directory | /workspace/1.chip_sw_example_rom/latest |
| Test location | /workspace/coverage/default/1.chip_sw_exit_test_unlocked_bootstrap.1844259570 |
| Short name | T1310 |
| Test name | |
| Test status | |
| Simulation time | 58667525400 ps |
| CPU time | 10251.3 seconds |
| Started | Aug 13 07:13:24 PM PDT 24 |
| Finished | Aug 13 10:04:17 PM PDT 24 |
| Peak memory | 625240 kb |
| Host | smart-25e87965-b3b7-478f-9adf-2fdd8c933628 |
| User | root |
| Command | /workspace/default/simv +flash_program_latency=5 +sw_test_timeout_ns=150_000_000 +sw_build_device=sim_dv +sw_images=exit_test_unlocked_bootstrap:1:new _rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/s im.tcl +ntb_random_seed=1844259570 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_exit_test_unlocked_bootstrap_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_exit_test_unlocked_bootstrap.1844259570 |
| Directory | /workspace/1.chip_sw_exit_test_unlocked_bootstrap/latest |
| Test location | /workspace/coverage/default/1.chip_sw_flash_crash_alert.3321504512 |
| Short name | T1098 |
| Test name | |
| Test status | |
| Simulation time | 6323239752 ps |
| CPU time | 797.08 seconds |
| Started | Aug 13 07:19:13 PM PDT 24 |
| Finished | Aug 13 07:32:30 PM PDT 24 |
| Peak memory | 611996 kb |
| Host | smart-7f86fee0-6515-415c-bdc1-021c7293bcf4 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=8_000_000 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1: new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tool s/sim.tcl +ntb_random_seed=3321504512 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_flash_host_gnt_err_inj_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_flash_crash_alert.3321504512 |
| Directory | /workspace/1.chip_sw_flash_crash_alert/latest |
| Test location | /workspace/coverage/default/1.chip_sw_flash_ctrl_access.3939358003 |
| Short name | T985 |
| Test name | |
| Test status | |
| Simulation time | 5100863010 ps |
| CPU time | 934.06 seconds |
| Started | Aug 13 07:16:13 PM PDT 24 |
| Finished | Aug 13 07:31:47 PM PDT 24 |
| Peak memory | 610372 kb |
| Host | smart-5750bc74-9ec8-48fd-a107-6afc4ddeaa78 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=flash_ctrl_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3939358003 -assert nopostproc +UVM_TESTNAME=ch ip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu ll -cm_name 1.chip_sw_flash_ctrl_access.3939358003 |
| Directory | /workspace/1.chip_sw_flash_ctrl_access/latest |
| Test location | /workspace/coverage/default/1.chip_sw_flash_ctrl_access_jitter_en.1440246831 |
| Short name | T382 |
| Test name | |
| Test status | |
| Simulation time | 5903342739 ps |
| CPU time | 1081.39 seconds |
| Started | Aug 13 07:14:46 PM PDT 24 |
| Finished | Aug 13 07:32:47 PM PDT 24 |
| Peak memory | 610520 kb |
| Host | smart-c49fdd54-64e1-4150-a743-ebe67e579ade |
| User | root |
| Command | /workspace/default/simv +en_jitter=1 +sw_build_device=sim_dv +sw_images=flash_ctrl_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1440246831 -assert nopostproc +UV M_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -c m_log /dev/null -cm_name 1.chip_sw_flash_ctrl_access_jitter_en.1440246831 |
| Directory | /workspace/1.chip_sw_flash_ctrl_access_jitter_en/latest |
| Test location | /workspace/coverage/default/1.chip_sw_flash_ctrl_access_jitter_en_reduced_freq.3894693932 |
| Short name | T978 |
| Test name | |
| Test status | |
| Simulation time | 7110325433 ps |
| CPU time | 1039.52 seconds |
| Started | Aug 13 07:22:19 PM PDT 24 |
| Finished | Aug 13 07:39:39 PM PDT 24 |
| Peak memory | 610820 kb |
| Host | smart-1925c632-57af-470b-a0d2-b182b43d67b5 |
| User | root |
| Command | /workspace/default/simv +en_jitter=1 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=flash_ctrl_test:1:new_rules,test_rom:0 +cdc_instrumentati on_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3894693932 - assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co verage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_flash_ctrl_access_jitter_en_reduced_freq.3894693932 |
| Directory | /workspace/1.chip_sw_flash_ctrl_access_jitter_en_reduced_freq/latest |
| Test location | /workspace/coverage/default/1.chip_sw_flash_ctrl_clock_freqs.2093406821 |
| Short name | T1162 |
| Test name | |
| Test status | |
| Simulation time | 6216350780 ps |
| CPU time | 1061.01 seconds |
| Started | Aug 13 07:15:15 PM PDT 24 |
| Finished | Aug 13 07:32:57 PM PDT 24 |
| Peak memory | 610768 kb |
| Host | smart-eb8bb78f-144e-40c9-9240-b59c4afd5117 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=flash_ctrl_clock_freqs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2093406821 -assert nopostproc +UVM _TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm _log /dev/null -cm_name 1.chip_sw_flash_ctrl_clock_freqs.2093406821 |
| Directory | /workspace/1.chip_sw_flash_ctrl_clock_freqs/latest |
| Test location | /workspace/coverage/default/1.chip_sw_flash_ctrl_idle_low_power.1302243348 |
| Short name | T1215 |
| Test name | |
| Test status | |
| Simulation time | 3923410608 ps |
| CPU time | 319.31 seconds |
| Started | Aug 13 07:14:44 PM PDT 24 |
| Finished | Aug 13 07:20:03 PM PDT 24 |
| Peak memory | 610652 kb |
| Host | smart-149e0ef7-f74d-4794-9167-c3e43fa9b695 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=flash_ctrl_idle_low_power_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1302243348 -assert nopostproc + UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_flash_ctrl_idle_low_power.1302243348 |
| Directory | /workspace/1.chip_sw_flash_ctrl_idle_low_power/latest |
| Test location | /workspace/coverage/default/1.chip_sw_flash_ctrl_lc_rw_en.836806352 |
| Short name | T1379 |
| Test name | |
| Test status | |
| Simulation time | 4164635635 ps |
| CPU time | 451.3 seconds |
| Started | Aug 13 07:15:40 PM PDT 24 |
| Finished | Aug 13 07:23:11 PM PDT 24 |
| Peak memory | 610000 kb |
| Host | smart-fd3388a8-8aef-4956-afe6-d8c41c026f46 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=flash_ctrl_lc_rw_en_test:1:new_rules,test_rom:0 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=83 6806352 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_flash_ctrl_lc_rw_en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_flash_ctrl_lc_rw_en.836806352 |
| Directory | /workspace/1.chip_sw_flash_ctrl_lc_rw_en/latest |
| Test location | /workspace/coverage/default/1.chip_sw_flash_ctrl_mem_protection.4125469994 |
| Short name | T1343 |
| Test name | |
| Test status | |
| Simulation time | 5368384260 ps |
| CPU time | 1481.17 seconds |
| Started | Aug 13 07:22:06 PM PDT 24 |
| Finished | Aug 13 07:46:47 PM PDT 24 |
| Peak memory | 610728 kb |
| Host | smart-08062143-d0ac-462a-a719-a3803eb8f157 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=flash_ctrl_mem_protection_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4125469994 -assert nopostproc + UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_flash_ctrl_mem_protection.4125469994 |
| Directory | /workspace/1.chip_sw_flash_ctrl_mem_protection/latest |
| Test location | /workspace/coverage/default/1.chip_sw_flash_ctrl_ops.824866489 |
| Short name | T348 |
| Test name | |
| Test status | |
| Simulation time | 4696821984 ps |
| CPU time | 689.9 seconds |
| Started | Aug 13 07:13:50 PM PDT 24 |
| Finished | Aug 13 07:25:20 PM PDT 24 |
| Peak memory | 610908 kb |
| Host | smart-ade9936b-862a-4e01-a601-e09193c51467 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=50_000_000 +sw_build_device=sim_dv +sw_images=flash_ctrl_ops_test:1:new_rules,test_rom:0 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=824866489 - assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co verage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_flash_ctrl_ops.824866489 |
| Directory | /workspace/1.chip_sw_flash_ctrl_ops/latest |
| Test location | /workspace/coverage/default/1.chip_sw_flash_ctrl_ops_jitter_en.1797879117 |
| Short name | T353 |
| Test name | |
| Test status | |
| Simulation time | 3932449843 ps |
| CPU time | 580.3 seconds |
| Started | Aug 13 07:13:39 PM PDT 24 |
| Finished | Aug 13 07:23:20 PM PDT 24 |
| Peak memory | 610656 kb |
| Host | smart-d194e5f9-2272-481e-b1c8-b5297f41707b |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=50_000_000 +en_jitter=1 +sw_build_device=sim_dv +sw_images=flash_ctrl_ops_test:1:new_rules,test_rom:0 +cdc _instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see d=1797879117 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_flash_ctrl_ops_jitter_en.1797879117 |
| Directory | /workspace/1.chip_sw_flash_ctrl_ops_jitter_en/latest |
| Test location | /workspace/coverage/default/1.chip_sw_flash_ctrl_write_clear.1182004578 |
| Short name | T941 |
| Test name | |
| Test status | |
| Simulation time | 2992179596 ps |
| CPU time | 327.46 seconds |
| Started | Aug 13 07:20:43 PM PDT 24 |
| Finished | Aug 13 07:26:10 PM PDT 24 |
| Peak memory | 610516 kb |
| Host | smart-135e4bbd-d87d-4220-adc2-69ed14918791 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=8_000_000 +sw_build_device=sim_dv +sw_images=flash_ctrl_write_clear_test:1:new_rules,test_rom:0 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1182004 578 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ce/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_flash_ctrl_write_clear.1182004578 |
| Directory | /workspace/1.chip_sw_flash_ctrl_write_clear/latest |
| Test location | /workspace/coverage/default/1.chip_sw_flash_init.2658630809 |
| Short name | T176 |
| Test name | |
| Test status | |
| Simulation time | 19079128073 ps |
| CPU time | 2146.03 seconds |
| Started | Aug 13 07:13:56 PM PDT 24 |
| Finished | Aug 13 07:49:43 PM PDT 24 |
| Peak memory | 613072 kb |
| Host | smart-c4a3adc1-ec05-4955-bf1c-347d8acb38d7 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=25_000_000 +sw_build_device=sim_dv +sw_images=flash_init_test:0:test_in_rom:new_rules +cdc_instrumentation _enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2658630809 -as sert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_flash_init_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac e/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_flash_init.2658630809 |
| Directory | /workspace/1.chip_sw_flash_init/latest |
| Test location | /workspace/coverage/default/1.chip_sw_flash_init_reduced_freq.133400813 |
| Short name | T245 |
| Test name | |
| Test status | |
| Simulation time | 23071568731 ps |
| CPU time | 1912.28 seconds |
| Started | Aug 13 07:20:16 PM PDT 24 |
| Finished | Aug 13 07:52:09 PM PDT 24 |
| Peak memory | 615412 kb |
| Host | smart-aa550cfe-91b5-40a8-8c3e-1ad528414318 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=25_000_000 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=flash_init_test:0:test_in_rom:new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=133400813 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_flash_init_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_flash_init_reduced_freq.133400813 |
| Directory | /workspace/1.chip_sw_flash_init_reduced_freq/latest |
| Test location | /workspace/coverage/default/1.chip_sw_flash_scrambling_smoketest.1384690328 |
| Short name | T1146 |
| Test name | |
| Test status | |
| Simulation time | 3190417398 ps |
| CPU time | 217.94 seconds |
| Started | Aug 13 07:25:13 PM PDT 24 |
| Finished | Aug 13 07:28:51 PM PDT 24 |
| Peak memory | 609904 kb |
| Host | smart-749b33bb-4f3b-4c78-8d31-646f11ae2a7c |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=flash_scrambling_smoketest:1:new_rules,flash_scrambling_smoket est_otp_img_rma:4,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=1384690328 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_flash_scrambling_smoketest.1384690328 |
| Directory | /workspace/1.chip_sw_flash_scrambling_smoketest/latest |
| Test location | /workspace/coverage/default/1.chip_sw_gpio_smoketest.3239528946 |
| Short name | T1119 |
| Test name | |
| Test status | |
| Simulation time | 3401409497 ps |
| CPU time | 274.37 seconds |
| Started | Aug 13 07:22:35 PM PDT 24 |
| Finished | Aug 13 07:27:10 PM PDT 24 |
| Peak memory | 612408 kb |
| Host | smart-3ef36f9a-307c-44c5-93b7-08162f1cb90e |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=gpio_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3239528946 -assert nopostproc +UVM_TESTNAME=chi p_base_test +UVM_TEST_SEQ=chip_sw_gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 1.chip_sw_gpio_smoketest.3239528946 |
| Directory | /workspace/1.chip_sw_gpio_smoketest/latest |
| Test location | /workspace/coverage/default/1.chip_sw_hmac_enc.2273169699 |
| Short name | T1121 |
| Test name | |
| Test status | |
| Simulation time | 3191418200 ps |
| CPU time | 305.54 seconds |
| Started | Aug 13 07:15:40 PM PDT 24 |
| Finished | Aug 13 07:20:46 PM PDT 24 |
| Peak memory | 609824 kb |
| Host | smart-db7ef368-e39b-43cf-aa50-3b6bf65dc381 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=hmac_enc_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2273169699 -assert nopostproc +UVM_TESTNAME=chip _base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_hmac_enc.2273169699 |
| Directory | /workspace/1.chip_sw_hmac_enc/latest |
| Test location | /workspace/coverage/default/1.chip_sw_hmac_enc_idle.1380637916 |
| Short name | T971 |
| Test name | |
| Test status | |
| Simulation time | 2632117750 ps |
| CPU time | 281.63 seconds |
| Started | Aug 13 07:17:48 PM PDT 24 |
| Finished | Aug 13 07:22:30 PM PDT 24 |
| Peak memory | 610224 kb |
| Host | smart-3865a580-180c-4ac3-a8f1-c523237fb5f4 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=hmac_enc_idle_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1380637916 -assert nopostproc +UVM_TESTNAME =chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 1.chip_sw_hmac_enc_idle.1380637916 |
| Directory | /workspace/1.chip_sw_hmac_enc_idle/latest |
| Test location | /workspace/coverage/default/1.chip_sw_hmac_enc_jitter_en.1386747240 |
| Short name | T329 |
| Test name | |
| Test status | |
| Simulation time | 3840756356 ps |
| CPU time | 358.56 seconds |
| Started | Aug 13 07:17:22 PM PDT 24 |
| Finished | Aug 13 07:23:21 PM PDT 24 |
| Peak memory | 610368 kb |
| Host | smart-7afc645b-c28e-495e-82ed-87549fb3f8da |
| User | root |
| Command | /workspace/default/simv +en_jitter=1 +sw_build_device=sim_dv +sw_images=hmac_enc_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1386747240 -assert nopostproc +UVM_ TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_ log /dev/null -cm_name 1.chip_sw_hmac_enc_jitter_en.1386747240 |
| Directory | /workspace/1.chip_sw_hmac_enc_jitter_en/latest |
| Test location | /workspace/coverage/default/1.chip_sw_hmac_enc_jitter_en_reduced_freq.3463718575 |
| Short name | T1293 |
| Test name | |
| Test status | |
| Simulation time | 2379552755 ps |
| CPU time | 261.48 seconds |
| Started | Aug 13 07:21:39 PM PDT 24 |
| Finished | Aug 13 07:26:00 PM PDT 24 |
| Peak memory | 610512 kb |
| Host | smart-7d905a02-53f5-411f-8815-cdff590cf641 |
| User | root |
| Command | /workspace/default/simv +en_jitter=1 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=hmac_enc_test:1:new_rules,test_rom:0 +cdc_instrumentation _enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3463718575 -as sert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove rage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_hmac_enc_jitter_en_reduced_freq.3463718575 |
| Directory | /workspace/1.chip_sw_hmac_enc_jitter_en_reduced_freq/latest |
| Test location | /workspace/coverage/default/1.chip_sw_hmac_multistream.2942278301 |
| Short name | T1013 |
| Test name | |
| Test status | |
| Simulation time | 6987738912 ps |
| CPU time | 1716.58 seconds |
| Started | Aug 13 07:17:32 PM PDT 24 |
| Finished | Aug 13 07:46:09 PM PDT 24 |
| Peak memory | 610792 kb |
| Host | smart-741f5de5-a1ee-4de7-bd54-d4770fdd582a |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=hmac_multistream_functest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2942278301 -assert nopostproc +UVM_T ESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l og /dev/null -cm_name 1.chip_sw_hmac_multistream.2942278301 |
| Directory | /workspace/1.chip_sw_hmac_multistream/latest |
| Test location | /workspace/coverage/default/1.chip_sw_hmac_oneshot.2045944487 |
| Short name | T964 |
| Test name | |
| Test status | |
| Simulation time | 2607284340 ps |
| CPU time | 344.79 seconds |
| Started | Aug 13 07:17:24 PM PDT 24 |
| Finished | Aug 13 07:23:09 PM PDT 24 |
| Peak memory | 610544 kb |
| Host | smart-ed16a6a5-d0bd-4a3e-942c-807a00ac793c |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=hmac_functest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2045944487 -assert nopostproc +UVM_TESTNAME=chip _base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_hmac_oneshot.2045944487 |
| Directory | /workspace/1.chip_sw_hmac_oneshot/latest |
| Test location | /workspace/coverage/default/1.chip_sw_hmac_smoketest.1399380720 |
| Short name | T954 |
| Test name | |
| Test status | |
| Simulation time | 3592314992 ps |
| CPU time | 423.95 seconds |
| Started | Aug 13 07:22:21 PM PDT 24 |
| Finished | Aug 13 07:29:25 PM PDT 24 |
| Peak memory | 610156 kb |
| Host | smart-170692be-f48b-4fd7-a357-4ffb01b3beed |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=hmac_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1399380720 -assert nopostproc +UVM_TESTNAME=chi p_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul l -cm_name 1.chip_sw_hmac_smoketest.1399380720 |
| Directory | /workspace/1.chip_sw_hmac_smoketest/latest |
| Test location | /workspace/coverage/default/1.chip_sw_i2c_device_tx_rx.2819376467 |
| Short name | T343 |
| Test name | |
| Test status | |
| Simulation time | 4426928712 ps |
| CPU time | 715.22 seconds |
| Started | Aug 13 07:13:28 PM PDT 24 |
| Finished | Aug 13 07:25:24 PM PDT 24 |
| Peak memory | 611308 kb |
| Host | smart-d6c46d95-23b4-4b59-9234-9ef04787ac45 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=i2c_device_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2819376467 -assert nopostproc +UVM_TESTN AME=chip_base_test +UVM_TEST_SEQ=chip_sw_i2c_device_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v db -cm_log /dev/null -cm_name 1.chip_sw_i2c_device_tx_rx.2819376467 |
| Directory | /workspace/1.chip_sw_i2c_device_tx_rx/latest |
| Test location | /workspace/coverage/default/1.chip_sw_i2c_host_tx_rx.2406155346 |
| Short name | T225 |
| Test name | |
| Test status | |
| Simulation time | 6098610000 ps |
| CPU time | 956.74 seconds |
| Started | Aug 13 07:15:51 PM PDT 24 |
| Finished | Aug 13 07:31:48 PM PDT 24 |
| Peak memory | 610732 kb |
| Host | smart-f8fad4ac-8d86-4c31-8035-13db4b1d0474 |
| User | root |
| Command | /workspace/default/simv +i2c_idx=0 +sw_build_device=sim_dv +sw_images=i2c_host_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2406155346 -assert nopostproc + UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_i2c_host_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de fault.vdb -cm_log /dev/null -cm_name 1.chip_sw_i2c_host_tx_rx.2406155346 |
| Directory | /workspace/1.chip_sw_i2c_host_tx_rx/latest |
| Test location | /workspace/coverage/default/1.chip_sw_i2c_host_tx_rx_idx1.1334276865 |
| Short name | T338 |
| Test name | |
| Test status | |
| Simulation time | 4605758278 ps |
| CPU time | 729.26 seconds |
| Started | Aug 13 07:15:40 PM PDT 24 |
| Finished | Aug 13 07:27:50 PM PDT 24 |
| Peak memory | 610992 kb |
| Host | smart-b9a1268f-e100-4abb-9adf-fa33f9214794 |
| User | root |
| Command | /workspace/default/simv +i2c_idx=1 +sw_build_device=sim_dv +sw_images=i2c_host_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1334276865 -assert nopostproc + UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_i2c_host_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de fault.vdb -cm_log /dev/null -cm_name 1.chip_sw_i2c_host_tx_rx_idx1.1334276865 |
| Directory | /workspace/1.chip_sw_i2c_host_tx_rx_idx1/latest |
| Test location | /workspace/coverage/default/1.chip_sw_i2c_host_tx_rx_idx2.1099067914 |
| Short name | T104 |
| Test name | |
| Test status | |
| Simulation time | 5094430144 ps |
| CPU time | 1033.73 seconds |
| Started | Aug 13 07:14:20 PM PDT 24 |
| Finished | Aug 13 07:31:34 PM PDT 24 |
| Peak memory | 611008 kb |
| Host | smart-d3705f00-7a93-4630-8e84-7c240c9e583d |
| User | root |
| Command | /workspace/default/simv +i2c_idx=2 +sw_build_device=sim_dv +sw_images=i2c_host_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1099067914 -assert nopostproc + UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_i2c_host_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de fault.vdb -cm_log /dev/null -cm_name 1.chip_sw_i2c_host_tx_rx_idx2.1099067914 |
| Directory | /workspace/1.chip_sw_i2c_host_tx_rx_idx2/latest |
| Test location | /workspace/coverage/default/1.chip_sw_inject_scramble_seed.1910346670 |
| Short name | T214 |
| Test name | |
| Test status | |
| Simulation time | 63451903842 ps |
| CPU time | 10705.7 seconds |
| Started | Aug 13 07:12:54 PM PDT 24 |
| Finished | Aug 13 10:11:21 PM PDT 24 |
| Peak memory | 625248 kb |
| Host | smart-e9bbd597-22cf-454e-8cc6-a10629e8ba3d |
| User | root |
| Command | /workspace/default/simv +lc_at_prod=1 +flash_program_latency=5 +sw_test_timeout_ns=150_000_000 +sw_build_device=sim_dv +sw_images=inject_scramble_seed :1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=1910346670 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_inject_scramble_seed_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_inject_scramble_seed.1910346670 |
| Directory | /workspace/1.chip_sw_inject_scramble_seed/latest |
| Test location | /workspace/coverage/default/1.chip_sw_keymgr_key_derivation.1556310472 |
| Short name | T1083 |
| Test name | |
| Test status | |
| Simulation time | 6054622390 ps |
| CPU time | 1023.48 seconds |
| Started | Aug 13 07:16:01 PM PDT 24 |
| Finished | Aug 13 07:33:05 PM PDT 24 |
| Peak memory | 618500 kb |
| Host | smart-b90d2217-62dc-40d6-a0af-52de8978240c |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=20_000_000 +sw_build_device=sim_dv +sw_images=keymgr_key_derivation_test:1:new_rules,test_rom:0 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1556 310472 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_keymgr_key_derivation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_keymgr_key_derivation.1556310472 |
| Directory | /workspace/1.chip_sw_keymgr_key_derivation/latest |
| Test location | /workspace/coverage/default/1.chip_sw_keymgr_key_derivation_jitter_en.2006109293 |
| Short name | T1399 |
| Test name | |
| Test status | |
| Simulation time | 7552858588 ps |
| CPU time | 1428.15 seconds |
| Started | Aug 13 07:18:20 PM PDT 24 |
| Finished | Aug 13 07:42:09 PM PDT 24 |
| Peak memory | 618452 kb |
| Host | smart-2c2d9f8f-78bb-41e9-83ab-b9cc52484c74 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=20_000_000 +en_jitter=1 +sw_build_device=sim_dv +sw_images=keymgr_key_derivation_test:1:new_rules,test_rom :0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=2006109293 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_keymgr_key_derivation_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_keymgr_key_derivation_jitter_en.2006109293 |
| Directory | /workspace/1.chip_sw_keymgr_key_derivation_jitter_en/latest |
| Test location | /workspace/coverage/default/1.chip_sw_keymgr_key_derivation_jitter_en_reduced_freq.3103606985 |
| Short name | T1191 |
| Test name | |
| Test status | |
| Simulation time | 11388813769 ps |
| CPU time | 2188.26 seconds |
| Started | Aug 13 07:20:16 PM PDT 24 |
| Finished | Aug 13 07:56:45 PM PDT 24 |
| Peak memory | 618560 kb |
| Host | smart-085828e6-9254-46ef-b714-a2959b0bd6de |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=20_000_000 +en_jitter=1 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=keymgr_key_derivation_test :1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=3103606985 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_keymgr_key_derivation_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_keymgr_key_derivation_jitter_en _reduced_freq.3103606985 |
| Directory | /workspace/1.chip_sw_keymgr_key_derivation_jitter_en_reduced_freq/latest |
| Test location | /workspace/coverage/default/1.chip_sw_keymgr_key_derivation_prod.3714660559 |
| Short name | T1185 |
| Test name | |
| Test status | |
| Simulation time | 10531700580 ps |
| CPU time | 1684.52 seconds |
| Started | Aug 13 07:18:13 PM PDT 24 |
| Finished | Aug 13 07:46:18 PM PDT 24 |
| Peak memory | 618456 kb |
| Host | smart-e26daacf-49e6-4bc2-af58-53b2b77dfb33 |
| User | root |
| Command | /workspace/default/simv +lc_at_prod=1 +sw_test_timeout_ns=20_000_000 +sw_build_device=sim_dv +sw_images=keymgr_key_derivation_test:1:new_rules,test_ro m:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=3714660559 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_keymgr_key_derivation_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_keymgr_key_derivation_prod.3714660559 |
| Directory | /workspace/1.chip_sw_keymgr_key_derivation_prod/latest |
| Test location | /workspace/coverage/default/1.chip_sw_keymgr_sideload_aes.3055181216 |
| Short name | T235 |
| Test name | |
| Test status | |
| Simulation time | 6216848536 ps |
| CPU time | 1118.22 seconds |
| Started | Aug 13 07:17:33 PM PDT 24 |
| Finished | Aug 13 07:36:12 PM PDT 24 |
| Peak memory | 612028 kb |
| Host | smart-26eb7d28-dbc7-4469-a275-a0f2507f4856 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=20_000_000 +sw_build_device=sim_dv +sw_images=keymgr_sideload_aes_test:1:new_rules,test_rom:0 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=305518 1216 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_keymgr_sideload_aes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_keymgr_sideload_aes.3055181216 |
| Directory | /workspace/1.chip_sw_keymgr_sideload_aes/latest |
| Test location | /workspace/coverage/default/1.chip_sw_keymgr_sideload_kmac.2609754926 |
| Short name | T1392 |
| Test name | |
| Test status | |
| Simulation time | 9431274120 ps |
| CPU time | 2053.09 seconds |
| Started | Aug 13 07:19:20 PM PDT 24 |
| Finished | Aug 13 07:53:33 PM PDT 24 |
| Peak memory | 610484 kb |
| Host | smart-6a0d7a02-4b4f-4edc-89e5-729b6824d0c0 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=20_000_000 +sw_build_device=sim_dv +sw_images=keymgr_sideload_kmac_test:1:new_rules,test_rom:0 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26097 54926 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_keymgr_sideload_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_keymgr_sideload_kmac.2609754926 |
| Directory | /workspace/1.chip_sw_keymgr_sideload_kmac/latest |
| Test location | /workspace/coverage/default/1.chip_sw_keymgr_sideload_otbn.1891960667 |
| Short name | T92 |
| Test name | |
| Test status | |
| Simulation time | 11332183020 ps |
| CPU time | 2432.21 seconds |
| Started | Aug 13 07:19:27 PM PDT 24 |
| Finished | Aug 13 08:00:00 PM PDT 24 |
| Peak memory | 611592 kb |
| Host | smart-0971deb6-f637-42eb-b9a6-c43bfc5bc5ac |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=20_000_000 +sw_build_device=sim_dv +sw_images=keymgr_sideload_otbn_test:1:new_rules,test_rom:0 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18919 60667 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_keymgr_sideload_otbn.1891960667 |
| Directory | /workspace/1.chip_sw_keymgr_sideload_otbn/latest |
| Test location | /workspace/coverage/default/1.chip_sw_kmac_app_rom.2624332644 |
| Short name | T422 |
| Test name | |
| Test status | |
| Simulation time | 2060648920 ps |
| CPU time | 162.88 seconds |
| Started | Aug 13 07:17:49 PM PDT 24 |
| Finished | Aug 13 07:20:32 PM PDT 24 |
| Peak memory | 610400 kb |
| Host | smart-dfa8c6b0-6944-41ed-9ce1-31e0a2144d85 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=kmac_app_rom_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2624332644 -assert nopostproc +UVM_TESTNAME= chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/ null -cm_name 1.chip_sw_kmac_app_rom.2624332644 |
| Directory | /workspace/1.chip_sw_kmac_app_rom/latest |
| Test location | /workspace/coverage/default/1.chip_sw_kmac_entropy.2916903923 |
| Short name | T462 |
| Test name | |
| Test status | |
| Simulation time | 2487118790 ps |
| CPU time | 213.33 seconds |
| Started | Aug 13 07:14:39 PM PDT 24 |
| Finished | Aug 13 07:18:13 PM PDT 24 |
| Peak memory | 610508 kb |
| Host | smart-1add7e8d-411b-4362-8acb-d8396b238b63 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=kmac_entropy_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2916903923 -assert nopostproc +UVM_TESTNAME= chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/ null -cm_name 1.chip_sw_kmac_entropy.2916903923 |
| Directory | /workspace/1.chip_sw_kmac_entropy/latest |
| Test location | /workspace/coverage/default/1.chip_sw_kmac_idle.2113240739 |
| Short name | T987 |
| Test name | |
| Test status | |
| Simulation time | 2543534224 ps |
| CPU time | 232.58 seconds |
| Started | Aug 13 07:19:13 PM PDT 24 |
| Finished | Aug 13 07:23:06 PM PDT 24 |
| Peak memory | 610192 kb |
| Host | smart-7c972c93-bcbe-4362-8e02-965b71288991 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=kmac_idle_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2113240739 -assert nopostproc +UVM_TESTNAME=chi p_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul l -cm_name 1.chip_sw_kmac_idle.2113240739 |
| Directory | /workspace/1.chip_sw_kmac_idle/latest |
| Test location | /workspace/coverage/default/1.chip_sw_kmac_mode_cshake.3978003342 |
| Short name | T95 |
| Test name | |
| Test status | |
| Simulation time | 2854686612 ps |
| CPU time | 283.12 seconds |
| Started | Aug 13 07:17:18 PM PDT 24 |
| Finished | Aug 13 07:22:02 PM PDT 24 |
| Peak memory | 610128 kb |
| Host | smart-185d0fc6-c893-4c71-94b6-a93cff9d8466 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=kmac_mode_cshake_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3978003342 -assert nopostproc +UVM_TESTN AME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log / dev/null -cm_name 1.chip_sw_kmac_mode_cshake.3978003342 |
| Directory | /workspace/1.chip_sw_kmac_mode_cshake/latest |
| Test location | /workspace/coverage/default/1.chip_sw_kmac_mode_kmac.2114340546 |
| Short name | T1212 |
| Test name | |
| Test status | |
| Simulation time | 2942983248 ps |
| CPU time | 269.01 seconds |
| Started | Aug 13 07:17:45 PM PDT 24 |
| Finished | Aug 13 07:22:14 PM PDT 24 |
| Peak memory | 610404 kb |
| Host | smart-f8e91ef1-c86b-43de-a557-aa4e935a2505 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=kmac_mode_kmac_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2114340546 -assert nopostproc +UVM_TESTNAM E=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 1.chip_sw_kmac_mode_kmac.2114340546 |
| Directory | /workspace/1.chip_sw_kmac_mode_kmac/latest |
| Test location | /workspace/coverage/default/1.chip_sw_kmac_mode_kmac_jitter_en.692099233 |
| Short name | T974 |
| Test name | |
| Test status | |
| Simulation time | 2666315619 ps |
| CPU time | 285.66 seconds |
| Started | Aug 13 07:18:35 PM PDT 24 |
| Finished | Aug 13 07:23:21 PM PDT 24 |
| Peak memory | 610420 kb |
| Host | smart-3e0c605c-40bc-4baf-a0de-daa2c8346f0a |
| User | root |
| Command | /workspace/default/simv +en_jitter=1 +sw_build_device=sim_dv +sw_images=kmac_mode_kmac_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=692099233 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_kmac_mode_kmac_jitter_en.692099233 |
| Directory | /workspace/1.chip_sw_kmac_mode_kmac_jitter_en/latest |
| Test location | /workspace/coverage/default/1.chip_sw_kmac_mode_kmac_jitter_en_reduced_freq.1643977934 |
| Short name | T982 |
| Test name | |
| Test status | |
| Simulation time | 3530767390 ps |
| CPU time | 297.08 seconds |
| Started | Aug 13 07:21:07 PM PDT 24 |
| Finished | Aug 13 07:26:05 PM PDT 24 |
| Peak memory | 610396 kb |
| Host | smart-20600567-1742-4d30-b88e-810d4c419f86 |
| User | root |
| Command | /workspace/default/simv +en_jitter=1 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=kmac_mode_kmac_test:1:new_rules,test_rom:0 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16439779 34 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac e/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_kmac_mode_kmac_jitter_en_reduced_freq.1643977934 |
| Directory | /workspace/1.chip_sw_kmac_mode_kmac_jitter_en_reduced_freq/latest |
| Test location | /workspace/coverage/default/1.chip_sw_kmac_smoketest.4250334016 |
| Short name | T1373 |
| Test name | |
| Test status | |
| Simulation time | 2885375904 ps |
| CPU time | 418.01 seconds |
| Started | Aug 13 07:21:17 PM PDT 24 |
| Finished | Aug 13 07:28:16 PM PDT 24 |
| Peak memory | 610448 kb |
| Host | smart-f7d1d2c1-7366-4cc6-aa68-d6fa22607774 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=kmac_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4250334016 -assert nopostproc +UVM_TESTNAME=chi p_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul l -cm_name 1.chip_sw_kmac_smoketest.4250334016 |
| Directory | /workspace/1.chip_sw_kmac_smoketest/latest |
| Test location | /workspace/coverage/default/1.chip_sw_lc_ctrl_otp_hw_cfg0.3738816300 |
| Short name | T298 |
| Test name | |
| Test status | |
| Simulation time | 3205427456 ps |
| CPU time | 279.52 seconds |
| Started | Aug 13 07:15:42 PM PDT 24 |
| Finished | Aug 13 07:20:22 PM PDT 24 |
| Peak memory | 610340 kb |
| Host | smart-81164294-0b3d-4945-8e93-0295fc8f2723 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=lc_ctrl_otp_hw_cfg0_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3738816300 -assert nopostproc +UVM_TE STNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_lo g /dev/null -cm_name 1.chip_sw_lc_ctrl_otp_hw_cfg0.3738816300 |
| Directory | /workspace/1.chip_sw_lc_ctrl_otp_hw_cfg0/latest |
| Test location | /workspace/coverage/default/1.chip_sw_lc_ctrl_program_error.230342599 |
| Short name | T175 |
| Test name | |
| Test status | |
| Simulation time | 4780048350 ps |
| CPU time | 526 seconds |
| Started | Aug 13 07:19:26 PM PDT 24 |
| Finished | Aug 13 07:28:12 PM PDT 24 |
| Peak memory | 611844 kb |
| Host | smart-1f60307d-d721-492d-b553-9bb1827b1c23 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=lc_ctrl_program_error:1:new_rules,test_rom:0 + cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_ seed=230342599 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_program_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_lc_ctrl_program_error.230342599 |
| Directory | /workspace/1.chip_sw_lc_ctrl_program_error/latest |
| Test location | /workspace/coverage/default/1.chip_sw_lc_ctrl_rand_to_scrap.2470645346 |
| Short name | T180 |
| Test name | |
| Test status | |
| Simulation time | 3628881609 ps |
| CPU time | 248.09 seconds |
| Started | Aug 13 07:17:20 PM PDT 24 |
| Finished | Aug 13 07:21:28 PM PDT 24 |
| Peak memory | 622140 kb |
| Host | smart-8520c413-3344-420e-80c9-81969227c630 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=lc_ctrl_scrap_test:1:new_rules,test_rom:0 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24706453 46 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_scrap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_lc_ctrl_rand_to_scrap.2470645346 |
| Directory | /workspace/1.chip_sw_lc_ctrl_rand_to_scrap/latest |
| Test location | /workspace/coverage/default/1.chip_sw_lc_ctrl_transition.137458040 |
| Short name | T1297 |
| Test name | |
| Test status | |
| Simulation time | 6830843850 ps |
| CPU time | 416.9 seconds |
| Started | Aug 13 07:13:21 PM PDT 24 |
| Finished | Aug 13 07:20:19 PM PDT 24 |
| Peak memory | 621880 kb |
| Host | smart-b48d1f85-c2dc-475f-80b7-e851ac89d3e8 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=lc_ctrl_transition_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=137458040 -assert nopostproc +UVM_TEST NAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_transition_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul t.vdb -cm_log /dev/null -cm_name 1.chip_sw_lc_ctrl_transition.137458040 |
| Directory | /workspace/1.chip_sw_lc_ctrl_transition/latest |
| Test location | /workspace/coverage/default/1.chip_sw_lc_ctrl_volatile_raw_unlock.524343769 |
| Short name | T1221 |
| Test name | |
| Test status | |
| Simulation time | 2557779657 ps |
| CPU time | 115.22 seconds |
| Started | Aug 13 07:20:19 PM PDT 24 |
| Finished | Aug 13 07:22:15 PM PDT 24 |
| Peak memory | 618956 kb |
| Host | smart-d2aa1b97-6daf-4ec1-9ed2-508467ad0d7b |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStRaw +exp_volatile_raw_unlock_en=0 +sw_build_device=sim_dv +sw_images=lc_ctrl_volatile_raw_unlock_tes t:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/ tools/sim.tcl +ntb_random_seed=524343769 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_volatile_raw_unlock_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_lc_ctrl_volatile_raw_unlock.524343769 |
| Directory | /workspace/1.chip_sw_lc_ctrl_volatile_raw_unlock/latest |
| Test location | /workspace/coverage/default/1.chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz.801610102 |
| Short name | T121 |
| Test name | |
| Test status | |
| Simulation time | 2846040096 ps |
| CPU time | 111.97 seconds |
| Started | Aug 13 07:16:37 PM PDT 24 |
| Finished | Aug 13 07:18:30 PM PDT 24 |
| Peak memory | 618308 kb |
| Host | smart-9774ea7b-a5cb-4a31-bdd3-8cec5c87d89a |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStRaw +chip_clock_source=ChipClockSourceExternal48Mhz +exp_volatile_raw_unlock_en=0 +sw_build_device=s im_dv +sw_images=lc_ctrl_volatile_raw_unlock_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=801610102 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST _SEQ=chip_sw_lc_volatile_raw_unlock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 1.chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz.801610102 |
| Directory | /workspace/1.chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz/latest |
| Test location | /workspace/coverage/default/1.chip_sw_lc_walkthrough_dev.526557971 |
| Short name | T1058 |
| Test name | |
| Test status | |
| Simulation time | 48445359162 ps |
| CPU time | 5199.57 seconds |
| Started | Aug 13 07:14:38 PM PDT 24 |
| Finished | Aug 13 08:41:19 PM PDT 24 |
| Peak memory | 624876 kb |
| Host | smart-02e56e72-0a2a-4962-8f99-be442ce68c7b |
| User | root |
| Command | /workspace/default/simv +flash_program_latency=5 +use_otp_image=OtpTypeLcStRaw +dest_dec_state=DecLcStDev +sw_test_timeout_ns=200_000_000 +sw_build_de vice=sim_dv +sw_images=lc_walkthrough_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=526557971 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=ch ip_sw_lc_walkthrough_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_ sw_lc_walkthrough_dev.526557971 |
| Directory | /workspace/1.chip_sw_lc_walkthrough_dev/latest |
| Test location | /workspace/coverage/default/1.chip_sw_lc_walkthrough_prod.683976735 |
| Short name | T243 |
| Test name | |
| Test status | |
| Simulation time | 47452731520 ps |
| CPU time | 5534.08 seconds |
| Started | Aug 13 07:15:37 PM PDT 24 |
| Finished | Aug 13 08:47:52 PM PDT 24 |
| Peak memory | 621104 kb |
| Host | smart-1e009184-85c4-43a6-8256-6346fee3ec13 |
| User | root |
| Command | /workspace/default/simv +flash_program_latency=5 +use_otp_image=OtpTypeLcStRaw +dest_dec_state=DecLcStProd +sw_test_timeout_ns=200_000_000 +sw_build_d evice=sim_dv +sw_images=lc_walkthrough_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=683976735 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=c hip_sw_lc_walkthrough_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip _sw_lc_walkthrough_prod.683976735 |
| Directory | /workspace/1.chip_sw_lc_walkthrough_prod/latest |
| Test location | /workspace/coverage/default/1.chip_sw_lc_walkthrough_prodend.3955902114 |
| Short name | T309 |
| Test name | |
| Test status | |
| Simulation time | 8781059228 ps |
| CPU time | 1037.43 seconds |
| Started | Aug 13 07:15:35 PM PDT 24 |
| Finished | Aug 13 07:32:53 PM PDT 24 |
| Peak memory | 620856 kb |
| Host | smart-81215e2d-ed46-46ef-9a99-3654873a17dc |
| User | root |
| Command | /workspace/default/simv +flash_program_latency=5 +use_otp_image=OtpTypeLcStRaw +dest_dec_state=DecLcStProdEnd +sw_build_device=sim_dv +sw_images=lc_wa lkthrough_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3955902114 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_walkthrough_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_lc_walkthrough_prodend.3955902114 |
| Directory | /workspace/1.chip_sw_lc_walkthrough_prodend/latest |
| Test location | /workspace/coverage/default/1.chip_sw_lc_walkthrough_testunlocks.1847070034 |
| Short name | T1123 |
| Test name | |
| Test status | |
| Simulation time | 20774915201 ps |
| CPU time | 1919.5 seconds |
| Started | Aug 13 07:15:36 PM PDT 24 |
| Finished | Aug 13 07:47:36 PM PDT 24 |
| Peak memory | 624704 kb |
| Host | smart-f76d9faf-395c-40a0-a9b4-67084b845fbc |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStRaw +dest_dec_state=DecLcStTestUnlock7 +sw_build_device=sim_dv +sw_images=lc_walkthrough_testunlocks _test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=1847070034 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_walkthrough_testunlocks_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_lc_walkthrough_testun locks.1847070034 |
| Directory | /workspace/1.chip_sw_lc_walkthrough_testunlocks/latest |
| Test location | /workspace/coverage/default/1.chip_sw_otbn_ecdsa_op_irq.2541587930 |
| Short name | T155 |
| Test name | |
| Test status | |
| Simulation time | 17422473096 ps |
| CPU time | 4064.48 seconds |
| Started | Aug 13 07:17:46 PM PDT 24 |
| Finished | Aug 13 08:25:31 PM PDT 24 |
| Peak memory | 610684 kb |
| Host | smart-81556596-b494-4d7c-b885-8a3323d0c751 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=28_000_000 +rng_srate_value=30 +sw_build_device=sim_dv +sw_images=otbn_ecdsa_op_irq_test:1:new_rules,test_ rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ random_seed=2541587930 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_otbn_ecdsa_op_irq.2541587930 |
| Directory | /workspace/1.chip_sw_otbn_ecdsa_op_irq/latest |
| Test location | /workspace/coverage/default/1.chip_sw_otbn_ecdsa_op_irq_jitter_en.1604333878 |
| Short name | T116 |
| Test name | |
| Test status | |
| Simulation time | 18650801638 ps |
| CPU time | 3703.51 seconds |
| Started | Aug 13 07:14:09 PM PDT 24 |
| Finished | Aug 13 08:15:53 PM PDT 24 |
| Peak memory | 610768 kb |
| Host | smart-4d4efeb6-bcbc-4ca2-a3ed-a367d2360964 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=33_000_000 +rng_srate_value=30 +en_jitter=1 +sw_build_device=sim_dv +sw_images=otbn_ecdsa_op_irq_test:1:ne w_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/ sim.tcl +ntb_random_seed=1604333878 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tg l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_otbn_ecdsa_op_irq_jitter_en.1604333878 |
| Directory | /workspace/1.chip_sw_otbn_ecdsa_op_irq_jitter_en/latest |
| Test location | /workspace/coverage/default/1.chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq.959866094 |
| Short name | T1257 |
| Test name | |
| Test status | |
| Simulation time | 24791795850 ps |
| CPU time | 3514.15 seconds |
| Started | Aug 13 07:21:08 PM PDT 24 |
| Finished | Aug 13 08:19:43 PM PDT 24 |
| Peak memory | 610976 kb |
| Host | smart-225e0822-dcef-49fd-837c-233637cf65b1 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=33_000_000 +rng_srate_value=30 +en_jitter=1 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=otbn_e cdsa_op_irq_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/ repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=959866094 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_otbn_ecdsa_op_irq_jitter_en_reduc ed_freq.959866094 |
| Directory | /workspace/1.chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq/latest |
| Test location | /workspace/coverage/default/1.chip_sw_otbn_mem_scramble.2447391163 |
| Short name | T290 |
| Test name | |
| Test status | |
| Simulation time | 4118519780 ps |
| CPU time | 535.69 seconds |
| Started | Aug 13 07:14:58 PM PDT 24 |
| Finished | Aug 13 07:23:54 PM PDT 24 |
| Peak memory | 610600 kb |
| Host | smart-1f752d81-6fec-4d52-9422-dfa4307e3d94 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=15_000_000 +en_scb_tl_err_chk=0 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=otbn _mem_scramble_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2447391163 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_otbn_mem_scramble.2447391163 |
| Directory | /workspace/1.chip_sw_otbn_mem_scramble/latest |
| Test location | /workspace/coverage/default/1.chip_sw_otbn_randomness.2502827731 |
| Short name | T1062 |
| Test name | |
| Test status | |
| Simulation time | 5560280682 ps |
| CPU time | 1011.14 seconds |
| Started | Aug 13 07:16:47 PM PDT 24 |
| Finished | Aug 13 07:33:39 PM PDT 24 |
| Peak memory | 610980 kb |
| Host | smart-11760f8d-94a4-47e1-8074-6b8e161d2fc7 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +rng_srate_value=30 +sw_build_device=sim_dv +sw_images=otbn_randomness_test:1:new_rules,test_ro m:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=2502827731 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_otbn_randomness.2502827731 |
| Directory | /workspace/1.chip_sw_otbn_randomness/latest |
| Test location | /workspace/coverage/default/1.chip_sw_otbn_smoketest.2274956617 |
| Short name | T1140 |
| Test name | |
| Test status | |
| Simulation time | 6957007022 ps |
| CPU time | 1383.23 seconds |
| Started | Aug 13 07:23:04 PM PDT 24 |
| Finished | Aug 13 07:46:07 PM PDT 24 |
| Peak memory | 611028 kb |
| Host | smart-8288a4d3-90d3-4535-b5ea-2c4afe304ac6 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=otbn_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2274956617 -assert nopostproc +UVM_TESTNAME=chi p_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul l -cm_name 1.chip_sw_otbn_smoketest.2274956617 |
| Directory | /workspace/1.chip_sw_otbn_smoketest/latest |
| Test location | /workspace/coverage/default/1.chip_sw_otp_ctrl_ecc_error_vendor_test.2827237959 |
| Short name | T938 |
| Test name | |
| Test status | |
| Simulation time | 2770400662 ps |
| CPU time | 282.62 seconds |
| Started | Aug 13 07:19:12 PM PDT 24 |
| Finished | Aug 13 07:23:55 PM PDT 24 |
| Peak memory | 610484 kb |
| Host | smart-b5f326f1-8ddb-4b14-b265-4c738c759976 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=otp_ctrl_vendor_test_ecc_error_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2827237959 -assert nopostp roc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_otp_ctrl_vendor_test_ecc_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_otp_ctrl_ecc_error_vendor_test.2827237959 |
| Directory | /workspace/1.chip_sw_otp_ctrl_ecc_error_vendor_test/latest |
| Test location | /workspace/coverage/default/1.chip_sw_otp_ctrl_lc_signals_dev.2886220222 |
| Short name | T1014 |
| Test name | |
| Test status | |
| Simulation time | 8457270834 ps |
| CPU time | 1216.29 seconds |
| Started | Aug 13 07:15:06 PM PDT 24 |
| Finished | Aug 13 07:35:23 PM PDT 24 |
| Peak memory | 611100 kb |
| Host | smart-571e8afc-b1cf-4863-b24a-2dd201d6251e |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStDev +otp_clear_secret2=1 +sw_build_device=sim_dv +sw_images=otp_ctrl_lc_signals_test:1:new_rules,tes t_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +nt b_random_seed=2886220222 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_otp_ctrl_lc_signals_dev.2886220222 |
| Directory | /workspace/1.chip_sw_otp_ctrl_lc_signals_dev/latest |
| Test location | /workspace/coverage/default/1.chip_sw_otp_ctrl_lc_signals_prod.4143818630 |
| Short name | T385 |
| Test name | |
| Test status | |
| Simulation time | 7527436884 ps |
| CPU time | 1295.26 seconds |
| Started | Aug 13 07:15:23 PM PDT 24 |
| Finished | Aug 13 07:36:59 PM PDT 24 |
| Peak memory | 611364 kb |
| Host | smart-a051d53b-9149-4b53-b798-f0e5995f7b8f |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStProd +otp_clear_secret2=1 +sw_build_device=sim_dv +sw_images=otp_ctrl_lc_signals_test:1:new_rules,te st_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n tb_random_seed=4143818630 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_otp_ctrl_lc_signals_prod.4143818630 |
| Directory | /workspace/1.chip_sw_otp_ctrl_lc_signals_prod/latest |
| Test location | /workspace/coverage/default/1.chip_sw_otp_ctrl_lc_signals_rma.1998026827 |
| Short name | T287 |
| Test name | |
| Test status | |
| Simulation time | 7545175200 ps |
| CPU time | 1014.33 seconds |
| Started | Aug 13 07:15:33 PM PDT 24 |
| Finished | Aug 13 07:32:27 PM PDT 24 |
| Peak memory | 611372 kb |
| Host | smart-9e0d862c-9273-42e2-b21c-4a068313a153 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStRma +otp_clear_secret2=1 +sw_build_device=sim_dv +sw_images=otp_ctrl_lc_signals_test:1:new_rules,tes t_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +nt b_random_seed=1998026827 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_otp_ctrl_lc_signals_rma.1998026827 |
| Directory | /workspace/1.chip_sw_otp_ctrl_lc_signals_rma/latest |
| Test location | /workspace/coverage/default/1.chip_sw_otp_ctrl_lc_signals_test_unlocked0.726582893 |
| Short name | T958 |
| Test name | |
| Test status | |
| Simulation time | 4158871512 ps |
| CPU time | 776.26 seconds |
| Started | Aug 13 07:14:59 PM PDT 24 |
| Finished | Aug 13 07:27:55 PM PDT 24 |
| Peak memory | 610372 kb |
| Host | smart-2eb7825a-7be9-4f28-b7ae-e5e3b2665bcf |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStTestUnlocked0 +otp_clear_secret2=1 +sw_build_device=sim_dv +sw_images=otp_ctrl_lc_signals_test:1:new _rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/s im.tcl +ntb_random_seed=726582893 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_otp_ctrl_lc_signals_test_unlocked0.726582893 |
| Directory | /workspace/1.chip_sw_otp_ctrl_lc_signals_test_unlocked0/latest |
| Test location | /workspace/coverage/default/1.chip_sw_otp_ctrl_smoketest.2000171755 |
| Short name | T550 |
| Test name | |
| Test status | |
| Simulation time | 2681723850 ps |
| CPU time | 230.52 seconds |
| Started | Aug 13 07:24:01 PM PDT 24 |
| Finished | Aug 13 07:27:52 PM PDT 24 |
| Peak memory | 610100 kb |
| Host | smart-62a4a972-d152-4681-8183-d38962eb1bdc |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=otp_ctrl_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2000171755 -assert nopostproc +UVM_TESTNAME =chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 1.chip_sw_otp_ctrl_smoketest.2000171755 |
| Directory | /workspace/1.chip_sw_otp_ctrl_smoketest/latest |
| Test location | /workspace/coverage/default/1.chip_sw_pattgen_ios.1411849594 |
| Short name | T1305 |
| Test name | |
| Test status | |
| Simulation time | 2692598122 ps |
| CPU time | 214.49 seconds |
| Started | Aug 13 07:17:29 PM PDT 24 |
| Finished | Aug 13 07:21:04 PM PDT 24 |
| Peak memory | 613840 kb |
| Host | smart-85ecc86b-bf29-4f52-9177-3f3a5817cd16 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=5_000_000 +sw_build_device=sim_dv +sw_images=pattgen_ios_test:1:new_rules,test_rom:0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1411849594 -ass ert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_patt_ios_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/c overage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_pattgen_ios.1411849594 |
| Directory | /workspace/1.chip_sw_pattgen_ios/latest |
| Test location | /workspace/coverage/default/1.chip_sw_plic_sw_irq.3490980742 |
| Short name | T747 |
| Test name | |
| Test status | |
| Simulation time | 2416423896 ps |
| CPU time | 253.7 seconds |
| Started | Aug 13 07:18:26 PM PDT 24 |
| Finished | Aug 13 07:22:40 PM PDT 24 |
| Peak memory | 610408 kb |
| Host | smart-1a92ea37-ff08-4e98-85ff-fbd3a2ddb106 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=plic_sw_irq_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3490980742 -assert nopostproc +UVM_TESTNAME=c hip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n ull -cm_name 1.chip_sw_plic_sw_irq.3490980742 |
| Directory | /workspace/1.chip_sw_plic_sw_irq/latest |
| Test location | /workspace/coverage/default/1.chip_sw_power_idle_load.831055484 |
| Short name | T154 |
| Test name | |
| Test status | |
| Simulation time | 4627190684 ps |
| CPU time | 690.45 seconds |
| Started | Aug 13 07:21:06 PM PDT 24 |
| Finished | Aug 13 07:32:36 PM PDT 24 |
| Peak memory | 610968 kb |
| Host | smart-13d9d0a3-4429-49bf-ab0a-10222d5b3158 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=chip_power_idle_load:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=831055484 -assert nopostproc +UVM_TESTNAM E=chip_base_test +UVM_TEST_SEQ=chip_sw_power_idle_load_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_power_idle_load.831055484 |
| Directory | /workspace/1.chip_sw_power_idle_load/latest |
| Test location | /workspace/coverage/default/1.chip_sw_power_sleep_load.1609301525 |
| Short name | T91 |
| Test name | |
| Test status | |
| Simulation time | 4481933420 ps |
| CPU time | 433.15 seconds |
| Started | Aug 13 07:21:08 PM PDT 24 |
| Finished | Aug 13 07:28:21 PM PDT 24 |
| Peak memory | 610396 kb |
| Host | smart-2a48b2c9-d549-41b6-9eba-37b66bf842d3 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=chip_power_sleep_load:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1609301525 -assert nopostproc +UVM_TESTN AME=chip_base_test +UVM_TEST_SEQ=chip_sw_power_sleep_load_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v db -cm_log /dev/null -cm_name 1.chip_sw_power_sleep_load.1609301525 |
| Directory | /workspace/1.chip_sw_power_sleep_load/latest |
| Test location | /workspace/coverage/default/1.chip_sw_power_virus.2083986111 |
| Short name | T210 |
| Test name | |
| Test status | |
| Simulation time | 5696046732 ps |
| CPU time | 1223.53 seconds |
| Started | Aug 13 07:27:28 PM PDT 24 |
| Finished | Aug 13 07:47:52 PM PDT 24 |
| Peak memory | 625412 kb |
| Host | smart-2b581de2-2fba-4a0c-9569-2b4b0e13a615 |
| User | root |
| Command | /workspace/default/simv +rng_srate_value_min=15 +rng_srate_value_max=20 +sw_test_timeout_ns=400_000_000 +use_otp_image=OtpTypeCustom +accelerate_cold_ power_up_time=3 +accelerate_regulators_power_up_time=2 +sw_build_device=sim_dv +sw_images=power_virus_systemtest:1:new_rules,power_virus_systemtes t_otp_img_rma:4,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d v/tools/sim.tcl +ntb_random_seed=2083986111 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_power_virus_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_power_virus.2083986111 |
| Directory | /workspace/1.chip_sw_power_virus/latest |
| Test location | /workspace/coverage/default/1.chip_sw_pwrmgr_all_reset_reqs.1722555993 |
| Short name | T1321 |
| Test name | |
| Test status | |
| Simulation time | 13428283653 ps |
| CPU time | 2039.83 seconds |
| Started | Aug 13 07:15:30 PM PDT 24 |
| Finished | Aug 13 07:49:30 PM PDT 24 |
| Peak memory | 612168 kb |
| Host | smart-0a0cd742-45e6-40af-8b90-036f3bacfe97 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=50_000_000 +sw_build_device=sim_dv +sw_images=pwrmgr_all_reset_reqs_test:1:new_rules,test_rom:0 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1722 555993 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_deep_sleep_all_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_pwrmgr_all_reset_reqs.1722555993 |
| Directory | /workspace/1.chip_sw_pwrmgr_all_reset_reqs/latest |
| Test location | /workspace/coverage/default/1.chip_sw_pwrmgr_b2b_sleep_reset_req.2444047670 |
| Short name | T4 |
| Test name | |
| Test status | |
| Simulation time | 24310934722 ps |
| CPU time | 2970.44 seconds |
| Started | Aug 13 07:17:16 PM PDT 24 |
| Finished | Aug 13 08:06:47 PM PDT 24 |
| Peak memory | 611616 kb |
| Host | smart-8e1fa7d6-26cf-4d08-b175-362fb2f291d9 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=35_000_000 +sw_build_device=sim_dv +sw_images=pwrmgr_b2b_sleep_reset_test:1:new_rules,test_rom:0 +cdc_inst rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=244 4047670 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_repeat_reset_wkup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_pwrmgr_b2b_sleep_reset_req.2444047670 |
| Directory | /workspace/1.chip_sw_pwrmgr_b2b_sleep_reset_req/latest |
| Test location | /workspace/coverage/default/1.chip_sw_pwrmgr_deep_sleep_all_reset_reqs.2237537207 |
| Short name | T963 |
| Test name | |
| Test status | |
| Simulation time | 14799232261 ps |
| CPU time | 1366.13 seconds |
| Started | Aug 13 07:15:20 PM PDT 24 |
| Finished | Aug 13 07:38:06 PM PDT 24 |
| Peak memory | 612216 kb |
| Host | smart-bafc8873-ceeb-4283-a980-7abb02499ca0 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=50_000_000 +sw_build_device=sim_dv +sw_images=pwrmgr_deep_sleep_all_reset_reqs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=2237537207 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_deep_sleep_all_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_pwrmgr_deep_sleep_all_reset_reqs.2237537207 |
| Directory | /workspace/1.chip_sw_pwrmgr_deep_sleep_all_reset_reqs/latest |
| Test location | /workspace/coverage/default/1.chip_sw_pwrmgr_deep_sleep_all_wake_ups.313843814 |
| Short name | T58 |
| Test name | |
| Test status | |
| Simulation time | 22201682392 ps |
| CPU time | 2073.67 seconds |
| Started | Aug 13 07:19:59 PM PDT 24 |
| Finished | Aug 13 07:54:33 PM PDT 24 |
| Peak memory | 611856 kb |
| Host | smart-e1010ccb-b6cc-4cdb-9974-e12677078a45 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=pwrmgr_deep_sleep_all_wake_ups:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 313843814 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_pwrmgr_deep_sleep_all_wake_ups_vseq +en_cov=1 -cm line+cond+fsm+tg l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_pwrmgr_deep_sleep_all_wake_ups.313843814 |
| Directory | /workspace/1.chip_sw_pwrmgr_deep_sleep_all_wake_ups/latest |
| Test location | /workspace/coverage/default/1.chip_sw_pwrmgr_deep_sleep_por_reset.199885069 |
| Short name | T1068 |
| Test name | |
| Test status | |
| Simulation time | 9837060804 ps |
| CPU time | 841.64 seconds |
| Started | Aug 13 07:17:20 PM PDT 24 |
| Finished | Aug 13 07:31:22 PM PDT 24 |
| Peak memory | 611604 kb |
| Host | smart-5bcd2b43-b943-4bba-9d26-2ed3108812fd |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_deep_sleep_por_reset_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=199885069 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sleep_por_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/ default.vdb -cm_log /dev/null -cm_name 1.chip_sw_pwrmgr_deep_sleep_por_reset.199885069 |
| Directory | /workspace/1.chip_sw_pwrmgr_deep_sleep_por_reset/latest |
| Test location | /workspace/coverage/default/1.chip_sw_pwrmgr_deep_sleep_power_glitch_reset.2355907591 |
| Short name | T314 |
| Test name | |
| Test status | |
| Simulation time | 5976664960 ps |
| CPU time | 546.57 seconds |
| Started | Aug 13 07:14:09 PM PDT 24 |
| Finished | Aug 13 07:23:16 PM PDT 24 |
| Peak memory | 618056 kb |
| Host | smart-05e57a9e-e2bd-406f-8043-028d600530d7 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=pwrmgr_deep_sleep_power_glitch_test:1:new_rules,test_rom :0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=2355907591 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_deep_power_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_pwrmgr_deep_sleep_power_glitch_reset.2355907591 |
| Directory | /workspace/1.chip_sw_pwrmgr_deep_sleep_power_glitch_reset/latest |
| Test location | /workspace/coverage/default/1.chip_sw_pwrmgr_full_aon_reset.3713802266 |
| Short name | T1395 |
| Test name | |
| Test status | |
| Simulation time | 8411879544 ps |
| CPU time | 516.09 seconds |
| Started | Aug 13 07:15:29 PM PDT 24 |
| Finished | Aug 13 07:24:05 PM PDT 24 |
| Peak memory | 610264 kb |
| Host | smart-2f7754e4-9de4-4542-a11c-74f44922fcc8 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=rstmgr_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3713802266 -assert nopostproc +UVM_TESTNAME=c hip_base_test +UVM_TEST_SEQ=chip_sw_full_aon_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_ log /dev/null -cm_name 1.chip_sw_pwrmgr_full_aon_reset.3713802266 |
| Directory | /workspace/1.chip_sw_pwrmgr_full_aon_reset/latest |
| Test location | /workspace/coverage/default/1.chip_sw_pwrmgr_lowpower_cancel.2499217461 |
| Short name | T269 |
| Test name | |
| Test status | |
| Simulation time | 4165552822 ps |
| CPU time | 456.65 seconds |
| Started | Aug 13 07:19:35 PM PDT 24 |
| Finished | Aug 13 07:27:12 PM PDT 24 |
| Peak memory | 610408 kb |
| Host | smart-960251a8-d51b-4353-a033-a6e04cf86030 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_lowpower_cancel_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2499217461 -assert nopostproc +UVM _TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm _log /dev/null -cm_name 1.chip_sw_pwrmgr_lowpower_cancel.2499217461 |
| Directory | /workspace/1.chip_sw_pwrmgr_lowpower_cancel/latest |
| Test location | /workspace/coverage/default/1.chip_sw_pwrmgr_main_power_glitch_reset.1335546820 |
| Short name | T1108 |
| Test name | |
| Test status | |
| Simulation time | 4321641288 ps |
| CPU time | 325.96 seconds |
| Started | Aug 13 07:17:09 PM PDT 24 |
| Finished | Aug 13 07:22:35 PM PDT 24 |
| Peak memory | 616964 kb |
| Host | smart-c57821ad-e64a-4f65-87a9-98edf8a77d85 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=pwrmgr_main_power_glitch_test:1:new_rules,test_rom:0 +cd c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se ed=1335546820 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_main_power_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_pwrmgr_main_power_glitch_reset.1335546820 |
| Directory | /workspace/1.chip_sw_pwrmgr_main_power_glitch_reset/latest |
| Test location | /workspace/coverage/default/1.chip_sw_pwrmgr_normal_sleep_all_wake_ups.3302262098 |
| Short name | T97 |
| Test name | |
| Test status | |
| Simulation time | 7315868744 ps |
| CPU time | 424.82 seconds |
| Started | Aug 13 07:20:27 PM PDT 24 |
| Finished | Aug 13 07:27:31 PM PDT 24 |
| Peak memory | 611060 kb |
| Host | smart-11e99146-cf24-4b1d-8a2a-e0d148ff5514 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_normal_sleep_all_wake_ups:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3302262098 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_pwrmgr_deep_sleep_all_wake_ups_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_pwrmgr_normal_sleep_all_wake_ups.3302262098 |
| Directory | /workspace/1.chip_sw_pwrmgr_normal_sleep_all_wake_ups/latest |
| Test location | /workspace/coverage/default/1.chip_sw_pwrmgr_normal_sleep_por_reset.2720372800 |
| Short name | T960 |
| Test name | |
| Test status | |
| Simulation time | 6072507892 ps |
| CPU time | 568.72 seconds |
| Started | Aug 13 07:16:52 PM PDT 24 |
| Finished | Aug 13 07:26:21 PM PDT 24 |
| Peak memory | 611556 kb |
| Host | smart-c88d2ca7-c2aa-4f15-971d-e6af687c693f |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_normal_sleep_por_reset_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2720372800 -assert nopostpr oc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sleep_por_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera ge/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_pwrmgr_normal_sleep_por_reset.2720372800 |
| Directory | /workspace/1.chip_sw_pwrmgr_normal_sleep_por_reset/latest |
| Test location | /workspace/coverage/default/1.chip_sw_pwrmgr_random_sleep_all_reset_reqs.3826781218 |
| Short name | T324 |
| Test name | |
| Test status | |
| Simulation time | 20721425852 ps |
| CPU time | 1788.25 seconds |
| Started | Aug 13 07:17:07 PM PDT 24 |
| Finished | Aug 13 07:46:55 PM PDT 24 |
| Peak memory | 612220 kb |
| Host | smart-fb8eb212-6161-4d71-8d6f-8947a6323214 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=50_000_000 +sw_build_device=sim_dv +sw_images=pwrmgr_random_sleep_all_reset_reqs_test:1:new_rules,test_rom :0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=3826781218 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_deep_sleep_all_reset_vseq +en_cov=1 -cm line+cond+fsm+tg l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_pwrmgr_random_sleep_all_reset_reqs.3826781218 |
| Directory | /workspace/1.chip_sw_pwrmgr_random_sleep_all_reset_reqs/latest |
| Test location | /workspace/coverage/default/1.chip_sw_pwrmgr_random_sleep_all_wake_ups.2918575601 |
| Short name | T110 |
| Test name | |
| Test status | |
| Simulation time | 21802718822 ps |
| CPU time | 1454.23 seconds |
| Started | Aug 13 07:19:15 PM PDT 24 |
| Finished | Aug 13 07:43:29 PM PDT 24 |
| Peak memory | 611676 kb |
| Host | smart-87873640-669d-4d4a-b4cd-847e33e3e88c |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +do_random=1 +sw_build_device=sim_dv +sw_images=pwrmgr_random_sleep_all_wake_ups:1:new_rules,te st_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n tb_random_seed=2918575601 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_pwrmgr_deep_sleep_all_wake_ups_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_pwrmgr_random_sleep_all_wake_ups.2918575601 |
| Directory | /workspace/1.chip_sw_pwrmgr_random_sleep_all_wake_ups/latest |
| Test location | /workspace/coverage/default/1.chip_sw_pwrmgr_random_sleep_power_glitch_reset.1612532859 |
| Short name | T1337 |
| Test name | |
| Test status | |
| Simulation time | 32643613090 ps |
| CPU time | 3161.71 seconds |
| Started | Aug 13 07:15:56 PM PDT 24 |
| Finished | Aug 13 08:08:38 PM PDT 24 |
| Peak memory | 612536 kb |
| Host | smart-7018c4ca-10bf-449f-9a7a-2c7852fa9785 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_test_timeout_ns=24_000_000 +sw_build_device=sim_dv +sw_images=pwrmgr_random_sleep_power _glitch_reset_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1612532859 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_random_power_glit ch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_pwrmgr_random_s leep_power_glitch_reset.1612532859 |
| Directory | /workspace/1.chip_sw_pwrmgr_random_sleep_power_glitch_reset/latest |
| Test location | /workspace/coverage/default/1.chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up.2186406926 |
| Short name | T373 |
| Test name | |
| Test status | |
| Simulation time | 5035377012 ps |
| CPU time | 423.25 seconds |
| Started | Aug 13 07:20:08 PM PDT 24 |
| Finished | Aug 13 07:27:11 PM PDT 24 |
| Peak memory | 611996 kb |
| Host | smart-a4c3316a-43ad-45c1-8482-9f3f7d21cacf |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +do_random=1 +sw_build_device=sim_dv +sw_images=pwrmgr_sensor_ctrl_deep_sleep_wake_up:1:new_rul es,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t cl +ntb_random_seed=2186406926 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_pwrmgr_sensor_ctrl_deep_s leep_wake_up.2186406926 |
| Directory | /workspace/1.chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up/latest |
| Test location | /workspace/coverage/default/1.chip_sw_pwrmgr_sleep_disabled.263774752 |
| Short name | T746 |
| Test name | |
| Test status | |
| Simulation time | 3597064904 ps |
| CPU time | 272.22 seconds |
| Started | Aug 13 07:15:20 PM PDT 24 |
| Finished | Aug 13 07:19:52 PM PDT 24 |
| Peak memory | 610312 kb |
| Host | smart-240f27ea-e441-4144-b0de-e6e24ccf5b38 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_sleep_disabled_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=263774752 -assert nopostproc +UVM_T ESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l og /dev/null -cm_name 1.chip_sw_pwrmgr_sleep_disabled.263774752 |
| Directory | /workspace/1.chip_sw_pwrmgr_sleep_disabled/latest |
| Test location | /workspace/coverage/default/1.chip_sw_pwrmgr_sleep_power_glitch_reset.814134145 |
| Short name | T1101 |
| Test name | |
| Test status | |
| Simulation time | 4746551960 ps |
| CPU time | 454.53 seconds |
| Started | Aug 13 07:15:33 PM PDT 24 |
| Finished | Aug 13 07:23:08 PM PDT 24 |
| Peak memory | 617940 kb |
| Host | smart-55de3630-67ae-491e-b84c-2d0fc714d750 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=pwrmgr_sleep_power_glitch_test:1:new_rules,test_rom:0 +c dc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_s eed=814134145 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_main_power_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_pwrmgr_sleep_power_glitch_reset.814134145 |
| Directory | /workspace/1.chip_sw_pwrmgr_sleep_power_glitch_reset/latest |
| Test location | /workspace/coverage/default/1.chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup.2022832204 |
| Short name | T135 |
| Test name | |
| Test status | |
| Simulation time | 4842348544 ps |
| CPU time | 613.54 seconds |
| Started | Aug 13 07:20:48 PM PDT 24 |
| Finished | Aug 13 07:31:02 PM PDT 24 |
| Peak memory | 609384 kb |
| Host | smart-e4b7d9c9-75f3-4f8f-9b5a-3dd508002dd1 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=8_000_000 +sw_build_device=sim_dv +sw_images=sensor_ctrl_wakeup_test:1:new_rules,test_rom:0 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20228322 04 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac e/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup.2022832204 |
| Directory | /workspace/1.chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup/latest |
| Test location | /workspace/coverage/default/1.chip_sw_pwrmgr_sleep_wake_5_bug.2271641223 |
| Short name | T1132 |
| Test name | |
| Test status | |
| Simulation time | 6640679984 ps |
| CPU time | 569.77 seconds |
| Started | Aug 13 07:23:07 PM PDT 24 |
| Finished | Aug 13 07:32:37 PM PDT 24 |
| Peak memory | 611444 kb |
| Host | smart-ff518c65-5b78-43ef-a31b-4695229b444a |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +do_random=1 +sw_build_device=sim_dv +sw_images=pwrmgr_sleep_wake_5_bug_test:1:new_rules,test_r om:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r andom_seed=2271641223 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_pwrmgr_sleep_wake_5_bug.2271641223 |
| Directory | /workspace/1.chip_sw_pwrmgr_sleep_wake_5_bug/latest |
| Test location | /workspace/coverage/default/1.chip_sw_pwrmgr_smoketest.1737207160 |
| Short name | T449 |
| Test name | |
| Test status | |
| Simulation time | 5888119558 ps |
| CPU time | 570.49 seconds |
| Started | Aug 13 07:26:41 PM PDT 24 |
| Finished | Aug 13 07:36:13 PM PDT 24 |
| Peak memory | 611000 kb |
| Host | smart-634e4398-0a44-4f06-9ea5-81593f2d92f3 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=10000000 +sw_build_device=sim_dv +sw_images=pwrmgr_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1737207160 -asse rt nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera ge/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_pwrmgr_smoketest.1737207160 |
| Directory | /workspace/1.chip_sw_pwrmgr_smoketest/latest |
| Test location | /workspace/coverage/default/1.chip_sw_pwrmgr_sysrst_ctrl_reset.2868162038 |
| Short name | T1085 |
| Test name | |
| Test status | |
| Simulation time | 5709869730 ps |
| CPU time | 1055.37 seconds |
| Started | Aug 13 07:15:15 PM PDT 24 |
| Finished | Aug 13 07:32:50 PM PDT 24 |
| Peak memory | 611588 kb |
| Host | smart-e51b49e4-454a-4266-b383-aa38de0f6947 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_sysrst_ctrl_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2868162038 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sysrst_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_pwrmgr_sysrst_ctrl_reset.2868162038 |
| Directory | /workspace/1.chip_sw_pwrmgr_sysrst_ctrl_reset/latest |
| Test location | /workspace/coverage/default/1.chip_sw_pwrmgr_usb_clk_disabled_when_active.1350188843 |
| Short name | T1128 |
| Test name | |
| Test status | |
| Simulation time | 4707787074 ps |
| CPU time | 475.08 seconds |
| Started | Aug 13 07:16:17 PM PDT 24 |
| Finished | Aug 13 07:24:13 PM PDT 24 |
| Peak memory | 611040 kb |
| Host | smart-7fd52841-20a9-4a76-a4a1-5154c083ddda |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_usb_clk_disabled_when_active_test:1:new_rules,test_rom:0 +cdc_instrumentation_enable d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1350188843 -assert no postproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de fault.vdb -cm_log /dev/null -cm_name 1.chip_sw_pwrmgr_usb_clk_disabled_when_active.1350188843 |
| Directory | /workspace/1.chip_sw_pwrmgr_usb_clk_disabled_when_active/latest |
| Test location | /workspace/coverage/default/1.chip_sw_pwrmgr_usbdev_smoketest.4075352317 |
| Short name | T1170 |
| Test name | |
| Test status | |
| Simulation time | 5859843120 ps |
| CPU time | 558.61 seconds |
| Started | Aug 13 07:22:03 PM PDT 24 |
| Finished | Aug 13 07:31:22 PM PDT 24 |
| Peak memory | 610424 kb |
| Host | smart-d3cd1ddb-1542-4036-aaef-7c0111f99917 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_usbdev_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4075352317 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_pwrmgr_usbdev_smoketest.4075352317 |
| Directory | /workspace/1.chip_sw_pwrmgr_usbdev_smoketest/latest |
| Test location | /workspace/coverage/default/1.chip_sw_pwrmgr_wdog_reset.1377941523 |
| Short name | T435 |
| Test name | |
| Test status | |
| Simulation time | 4190202692 ps |
| CPU time | 708.09 seconds |
| Started | Aug 13 07:17:09 PM PDT 24 |
| Finished | Aug 13 07:28:57 PM PDT 24 |
| Peak memory | 610836 kb |
| Host | smart-4eb73e76-5539-4651-84b0-11515a766d05 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=pwrmgr_wdog_reset_reqs_test:1:new_rules,test_rom:0 +cdc_inst rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=137 7941523 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_pwrmgr_wdog_reset.1377941523 |
| Directory | /workspace/1.chip_sw_pwrmgr_wdog_reset/latest |
| Test location | /workspace/coverage/default/1.chip_sw_rom_ctrl_integrity_check.4169855721 |
| Short name | T280 |
| Test name | |
| Test status | |
| Simulation time | 8529780385 ps |
| CPU time | 663.78 seconds |
| Started | Aug 13 07:17:45 PM PDT 24 |
| Finished | Aug 13 07:28:49 PM PDT 24 |
| Peak memory | 624708 kb |
| Host | smart-34dcb96a-bd22-41a2-a8c0-03d2b45533ac |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=rom_ctrl_integrity_check_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4169855721 -assert nopostproc +U VM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rom_ctrl_integrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co verage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_rom_ctrl_integrity_check.4169855721 |
| Directory | /workspace/1.chip_sw_rom_ctrl_integrity_check/latest |
| Test location | /workspace/coverage/default/1.chip_sw_rstmgr_alert_info.894167503 |
| Short name | T251 |
| Test name | |
| Test status | |
| Simulation time | 10098459240 ps |
| CPU time | 1537.18 seconds |
| Started | Aug 13 07:15:27 PM PDT 24 |
| Finished | Aug 13 07:41:05 PM PDT 24 |
| Peak memory | 611340 kb |
| Host | smart-568f92d4-c07f-4564-bc3c-689292b586ea |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=30_000_000 +en_scb_tl_err_chk=0 +sw_build_device=sim_dv +sw_images=rstmgr_alert_info_test:1:new_rules,test _rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb _random_seed=894167503 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_rstmgr_alert_info.894167503 |
| Directory | /workspace/1.chip_sw_rstmgr_alert_info/latest |
| Test location | /workspace/coverage/default/1.chip_sw_rstmgr_cpu_info.4281900516 |
| Short name | T250 |
| Test name | |
| Test status | |
| Simulation time | 7052439920 ps |
| CPU time | 590.28 seconds |
| Started | Aug 13 07:16:45 PM PDT 24 |
| Finished | Aug 13 07:26:36 PM PDT 24 |
| Peak memory | 611296 kb |
| Host | smart-5ed3425d-f211-44df-952c-24d0f4a8eb8e |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=rstmgr_cpu_info_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4281900516 -assert nopostproc +UVM_TESTNA ME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 1.chip_sw_rstmgr_cpu_info.4281900516 |
| Directory | /workspace/1.chip_sw_rstmgr_cpu_info/latest |
| Test location | /workspace/coverage/default/1.chip_sw_rstmgr_rst_cnsty_escalation.1463719775 |
| Short name | T368 |
| Test name | |
| Test status | |
| Simulation time | 4718923650 ps |
| CPU time | 771.7 seconds |
| Started | Aug 13 07:15:22 PM PDT 24 |
| Finished | Aug 13 07:28:14 PM PDT 24 |
| Peak memory | 642452 kb |
| Host | smart-f1c67cf7-1702-4090-b157-768311cc591e |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 1463719775 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rstmgr_cnsty_fault_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_rstmgr_rst_cnsty_escalation.1463719775 |
| Directory | /workspace/1.chip_sw_rstmgr_rst_cnsty_escalation/latest |
| Test location | /workspace/coverage/default/1.chip_sw_rstmgr_smoketest.3605975249 |
| Short name | T432 |
| Test name | |
| Test status | |
| Simulation time | 2746262416 ps |
| CPU time | 223.62 seconds |
| Started | Aug 13 07:24:46 PM PDT 24 |
| Finished | Aug 13 07:28:30 PM PDT 24 |
| Peak memory | 610484 kb |
| Host | smart-b0492361-830f-4f38-b40e-1fd56787b810 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=rstmgr_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3605975249 -assert nopostproc +UVM_TESTNAME=c hip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n ull -cm_name 1.chip_sw_rstmgr_smoketest.3605975249 |
| Directory | /workspace/1.chip_sw_rstmgr_smoketest/latest |
| Test location | /workspace/coverage/default/1.chip_sw_rstmgr_sw_req.4207519532 |
| Short name | T1084 |
| Test name | |
| Test status | |
| Simulation time | 3323935160 ps |
| CPU time | 288.27 seconds |
| Started | Aug 13 07:17:16 PM PDT 24 |
| Finished | Aug 13 07:22:05 PM PDT 24 |
| Peak memory | 610900 kb |
| Host | smart-1ee3fc42-2030-4a72-b765-22bba71795a7 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=rstmgr_sw_req_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4207519532 -assert nopostproc +UVM_TESTNAME =chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 1.chip_sw_rstmgr_sw_req.4207519532 |
| Directory | /workspace/1.chip_sw_rstmgr_sw_req/latest |
| Test location | /workspace/coverage/default/1.chip_sw_rstmgr_sw_rst.2404043491 |
| Short name | T1357 |
| Test name | |
| Test status | |
| Simulation time | 2904997096 ps |
| CPU time | 309.9 seconds |
| Started | Aug 13 07:13:37 PM PDT 24 |
| Finished | Aug 13 07:18:48 PM PDT 24 |
| Peak memory | 610456 kb |
| Host | smart-75288f43-b61f-427f-8e95-cd7e00125469 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=rstmgr_sw_rst_ctrl_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2404043491 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_rstmgr_sw_rst.2404043491 |
| Directory | /workspace/1.chip_sw_rstmgr_sw_rst/latest |
| Test location | /workspace/coverage/default/1.chip_sw_rv_core_ibex_address_translation.939711687 |
| Short name | T301 |
| Test name | |
| Test status | |
| Simulation time | 2776384116 ps |
| CPU time | 296.08 seconds |
| Started | Aug 13 07:19:28 PM PDT 24 |
| Finished | Aug 13 07:24:25 PM PDT 24 |
| Peak memory | 610608 kb |
| Host | smart-ed9d870f-1419-47e3-911b-f5f19af1f73c |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=7_000_000 +sw_build_device=sim_dv +sw_images=rv_core_ibex_address_translation_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random _seed=939711687 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_rv_core_ibex_address_translation.939711687 |
| Directory | /workspace/1.chip_sw_rv_core_ibex_address_translation/latest |
| Test location | /workspace/coverage/default/1.chip_sw_rv_core_ibex_icache_invalidate.2970610967 |
| Short name | T188 |
| Test name | |
| Test status | |
| Simulation time | 3300153676 ps |
| CPU time | 261.52 seconds |
| Started | Aug 13 07:19:55 PM PDT 24 |
| Finished | Aug 13 07:24:17 PM PDT 24 |
| Peak memory | 610856 kb |
| Host | smart-03397f03-7bd4-40ba-be46-e6f64f7f0bc8 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=rv_core_ibex_icache_invalidate_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2970610967 -assert nopostp roc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rv_core_ibex_icache_invalidate_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_rv_core_ibex_icache_invalidate.2970610967 |
| Directory | /workspace/1.chip_sw_rv_core_ibex_icache_invalidate/latest |
| Test location | /workspace/coverage/default/1.chip_sw_rv_core_ibex_lockstep_glitch.3882908162 |
| Short name | T405 |
| Test name | |
| Test status | |
| Simulation time | 2557831830 ps |
| CPU time | 193.47 seconds |
| Started | Aug 13 07:19:52 PM PDT 24 |
| Finished | Aug 13 07:23:06 PM PDT 24 |
| Peak memory | 642236 kb |
| Host | smart-4e67def7-758a-4391-bd1b-f3cd76e3d46d |
| User | root |
| Command | /workspace/default/simv +disable_assert_final_checks +sw_build_device=sim_dv +sw_images=aes_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3882908162 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rv_core_ibex_lockstep_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_rv_core_ibex_lockstep_glitch.3882908162 |
| Directory | /workspace/1.chip_sw_rv_core_ibex_lockstep_glitch/latest |
| Test location | /workspace/coverage/default/1.chip_sw_rv_core_ibex_nmi_irq.2685045421 |
| Short name | T548 |
| Test name | |
| Test status | |
| Simulation time | 5689496700 ps |
| CPU time | 789.21 seconds |
| Started | Aug 13 07:14:51 PM PDT 24 |
| Finished | Aug 13 07:28:01 PM PDT 24 |
| Peak memory | 610780 kb |
| Host | smart-7473a7e1-c4dc-4c67-9e8d-c47722118e28 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=10_000_000 +sw_build_device=sim_dv +sw_images=rv_core_ibex_nmi_irq_test:1:new_rules,test_rom:0 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26850 45421 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_rv_core_ibex_nmi_irq.2685045421 |
| Directory | /workspace/1.chip_sw_rv_core_ibex_nmi_irq/latest |
| Test location | /workspace/coverage/default/1.chip_sw_rv_core_ibex_rnd.1851485215 |
| Short name | T957 |
| Test name | |
| Test status | |
| Simulation time | 5327535140 ps |
| CPU time | 1071.64 seconds |
| Started | Aug 13 07:17:20 PM PDT 24 |
| Finished | Aug 13 07:35:12 PM PDT 24 |
| Peak memory | 610944 kb |
| Host | smart-fec472bb-ed6e-4d81-b701-dbdc8e85a58a |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=20_000_000 +rng_srate_value_max=32 +sw_build_device=sim_dv +sw_images=rv_core_ibex_rnd_test:1:new_rules,te st_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n tb_random_seed=1851485215 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_rv_core_ibex_rnd.1851485215 |
| Directory | /workspace/1.chip_sw_rv_core_ibex_rnd/latest |
| Test location | /workspace/coverage/default/1.chip_sw_rv_dm_access_after_escalation_reset.3895175644 |
| Short name | T1 |
| Test name | |
| Test status | |
| Simulation time | 4867420515 ps |
| CPU time | 596.47 seconds |
| Started | Aug 13 07:21:20 PM PDT 24 |
| Finished | Aug 13 07:31:17 PM PDT 24 |
| Peak memory | 621688 kb |
| Host | smart-3d2a8d0b-67d9-45ff-97b0-4530b872c960 |
| User | root |
| Command | /workspace/default/simv +use_jtag_dmi=1 +sw_build_device=sim_dv +sw_images=alert_handler_escalation_test:1:new_rules,test_rom:0 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3895175644 -asse rt nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rv_dm_access_after_escalation_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_rv_dm_access_after_escalation_reset.3895175644 |
| Directory | /workspace/1.chip_sw_rv_dm_access_after_escalation_reset/latest |
| Test location | /workspace/coverage/default/1.chip_sw_rv_dm_access_after_wakeup.1184650957 |
| Short name | T1045 |
| Test name | |
| Test status | |
| Simulation time | 5558166260 ps |
| CPU time | 575.74 seconds |
| Started | Aug 13 07:21:31 PM PDT 24 |
| Finished | Aug 13 07:31:07 PM PDT 24 |
| Peak memory | 620224 kb |
| Host | smart-f37c1b90-59cc-446c-bb94-205782f8a5bb |
| User | root |
| Command | /workspace/default/simv +use_jtag_dmi=1 +sw_build_device=sim_dv +sw_images=rv_dm_access_after_wakeup_rma:1:new_rules,test_rom:0 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1184650957 -asse rt nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rv_dm_access_after_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_rv_dm_access_after_wakeup.1184650957 |
| Directory | /workspace/1.chip_sw_rv_dm_access_after_wakeup/latest |
| Test location | /workspace/coverage/default/1.chip_sw_rv_dm_ndm_reset_req_when_cpu_halted.1163837184 |
| Short name | T320 |
| Test name | |
| Test status | |
| Simulation time | 3801605132 ps |
| CPU time | 444.57 seconds |
| Started | Aug 13 07:19:14 PM PDT 24 |
| Finished | Aug 13 07:26:40 PM PDT 24 |
| Peak memory | 620596 kb |
| Host | smart-a4e721b2-8e18-43a5-90d2-292ef23c4275 |
| User | root |
| Command | /workspace/default/simv +use_jtag_dmi=1 +sw_build_device=sim_dv +sw_images=rv_dm_ndm_reset_req_when_cpu_halted_rma:1:new_rules,test_rom:0 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=116383 7184 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rv_dm_ndm_reset_when_cpu_halted_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_rv_dm_ndm_reset_req_when_cpu_halted.1163837184 |
| Directory | /workspace/1.chip_sw_rv_dm_ndm_reset_req_when_cpu_halted/latest |
| Test location | /workspace/coverage/default/1.chip_sw_rv_plic_smoketest.4075435647 |
| Short name | T1367 |
| Test name | |
| Test status | |
| Simulation time | 2637328000 ps |
| CPU time | 226.35 seconds |
| Started | Aug 13 07:24:24 PM PDT 24 |
| Finished | Aug 13 07:28:11 PM PDT 24 |
| Peak memory | 610112 kb |
| Host | smart-3e96b408-58c3-45e0-acf7-bda4666343e4 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=rv_plic_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4075435647 -assert nopostproc +UVM_TESTNAME= chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/ null -cm_name 1.chip_sw_rv_plic_smoketest.4075435647 |
| Directory | /workspace/1.chip_sw_rv_plic_smoketest/latest |
| Test location | /workspace/coverage/default/1.chip_sw_rv_timer_irq.1087479997 |
| Short name | T1374 |
| Test name | |
| Test status | |
| Simulation time | 2159840110 ps |
| CPU time | 189.82 seconds |
| Started | Aug 13 07:14:55 PM PDT 24 |
| Finished | Aug 13 07:18:05 PM PDT 24 |
| Peak memory | 610264 kb |
| Host | smart-55335b24-2e7a-46a2-99ae-26a14d9036b4 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=rv_timer_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1087479997 -assert nopostproc +UVM_TESTNAME =chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 1.chip_sw_rv_timer_irq.1087479997 |
| Directory | /workspace/1.chip_sw_rv_timer_irq/latest |
| Test location | /workspace/coverage/default/1.chip_sw_rv_timer_smoketest.934044074 |
| Short name | T258 |
| Test name | |
| Test status | |
| Simulation time | 2305874324 ps |
| CPU time | 245.89 seconds |
| Started | Aug 13 07:22:46 PM PDT 24 |
| Finished | Aug 13 07:26:52 PM PDT 24 |
| Peak memory | 610340 kb |
| Host | smart-33b7b544-eee7-4c9a-9f0d-22923db9a088 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=rv_timer_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=934044074 -assert nopostproc +UVM_TESTNAME= chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/ null -cm_name 1.chip_sw_rv_timer_smoketest.934044074 |
| Directory | /workspace/1.chip_sw_rv_timer_smoketest/latest |
| Test location | /workspace/coverage/default/1.chip_sw_sensor_ctrl_status.752071902 |
| Short name | T1402 |
| Test name | |
| Test status | |
| Simulation time | 2805361521 ps |
| CPU time | 260.48 seconds |
| Started | Aug 13 07:18:30 PM PDT 24 |
| Finished | Aug 13 07:22:51 PM PDT 24 |
| Peak memory | 611532 kb |
| Host | smart-a5b7ce85-a311-4f16-bbb7-7b2eb2d46098 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=40_000_000 +sw_build_device=sim_dv +sw_images=sensor_ctrl_status_test:1:new_rules,test_rom:0 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=7520719 02 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sensor_ctrl_status_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_sensor_ctrl_status.752071902 |
| Directory | /workspace/1.chip_sw_sensor_ctrl_status/latest |
| Test location | /workspace/coverage/default/1.chip_sw_sleep_pin_retention.988068520 |
| Short name | T50 |
| Test name | |
| Test status | |
| Simulation time | 4277106460 ps |
| CPU time | 382.02 seconds |
| Started | Aug 13 07:14:39 PM PDT 24 |
| Finished | Aug 13 07:21:01 PM PDT 24 |
| Peak memory | 610424 kb |
| Host | smart-8f55c7be-fd55-44c8-87d9-c1c17f568422 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=sleep_pin_retention_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=988068520 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sleep_pin_retention_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defa ult.vdb -cm_log /dev/null -cm_name 1.chip_sw_sleep_pin_retention.988068520 |
| Directory | /workspace/1.chip_sw_sleep_pin_retention/latest |
| Test location | /workspace/coverage/default/1.chip_sw_sleep_pin_wake.483945319 |
| Short name | T99 |
| Test name | |
| Test status | |
| Simulation time | 3673103544 ps |
| CPU time | 299.27 seconds |
| Started | Aug 13 07:12:23 PM PDT 24 |
| Finished | Aug 13 07:17:22 PM PDT 24 |
| Peak memory | 610416 kb |
| Host | smart-b4f5e6e2-dd53-4bd4-be60-53438e8777de |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStProd +sw_build_device=sim_dv +sw_images=sleep_pin_wake_test:1:new_rules,test_rom:0 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=483945319 - assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sleep_pin_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_sleep_pin_wake.483945319 |
| Directory | /workspace/1.chip_sw_sleep_pin_wake/latest |
| Test location | /workspace/coverage/default/1.chip_sw_sleep_pwm_pulses.1646481197 |
| Short name | T1418 |
| Test name | |
| Test status | |
| Simulation time | 9356341404 ps |
| CPU time | 1417.74 seconds |
| Started | Aug 13 07:12:33 PM PDT 24 |
| Finished | Aug 13 07:36:11 PM PDT 24 |
| Peak memory | 610580 kb |
| Host | smart-a6ba6273-e1b7-4448-9437-48b7f80497bd |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=sleep_pwm_pulses_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1646481197 -assert nopostproc +UVM_TESTN AME=chip_base_test +UVM_TEST_SEQ=chip_sw_pwm_pulses_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm _log /dev/null -cm_name 1.chip_sw_sleep_pwm_pulses.1646481197 |
| Directory | /workspace/1.chip_sw_sleep_pwm_pulses/latest |
| Test location | /workspace/coverage/default/1.chip_sw_sleep_sram_ret_contents_no_scramble.4028539539 |
| Short name | T1249 |
| Test name | |
| Test status | |
| Simulation time | 7750832660 ps |
| CPU time | 521.06 seconds |
| Started | Aug 13 07:19:10 PM PDT 24 |
| Finished | Aug 13 07:27:51 PM PDT 24 |
| Peak memory | 611268 kb |
| Host | smart-5429f840-6a2e-4219-b8f1-7a89b52d78d1 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=20_000_000 +en_scb_tl_err_chk=0 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=sram _ctrl_sleep_sram_ret_contents_no_scramble_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4028539539 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_S EQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_sl eep_sram_ret_contents_no_scramble.4028539539 |
| Directory | /workspace/1.chip_sw_sleep_sram_ret_contents_no_scramble/latest |
| Test location | /workspace/coverage/default/1.chip_sw_sleep_sram_ret_contents_scramble.712670681 |
| Short name | T1354 |
| Test name | |
| Test status | |
| Simulation time | 6822490536 ps |
| CPU time | 859.84 seconds |
| Started | Aug 13 07:17:30 PM PDT 24 |
| Finished | Aug 13 07:31:51 PM PDT 24 |
| Peak memory | 611332 kb |
| Host | smart-156496e1-662e-4d13-a0ed-75bcde4a696c |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=20_000_000 +en_scb_tl_err_chk=0 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=sram _ctrl_sleep_sram_ret_contents_scramble_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=712670681 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=c hip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_sleep_ sram_ret_contents_scramble.712670681 |
| Directory | /workspace/1.chip_sw_sleep_sram_ret_contents_scramble/latest |
| Test location | /workspace/coverage/default/1.chip_sw_spi_device_pass_through.572832665 |
| Short name | T206 |
| Test name | |
| Test status | |
| Simulation time | 6858531437 ps |
| CPU time | 586.31 seconds |
| Started | Aug 13 07:12:59 PM PDT 24 |
| Finished | Aug 13 07:22:45 PM PDT 24 |
| Peak memory | 625312 kb |
| Host | smart-c76b5c1d-fc3e-4961-b33c-1c4f141dae9e |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=spi_passthrough_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=572832665 -assert nopostproc +UVM_TESTNAM E=chip_base_test +UVM_TEST_SEQ=chip_sw_spi_passthrough_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_spi_device_pass_through.572832665 |
| Directory | /workspace/1.chip_sw_spi_device_pass_through/latest |
| Test location | /workspace/coverage/default/1.chip_sw_spi_device_pass_through_collision.4275932841 |
| Short name | T13 |
| Test name | |
| Test status | |
| Simulation time | 4414829172 ps |
| CPU time | 437.39 seconds |
| Started | Aug 13 07:18:27 PM PDT 24 |
| Finished | Aug 13 07:25:44 PM PDT 24 |
| Peak memory | 625348 kb |
| Host | smart-be0b193e-bc03-4523-8cba-757f315923bb |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=spi_passthrough_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4275932841 -assert nopostproc +UVM_TESTNA ME=chip_base_test +UVM_TEST_SEQ=chip_sw_spi_passthrough_collision_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/d efault.vdb -cm_log /dev/null -cm_name 1.chip_sw_spi_device_pass_through_collision.4275932841 |
| Directory | /workspace/1.chip_sw_spi_device_pass_through_collision/latest |
| Test location | /workspace/coverage/default/1.chip_sw_spi_device_pinmux_sleep_retention.4183022740 |
| Short name | T49 |
| Test name | |
| Test status | |
| Simulation time | 3373457982 ps |
| CPU time | 314.5 seconds |
| Started | Aug 13 07:16:48 PM PDT 24 |
| Finished | Aug 13 07:22:03 PM PDT 24 |
| Peak memory | 619784 kb |
| Host | smart-79f180c8-b92b-4084-9d55-dc8dd4949443 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=spi_device_sleep_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4183022740 -assert nopostproc +UVM_TESTN AME=chip_base_test +UVM_TEST_SEQ=chip_sw_spi_device_pinmux_sleep_retention_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/c overage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_spi_device_pinmux_sleep_retention.4183022740 |
| Directory | /workspace/1.chip_sw_spi_device_pinmux_sleep_retention/latest |
| Test location | /workspace/coverage/default/1.chip_sw_spi_device_tpm.3912252902 |
| Short name | T39 |
| Test name | |
| Test status | |
| Simulation time | 3341270886 ps |
| CPU time | 412.63 seconds |
| Started | Aug 13 07:14:00 PM PDT 24 |
| Finished | Aug 13 07:20:53 PM PDT 24 |
| Peak memory | 619380 kb |
| Host | smart-3a719421-a44f-4806-aec0-516e17ce748d |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=spi_device_tpm_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3912252902 -assert nopostproc +UVM_T ESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_spi_device_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default .vdb -cm_log /dev/null -cm_name 1.chip_sw_spi_device_tpm.3912252902 |
| Directory | /workspace/1.chip_sw_spi_device_tpm/latest |
| Test location | /workspace/coverage/default/1.chip_sw_spi_host_tx_rx.3852055626 |
| Short name | T32 |
| Test name | |
| Test status | |
| Simulation time | 3209793210 ps |
| CPU time | 311.66 seconds |
| Started | Aug 13 07:15:08 PM PDT 24 |
| Finished | Aug 13 07:20:20 PM PDT 24 |
| Peak memory | 610408 kb |
| Host | smart-fec64114-e965-4172-97bd-b4fba6c1b514 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=spi_host_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3852055626 -assert nopostproc +UVM_TESTNAM E=chip_base_test +UVM_TEST_SEQ=chip_sw_spi_host_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb - cm_log /dev/null -cm_name 1.chip_sw_spi_host_tx_rx.3852055626 |
| Directory | /workspace/1.chip_sw_spi_host_tx_rx/latest |
| Test location | /workspace/coverage/default/1.chip_sw_sram_ctrl_execution_main.3559983243 |
| Short name | T187 |
| Test name | |
| Test status | |
| Simulation time | 9422385159 ps |
| CPU time | 924.89 seconds |
| Started | Aug 13 07:18:11 PM PDT 24 |
| Finished | Aug 13 07:33:36 PM PDT 24 |
| Peak memory | 610152 kb |
| Host | smart-542a43b4-3949-496c-ad52-5f06eb86581d |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=sram_ctrl_execution_main_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3559983243 -assert nopostproc +U VM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sram_ctrl_execution_main_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co verage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_sram_ctrl_execution_main.3559983243 |
| Directory | /workspace/1.chip_sw_sram_ctrl_execution_main/latest |
| Test location | /workspace/coverage/default/1.chip_sw_sram_ctrl_scrambled_access.2733143015 |
| Short name | T1272 |
| Test name | |
| Test status | |
| Simulation time | 5170118600 ps |
| CPU time | 853.39 seconds |
| Started | Aug 13 07:18:30 PM PDT 24 |
| Finished | Aug 13 07:32:43 PM PDT 24 |
| Peak memory | 611868 kb |
| Host | smart-15e9cf89-75b6-445a-b16c-a6f53b179527 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=12_000_000 +en_scb_tl_err_chk=0 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=sram _ctrl_scrambled_access_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2733143015 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sram_ctr l_scrambled_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw _sram_ctrl_scrambled_access.2733143015 |
| Directory | /workspace/1.chip_sw_sram_ctrl_scrambled_access/latest |
| Test location | /workspace/coverage/default/1.chip_sw_sram_ctrl_scrambled_access_jitter_en.2799179538 |
| Short name | T293 |
| Test name | |
| Test status | |
| Simulation time | 5653374454 ps |
| CPU time | 664.15 seconds |
| Started | Aug 13 07:18:08 PM PDT 24 |
| Finished | Aug 13 07:29:12 PM PDT 24 |
| Peak memory | 611524 kb |
| Host | smart-ba0c39d3-925c-4d27-a28a-bb04fc649782 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=12_000_000 +bypass_alert_ready_to_end_check=1 +en_jitter=1 +en_scb_tl_err_chk=0 +sw_build_device=sim_dv +s w_images=sram_ctrl_scrambled_access_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2799179538 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chi p_sw_sram_ctrl_scrambled_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n ame 1.chip_sw_sram_ctrl_scrambled_access_jitter_en.2799179538 |
| Directory | /workspace/1.chip_sw_sram_ctrl_scrambled_access_jitter_en/latest |
| Test location | /workspace/coverage/default/1.chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq.2432743505 |
| Short name | T291 |
| Test name | |
| Test status | |
| Simulation time | 5632260246 ps |
| CPU time | 680.76 seconds |
| Started | Aug 13 07:21:29 PM PDT 24 |
| Finished | Aug 13 07:32:50 PM PDT 24 |
| Peak memory | 611704 kb |
| Host | smart-895fc8ca-0580-4b74-babf-52331d6846d9 |
| User | root |
| Command | /workspace/default/simv +mem_sel=main +sw_test_timeout_ns=12_000_000 +bypass_alert_ready_to_end_check=1 +en_jitter=1 +en_scb_tl_err_chk=0 +cal_sys_clk _70mhz=1 +sw_build_device=sim_dv +sw_images=sram_ctrl_scrambled_access_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2432743505 -assert nopostproc +UVM_TESTNA ME=chip_base_test +UVM_TEST_SEQ=chip_sw_sram_ctrl_scrambled_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/ default.vdb -cm_log /dev/null -cm_name 1.chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq.2432743505 |
| Directory | /workspace/1.chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq/latest |
| Test location | /workspace/coverage/default/1.chip_sw_sram_ctrl_smoketest.1598679110 |
| Short name | T445 |
| Test name | |
| Test status | |
| Simulation time | 2444939250 ps |
| CPU time | 275.64 seconds |
| Started | Aug 13 07:22:56 PM PDT 24 |
| Finished | Aug 13 07:27:32 PM PDT 24 |
| Peak memory | 610352 kb |
| Host | smart-7773d00b-dd68-49e5-acb6-6d3508a4d909 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=sram_ctrl_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1598679110 -assert nopostproc +UVM_TESTNAM E=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 1.chip_sw_sram_ctrl_smoketest.1598679110 |
| Directory | /workspace/1.chip_sw_sram_ctrl_smoketest/latest |
| Test location | /workspace/coverage/default/1.chip_sw_sysrst_ctrl_ec_rst_l.2849340199 |
| Short name | T1056 |
| Test name | |
| Test status | |
| Simulation time | 20758933708 ps |
| CPU time | 3123.46 seconds |
| Started | Aug 13 07:16:01 PM PDT 24 |
| Finished | Aug 13 08:08:05 PM PDT 24 |
| Peak memory | 610604 kb |
| Host | smart-39c09c68-3845-4cff-8cde-5ec074d9e123 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=sysrst_ctrl_ec_rst_l_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2849340199 -assert nopostproc +UVM_T ESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sysrst_ctrl_ec_rst_l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/d efault.vdb -cm_log /dev/null -cm_name 1.chip_sw_sysrst_ctrl_ec_rst_l.2849340199 |
| Directory | /workspace/1.chip_sw_sysrst_ctrl_ec_rst_l/latest |
| Test location | /workspace/coverage/default/1.chip_sw_sysrst_ctrl_in_irq.3426325388 |
| Short name | T219 |
| Test name | |
| Test status | |
| Simulation time | 4641116410 ps |
| CPU time | 699.51 seconds |
| Started | Aug 13 07:14:06 PM PDT 24 |
| Finished | Aug 13 07:25:47 PM PDT 24 |
| Peak memory | 614452 kb |
| Host | smart-1bb0711d-4f9a-45d8-8e8f-3b521d5cd609 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=sysrst_ctrl_in_irq_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3426325388 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sysrst_ctrl_in_irq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau lt.vdb -cm_log /dev/null -cm_name 1.chip_sw_sysrst_ctrl_in_irq.3426325388 |
| Directory | /workspace/1.chip_sw_sysrst_ctrl_in_irq/latest |
| Test location | /workspace/coverage/default/1.chip_sw_sysrst_ctrl_inputs.2316402398 |
| Short name | T216 |
| Test name | |
| Test status | |
| Simulation time | 3018506406 ps |
| CPU time | 262.44 seconds |
| Started | Aug 13 07:17:17 PM PDT 24 |
| Finished | Aug 13 07:21:41 PM PDT 24 |
| Peak memory | 614104 kb |
| Host | smart-699c332d-4390-485f-ad9a-8ab61fa67e83 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=sysrst_ctrl_inputs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2316402398 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sysrst_ctrl_inputs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau lt.vdb -cm_log /dev/null -cm_name 1.chip_sw_sysrst_ctrl_inputs.2316402398 |
| Directory | /workspace/1.chip_sw_sysrst_ctrl_inputs/latest |
| Test location | /workspace/coverage/default/1.chip_sw_sysrst_ctrl_outputs.159997686 |
| Short name | T767 |
| Test name | |
| Test status | |
| Simulation time | 3764455554 ps |
| CPU time | 397.86 seconds |
| Started | Aug 13 07:17:16 PM PDT 24 |
| Finished | Aug 13 07:23:54 PM PDT 24 |
| Peak memory | 610728 kb |
| Host | smart-8287771d-0b52-4b11-b076-5e7423f20aa5 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=sysrst_ctrl_outputs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=159997686 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sysrst_ctrl_outputs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defa ult.vdb -cm_log /dev/null -cm_name 1.chip_sw_sysrst_ctrl_outputs.159997686 |
| Directory | /workspace/1.chip_sw_sysrst_ctrl_outputs/latest |
| Test location | /workspace/coverage/default/1.chip_sw_sysrst_ctrl_ulp_z3_wakeup.2380738242 |
| Short name | T36 |
| Test name | |
| Test status | |
| Simulation time | 5704074956 ps |
| CPU time | 411.26 seconds |
| Started | Aug 13 07:17:11 PM PDT 24 |
| Finished | Aug 13 07:24:02 PM PDT 24 |
| Peak memory | 610608 kb |
| Host | smart-5b075458-86e9-4d69-bbdc-270ebae9d8e3 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=sysrst_ctrl_ulp_z3_wakeup_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2380738242 -assert nopostproc + UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sysrst_ctrl_ulp_z3_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/ coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_sysrst_ctrl_ulp_z3_wakeup.2380738242 |
| Directory | /workspace/1.chip_sw_sysrst_ctrl_ulp_z3_wakeup/latest |
| Test location | /workspace/coverage/default/1.chip_sw_uart_rand_baudrate.3515053933 |
| Short name | T1375 |
| Test name | |
| Test status | |
| Simulation time | 8169629400 ps |
| CPU time | 1716.96 seconds |
| Started | Aug 13 07:14:30 PM PDT 24 |
| Finished | Aug 13 07:43:08 PM PDT 24 |
| Peak memory | 619324 kb |
| Host | smart-69b787d5-51c5-4c38-b15f-843f64d8a51e |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random _seed=3515053933 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_uart_rand_baudrate.3515053933 |
| Directory | /workspace/1.chip_sw_uart_rand_baudrate/latest |
| Test location | /workspace/coverage/default/1.chip_sw_uart_smoketest.315219913 |
| Short name | T1405 |
| Test name | |
| Test status | |
| Simulation time | 2496502216 ps |
| CPU time | 217.83 seconds |
| Started | Aug 13 07:21:55 PM PDT 24 |
| Finished | Aug 13 07:25:33 PM PDT 24 |
| Peak memory | 612760 kb |
| Host | smart-a445a6d2-83bf-4a54-ac43-4fbe006af091 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=uart_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=315219913 -assert nopostproc +UVM_TESTNAME=chip _base_test +UVM_TEST_SEQ=chip_sw_uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 1.chip_sw_uart_smoketest.315219913 |
| Directory | /workspace/1.chip_sw_uart_smoketest/latest |
| Test location | /workspace/coverage/default/1.chip_sw_uart_tx_rx.1330444699 |
| Short name | T355 |
| Test name | |
| Test status | |
| Simulation time | 4010113464 ps |
| CPU time | 640.32 seconds |
| Started | Aug 13 07:15:46 PM PDT 24 |
| Finished | Aug 13 07:26:26 PM PDT 24 |
| Peak memory | 620520 kb |
| Host | smart-6d5a7bb7-6d92-4325-9909-4a9953b33fa8 |
| User | root |
| Command | /workspace/default/simv +uart_idx=0 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1330444699 -a ssert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ce/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_uart_tx_rx.1330444699 |
| Directory | /workspace/1.chip_sw_uart_tx_rx/latest |
| Test location | /workspace/coverage/default/1.chip_sw_uart_tx_rx_alt_clk_freq.503927152 |
| Short name | T1007 |
| Test name | |
| Test status | |
| Simulation time | 4461587348 ps |
| CPU time | 711.17 seconds |
| Started | Aug 13 07:12:36 PM PDT 24 |
| Finished | Aug 13 07:24:28 PM PDT 24 |
| Peak memory | 625060 kb |
| Host | smart-49688e56-a9db-45be-9440-d30c17bef63d |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=80_000_000 +chip_clock_source=ChipClockSourceExternal96Mhz +calibrate_usb_clk=1 +sw_build_device=sim_dv +s w_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=503927152 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_ba udrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_uart_tx_rx_ alt_clk_freq.503927152 |
| Directory | /workspace/1.chip_sw_uart_tx_rx_alt_clk_freq/latest |
| Test location | /workspace/coverage/default/1.chip_sw_uart_tx_rx_bootstrap.637185101 |
| Short name | T453 |
| Test name | |
| Test status | |
| Simulation time | 78896097106 ps |
| CPU time | 12577.5 seconds |
| Started | Aug 13 07:15:17 PM PDT 24 |
| Finished | Aug 13 10:44:56 PM PDT 24 |
| Peak memory | 634532 kb |
| Host | smart-0867e0d3-d253-4eee-b2f3-b1fbfb08eaa3 |
| User | root |
| Command | /workspace/default/simv +use_spi_load_bootstrap=1 +calibrate_usb_clk=1 +test_timeout_ns=160_000_000 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test :1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=637185101 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_uart_tx_rx_bootstrap.637185101 |
| Directory | /workspace/1.chip_sw_uart_tx_rx_bootstrap/latest |
| Test location | /workspace/coverage/default/1.chip_sw_uart_tx_rx_idx1.2797699195 |
| Short name | T364 |
| Test name | |
| Test status | |
| Simulation time | 4139700712 ps |
| CPU time | 690.79 seconds |
| Started | Aug 13 07:13:23 PM PDT 24 |
| Finished | Aug 13 07:24:55 PM PDT 24 |
| Peak memory | 620520 kb |
| Host | smart-06a4152e-1cc3-48ed-8dd3-0f1b7ad739cd |
| User | root |
| Command | /workspace/default/simv +uart_idx=1 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2797699195 -a ssert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ce/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_uart_tx_rx_idx1.2797699195 |
| Directory | /workspace/1.chip_sw_uart_tx_rx_idx1/latest |
| Test location | /workspace/coverage/default/1.chip_sw_uart_tx_rx_idx2.4245166207 |
| Short name | T1020 |
| Test name | |
| Test status | |
| Simulation time | 4515885224 ps |
| CPU time | 599.06 seconds |
| Started | Aug 13 07:16:06 PM PDT 24 |
| Finished | Aug 13 07:26:05 PM PDT 24 |
| Peak memory | 620788 kb |
| Host | smart-4fefbd77-b746-4751-a173-06cc62774459 |
| User | root |
| Command | /workspace/default/simv +uart_idx=2 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4245166207 -a ssert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ce/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_uart_tx_rx_idx2.4245166207 |
| Directory | /workspace/1.chip_sw_uart_tx_rx_idx2/latest |
| Test location | /workspace/coverage/default/1.chip_sw_uart_tx_rx_idx3.1986510818 |
| Short name | T365 |
| Test name | |
| Test status | |
| Simulation time | 4220027928 ps |
| CPU time | 632.16 seconds |
| Started | Aug 13 07:12:26 PM PDT 24 |
| Finished | Aug 13 07:22:59 PM PDT 24 |
| Peak memory | 624548 kb |
| Host | smart-5425e1bc-3624-4880-a4ea-cdd5b200beaf |
| User | root |
| Command | /workspace/default/simv +uart_idx=3 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1986510818 -a ssert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ce/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_uart_tx_rx_idx3.1986510818 |
| Directory | /workspace/1.chip_sw_uart_tx_rx_idx3/latest |
| Test location | /workspace/coverage/default/1.chip_tap_straps_dev.160904547 |
| Short name | T1363 |
| Test name | |
| Test status | |
| Simulation time | 6355552750 ps |
| CPU time | 532.42 seconds |
| Started | Aug 13 07:22:45 PM PDT 24 |
| Finished | Aug 13 07:31:37 PM PDT 24 |
| Peak memory | 625656 kb |
| Host | smart-de81d9bd-ae23-418e-bfca-863bcb0fd2b4 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStDev +create_jtag_riscv_map=1 +sw_build_device=sim_dv +sw_images=example_test_from_rom:0:test_in_rom: new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=160904547 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_tap_straps_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_tap_straps_dev.160904547 |
| Directory | /workspace/1.chip_tap_straps_dev/latest |
| Test location | /workspace/coverage/default/1.chip_tap_straps_prod.1516759051 |
| Short name | T1117 |
| Test name | |
| Test status | |
| Simulation time | 3177683535 ps |
| CPU time | 129.66 seconds |
| Started | Aug 13 07:18:37 PM PDT 24 |
| Finished | Aug 13 07:20:46 PM PDT 24 |
| Peak memory | 624736 kb |
| Host | smart-9517f53c-db3b-4639-bdaa-56a1ecdd290d |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStProd +create_jtag_riscv_map=1 +sw_build_device=sim_dv +sw_images=example_test_from_rom:0:test_in_rom :new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1516759051 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_tap_straps_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_tap_straps_prod.1516759051 |
| Directory | /workspace/1.chip_tap_straps_prod/latest |
| Test location | /workspace/coverage/default/1.chip_tap_straps_rma.4160263412 |
| Short name | T1304 |
| Test name | |
| Test status | |
| Simulation time | 2341010575 ps |
| CPU time | 171.45 seconds |
| Started | Aug 13 07:20:13 PM PDT 24 |
| Finished | Aug 13 07:23:05 PM PDT 24 |
| Peak memory | 625364 kb |
| Host | smart-58776e0a-5dc1-4c2c-b543-7896d1d00f68 |
| User | root |
| Command | /workspace/default/simv +create_jtag_riscv_map=1 +sw_build_device=sim_dv +sw_images=example_test_from_rom:0:test_in_rom:new_rules +cdc_instrumentation _enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4160263412 -as sert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_tap_straps_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/c overage/default.vdb -cm_log /dev/null -cm_name 1.chip_tap_straps_rma.4160263412 |
| Directory | /workspace/1.chip_tap_straps_rma/latest |
| Test location | /workspace/coverage/default/1.rom_e2e_asm_init_dev.3406061717 |
| Short name | T395 |
| Test name | |
| Test status | |
| Simulation time | 15002148850 ps |
| CPU time | 3876.5 seconds |
| Started | Aug 13 07:25:41 PM PDT 24 |
| Finished | Aug 13 08:30:18 PM PDT 24 |
| Peak memory | 610920 kb |
| Host | smart-2aa20b3e-d68e-4ba0-85c3-0365227295b5 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeCustom +sw_test_timeout_ns=20000000 +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_prod _key_0:1:ot_flash_binary,otp_img_e2e_bootstrap_entry_dev:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3406061717 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_S EQ=chip_sw_rom_e2e_asm_init_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_e2e_asm_init_dev.3406061717 |
| Directory | /workspace/1.rom_e2e_asm_init_dev/latest |
| Test location | /workspace/coverage/default/1.rom_e2e_asm_init_prod.1282117249 |
| Short name | T1307 |
| Test name | |
| Test status | |
| Simulation time | 15464973358 ps |
| CPU time | 3750.89 seconds |
| Started | Aug 13 07:25:43 PM PDT 24 |
| Finished | Aug 13 08:28:14 PM PDT 24 |
| Peak memory | 610620 kb |
| Host | smart-12c45c3f-0f7a-49f5-a49f-53d1e85c28a2 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeCustom +sw_test_timeout_ns=20000000 +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_prod _key_0:1:ot_flash_binary,otp_img_e2e_bootstrap_entry_prod:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1282117249 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_ SEQ=chip_sw_rom_e2e_asm_init_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_e2e_asm_init_prod.1282117249 |
| Directory | /workspace/1.rom_e2e_asm_init_prod/latest |
| Test location | /workspace/coverage/default/1.rom_e2e_asm_init_prod_end.3445881362 |
| Short name | T1104 |
| Test name | |
| Test status | |
| Simulation time | 15029696319 ps |
| CPU time | 3212.97 seconds |
| Started | Aug 13 07:26:53 PM PDT 24 |
| Finished | Aug 13 08:20:26 PM PDT 24 |
| Peak memory | 610648 kb |
| Host | smart-ab41e043-4c6c-4c9b-b8c5-97b79d1785d6 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeCustom +sw_test_timeout_ns=20000000 +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_prod _key_0:1:ot_flash_binary,otp_img_e2e_bootstrap_entry_prod_end:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3445881362 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_T EST_SEQ=chip_sw_rom_e2e_asm_init_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 1.rom_e2e_asm_init_prod_end.3445881362 |
| Directory | /workspace/1.rom_e2e_asm_init_prod_end/latest |
| Test location | /workspace/coverage/default/1.rom_e2e_asm_init_rma.1866230899 |
| Short name | T1187 |
| Test name | |
| Test status | |
| Simulation time | 14573640578 ps |
| CPU time | 3642.85 seconds |
| Started | Aug 13 07:27:31 PM PDT 24 |
| Finished | Aug 13 08:28:14 PM PDT 24 |
| Peak memory | 610832 kb |
| Host | smart-089985b2-650e-479f-a420-e5c7a00dbc15 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeCustom +sw_test_timeout_ns=20000000 +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_prod _key_0:1:ot_flash_binary,otp_img_e2e_bootstrap_entry_rma:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1866230899 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_S EQ=chip_sw_rom_e2e_asm_init_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_e2e_asm_init_rma.1866230899 |
| Directory | /workspace/1.rom_e2e_asm_init_rma/latest |
| Test location | /workspace/coverage/default/1.rom_e2e_asm_init_test_unlocked0.1624991080 |
| Short name | T999 |
| Test name | |
| Test status | |
| Simulation time | 10911537469 ps |
| CPU time | 2898.69 seconds |
| Started | Aug 13 07:26:02 PM PDT 24 |
| Finished | Aug 13 08:14:21 PM PDT 24 |
| Peak memory | 610520 kb |
| Host | smart-2de17dc8-ce0b-4b55-9787-666e3d5ab2e4 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeCustom +sw_test_timeout_ns=410_000_000 +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_p rod_key_0:1:ot_flash_binary,otp_img_e2e_bootstrap_entry_test_unlocked0:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY =UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1624991080 -assert nopostproc +UVM_TESTNAME=chip_base_te st +UVM_TEST_SEQ=chip_sw_rom_e2e_asm_init_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/ null -cm_name 1.rom_e2e_asm_init_test_unlocked0.1624991080 |
| Directory | /workspace/1.rom_e2e_asm_init_test_unlocked0/latest |
| Test location | /workspace/coverage/default/1.rom_e2e_keymgr_init_rom_ext_invalid_meas.791760021 |
| Short name | T272 |
| Test name | |
| Test status | |
| Simulation time | 14660628440 ps |
| CPU time | 3136.61 seconds |
| Started | Aug 13 07:27:01 PM PDT 24 |
| Finished | Aug 13 08:19:18 PM PDT 24 |
| Peak memory | 610820 kb |
| Host | smart-b8649679-6325-4c5c-80fb-6aa4e06252e1 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=40_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=rom_e2e_keymgr_init_otp_invalid _meas:1:new_rules,otp_img_keymgr_otp_invalid_meas:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=791760021 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_ sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_e2e_keymgr_ini t_rom_ext_invalid_meas.791760021 |
| Directory | /workspace/1.rom_e2e_keymgr_init_rom_ext_invalid_meas/latest |
| Test location | /workspace/coverage/default/1.rom_e2e_keymgr_init_rom_ext_meas.2388944306 |
| Short name | T1031 |
| Test name | |
| Test status | |
| Simulation time | 14984140550 ps |
| CPU time | 3334.88 seconds |
| Started | Aug 13 07:27:21 PM PDT 24 |
| Finished | Aug 13 08:22:57 PM PDT 24 |
| Peak memory | 610024 kb |
| Host | smart-4f1ea376-e589-4858-b773-c9718d03a224 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=40_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=rom_e2e_keymgr_init_otp_meas:1: new_rules,otp_img_keymgr_otp_meas:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2388944306 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_e2e_keymgr_init_rom_ext_meas.2388944306 |
| Directory | /workspace/1.rom_e2e_keymgr_init_rom_ext_meas/latest |
| Test location | /workspace/coverage/default/1.rom_e2e_keymgr_init_rom_ext_no_meas.3333064533 |
| Short name | T1341 |
| Test name | |
| Test status | |
| Simulation time | 14539378210 ps |
| CPU time | 3314.76 seconds |
| Started | Aug 13 07:27:24 PM PDT 24 |
| Finished | Aug 13 08:22:40 PM PDT 24 |
| Peak memory | 610872 kb |
| Host | smart-1ede2aa7-9f1d-4525-9122-f2cb545125cf |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=40_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=rom_e2e_keymgr_init_otp_no_meas :1:new_rules,otp_img_keymgr_otp_no_meas:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3333064533 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_e2e_keymgr_init_rom_ext _no_meas.3333064533 |
| Directory | /workspace/1.rom_e2e_keymgr_init_rom_ext_no_meas/latest |
| Test location | /workspace/coverage/default/1.rom_e2e_self_hash.1732479272 |
| Short name | T396 |
| Test name | |
| Test status | |
| Simulation time | 26578511032 ps |
| CPU time | 6020.52 seconds |
| Started | Aug 13 07:26:48 PM PDT 24 |
| Finished | Aug 13 09:07:09 PM PDT 24 |
| Peak memory | 610920 kb |
| Host | smart-a3ca6061-2b16-4732-b9ee-61145a6d6282 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=200_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=rom_e2e_self_hash_test:1:new_r ules,otp_img_sigverify_spx_prod:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1732479272 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_e2e_self_hash.1732479272 |
| Directory | /workspace/1.rom_e2e_self_hash/latest |
| Test location | /workspace/coverage/default/1.rom_e2e_shutdown_exception_c.943468161 |
| Short name | T1160 |
| Test name | |
| Test status | |
| Simulation time | 15627809991 ps |
| CPU time | 3435.17 seconds |
| Started | Aug 13 07:24:18 PM PDT 24 |
| Finished | Aug 13 08:21:34 PM PDT 24 |
| Peak memory | 611048 kb |
| Host | smart-3c4697bc-6d2e-495a-b8d3-1430c7ff390b |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=40000000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=rom_e2e_shutdown_exception_c:1:ne w_rules,otp_img_secret2_locked_rma:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=943468161 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rom_e2e_shut down_exception_c_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_e2e_s hutdown_exception_c.943468161 |
| Directory | /workspace/1.rom_e2e_shutdown_exception_c/latest |
| Test location | /workspace/coverage/default/1.rom_e2e_shutdown_output.1770285245 |
| Short name | T41 |
| Test name | |
| Test status | |
| Simulation time | 29888188256 ps |
| CPU time | 3392.14 seconds |
| Started | Aug 13 07:27:28 PM PDT 24 |
| Finished | Aug 13 08:24:01 PM PDT 24 |
| Peak memory | 613164 kb |
| Host | smart-4c5cf06b-bc20-4d92-860b-c4a9ae872af8 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=20000000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_unsigned:1:ot_f lash_binary,otp_img_shutdown_output_test_unlocked0:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1770285245 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chi p_sw_rom_e2e_shutdown_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_e2e_shutdown_output.1770285245 |
| Directory | /workspace/1.rom_e2e_shutdown_output/latest |
| Test location | /workspace/coverage/default/1.rom_e2e_smoke.2531487901 |
| Short name | T1240 |
| Test name | |
| Test status | |
| Simulation time | 15394810272 ps |
| CPU time | 3819.88 seconds |
| Started | Aug 13 07:25:12 PM PDT 24 |
| Finished | Aug 13 08:28:53 PM PDT 24 |
| Peak memory | 610756 kb |
| Host | smart-a5107a06-c7ee-4dfd-9d01-ad336839fa60 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=40000000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=rom_e2e_smoke:1:new_rules,otp_img _secret2_locked_rma:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_to p/hw/dv/tools/sim.tcl +ntb_random_seed=2531487901 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_e2e_smoke.2531487901 |
| Directory | /workspace/1.rom_e2e_smoke/latest |
| Test location | /workspace/coverage/default/1.rom_e2e_static_critical.596156526 |
| Short name | T1011 |
| Test name | |
| Test status | |
| Simulation time | 17568982444 ps |
| CPU time | 4093.63 seconds |
| Started | Aug 13 07:26:58 PM PDT 24 |
| Finished | Aug 13 08:35:12 PM PDT 24 |
| Peak memory | 610852 kb |
| Host | smart-6d8f7a1b-6a40-4396-8dd8-1c60f0e7d422 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=40000000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=rom_e2e_static_critical:1:new_rul es,otp_img_secret2_locked_rma:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=596156526 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_e2e_static_critical.596156526 |
| Directory | /workspace/1.rom_e2e_static_critical/latest |
| Test location | /workspace/coverage/default/1.rom_keymgr_functest.3663986329 |
| Short name | T1032 |
| Test name | |
| Test status | |
| Simulation time | 4643950320 ps |
| CPU time | 736.26 seconds |
| Started | Aug 13 07:22:04 PM PDT 24 |
| Finished | Aug 13 07:34:20 PM PDT 24 |
| Peak memory | 610360 kb |
| Host | smart-28b49685-43e3-48e4-bdca-e4984eab39ae |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=10_000_000 +sw_build_device=sim_dv +sw_images=keymgr_functest:1:new_rules,test_rom:0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3663986329 -ass ert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 1.rom_keymgr_functest.3663986329 |
| Directory | /workspace/1.rom_keymgr_functest/latest |
| Test location | /workspace/coverage/default/1.rom_raw_unlock.3708095362 |
| Short name | T74 |
| Test name | |
| Test status | |
| Simulation time | 6998383183 ps |
| CPU time | 303.67 seconds |
| Started | Aug 13 07:23:39 PM PDT 24 |
| Finished | Aug 13 07:28:43 PM PDT 24 |
| Peak memory | 620340 kb |
| Host | smart-e35aa911-f951-48d7-b60e-2f31409fcb6a |
| User | root |
| Command | /workspace/default/simv +do_creator_sw_cfg_ast_cfg=0 +sw_test_timeout_ns=200_000_000 +use_otp_image=OtpTypeLcStRaw +chip_clock_source=ChipClockSourceE xternal48Mhz +rom_prod_mode=1 +use_jtag_dmi=1 +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_test_key_0:1:ot_flash_binary,mask_ro m:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=3708095362 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_raw_unlock_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_raw_unlock.3708095362 |
| Directory | /workspace/1.rom_raw_unlock/latest |
| Test location | /workspace/coverage/default/1.rom_volatile_raw_unlock.93765482 |
| Short name | T278 |
| Test name | |
| Test status | |
| Simulation time | 2796007758 ps |
| CPU time | 121.73 seconds |
| Started | Aug 13 07:23:16 PM PDT 24 |
| Finished | Aug 13 07:25:18 PM PDT 24 |
| Peak memory | 617916 kb |
| Host | smart-19251676-a1b9-4e16-aa27-e16075f20733 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=200_000_000 +use_otp_image=OtpTypeLcStRaw +chip_clock_source=ChipClockSourceExternal48Mhz +rom_prod_mode=1 +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_test_key_0:1:ot_flash_binary,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=93765482 -assert nopostproc +UVM_TE STNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_volatile_raw_unlock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/ default.vdb -cm_log /dev/null -cm_name 1.rom_volatile_raw_unlock.93765482 |
| Directory | /workspace/1.rom_volatile_raw_unlock/latest |
| Test location | /workspace/coverage/default/10.chip_sw_lc_ctrl_transition.774594358 |
| Short name | T1286 |
| Test name | |
| Test status | |
| Simulation time | 6858285521 ps |
| CPU time | 489.58 seconds |
| Started | Aug 13 07:33:38 PM PDT 24 |
| Finished | Aug 13 07:41:48 PM PDT 24 |
| Peak memory | 621796 kb |
| Host | smart-ee48947e-465f-42c9-befa-51c1e7952083 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=lc_ctrl_transition_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=774594358 -assert nopostproc +UVM_TEST NAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_transition_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul t.vdb -cm_log /dev/null -cm_name 10.chip_sw_lc_ctrl_transition.774594358 |
| Directory | /workspace/10.chip_sw_lc_ctrl_transition/latest |
| Test location | /workspace/coverage/default/10.chip_sw_uart_rand_baudrate.1806634761 |
| Short name | T1283 |
| Test name | |
| Test status | |
| Simulation time | 7833261196 ps |
| CPU time | 1189.79 seconds |
| Started | Aug 13 07:35:06 PM PDT 24 |
| Finished | Aug 13 07:54:56 PM PDT 24 |
| Peak memory | 620180 kb |
| Host | smart-7471b7ad-d90e-4078-abcf-945caf9d2ca2 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random _seed=1806634761 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.chip_sw_uart_rand_baudrate.1806634761 |
| Directory | /workspace/10.chip_sw_uart_rand_baudrate/latest |
| Test location | /workspace/coverage/default/11.chip_sw_lc_ctrl_transition.2304740199 |
| Short name | T1165 |
| Test name | |
| Test status | |
| Simulation time | 7130768012 ps |
| CPU time | 591.91 seconds |
| Started | Aug 13 07:33:44 PM PDT 24 |
| Finished | Aug 13 07:43:37 PM PDT 24 |
| Peak memory | 622068 kb |
| Host | smart-9e8f15eb-52ab-4232-99c1-ce5f8193b1c3 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=lc_ctrl_transition_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2304740199 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_transition_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau lt.vdb -cm_log /dev/null -cm_name 11.chip_sw_lc_ctrl_transition.2304740199 |
| Directory | /workspace/11.chip_sw_lc_ctrl_transition/latest |
| Test location | /workspace/coverage/default/11.chip_sw_uart_rand_baudrate.4097154563 |
| Short name | T1339 |
| Test name | |
| Test status | |
| Simulation time | 8535832470 ps |
| CPU time | 1471.67 seconds |
| Started | Aug 13 07:37:14 PM PDT 24 |
| Finished | Aug 13 08:01:46 PM PDT 24 |
| Peak memory | 620160 kb |
| Host | smart-553179c2-6014-4f20-be22-e6355f12c04c |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random _seed=4097154563 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.chip_sw_uart_rand_baudrate.4097154563 |
| Directory | /workspace/11.chip_sw_uart_rand_baudrate/latest |
| Test location | /workspace/coverage/default/12.chip_sw_lc_ctrl_transition.2367171384 |
| Short name | T1000 |
| Test name | |
| Test status | |
| Simulation time | 11596716251 ps |
| CPU time | 824.9 seconds |
| Started | Aug 13 07:34:02 PM PDT 24 |
| Finished | Aug 13 07:47:47 PM PDT 24 |
| Peak memory | 622128 kb |
| Host | smart-25837731-1786-495c-92cc-1e8f64b60538 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=lc_ctrl_transition_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2367171384 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_transition_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau lt.vdb -cm_log /dev/null -cm_name 12.chip_sw_lc_ctrl_transition.2367171384 |
| Directory | /workspace/12.chip_sw_lc_ctrl_transition/latest |
| Test location | /workspace/coverage/default/12.chip_sw_uart_rand_baudrate.3354800401 |
| Short name | T1034 |
| Test name | |
| Test status | |
| Simulation time | 8386771900 ps |
| CPU time | 1468.86 seconds |
| Started | Aug 13 07:35:20 PM PDT 24 |
| Finished | Aug 13 07:59:49 PM PDT 24 |
| Peak memory | 619888 kb |
| Host | smart-d5eb62a4-ef7e-43d4-abc8-f2c80263c210 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random _seed=3354800401 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.chip_sw_uart_rand_baudrate.3354800401 |
| Directory | /workspace/12.chip_sw_uart_rand_baudrate/latest |
| Test location | /workspace/coverage/default/13.chip_sw_uart_rand_baudrate.1384952444 |
| Short name | T1113 |
| Test name | |
| Test status | |
| Simulation time | 8802965768 ps |
| CPU time | 1258.81 seconds |
| Started | Aug 13 07:35:39 PM PDT 24 |
| Finished | Aug 13 07:56:38 PM PDT 24 |
| Peak memory | 620092 kb |
| Host | smart-0b6655c9-d517-49a7-9ddc-f3f79496299c |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random _seed=1384952444 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.chip_sw_uart_rand_baudrate.1384952444 |
| Directory | /workspace/13.chip_sw_uart_rand_baudrate/latest |
| Test location | /workspace/coverage/default/14.chip_sw_alert_handler_lpg_sleep_mode_alerts.853990604 |
| Short name | T276 |
| Test name | |
| Test status | |
| Simulation time | 3624829384 ps |
| CPU time | 465.29 seconds |
| Started | Aug 13 07:36:37 PM PDT 24 |
| Finished | Aug 13 07:44:23 PM PDT 24 |
| Peak memory | 649304 kb |
| Host | smart-2f13c8a5-5c20-4f19-8c61-50de9a9af29f |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=853990604 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all _escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.chip_s w_alert_handler_lpg_sleep_mode_alerts.853990604 |
| Directory | /workspace/14.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/14.chip_sw_all_escalation_resets.2712210689 |
| Short name | T270 |
| Test name | |
| Test status | |
| Simulation time | 6014479820 ps |
| CPU time | 789.64 seconds |
| Started | Aug 13 07:34:59 PM PDT 24 |
| Finished | Aug 13 07:48:09 PM PDT 24 |
| Peak memory | 620524 kb |
| Host | smart-7e399c31-654e-471f-9484-180bb29e1046 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 2712210689 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.chip_sw_all_escalation_resets.2712210689 |
| Directory | /workspace/14.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/14.chip_sw_lc_ctrl_transition.587664267 |
| Short name | T1279 |
| Test name | |
| Test status | |
| Simulation time | 11465780369 ps |
| CPU time | 788.6 seconds |
| Started | Aug 13 07:37:15 PM PDT 24 |
| Finished | Aug 13 07:50:25 PM PDT 24 |
| Peak memory | 622168 kb |
| Host | smart-8dbd2daa-2a98-4ab8-85d3-be42befe1071 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=lc_ctrl_transition_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=587664267 -assert nopostproc +UVM_TEST NAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_transition_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul t.vdb -cm_log /dev/null -cm_name 14.chip_sw_lc_ctrl_transition.587664267 |
| Directory | /workspace/14.chip_sw_lc_ctrl_transition/latest |
| Test location | /workspace/coverage/default/14.chip_sw_uart_rand_baudrate.3590264991 |
| Short name | T16 |
| Test name | |
| Test status | |
| Simulation time | 3977592120 ps |
| CPU time | 465.2 seconds |
| Started | Aug 13 07:35:37 PM PDT 24 |
| Finished | Aug 13 07:43:23 PM PDT 24 |
| Peak memory | 619576 kb |
| Host | smart-3745fb1a-0495-4b98-acf2-ebbfbd3ca831 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random _seed=3590264991 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.chip_sw_uart_rand_baudrate.3590264991 |
| Directory | /workspace/14.chip_sw_uart_rand_baudrate/latest |
| Test location | /workspace/coverage/default/15.chip_sw_all_escalation_resets.1649706436 |
| Short name | T788 |
| Test name | |
| Test status | |
| Simulation time | 5976829456 ps |
| CPU time | 806.61 seconds |
| Started | Aug 13 07:34:14 PM PDT 24 |
| Finished | Aug 13 07:47:41 PM PDT 24 |
| Peak memory | 650836 kb |
| Host | smart-83b4a67b-254b-4777-a686-d0742b7aabc5 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 1649706436 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.chip_sw_all_escalation_resets.1649706436 |
| Directory | /workspace/15.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/15.chip_sw_uart_rand_baudrate.4265524459 |
| Short name | T1216 |
| Test name | |
| Test status | |
| Simulation time | 8385185424 ps |
| CPU time | 1528.47 seconds |
| Started | Aug 13 07:35:45 PM PDT 24 |
| Finished | Aug 13 08:01:14 PM PDT 24 |
| Peak memory | 620172 kb |
| Host | smart-e620b891-bedc-4726-a437-e8dedc8765fd |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random _seed=4265524459 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.chip_sw_uart_rand_baudrate.4265524459 |
| Directory | /workspace/15.chip_sw_uart_rand_baudrate/latest |
| Test location | /workspace/coverage/default/16.chip_sw_alert_handler_lpg_sleep_mode_alerts.3231050638 |
| Short name | T393 |
| Test name | |
| Test status | |
| Simulation time | 3543582736 ps |
| CPU time | 418.01 seconds |
| Started | Aug 13 07:37:32 PM PDT 24 |
| Finished | Aug 13 07:44:31 PM PDT 24 |
| Peak memory | 649564 kb |
| Host | smart-273cac12-601a-42a2-bbac-131a38138564 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3231050638 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.chip_ sw_alert_handler_lpg_sleep_mode_alerts.3231050638 |
| Directory | /workspace/16.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/16.chip_sw_all_escalation_resets.2169891757 |
| Short name | T861 |
| Test name | |
| Test status | |
| Simulation time | 4864800932 ps |
| CPU time | 653.67 seconds |
| Started | Aug 13 07:34:47 PM PDT 24 |
| Finished | Aug 13 07:45:40 PM PDT 24 |
| Peak memory | 650840 kb |
| Host | smart-a670194f-40cb-4b93-a6d3-7de043abcf4e |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 2169891757 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.chip_sw_all_escalation_resets.2169891757 |
| Directory | /workspace/16.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/16.chip_sw_uart_rand_baudrate.478701707 |
| Short name | T153 |
| Test name | |
| Test status | |
| Simulation time | 8316500440 ps |
| CPU time | 1189.47 seconds |
| Started | Aug 13 07:34:50 PM PDT 24 |
| Finished | Aug 13 07:54:39 PM PDT 24 |
| Peak memory | 620168 kb |
| Host | smart-eb9cc88d-4c61-4af1-a392-e3f32f7243d0 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random _seed=478701707 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.chip_sw_uart_rand_baudrate.478701707 |
| Directory | /workspace/16.chip_sw_uart_rand_baudrate/latest |
| Test location | /workspace/coverage/default/17.chip_sw_alert_handler_lpg_sleep_mode_alerts.406872011 |
| Short name | T1346 |
| Test name | |
| Test status | |
| Simulation time | 2877298792 ps |
| CPU time | 360.82 seconds |
| Started | Aug 13 07:36:14 PM PDT 24 |
| Finished | Aug 13 07:42:15 PM PDT 24 |
| Peak memory | 619388 kb |
| Host | smart-e2f693d6-fd59-40e4-b91c-68714c27c430 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=406872011 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all _escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.chip_s w_alert_handler_lpg_sleep_mode_alerts.406872011 |
| Directory | /workspace/17.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/17.chip_sw_all_escalation_resets.3908945824 |
| Short name | T307 |
| Test name | |
| Test status | |
| Simulation time | 4980267814 ps |
| CPU time | 764.19 seconds |
| Started | Aug 13 07:36:08 PM PDT 24 |
| Finished | Aug 13 07:48:53 PM PDT 24 |
| Peak memory | 650680 kb |
| Host | smart-83c7f9af-6f07-405e-ae2f-fb708d966756 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 3908945824 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.chip_sw_all_escalation_resets.3908945824 |
| Directory | /workspace/17.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/17.chip_sw_uart_rand_baudrate.3115877430 |
| Short name | T1135 |
| Test name | |
| Test status | |
| Simulation time | 3597189500 ps |
| CPU time | 534.95 seconds |
| Started | Aug 13 07:36:15 PM PDT 24 |
| Finished | Aug 13 07:45:11 PM PDT 24 |
| Peak memory | 620148 kb |
| Host | smart-766c5706-9695-4546-9cc3-528f3ace6620 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random _seed=3115877430 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.chip_sw_uart_rand_baudrate.3115877430 |
| Directory | /workspace/17.chip_sw_uart_rand_baudrate/latest |
| Test location | /workspace/coverage/default/18.chip_sw_all_escalation_resets.384118125 |
| Short name | T966 |
| Test name | |
| Test status | |
| Simulation time | 5411802270 ps |
| CPU time | 777.61 seconds |
| Started | Aug 13 07:36:57 PM PDT 24 |
| Finished | Aug 13 07:49:55 PM PDT 24 |
| Peak memory | 650772 kb |
| Host | smart-5b84a0b2-d0d7-4942-b468-74f4424b36ef |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 384118125 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.chip_sw_all_escalation_resets.384118125 |
| Directory | /workspace/18.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/18.chip_sw_uart_rand_baudrate.4243661237 |
| Short name | T1382 |
| Test name | |
| Test status | |
| Simulation time | 4657547488 ps |
| CPU time | 544.65 seconds |
| Started | Aug 13 07:36:05 PM PDT 24 |
| Finished | Aug 13 07:45:10 PM PDT 24 |
| Peak memory | 620064 kb |
| Host | smart-9a6efb18-47f2-4546-9372-69aa8ce33d10 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random _seed=4243661237 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.chip_sw_uart_rand_baudrate.4243661237 |
| Directory | /workspace/18.chip_sw_uart_rand_baudrate/latest |
| Test location | /workspace/coverage/default/19.chip_sw_uart_rand_baudrate.3580281725 |
| Short name | T339 |
| Test name | |
| Test status | |
| Simulation time | 8109426744 ps |
| CPU time | 1469.91 seconds |
| Started | Aug 13 07:35:18 PM PDT 24 |
| Finished | Aug 13 07:59:49 PM PDT 24 |
| Peak memory | 620192 kb |
| Host | smart-f6dfd6d2-f8be-4044-8406-43fa10485b6f |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random _seed=3580281725 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.chip_sw_uart_rand_baudrate.3580281725 |
| Directory | /workspace/19.chip_sw_uart_rand_baudrate/latest |
| Test location | /workspace/coverage/default/2.chip_jtag_mem_access.867853574 |
| Short name | T212 |
| Test name | |
| Test status | |
| Simulation time | 13560600279 ps |
| CPU time | 1569.02 seconds |
| Started | Aug 13 07:22:22 PM PDT 24 |
| Finished | Aug 13 07:48:31 PM PDT 24 |
| Peak memory | 608476 kb |
| Host | smart-7e72a966-7fd4-4a14-81a7-658fe9986101 |
| User | root |
| Command | /workspace/default/simv +create_jtag_riscv_map=1 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=867853574 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_jtag_m em_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_jtag_mem_access.867853574 |
| Directory | /workspace/2.chip_jtag_mem_access/latest |
| Test location | /workspace/coverage/default/2.chip_rv_dm_ndm_reset_req.2480350008 |
| Short name | T441 |
| Test name | |
| Test status | |
| Simulation time | 4315876656 ps |
| CPU time | 418.42 seconds |
| Started | Aug 13 07:28:44 PM PDT 24 |
| Finished | Aug 13 07:35:43 PM PDT 24 |
| Peak memory | 620240 kb |
| Host | smart-656e7da0-8e1f-44d4-96b5-6084c53a4abb |
| User | root |
| Command | /workspace/default/simv +en_scb_tl_err_chk=0 +use_jtag_dmi=1 +sw_build_device=sim_dv +sw_images=rv_dm_ndm_reset_req_rma:1:new_rules,test_rom:0 +cdc_in strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2 480350008 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_rv_dm_ndm_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_rv_dm_ndm_reset_req.2480350008 |
| Directory | /workspace/2.chip_rv_dm_ndm_reset_req/latest |
| Test location | /workspace/coverage/default/2.chip_sival_flash_info_access.2006914614 |
| Short name | T354 |
| Test name | |
| Test status | |
| Simulation time | 3734170434 ps |
| CPU time | 425.07 seconds |
| Started | Aug 13 07:29:04 PM PDT 24 |
| Finished | Aug 13 07:36:10 PM PDT 24 |
| Peak memory | 610696 kb |
| Host | smart-944553b9-105e-4d30-b491-4df72b7e6c38 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStTestUnlocked0 +sw_build_device=sim_dv +sw_images=flash_ctrl_info_access_lc:1:new_rules,test_rom:0 +c dc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_s eed=2006914614 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sival_flash_info_access.2006914614 |
| Directory | /workspace/2.chip_sival_flash_info_access/latest |
| Test location | /workspace/coverage/default/2.chip_sw_aes_enc.107198388 |
| Short name | T986 |
| Test name | |
| Test status | |
| Simulation time | 2488458944 ps |
| CPU time | 239.9 seconds |
| Started | Aug 13 07:27:24 PM PDT 24 |
| Finished | Aug 13 07:31:24 PM PDT 24 |
| Peak memory | 610260 kb |
| Host | smart-128ff110-3929-4465-a2d8-4bb021195223 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=22_000_000 +sw_build_device=sim_dv +sw_images=aes_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=107198388 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage /default.vdb -cm_log /dev/null -cm_name 2.chip_sw_aes_enc.107198388 |
| Directory | /workspace/2.chip_sw_aes_enc/latest |
| Test location | /workspace/coverage/default/2.chip_sw_aes_enc_jitter_en.3953228010 |
| Short name | T1168 |
| Test name | |
| Test status | |
| Simulation time | 3324983219 ps |
| CPU time | 254.92 seconds |
| Started | Aug 13 07:27:58 PM PDT 24 |
| Finished | Aug 13 07:32:13 PM PDT 24 |
| Peak memory | 609176 kb |
| Host | smart-e56b1a80-b797-42cc-89b6-73fbfa11f13c |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=26_000_000 +en_jitter=1 +sw_build_device=sim_dv +sw_images=aes_smoketest:1:new_rules,test_rom:0 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3953 228010 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work space/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_aes_enc_jitter_en.3953228010 |
| Directory | /workspace/2.chip_sw_aes_enc_jitter_en/latest |
| Test location | /workspace/coverage/default/2.chip_sw_aes_enc_jitter_en_reduced_freq.4054872197 |
| Short name | T989 |
| Test name | |
| Test status | |
| Simulation time | 2845595513 ps |
| CPU time | 341 seconds |
| Started | Aug 13 07:32:17 PM PDT 24 |
| Finished | Aug 13 07:37:58 PM PDT 24 |
| Peak memory | 610476 kb |
| Host | smart-08791c7c-6aa8-4c71-800a-0d0c6704ad2f |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=26_000_000 +en_jitter=1 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=aes_smoketest:1:new_rules, test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4054872197 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_aes_enc_jitter_en_reduced_freq.4054872197 |
| Directory | /workspace/2.chip_sw_aes_enc_jitter_en_reduced_freq/latest |
| Test location | /workspace/coverage/default/2.chip_sw_aes_entropy.3334850223 |
| Short name | T1122 |
| Test name | |
| Test status | |
| Simulation time | 2960243958 ps |
| CPU time | 268.81 seconds |
| Started | Aug 13 07:30:33 PM PDT 24 |
| Finished | Aug 13 07:35:02 PM PDT 24 |
| Peak memory | 610212 kb |
| Host | smart-343b2b6c-df04-4ba6-bda4-2176a6bf3a26 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=15_000_000 +sw_build_device=sim_dv +sw_images=aes_entropy_test:1:new_rules,test_rom:0 +cdc_instrumentation _enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3334850223 -as sert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove rage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_aes_entropy.3334850223 |
| Directory | /workspace/2.chip_sw_aes_entropy/latest |
| Test location | /workspace/coverage/default/2.chip_sw_aes_idle.3670698332 |
| Short name | T758 |
| Test name | |
| Test status | |
| Simulation time | 3127232968 ps |
| CPU time | 224.04 seconds |
| Started | Aug 13 07:27:00 PM PDT 24 |
| Finished | Aug 13 07:30:44 PM PDT 24 |
| Peak memory | 609824 kb |
| Host | smart-a9b4387b-7d69-40ef-872c-7d2c08a96ee7 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=25_000_000 +sw_build_device=sim_dv +sw_images=aes_idle_test:1:new_rules,test_rom:0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3670698332 -asser t nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag e/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_aes_idle.3670698332 |
| Directory | /workspace/2.chip_sw_aes_idle/latest |
| Test location | /workspace/coverage/default/2.chip_sw_aes_masking_off.3204237649 |
| Short name | T1251 |
| Test name | |
| Test status | |
| Simulation time | 3237210522 ps |
| CPU time | 319.27 seconds |
| Started | Aug 13 07:26:35 PM PDT 24 |
| Finished | Aug 13 07:31:55 PM PDT 24 |
| Peak memory | 609896 kb |
| Host | smart-5a778536-1a44-4eac-af64-82ea668af235 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=aes_masking_off_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3204237649 -assert nopostproc +UVM_TESTNA ME=chip_base_test +UVM_TEST_SEQ=chip_sw_aes_masking_off_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_aes_masking_off.3204237649 |
| Directory | /workspace/2.chip_sw_aes_masking_off/latest |
| Test location | /workspace/coverage/default/2.chip_sw_aes_smoketest.1009461127 |
| Short name | T1197 |
| Test name | |
| Test status | |
| Simulation time | 3027454472 ps |
| CPU time | 255.16 seconds |
| Started | Aug 13 07:32:09 PM PDT 24 |
| Finished | Aug 13 07:36:25 PM PDT 24 |
| Peak memory | 610484 kb |
| Host | smart-c8e24cc6-ecf8-4458-b084-240cad8b70dd |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=aes_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1009461127 -assert nopostproc +UVM_TESTNAME=chip _base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_aes_smoketest.1009461127 |
| Directory | /workspace/2.chip_sw_aes_smoketest/latest |
| Test location | /workspace/coverage/default/2.chip_sw_alert_handler_entropy.3490635916 |
| Short name | T1211 |
| Test name | |
| Test status | |
| Simulation time | 3716341597 ps |
| CPU time | 336.94 seconds |
| Started | Aug 13 07:28:37 PM PDT 24 |
| Finished | Aug 13 07:34:15 PM PDT 24 |
| Peak memory | 610100 kb |
| Host | smart-7161702f-801c-473a-ab83-919ad92f675c |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=alert_handler_entropy_test:1:new_rules,test_ro m:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=3490635916 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_alert_handler_entropy.3490635916 |
| Directory | /workspace/2.chip_sw_alert_handler_entropy/latest |
| Test location | /workspace/coverage/default/2.chip_sw_alert_handler_escalation.2864698177 |
| Short name | T1157 |
| Test name | |
| Test status | |
| Simulation time | 4767711316 ps |
| CPU time | 590.81 seconds |
| Started | Aug 13 07:27:38 PM PDT 24 |
| Finished | Aug 13 07:37:29 PM PDT 24 |
| Peak memory | 620264 kb |
| Host | smart-80e523cd-4819-4b38-8d75-1d390fa7da4c |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=alert_handler_escalation_test:1:new_rules,test _rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb _random_seed=2864698177 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_alert_handler_escalation_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_alert_handler_escalation.2864698177 |
| Directory | /workspace/2.chip_sw_alert_handler_escalation/latest |
| Test location | /workspace/coverage/default/2.chip_sw_alert_handler_lpg_clkoff.14882696 |
| Short name | T461 |
| Test name | |
| Test status | |
| Simulation time | 9131411056 ps |
| CPU time | 2030.33 seconds |
| Started | Aug 13 07:26:59 PM PDT 24 |
| Finished | Aug 13 08:00:49 PM PDT 24 |
| Peak memory | 610664 kb |
| Host | smart-c4483e71-ca7f-4309-8f68-6d658d41a67a |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +sw_build_device=sim_dv +sw_images=alert_handler_lpg_clkoff_test:1:new_rules,test_r om:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r andom_seed=14882696 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_alert_handler_lpg_clkoff_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_alert_handler_lpg_clkoff.14882696 |
| Directory | /workspace/2.chip_sw_alert_handler_lpg_clkoff/latest |
| Test location | /workspace/coverage/default/2.chip_sw_alert_handler_lpg_reset_toggle.4201431286 |
| Short name | T222 |
| Test name | |
| Test status | |
| Simulation time | 7322875126 ps |
| CPU time | 1643.31 seconds |
| Started | Aug 13 07:28:51 PM PDT 24 |
| Finished | Aug 13 07:56:15 PM PDT 24 |
| Peak memory | 609788 kb |
| Host | smart-fcf4cad5-d567-434c-a9bd-0e173b5bdc85 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +sw_build_device=sim_dv +sw_images=alert_handler_lpg_reset_toggle_test:1:new_rules, test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4201431286 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_alert_handler_shorten_ping_wait_cycle_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_alert_handler_lpg_reset_togg le.4201431286 |
| Directory | /workspace/2.chip_sw_alert_handler_lpg_reset_toggle/latest |
| Test location | /workspace/coverage/default/2.chip_sw_alert_handler_lpg_sleep_mode_alerts.472157180 |
| Short name | T835 |
| Test name | |
| Test status | |
| Simulation time | 3670593700 ps |
| CPU time | 368.4 seconds |
| Started | Aug 13 07:27:06 PM PDT 24 |
| Finished | Aug 13 07:33:15 PM PDT 24 |
| Peak memory | 649552 kb |
| Host | smart-b4e23685-525c-42ef-86e9-b1dd602b7e53 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=472157180 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all _escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw _alert_handler_lpg_sleep_mode_alerts.472157180 |
| Directory | /workspace/2.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/2.chip_sw_alert_handler_lpg_sleep_mode_pings.3337767869 |
| Short name | T1331 |
| Test name | |
| Test status | |
| Simulation time | 10294040936 ps |
| CPU time | 1097.68 seconds |
| Started | Aug 13 07:27:45 PM PDT 24 |
| Finished | Aug 13 07:46:03 PM PDT 24 |
| Peak memory | 611672 kb |
| Host | smart-44869785-eea0-455c-96b2-0b1245fbbde7 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=alert_handler _lpg_sleep_mode_pings_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3337767869 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_alert_han dler_shorten_ping_wait_cycle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_alert_handler_lpg_sleep_mode_pings.3337767869 |
| Directory | /workspace/2.chip_sw_alert_handler_lpg_sleep_mode_pings/latest |
| Test location | /workspace/coverage/default/2.chip_sw_alert_handler_ping_ok.2744262134 |
| Short name | T1111 |
| Test name | |
| Test status | |
| Simulation time | 8213130532 ps |
| CPU time | 1328.54 seconds |
| Started | Aug 13 07:27:59 PM PDT 24 |
| Finished | Aug 13 07:50:08 PM PDT 24 |
| Peak memory | 610536 kb |
| Host | smart-fd4ae1d8-9dd9-48ff-95e1-0c0c9e2aa6c8 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=24000000 +sw_build_device=sim_dv +sw_images=alert_handler_ping_ok_test:1:new_rules,test_rom:0 +c dc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_s eed=2744262134 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_alert_handler_ping_ok.2744262134 |
| Directory | /workspace/2.chip_sw_alert_handler_ping_ok/latest |
| Test location | /workspace/coverage/default/2.chip_sw_alert_handler_ping_timeout.2291853573 |
| Short name | T411 |
| Test name | |
| Test status | |
| Simulation time | 5060693400 ps |
| CPU time | 578.22 seconds |
| Started | Aug 13 07:28:19 PM PDT 24 |
| Finished | Aug 13 07:37:57 PM PDT 24 |
| Peak memory | 610808 kb |
| Host | smart-91132f72-7a4a-49d9-9616-38314a08948b |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=24000000 +sw_build_device=sim_dv +sw_images=alert_handler_ping_timeout_test:1:new_rules,test_rom :0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=2291853573 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_alert_handler_ping_timeout.2291853573 |
| Directory | /workspace/2.chip_sw_alert_handler_ping_timeout/latest |
| Test location | /workspace/coverage/default/2.chip_sw_alert_handler_reverse_ping_in_deep_sleep.3998523109 |
| Short name | T162 |
| Test name | |
| Test status | |
| Simulation time | 256445869774 ps |
| CPU time | 13000.3 seconds |
| Started | Aug 13 07:28:04 PM PDT 24 |
| Finished | Aug 13 11:04:46 PM PDT 24 |
| Peak memory | 611404 kb |
| Host | smart-103eeb31-29af-4c17-b4a2-16c118f63321 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=300_000_000 +sw_build_device=sim_dv +sw_images=alert_handler_reverse_ping_in_deep_sleep_test:1:n ew_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3998523109 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_alert_handler_reverse_ping_in_deep_sleep.3998523109 |
| Directory | /workspace/2.chip_sw_alert_handler_reverse_ping_in_deep_sleep/latest |
| Test location | /workspace/coverage/default/2.chip_sw_alert_test.731558502 |
| Short name | T48 |
| Test name | |
| Test status | |
| Simulation time | 2844916370 ps |
| CPU time | 307.24 seconds |
| Started | Aug 13 07:27:21 PM PDT 24 |
| Finished | Aug 13 07:32:29 PM PDT 24 |
| Peak memory | 610380 kb |
| Host | smart-cff77a73-1ee5-43de-8432-8b183ab9ed0f |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=alert_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=731558502 -assert nopostproc +UVM_TESTNAME=chip_bas e_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm _name 2.chip_sw_alert_test.731558502 |
| Directory | /workspace/2.chip_sw_alert_test/latest |
| Test location | /workspace/coverage/default/2.chip_sw_aon_timer_irq.393511751 |
| Short name | T260 |
| Test name | |
| Test status | |
| Simulation time | 3766612076 ps |
| CPU time | 448.69 seconds |
| Started | Aug 13 07:25:11 PM PDT 24 |
| Finished | Aug 13 07:32:40 PM PDT 24 |
| Peak memory | 610464 kb |
| Host | smart-cb205193-987f-4f0a-ab34-8a58c7b93c8a |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=aon_timer_irq_test:1:new_rules,test_rom:0 +cdc_instrumentati on_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=393511751 -a ssert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov erage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_aon_timer_irq.393511751 |
| Directory | /workspace/2.chip_sw_aon_timer_irq/latest |
| Test location | /workspace/coverage/default/2.chip_sw_aon_timer_sleep_wdog_sleep_pause.3539181763 |
| Short name | T1417 |
| Test name | |
| Test status | |
| Simulation time | 6626049060 ps |
| CPU time | 347.62 seconds |
| Started | Aug 13 07:26:40 PM PDT 24 |
| Finished | Aug 13 07:32:28 PM PDT 24 |
| Peak memory | 611220 kb |
| Host | smart-bab4eb3e-1f77-4eea-a575-a4243cb92770 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=aon_timer_sleep_wdog_sleep_pause_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=3539181763 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_aon_timer_sleep_wdog_sleep_pause.3539181763 |
| Directory | /workspace/2.chip_sw_aon_timer_sleep_wdog_sleep_pause/latest |
| Test location | /workspace/coverage/default/2.chip_sw_aon_timer_smoketest.1161752288 |
| Short name | T968 |
| Test name | |
| Test status | |
| Simulation time | 2978493436 ps |
| CPU time | 337.21 seconds |
| Started | Aug 13 07:32:17 PM PDT 24 |
| Finished | Aug 13 07:37:54 PM PDT 24 |
| Peak memory | 610488 kb |
| Host | smart-73c896cb-8c68-452f-9fa8-a3be4ab2d00b |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=aon_timer_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1161752288 -assert nopostproc +UVM_TESTNAM E=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 2.chip_sw_aon_timer_smoketest.1161752288 |
| Directory | /workspace/2.chip_sw_aon_timer_smoketest/latest |
| Test location | /workspace/coverage/default/2.chip_sw_aon_timer_wdog_bite_reset.3434101526 |
| Short name | T953 |
| Test name | |
| Test status | |
| Simulation time | 9940272134 ps |
| CPU time | 742.87 seconds |
| Started | Aug 13 07:25:38 PM PDT 24 |
| Finished | Aug 13 07:38:01 PM PDT 24 |
| Peak memory | 611216 kb |
| Host | smart-43d27c88-cde7-4da5-96cc-90f4c4c971f7 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=aon_timer_wdog_bite_reset_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 3434101526 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_aon_timer_wdog_bite_reset.3434101526 |
| Directory | /workspace/2.chip_sw_aon_timer_wdog_bite_reset/latest |
| Test location | /workspace/coverage/default/2.chip_sw_aon_timer_wdog_lc_escalate.861721257 |
| Short name | T980 |
| Test name | |
| Test status | |
| Simulation time | 5741655440 ps |
| CPU time | 641.03 seconds |
| Started | Aug 13 07:26:49 PM PDT 24 |
| Finished | Aug 13 07:37:31 PM PDT 24 |
| Peak memory | 611376 kb |
| Host | smart-46882fa7-86c3-4432-984e-7bb9261fa1ef |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=aon_timer_wdog_lc_escalate_test:1:new_rules,test_rom:0 +cdc_ instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed =861721257 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_aon_timer_wdog_lc_escalate.861721257 |
| Directory | /workspace/2.chip_sw_aon_timer_wdog_lc_escalate/latest |
| Test location | /workspace/coverage/default/2.chip_sw_ast_clk_outputs.2412667517 |
| Short name | T1009 |
| Test name | |
| Test status | |
| Simulation time | 8471312548 ps |
| CPU time | 1052.08 seconds |
| Started | Aug 13 07:33:07 PM PDT 24 |
| Finished | Aug 13 07:50:39 PM PDT 24 |
| Peak memory | 618160 kb |
| Host | smart-9251b1cc-1827-4f1c-8d9b-b36353c56d16 |
| User | root |
| Command | /workspace/default/simv +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=ast_clk_outs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled= 1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2412667517 -assert nopo stproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_ast_clk_outputs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co verage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_ast_clk_outputs.2412667517 |
| Directory | /workspace/2.chip_sw_ast_clk_outputs/latest |
| Test location | /workspace/coverage/default/2.chip_sw_ast_clk_rst_inputs.1700892569 |
| Short name | T146 |
| Test name | |
| Test status | |
| Simulation time | 28330466159 ps |
| CPU time | 3860.1 seconds |
| Started | Aug 13 07:31:20 PM PDT 24 |
| Finished | Aug 13 08:35:42 PM PDT 24 |
| Peak memory | 611552 kb |
| Host | smart-169c5f0b-4be7-4dbe-a36c-c62c9d00f94c |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=200_000_000 +sw_build_device=sim_dv +sw_images=ast_clk_rst_inputs:1:new_rules,test_rom:0 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1700892569 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_ast_clk_rst_inputs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_ast_clk_rst_inputs.1700892569 |
| Directory | /workspace/2.chip_sw_ast_clk_rst_inputs/latest |
| Test location | /workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_lc.2898088494 |
| Short name | T1099 |
| Test name | |
| Test status | |
| Simulation time | 9837332853 ps |
| CPU time | 1155.92 seconds |
| Started | Aug 13 07:32:08 PM PDT 24 |
| Finished | Aug 13 07:51:24 PM PDT 24 |
| Peak memory | 622116 kb |
| Host | smart-043fc15b-ee6c-4945-aafe-c49e4958e1e8 |
| User | root |
| Command | /workspace/default/simv +chip_clock_source=ChipClockSourceExternal48Mhz +sw_build_device=sim_dv +sw_images=clkmgr_external_clk_src_for_lc_test:1:new_r ules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim .tcl +ntb_random_seed=2898088494 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_transition_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_clkmgr_external_clk_src_for_lc.2898088494 |
| Directory | /workspace/2.chip_sw_clkmgr_external_clk_src_for_lc/latest |
| Test location | /workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_fast_dev.4005841095 |
| Short name | T1175 |
| Test name | |
| Test status | |
| Simulation time | 3769943056 ps |
| CPU time | 671.66 seconds |
| Started | Aug 13 07:29:09 PM PDT 24 |
| Finished | Aug 13 07:40:21 PM PDT 24 |
| Peak memory | 614624 kb |
| Host | smart-a3137bef-760a-4fdd-8605-de1f3386e3f8 |
| User | root |
| Command | /workspace/default/simv +chip_clock_source=ChipClockSourceExternal96Mhz +calibrate_usb_clk=1 +src_dec_state=DecLcStDev +sw_build_device=sim_dv +sw_ima ges=clkmgr_external_clk_src_for_sw_fast_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4005841095 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ =chip_sw_lc_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_c lkmgr_external_clk_src_for_sw_fast_dev.4005841095 |
| Directory | /workspace/2.chip_sw_clkmgr_external_clk_src_for_sw_fast_dev/latest |
| Test location | /workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_fast_rma.2969114372 |
| Short name | T1080 |
| Test name | |
| Test status | |
| Simulation time | 4060440658 ps |
| CPU time | 698.91 seconds |
| Started | Aug 13 07:30:40 PM PDT 24 |
| Finished | Aug 13 07:42:19 PM PDT 24 |
| Peak memory | 613928 kb |
| Host | smart-471fd072-79d7-4f63-9e3b-0bee4d4039a8 |
| User | root |
| Command | /workspace/default/simv +chip_clock_source=ChipClockSourceExternal96Mhz +calibrate_usb_clk=1 +src_dec_state=DecLcStRma +sw_build_device=sim_dv +sw_ima ges=clkmgr_external_clk_src_for_sw_fast_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2969114372 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ =chip_sw_lc_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_c lkmgr_external_clk_src_for_sw_fast_rma.2969114372 |
| Directory | /workspace/2.chip_sw_clkmgr_external_clk_src_for_sw_fast_rma/latest |
| Test location | /workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0.1825248749 |
| Short name | T1026 |
| Test name | |
| Test status | |
| Simulation time | 4116956900 ps |
| CPU time | 713.06 seconds |
| Started | Aug 13 07:32:37 PM PDT 24 |
| Finished | Aug 13 07:44:30 PM PDT 24 |
| Peak memory | 614724 kb |
| Host | smart-40ec6dd7-a0b9-471d-afa0-997f0dad2dcd |
| User | root |
| Command | /workspace/default/simv +chip_clock_source=ChipClockSourceExternal96Mhz +calibrate_usb_clk=1 +src_dec_state=DecLcStTestUnlocked0 +sw_build_device=sim_ dv +sw_images=clkmgr_external_clk_src_for_sw_fast_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1825248749 -assert nopostproc +UVM_TESTNAME=chip_base_test +UV M_TEST_SEQ=chip_sw_lc_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2 .chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0.1825248749 |
| Directory | /workspace/2.chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0/latest |
| Test location | /workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_slow_dev.384628302 |
| Short name | T1144 |
| Test name | |
| Test status | |
| Simulation time | 4515229188 ps |
| CPU time | 636.39 seconds |
| Started | Aug 13 07:30:55 PM PDT 24 |
| Finished | Aug 13 07:41:32 PM PDT 24 |
| Peak memory | 614916 kb |
| Host | smart-6b19e4c6-d0eb-48ee-bb48-64c87218f04c |
| User | root |
| Command | /workspace/default/simv +chip_clock_source=ChipClockSourceExternal48Mhz +calibrate_usb_clk=1 +src_dec_state=DecLcStDev +sw_build_device=sim_dv +sw_ima ges=clkmgr_external_clk_src_for_sw_slow_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=384628302 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ= chip_sw_lc_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_cl kmgr_external_clk_src_for_sw_slow_dev.384628302 |
| Directory | /workspace/2.chip_sw_clkmgr_external_clk_src_for_sw_slow_dev/latest |
| Test location | /workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_slow_rma.3253800673 |
| Short name | T1004 |
| Test name | |
| Test status | |
| Simulation time | 5089390636 ps |
| CPU time | 690.17 seconds |
| Started | Aug 13 07:32:41 PM PDT 24 |
| Finished | Aug 13 07:44:12 PM PDT 24 |
| Peak memory | 614924 kb |
| Host | smart-67650291-f040-46c5-b97b-22a07d130681 |
| User | root |
| Command | /workspace/default/simv +chip_clock_source=ChipClockSourceExternal48Mhz +calibrate_usb_clk=1 +src_dec_state=DecLcStRma +sw_build_device=sim_dv +sw_ima ges=clkmgr_external_clk_src_for_sw_slow_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3253800673 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ =chip_sw_lc_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_c lkmgr_external_clk_src_for_sw_slow_rma.3253800673 |
| Directory | /workspace/2.chip_sw_clkmgr_external_clk_src_for_sw_slow_rma/latest |
| Test location | /workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0.1635477154 |
| Short name | T124 |
| Test name | |
| Test status | |
| Simulation time | 3965683116 ps |
| CPU time | 596.79 seconds |
| Started | Aug 13 07:28:44 PM PDT 24 |
| Finished | Aug 13 07:38:41 PM PDT 24 |
| Peak memory | 614868 kb |
| Host | smart-c4840f25-401d-47f2-be0b-434cdf35980b |
| User | root |
| Command | /workspace/default/simv +chip_clock_source=ChipClockSourceExternal48Mhz +calibrate_usb_clk=1 +src_dec_state=DecLcStTestUnlocked0 +sw_build_device=sim_ dv +sw_images=clkmgr_external_clk_src_for_sw_slow_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1635477154 -assert nopostproc +UVM_TESTNAME=chip_base_test +UV M_TEST_SEQ=chip_sw_lc_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2 .chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0.1635477154 |
| Directory | /workspace/2.chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0/latest |
| Test location | /workspace/coverage/default/2.chip_sw_clkmgr_jitter.3055332959 |
| Short name | T1213 |
| Test name | |
| Test status | |
| Simulation time | 2931410816 ps |
| CPU time | 205.33 seconds |
| Started | Aug 13 07:28:37 PM PDT 24 |
| Finished | Aug 13 07:32:02 PM PDT 24 |
| Peak memory | 610336 kb |
| Host | smart-09fc2f6d-5ad5-4a96-bca2-41c6175f63e5 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=clkmgr_jitter_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3055332959 -assert nopostproc +UVM_TESTNAME =chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 2.chip_sw_clkmgr_jitter.3055332959 |
| Directory | /workspace/2.chip_sw_clkmgr_jitter/latest |
| Test location | /workspace/coverage/default/2.chip_sw_clkmgr_jitter_frequency.3003378913 |
| Short name | T83 |
| Test name | |
| Test status | |
| Simulation time | 3890273720 ps |
| CPU time | 523.58 seconds |
| Started | Aug 13 07:29:20 PM PDT 24 |
| Finished | Aug 13 07:38:04 PM PDT 24 |
| Peak memory | 610404 kb |
| Host | smart-22824936-a7ea-45e7-a3fe-99f29f696d3b |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=clkmgr_jitter_frequency_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3003378913 -assert nopostproc +UV M_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -c m_log /dev/null -cm_name 2.chip_sw_clkmgr_jitter_frequency.3003378913 |
| Directory | /workspace/2.chip_sw_clkmgr_jitter_frequency/latest |
| Test location | /workspace/coverage/default/2.chip_sw_clkmgr_jitter_reduced_freq.2618064420 |
| Short name | T1115 |
| Test name | |
| Test status | |
| Simulation time | 2551816738 ps |
| CPU time | 185.22 seconds |
| Started | Aug 13 07:30:49 PM PDT 24 |
| Finished | Aug 13 07:33:55 PM PDT 24 |
| Peak memory | 610448 kb |
| Host | smart-11547807-ae5f-49cc-bc1d-af82d0dbf2f6 |
| User | root |
| Command | /workspace/default/simv +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=clkmgr_jitter_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2618064420 -assert nop ostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def ault.vdb -cm_log /dev/null -cm_name 2.chip_sw_clkmgr_jitter_reduced_freq.2618064420 |
| Directory | /workspace/2.chip_sw_clkmgr_jitter_reduced_freq/latest |
| Test location | /workspace/coverage/default/2.chip_sw_clkmgr_off_aes_trans.3939065822 |
| Short name | T414 |
| Test name | |
| Test status | |
| Simulation time | 5084560268 ps |
| CPU time | 458.7 seconds |
| Started | Aug 13 07:29:37 PM PDT 24 |
| Finished | Aug 13 07:37:15 PM PDT 24 |
| Peak memory | 610924 kb |
| Host | smart-7a3b5541-bc92-4f1e-b524-e158b4c3299b |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=clkmgr_off_aes_trans_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3939065822 -assert nopostproc +UVM_T ESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l og /dev/null -cm_name 2.chip_sw_clkmgr_off_aes_trans.3939065822 |
| Directory | /workspace/2.chip_sw_clkmgr_off_aes_trans/latest |
| Test location | /workspace/coverage/default/2.chip_sw_clkmgr_off_hmac_trans.97405227 |
| Short name | T1361 |
| Test name | |
| Test status | |
| Simulation time | 4597562076 ps |
| CPU time | 542.38 seconds |
| Started | Aug 13 07:32:23 PM PDT 24 |
| Finished | Aug 13 07:41:26 PM PDT 24 |
| Peak memory | 611136 kb |
| Host | smart-77c0f442-cca4-406f-bb7d-c030c65c9a37 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=clkmgr_off_hmac_trans_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=97405227 -assert nopostproc +UVM_TE STNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_lo g /dev/null -cm_name 2.chip_sw_clkmgr_off_hmac_trans.97405227 |
| Directory | /workspace/2.chip_sw_clkmgr_off_hmac_trans/latest |
| Test location | /workspace/coverage/default/2.chip_sw_clkmgr_off_kmac_trans.1596218022 |
| Short name | T1219 |
| Test name | |
| Test status | |
| Simulation time | 3511606800 ps |
| CPU time | 485.89 seconds |
| Started | Aug 13 07:32:39 PM PDT 24 |
| Finished | Aug 13 07:40:45 PM PDT 24 |
| Peak memory | 610852 kb |
| Host | smart-efaf9f98-cc47-42ef-88c6-026e191579fd |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=clkmgr_off_kmac_trans_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1596218022 -assert nopostproc +UVM_ TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_ log /dev/null -cm_name 2.chip_sw_clkmgr_off_kmac_trans.1596218022 |
| Directory | /workspace/2.chip_sw_clkmgr_off_kmac_trans/latest |
| Test location | /workspace/coverage/default/2.chip_sw_clkmgr_off_otbn_trans.1922807985 |
| Short name | T951 |
| Test name | |
| Test status | |
| Simulation time | 4899931678 ps |
| CPU time | 616.32 seconds |
| Started | Aug 13 07:29:38 PM PDT 24 |
| Finished | Aug 13 07:39:55 PM PDT 24 |
| Peak memory | 611184 kb |
| Host | smart-5f98586e-2c4b-4a38-83ec-14629b99a627 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=clkmgr_off_otbn_trans_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1922807985 -assert nopostproc +UVM_ TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_ log /dev/null -cm_name 2.chip_sw_clkmgr_off_otbn_trans.1922807985 |
| Directory | /workspace/2.chip_sw_clkmgr_off_otbn_trans/latest |
| Test location | /workspace/coverage/default/2.chip_sw_clkmgr_off_peri.3719006256 |
| Short name | T1348 |
| Test name | |
| Test status | |
| Simulation time | 10004810336 ps |
| CPU time | 1296.55 seconds |
| Started | Aug 13 07:30:50 PM PDT 24 |
| Finished | Aug 13 07:52:27 PM PDT 24 |
| Peak memory | 611280 kb |
| Host | smart-f3003dc5-5461-4703-bd67-1e350665bfdf |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=30_000_000 +sw_build_device=sim_dv +sw_images=clkmgr_off_peri_test:1:new_rules,test_rom:0 +cdc_instrumenta tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3719006256 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/ coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_clkmgr_off_peri.3719006256 |
| Directory | /workspace/2.chip_sw_clkmgr_off_peri/latest |
| Test location | /workspace/coverage/default/2.chip_sw_clkmgr_reset_frequency.1765037672 |
| Short name | T1326 |
| Test name | |
| Test status | |
| Simulation time | 3896671800 ps |
| CPU time | 345.01 seconds |
| Started | Aug 13 07:33:11 PM PDT 24 |
| Finished | Aug 13 07:38:56 PM PDT 24 |
| Peak memory | 610656 kb |
| Host | smart-4cb9e602-71cf-40d4-bb1a-bf44d4dadfc5 |
| User | root |
| Command | /workspace/default/simv +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=clkmgr_reset_frequency_test:1:new_rules,test_rom:0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1765037672 -a ssert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov erage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_clkmgr_reset_frequency.1765037672 |
| Directory | /workspace/2.chip_sw_clkmgr_reset_frequency/latest |
| Test location | /workspace/coverage/default/2.chip_sw_clkmgr_sleep_frequency.2521909787 |
| Short name | T1029 |
| Test name | |
| Test status | |
| Simulation time | 5157697820 ps |
| CPU time | 771.84 seconds |
| Started | Aug 13 07:32:21 PM PDT 24 |
| Finished | Aug 13 07:45:13 PM PDT 24 |
| Peak memory | 611064 kb |
| Host | smart-ea56b5b7-c73d-40a5-8c11-c91de80aecb5 |
| User | root |
| Command | /workspace/default/simv +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=clkmgr_sleep_frequency_test:1:new_rules,test_rom:0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2521909787 -a ssert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov erage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_clkmgr_sleep_frequency.2521909787 |
| Directory | /workspace/2.chip_sw_clkmgr_sleep_frequency/latest |
| Test location | /workspace/coverage/default/2.chip_sw_clkmgr_smoketest.1267266279 |
| Short name | T1276 |
| Test name | |
| Test status | |
| Simulation time | 2859446184 ps |
| CPU time | 301.24 seconds |
| Started | Aug 13 07:31:14 PM PDT 24 |
| Finished | Aug 13 07:36:15 PM PDT 24 |
| Peak memory | 610068 kb |
| Host | smart-9dc5bae0-0751-4b01-9674-52a9211ba739 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=clkmgr_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1267266279 -assert nopostproc +UVM_TESTNAME=c hip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n ull -cm_name 2.chip_sw_clkmgr_smoketest.1267266279 |
| Directory | /workspace/2.chip_sw_clkmgr_smoketest/latest |
| Test location | /workspace/coverage/default/2.chip_sw_csrng_edn_concurrency.3422333808 |
| Short name | T1184 |
| Test name | |
| Test status | |
| Simulation time | 17760333640 ps |
| CPU time | 4030.77 seconds |
| Started | Aug 13 07:30:57 PM PDT 24 |
| Finished | Aug 13 08:38:08 PM PDT 24 |
| Peak memory | 611092 kb |
| Host | smart-29455e77-71f4-46ec-82d8-ab92b6065ce9 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=140_000_000 +rng_srate_value_min=15 +rng_srate_value_max=20 +accelerate_cold_power_up_time=3 +accelerate_r egulators_power_up_time=2 +sw_build_device=sim_dv +sw_images=csrng_edn_concurrency_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3422333808 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd b -cm_log /dev/null -cm_name 2.chip_sw_csrng_edn_concurrency.3422333808 |
| Directory | /workspace/2.chip_sw_csrng_edn_concurrency/latest |
| Test location | /workspace/coverage/default/2.chip_sw_csrng_edn_concurrency_reduced_freq.2097299864 |
| Short name | T114 |
| Test name | |
| Test status | |
| Simulation time | 24382391209 ps |
| CPU time | 3922.47 seconds |
| Started | Aug 13 07:33:03 PM PDT 24 |
| Finished | Aug 13 08:38:26 PM PDT 24 |
| Peak memory | 611040 kb |
| Host | smart-39e36bbf-d974-41cb-81eb-49d4c037d19e |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=360_000_000 +rng_srate_value_min=15 +rng_srate_value_max=20 +cal_sys_clk_70mhz=1 +en_jitter=1 +accelerate_ cold_power_up_time=3 +accelerate_regulators_power_up_time=2 +sw_build_device=sim_dv +sw_images=csrng_edn_concurrency_test:1:new_rules,test_rom:0 + cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_ seed=2097299864 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_csrng_edn_concurrency_reduced_freq.2097299864 |
| Directory | /workspace/2.chip_sw_csrng_edn_concurrency_reduced_freq/latest |
| Test location | /workspace/coverage/default/2.chip_sw_csrng_fuse_en_sw_app_read_test.2599748953 |
| Short name | T196 |
| Test name | |
| Test status | |
| Simulation time | 3873197140 ps |
| CPU time | 609.67 seconds |
| Started | Aug 13 07:28:02 PM PDT 24 |
| Finished | Aug 13 07:38:12 PM PDT 24 |
| Peak memory | 609972 kb |
| Host | smart-0e833a7c-d787-4da7-9041-34305e707212 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=15_000_000 +sw_build_device=sim_dv +sw_images=csrng_fuse_en_sw_app_read:1:new_rules,test_rom:0 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25997 48953 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_entropy_src_fuse_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_csrng_fuse_en_sw_app_read_test.2599748953 |
| Directory | /workspace/2.chip_sw_csrng_fuse_en_sw_app_read_test/latest |
| Test location | /workspace/coverage/default/2.chip_sw_csrng_kat_test.3072464420 |
| Short name | T1070 |
| Test name | |
| Test status | |
| Simulation time | 2937094820 ps |
| CPU time | 198.69 seconds |
| Started | Aug 13 07:27:53 PM PDT 24 |
| Finished | Aug 13 07:31:13 PM PDT 24 |
| Peak memory | 610352 kb |
| Host | smart-d741b4fd-689a-4c0b-a618-c73ad4169d50 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=csrng_kat_test:1:new_rules,test_rom:0 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3072464420 -asse rt nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera ge/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_csrng_kat_test.3072464420 |
| Directory | /workspace/2.chip_sw_csrng_kat_test/latest |
| Test location | /workspace/coverage/default/2.chip_sw_csrng_lc_hw_debug_en_test.2877215733 |
| Short name | T126 |
| Test name | |
| Test status | |
| Simulation time | 8306308258 ps |
| CPU time | 726.97 seconds |
| Started | Aug 13 07:37:24 PM PDT 24 |
| Finished | Aug 13 07:49:31 PM PDT 24 |
| Peak memory | 611296 kb |
| Host | smart-2080eaa9-3bb9-4260-ad85-289bc319d6fc |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=15_000_000 +rng_srate_value_min=15 +use_otp_image=OtpTypeLcStTestUnlocked0 +sw_build_device=sim_dv +sw_ima ges=csrng_lc_hw_debug_en_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2877215733 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_csrng_ lc_hw_debug_en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_csr ng_lc_hw_debug_en_test.2877215733 |
| Directory | /workspace/2.chip_sw_csrng_lc_hw_debug_en_test/latest |
| Test location | /workspace/coverage/default/2.chip_sw_csrng_smoketest.2623474568 |
| Short name | T961 |
| Test name | |
| Test status | |
| Simulation time | 2733930482 ps |
| CPU time | 377.33 seconds |
| Started | Aug 13 07:30:31 PM PDT 24 |
| Finished | Aug 13 07:36:49 PM PDT 24 |
| Peak memory | 610400 kb |
| Host | smart-3126f379-5424-4318-8322-f961df6ce297 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=csrng_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2623474568 -assert nopostproc +UVM_TESTNAME=ch ip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu ll -cm_name 2.chip_sw_csrng_smoketest.2623474568 |
| Directory | /workspace/2.chip_sw_csrng_smoketest/latest |
| Test location | /workspace/coverage/default/2.chip_sw_data_integrity_escalation.2594186634 |
| Short name | T284 |
| Test name | |
| Test status | |
| Simulation time | 5970348100 ps |
| CPU time | 929.73 seconds |
| Started | Aug 13 07:22:18 PM PDT 24 |
| Finished | Aug 13 07:37:48 PM PDT 24 |
| Peak memory | 611852 kb |
| Host | smart-488e8905-1d3e-41af-bb52-638d2c2ecdb1 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=data_integrity_escalation_reset_test:1:new_rules,test_ro m:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=2594186634 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_data_integrity_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_data_integrity_escalation.2594186634 |
| Directory | /workspace/2.chip_sw_data_integrity_escalation/latest |
| Test location | /workspace/coverage/default/2.chip_sw_edn_auto_mode.3368589067 |
| Short name | T127 |
| Test name | |
| Test status | |
| Simulation time | 6626619752 ps |
| CPU time | 1951.03 seconds |
| Started | Aug 13 07:37:15 PM PDT 24 |
| Finished | Aug 13 08:09:47 PM PDT 24 |
| Peak memory | 610896 kb |
| Host | smart-b71fd212-ed15-44dd-91db-316948a53f69 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +rng_srate_value=5 +accelerate_cold_power_up_time=3 +accelerate_regulators_power_up_time=2 +sw_ build_device=sim_dv +sw_images=edn_auto_mode:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3368589067 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ =chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_edn_ auto_mode.3368589067 |
| Directory | /workspace/2.chip_sw_edn_auto_mode/latest |
| Test location | /workspace/coverage/default/2.chip_sw_edn_boot_mode.2536155309 |
| Short name | T719 |
| Test name | |
| Test status | |
| Simulation time | 3386683508 ps |
| CPU time | 637.15 seconds |
| Started | Aug 13 07:27:23 PM PDT 24 |
| Finished | Aug 13 07:38:00 PM PDT 24 |
| Peak memory | 610772 kb |
| Host | smart-14cb7751-874f-4adc-bd51-7177d2dbeb0b |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +rng_srate_value=5 +accelerate_cold_power_up_time=3 +accelerate_regulators_power_up_time=2 +sw_ build_device=sim_dv +sw_images=edn_boot_mode:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2536155309 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ =chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_edn_ boot_mode.2536155309 |
| Directory | /workspace/2.chip_sw_edn_boot_mode/latest |
| Test location | /workspace/coverage/default/2.chip_sw_edn_entropy_reqs.1361943747 |
| Short name | T1388 |
| Test name | |
| Test status | |
| Simulation time | 6911513480 ps |
| CPU time | 1169.29 seconds |
| Started | Aug 13 07:29:12 PM PDT 24 |
| Finished | Aug 13 07:48:42 PM PDT 24 |
| Peak memory | 611388 kb |
| Host | smart-1e366a3c-a028-4711-8b6e-f23225e9ebe5 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=15000000 +rng_srate_value_min=15 +rng_srate_value_max=30 +sw_build_device=sim_dv +sw_images=entropy_src_ed n_reqs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1361943747 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_edn_entropy_reqs.1361943747 |
| Directory | /workspace/2.chip_sw_edn_entropy_reqs/latest |
| Test location | /workspace/coverage/default/2.chip_sw_edn_entropy_reqs_jitter.3630582585 |
| Short name | T1372 |
| Test name | |
| Test status | |
| Simulation time | 6561519621 ps |
| CPU time | 1346.02 seconds |
| Started | Aug 13 07:27:36 PM PDT 24 |
| Finished | Aug 13 07:50:03 PM PDT 24 |
| Peak memory | 610408 kb |
| Host | smart-9ef8aa4b-cbaf-4578-8d45-7e5bd9039b34 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=15000000 +rng_srate_value_min=15 +rng_srate_value_max=30 +en_jitter=1 +sw_build_device=sim_dv +sw_images=e ntropy_src_edn_reqs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3630582585 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_edn_entropy_reqs_jitter.3630582585 |
| Directory | /workspace/2.chip_sw_edn_entropy_reqs_jitter/latest |
| Test location | /workspace/coverage/default/2.chip_sw_edn_kat.699075592 |
| Short name | T1358 |
| Test name | |
| Test status | |
| Simulation time | 3062955312 ps |
| CPU time | 769.21 seconds |
| Started | Aug 13 07:28:42 PM PDT 24 |
| Finished | Aug 13 07:41:33 PM PDT 24 |
| Peak memory | 617276 kb |
| Host | smart-a6750f7c-1c25-49bc-9cae-cd6fdc23fcc7 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +rng_srate_value=5 +disable_assert_edn_output_diff_from_prev=1 +accelerate_cold_power_up_time=3 +accelerate_regulators_power_up_time=2 +sw_build_device=sim_dv +sw_images=edn_kat:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=699075592 -assert nopostproc +UVM_ TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_ log /dev/null -cm_name 2.chip_sw_edn_kat.699075592 |
| Directory | /workspace/2.chip_sw_edn_kat/latest |
| Test location | /workspace/coverage/default/2.chip_sw_edn_sw_mode.2527845505 |
| Short name | T300 |
| Test name | |
| Test status | |
| Simulation time | 10201625078 ps |
| CPU time | 2072.11 seconds |
| Started | Aug 13 07:28:46 PM PDT 24 |
| Finished | Aug 13 08:03:18 PM PDT 24 |
| Peak memory | 610356 kb |
| Host | smart-4c2b0a37-5d05-4d5b-92e5-bd54126856d2 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=edn_sw_mode:1:new_rules,test_rom:0 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2527845505 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/ default.vdb -cm_log /dev/null -cm_name 2.chip_sw_edn_sw_mode.2527845505 |
| Directory | /workspace/2.chip_sw_edn_sw_mode/latest |
| Test location | /workspace/coverage/default/2.chip_sw_entropy_src_ast_rng_req.2195380562 |
| Short name | T412 |
| Test name | |
| Test status | |
| Simulation time | 2898327580 ps |
| CPU time | 286.05 seconds |
| Started | Aug 13 07:28:06 PM PDT 24 |
| Finished | Aug 13 07:32:52 PM PDT 24 |
| Peak memory | 610432 kb |
| Host | smart-fdef64b4-19ca-4ff7-95a7-85d5e8e58462 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=15_000_000 +sw_build_device=sim_dv +sw_images=entropy_src_ast_rng_req_test:1:new_rules,test_rom:0 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21 95380562 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_entropy_src_ast_rng_req.2195380562 |
| Directory | /workspace/2.chip_sw_entropy_src_ast_rng_req/latest |
| Test location | /workspace/coverage/default/2.chip_sw_entropy_src_csrng.2898807296 |
| Short name | T334 |
| Test name | |
| Test status | |
| Simulation time | 7944550936 ps |
| CPU time | 1635.51 seconds |
| Started | Aug 13 07:28:11 PM PDT 24 |
| Finished | Aug 13 07:55:27 PM PDT 24 |
| Peak memory | 609728 kb |
| Host | smart-5588eb41-bb82-40a2-9e5c-cbabfbd4cefc |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=50_000_000 +rng_srate_value_min=15 +rng_srate_value_max=30 +sw_build_device=sim_dv +sw_images=entropy_src_ csrng_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2898807296 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_entropy_src_csrng.2898807296 |
| Directory | /workspace/2.chip_sw_entropy_src_csrng/latest |
| Test location | /workspace/coverage/default/2.chip_sw_entropy_src_kat_test.1624442395 |
| Short name | T1300 |
| Test name | |
| Test status | |
| Simulation time | 3284764808 ps |
| CPU time | 223.76 seconds |
| Started | Aug 13 07:28:18 PM PDT 24 |
| Finished | Aug 13 07:32:02 PM PDT 24 |
| Peak memory | 610228 kb |
| Host | smart-07e4f9bf-797c-4701-94ab-0672ccc2e36b |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=entropy_src_kat_test:1:new_rules,test_rom:0 +cdc_instrumenta tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1624442395 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/ coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_entropy_src_kat_test.1624442395 |
| Directory | /workspace/2.chip_sw_entropy_src_kat_test/latest |
| Test location | /workspace/coverage/default/2.chip_sw_entropy_src_smoketest.545804580 |
| Short name | T1369 |
| Test name | |
| Test status | |
| Simulation time | 3232664684 ps |
| CPU time | 421.7 seconds |
| Started | Aug 13 07:31:02 PM PDT 24 |
| Finished | Aug 13 07:38:04 PM PDT 24 |
| Peak memory | 610544 kb |
| Host | smart-8e49aa22-293f-4bc7-ba8d-d7f1f027d38c |
| User | root |
| Command | /workspace/default/simv +rng_srate_value_min=15 +rng_srate_value_max=30 +sw_build_device=sim_dv +sw_images=entropy_src_smoketest:1:new_rules,test_rom: 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand om_seed=545804580 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_entropy_src_smoketest.545804580 |
| Directory | /workspace/2.chip_sw_entropy_src_smoketest/latest |
| Test location | /workspace/coverage/default/2.chip_sw_example_concurrency.4197275431 |
| Short name | T998 |
| Test name | |
| Test status | |
| Simulation time | 3100754214 ps |
| CPU time | 250.54 seconds |
| Started | Aug 13 07:26:57 PM PDT 24 |
| Finished | Aug 13 07:31:10 PM PDT 24 |
| Peak memory | 610364 kb |
| Host | smart-b7e7beb8-593f-43b6-873f-0b5920c40255 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=example_concurrency_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4197275431 -assert nopostproc +UVM_TE STNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_lo g /dev/null -cm_name 2.chip_sw_example_concurrency.4197275431 |
| Directory | /workspace/2.chip_sw_example_concurrency/latest |
| Test location | /workspace/coverage/default/2.chip_sw_example_flash.1581459024 |
| Short name | T990 |
| Test name | |
| Test status | |
| Simulation time | 3052317614 ps |
| CPU time | 243.1 seconds |
| Started | Aug 13 07:21:54 PM PDT 24 |
| Finished | Aug 13 07:25:57 PM PDT 24 |
| Peak memory | 610344 kb |
| Host | smart-cf3ae0c4-f4f4-49ab-822b-c2780d76509c |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=example_test_from_flash:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1581459024 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_example_flash.1581459024 |
| Directory | /workspace/2.chip_sw_example_flash/latest |
| Test location | /workspace/coverage/default/2.chip_sw_example_manufacturer.3125883791 |
| Short name | T1164 |
| Test name | |
| Test status | |
| Simulation time | 2834612302 ps |
| CPU time | 237.55 seconds |
| Started | Aug 13 07:23:47 PM PDT 24 |
| Finished | Aug 13 07:27:44 PM PDT 24 |
| Peak memory | 610416 kb |
| Host | smart-c6210df2-288f-41f0-b39a-2499462784cd |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=example_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3125883791 -assert nopostproc +UVM_TESTNAME=chip_ base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_example_manufacturer.3125883791 |
| Directory | /workspace/2.chip_sw_example_manufacturer/latest |
| Test location | /workspace/coverage/default/2.chip_sw_example_rom.715030324 |
| Short name | T297 |
| Test name | |
| Test status | |
| Simulation time | 2531122404 ps |
| CPU time | 116.42 seconds |
| Started | Aug 13 07:22:01 PM PDT 24 |
| Finished | Aug 13 07:23:57 PM PDT 24 |
| Peak memory | 610004 kb |
| Host | smart-c210cbdb-5a8f-434e-b621-66fd3dcc5f2d |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=example_test_from_rom:0:test_in_rom:new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=715030324 -assert nopostproc +UVM_TESTN AME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log / dev/null -cm_name 2.chip_sw_example_rom.715030324 |
| Directory | /workspace/2.chip_sw_example_rom/latest |
| Test location | /workspace/coverage/default/2.chip_sw_flash_crash_alert.661535036 |
| Short name | T1038 |
| Test name | |
| Test status | |
| Simulation time | 5255341918 ps |
| CPU time | 699.17 seconds |
| Started | Aug 13 07:29:56 PM PDT 24 |
| Finished | Aug 13 07:41:35 PM PDT 24 |
| Peak memory | 611864 kb |
| Host | smart-3108b8a8-1727-463a-9e74-cfc8f39e6878 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=8_000_000 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1: new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tool s/sim.tcl +ntb_random_seed=661535036 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_flash_host_gnt_err_inj_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_flash_crash_alert.661535036 |
| Directory | /workspace/2.chip_sw_flash_crash_alert/latest |
| Test location | /workspace/coverage/default/2.chip_sw_flash_ctrl_access.3354377594 |
| Short name | T1171 |
| Test name | |
| Test status | |
| Simulation time | 5626192300 ps |
| CPU time | 1038.01 seconds |
| Started | Aug 13 07:24:32 PM PDT 24 |
| Finished | Aug 13 07:41:51 PM PDT 24 |
| Peak memory | 610412 kb |
| Host | smart-db338d2a-b98c-4e29-aacd-3fb172fe0a5d |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=flash_ctrl_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3354377594 -assert nopostproc +UVM_TESTNAME=ch ip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu ll -cm_name 2.chip_sw_flash_ctrl_access.3354377594 |
| Directory | /workspace/2.chip_sw_flash_ctrl_access/latest |
| Test location | /workspace/coverage/default/2.chip_sw_flash_ctrl_access_jitter_en.1792648665 |
| Short name | T107 |
| Test name | |
| Test status | |
| Simulation time | 5568497552 ps |
| CPU time | 1031.99 seconds |
| Started | Aug 13 07:24:57 PM PDT 24 |
| Finished | Aug 13 07:42:09 PM PDT 24 |
| Peak memory | 610744 kb |
| Host | smart-9fde2f66-f9ce-4889-b0ad-0a6552c81d53 |
| User | root |
| Command | /workspace/default/simv +en_jitter=1 +sw_build_device=sim_dv +sw_images=flash_ctrl_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1792648665 -assert nopostproc +UV M_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -c m_log /dev/null -cm_name 2.chip_sw_flash_ctrl_access_jitter_en.1792648665 |
| Directory | /workspace/2.chip_sw_flash_ctrl_access_jitter_en/latest |
| Test location | /workspace/coverage/default/2.chip_sw_flash_ctrl_access_jitter_en_reduced_freq.3844104871 |
| Short name | T948 |
| Test name | |
| Test status | |
| Simulation time | 7192853849 ps |
| CPU time | 1329.4 seconds |
| Started | Aug 13 07:30:18 PM PDT 24 |
| Finished | Aug 13 07:52:27 PM PDT 24 |
| Peak memory | 610836 kb |
| Host | smart-7c47b401-d68d-420b-ba36-a5f016505831 |
| User | root |
| Command | /workspace/default/simv +en_jitter=1 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=flash_ctrl_test:1:new_rules,test_rom:0 +cdc_instrumentati on_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3844104871 - assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co verage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_flash_ctrl_access_jitter_en_reduced_freq.3844104871 |
| Directory | /workspace/2.chip_sw_flash_ctrl_access_jitter_en_reduced_freq/latest |
| Test location | /workspace/coverage/default/2.chip_sw_flash_ctrl_clock_freqs.151987931 |
| Short name | T1234 |
| Test name | |
| Test status | |
| Simulation time | 5703888803 ps |
| CPU time | 1184.58 seconds |
| Started | Aug 13 07:25:18 PM PDT 24 |
| Finished | Aug 13 07:45:03 PM PDT 24 |
| Peak memory | 610780 kb |
| Host | smart-ef19e463-13c2-44c6-adcb-727890654316 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=flash_ctrl_clock_freqs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=151987931 -assert nopostproc +UVM_ TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_ log /dev/null -cm_name 2.chip_sw_flash_ctrl_clock_freqs.151987931 |
| Directory | /workspace/2.chip_sw_flash_ctrl_clock_freqs/latest |
| Test location | /workspace/coverage/default/2.chip_sw_flash_ctrl_idle_low_power.3127561750 |
| Short name | T1154 |
| Test name | |
| Test status | |
| Simulation time | 3049916400 ps |
| CPU time | 376.8 seconds |
| Started | Aug 13 07:26:31 PM PDT 24 |
| Finished | Aug 13 07:32:48 PM PDT 24 |
| Peak memory | 610676 kb |
| Host | smart-459bd6eb-f531-4a43-8150-4b359f65c5ca |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=flash_ctrl_idle_low_power_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3127561750 -assert nopostproc + UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_flash_ctrl_idle_low_power.3127561750 |
| Directory | /workspace/2.chip_sw_flash_ctrl_idle_low_power/latest |
| Test location | /workspace/coverage/default/2.chip_sw_flash_ctrl_mem_protection.3758175077 |
| Short name | T1225 |
| Test name | |
| Test status | |
| Simulation time | 5877607304 ps |
| CPU time | 1088.67 seconds |
| Started | Aug 13 07:30:05 PM PDT 24 |
| Finished | Aug 13 07:48:14 PM PDT 24 |
| Peak memory | 610484 kb |
| Host | smart-315f9172-53d6-471c-91c6-03ac13b930cb |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=flash_ctrl_mem_protection_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3758175077 -assert nopostproc + UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_flash_ctrl_mem_protection.3758175077 |
| Directory | /workspace/2.chip_sw_flash_ctrl_mem_protection/latest |
| Test location | /workspace/coverage/default/2.chip_sw_flash_ctrl_ops.2574315741 |
| Short name | T1120 |
| Test name | |
| Test status | |
| Simulation time | 4389119922 ps |
| CPU time | 754.93 seconds |
| Started | Aug 13 07:26:07 PM PDT 24 |
| Finished | Aug 13 07:38:43 PM PDT 24 |
| Peak memory | 610920 kb |
| Host | smart-ba2b2151-24b1-4d40-89a4-78ca923850ae |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=50_000_000 +sw_build_device=sim_dv +sw_images=flash_ctrl_ops_test:1:new_rules,test_rom:0 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2574315741 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/c overage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_flash_ctrl_ops.2574315741 |
| Directory | /workspace/2.chip_sw_flash_ctrl_ops/latest |
| Test location | /workspace/coverage/default/2.chip_sw_flash_ctrl_ops_jitter_en.4027334294 |
| Short name | T370 |
| Test name | |
| Test status | |
| Simulation time | 4260012696 ps |
| CPU time | 774.17 seconds |
| Started | Aug 13 07:24:35 PM PDT 24 |
| Finished | Aug 13 07:37:30 PM PDT 24 |
| Peak memory | 610420 kb |
| Host | smart-731098e6-6348-4d35-8e25-3c556040a624 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=50_000_000 +en_jitter=1 +sw_build_device=sim_dv +sw_images=flash_ctrl_ops_test:1:new_rules,test_rom:0 +cdc _instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see d=4027334294 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_flash_ctrl_ops_jitter_en.4027334294 |
| Directory | /workspace/2.chip_sw_flash_ctrl_ops_jitter_en/latest |
| Test location | /workspace/coverage/default/2.chip_sw_flash_ctrl_ops_jitter_en_reduced_freq.1890527332 |
| Short name | T350 |
| Test name | |
| Test status | |
| Simulation time | 4618222328 ps |
| CPU time | 619.58 seconds |
| Started | Aug 13 07:29:49 PM PDT 24 |
| Finished | Aug 13 07:40:09 PM PDT 24 |
| Peak memory | 610920 kb |
| Host | smart-c7fb8e16-ec3d-4793-984e-17e0a7db5d44 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=50_000_000 +en_jitter=1 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=flash_ctrl_ops_test:1:new_ rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si m.tcl +ntb_random_seed=1890527332 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_flash_ctrl_ops_jitter_en_reduced_freq.1890527332 |
| Directory | /workspace/2.chip_sw_flash_ctrl_ops_jitter_en_reduced_freq/latest |
| Test location | /workspace/coverage/default/2.chip_sw_flash_ctrl_write_clear.1484245253 |
| Short name | T1041 |
| Test name | |
| Test status | |
| Simulation time | 3030761900 ps |
| CPU time | 406.17 seconds |
| Started | Aug 13 07:31:11 PM PDT 24 |
| Finished | Aug 13 07:37:57 PM PDT 24 |
| Peak memory | 610460 kb |
| Host | smart-bb800e6c-4dfb-45e3-ab89-5d87e015ad5e |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=8_000_000 +sw_build_device=sim_dv +sw_images=flash_ctrl_write_clear_test:1:new_rules,test_rom:0 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1484245 253 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ce/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_flash_ctrl_write_clear.1484245253 |
| Directory | /workspace/2.chip_sw_flash_ctrl_write_clear/latest |
| Test location | /workspace/coverage/default/2.chip_sw_flash_init.3151469642 |
| Short name | T239 |
| Test name | |
| Test status | |
| Simulation time | 20688553046 ps |
| CPU time | 1864.81 seconds |
| Started | Aug 13 07:23:08 PM PDT 24 |
| Finished | Aug 13 07:54:14 PM PDT 24 |
| Peak memory | 613492 kb |
| Host | smart-89d66295-e4c5-4db0-b73b-1f5bc85fbb84 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=25_000_000 +sw_build_device=sim_dv +sw_images=flash_init_test:0:test_in_rom:new_rules +cdc_instrumentation _enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3151469642 -as sert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_flash_init_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac e/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_flash_init.3151469642 |
| Directory | /workspace/2.chip_sw_flash_init/latest |
| Test location | /workspace/coverage/default/2.chip_sw_flash_scrambling_smoketest.4013716596 |
| Short name | T398 |
| Test name | |
| Test status | |
| Simulation time | 3356402384 ps |
| CPU time | 320.08 seconds |
| Started | Aug 13 07:36:04 PM PDT 24 |
| Finished | Aug 13 07:41:24 PM PDT 24 |
| Peak memory | 609900 kb |
| Host | smart-8e9cc4d6-91c3-47a1-8e29-e54262c6c5f3 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=flash_scrambling_smoketest:1:new_rules,flash_scrambling_smoket est_otp_img_rma:4,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=4013716596 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_flash_scrambling_smoketest.4013716596 |
| Directory | /workspace/2.chip_sw_flash_scrambling_smoketest/latest |
| Test location | /workspace/coverage/default/2.chip_sw_gpio_smoketest.1140938762 |
| Short name | T24 |
| Test name | |
| Test status | |
| Simulation time | 3192894223 ps |
| CPU time | 226.44 seconds |
| Started | Aug 13 07:32:27 PM PDT 24 |
| Finished | Aug 13 07:36:14 PM PDT 24 |
| Peak memory | 610452 kb |
| Host | smart-d8f7e087-0aef-4076-a0bd-ec09b0321675 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=gpio_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1140938762 -assert nopostproc +UVM_TESTNAME=chi p_base_test +UVM_TEST_SEQ=chip_sw_gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 2.chip_sw_gpio_smoketest.1140938762 |
| Directory | /workspace/2.chip_sw_gpio_smoketest/latest |
| Test location | /workspace/coverage/default/2.chip_sw_hmac_enc.625506891 |
| Short name | T371 |
| Test name | |
| Test status | |
| Simulation time | 3035976850 ps |
| CPU time | 241.07 seconds |
| Started | Aug 13 07:28:35 PM PDT 24 |
| Finished | Aug 13 07:32:36 PM PDT 24 |
| Peak memory | 610312 kb |
| Host | smart-c7de87a0-e6d5-42e6-83b2-c27d366e4bba |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=hmac_enc_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=625506891 -assert nopostproc +UVM_TESTNAME=chip_ base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_hmac_enc.625506891 |
| Directory | /workspace/2.chip_sw_hmac_enc/latest |
| Test location | /workspace/coverage/default/2.chip_sw_hmac_enc_idle.386822676 |
| Short name | T1292 |
| Test name | |
| Test status | |
| Simulation time | 2997068982 ps |
| CPU time | 339.59 seconds |
| Started | Aug 13 07:28:43 PM PDT 24 |
| Finished | Aug 13 07:34:23 PM PDT 24 |
| Peak memory | 610352 kb |
| Host | smart-ebf6cf14-c54d-4d1a-88eb-8170315642dd |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=hmac_enc_idle_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=386822676 -assert nopostproc +UVM_TESTNAME= chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/ null -cm_name 2.chip_sw_hmac_enc_idle.386822676 |
| Directory | /workspace/2.chip_sw_hmac_enc_idle/latest |
| Test location | /workspace/coverage/default/2.chip_sw_hmac_enc_jitter_en.2510504404 |
| Short name | T328 |
| Test name | |
| Test status | |
| Simulation time | 2736231407 ps |
| CPU time | 292.48 seconds |
| Started | Aug 13 07:28:36 PM PDT 24 |
| Finished | Aug 13 07:33:29 PM PDT 24 |
| Peak memory | 610524 kb |
| Host | smart-e83581e5-a16e-4de4-b70b-98981365e2ee |
| User | root |
| Command | /workspace/default/simv +en_jitter=1 +sw_build_device=sim_dv +sw_images=hmac_enc_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2510504404 -assert nopostproc +UVM_ TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_ log /dev/null -cm_name 2.chip_sw_hmac_enc_jitter_en.2510504404 |
| Directory | /workspace/2.chip_sw_hmac_enc_jitter_en/latest |
| Test location | /workspace/coverage/default/2.chip_sw_hmac_enc_jitter_en_reduced_freq.2651214394 |
| Short name | T117 |
| Test name | |
| Test status | |
| Simulation time | 3276449639 ps |
| CPU time | 330.22 seconds |
| Started | Aug 13 07:32:09 PM PDT 24 |
| Finished | Aug 13 07:37:39 PM PDT 24 |
| Peak memory | 609220 kb |
| Host | smart-fb4f6146-f9b8-44ba-8d52-ccc5eb750824 |
| User | root |
| Command | /workspace/default/simv +en_jitter=1 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=hmac_enc_test:1:new_rules,test_rom:0 +cdc_instrumentation _enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2651214394 -as sert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove rage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_hmac_enc_jitter_en_reduced_freq.2651214394 |
| Directory | /workspace/2.chip_sw_hmac_enc_jitter_en_reduced_freq/latest |
| Test location | /workspace/coverage/default/2.chip_sw_hmac_multistream.1862287623 |
| Short name | T1082 |
| Test name | |
| Test status | |
| Simulation time | 6924105320 ps |
| CPU time | 1679.94 seconds |
| Started | Aug 13 07:27:56 PM PDT 24 |
| Finished | Aug 13 07:55:57 PM PDT 24 |
| Peak memory | 610572 kb |
| Host | smart-b7d20fe2-cd42-49e6-a7b6-d4b7992b4aca |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=hmac_multistream_functest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1862287623 -assert nopostproc +UVM_T ESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l og /dev/null -cm_name 2.chip_sw_hmac_multistream.1862287623 |
| Directory | /workspace/2.chip_sw_hmac_multistream/latest |
| Test location | /workspace/coverage/default/2.chip_sw_hmac_oneshot.977451904 |
| Short name | T1384 |
| Test name | |
| Test status | |
| Simulation time | 2301231320 ps |
| CPU time | 217.04 seconds |
| Started | Aug 13 07:29:57 PM PDT 24 |
| Finished | Aug 13 07:33:35 PM PDT 24 |
| Peak memory | 608836 kb |
| Host | smart-829cfb36-a520-46b8-82c5-a2c31e3cf287 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=hmac_functest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=977451904 -assert nopostproc +UVM_TESTNAME=chip_ base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_hmac_oneshot.977451904 |
| Directory | /workspace/2.chip_sw_hmac_oneshot/latest |
| Test location | /workspace/coverage/default/2.chip_sw_hmac_smoketest.1977624056 |
| Short name | T1046 |
| Test name | |
| Test status | |
| Simulation time | 3117242872 ps |
| CPU time | 413.15 seconds |
| Started | Aug 13 07:32:01 PM PDT 24 |
| Finished | Aug 13 07:38:54 PM PDT 24 |
| Peak memory | 610456 kb |
| Host | smart-0101147b-51e9-42dc-9293-3b36720c42ef |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=hmac_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1977624056 -assert nopostproc +UVM_TESTNAME=chi p_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul l -cm_name 2.chip_sw_hmac_smoketest.1977624056 |
| Directory | /workspace/2.chip_sw_hmac_smoketest/latest |
| Test location | /workspace/coverage/default/2.chip_sw_i2c_device_tx_rx.2884307202 |
| Short name | T224 |
| Test name | |
| Test status | |
| Simulation time | 4248721818 ps |
| CPU time | 551.79 seconds |
| Started | Aug 13 07:23:07 PM PDT 24 |
| Finished | Aug 13 07:32:20 PM PDT 24 |
| Peak memory | 611028 kb |
| Host | smart-0def84a9-8059-444d-b122-770309827dd9 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=i2c_device_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2884307202 -assert nopostproc +UVM_TESTN AME=chip_base_test +UVM_TEST_SEQ=chip_sw_i2c_device_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v db -cm_log /dev/null -cm_name 2.chip_sw_i2c_device_tx_rx.2884307202 |
| Directory | /workspace/2.chip_sw_i2c_device_tx_rx/latest |
| Test location | /workspace/coverage/default/2.chip_sw_i2c_host_tx_rx.3232900580 |
| Short name | T342 |
| Test name | |
| Test status | |
| Simulation time | 4618616952 ps |
| CPU time | 898.21 seconds |
| Started | Aug 13 07:23:22 PM PDT 24 |
| Finished | Aug 13 07:38:21 PM PDT 24 |
| Peak memory | 610320 kb |
| Host | smart-02f4ba59-bd84-4a81-8d4d-5f567c4ef7e5 |
| User | root |
| Command | /workspace/default/simv +i2c_idx=0 +sw_build_device=sim_dv +sw_images=i2c_host_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3232900580 -assert nopostproc + UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_i2c_host_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de fault.vdb -cm_log /dev/null -cm_name 2.chip_sw_i2c_host_tx_rx.3232900580 |
| Directory | /workspace/2.chip_sw_i2c_host_tx_rx/latest |
| Test location | /workspace/coverage/default/2.chip_sw_i2c_host_tx_rx_idx1.1557950496 |
| Short name | T289 |
| Test name | |
| Test status | |
| Simulation time | 4602225212 ps |
| CPU time | 819.77 seconds |
| Started | Aug 13 07:25:27 PM PDT 24 |
| Finished | Aug 13 07:39:08 PM PDT 24 |
| Peak memory | 610736 kb |
| Host | smart-e28507c3-0ee6-41c4-9ede-755c41c4682d |
| User | root |
| Command | /workspace/default/simv +i2c_idx=1 +sw_build_device=sim_dv +sw_images=i2c_host_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1557950496 -assert nopostproc + UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_i2c_host_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de fault.vdb -cm_log /dev/null -cm_name 2.chip_sw_i2c_host_tx_rx_idx1.1557950496 |
| Directory | /workspace/2.chip_sw_i2c_host_tx_rx_idx1/latest |
| Test location | /workspace/coverage/default/2.chip_sw_inject_scramble_seed.3576065741 |
| Short name | T1039 |
| Test name | |
| Test status | |
| Simulation time | 63523167434 ps |
| CPU time | 12436.5 seconds |
| Started | Aug 13 07:26:55 PM PDT 24 |
| Finished | Aug 13 10:54:14 PM PDT 24 |
| Peak memory | 625248 kb |
| Host | smart-e9e306ef-111e-41e7-bd32-732244eedf03 |
| User | root |
| Command | /workspace/default/simv +lc_at_prod=1 +flash_program_latency=5 +sw_test_timeout_ns=150_000_000 +sw_build_device=sim_dv +sw_images=inject_scramble_seed :1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=3576065741 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_inject_scramble_seed_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_inject_scramble_seed.3576065741 |
| Directory | /workspace/2.chip_sw_inject_scramble_seed/latest |
| Test location | /workspace/coverage/default/2.chip_sw_keymgr_key_derivation.1269606944 |
| Short name | T409 |
| Test name | |
| Test status | |
| Simulation time | 7642286580 ps |
| CPU time | 1286.58 seconds |
| Started | Aug 13 07:29:23 PM PDT 24 |
| Finished | Aug 13 07:50:50 PM PDT 24 |
| Peak memory | 618416 kb |
| Host | smart-31595cfb-908e-41c6-98e7-6f9530bae850 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=20_000_000 +sw_build_device=sim_dv +sw_images=keymgr_key_derivation_test:1:new_rules,test_rom:0 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1269 606944 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_keymgr_key_derivation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_keymgr_key_derivation.1269606944 |
| Directory | /workspace/2.chip_sw_keymgr_key_derivation/latest |
| Test location | /workspace/coverage/default/2.chip_sw_keymgr_key_derivation_jitter_en.2135269710 |
| Short name | T1147 |
| Test name | |
| Test status | |
| Simulation time | 8027507052 ps |
| CPU time | 769.72 seconds |
| Started | Aug 13 07:30:28 PM PDT 24 |
| Finished | Aug 13 07:43:18 PM PDT 24 |
| Peak memory | 617076 kb |
| Host | smart-6a5a111b-483c-45fa-a36f-595e24ce0cc2 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=20_000_000 +en_jitter=1 +sw_build_device=sim_dv +sw_images=keymgr_key_derivation_test:1:new_rules,test_rom :0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=2135269710 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_keymgr_key_derivation_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_keymgr_key_derivation_jitter_en.2135269710 |
| Directory | /workspace/2.chip_sw_keymgr_key_derivation_jitter_en/latest |
| Test location | /workspace/coverage/default/2.chip_sw_keymgr_key_derivation_jitter_en_reduced_freq.3483231988 |
| Short name | T1414 |
| Test name | |
| Test status | |
| Simulation time | 13317440102 ps |
| CPU time | 1907.63 seconds |
| Started | Aug 13 07:29:55 PM PDT 24 |
| Finished | Aug 13 08:01:43 PM PDT 24 |
| Peak memory | 618812 kb |
| Host | smart-a494596b-98f7-4f00-b834-742dfdfb17e5 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=20_000_000 +en_jitter=1 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=keymgr_key_derivation_test :1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=3483231988 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_keymgr_key_derivation_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_keymgr_key_derivation_jitter_en _reduced_freq.3483231988 |
| Directory | /workspace/2.chip_sw_keymgr_key_derivation_jitter_en_reduced_freq/latest |
| Test location | /workspace/coverage/default/2.chip_sw_keymgr_key_derivation_prod.1247926829 |
| Short name | T129 |
| Test name | |
| Test status | |
| Simulation time | 9452991260 ps |
| CPU time | 1524.35 seconds |
| Started | Aug 13 07:30:27 PM PDT 24 |
| Finished | Aug 13 07:55:52 PM PDT 24 |
| Peak memory | 617096 kb |
| Host | smart-f52e2c6c-d88c-4c89-af61-44fb0ce6da67 |
| User | root |
| Command | /workspace/default/simv +lc_at_prod=1 +sw_test_timeout_ns=20_000_000 +sw_build_device=sim_dv +sw_images=keymgr_key_derivation_test:1:new_rules,test_ro m:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=1247926829 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_keymgr_key_derivation_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_keymgr_key_derivation_prod.1247926829 |
| Directory | /workspace/2.chip_sw_keymgr_key_derivation_prod/latest |
| Test location | /workspace/coverage/default/2.chip_sw_keymgr_sideload_aes.3102911167 |
| Short name | T236 |
| Test name | |
| Test status | |
| Simulation time | 5273710608 ps |
| CPU time | 1020.44 seconds |
| Started | Aug 13 07:28:40 PM PDT 24 |
| Finished | Aug 13 07:45:41 PM PDT 24 |
| Peak memory | 612068 kb |
| Host | smart-8a8cb41f-4174-4204-882a-7b209f908662 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=20_000_000 +sw_build_device=sim_dv +sw_images=keymgr_sideload_aes_test:1:new_rules,test_rom:0 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=310291 1167 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_keymgr_sideload_aes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_keymgr_sideload_aes.3102911167 |
| Directory | /workspace/2.chip_sw_keymgr_sideload_aes/latest |
| Test location | /workspace/coverage/default/2.chip_sw_keymgr_sideload_otbn.756585259 |
| Short name | T238 |
| Test name | |
| Test status | |
| Simulation time | 13424801204 ps |
| CPU time | 3341.31 seconds |
| Started | Aug 13 07:29:43 PM PDT 24 |
| Finished | Aug 13 08:25:24 PM PDT 24 |
| Peak memory | 611608 kb |
| Host | smart-cbe82953-d69a-42d4-b6e9-9d89386e73dd |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=20_000_000 +sw_build_device=sim_dv +sw_images=keymgr_sideload_otbn_test:1:new_rules,test_rom:0 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75658 5259 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_keymgr_sideload_otbn.756585259 |
| Directory | /workspace/2.chip_sw_keymgr_sideload_otbn/latest |
| Test location | /workspace/coverage/default/2.chip_sw_kmac_app_rom.1297804926 |
| Short name | T1035 |
| Test name | |
| Test status | |
| Simulation time | 2875159618 ps |
| CPU time | 316.57 seconds |
| Started | Aug 13 07:29:07 PM PDT 24 |
| Finished | Aug 13 07:34:24 PM PDT 24 |
| Peak memory | 610360 kb |
| Host | smart-fd592b27-1c01-45e9-86a7-10c38ef33ca1 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=kmac_app_rom_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1297804926 -assert nopostproc +UVM_TESTNAME= chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/ null -cm_name 2.chip_sw_kmac_app_rom.1297804926 |
| Directory | /workspace/2.chip_sw_kmac_app_rom/latest |
| Test location | /workspace/coverage/default/2.chip_sw_kmac_entropy.2640414486 |
| Short name | T306 |
| Test name | |
| Test status | |
| Simulation time | 3806008164 ps |
| CPU time | 374.26 seconds |
| Started | Aug 13 07:26:12 PM PDT 24 |
| Finished | Aug 13 07:32:27 PM PDT 24 |
| Peak memory | 610280 kb |
| Host | smart-5ec662dd-af68-4c1d-a6f2-f643fbc2fd97 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=kmac_entropy_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2640414486 -assert nopostproc +UVM_TESTNAME= chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/ null -cm_name 2.chip_sw_kmac_entropy.2640414486 |
| Directory | /workspace/2.chip_sw_kmac_entropy/latest |
| Test location | /workspace/coverage/default/2.chip_sw_kmac_idle.875099865 |
| Short name | T1149 |
| Test name | |
| Test status | |
| Simulation time | 3052666856 ps |
| CPU time | 287.16 seconds |
| Started | Aug 13 07:29:49 PM PDT 24 |
| Finished | Aug 13 07:34:37 PM PDT 24 |
| Peak memory | 610332 kb |
| Host | smart-f8a3c96c-3d72-4f44-baa6-8c8dc51d702e |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=kmac_idle_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=875099865 -assert nopostproc +UVM_TESTNAME=chip _base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_kmac_idle.875099865 |
| Directory | /workspace/2.chip_sw_kmac_idle/latest |
| Test location | /workspace/coverage/default/2.chip_sw_kmac_mode_cshake.519116313 |
| Short name | T1081 |
| Test name | |
| Test status | |
| Simulation time | 3032508752 ps |
| CPU time | 228.33 seconds |
| Started | Aug 13 07:28:42 PM PDT 24 |
| Finished | Aug 13 07:32:31 PM PDT 24 |
| Peak memory | 610432 kb |
| Host | smart-e03e1a09-e4bc-43d8-9c5c-713a805c369a |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=kmac_mode_cshake_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=519116313 -assert nopostproc +UVM_TESTNA ME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 2.chip_sw_kmac_mode_cshake.519116313 |
| Directory | /workspace/2.chip_sw_kmac_mode_cshake/latest |
| Test location | /workspace/coverage/default/2.chip_sw_kmac_mode_kmac.1016666989 |
| Short name | T1368 |
| Test name | |
| Test status | |
| Simulation time | 2892326600 ps |
| CPU time | 295.23 seconds |
| Started | Aug 13 07:29:28 PM PDT 24 |
| Finished | Aug 13 07:34:24 PM PDT 24 |
| Peak memory | 610444 kb |
| Host | smart-06e28e48-27e4-4aab-9220-6ce8ff6f848d |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=kmac_mode_kmac_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1016666989 -assert nopostproc +UVM_TESTNAM E=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 2.chip_sw_kmac_mode_kmac.1016666989 |
| Directory | /workspace/2.chip_sw_kmac_mode_kmac/latest |
| Test location | /workspace/coverage/default/2.chip_sw_kmac_mode_kmac_jitter_en.3034438809 |
| Short name | T1010 |
| Test name | |
| Test status | |
| Simulation time | 2936548368 ps |
| CPU time | 340.05 seconds |
| Started | Aug 13 07:28:03 PM PDT 24 |
| Finished | Aug 13 07:33:44 PM PDT 24 |
| Peak memory | 610360 kb |
| Host | smart-d3a6626c-bdd0-4348-9c3c-ddfaff42454f |
| User | root |
| Command | /workspace/default/simv +en_jitter=1 +sw_build_device=sim_dv +sw_images=kmac_mode_kmac_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3034438809 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd b -cm_log /dev/null -cm_name 2.chip_sw_kmac_mode_kmac_jitter_en.3034438809 |
| Directory | /workspace/2.chip_sw_kmac_mode_kmac_jitter_en/latest |
| Test location | /workspace/coverage/default/2.chip_sw_kmac_mode_kmac_jitter_en_reduced_freq.2626296294 |
| Short name | T1048 |
| Test name | |
| Test status | |
| Simulation time | 3261425406 ps |
| CPU time | 291.57 seconds |
| Started | Aug 13 07:31:14 PM PDT 24 |
| Finished | Aug 13 07:36:06 PM PDT 24 |
| Peak memory | 609192 kb |
| Host | smart-cf2a0d0d-718b-428e-8ecb-b6514a3296a7 |
| User | root |
| Command | /workspace/default/simv +en_jitter=1 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=kmac_mode_kmac_test:1:new_rules,test_rom:0 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26262962 94 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac e/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_kmac_mode_kmac_jitter_en_reduced_freq.2626296294 |
| Directory | /workspace/2.chip_sw_kmac_mode_kmac_jitter_en_reduced_freq/latest |
| Test location | /workspace/coverage/default/2.chip_sw_kmac_smoketest.418501287 |
| Short name | T460 |
| Test name | |
| Test status | |
| Simulation time | 3448179328 ps |
| CPU time | 382.31 seconds |
| Started | Aug 13 07:32:30 PM PDT 24 |
| Finished | Aug 13 07:38:52 PM PDT 24 |
| Peak memory | 610440 kb |
| Host | smart-f0b70862-70f6-45b5-afcc-3f0c1fa72734 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=kmac_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=418501287 -assert nopostproc +UVM_TESTNAME=chip _base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_kmac_smoketest.418501287 |
| Directory | /workspace/2.chip_sw_kmac_smoketest/latest |
| Test location | /workspace/coverage/default/2.chip_sw_lc_ctrl_otp_hw_cfg0.1484094180 |
| Short name | T90 |
| Test name | |
| Test status | |
| Simulation time | 2813426304 ps |
| CPU time | 270.02 seconds |
| Started | Aug 13 07:24:51 PM PDT 24 |
| Finished | Aug 13 07:29:21 PM PDT 24 |
| Peak memory | 609888 kb |
| Host | smart-1d6a2064-c556-4fe7-8b40-d47d71fda989 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=lc_ctrl_otp_hw_cfg0_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1484094180 -assert nopostproc +UVM_TE STNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_lo g /dev/null -cm_name 2.chip_sw_lc_ctrl_otp_hw_cfg0.1484094180 |
| Directory | /workspace/2.chip_sw_lc_ctrl_otp_hw_cfg0/latest |
| Test location | /workspace/coverage/default/2.chip_sw_lc_ctrl_program_error.514166388 |
| Short name | T173 |
| Test name | |
| Test status | |
| Simulation time | 4327056214 ps |
| CPU time | 517.92 seconds |
| Started | Aug 13 07:29:59 PM PDT 24 |
| Finished | Aug 13 07:38:37 PM PDT 24 |
| Peak memory | 611768 kb |
| Host | smart-0d3041c4-a0e6-4469-814c-a64dc830bf17 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=lc_ctrl_program_error:1:new_rules,test_rom:0 + cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_ seed=514166388 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_program_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_lc_ctrl_program_error.514166388 |
| Directory | /workspace/2.chip_sw_lc_ctrl_program_error/latest |
| Test location | /workspace/coverage/default/2.chip_sw_lc_ctrl_rand_to_scrap.1863080145 |
| Short name | T182 |
| Test name | |
| Test status | |
| Simulation time | 4231384309 ps |
| CPU time | 276.29 seconds |
| Started | Aug 13 07:25:23 PM PDT 24 |
| Finished | Aug 13 07:29:59 PM PDT 24 |
| Peak memory | 622120 kb |
| Host | smart-75bb0ab2-1055-418b-aa73-e706dd7ae150 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=lc_ctrl_scrap_test:1:new_rules,test_rom:0 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18630801 45 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_scrap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_lc_ctrl_rand_to_scrap.1863080145 |
| Directory | /workspace/2.chip_sw_lc_ctrl_rand_to_scrap/latest |
| Test location | /workspace/coverage/default/2.chip_sw_lc_ctrl_transition.3388489303 |
| Short name | T1109 |
| Test name | |
| Test status | |
| Simulation time | 6853970588 ps |
| CPU time | 747.12 seconds |
| Started | Aug 13 07:24:59 PM PDT 24 |
| Finished | Aug 13 07:37:26 PM PDT 24 |
| Peak memory | 622048 kb |
| Host | smart-10d53296-a486-4fad-95ad-9400ecf54a43 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=lc_ctrl_transition_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3388489303 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_transition_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau lt.vdb -cm_log /dev/null -cm_name 2.chip_sw_lc_ctrl_transition.3388489303 |
| Directory | /workspace/2.chip_sw_lc_ctrl_transition/latest |
| Test location | /workspace/coverage/default/2.chip_sw_lc_ctrl_volatile_raw_unlock.2283343674 |
| Short name | T738 |
| Test name | |
| Test status | |
| Simulation time | 2535413894 ps |
| CPU time | 106.3 seconds |
| Started | Aug 13 07:24:15 PM PDT 24 |
| Finished | Aug 13 07:26:02 PM PDT 24 |
| Peak memory | 618992 kb |
| Host | smart-5e30e01e-bf1e-4c6b-9cd2-7405a16c88e1 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStRaw +exp_volatile_raw_unlock_en=0 +sw_build_device=sim_dv +sw_images=lc_ctrl_volatile_raw_unlock_tes t:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/ tools/sim.tcl +ntb_random_seed=2283343674 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_volatile_raw_unlock_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_lc_ctrl_volatile_raw_unlock.2283343674 |
| Directory | /workspace/2.chip_sw_lc_ctrl_volatile_raw_unlock/latest |
| Test location | /workspace/coverage/default/2.chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz.837928802 |
| Short name | T277 |
| Test name | |
| Test status | |
| Simulation time | 2396870261 ps |
| CPU time | 124.53 seconds |
| Started | Aug 13 07:24:40 PM PDT 24 |
| Finished | Aug 13 07:26:45 PM PDT 24 |
| Peak memory | 617972 kb |
| Host | smart-7f29095b-d72b-4f1d-8b36-9046e0b1e1cb |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStRaw +chip_clock_source=ChipClockSourceExternal48Mhz +exp_volatile_raw_unlock_en=0 +sw_build_device=s im_dv +sw_images=lc_ctrl_volatile_raw_unlock_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=837928802 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST _SEQ=chip_sw_lc_volatile_raw_unlock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 2.chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz.837928802 |
| Directory | /workspace/2.chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz/latest |
| Test location | /workspace/coverage/default/2.chip_sw_lc_walkthrough_dev.316219211 |
| Short name | T1377 |
| Test name | |
| Test status | |
| Simulation time | 48314870384 ps |
| CPU time | 5363.35 seconds |
| Started | Aug 13 07:25:11 PM PDT 24 |
| Finished | Aug 13 08:54:36 PM PDT 24 |
| Peak memory | 621188 kb |
| Host | smart-4254ca31-07aa-4e39-a374-f49465584a8a |
| User | root |
| Command | /workspace/default/simv +flash_program_latency=5 +use_otp_image=OtpTypeLcStRaw +dest_dec_state=DecLcStDev +sw_test_timeout_ns=200_000_000 +sw_build_de vice=sim_dv +sw_images=lc_walkthrough_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=316219211 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=ch ip_sw_lc_walkthrough_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_ sw_lc_walkthrough_dev.316219211 |
| Directory | /workspace/2.chip_sw_lc_walkthrough_dev/latest |
| Test location | /workspace/coverage/default/2.chip_sw_lc_walkthrough_prod.1183343829 |
| Short name | T1284 |
| Test name | |
| Test status | |
| Simulation time | 50794939543 ps |
| CPU time | 5514.35 seconds |
| Started | Aug 13 07:25:03 PM PDT 24 |
| Finished | Aug 13 08:56:58 PM PDT 24 |
| Peak memory | 621092 kb |
| Host | smart-2081937f-aa57-4e42-a998-de0a5344800c |
| User | root |
| Command | /workspace/default/simv +flash_program_latency=5 +use_otp_image=OtpTypeLcStRaw +dest_dec_state=DecLcStProd +sw_test_timeout_ns=200_000_000 +sw_build_d evice=sim_dv +sw_images=lc_walkthrough_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1183343829 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ= chip_sw_lc_walkthrough_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chi p_sw_lc_walkthrough_prod.1183343829 |
| Directory | /workspace/2.chip_sw_lc_walkthrough_prod/latest |
| Test location | /workspace/coverage/default/2.chip_sw_lc_walkthrough_prodend.4243150392 |
| Short name | T305 |
| Test name | |
| Test status | |
| Simulation time | 10577046100 ps |
| CPU time | 900.93 seconds |
| Started | Aug 13 07:25:06 PM PDT 24 |
| Finished | Aug 13 07:40:07 PM PDT 24 |
| Peak memory | 620580 kb |
| Host | smart-7423dc07-56e9-4d07-b1e0-a18f2fad533f |
| User | root |
| Command | /workspace/default/simv +flash_program_latency=5 +use_otp_image=OtpTypeLcStRaw +dest_dec_state=DecLcStProdEnd +sw_build_device=sim_dv +sw_images=lc_wa lkthrough_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=4243150392 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_walkthrough_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_lc_walkthrough_prodend.4243150392 |
| Directory | /workspace/2.chip_sw_lc_walkthrough_prodend/latest |
| Test location | /workspace/coverage/default/2.chip_sw_lc_walkthrough_rma.2043983043 |
| Short name | T179 |
| Test name | |
| Test status | |
| Simulation time | 47848843950 ps |
| CPU time | 5784.06 seconds |
| Started | Aug 13 07:25:26 PM PDT 24 |
| Finished | Aug 13 09:01:51 PM PDT 24 |
| Peak memory | 620136 kb |
| Host | smart-8d619ab9-cfae-4501-90e6-97b2ba4f15d2 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStRaw +dest_dec_state=DecLcStRma +flash_program_latency=5 +sw_test_timeout_ns=200_000_000 +sw_build_de vice=sim_dv +sw_images=lc_walkthrough_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2043983043 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=c hip_sw_lc_walkthrough_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip _sw_lc_walkthrough_rma.2043983043 |
| Directory | /workspace/2.chip_sw_lc_walkthrough_rma/latest |
| Test location | /workspace/coverage/default/2.chip_sw_lc_walkthrough_testunlocks.3740549905 |
| Short name | T1057 |
| Test name | |
| Test status | |
| Simulation time | 34864447064 ps |
| CPU time | 2229.25 seconds |
| Started | Aug 13 07:25:25 PM PDT 24 |
| Finished | Aug 13 08:02:35 PM PDT 24 |
| Peak memory | 621068 kb |
| Host | smart-b115875a-e6dd-4fc1-adf7-ff04c19b06e9 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStRaw +dest_dec_state=DecLcStTestUnlock7 +sw_build_device=sim_dv +sw_images=lc_walkthrough_testunlocks _test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=3740549905 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_walkthrough_testunlocks_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_lc_walkthrough_testun locks.3740549905 |
| Directory | /workspace/2.chip_sw_lc_walkthrough_testunlocks/latest |
| Test location | /workspace/coverage/default/2.chip_sw_otbn_ecdsa_op_irq.2135949657 |
| Short name | T1054 |
| Test name | |
| Test status | |
| Simulation time | 16863198522 ps |
| CPU time | 2939.92 seconds |
| Started | Aug 13 07:27:33 PM PDT 24 |
| Finished | Aug 13 08:16:33 PM PDT 24 |
| Peak memory | 610708 kb |
| Host | smart-d8cf2012-ee26-48d1-8990-b4aff69f2f53 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=28_000_000 +rng_srate_value=30 +sw_build_device=sim_dv +sw_images=otbn_ecdsa_op_irq_test:1:new_rules,test_ rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ random_seed=2135949657 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_otbn_ecdsa_op_irq.2135949657 |
| Directory | /workspace/2.chip_sw_otbn_ecdsa_op_irq/latest |
| Test location | /workspace/coverage/default/2.chip_sw_otbn_ecdsa_op_irq_jitter_en.1520836538 |
| Short name | T1047 |
| Test name | |
| Test status | |
| Simulation time | 18070518776 ps |
| CPU time | 3338.38 seconds |
| Started | Aug 13 07:28:05 PM PDT 24 |
| Finished | Aug 13 08:23:44 PM PDT 24 |
| Peak memory | 610972 kb |
| Host | smart-861742be-a639-42b4-87e9-ec8b11d74a13 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=33_000_000 +rng_srate_value=30 +en_jitter=1 +sw_build_device=sim_dv +sw_images=otbn_ecdsa_op_irq_test:1:ne w_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/ sim.tcl +ntb_random_seed=1520836538 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tg l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_otbn_ecdsa_op_irq_jitter_en.1520836538 |
| Directory | /workspace/2.chip_sw_otbn_ecdsa_op_irq_jitter_en/latest |
| Test location | /workspace/coverage/default/2.chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq.3166446628 |
| Short name | T1291 |
| Test name | |
| Test status | |
| Simulation time | 24907548232 ps |
| CPU time | 3251.88 seconds |
| Started | Aug 13 07:32:23 PM PDT 24 |
| Finished | Aug 13 08:26:36 PM PDT 24 |
| Peak memory | 610968 kb |
| Host | smart-d6523d8a-07a1-45e9-8d0f-f2cd1ac2a51e |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=33_000_000 +rng_srate_value=30 +en_jitter=1 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=otbn_e cdsa_op_irq_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/ repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3166446628 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_otbn_ecdsa_op_irq_jitter_en_redu ced_freq.3166446628 |
| Directory | /workspace/2.chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq/latest |
| Test location | /workspace/coverage/default/2.chip_sw_otbn_mem_scramble.1754299907 |
| Short name | T247 |
| Test name | |
| Test status | |
| Simulation time | 4258707400 ps |
| CPU time | 606.92 seconds |
| Started | Aug 13 07:26:20 PM PDT 24 |
| Finished | Aug 13 07:36:27 PM PDT 24 |
| Peak memory | 609160 kb |
| Host | smart-b33b6ece-3ef4-439d-8711-09fe72f18839 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=15_000_000 +en_scb_tl_err_chk=0 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=otbn _mem_scramble_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1754299907 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_otbn_mem_scramble.1754299907 |
| Directory | /workspace/2.chip_sw_otbn_mem_scramble/latest |
| Test location | /workspace/coverage/default/2.chip_sw_otbn_randomness.2068596551 |
| Short name | T1411 |
| Test name | |
| Test status | |
| Simulation time | 5922534732 ps |
| CPU time | 991.85 seconds |
| Started | Aug 13 07:27:21 PM PDT 24 |
| Finished | Aug 13 07:43:53 PM PDT 24 |
| Peak memory | 610660 kb |
| Host | smart-9e47980f-557d-441e-acbc-7cd292209135 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +rng_srate_value=30 +sw_build_device=sim_dv +sw_images=otbn_randomness_test:1:new_rules,test_ro m:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=2068596551 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_otbn_randomness.2068596551 |
| Directory | /workspace/2.chip_sw_otbn_randomness/latest |
| Test location | /workspace/coverage/default/2.chip_sw_otbn_smoketest.3698937729 |
| Short name | T1194 |
| Test name | |
| Test status | |
| Simulation time | 8796542090 ps |
| CPU time | 2014.81 seconds |
| Started | Aug 13 07:33:34 PM PDT 24 |
| Finished | Aug 13 08:07:10 PM PDT 24 |
| Peak memory | 610776 kb |
| Host | smart-9004b79d-051a-4675-b062-4f608369d033 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=otbn_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3698937729 -assert nopostproc +UVM_TESTNAME=chi p_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul l -cm_name 2.chip_sw_otbn_smoketest.3698937729 |
| Directory | /workspace/2.chip_sw_otbn_smoketest/latest |
| Test location | /workspace/coverage/default/2.chip_sw_otp_ctrl_ecc_error_vendor_test.423773283 |
| Short name | T1353 |
| Test name | |
| Test status | |
| Simulation time | 2750828633 ps |
| CPU time | 349.92 seconds |
| Started | Aug 13 07:25:08 PM PDT 24 |
| Finished | Aug 13 07:30:58 PM PDT 24 |
| Peak memory | 610360 kb |
| Host | smart-ddcf9950-ed6a-4a34-9653-4eecc8b8ddae |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=otp_ctrl_vendor_test_ecc_error_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=423773283 -assert nopostpr oc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_otp_ctrl_vendor_test_ecc_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_otp_ctrl_ecc_error_vendor_test.423773283 |
| Directory | /workspace/2.chip_sw_otp_ctrl_ecc_error_vendor_test/latest |
| Test location | /workspace/coverage/default/2.chip_sw_otp_ctrl_lc_signals_dev.3879750264 |
| Short name | T158 |
| Test name | |
| Test status | |
| Simulation time | 8317489536 ps |
| CPU time | 1201.44 seconds |
| Started | Aug 13 07:24:43 PM PDT 24 |
| Finished | Aug 13 07:44:44 PM PDT 24 |
| Peak memory | 611152 kb |
| Host | smart-024832c5-6399-44b2-a69f-8b9216049947 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStDev +otp_clear_secret2=1 +sw_build_device=sim_dv +sw_images=otp_ctrl_lc_signals_test:1:new_rules,tes t_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +nt b_random_seed=3879750264 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_otp_ctrl_lc_signals_dev.3879750264 |
| Directory | /workspace/2.chip_sw_otp_ctrl_lc_signals_dev/latest |
| Test location | /workspace/coverage/default/2.chip_sw_otp_ctrl_lc_signals_prod.922972996 |
| Short name | T1332 |
| Test name | |
| Test status | |
| Simulation time | 7411646292 ps |
| CPU time | 1152.51 seconds |
| Started | Aug 13 07:25:34 PM PDT 24 |
| Finished | Aug 13 07:44:47 PM PDT 24 |
| Peak memory | 611456 kb |
| Host | smart-f0060f08-9a4a-49cb-b193-b7df67df5e8e |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStProd +otp_clear_secret2=1 +sw_build_device=sim_dv +sw_images=otp_ctrl_lc_signals_test:1:new_rules,te st_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n tb_random_seed=922972996 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_otp_ctrl_lc_signals_prod.922972996 |
| Directory | /workspace/2.chip_sw_otp_ctrl_lc_signals_prod/latest |
| Test location | /workspace/coverage/default/2.chip_sw_otp_ctrl_lc_signals_rma.2377588135 |
| Short name | T1179 |
| Test name | |
| Test status | |
| Simulation time | 7619690684 ps |
| CPU time | 1289.64 seconds |
| Started | Aug 13 07:26:10 PM PDT 24 |
| Finished | Aug 13 07:47:40 PM PDT 24 |
| Peak memory | 610116 kb |
| Host | smart-8c26cd62-86ee-43c4-8e7e-d034686a93a2 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStRma +otp_clear_secret2=1 +sw_build_device=sim_dv +sw_images=otp_ctrl_lc_signals_test:1:new_rules,tes t_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +nt b_random_seed=2377588135 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_otp_ctrl_lc_signals_rma.2377588135 |
| Directory | /workspace/2.chip_sw_otp_ctrl_lc_signals_rma/latest |
| Test location | /workspace/coverage/default/2.chip_sw_otp_ctrl_lc_signals_test_unlocked0.2975351896 |
| Short name | T1351 |
| Test name | |
| Test status | |
| Simulation time | 4170347404 ps |
| CPU time | 671.49 seconds |
| Started | Aug 13 07:25:23 PM PDT 24 |
| Finished | Aug 13 07:36:35 PM PDT 24 |
| Peak memory | 610172 kb |
| Host | smart-8262bde5-a5d7-4b1b-b517-75878bb02c58 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStTestUnlocked0 +otp_clear_secret2=1 +sw_build_device=sim_dv +sw_images=otp_ctrl_lc_signals_test:1:new _rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/s im.tcl +ntb_random_seed=2975351896 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_otp_ctrl_lc_signals_test_unlocked0.2975351896 |
| Directory | /workspace/2.chip_sw_otp_ctrl_lc_signals_test_unlocked0/latest |
| Test location | /workspace/coverage/default/2.chip_sw_otp_ctrl_smoketest.3651581078 |
| Short name | T949 |
| Test name | |
| Test status | |
| Simulation time | 3111685512 ps |
| CPU time | 319.09 seconds |
| Started | Aug 13 07:32:56 PM PDT 24 |
| Finished | Aug 13 07:38:16 PM PDT 24 |
| Peak memory | 610332 kb |
| Host | smart-e9f4f80f-76b6-40ef-b328-a5c7093615f8 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=otp_ctrl_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3651581078 -assert nopostproc +UVM_TESTNAME =chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 2.chip_sw_otp_ctrl_smoketest.3651581078 |
| Directory | /workspace/2.chip_sw_otp_ctrl_smoketest/latest |
| Test location | /workspace/coverage/default/2.chip_sw_pattgen_ios.1016581248 |
| Short name | T226 |
| Test name | |
| Test status | |
| Simulation time | 2467752321 ps |
| CPU time | 265.84 seconds |
| Started | Aug 13 07:23:12 PM PDT 24 |
| Finished | Aug 13 07:27:38 PM PDT 24 |
| Peak memory | 613520 kb |
| Host | smart-66295087-3e1f-4b4e-abac-28db30f87754 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=5_000_000 +sw_build_device=sim_dv +sw_images=pattgen_ios_test:1:new_rules,test_rom:0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1016581248 -ass ert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_patt_ios_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/c overage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_pattgen_ios.1016581248 |
| Directory | /workspace/2.chip_sw_pattgen_ios/latest |
| Test location | /workspace/coverage/default/2.chip_sw_plic_sw_irq.3482628887 |
| Short name | T256 |
| Test name | |
| Test status | |
| Simulation time | 2814110220 ps |
| CPU time | 303.67 seconds |
| Started | Aug 13 07:32:10 PM PDT 24 |
| Finished | Aug 13 07:37:15 PM PDT 24 |
| Peak memory | 610272 kb |
| Host | smart-da7cc70d-b3c1-4e60-8eb6-d038ed0e8f08 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=plic_sw_irq_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3482628887 -assert nopostproc +UVM_TESTNAME=c hip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n ull -cm_name 2.chip_sw_plic_sw_irq.3482628887 |
| Directory | /workspace/2.chip_sw_plic_sw_irq/latest |
| Test location | /workspace/coverage/default/2.chip_sw_power_idle_load.3945135358 |
| Short name | T230 |
| Test name | |
| Test status | |
| Simulation time | 4161786264 ps |
| CPU time | 652.23 seconds |
| Started | Aug 13 07:31:44 PM PDT 24 |
| Finished | Aug 13 07:42:36 PM PDT 24 |
| Peak memory | 610348 kb |
| Host | smart-2dd8dd4c-9869-4772-8c35-1afcf9c69b11 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=chip_power_idle_load:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3945135358 -assert nopostproc +UVM_TESTNA ME=chip_base_test +UVM_TEST_SEQ=chip_sw_power_idle_load_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_power_idle_load.3945135358 |
| Directory | /workspace/2.chip_sw_power_idle_load/latest |
| Test location | /workspace/coverage/default/2.chip_sw_power_sleep_load.62994244 |
| Short name | T757 |
| Test name | |
| Test status | |
| Simulation time | 5087579656 ps |
| CPU time | 435.57 seconds |
| Started | Aug 13 07:32:55 PM PDT 24 |
| Finished | Aug 13 07:40:11 PM PDT 24 |
| Peak memory | 610972 kb |
| Host | smart-eae0426c-42f6-4599-b016-c20b7bb00dca |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=chip_power_sleep_load:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=62994244 -assert nopostproc +UVM_TESTNAM E=chip_base_test +UVM_TEST_SEQ=chip_sw_power_sleep_load_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_power_sleep_load.62994244 |
| Directory | /workspace/2.chip_sw_power_sleep_load/latest |
| Test location | /workspace/coverage/default/2.chip_sw_pwrmgr_all_reset_reqs.2144523123 |
| Short name | T1178 |
| Test name | |
| Test status | |
| Simulation time | 10088552341 ps |
| CPU time | 1737.45 seconds |
| Started | Aug 13 07:26:23 PM PDT 24 |
| Finished | Aug 13 07:55:22 PM PDT 24 |
| Peak memory | 612188 kb |
| Host | smart-3bea7c80-676e-46d9-bebf-56382fa9eb60 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=50_000_000 +sw_build_device=sim_dv +sw_images=pwrmgr_all_reset_reqs_test:1:new_rules,test_rom:0 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2144 523123 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_deep_sleep_all_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_pwrmgr_all_reset_reqs.2144523123 |
| Directory | /workspace/2.chip_sw_pwrmgr_all_reset_reqs/latest |
| Test location | /workspace/coverage/default/2.chip_sw_pwrmgr_b2b_sleep_reset_req.1947660678 |
| Short name | T1087 |
| Test name | |
| Test status | |
| Simulation time | 25946600605 ps |
| CPU time | 1723.2 seconds |
| Started | Aug 13 07:29:21 PM PDT 24 |
| Finished | Aug 13 07:58:05 PM PDT 24 |
| Peak memory | 611556 kb |
| Host | smart-0a131332-059b-4f0d-bde7-0cf6d0cb9bc6 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=35_000_000 +sw_build_device=sim_dv +sw_images=pwrmgr_b2b_sleep_reset_test:1:new_rules,test_rom:0 +cdc_inst rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=194 7660678 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_repeat_reset_wkup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_pwrmgr_b2b_sleep_reset_req.1947660678 |
| Directory | /workspace/2.chip_sw_pwrmgr_b2b_sleep_reset_req/latest |
| Test location | /workspace/coverage/default/2.chip_sw_pwrmgr_deep_sleep_all_reset_reqs.1926760632 |
| Short name | T1345 |
| Test name | |
| Test status | |
| Simulation time | 13661048815 ps |
| CPU time | 1101.19 seconds |
| Started | Aug 13 07:35:27 PM PDT 24 |
| Finished | Aug 13 07:53:48 PM PDT 24 |
| Peak memory | 611988 kb |
| Host | smart-e008df51-0c14-44fe-be22-3af2bc5027a8 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=50_000_000 +sw_build_device=sim_dv +sw_images=pwrmgr_deep_sleep_all_reset_reqs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=1926760632 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_deep_sleep_all_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_pwrmgr_deep_sleep_all_reset_reqs.1926760632 |
| Directory | /workspace/2.chip_sw_pwrmgr_deep_sleep_all_reset_reqs/latest |
| Test location | /workspace/coverage/default/2.chip_sw_pwrmgr_deep_sleep_por_reset.1630185781 |
| Short name | T1151 |
| Test name | |
| Test status | |
| Simulation time | 6755593488 ps |
| CPU time | 507.15 seconds |
| Started | Aug 13 07:24:42 PM PDT 24 |
| Finished | Aug 13 07:33:10 PM PDT 24 |
| Peak memory | 610276 kb |
| Host | smart-69e1b8d2-abba-4d21-ae04-d4724ada3fff |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_deep_sleep_por_reset_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1630185781 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sleep_por_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage /default.vdb -cm_log /dev/null -cm_name 2.chip_sw_pwrmgr_deep_sleep_por_reset.1630185781 |
| Directory | /workspace/2.chip_sw_pwrmgr_deep_sleep_por_reset/latest |
| Test location | /workspace/coverage/default/2.chip_sw_pwrmgr_deep_sleep_power_glitch_reset.1540992323 |
| Short name | T1282 |
| Test name | |
| Test status | |
| Simulation time | 8113356650 ps |
| CPU time | 572.09 seconds |
| Started | Aug 13 07:25:09 PM PDT 24 |
| Finished | Aug 13 07:34:41 PM PDT 24 |
| Peak memory | 617020 kb |
| Host | smart-fb4c5421-f726-4f8f-87c7-6c9081516207 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=pwrmgr_deep_sleep_power_glitch_test:1:new_rules,test_rom :0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=1540992323 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_deep_power_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_pwrmgr_deep_sleep_power_glitch_reset.1540992323 |
| Directory | /workspace/2.chip_sw_pwrmgr_deep_sleep_power_glitch_reset/latest |
| Test location | /workspace/coverage/default/2.chip_sw_pwrmgr_full_aon_reset.3379567507 |
| Short name | T132 |
| Test name | |
| Test status | |
| Simulation time | 9507808168 ps |
| CPU time | 435.05 seconds |
| Started | Aug 13 07:34:18 PM PDT 24 |
| Finished | Aug 13 07:41:34 PM PDT 24 |
| Peak memory | 611620 kb |
| Host | smart-e014cba7-05de-4309-87e0-6ace21d300e8 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=rstmgr_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3379567507 -assert nopostproc +UVM_TESTNAME=c hip_base_test +UVM_TEST_SEQ=chip_sw_full_aon_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_ log /dev/null -cm_name 2.chip_sw_pwrmgr_full_aon_reset.3379567507 |
| Directory | /workspace/2.chip_sw_pwrmgr_full_aon_reset/latest |
| Test location | /workspace/coverage/default/2.chip_sw_pwrmgr_lowpower_cancel.1490152853 |
| Short name | T346 |
| Test name | |
| Test status | |
| Simulation time | 3639328680 ps |
| CPU time | 377.67 seconds |
| Started | Aug 13 07:30:06 PM PDT 24 |
| Finished | Aug 13 07:36:24 PM PDT 24 |
| Peak memory | 610652 kb |
| Host | smart-8c8ca638-98ca-4121-add1-e560688aca65 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_lowpower_cancel_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1490152853 -assert nopostproc +UVM _TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm _log /dev/null -cm_name 2.chip_sw_pwrmgr_lowpower_cancel.1490152853 |
| Directory | /workspace/2.chip_sw_pwrmgr_lowpower_cancel/latest |
| Test location | /workspace/coverage/default/2.chip_sw_pwrmgr_main_power_glitch_reset.1043088350 |
| Short name | T977 |
| Test name | |
| Test status | |
| Simulation time | 4723803624 ps |
| CPU time | 471.9 seconds |
| Started | Aug 13 07:28:11 PM PDT 24 |
| Finished | Aug 13 07:36:03 PM PDT 24 |
| Peak memory | 618236 kb |
| Host | smart-a25d958c-513d-460c-8d0a-e791fee565f2 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=pwrmgr_main_power_glitch_test:1:new_rules,test_rom:0 +cd c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se ed=1043088350 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_main_power_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_pwrmgr_main_power_glitch_reset.1043088350 |
| Directory | /workspace/2.chip_sw_pwrmgr_main_power_glitch_reset/latest |
| Test location | /workspace/coverage/default/2.chip_sw_pwrmgr_normal_sleep_all_reset_reqs.1158930393 |
| Short name | T1387 |
| Test name | |
| Test status | |
| Simulation time | 10530469669 ps |
| CPU time | 1409.58 seconds |
| Started | Aug 13 07:24:39 PM PDT 24 |
| Finished | Aug 13 07:48:09 PM PDT 24 |
| Peak memory | 612216 kb |
| Host | smart-98897481-8e29-44e9-a908-63e491dacfc0 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_normal_sleep_all_reset_reqs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1158930393 -assert nop ostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_deep_sleep_all_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_pwrmgr_normal_sleep_all_reset_reqs.1158930393 |
| Directory | /workspace/2.chip_sw_pwrmgr_normal_sleep_all_reset_reqs/latest |
| Test location | /workspace/coverage/default/2.chip_sw_pwrmgr_normal_sleep_all_wake_ups.52834278 |
| Short name | T100 |
| Test name | |
| Test status | |
| Simulation time | 7580166984 ps |
| CPU time | 424.97 seconds |
| Started | Aug 13 07:29:58 PM PDT 24 |
| Finished | Aug 13 07:37:03 PM PDT 24 |
| Peak memory | 611084 kb |
| Host | smart-d06be75a-9d3f-4520-b322-870780c52044 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_normal_sleep_all_wake_ups:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=52834278 -assert nopostproc + UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_pwrmgr_deep_sleep_all_wake_ups_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_pwrmgr_normal_sleep_all_wake_ups.52834278 |
| Directory | /workspace/2.chip_sw_pwrmgr_normal_sleep_all_wake_ups/latest |
| Test location | /workspace/coverage/default/2.chip_sw_pwrmgr_normal_sleep_por_reset.4211670853 |
| Short name | T1404 |
| Test name | |
| Test status | |
| Simulation time | 7719137630 ps |
| CPU time | 580.43 seconds |
| Started | Aug 13 07:26:02 PM PDT 24 |
| Finished | Aug 13 07:35:43 PM PDT 24 |
| Peak memory | 610332 kb |
| Host | smart-f865f293-e15a-4db8-8c7c-d6fb977b2753 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_normal_sleep_por_reset_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4211670853 -assert nopostpr oc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sleep_por_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera ge/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_pwrmgr_normal_sleep_por_reset.4211670853 |
| Directory | /workspace/2.chip_sw_pwrmgr_normal_sleep_por_reset/latest |
| Test location | /workspace/coverage/default/2.chip_sw_pwrmgr_random_sleep_all_reset_reqs.2744260906 |
| Short name | T1159 |
| Test name | |
| Test status | |
| Simulation time | 29880980325 ps |
| CPU time | 2748.41 seconds |
| Started | Aug 13 07:26:19 PM PDT 24 |
| Finished | Aug 13 08:12:08 PM PDT 24 |
| Peak memory | 611924 kb |
| Host | smart-38cebc0d-82ef-4d1c-8c2b-43424d9d41b1 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=50_000_000 +sw_build_device=sim_dv +sw_images=pwrmgr_random_sleep_all_reset_reqs_test:1:new_rules,test_rom :0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=2744260906 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_deep_sleep_all_reset_vseq +en_cov=1 -cm line+cond+fsm+tg l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_pwrmgr_random_sleep_all_reset_reqs.2744260906 |
| Directory | /workspace/2.chip_sw_pwrmgr_random_sleep_all_reset_reqs/latest |
| Test location | /workspace/coverage/default/2.chip_sw_pwrmgr_random_sleep_all_wake_ups.2529281150 |
| Short name | T98 |
| Test name | |
| Test status | |
| Simulation time | 25710360760 ps |
| CPU time | 1696.04 seconds |
| Started | Aug 13 07:31:18 PM PDT 24 |
| Finished | Aug 13 07:59:35 PM PDT 24 |
| Peak memory | 611756 kb |
| Host | smart-fd33456a-8e8d-4479-9a1d-d4ed49041ed3 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +do_random=1 +sw_build_device=sim_dv +sw_images=pwrmgr_random_sleep_all_wake_ups:1:new_rules,te st_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n tb_random_seed=2529281150 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_pwrmgr_deep_sleep_all_wake_ups_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_pwrmgr_random_sleep_all_wake_ups.2529281150 |
| Directory | /workspace/2.chip_sw_pwrmgr_random_sleep_all_wake_ups/latest |
| Test location | /workspace/coverage/default/2.chip_sw_pwrmgr_random_sleep_power_glitch_reset.1352565382 |
| Short name | T1158 |
| Test name | |
| Test status | |
| Simulation time | 43403410613 ps |
| CPU time | 3270.51 seconds |
| Started | Aug 13 07:34:06 PM PDT 24 |
| Finished | Aug 13 08:28:37 PM PDT 24 |
| Peak memory | 612584 kb |
| Host | smart-576a094b-55f4-4546-abf7-a496bfe3497a |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_test_timeout_ns=24_000_000 +sw_build_device=sim_dv +sw_images=pwrmgr_random_sleep_power _glitch_reset_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1352565382 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_random_power_glit ch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_pwrmgr_random_s leep_power_glitch_reset.1352565382 |
| Directory | /workspace/2.chip_sw_pwrmgr_random_sleep_power_glitch_reset/latest |
| Test location | /workspace/coverage/default/2.chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up.2595253078 |
| Short name | T375 |
| Test name | |
| Test status | |
| Simulation time | 6851076272 ps |
| CPU time | 613.83 seconds |
| Started | Aug 13 07:30:16 PM PDT 24 |
| Finished | Aug 13 07:40:30 PM PDT 24 |
| Peak memory | 611680 kb |
| Host | smart-ba72aa65-2baf-46ef-b073-2579d59eb745 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +do_random=1 +sw_build_device=sim_dv +sw_images=pwrmgr_sensor_ctrl_deep_sleep_wake_up:1:new_rul es,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t cl +ntb_random_seed=2595253078 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_pwrmgr_sensor_ctrl_deep_s leep_wake_up.2595253078 |
| Directory | /workspace/2.chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up/latest |
| Test location | /workspace/coverage/default/2.chip_sw_pwrmgr_sleep_disabled.1389021934 |
| Short name | T745 |
| Test name | |
| Test status | |
| Simulation time | 3151813634 ps |
| CPU time | 399.76 seconds |
| Started | Aug 13 07:25:26 PM PDT 24 |
| Finished | Aug 13 07:32:06 PM PDT 24 |
| Peak memory | 610292 kb |
| Host | smart-342bcd05-0528-4850-a4d4-fa8c57061657 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_sleep_disabled_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1389021934 -assert nopostproc +UVM_ TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_ log /dev/null -cm_name 2.chip_sw_pwrmgr_sleep_disabled.1389021934 |
| Directory | /workspace/2.chip_sw_pwrmgr_sleep_disabled/latest |
| Test location | /workspace/coverage/default/2.chip_sw_pwrmgr_sleep_power_glitch_reset.1447023343 |
| Short name | T415 |
| Test name | |
| Test status | |
| Simulation time | 6198841152 ps |
| CPU time | 415.42 seconds |
| Started | Aug 13 07:34:51 PM PDT 24 |
| Finished | Aug 13 07:41:47 PM PDT 24 |
| Peak memory | 618488 kb |
| Host | smart-d440c66f-5c5a-4a19-b83f-9b29f52e3061 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=pwrmgr_sleep_power_glitch_test:1:new_rules,test_rom:0 +c dc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_s eed=1447023343 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_main_power_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_pwrmgr_sleep_power_glitch_reset.1447023343 |
| Directory | /workspace/2.chip_sw_pwrmgr_sleep_power_glitch_reset/latest |
| Test location | /workspace/coverage/default/2.chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup.3432123411 |
| Short name | T133 |
| Test name | |
| Test status | |
| Simulation time | 5221672544 ps |
| CPU time | 488.72 seconds |
| Started | Aug 13 07:31:56 PM PDT 24 |
| Finished | Aug 13 07:40:05 PM PDT 24 |
| Peak memory | 610704 kb |
| Host | smart-1d792679-3d31-4bda-84f1-78bec625d50b |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=8_000_000 +sw_build_device=sim_dv +sw_images=sensor_ctrl_wakeup_test:1:new_rules,test_rom:0 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34321234 11 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac e/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup.3432123411 |
| Directory | /workspace/2.chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup/latest |
| Test location | /workspace/coverage/default/2.chip_sw_pwrmgr_sleep_wake_5_bug.4088505549 |
| Short name | T1008 |
| Test name | |
| Test status | |
| Simulation time | 5904310616 ps |
| CPU time | 586.68 seconds |
| Started | Aug 13 07:30:19 PM PDT 24 |
| Finished | Aug 13 07:40:06 PM PDT 24 |
| Peak memory | 611448 kb |
| Host | smart-d33319f8-d8f2-4dec-9d70-b8bcbc1026d4 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +do_random=1 +sw_build_device=sim_dv +sw_images=pwrmgr_sleep_wake_5_bug_test:1:new_rules,test_r om:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r andom_seed=4088505549 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_pwrmgr_sleep_wake_5_bug.4088505549 |
| Directory | /workspace/2.chip_sw_pwrmgr_sleep_wake_5_bug/latest |
| Test location | /workspace/coverage/default/2.chip_sw_pwrmgr_smoketest.1537624552 |
| Short name | T1044 |
| Test name | |
| Test status | |
| Simulation time | 5028580124 ps |
| CPU time | 318.24 seconds |
| Started | Aug 13 07:32:12 PM PDT 24 |
| Finished | Aug 13 07:37:30 PM PDT 24 |
| Peak memory | 611208 kb |
| Host | smart-8bcfcecc-b42a-4bd8-9a50-3abe588412bd |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=10000000 +sw_build_device=sim_dv +sw_images=pwrmgr_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1537624552 -asse rt nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera ge/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_pwrmgr_smoketest.1537624552 |
| Directory | /workspace/2.chip_sw_pwrmgr_smoketest/latest |
| Test location | /workspace/coverage/default/2.chip_sw_pwrmgr_sysrst_ctrl_reset.1197486243 |
| Short name | T981 |
| Test name | |
| Test status | |
| Simulation time | 6906942776 ps |
| CPU time | 1105.59 seconds |
| Started | Aug 13 07:25:10 PM PDT 24 |
| Finished | Aug 13 07:43:36 PM PDT 24 |
| Peak memory | 611396 kb |
| Host | smart-9e421dbf-9299-4216-ba9a-0a64be73323b |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_sysrst_ctrl_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1197486243 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sysrst_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_pwrmgr_sysrst_ctrl_reset.1197486243 |
| Directory | /workspace/2.chip_sw_pwrmgr_sysrst_ctrl_reset/latest |
| Test location | /workspace/coverage/default/2.chip_sw_pwrmgr_usb_clk_disabled_when_active.3430718725 |
| Short name | T1313 |
| Test name | |
| Test status | |
| Simulation time | 4982219896 ps |
| CPU time | 441.91 seconds |
| Started | Aug 13 07:27:06 PM PDT 24 |
| Finished | Aug 13 07:34:28 PM PDT 24 |
| Peak memory | 610820 kb |
| Host | smart-ae9a3e7a-7dfc-43bc-a60c-3b55d1d52018 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_usb_clk_disabled_when_active_test:1:new_rules,test_rom:0 +cdc_instrumentation_enable d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3430718725 -assert no postproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de fault.vdb -cm_log /dev/null -cm_name 2.chip_sw_pwrmgr_usb_clk_disabled_when_active.3430718725 |
| Directory | /workspace/2.chip_sw_pwrmgr_usb_clk_disabled_when_active/latest |
| Test location | /workspace/coverage/default/2.chip_sw_pwrmgr_usbdev_smoketest.484221668 |
| Short name | T1278 |
| Test name | |
| Test status | |
| Simulation time | 5874127324 ps |
| CPU time | 382 seconds |
| Started | Aug 13 07:33:42 PM PDT 24 |
| Finished | Aug 13 07:40:04 PM PDT 24 |
| Peak memory | 609956 kb |
| Host | smart-10e4ba05-a62b-4112-945e-d59aee2eccc5 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_usbdev_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=484221668 -assert nopostproc +UVM_TEST NAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_pwrmgr_usbdev_smoketest.484221668 |
| Directory | /workspace/2.chip_sw_pwrmgr_usbdev_smoketest/latest |
| Test location | /workspace/coverage/default/2.chip_sw_pwrmgr_wdog_reset.3205051557 |
| Short name | T973 |
| Test name | |
| Test status | |
| Simulation time | 5370133872 ps |
| CPU time | 538.72 seconds |
| Started | Aug 13 07:27:55 PM PDT 24 |
| Finished | Aug 13 07:36:54 PM PDT 24 |
| Peak memory | 611008 kb |
| Host | smart-af523bea-c31a-45ae-8fd6-c11fda85258f |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=pwrmgr_wdog_reset_reqs_test:1:new_rules,test_rom:0 +cdc_inst rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=320 5051557 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_pwrmgr_wdog_reset.3205051557 |
| Directory | /workspace/2.chip_sw_pwrmgr_wdog_reset/latest |
| Test location | /workspace/coverage/default/2.chip_sw_rom_ctrl_integrity_check.169395788 |
| Short name | T281 |
| Test name | |
| Test status | |
| Simulation time | 8509131855 ps |
| CPU time | 604.11 seconds |
| Started | Aug 13 07:28:08 PM PDT 24 |
| Finished | Aug 13 07:38:13 PM PDT 24 |
| Peak memory | 624708 kb |
| Host | smart-6ed8d546-8234-408c-99e3-160a6445cffb |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=rom_ctrl_integrity_check_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=169395788 -assert nopostproc +UV M_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rom_ctrl_integrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov erage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_rom_ctrl_integrity_check.169395788 |
| Directory | /workspace/2.chip_sw_rom_ctrl_integrity_check/latest |
| Test location | /workspace/coverage/default/2.chip_sw_rstmgr_alert_info.2542062032 |
| Short name | T332 |
| Test name | |
| Test status | |
| Simulation time | 10361534646 ps |
| CPU time | 1502.6 seconds |
| Started | Aug 13 07:28:08 PM PDT 24 |
| Finished | Aug 13 07:53:11 PM PDT 24 |
| Peak memory | 611656 kb |
| Host | smart-98f83a00-a2f2-4184-b14c-f4d6d73a645f |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=30_000_000 +en_scb_tl_err_chk=0 +sw_build_device=sim_dv +sw_images=rstmgr_alert_info_test:1:new_rules,test _rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb _random_seed=2542062032 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_rstmgr_alert_info.2542062032 |
| Directory | /workspace/2.chip_sw_rstmgr_alert_info/latest |
| Test location | /workspace/coverage/default/2.chip_sw_rstmgr_cpu_info.2188413858 |
| Short name | T248 |
| Test name | |
| Test status | |
| Simulation time | 4788046858 ps |
| CPU time | 582.41 seconds |
| Started | Aug 13 07:26:15 PM PDT 24 |
| Finished | Aug 13 07:35:58 PM PDT 24 |
| Peak memory | 611088 kb |
| Host | smart-f451d4b1-7e30-4a7c-9a70-278645d6cc73 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=rstmgr_cpu_info_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2188413858 -assert nopostproc +UVM_TESTNA ME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 2.chip_sw_rstmgr_cpu_info.2188413858 |
| Directory | /workspace/2.chip_sw_rstmgr_cpu_info/latest |
| Test location | /workspace/coverage/default/2.chip_sw_rstmgr_rst_cnsty_escalation.665675516 |
| Short name | T357 |
| Test name | |
| Test status | |
| Simulation time | 5517637120 ps |
| CPU time | 905.29 seconds |
| Started | Aug 13 07:23:19 PM PDT 24 |
| Finished | Aug 13 07:38:25 PM PDT 24 |
| Peak memory | 642092 kb |
| Host | smart-ce71129f-95a5-4269-be37-72e93d447f29 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 665675516 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rstmgr_cnsty_fault_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_rstmgr_rst_cnsty_escalation.665675516 |
| Directory | /workspace/2.chip_sw_rstmgr_rst_cnsty_escalation/latest |
| Test location | /workspace/coverage/default/2.chip_sw_rstmgr_smoketest.1485611660 |
| Short name | T399 |
| Test name | |
| Test status | |
| Simulation time | 2479573416 ps |
| CPU time | 247.33 seconds |
| Started | Aug 13 07:33:24 PM PDT 24 |
| Finished | Aug 13 07:37:32 PM PDT 24 |
| Peak memory | 610412 kb |
| Host | smart-c4a65fd0-d0fd-4ac0-afa3-143f12e711f0 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=rstmgr_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1485611660 -assert nopostproc +UVM_TESTNAME=c hip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n ull -cm_name 2.chip_sw_rstmgr_smoketest.1485611660 |
| Directory | /workspace/2.chip_sw_rstmgr_smoketest/latest |
| Test location | /workspace/coverage/default/2.chip_sw_rstmgr_sw_req.2406994728 |
| Short name | T1350 |
| Test name | |
| Test status | |
| Simulation time | 3395488920 ps |
| CPU time | 423.98 seconds |
| Started | Aug 13 07:25:19 PM PDT 24 |
| Finished | Aug 13 07:32:23 PM PDT 24 |
| Peak memory | 610508 kb |
| Host | smart-714390e6-7211-4dac-a673-db81fce40514 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=rstmgr_sw_req_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2406994728 -assert nopostproc +UVM_TESTNAME =chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 2.chip_sw_rstmgr_sw_req.2406994728 |
| Directory | /workspace/2.chip_sw_rstmgr_sw_req/latest |
| Test location | /workspace/coverage/default/2.chip_sw_rstmgr_sw_rst.95903302 |
| Short name | T220 |
| Test name | |
| Test status | |
| Simulation time | 2676203598 ps |
| CPU time | 260.82 seconds |
| Started | Aug 13 07:26:12 PM PDT 24 |
| Finished | Aug 13 07:30:33 PM PDT 24 |
| Peak memory | 610332 kb |
| Host | smart-72c144df-aa15-4e36-aa6f-7639c9ad7922 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=rstmgr_sw_rst_ctrl_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=95903302 -assert nopostproc +UVM_TESTN AME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log / dev/null -cm_name 2.chip_sw_rstmgr_sw_rst.95903302 |
| Directory | /workspace/2.chip_sw_rstmgr_sw_rst/latest |
| Test location | /workspace/coverage/default/2.chip_sw_rv_core_ibex_address_translation.3840158434 |
| Short name | T302 |
| Test name | |
| Test status | |
| Simulation time | 3191919588 ps |
| CPU time | 224.55 seconds |
| Started | Aug 13 07:30:00 PM PDT 24 |
| Finished | Aug 13 07:33:45 PM PDT 24 |
| Peak memory | 609108 kb |
| Host | smart-087abdee-e48c-4178-bb55-befaf926a4fb |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=7_000_000 +sw_build_device=sim_dv +sw_images=rv_core_ibex_address_translation_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random _seed=3840158434 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_rv_core_ibex_address_translation.3840158434 |
| Directory | /workspace/2.chip_sw_rv_core_ibex_address_translation/latest |
| Test location | /workspace/coverage/default/2.chip_sw_rv_core_ibex_icache_invalidate.277009350 |
| Short name | T186 |
| Test name | |
| Test status | |
| Simulation time | 2678214362 ps |
| CPU time | 205.53 seconds |
| Started | Aug 13 07:28:59 PM PDT 24 |
| Finished | Aug 13 07:32:25 PM PDT 24 |
| Peak memory | 610324 kb |
| Host | smart-fe069071-973f-4f90-8468-087397655adc |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=rv_core_ibex_icache_invalidate_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=277009350 -assert nopostpr oc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rv_core_ibex_icache_invalidate_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_rv_core_ibex_icache_invalidate.277009350 |
| Directory | /workspace/2.chip_sw_rv_core_ibex_icache_invalidate/latest |
| Test location | /workspace/coverage/default/2.chip_sw_rv_core_ibex_nmi_irq.808004689 |
| Short name | T547 |
| Test name | |
| Test status | |
| Simulation time | 4908323106 ps |
| CPU time | 1110.55 seconds |
| Started | Aug 13 07:27:13 PM PDT 24 |
| Finished | Aug 13 07:45:44 PM PDT 24 |
| Peak memory | 610884 kb |
| Host | smart-2f269766-731e-4021-81c0-6aab4ab6f205 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=10_000_000 +sw_build_device=sim_dv +sw_images=rv_core_ibex_nmi_irq_test:1:new_rules,test_rom:0 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=80800 4689 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_rv_core_ibex_nmi_irq.808004689 |
| Directory | /workspace/2.chip_sw_rv_core_ibex_nmi_irq/latest |
| Test location | /workspace/coverage/default/2.chip_sw_rv_core_ibex_rnd.2739404192 |
| Short name | T267 |
| Test name | |
| Test status | |
| Simulation time | 5703854488 ps |
| CPU time | 1056.52 seconds |
| Started | Aug 13 07:26:47 PM PDT 24 |
| Finished | Aug 13 07:44:25 PM PDT 24 |
| Peak memory | 610876 kb |
| Host | smart-53b3362d-b43f-46d7-bb74-0ecb2ee01f44 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=20_000_000 +rng_srate_value_max=32 +sw_build_device=sim_dv +sw_images=rv_core_ibex_rnd_test:1:new_rules,te st_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n tb_random_seed=2739404192 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_rv_core_ibex_rnd.2739404192 |
| Directory | /workspace/2.chip_sw_rv_core_ibex_rnd/latest |
| Test location | /workspace/coverage/default/2.chip_sw_rv_dm_access_after_escalation_reset.3380157806 |
| Short name | T735 |
| Test name | |
| Test status | |
| Simulation time | 6188592258 ps |
| CPU time | 658.73 seconds |
| Started | Aug 13 07:29:30 PM PDT 24 |
| Finished | Aug 13 07:40:29 PM PDT 24 |
| Peak memory | 625204 kb |
| Host | smart-5a4f39b4-f65d-4a45-8dc8-fca9d3265196 |
| User | root |
| Command | /workspace/default/simv +use_jtag_dmi=1 +sw_build_device=sim_dv +sw_images=alert_handler_escalation_test:1:new_rules,test_rom:0 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3380157806 -asse rt nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rv_dm_access_after_escalation_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_rv_dm_access_after_escalation_reset.3380157806 |
| Directory | /workspace/2.chip_sw_rv_dm_access_after_escalation_reset/latest |
| Test location | /workspace/coverage/default/2.chip_sw_rv_dm_access_after_wakeup.4286937796 |
| Short name | T1287 |
| Test name | |
| Test status | |
| Simulation time | 6170894732 ps |
| CPU time | 500.71 seconds |
| Started | Aug 13 07:31:30 PM PDT 24 |
| Finished | Aug 13 07:39:51 PM PDT 24 |
| Peak memory | 620524 kb |
| Host | smart-4b91ca18-52b9-47f5-9093-9a5cf0f9590e |
| User | root |
| Command | /workspace/default/simv +use_jtag_dmi=1 +sw_build_device=sim_dv +sw_images=rv_dm_access_after_wakeup_rma:1:new_rules,test_rom:0 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4286937796 -asse rt nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rv_dm_access_after_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_rv_dm_access_after_wakeup.4286937796 |
| Directory | /workspace/2.chip_sw_rv_dm_access_after_wakeup/latest |
| Test location | /workspace/coverage/default/2.chip_sw_rv_dm_ndm_reset_req_when_cpu_halted.3411850491 |
| Short name | T321 |
| Test name | |
| Test status | |
| Simulation time | 3693060168 ps |
| CPU time | 447.05 seconds |
| Started | Aug 13 07:29:30 PM PDT 24 |
| Finished | Aug 13 07:36:58 PM PDT 24 |
| Peak memory | 620652 kb |
| Host | smart-117f905a-dfeb-49b7-8c15-3be1c3159ee3 |
| User | root |
| Command | /workspace/default/simv +use_jtag_dmi=1 +sw_build_device=sim_dv +sw_images=rv_dm_ndm_reset_req_when_cpu_halted_rma:1:new_rules,test_rom:0 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=341185 0491 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rv_dm_ndm_reset_when_cpu_halted_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_rv_dm_ndm_reset_req_when_cpu_halted.3411850491 |
| Directory | /workspace/2.chip_sw_rv_dm_ndm_reset_req_when_cpu_halted/latest |
| Test location | /workspace/coverage/default/2.chip_sw_rv_plic_smoketest.3554489253 |
| Short name | T106 |
| Test name | |
| Test status | |
| Simulation time | 3258403880 ps |
| CPU time | 197.74 seconds |
| Started | Aug 13 07:32:14 PM PDT 24 |
| Finished | Aug 13 07:35:32 PM PDT 24 |
| Peak memory | 610188 kb |
| Host | smart-36e936e1-6cad-4829-8dec-2c37d7d98664 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=rv_plic_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3554489253 -assert nopostproc +UVM_TESTNAME= chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/ null -cm_name 2.chip_sw_rv_plic_smoketest.3554489253 |
| Directory | /workspace/2.chip_sw_rv_plic_smoketest/latest |
| Test location | /workspace/coverage/default/2.chip_sw_rv_timer_irq.2121585355 |
| Short name | T259 |
| Test name | |
| Test status | |
| Simulation time | 2298923460 ps |
| CPU time | 205.72 seconds |
| Started | Aug 13 07:25:18 PM PDT 24 |
| Finished | Aug 13 07:28:44 PM PDT 24 |
| Peak memory | 610476 kb |
| Host | smart-6e84fff9-4e48-4fd5-83f0-8f6e908b3012 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=rv_timer_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2121585355 -assert nopostproc +UVM_TESTNAME =chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 2.chip_sw_rv_timer_irq.2121585355 |
| Directory | /workspace/2.chip_sw_rv_timer_irq/latest |
| Test location | /workspace/coverage/default/2.chip_sw_rv_timer_smoketest.2270935699 |
| Short name | T1118 |
| Test name | |
| Test status | |
| Simulation time | 2805597220 ps |
| CPU time | 258.08 seconds |
| Started | Aug 13 07:31:29 PM PDT 24 |
| Finished | Aug 13 07:35:47 PM PDT 24 |
| Peak memory | 609836 kb |
| Host | smart-e74010c6-3ef5-47cd-a8c4-602cb53e3ac5 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=rv_timer_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2270935699 -assert nopostproc +UVM_TESTNAME =chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 2.chip_sw_rv_timer_smoketest.2270935699 |
| Directory | /workspace/2.chip_sw_rv_timer_smoketest/latest |
| Test location | /workspace/coverage/default/2.chip_sw_sensor_ctrl_alert.2294242035 |
| Short name | T138 |
| Test name | |
| Test status | |
| Simulation time | 5104498400 ps |
| CPU time | 729.09 seconds |
| Started | Aug 13 07:28:54 PM PDT 24 |
| Finished | Aug 13 07:41:03 PM PDT 24 |
| Peak memory | 611260 kb |
| Host | smart-f94197b2-b7ba-4381-b091-af2410f912cd |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=40_000_000 +sw_build_device=sim_dv +sw_images=sensor_ctrl_alert_test:1:new_rules,test_rom:0 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22942420 35 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac e/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_sensor_ctrl_alert.2294242035 |
| Directory | /workspace/2.chip_sw_sensor_ctrl_alert/latest |
| Test location | /workspace/coverage/default/2.chip_sw_sensor_ctrl_status.2527395405 |
| Short name | T148 |
| Test name | |
| Test status | |
| Simulation time | 2827347844 ps |
| CPU time | 315.97 seconds |
| Started | Aug 13 07:28:12 PM PDT 24 |
| Finished | Aug 13 07:33:28 PM PDT 24 |
| Peak memory | 611512 kb |
| Host | smart-944169c9-f736-45bc-8c03-239a4ea842c9 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=40_000_000 +sw_build_device=sim_dv +sw_images=sensor_ctrl_status_test:1:new_rules,test_rom:0 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2527395 405 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sensor_ctrl_status_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_sensor_ctrl_status.2527395405 |
| Directory | /workspace/2.chip_sw_sensor_ctrl_status/latest |
| Test location | /workspace/coverage/default/2.chip_sw_sleep_pin_retention.4117021654 |
| Short name | T51 |
| Test name | |
| Test status | |
| Simulation time | 3021992860 ps |
| CPU time | 297.05 seconds |
| Started | Aug 13 07:22:49 PM PDT 24 |
| Finished | Aug 13 07:27:46 PM PDT 24 |
| Peak memory | 611000 kb |
| Host | smart-45de3f2d-76f9-4436-a8eb-bbbc6734a2b9 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=sleep_pin_retention_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4117021654 -assert nopostproc +UVM_TE STNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sleep_pin_retention_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def ault.vdb -cm_log /dev/null -cm_name 2.chip_sw_sleep_pin_retention.4117021654 |
| Directory | /workspace/2.chip_sw_sleep_pin_retention/latest |
| Test location | /workspace/coverage/default/2.chip_sw_sleep_pwm_pulses.2727646034 |
| Short name | T433 |
| Test name | |
| Test status | |
| Simulation time | 9092605694 ps |
| CPU time | 1440.35 seconds |
| Started | Aug 13 07:25:44 PM PDT 24 |
| Finished | Aug 13 07:49:44 PM PDT 24 |
| Peak memory | 611328 kb |
| Host | smart-028b00f8-523c-4699-bcca-2fa31918c50d |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=sleep_pwm_pulses_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2727646034 -assert nopostproc +UVM_TESTN AME=chip_base_test +UVM_TEST_SEQ=chip_sw_pwm_pulses_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm _log /dev/null -cm_name 2.chip_sw_sleep_pwm_pulses.2727646034 |
| Directory | /workspace/2.chip_sw_sleep_pwm_pulses/latest |
| Test location | /workspace/coverage/default/2.chip_sw_sleep_sram_ret_contents_no_scramble.468377999 |
| Short name | T1086 |
| Test name | |
| Test status | |
| Simulation time | 6556374478 ps |
| CPU time | 653.84 seconds |
| Started | Aug 13 07:29:03 PM PDT 24 |
| Finished | Aug 13 07:39:57 PM PDT 24 |
| Peak memory | 611056 kb |
| Host | smart-c789e98f-bbb4-4dc0-8ede-c9a0705299f9 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=20_000_000 +en_scb_tl_err_chk=0 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=sram _ctrl_sleep_sram_ret_contents_no_scramble_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=468377999 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SE Q=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_sle ep_sram_ret_contents_no_scramble.468377999 |
| Directory | /workspace/2.chip_sw_sleep_sram_ret_contents_no_scramble/latest |
| Test location | /workspace/coverage/default/2.chip_sw_sleep_sram_ret_contents_scramble.514237949 |
| Short name | T1206 |
| Test name | |
| Test status | |
| Simulation time | 7780461292 ps |
| CPU time | 790.24 seconds |
| Started | Aug 13 07:28:08 PM PDT 24 |
| Finished | Aug 13 07:41:18 PM PDT 24 |
| Peak memory | 611368 kb |
| Host | smart-4bd5200c-641a-4af5-977d-ca9c040e493a |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=20_000_000 +en_scb_tl_err_chk=0 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=sram _ctrl_sleep_sram_ret_contents_scramble_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=514237949 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=c hip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_sleep_ sram_ret_contents_scramble.514237949 |
| Directory | /workspace/2.chip_sw_sleep_sram_ret_contents_scramble/latest |
| Test location | /workspace/coverage/default/2.chip_sw_spi_device_pass_through.2234664562 |
| Short name | T208 |
| Test name | |
| Test status | |
| Simulation time | 6257442627 ps |
| CPU time | 659.65 seconds |
| Started | Aug 13 07:26:16 PM PDT 24 |
| Finished | Aug 13 07:37:16 PM PDT 24 |
| Peak memory | 625356 kb |
| Host | smart-3f9f6690-5933-4fa7-8e67-5a4f4b9e3d38 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=spi_passthrough_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2234664562 -assert nopostproc +UVM_TESTNA ME=chip_base_test +UVM_TEST_SEQ=chip_sw_spi_passthrough_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_spi_device_pass_through.2234664562 |
| Directory | /workspace/2.chip_sw_spi_device_pass_through/latest |
| Test location | /workspace/coverage/default/2.chip_sw_spi_device_pass_through_collision.992697020 |
| Short name | T209 |
| Test name | |
| Test status | |
| Simulation time | 4462178130 ps |
| CPU time | 462.27 seconds |
| Started | Aug 13 07:23:30 PM PDT 24 |
| Finished | Aug 13 07:31:12 PM PDT 24 |
| Peak memory | 625432 kb |
| Host | smart-19cfcd59-af62-44ec-b561-8d2372593147 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=spi_passthrough_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=992697020 -assert nopostproc +UVM_TESTNAM E=chip_base_test +UVM_TEST_SEQ=chip_sw_spi_passthrough_collision_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de fault.vdb -cm_log /dev/null -cm_name 2.chip_sw_spi_device_pass_through_collision.992697020 |
| Directory | /workspace/2.chip_sw_spi_device_pass_through_collision/latest |
| Test location | /workspace/coverage/default/2.chip_sw_spi_device_pinmux_sleep_retention.4289690245 |
| Short name | T54 |
| Test name | |
| Test status | |
| Simulation time | 3555066970 ps |
| CPU time | 298.44 seconds |
| Started | Aug 13 07:24:11 PM PDT 24 |
| Finished | Aug 13 07:29:10 PM PDT 24 |
| Peak memory | 618532 kb |
| Host | smart-17dc030e-44b0-4779-ad57-5af38162a5fb |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=spi_device_sleep_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4289690245 -assert nopostproc +UVM_TESTN AME=chip_base_test +UVM_TEST_SEQ=chip_sw_spi_device_pinmux_sleep_retention_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/c overage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_spi_device_pinmux_sleep_retention.4289690245 |
| Directory | /workspace/2.chip_sw_spi_device_pinmux_sleep_retention/latest |
| Test location | /workspace/coverage/default/2.chip_sw_spi_device_tpm.3025996466 |
| Short name | T37 |
| Test name | |
| Test status | |
| Simulation time | 2910242300 ps |
| CPU time | 341.06 seconds |
| Started | Aug 13 07:26:33 PM PDT 24 |
| Finished | Aug 13 07:32:14 PM PDT 24 |
| Peak memory | 623780 kb |
| Host | smart-94788aeb-98c8-4fce-8b65-bea6ce4c51d6 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=spi_device_tpm_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3025996466 -assert nopostproc +UVM_T ESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_spi_device_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default .vdb -cm_log /dev/null -cm_name 2.chip_sw_spi_device_tpm.3025996466 |
| Directory | /workspace/2.chip_sw_spi_device_tpm/latest |
| Test location | /workspace/coverage/default/2.chip_sw_spi_host_tx_rx.948664045 |
| Short name | T33 |
| Test name | |
| Test status | |
| Simulation time | 3601145464 ps |
| CPU time | 342.93 seconds |
| Started | Aug 13 07:24:54 PM PDT 24 |
| Finished | Aug 13 07:30:37 PM PDT 24 |
| Peak memory | 609616 kb |
| Host | smart-479ae925-8450-47a8-ba4d-0fb6f7fb364b |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=spi_host_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=948664045 -assert nopostproc +UVM_TESTNAME =chip_base_test +UVM_TEST_SEQ=chip_sw_spi_host_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -c m_log /dev/null -cm_name 2.chip_sw_spi_host_tx_rx.948664045 |
| Directory | /workspace/2.chip_sw_spi_host_tx_rx/latest |
| Test location | /workspace/coverage/default/2.chip_sw_sram_ctrl_execution_main.2549098289 |
| Short name | T312 |
| Test name | |
| Test status | |
| Simulation time | 8658960091 ps |
| CPU time | 868.74 seconds |
| Started | Aug 13 07:29:10 PM PDT 24 |
| Finished | Aug 13 07:43:39 PM PDT 24 |
| Peak memory | 611128 kb |
| Host | smart-67b26bcd-bd20-4435-b2be-aaf42346308e |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=sram_ctrl_execution_main_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2549098289 -assert nopostproc +U VM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sram_ctrl_execution_main_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co verage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_sram_ctrl_execution_main.2549098289 |
| Directory | /workspace/2.chip_sw_sram_ctrl_execution_main/latest |
| Test location | /workspace/coverage/default/2.chip_sw_sram_ctrl_scrambled_access_jitter_en.4281141390 |
| Short name | T695 |
| Test name | |
| Test status | |
| Simulation time | 4989373238 ps |
| CPU time | 748.75 seconds |
| Started | Aug 13 07:28:18 PM PDT 24 |
| Finished | Aug 13 07:40:47 PM PDT 24 |
| Peak memory | 611436 kb |
| Host | smart-8d81cd16-41f7-45c0-afd5-77bc16eadc31 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=12_000_000 +bypass_alert_ready_to_end_check=1 +en_jitter=1 +en_scb_tl_err_chk=0 +sw_build_device=sim_dv +s w_images=sram_ctrl_scrambled_access_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4281141390 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chi p_sw_sram_ctrl_scrambled_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n ame 2.chip_sw_sram_ctrl_scrambled_access_jitter_en.4281141390 |
| Directory | /workspace/2.chip_sw_sram_ctrl_scrambled_access_jitter_en/latest |
| Test location | /workspace/coverage/default/2.chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq.2688565999 |
| Short name | T292 |
| Test name | |
| Test status | |
| Simulation time | 4918250437 ps |
| CPU time | 625.67 seconds |
| Started | Aug 13 07:29:50 PM PDT 24 |
| Finished | Aug 13 07:40:16 PM PDT 24 |
| Peak memory | 610568 kb |
| Host | smart-92b45f3f-2689-4b11-8f24-31ccdf54509b |
| User | root |
| Command | /workspace/default/simv +mem_sel=main +sw_test_timeout_ns=12_000_000 +bypass_alert_ready_to_end_check=1 +en_jitter=1 +en_scb_tl_err_chk=0 +cal_sys_clk _70mhz=1 +sw_build_device=sim_dv +sw_images=sram_ctrl_scrambled_access_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2688565999 -assert nopostproc +UVM_TESTNA ME=chip_base_test +UVM_TEST_SEQ=chip_sw_sram_ctrl_scrambled_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/ default.vdb -cm_log /dev/null -cm_name 2.chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq.2688565999 |
| Directory | /workspace/2.chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq/latest |
| Test location | /workspace/coverage/default/2.chip_sw_sram_ctrl_smoketest.2711077762 |
| Short name | T288 |
| Test name | |
| Test status | |
| Simulation time | 2470945710 ps |
| CPU time | 205.43 seconds |
| Started | Aug 13 07:33:05 PM PDT 24 |
| Finished | Aug 13 07:36:31 PM PDT 24 |
| Peak memory | 610212 kb |
| Host | smart-e9ed043c-3eae-4692-913c-9acee93d5e32 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=sram_ctrl_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2711077762 -assert nopostproc +UVM_TESTNAM E=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 2.chip_sw_sram_ctrl_smoketest.2711077762 |
| Directory | /workspace/2.chip_sw_sram_ctrl_smoketest/latest |
| Test location | /workspace/coverage/default/2.chip_sw_sysrst_ctrl_ec_rst_l.3902165265 |
| Short name | T22 |
| Test name | |
| Test status | |
| Simulation time | 20576051958 ps |
| CPU time | 2997.96 seconds |
| Started | Aug 13 07:25:45 PM PDT 24 |
| Finished | Aug 13 08:15:43 PM PDT 24 |
| Peak memory | 611572 kb |
| Host | smart-ac6656e2-9b19-477d-970c-157b8484b421 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=sysrst_ctrl_ec_rst_l_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3902165265 -assert nopostproc +UVM_T ESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sysrst_ctrl_ec_rst_l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/d efault.vdb -cm_log /dev/null -cm_name 2.chip_sw_sysrst_ctrl_ec_rst_l.3902165265 |
| Directory | /workspace/2.chip_sw_sysrst_ctrl_ec_rst_l/latest |
| Test location | /workspace/coverage/default/2.chip_sw_sysrst_ctrl_in_irq.1581313575 |
| Short name | T218 |
| Test name | |
| Test status | |
| Simulation time | 4012844277 ps |
| CPU time | 576.98 seconds |
| Started | Aug 13 07:26:44 PM PDT 24 |
| Finished | Aug 13 07:36:24 PM PDT 24 |
| Peak memory | 614028 kb |
| Host | smart-842b3d26-a863-4f8e-81d1-563834155f3d |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=sysrst_ctrl_in_irq_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1581313575 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sysrst_ctrl_in_irq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau lt.vdb -cm_log /dev/null -cm_name 2.chip_sw_sysrst_ctrl_in_irq.1581313575 |
| Directory | /workspace/2.chip_sw_sysrst_ctrl_in_irq/latest |
| Test location | /workspace/coverage/default/2.chip_sw_sysrst_ctrl_inputs.407658474 |
| Short name | T1265 |
| Test name | |
| Test status | |
| Simulation time | 3540208911 ps |
| CPU time | 345.86 seconds |
| Started | Aug 13 07:26:20 PM PDT 24 |
| Finished | Aug 13 07:32:07 PM PDT 24 |
| Peak memory | 614028 kb |
| Host | smart-d235ac0d-6856-40cb-b161-47d233267a05 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=sysrst_ctrl_inputs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=407658474 -assert nopostproc +UVM_TEST NAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sysrst_ctrl_inputs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul t.vdb -cm_log /dev/null -cm_name 2.chip_sw_sysrst_ctrl_inputs.407658474 |
| Directory | /workspace/2.chip_sw_sysrst_ctrl_inputs/latest |
| Test location | /workspace/coverage/default/2.chip_sw_sysrst_ctrl_outputs.3513679825 |
| Short name | T1398 |
| Test name | |
| Test status | |
| Simulation time | 3827660976 ps |
| CPU time | 392.76 seconds |
| Started | Aug 13 07:28:02 PM PDT 24 |
| Finished | Aug 13 07:34:35 PM PDT 24 |
| Peak memory | 610616 kb |
| Host | smart-49c9a234-8171-4c49-b55c-c1138876762a |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=sysrst_ctrl_outputs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3513679825 -assert nopostproc +UVM_TE STNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sysrst_ctrl_outputs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def ault.vdb -cm_log /dev/null -cm_name 2.chip_sw_sysrst_ctrl_outputs.3513679825 |
| Directory | /workspace/2.chip_sw_sysrst_ctrl_outputs/latest |
| Test location | /workspace/coverage/default/2.chip_sw_sysrst_ctrl_reset.1367809953 |
| Short name | T1371 |
| Test name | |
| Test status | |
| Simulation time | 24726174068 ps |
| CPU time | 1565.24 seconds |
| Started | Aug 13 07:35:36 PM PDT 24 |
| Finished | Aug 13 08:01:42 PM PDT 24 |
| Peak memory | 614904 kb |
| Host | smart-eb41cde7-8d33-43f2-9c37-1d3e010389c3 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=36_000_000 +sw_build_device=sim_dv +sw_images=sysrst_ctrl_reset_test:1:new_rules,test_rom:0 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13678099 53 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sysrst_ctrl_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_sysrst_ctrl_reset.1367809953 |
| Directory | /workspace/2.chip_sw_sysrst_ctrl_reset/latest |
| Test location | /workspace/coverage/default/2.chip_sw_sysrst_ctrl_ulp_z3_wakeup.1259876016 |
| Short name | T34 |
| Test name | |
| Test status | |
| Simulation time | 4908221708 ps |
| CPU time | 446.16 seconds |
| Started | Aug 13 07:26:15 PM PDT 24 |
| Finished | Aug 13 07:33:42 PM PDT 24 |
| Peak memory | 610472 kb |
| Host | smart-27fd95c4-a3c7-4506-8e87-41ab8ddb7b3f |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=sysrst_ctrl_ulp_z3_wakeup_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1259876016 -assert nopostproc + UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sysrst_ctrl_ulp_z3_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/ coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_sysrst_ctrl_ulp_z3_wakeup.1259876016 |
| Directory | /workspace/2.chip_sw_sysrst_ctrl_ulp_z3_wakeup/latest |
| Test location | /workspace/coverage/default/2.chip_sw_uart_rand_baudrate.2249792964 |
| Short name | T1015 |
| Test name | |
| Test status | |
| Simulation time | 3973040802 ps |
| CPU time | 580.57 seconds |
| Started | Aug 13 07:23:07 PM PDT 24 |
| Finished | Aug 13 07:32:48 PM PDT 24 |
| Peak memory | 620172 kb |
| Host | smart-72a25231-de04-49f9-8b5d-f41b3f2e717f |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random _seed=2249792964 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_uart_rand_baudrate.2249792964 |
| Directory | /workspace/2.chip_sw_uart_rand_baudrate/latest |
| Test location | /workspace/coverage/default/2.chip_sw_uart_smoketest.1390180454 |
| Short name | T1124 |
| Test name | |
| Test status | |
| Simulation time | 2557557376 ps |
| CPU time | 346.07 seconds |
| Started | Aug 13 07:31:47 PM PDT 24 |
| Finished | Aug 13 07:37:33 PM PDT 24 |
| Peak memory | 615576 kb |
| Host | smart-1013f42f-84e4-4146-a02b-2b90fe395fcd |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=uart_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1390180454 -assert nopostproc +UVM_TESTNAME=chi p_base_test +UVM_TEST_SEQ=chip_sw_uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 2.chip_sw_uart_smoketest.1390180454 |
| Directory | /workspace/2.chip_sw_uart_smoketest/latest |
| Test location | /workspace/coverage/default/2.chip_sw_uart_tx_rx.4098570055 |
| Short name | T1342 |
| Test name | |
| Test status | |
| Simulation time | 3712424740 ps |
| CPU time | 619.7 seconds |
| Started | Aug 13 07:23:06 PM PDT 24 |
| Finished | Aug 13 07:33:27 PM PDT 24 |
| Peak memory | 620524 kb |
| Host | smart-99e8d6f5-d083-4420-87eb-7bce1f2bd763 |
| User | root |
| Command | /workspace/default/simv +uart_idx=0 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4098570055 -a ssert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ce/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_uart_tx_rx.4098570055 |
| Directory | /workspace/2.chip_sw_uart_tx_rx/latest |
| Test location | /workspace/coverage/default/2.chip_sw_uart_tx_rx_alt_clk_freq.1656846303 |
| Short name | T1107 |
| Test name | |
| Test status | |
| Simulation time | 8625359956 ps |
| CPU time | 1953.26 seconds |
| Started | Aug 13 07:25:23 PM PDT 24 |
| Finished | Aug 13 07:57:57 PM PDT 24 |
| Peak memory | 624832 kb |
| Host | smart-b1e41d75-a531-4c9d-8826-5227c6f4994a |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=80_000_000 +chip_clock_source=ChipClockSourceExternal96Mhz +calibrate_usb_clk=1 +sw_build_device=sim_dv +s w_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1656846303 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_b audrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_uart_tx_rx _alt_clk_freq.1656846303 |
| Directory | /workspace/2.chip_sw_uart_tx_rx_alt_clk_freq/latest |
| Test location | /workspace/coverage/default/2.chip_sw_uart_tx_rx_alt_clk_freq_low_speed.3796413947 |
| Short name | T1401 |
| Test name | |
| Test status | |
| Simulation time | 13926570530 ps |
| CPU time | 2360.14 seconds |
| Started | Aug 13 07:27:08 PM PDT 24 |
| Finished | Aug 13 08:06:29 PM PDT 24 |
| Peak memory | 625076 kb |
| Host | smart-4cd96e80-df6c-43ce-84fa-3117494bb4ca |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +chip_clock_source=ChipClockSourceExternal48Mhz +sw_build_device=sim_dv +s w_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3796413947 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_b audrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_uart_tx_rx _alt_clk_freq_low_speed.3796413947 |
| Directory | /workspace/2.chip_sw_uart_tx_rx_alt_clk_freq_low_speed/latest |
| Test location | /workspace/coverage/default/2.chip_sw_uart_tx_rx_bootstrap.1077876477 |
| Short name | T341 |
| Test name | |
| Test status | |
| Simulation time | 77447432508 ps |
| CPU time | 14753 seconds |
| Started | Aug 13 07:26:33 PM PDT 24 |
| Finished | Aug 13 11:32:30 PM PDT 24 |
| Peak memory | 635560 kb |
| Host | smart-e5eaf6a1-6e80-4f59-942f-a1fde5151a38 |
| User | root |
| Command | /workspace/default/simv +use_spi_load_bootstrap=1 +calibrate_usb_clk=1 +test_timeout_ns=160_000_000 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test :1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=1077876477 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_uart_tx_rx_bootstrap.1077876477 |
| Directory | /workspace/2.chip_sw_uart_tx_rx_bootstrap/latest |
| Test location | /workspace/coverage/default/2.chip_sw_uart_tx_rx_idx1.784126363 |
| Short name | T1260 |
| Test name | |
| Test status | |
| Simulation time | 4572254650 ps |
| CPU time | 715.33 seconds |
| Started | Aug 13 07:22:33 PM PDT 24 |
| Finished | Aug 13 07:34:29 PM PDT 24 |
| Peak memory | 620660 kb |
| Host | smart-ddf9b880-7ba0-4e44-8058-c49e8b3696e4 |
| User | root |
| Command | /workspace/default/simv +uart_idx=1 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=784126363 -as sert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac e/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_uart_tx_rx_idx1.784126363 |
| Directory | /workspace/2.chip_sw_uart_tx_rx_idx1/latest |
| Test location | /workspace/coverage/default/2.chip_sw_uart_tx_rx_idx2.1970327285 |
| Short name | T1002 |
| Test name | |
| Test status | |
| Simulation time | 4253689964 ps |
| CPU time | 718.42 seconds |
| Started | Aug 13 07:24:34 PM PDT 24 |
| Finished | Aug 13 07:36:33 PM PDT 24 |
| Peak memory | 620408 kb |
| Host | smart-091195e8-4153-49b2-81d5-e61210b70faa |
| User | root |
| Command | /workspace/default/simv +uart_idx=2 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1970327285 -a ssert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ce/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_uart_tx_rx_idx2.1970327285 |
| Directory | /workspace/2.chip_sw_uart_tx_rx_idx2/latest |
| Test location | /workspace/coverage/default/2.chip_sw_uart_tx_rx_idx3.4259772971 |
| Short name | T1220 |
| Test name | |
| Test status | |
| Simulation time | 3989175184 ps |
| CPU time | 574.05 seconds |
| Started | Aug 13 07:23:54 PM PDT 24 |
| Finished | Aug 13 07:33:29 PM PDT 24 |
| Peak memory | 620548 kb |
| Host | smart-5968515e-3362-45c6-aba9-9aa342052ef6 |
| User | root |
| Command | /workspace/default/simv +uart_idx=3 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4259772971 -a ssert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ce/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_uart_tx_rx_idx3.4259772971 |
| Directory | /workspace/2.chip_sw_uart_tx_rx_idx3/latest |
| Test location | /workspace/coverage/default/2.chip_tap_straps_dev.3860831500 |
| Short name | T1166 |
| Test name | |
| Test status | |
| Simulation time | 12080076276 ps |
| CPU time | 1122.32 seconds |
| Started | Aug 13 07:29:56 PM PDT 24 |
| Finished | Aug 13 07:48:38 PM PDT 24 |
| Peak memory | 633892 kb |
| Host | smart-dcd9332c-99a9-4fb5-b570-06341dd6d813 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStDev +create_jtag_riscv_map=1 +sw_build_device=sim_dv +sw_images=example_test_from_rom:0:test_in_rom: new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=3860831500 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_tap_straps_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_tap_straps_dev.3860831500 |
| Directory | /workspace/2.chip_tap_straps_dev/latest |
| Test location | /workspace/coverage/default/2.chip_tap_straps_prod.2475233018 |
| Short name | T68 |
| Test name | |
| Test status | |
| Simulation time | 11048837405 ps |
| CPU time | 1132.14 seconds |
| Started | Aug 13 07:28:32 PM PDT 24 |
| Finished | Aug 13 07:47:25 PM PDT 24 |
| Peak memory | 633900 kb |
| Host | smart-0e806776-b639-4c24-a3bd-a1bfd8084140 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStProd +create_jtag_riscv_map=1 +sw_build_device=sim_dv +sw_images=example_test_from_rom:0:test_in_rom :new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2475233018 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_tap_straps_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_tap_straps_prod.2475233018 |
| Directory | /workspace/2.chip_tap_straps_prod/latest |
| Test location | /workspace/coverage/default/2.chip_tap_straps_rma.3269465680 |
| Short name | T64 |
| Test name | |
| Test status | |
| Simulation time | 3902582394 ps |
| CPU time | 341.33 seconds |
| Started | Aug 13 07:29:13 PM PDT 24 |
| Finished | Aug 13 07:34:55 PM PDT 24 |
| Peak memory | 625584 kb |
| Host | smart-b66aa09d-0d83-4c67-8307-2441fcdf1f05 |
| User | root |
| Command | /workspace/default/simv +create_jtag_riscv_map=1 +sw_build_device=sim_dv +sw_images=example_test_from_rom:0:test_in_rom:new_rules +cdc_instrumentation _enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3269465680 -as sert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_tap_straps_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/c overage/default.vdb -cm_log /dev/null -cm_name 2.chip_tap_straps_rma.3269465680 |
| Directory | /workspace/2.chip_tap_straps_rma/latest |
| Test location | /workspace/coverage/default/2.chip_tap_straps_testunlock0.2258492468 |
| Short name | T1349 |
| Test name | |
| Test status | |
| Simulation time | 6722512297 ps |
| CPU time | 813.28 seconds |
| Started | Aug 13 07:29:45 PM PDT 24 |
| Finished | Aug 13 07:43:19 PM PDT 24 |
| Peak memory | 633268 kb |
| Host | smart-83fe01a7-a794-4fa3-a3cc-f8555b7a92ce |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStTestUnlocked0 +create_jtag_riscv_map=1 +sw_build_device=sim_dv +sw_images=example_test_from_rom:0:te st_in_rom:new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2258492468 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_tap_straps_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_tap_straps_testunlock0.2258492468 |
| Directory | /workspace/2.chip_tap_straps_testunlock0/latest |
| Test location | /workspace/coverage/default/2.rom_e2e_asm_init_dev.140379974 |
| Short name | T1201 |
| Test name | |
| Test status | |
| Simulation time | 16172134149 ps |
| CPU time | 3157.89 seconds |
| Started | Aug 13 07:35:57 PM PDT 24 |
| Finished | Aug 13 08:28:35 PM PDT 24 |
| Peak memory | 610924 kb |
| Host | smart-a2756af9-9262-4b55-95e6-eadb5b5b1fb2 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeCustom +sw_test_timeout_ns=20000000 +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_prod _key_0:1:ot_flash_binary,otp_img_e2e_bootstrap_entry_dev:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=140379974 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SE Q=chip_sw_rom_e2e_asm_init_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2 .rom_e2e_asm_init_dev.140379974 |
| Directory | /workspace/2.rom_e2e_asm_init_dev/latest |
| Test location | /workspace/coverage/default/2.rom_e2e_asm_init_prod.1892180366 |
| Short name | T1065 |
| Test name | |
| Test status | |
| Simulation time | 15988388900 ps |
| CPU time | 3625.13 seconds |
| Started | Aug 13 07:37:35 PM PDT 24 |
| Finished | Aug 13 08:38:00 PM PDT 24 |
| Peak memory | 610912 kb |
| Host | smart-3f3025f6-e434-4f1b-a8c0-5cfdd0f3d6e5 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeCustom +sw_test_timeout_ns=20000000 +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_prod _key_0:1:ot_flash_binary,otp_img_e2e_bootstrap_entry_prod:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1892180366 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_ SEQ=chip_sw_rom_e2e_asm_init_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_e2e_asm_init_prod.1892180366 |
| Directory | /workspace/2.rom_e2e_asm_init_prod/latest |
| Test location | /workspace/coverage/default/2.rom_e2e_asm_init_prod_end.1618127931 |
| Short name | T184 |
| Test name | |
| Test status | |
| Simulation time | 15993438569 ps |
| CPU time | 3636.03 seconds |
| Started | Aug 13 07:34:58 PM PDT 24 |
| Finished | Aug 13 08:35:34 PM PDT 24 |
| Peak memory | 610924 kb |
| Host | smart-64210f3e-e195-4781-a602-d10d7f84548b |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeCustom +sw_test_timeout_ns=20000000 +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_prod _key_0:1:ot_flash_binary,otp_img_e2e_bootstrap_entry_prod_end:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1618127931 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_T EST_SEQ=chip_sw_rom_e2e_asm_init_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 2.rom_e2e_asm_init_prod_end.1618127931 |
| Directory | /workspace/2.rom_e2e_asm_init_prod_end/latest |
| Test location | /workspace/coverage/default/2.rom_e2e_asm_init_rma.971536271 |
| Short name | T1040 |
| Test name | |
| Test status | |
| Simulation time | 15091866803 ps |
| CPU time | 3688.06 seconds |
| Started | Aug 13 07:37:25 PM PDT 24 |
| Finished | Aug 13 08:38:53 PM PDT 24 |
| Peak memory | 610916 kb |
| Host | smart-6d59d33c-9a12-49cc-81c7-2662f7a624a5 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeCustom +sw_test_timeout_ns=20000000 +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_prod _key_0:1:ot_flash_binary,otp_img_e2e_bootstrap_entry_rma:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=971536271 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SE Q=chip_sw_rom_e2e_asm_init_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2 .rom_e2e_asm_init_rma.971536271 |
| Directory | /workspace/2.rom_e2e_asm_init_rma/latest |
| Test location | /workspace/coverage/default/2.rom_e2e_asm_init_test_unlocked0.553221360 |
| Short name | T1116 |
| Test name | |
| Test status | |
| Simulation time | 11777531372 ps |
| CPU time | 2574.61 seconds |
| Started | Aug 13 07:36:40 PM PDT 24 |
| Finished | Aug 13 08:19:35 PM PDT 24 |
| Peak memory | 610524 kb |
| Host | smart-856ee221-98b1-437f-bfa0-182665f77b08 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeCustom +sw_test_timeout_ns=410_000_000 +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_p rod_key_0:1:ot_flash_binary,otp_img_e2e_bootstrap_entry_test_unlocked0:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY =UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=553221360 -assert nopostproc +UVM_TESTNAME=chip_base_tes t +UVM_TEST_SEQ=chip_sw_rom_e2e_asm_init_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n ull -cm_name 2.rom_e2e_asm_init_test_unlocked0.553221360 |
| Directory | /workspace/2.rom_e2e_asm_init_test_unlocked0/latest |
| Test location | /workspace/coverage/default/2.rom_e2e_keymgr_init_rom_ext_invalid_meas.3646461560 |
| Short name | T313 |
| Test name | |
| Test status | |
| Simulation time | 15059086952 ps |
| CPU time | 3497.92 seconds |
| Started | Aug 13 07:38:04 PM PDT 24 |
| Finished | Aug 13 08:36:23 PM PDT 24 |
| Peak memory | 610816 kb |
| Host | smart-faa02467-5472-4ee0-b89c-0e158b6b9229 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=40_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=rom_e2e_keymgr_init_otp_invalid _meas:1:new_rules,otp_img_keymgr_otp_invalid_meas:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3646461560 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip _sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_e2e_keymgr_in it_rom_ext_invalid_meas.3646461560 |
| Directory | /workspace/2.rom_e2e_keymgr_init_rom_ext_invalid_meas/latest |
| Test location | /workspace/coverage/default/2.rom_e2e_keymgr_init_rom_ext_meas.2112173996 |
| Short name | T1180 |
| Test name | |
| Test status | |
| Simulation time | 15402955088 ps |
| CPU time | 2955.96 seconds |
| Started | Aug 13 07:37:35 PM PDT 24 |
| Finished | Aug 13 08:26:51 PM PDT 24 |
| Peak memory | 610076 kb |
| Host | smart-8d5df4f9-f015-4e94-8547-4171e63fd9b9 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=40_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=rom_e2e_keymgr_init_otp_meas:1: new_rules,otp_img_keymgr_otp_meas:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2112173996 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_e2e_keymgr_init_rom_ext_meas.2112173996 |
| Directory | /workspace/2.rom_e2e_keymgr_init_rom_ext_meas/latest |
| Test location | /workspace/coverage/default/2.rom_e2e_keymgr_init_rom_ext_no_meas.1742213033 |
| Short name | T1268 |
| Test name | |
| Test status | |
| Simulation time | 14832290276 ps |
| CPU time | 4070.24 seconds |
| Started | Aug 13 07:36:27 PM PDT 24 |
| Finished | Aug 13 08:44:18 PM PDT 24 |
| Peak memory | 610536 kb |
| Host | smart-bebea48f-9ec2-4365-884e-c6ae4eb42552 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=40_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=rom_e2e_keymgr_init_otp_no_meas :1:new_rules,otp_img_keymgr_otp_no_meas:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1742213033 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_e2e_keymgr_init_rom_ext _no_meas.1742213033 |
| Directory | /workspace/2.rom_e2e_keymgr_init_rom_ext_no_meas/latest |
| Test location | /workspace/coverage/default/2.rom_e2e_shutdown_exception_c.4026564782 |
| Short name | T1223 |
| Test name | |
| Test status | |
| Simulation time | 14937293112 ps |
| CPU time | 3308.76 seconds |
| Started | Aug 13 07:37:22 PM PDT 24 |
| Finished | Aug 13 08:32:31 PM PDT 24 |
| Peak memory | 612052 kb |
| Host | smart-c8bb7137-0c6a-4c4c-8c71-e9283ab62b2b |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=40000000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=rom_e2e_shutdown_exception_c:1:ne w_rules,otp_img_secret2_locked_rma:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4026564782 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rom_e2e_shu tdown_exception_c_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_e2e_ shutdown_exception_c.4026564782 |
| Directory | /workspace/2.rom_e2e_shutdown_exception_c/latest |
| Test location | /workspace/coverage/default/2.rom_e2e_shutdown_output.2166433628 |
| Short name | T1063 |
| Test name | |
| Test status | |
| Simulation time | 25813720973 ps |
| CPU time | 3008.32 seconds |
| Started | Aug 13 07:35:48 PM PDT 24 |
| Finished | Aug 13 08:25:57 PM PDT 24 |
| Peak memory | 612212 kb |
| Host | smart-513771b8-d9fa-4622-b66f-dfdf28205179 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=20000000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_unsigned:1:ot_f lash_binary,otp_img_shutdown_output_test_unlocked0:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2166433628 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chi p_sw_rom_e2e_shutdown_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_e2e_shutdown_output.2166433628 |
| Directory | /workspace/2.rom_e2e_shutdown_output/latest |
| Test location | /workspace/coverage/default/2.rom_e2e_smoke.1007446187 |
| Short name | T1248 |
| Test name | |
| Test status | |
| Simulation time | 14658173280 ps |
| CPU time | 4059.28 seconds |
| Started | Aug 13 07:35:08 PM PDT 24 |
| Finished | Aug 13 08:42:48 PM PDT 24 |
| Peak memory | 610876 kb |
| Host | smart-cb0e4bcf-5aea-4a7f-87eb-139b795fb063 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=40000000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=rom_e2e_smoke:1:new_rules,otp_img _secret2_locked_rma:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_to p/hw/dv/tools/sim.tcl +ntb_random_seed=1007446187 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_e2e_smoke.1007446187 |
| Directory | /workspace/2.rom_e2e_smoke/latest |
| Test location | /workspace/coverage/default/2.rom_e2e_static_critical.552602328 |
| Short name | T1239 |
| Test name | |
| Test status | |
| Simulation time | 17034840856 ps |
| CPU time | 3275.54 seconds |
| Started | Aug 13 07:36:18 PM PDT 24 |
| Finished | Aug 13 08:30:55 PM PDT 24 |
| Peak memory | 610836 kb |
| Host | smart-dd46666b-10f3-4c1b-bb2d-2aae269c6df0 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=40000000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=rom_e2e_static_critical:1:new_rul es,otp_img_secret2_locked_rma:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=552602328 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_e2e_static_critical.552602328 |
| Directory | /workspace/2.rom_e2e_static_critical/latest |
| Test location | /workspace/coverage/default/2.rom_keymgr_functest.3266342343 |
| Short name | T1019 |
| Test name | |
| Test status | |
| Simulation time | 4523381944 ps |
| CPU time | 472.06 seconds |
| Started | Aug 13 07:31:07 PM PDT 24 |
| Finished | Aug 13 07:38:59 PM PDT 24 |
| Peak memory | 611168 kb |
| Host | smart-c3738283-3f04-4bd8-b34a-017dd3fb16e3 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=10_000_000 +sw_build_device=sim_dv +sw_images=keymgr_functest:1:new_rules,test_rom:0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3266342343 -ass ert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 2.rom_keymgr_functest.3266342343 |
| Directory | /workspace/2.rom_keymgr_functest/latest |
| Test location | /workspace/coverage/default/2.rom_raw_unlock.32951890 |
| Short name | T761 |
| Test name | |
| Test status | |
| Simulation time | 5739179146 ps |
| CPU time | 315.88 seconds |
| Started | Aug 13 07:33:05 PM PDT 24 |
| Finished | Aug 13 07:38:21 PM PDT 24 |
| Peak memory | 620176 kb |
| Host | smart-5ecbdb50-4ea0-4985-9835-2c25088918f0 |
| User | root |
| Command | /workspace/default/simv +do_creator_sw_cfg_ast_cfg=0 +sw_test_timeout_ns=200_000_000 +use_otp_image=OtpTypeLcStRaw +chip_clock_source=ChipClockSourceE xternal48Mhz +rom_prod_mode=1 +use_jtag_dmi=1 +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_test_key_0:1:ot_flash_binary,mask_ro m:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=32951890 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_raw_unlock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_raw_unlock.32951890 |
| Directory | /workspace/2.rom_raw_unlock/latest |
| Test location | /workspace/coverage/default/2.rom_volatile_raw_unlock.2127063757 |
| Short name | T1254 |
| Test name | |
| Test status | |
| Simulation time | 2960761351 ps |
| CPU time | 116.15 seconds |
| Started | Aug 13 07:31:12 PM PDT 24 |
| Finished | Aug 13 07:33:08 PM PDT 24 |
| Peak memory | 618184 kb |
| Host | smart-72a8a2ea-d8d6-4511-b525-ac4bd6c84425 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=200_000_000 +use_otp_image=OtpTypeLcStRaw +chip_clock_source=ChipClockSourceExternal48Mhz +rom_prod_mode=1 +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_test_key_0:1:ot_flash_binary,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2127063757 -assert nopostproc +UVM_ TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_volatile_raw_unlock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag e/default.vdb -cm_log /dev/null -cm_name 2.rom_volatile_raw_unlock.2127063757 |
| Directory | /workspace/2.rom_volatile_raw_unlock/latest |
| Test location | /workspace/coverage/default/23.chip_sw_alert_handler_lpg_sleep_mode_alerts.1677878052 |
| Short name | T406 |
| Test name | |
| Test status | |
| Simulation time | 3624926538 ps |
| CPU time | 397.6 seconds |
| Started | Aug 13 07:37:38 PM PDT 24 |
| Finished | Aug 13 07:44:16 PM PDT 24 |
| Peak memory | 649676 kb |
| Host | smart-5e3b90dc-62dd-4f85-b60d-10127489e5b7 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1677878052 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.chip_ sw_alert_handler_lpg_sleep_mode_alerts.1677878052 |
| Directory | /workspace/23.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/23.chip_sw_all_escalation_resets.846073740 |
| Short name | T810 |
| Test name | |
| Test status | |
| Simulation time | 4993367852 ps |
| CPU time | 608.27 seconds |
| Started | Aug 13 07:36:58 PM PDT 24 |
| Finished | Aug 13 07:47:06 PM PDT 24 |
| Peak memory | 650844 kb |
| Host | smart-cc3df199-9c0f-4f3b-a4ee-4e4f49f389fd |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 846073740 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.chip_sw_all_escalation_resets.846073740 |
| Directory | /workspace/23.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/25.chip_sw_all_escalation_resets.1917516314 |
| Short name | T836 |
| Test name | |
| Test status | |
| Simulation time | 4192171356 ps |
| CPU time | 466.03 seconds |
| Started | Aug 13 07:38:07 PM PDT 24 |
| Finished | Aug 13 07:45:54 PM PDT 24 |
| Peak memory | 650572 kb |
| Host | smart-8df79e13-a0e6-4ea2-9a7a-a9e7a1de00e6 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 1917516314 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.chip_sw_all_escalation_resets.1917516314 |
| Directory | /workspace/25.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/26.chip_sw_alert_handler_lpg_sleep_mode_alerts.3892839871 |
| Short name | T803 |
| Test name | |
| Test status | |
| Simulation time | 3561103512 ps |
| CPU time | 407.2 seconds |
| Started | Aug 13 07:38:01 PM PDT 24 |
| Finished | Aug 13 07:44:49 PM PDT 24 |
| Peak memory | 649668 kb |
| Host | smart-6dcf5253-01f8-469b-a4c2-33d40606610a |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3892839871 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.chip_ sw_alert_handler_lpg_sleep_mode_alerts.3892839871 |
| Directory | /workspace/26.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/27.chip_sw_alert_handler_lpg_sleep_mode_alerts.2631201260 |
| Short name | T447 |
| Test name | |
| Test status | |
| Simulation time | 4151943160 ps |
| CPU time | 439.65 seconds |
| Started | Aug 13 07:37:48 PM PDT 24 |
| Finished | Aug 13 07:45:08 PM PDT 24 |
| Peak memory | 649756 kb |
| Host | smart-cf1adf36-4fea-4dd0-a1cc-452e9693b1c2 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2631201260 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.chip_ sw_alert_handler_lpg_sleep_mode_alerts.2631201260 |
| Directory | /workspace/27.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/28.chip_sw_all_escalation_resets.1663632446 |
| Short name | T221 |
| Test name | |
| Test status | |
| Simulation time | 5071674688 ps |
| CPU time | 553.48 seconds |
| Started | Aug 13 07:38:49 PM PDT 24 |
| Finished | Aug 13 07:48:03 PM PDT 24 |
| Peak memory | 650472 kb |
| Host | smart-edffbf66-c256-40e4-be1f-0a872affc2f3 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 1663632446 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.chip_sw_all_escalation_resets.1663632446 |
| Directory | /workspace/28.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/29.chip_sw_alert_handler_lpg_sleep_mode_alerts.3668039390 |
| Short name | T812 |
| Test name | |
| Test status | |
| Simulation time | 3385965376 ps |
| CPU time | 391.74 seconds |
| Started | Aug 13 07:36:30 PM PDT 24 |
| Finished | Aug 13 07:43:02 PM PDT 24 |
| Peak memory | 649568 kb |
| Host | smart-1dec3c1b-15af-49f0-8eea-4730538b72a5 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3668039390 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.chip_ sw_alert_handler_lpg_sleep_mode_alerts.3668039390 |
| Directory | /workspace/29.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/29.chip_sw_all_escalation_resets.102302494 |
| Short name | T1064 |
| Test name | |
| Test status | |
| Simulation time | 5654937270 ps |
| CPU time | 703.96 seconds |
| Started | Aug 13 07:36:44 PM PDT 24 |
| Finished | Aug 13 07:48:28 PM PDT 24 |
| Peak memory | 620640 kb |
| Host | smart-1a596998-5181-448b-999a-cc7e0f73fed4 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 102302494 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.chip_sw_all_escalation_resets.102302494 |
| Directory | /workspace/29.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/3.chip_sw_alert_handler_lpg_sleep_mode_alerts.3451782364 |
| Short name | T792 |
| Test name | |
| Test status | |
| Simulation time | 4350681600 ps |
| CPU time | 483.67 seconds |
| Started | Aug 13 07:31:51 PM PDT 24 |
| Finished | Aug 13 07:39:56 PM PDT 24 |
| Peak memory | 649516 kb |
| Host | smart-9ef18c4e-d83e-4349-ab58-45466e5cc090 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3451782364 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.chip_s w_alert_handler_lpg_sleep_mode_alerts.3451782364 |
| Directory | /workspace/3.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/3.chip_sw_all_escalation_resets.3968675564 |
| Short name | T172 |
| Test name | |
| Test status | |
| Simulation time | 6057110666 ps |
| CPU time | 675.72 seconds |
| Started | Aug 13 07:34:42 PM PDT 24 |
| Finished | Aug 13 07:45:58 PM PDT 24 |
| Peak memory | 620568 kb |
| Host | smart-0035eacd-fc07-4f53-9c2f-fd55e8d2845b |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 3968675564 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.chip_sw_all_escalation_resets.3968675564 |
| Directory | /workspace/3.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/3.chip_sw_aon_timer_sleep_wdog_sleep_pause.2763444580 |
| Short name | T943 |
| Test name | |
| Test status | |
| Simulation time | 7278375128 ps |
| CPU time | 501.18 seconds |
| Started | Aug 13 07:33:03 PM PDT 24 |
| Finished | Aug 13 07:41:25 PM PDT 24 |
| Peak memory | 611212 kb |
| Host | smart-264ef999-943b-463f-be44-9be43264fa39 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=aon_timer_sleep_wdog_sleep_pause_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=2763444580 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.chip_sw_aon_timer_sleep_wdog_sleep_pause.2763444580 |
| Directory | /workspace/3.chip_sw_aon_timer_sleep_wdog_sleep_pause/latest |
| Test location | /workspace/coverage/default/3.chip_sw_csrng_edn_concurrency.2780321993 |
| Short name | T266 |
| Test name | |
| Test status | |
| Simulation time | 19660469520 ps |
| CPU time | 3938.18 seconds |
| Started | Aug 13 07:33:16 PM PDT 24 |
| Finished | Aug 13 08:38:55 PM PDT 24 |
| Peak memory | 611128 kb |
| Host | smart-9b05f0e3-cf33-4f12-b599-370f1e9c8822 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=140_000_000 +rng_srate_value_min=15 +rng_srate_value_max=20 +accelerate_cold_power_up_time=3 +accelerate_r egulators_power_up_time=2 +sw_build_device=sim_dv +sw_images=csrng_edn_concurrency_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2780321993 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd b -cm_log /dev/null -cm_name 3.chip_sw_csrng_edn_concurrency.2780321993 |
| Directory | /workspace/3.chip_sw_csrng_edn_concurrency/latest |
| Test location | /workspace/coverage/default/3.chip_sw_data_integrity_escalation.3387626044 |
| Short name | T233 |
| Test name | |
| Test status | |
| Simulation time | 5058207818 ps |
| CPU time | 577.75 seconds |
| Started | Aug 13 07:33:05 PM PDT 24 |
| Finished | Aug 13 07:42:43 PM PDT 24 |
| Peak memory | 611552 kb |
| Host | smart-36ae43a2-d333-4612-b454-f98b2ccabbe0 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=data_integrity_escalation_reset_test:1:new_rules,test_ro m:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=3387626044 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_data_integrity_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.chip_sw_data_integrity_escalation.3387626044 |
| Directory | /workspace/3.chip_sw_data_integrity_escalation/latest |
| Test location | /workspace/coverage/default/3.chip_sw_lc_ctrl_transition.644881728 |
| Short name | T1042 |
| Test name | |
| Test status | |
| Simulation time | 6557076898 ps |
| CPU time | 481.44 seconds |
| Started | Aug 13 07:32:30 PM PDT 24 |
| Finished | Aug 13 07:40:31 PM PDT 24 |
| Peak memory | 622072 kb |
| Host | smart-14f78287-bb91-429f-a4b5-e9d33adcd934 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=lc_ctrl_transition_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=644881728 -assert nopostproc +UVM_TEST NAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_transition_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul t.vdb -cm_log /dev/null -cm_name 3.chip_sw_lc_ctrl_transition.644881728 |
| Directory | /workspace/3.chip_sw_lc_ctrl_transition/latest |
| Test location | /workspace/coverage/default/3.chip_sw_sensor_ctrl_alert.1054124165 |
| Short name | T137 |
| Test name | |
| Test status | |
| Simulation time | 6450044922 ps |
| CPU time | 685.58 seconds |
| Started | Aug 13 07:32:08 PM PDT 24 |
| Finished | Aug 13 07:43:34 PM PDT 24 |
| Peak memory | 611204 kb |
| Host | smart-a5440ddf-862d-47c1-972d-f7d352dac110 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=40_000_000 +sw_build_device=sim_dv +sw_images=sensor_ctrl_alert_test:1:new_rules,test_rom:0 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10541241 65 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac e/coverage/default.vdb -cm_log /dev/null -cm_name 3.chip_sw_sensor_ctrl_alert.1054124165 |
| Directory | /workspace/3.chip_sw_sensor_ctrl_alert/latest |
| Test location | /workspace/coverage/default/3.chip_sw_uart_rand_baudrate.3382265515 |
| Short name | T1203 |
| Test name | |
| Test status | |
| Simulation time | 3866378440 ps |
| CPU time | 579.69 seconds |
| Started | Aug 13 07:33:24 PM PDT 24 |
| Finished | Aug 13 07:43:04 PM PDT 24 |
| Peak memory | 620152 kb |
| Host | smart-7192e0ec-a2e9-4c63-b9ad-db443e0cfc38 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random _seed=3382265515 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.chip_sw_uart_rand_baudrate.3382265515 |
| Directory | /workspace/3.chip_sw_uart_rand_baudrate/latest |
| Test location | /workspace/coverage/default/3.chip_sw_uart_tx_rx_alt_clk_freq.3697504381 |
| Short name | T1247 |
| Test name | |
| Test status | |
| Simulation time | 8655239267 ps |
| CPU time | 1737.92 seconds |
| Started | Aug 13 07:31:46 PM PDT 24 |
| Finished | Aug 13 08:00:45 PM PDT 24 |
| Peak memory | 624772 kb |
| Host | smart-6871e9aa-7bb5-4bf5-9cb2-28c300dd0411 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=80_000_000 +chip_clock_source=ChipClockSourceExternal96Mhz +calibrate_usb_clk=1 +sw_build_device=sim_dv +s w_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3697504381 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_b audrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.chip_sw_uart_tx_rx _alt_clk_freq.3697504381 |
| Directory | /workspace/3.chip_sw_uart_tx_rx_alt_clk_freq/latest |
| Test location | /workspace/coverage/default/3.chip_sw_uart_tx_rx_alt_clk_freq_low_speed.4072188381 |
| Short name | T994 |
| Test name | |
| Test status | |
| Simulation time | 4042432634 ps |
| CPU time | 544.47 seconds |
| Started | Aug 13 07:32:20 PM PDT 24 |
| Finished | Aug 13 07:41:25 PM PDT 24 |
| Peak memory | 624768 kb |
| Host | smart-b649ffbf-a3af-4743-ba3c-699311f79a0e |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +chip_clock_source=ChipClockSourceExternal48Mhz +sw_build_device=sim_dv +s w_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4072188381 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_b audrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.chip_sw_uart_tx_rx _alt_clk_freq_low_speed.4072188381 |
| Directory | /workspace/3.chip_sw_uart_tx_rx_alt_clk_freq_low_speed/latest |
| Test location | /workspace/coverage/default/3.chip_sw_uart_tx_rx_idx1.3141468085 |
| Short name | T1309 |
| Test name | |
| Test status | |
| Simulation time | 3799116818 ps |
| CPU time | 530.29 seconds |
| Started | Aug 13 07:33:09 PM PDT 24 |
| Finished | Aug 13 07:42:00 PM PDT 24 |
| Peak memory | 620432 kb |
| Host | smart-a1db5217-7583-406a-9718-10745f59e3ee |
| User | root |
| Command | /workspace/default/simv +uart_idx=1 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3141468085 -a ssert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ce/coverage/default.vdb -cm_log /dev/null -cm_name 3.chip_sw_uart_tx_rx_idx1.3141468085 |
| Directory | /workspace/3.chip_sw_uart_tx_rx_idx1/latest |
| Test location | /workspace/coverage/default/3.chip_sw_uart_tx_rx_idx3.2619886452 |
| Short name | T366 |
| Test name | |
| Test status | |
| Simulation time | 4837860828 ps |
| CPU time | 491.68 seconds |
| Started | Aug 13 07:33:28 PM PDT 24 |
| Finished | Aug 13 07:41:40 PM PDT 24 |
| Peak memory | 620884 kb |
| Host | smart-d22aae09-c2cf-4f43-a93e-f13f82e46fb8 |
| User | root |
| Command | /workspace/default/simv +uart_idx=3 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2619886452 -a ssert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ce/coverage/default.vdb -cm_log /dev/null -cm_name 3.chip_sw_uart_tx_rx_idx3.2619886452 |
| Directory | /workspace/3.chip_sw_uart_tx_rx_idx3/latest |
| Test location | /workspace/coverage/default/3.chip_tap_straps_dev.2156718462 |
| Short name | T737 |
| Test name | |
| Test status | |
| Simulation time | 12504808200 ps |
| CPU time | 1260.2 seconds |
| Started | Aug 13 07:32:48 PM PDT 24 |
| Finished | Aug 13 07:53:48 PM PDT 24 |
| Peak memory | 625764 kb |
| Host | smart-65d0c7d9-931a-4a89-9838-b5a7793a7858 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStDev +create_jtag_riscv_map=1 +sw_build_device=sim_dv +sw_images=example_test_from_rom:0:test_in_rom: new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=2156718462 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_tap_straps_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.chip_tap_straps_dev.2156718462 |
| Directory | /workspace/3.chip_tap_straps_dev/latest |
| Test location | /workspace/coverage/default/3.chip_tap_straps_prod.1570233976 |
| Short name | T1089 |
| Test name | |
| Test status | |
| Simulation time | 8914323372 ps |
| CPU time | 1080.5 seconds |
| Started | Aug 13 07:31:50 PM PDT 24 |
| Finished | Aug 13 07:49:51 PM PDT 24 |
| Peak memory | 625640 kb |
| Host | smart-76ca95cb-c77d-411f-9a16-728ade2288f1 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStProd +create_jtag_riscv_map=1 +sw_build_device=sim_dv +sw_images=example_test_from_rom:0:test_in_rom :new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1570233976 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_tap_straps_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.chip_tap_straps_prod.1570233976 |
| Directory | /workspace/3.chip_tap_straps_prod/latest |
| Test location | /workspace/coverage/default/3.chip_tap_straps_rma.172548908 |
| Short name | T1322 |
| Test name | |
| Test status | |
| Simulation time | 2423036014 ps |
| CPU time | 189.09 seconds |
| Started | Aug 13 07:32:24 PM PDT 24 |
| Finished | Aug 13 07:35:33 PM PDT 24 |
| Peak memory | 625660 kb |
| Host | smart-19d0e87c-4681-45aa-96f9-e50895ea1066 |
| User | root |
| Command | /workspace/default/simv +create_jtag_riscv_map=1 +sw_build_device=sim_dv +sw_images=example_test_from_rom:0:test_in_rom:new_rules +cdc_instrumentation _enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=172548908 -ass ert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_tap_straps_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co verage/default.vdb -cm_log /dev/null -cm_name 3.chip_tap_straps_rma.172548908 |
| Directory | /workspace/3.chip_tap_straps_rma/latest |
| Test location | /workspace/coverage/default/3.chip_tap_straps_testunlock0.1182303571 |
| Short name | T1329 |
| Test name | |
| Test status | |
| Simulation time | 2731385499 ps |
| CPU time | 170.8 seconds |
| Started | Aug 13 07:31:40 PM PDT 24 |
| Finished | Aug 13 07:34:31 PM PDT 24 |
| Peak memory | 624288 kb |
| Host | smart-e3f5faba-ca26-46c2-8621-cbb349209620 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStTestUnlocked0 +create_jtag_riscv_map=1 +sw_build_device=sim_dv +sw_images=example_test_from_rom:0:te st_in_rom:new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1182303571 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_tap_straps_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.chip_tap_straps_testunlock0.1182303571 |
| Directory | /workspace/3.chip_tap_straps_testunlock0/latest |
| Test location | /workspace/coverage/default/31.chip_sw_all_escalation_resets.1786950989 |
| Short name | T1263 |
| Test name | |
| Test status | |
| Simulation time | 4645010232 ps |
| CPU time | 521.77 seconds |
| Started | Aug 13 07:35:39 PM PDT 24 |
| Finished | Aug 13 07:44:21 PM PDT 24 |
| Peak memory | 650880 kb |
| Host | smart-d4be233e-c761-4697-a9ab-e8c48a1af1dd |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 1786950989 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.chip_sw_all_escalation_resets.1786950989 |
| Directory | /workspace/31.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/32.chip_sw_all_escalation_resets.1841777264 |
| Short name | T786 |
| Test name | |
| Test status | |
| Simulation time | 5286692648 ps |
| CPU time | 770.84 seconds |
| Started | Aug 13 07:35:41 PM PDT 24 |
| Finished | Aug 13 07:48:32 PM PDT 24 |
| Peak memory | 650756 kb |
| Host | smart-8f639741-c6b3-4e7f-af28-da21b36fe10d |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 1841777264 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.chip_sw_all_escalation_resets.1841777264 |
| Directory | /workspace/32.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/33.chip_sw_all_escalation_resets.2354485233 |
| Short name | T234 |
| Test name | |
| Test status | |
| Simulation time | 4540794172 ps |
| CPU time | 573.37 seconds |
| Started | Aug 13 07:36:48 PM PDT 24 |
| Finished | Aug 13 07:46:22 PM PDT 24 |
| Peak memory | 650808 kb |
| Host | smart-124febf2-b5d5-4862-bd09-b40785f2c860 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 2354485233 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.chip_sw_all_escalation_resets.2354485233 |
| Directory | /workspace/33.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/34.chip_sw_alert_handler_lpg_sleep_mode_alerts.1113513471 |
| Short name | T837 |
| Test name | |
| Test status | |
| Simulation time | 4273629160 ps |
| CPU time | 409.1 seconds |
| Started | Aug 13 07:36:49 PM PDT 24 |
| Finished | Aug 13 07:43:39 PM PDT 24 |
| Peak memory | 649524 kb |
| Host | smart-e06c73de-3f3a-4238-803e-865b120be66a |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1113513471 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.chip_ sw_alert_handler_lpg_sleep_mode_alerts.1113513471 |
| Directory | /workspace/34.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/35.chip_sw_alert_handler_lpg_sleep_mode_alerts.1393777910 |
| Short name | T1207 |
| Test name | |
| Test status | |
| Simulation time | 3947724538 ps |
| CPU time | 364.99 seconds |
| Started | Aug 13 07:36:51 PM PDT 24 |
| Finished | Aug 13 07:42:56 PM PDT 24 |
| Peak memory | 649868 kb |
| Host | smart-1f6f4af8-8f98-4f52-ab52-20e948461da5 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1393777910 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.chip_ sw_alert_handler_lpg_sleep_mode_alerts.1393777910 |
| Directory | /workspace/35.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/35.chip_sw_all_escalation_resets.247435101 |
| Short name | T827 |
| Test name | |
| Test status | |
| Simulation time | 5596288120 ps |
| CPU time | 783.35 seconds |
| Started | Aug 13 07:37:20 PM PDT 24 |
| Finished | Aug 13 07:50:24 PM PDT 24 |
| Peak memory | 650732 kb |
| Host | smart-dc515b57-2f8d-471e-8478-c7b284aa34a3 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 247435101 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.chip_sw_all_escalation_resets.247435101 |
| Directory | /workspace/35.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/36.chip_sw_all_escalation_resets.1130572295 |
| Short name | T759 |
| Test name | |
| Test status | |
| Simulation time | 5829197760 ps |
| CPU time | 711.45 seconds |
| Started | Aug 13 07:36:42 PM PDT 24 |
| Finished | Aug 13 07:48:34 PM PDT 24 |
| Peak memory | 650720 kb |
| Host | smart-b8528441-0469-4440-83a1-83098f898eef |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 1130572295 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.chip_sw_all_escalation_resets.1130572295 |
| Directory | /workspace/36.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/38.chip_sw_alert_handler_lpg_sleep_mode_alerts.314517503 |
| Short name | T806 |
| Test name | |
| Test status | |
| Simulation time | 4051205808 ps |
| CPU time | 435.2 seconds |
| Started | Aug 13 07:36:14 PM PDT 24 |
| Finished | Aug 13 07:43:30 PM PDT 24 |
| Peak memory | 649276 kb |
| Host | smart-3e3f2c14-107a-4116-9791-ea5e8a6e5474 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=314517503 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all _escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.chip_s w_alert_handler_lpg_sleep_mode_alerts.314517503 |
| Directory | /workspace/38.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/38.chip_sw_all_escalation_resets.1440032379 |
| Short name | T1066 |
| Test name | |
| Test status | |
| Simulation time | 5833388164 ps |
| CPU time | 583.18 seconds |
| Started | Aug 13 07:40:18 PM PDT 24 |
| Finished | Aug 13 07:50:02 PM PDT 24 |
| Peak memory | 650420 kb |
| Host | smart-61c6a937-7336-4aa0-ab3d-6d5d80e653e0 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 1440032379 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.chip_sw_all_escalation_resets.1440032379 |
| Directory | /workspace/38.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/39.chip_sw_alert_handler_lpg_sleep_mode_alerts.743766676 |
| Short name | T379 |
| Test name | |
| Test status | |
| Simulation time | 4346462434 ps |
| CPU time | 441.87 seconds |
| Started | Aug 13 07:38:37 PM PDT 24 |
| Finished | Aug 13 07:45:59 PM PDT 24 |
| Peak memory | 649820 kb |
| Host | smart-552a7860-2d41-4b93-8a41-24501f417831 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=743766676 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all _escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.chip_s w_alert_handler_lpg_sleep_mode_alerts.743766676 |
| Directory | /workspace/39.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/39.chip_sw_all_escalation_resets.472122166 |
| Short name | T1365 |
| Test name | |
| Test status | |
| Simulation time | 5092572780 ps |
| CPU time | 628.73 seconds |
| Started | Aug 13 07:40:12 PM PDT 24 |
| Finished | Aug 13 07:50:41 PM PDT 24 |
| Peak memory | 650708 kb |
| Host | smart-b4a1fc12-54bb-4b13-8b68-695fa55e931c |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 472122166 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.chip_sw_all_escalation_resets.472122166 |
| Directory | /workspace/39.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/4.chip_sw_aon_timer_sleep_wdog_sleep_pause.1040862007 |
| Short name | T988 |
| Test name | |
| Test status | |
| Simulation time | 7022051950 ps |
| CPU time | 554.15 seconds |
| Started | Aug 13 07:31:47 PM PDT 24 |
| Finished | Aug 13 07:41:01 PM PDT 24 |
| Peak memory | 611160 kb |
| Host | smart-07f5c482-067a-4cd0-b882-a656c0b8a870 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=aon_timer_sleep_wdog_sleep_pause_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=1040862007 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.chip_sw_aon_timer_sleep_wdog_sleep_pause.1040862007 |
| Directory | /workspace/4.chip_sw_aon_timer_sleep_wdog_sleep_pause/latest |
| Test location | /workspace/coverage/default/4.chip_sw_csrng_edn_concurrency.1657329140 |
| Short name | T1376 |
| Test name | |
| Test status | |
| Simulation time | 18073445352 ps |
| CPU time | 3666.05 seconds |
| Started | Aug 13 07:32:17 PM PDT 24 |
| Finished | Aug 13 08:33:23 PM PDT 24 |
| Peak memory | 610876 kb |
| Host | smart-9724d92e-f2f5-4bc0-b638-004c256ba23c |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=140_000_000 +rng_srate_value_min=15 +rng_srate_value_max=20 +accelerate_cold_power_up_time=3 +accelerate_r egulators_power_up_time=2 +sw_build_device=sim_dv +sw_images=csrng_edn_concurrency_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1657329140 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd b -cm_log /dev/null -cm_name 4.chip_sw_csrng_edn_concurrency.1657329140 |
| Directory | /workspace/4.chip_sw_csrng_edn_concurrency/latest |
| Test location | /workspace/coverage/default/4.chip_sw_data_integrity_escalation.136042304 |
| Short name | T282 |
| Test name | |
| Test status | |
| Simulation time | 5605030400 ps |
| CPU time | 644.86 seconds |
| Started | Aug 13 07:32:40 PM PDT 24 |
| Finished | Aug 13 07:43:26 PM PDT 24 |
| Peak memory | 611960 kb |
| Host | smart-f71a8693-3733-4135-83d5-44f1eae95919 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=data_integrity_escalation_reset_test:1:new_rules,test_ro m:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=136042304 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_data_integrity_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.chip_sw_data_integrity_escalation.136042304 |
| Directory | /workspace/4.chip_sw_data_integrity_escalation/latest |
| Test location | /workspace/coverage/default/4.chip_sw_lc_ctrl_transition.1295418833 |
| Short name | T1030 |
| Test name | |
| Test status | |
| Simulation time | 9109061942 ps |
| CPU time | 1026.1 seconds |
| Started | Aug 13 07:32:42 PM PDT 24 |
| Finished | Aug 13 07:49:49 PM PDT 24 |
| Peak memory | 621944 kb |
| Host | smart-5cb49640-e160-490a-9d5b-658956ba6e33 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=lc_ctrl_transition_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1295418833 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_transition_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau lt.vdb -cm_log /dev/null -cm_name 4.chip_sw_lc_ctrl_transition.1295418833 |
| Directory | /workspace/4.chip_sw_lc_ctrl_transition/latest |
| Test location | /workspace/coverage/default/4.chip_sw_sensor_ctrl_alert.3292045829 |
| Short name | T134 |
| Test name | |
| Test status | |
| Simulation time | 5566631212 ps |
| CPU time | 789.57 seconds |
| Started | Aug 13 07:32:14 PM PDT 24 |
| Finished | Aug 13 07:45:24 PM PDT 24 |
| Peak memory | 611220 kb |
| Host | smart-d569faa1-3870-43ea-8b81-f5104197a6dc |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=40_000_000 +sw_build_device=sim_dv +sw_images=sensor_ctrl_alert_test:1:new_rules,test_rom:0 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32920458 29 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac e/coverage/default.vdb -cm_log /dev/null -cm_name 4.chip_sw_sensor_ctrl_alert.3292045829 |
| Directory | /workspace/4.chip_sw_sensor_ctrl_alert/latest |
| Test location | /workspace/coverage/default/4.chip_sw_uart_rand_baudrate.649508521 |
| Short name | T1241 |
| Test name | |
| Test status | |
| Simulation time | 8888961044 ps |
| CPU time | 1567.37 seconds |
| Started | Aug 13 07:33:48 PM PDT 24 |
| Finished | Aug 13 07:59:56 PM PDT 24 |
| Peak memory | 620136 kb |
| Host | smart-7aa3712a-b555-460c-8bb6-e4e68881c89c |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random _seed=649508521 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.chip_sw_uart_rand_baudrate.649508521 |
| Directory | /workspace/4.chip_sw_uart_rand_baudrate/latest |
| Test location | /workspace/coverage/default/4.chip_sw_uart_tx_rx.1583445177 |
| Short name | T1105 |
| Test name | |
| Test status | |
| Simulation time | 4848435800 ps |
| CPU time | 579.64 seconds |
| Started | Aug 13 07:35:19 PM PDT 24 |
| Finished | Aug 13 07:44:59 PM PDT 24 |
| Peak memory | 620832 kb |
| Host | smart-aed986ef-e509-4f24-8c52-b6d4253f0ea3 |
| User | root |
| Command | /workspace/default/simv +uart_idx=0 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1583445177 -a ssert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ce/coverage/default.vdb -cm_log /dev/null -cm_name 4.chip_sw_uart_tx_rx.1583445177 |
| Directory | /workspace/4.chip_sw_uart_tx_rx/latest |
| Test location | /workspace/coverage/default/4.chip_sw_uart_tx_rx_alt_clk_freq.1734574489 |
| Short name | T1092 |
| Test name | |
| Test status | |
| Simulation time | 4330742818 ps |
| CPU time | 545.95 seconds |
| Started | Aug 13 07:33:44 PM PDT 24 |
| Finished | Aug 13 07:42:50 PM PDT 24 |
| Peak memory | 619964 kb |
| Host | smart-e8dec7d8-86d9-4e0c-8b7a-cfce1e29d424 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=80_000_000 +chip_clock_source=ChipClockSourceExternal96Mhz +calibrate_usb_clk=1 +sw_build_device=sim_dv +s w_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1734574489 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_b audrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.chip_sw_uart_tx_rx _alt_clk_freq.1734574489 |
| Directory | /workspace/4.chip_sw_uart_tx_rx_alt_clk_freq/latest |
| Test location | /workspace/coverage/default/4.chip_sw_uart_tx_rx_alt_clk_freq_low_speed.999891861 |
| Short name | T274 |
| Test name | |
| Test status | |
| Simulation time | 4219170995 ps |
| CPU time | 619.86 seconds |
| Started | Aug 13 07:35:30 PM PDT 24 |
| Finished | Aug 13 07:45:50 PM PDT 24 |
| Peak memory | 625092 kb |
| Host | smart-4f366696-331d-422e-aa34-0a1522a8fb20 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +chip_clock_source=ChipClockSourceExternal48Mhz +sw_build_device=sim_dv +s w_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=999891861 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_ba udrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.chip_sw_uart_tx_rx_ alt_clk_freq_low_speed.999891861 |
| Directory | /workspace/4.chip_sw_uart_tx_rx_alt_clk_freq_low_speed/latest |
| Test location | /workspace/coverage/default/4.chip_sw_uart_tx_rx_idx1.748248158 |
| Short name | T1250 |
| Test name | |
| Test status | |
| Simulation time | 4167922004 ps |
| CPU time | 669.41 seconds |
| Started | Aug 13 07:33:48 PM PDT 24 |
| Finished | Aug 13 07:44:57 PM PDT 24 |
| Peak memory | 620484 kb |
| Host | smart-1a663c38-a64d-427e-b0ea-841f20252a9f |
| User | root |
| Command | /workspace/default/simv +uart_idx=1 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=748248158 -as sert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac e/coverage/default.vdb -cm_log /dev/null -cm_name 4.chip_sw_uart_tx_rx_idx1.748248158 |
| Directory | /workspace/4.chip_sw_uart_tx_rx_idx1/latest |
| Test location | /workspace/coverage/default/4.chip_sw_uart_tx_rx_idx2.4177583722 |
| Short name | T1052 |
| Test name | |
| Test status | |
| Simulation time | 4027743256 ps |
| CPU time | 822.04 seconds |
| Started | Aug 13 07:31:31 PM PDT 24 |
| Finished | Aug 13 07:45:13 PM PDT 24 |
| Peak memory | 620456 kb |
| Host | smart-ca9f6e82-a6a7-46ef-b43c-d9ee2aab30f1 |
| User | root |
| Command | /workspace/default/simv +uart_idx=2 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4177583722 -a ssert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ce/coverage/default.vdb -cm_log /dev/null -cm_name 4.chip_sw_uart_tx_rx_idx2.4177583722 |
| Directory | /workspace/4.chip_sw_uart_tx_rx_idx2/latest |
| Test location | /workspace/coverage/default/4.chip_sw_uart_tx_rx_idx3.4143976143 |
| Short name | T1133 |
| Test name | |
| Test status | |
| Simulation time | 4505553404 ps |
| CPU time | 695.46 seconds |
| Started | Aug 13 07:32:50 PM PDT 24 |
| Finished | Aug 13 07:44:26 PM PDT 24 |
| Peak memory | 620776 kb |
| Host | smart-f3feaea0-b23d-4954-9014-b557b4ad23f6 |
| User | root |
| Command | /workspace/default/simv +uart_idx=3 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4143976143 -a ssert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ce/coverage/default.vdb -cm_log /dev/null -cm_name 4.chip_sw_uart_tx_rx_idx3.4143976143 |
| Directory | /workspace/4.chip_sw_uart_tx_rx_idx3/latest |
| Test location | /workspace/coverage/default/4.chip_tap_straps_dev.3895668110 |
| Short name | T67 |
| Test name | |
| Test status | |
| Simulation time | 6716045861 ps |
| CPU time | 630.53 seconds |
| Started | Aug 13 07:31:32 PM PDT 24 |
| Finished | Aug 13 07:42:03 PM PDT 24 |
| Peak memory | 625652 kb |
| Host | smart-72f94bbe-12d2-4173-8f7a-f8c554d941f6 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStDev +create_jtag_riscv_map=1 +sw_build_device=sim_dv +sw_images=example_test_from_rom:0:test_in_rom: new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=3895668110 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_tap_straps_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.chip_tap_straps_dev.3895668110 |
| Directory | /workspace/4.chip_tap_straps_dev/latest |
| Test location | /workspace/coverage/default/4.chip_tap_straps_prod.352586742 |
| Short name | T1134 |
| Test name | |
| Test status | |
| Simulation time | 9849289380 ps |
| CPU time | 851.92 seconds |
| Started | Aug 13 07:34:28 PM PDT 24 |
| Finished | Aug 13 07:48:40 PM PDT 24 |
| Peak memory | 625636 kb |
| Host | smart-8fc2a92a-c596-4dd7-aa34-72c99399ab81 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStProd +create_jtag_riscv_map=1 +sw_build_device=sim_dv +sw_images=example_test_from_rom:0:test_in_rom :new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=352586742 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_tap_straps_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.chip_tap_straps_prod.352586742 |
| Directory | /workspace/4.chip_tap_straps_prod/latest |
| Test location | /workspace/coverage/default/4.chip_tap_straps_rma.1517185286 |
| Short name | T1198 |
| Test name | |
| Test status | |
| Simulation time | 3513996571 ps |
| CPU time | 233.63 seconds |
| Started | Aug 13 07:31:55 PM PDT 24 |
| Finished | Aug 13 07:35:49 PM PDT 24 |
| Peak memory | 625668 kb |
| Host | smart-852f7364-9308-49f4-9684-26daea4223aa |
| User | root |
| Command | /workspace/default/simv +create_jtag_riscv_map=1 +sw_build_device=sim_dv +sw_images=example_test_from_rom:0:test_in_rom:new_rules +cdc_instrumentation _enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1517185286 -as sert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_tap_straps_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/c overage/default.vdb -cm_log /dev/null -cm_name 4.chip_tap_straps_rma.1517185286 |
| Directory | /workspace/4.chip_tap_straps_rma/latest |
| Test location | /workspace/coverage/default/4.chip_tap_straps_testunlock0.4003642873 |
| Short name | T65 |
| Test name | |
| Test status | |
| Simulation time | 3439631037 ps |
| CPU time | 277.92 seconds |
| Started | Aug 13 07:34:24 PM PDT 24 |
| Finished | Aug 13 07:39:02 PM PDT 24 |
| Peak memory | 625708 kb |
| Host | smart-7cff1c39-1381-4b68-b143-30bec6dbccc9 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStTestUnlocked0 +create_jtag_riscv_map=1 +sw_build_device=sim_dv +sw_images=example_test_from_rom:0:te st_in_rom:new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4003642873 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_tap_straps_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.chip_tap_straps_testunlock0.4003642873 |
| Directory | /workspace/4.chip_tap_straps_testunlock0/latest |
| Test location | /workspace/coverage/default/40.chip_sw_all_escalation_resets.1288401798 |
| Short name | T849 |
| Test name | |
| Test status | |
| Simulation time | 4747501474 ps |
| CPU time | 662.71 seconds |
| Started | Aug 13 07:36:12 PM PDT 24 |
| Finished | Aug 13 07:47:16 PM PDT 24 |
| Peak memory | 650808 kb |
| Host | smart-8da4c436-7965-4340-98fa-33a8d1901058 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 1288401798 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.chip_sw_all_escalation_resets.1288401798 |
| Directory | /workspace/40.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/41.chip_sw_all_escalation_resets.3319099001 |
| Short name | T62 |
| Test name | |
| Test status | |
| Simulation time | 5905440248 ps |
| CPU time | 628.17 seconds |
| Started | Aug 13 07:41:29 PM PDT 24 |
| Finished | Aug 13 07:51:58 PM PDT 24 |
| Peak memory | 650788 kb |
| Host | smart-abcaabab-c3df-4833-8f68-3ad1f976406a |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 3319099001 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.chip_sw_all_escalation_resets.3319099001 |
| Directory | /workspace/41.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/42.chip_sw_alert_handler_lpg_sleep_mode_alerts.4052991057 |
| Short name | T860 |
| Test name | |
| Test status | |
| Simulation time | 3476111718 ps |
| CPU time | 414.75 seconds |
| Started | Aug 13 07:42:01 PM PDT 24 |
| Finished | Aug 13 07:48:56 PM PDT 24 |
| Peak memory | 649680 kb |
| Host | smart-124b9946-5263-48d0-85a5-14d3f04963a4 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4052991057 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.chip_ sw_alert_handler_lpg_sleep_mode_alerts.4052991057 |
| Directory | /workspace/42.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/43.chip_sw_alert_handler_lpg_sleep_mode_alerts.2970964866 |
| Short name | T1188 |
| Test name | |
| Test status | |
| Simulation time | 3494113152 ps |
| CPU time | 423.43 seconds |
| Started | Aug 13 07:37:05 PM PDT 24 |
| Finished | Aug 13 07:44:09 PM PDT 24 |
| Peak memory | 619636 kb |
| Host | smart-2ff2a023-3e74-48f5-a188-97cba7df0e52 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2970964866 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.chip_ sw_alert_handler_lpg_sleep_mode_alerts.2970964866 |
| Directory | /workspace/43.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/43.chip_sw_all_escalation_resets.3295810141 |
| Short name | T1320 |
| Test name | |
| Test status | |
| Simulation time | 6559255264 ps |
| CPU time | 626.91 seconds |
| Started | Aug 13 07:39:08 PM PDT 24 |
| Finished | Aug 13 07:49:35 PM PDT 24 |
| Peak memory | 620648 kb |
| Host | smart-468d773c-f117-43fc-9a56-fd4f187d2ca3 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 3295810141 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.chip_sw_all_escalation_resets.3295810141 |
| Directory | /workspace/43.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/44.chip_sw_alert_handler_lpg_sleep_mode_alerts.1806818948 |
| Short name | T857 |
| Test name | |
| Test status | |
| Simulation time | 3367975404 ps |
| CPU time | 400.9 seconds |
| Started | Aug 13 07:37:10 PM PDT 24 |
| Finished | Aug 13 07:43:52 PM PDT 24 |
| Peak memory | 649292 kb |
| Host | smart-5af89eb6-4bdf-49ed-abc3-2f2b4be19120 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1806818948 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.chip_ sw_alert_handler_lpg_sleep_mode_alerts.1806818948 |
| Directory | /workspace/44.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/44.chip_sw_all_escalation_resets.1306601336 |
| Short name | T789 |
| Test name | |
| Test status | |
| Simulation time | 4808047042 ps |
| CPU time | 614.56 seconds |
| Started | Aug 13 07:39:07 PM PDT 24 |
| Finished | Aug 13 07:49:22 PM PDT 24 |
| Peak memory | 650656 kb |
| Host | smart-e66e9f69-d925-4730-b4cc-607395d91e56 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 1306601336 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.chip_sw_all_escalation_resets.1306601336 |
| Directory | /workspace/44.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/45.chip_sw_alert_handler_lpg_sleep_mode_alerts.3768708413 |
| Short name | T1264 |
| Test name | |
| Test status | |
| Simulation time | 3098906136 ps |
| CPU time | 354.56 seconds |
| Started | Aug 13 07:39:39 PM PDT 24 |
| Finished | Aug 13 07:45:34 PM PDT 24 |
| Peak memory | 619668 kb |
| Host | smart-69f6d784-2a8a-402e-baee-78d9cf0a2b0d |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3768708413 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.chip_ sw_alert_handler_lpg_sleep_mode_alerts.3768708413 |
| Directory | /workspace/45.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/45.chip_sw_all_escalation_resets.427052306 |
| Short name | T1143 |
| Test name | |
| Test status | |
| Simulation time | 4794730840 ps |
| CPU time | 553.39 seconds |
| Started | Aug 13 07:38:37 PM PDT 24 |
| Finished | Aug 13 07:47:50 PM PDT 24 |
| Peak memory | 650752 kb |
| Host | smart-080fd346-a35f-4805-907e-13a535edf543 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 427052306 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.chip_sw_all_escalation_resets.427052306 |
| Directory | /workspace/45.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/46.chip_sw_alert_handler_lpg_sleep_mode_alerts.81682657 |
| Short name | T401 |
| Test name | |
| Test status | |
| Simulation time | 3413316660 ps |
| CPU time | 359.66 seconds |
| Started | Aug 13 07:36:19 PM PDT 24 |
| Finished | Aug 13 07:42:19 PM PDT 24 |
| Peak memory | 649908 kb |
| Host | smart-ed89e77a-314e-4a9a-b853-a36fd3e10d95 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=81682657 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_ escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.chip_sw _alert_handler_lpg_sleep_mode_alerts.81682657 |
| Directory | /workspace/46.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/46.chip_sw_all_escalation_resets.594239629 |
| Short name | T360 |
| Test name | |
| Test status | |
| Simulation time | 5622854904 ps |
| CPU time | 679.37 seconds |
| Started | Aug 13 07:39:04 PM PDT 24 |
| Finished | Aug 13 07:50:24 PM PDT 24 |
| Peak memory | 650748 kb |
| Host | smart-ab6379a7-d89c-4874-ac27-8c821ac1b9c6 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 594239629 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.chip_sw_all_escalation_resets.594239629 |
| Directory | /workspace/46.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/47.chip_sw_all_escalation_resets.2310910303 |
| Short name | T367 |
| Test name | |
| Test status | |
| Simulation time | 6076781872 ps |
| CPU time | 545.87 seconds |
| Started | Aug 13 07:41:35 PM PDT 24 |
| Finished | Aug 13 07:50:42 PM PDT 24 |
| Peak memory | 650436 kb |
| Host | smart-77bc5786-23c9-4537-8e09-6f5811894598 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 2310910303 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.chip_sw_all_escalation_resets.2310910303 |
| Directory | /workspace/47.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/48.chip_sw_alert_handler_lpg_sleep_mode_alerts.1694130432 |
| Short name | T1383 |
| Test name | |
| Test status | |
| Simulation time | 4117233280 ps |
| CPU time | 395.59 seconds |
| Started | Aug 13 07:38:11 PM PDT 24 |
| Finished | Aug 13 07:44:47 PM PDT 24 |
| Peak memory | 649448 kb |
| Host | smart-4534d359-1380-4edf-bf38-79ba518e4bdc |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1694130432 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.chip_ sw_alert_handler_lpg_sleep_mode_alerts.1694130432 |
| Directory | /workspace/48.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/49.chip_sw_all_escalation_resets.540616474 |
| Short name | T1094 |
| Test name | |
| Test status | |
| Simulation time | 5614686532 ps |
| CPU time | 506.33 seconds |
| Started | Aug 13 07:37:11 PM PDT 24 |
| Finished | Aug 13 07:45:37 PM PDT 24 |
| Peak memory | 650748 kb |
| Host | smart-1a5295bd-9301-4dd1-b83d-e50996932e51 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 540616474 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.chip_sw_all_escalation_resets.540616474 |
| Directory | /workspace/49.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/5.chip_sw_alert_handler_lpg_sleep_mode_alerts.915159629 |
| Short name | T392 |
| Test name | |
| Test status | |
| Simulation time | 4015228128 ps |
| CPU time | 305.46 seconds |
| Started | Aug 13 07:33:36 PM PDT 24 |
| Finished | Aug 13 07:38:42 PM PDT 24 |
| Peak memory | 649564 kb |
| Host | smart-683af762-2315-429c-836d-fea27ccf03f1 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=915159629 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all _escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.chip_sw _alert_handler_lpg_sleep_mode_alerts.915159629 |
| Directory | /workspace/5.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/5.chip_sw_csrng_edn_concurrency.1088309007 |
| Short name | T1024 |
| Test name | |
| Test status | |
| Simulation time | 16997201800 ps |
| CPU time | 3439.68 seconds |
| Started | Aug 13 07:34:29 PM PDT 24 |
| Finished | Aug 13 08:31:50 PM PDT 24 |
| Peak memory | 611124 kb |
| Host | smart-f7135f16-db19-450c-853d-62428c2fb095 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=140_000_000 +rng_srate_value_min=15 +rng_srate_value_max=20 +accelerate_cold_power_up_time=3 +accelerate_r egulators_power_up_time=2 +sw_build_device=sim_dv +sw_images=csrng_edn_concurrency_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1088309007 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd b -cm_log /dev/null -cm_name 5.chip_sw_csrng_edn_concurrency.1088309007 |
| Directory | /workspace/5.chip_sw_csrng_edn_concurrency/latest |
| Test location | /workspace/coverage/default/5.chip_sw_data_integrity_escalation.205921413 |
| Short name | T358 |
| Test name | |
| Test status | |
| Simulation time | 6364450278 ps |
| CPU time | 613.13 seconds |
| Started | Aug 13 07:33:20 PM PDT 24 |
| Finished | Aug 13 07:43:33 PM PDT 24 |
| Peak memory | 611732 kb |
| Host | smart-6cfc9121-f4d7-4fec-b986-bf472810e26a |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=data_integrity_escalation_reset_test:1:new_rules,test_ro m:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=205921413 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_data_integrity_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.chip_sw_data_integrity_escalation.205921413 |
| Directory | /workspace/5.chip_sw_data_integrity_escalation/latest |
| Test location | /workspace/coverage/default/5.chip_sw_lc_ctrl_transition.3587102203 |
| Short name | T1256 |
| Test name | |
| Test status | |
| Simulation time | 5529613535 ps |
| CPU time | 348.68 seconds |
| Started | Aug 13 07:33:15 PM PDT 24 |
| Finished | Aug 13 07:39:04 PM PDT 24 |
| Peak memory | 621680 kb |
| Host | smart-df54719b-1585-40a6-af25-ff4ffed7fc86 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=lc_ctrl_transition_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3587102203 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_transition_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau lt.vdb -cm_log /dev/null -cm_name 5.chip_sw_lc_ctrl_transition.3587102203 |
| Directory | /workspace/5.chip_sw_lc_ctrl_transition/latest |
| Test location | /workspace/coverage/default/5.chip_sw_uart_rand_baudrate.2622740227 |
| Short name | T356 |
| Test name | |
| Test status | |
| Simulation time | 4697249342 ps |
| CPU time | 709.41 seconds |
| Started | Aug 13 07:33:47 PM PDT 24 |
| Finished | Aug 13 07:45:37 PM PDT 24 |
| Peak memory | 620180 kb |
| Host | smart-e18c0bc6-f4a1-41e2-a67b-fefba03a095e |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random _seed=2622740227 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.chip_sw_uart_rand_baudrate.2622740227 |
| Directory | /workspace/5.chip_sw_uart_rand_baudrate/latest |
| Test location | /workspace/coverage/default/50.chip_sw_alert_handler_lpg_sleep_mode_alerts.930673652 |
| Short name | T859 |
| Test name | |
| Test status | |
| Simulation time | 4312895140 ps |
| CPU time | 418.12 seconds |
| Started | Aug 13 07:37:37 PM PDT 24 |
| Finished | Aug 13 07:44:36 PM PDT 24 |
| Peak memory | 649928 kb |
| Host | smart-ce73ac0c-9bd2-4c05-a59f-91edecb41b44 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=930673652 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all _escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 50.chip_s w_alert_handler_lpg_sleep_mode_alerts.930673652 |
| Directory | /workspace/50.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/51.chip_sw_alert_handler_lpg_sleep_mode_alerts.355021822 |
| Short name | T1148 |
| Test name | |
| Test status | |
| Simulation time | 4001489404 ps |
| CPU time | 473.56 seconds |
| Started | Aug 13 07:38:42 PM PDT 24 |
| Finished | Aug 13 07:46:35 PM PDT 24 |
| Peak memory | 649432 kb |
| Host | smart-edb6a402-c5a1-42af-b71e-5859454aa0d6 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=355021822 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all _escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 51.chip_s w_alert_handler_lpg_sleep_mode_alerts.355021822 |
| Directory | /workspace/51.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/51.chip_sw_all_escalation_resets.2747974183 |
| Short name | T428 |
| Test name | |
| Test status | |
| Simulation time | 5246176336 ps |
| CPU time | 744.28 seconds |
| Started | Aug 13 07:38:04 PM PDT 24 |
| Finished | Aug 13 07:50:28 PM PDT 24 |
| Peak memory | 650512 kb |
| Host | smart-d45f7a59-9ec5-40dc-8268-a6469bb25448 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 2747974183 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 51.chip_sw_all_escalation_resets.2747974183 |
| Directory | /workspace/51.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/52.chip_sw_alert_handler_lpg_sleep_mode_alerts.3715713810 |
| Short name | T1407 |
| Test name | |
| Test status | |
| Simulation time | 3605122412 ps |
| CPU time | 460.91 seconds |
| Started | Aug 13 07:43:19 PM PDT 24 |
| Finished | Aug 13 07:51:00 PM PDT 24 |
| Peak memory | 649664 kb |
| Host | smart-f554d12c-b25a-4c61-bf9e-947f0095db62 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3715713810 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 52.chip_ sw_alert_handler_lpg_sleep_mode_alerts.3715713810 |
| Directory | /workspace/52.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/52.chip_sw_all_escalation_resets.1984410290 |
| Short name | T838 |
| Test name | |
| Test status | |
| Simulation time | 4121768880 ps |
| CPU time | 486.24 seconds |
| Started | Aug 13 07:40:31 PM PDT 24 |
| Finished | Aug 13 07:48:37 PM PDT 24 |
| Peak memory | 650472 kb |
| Host | smart-68506e90-f7ec-498a-967d-b85d4f26b2b9 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 1984410290 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 52.chip_sw_all_escalation_resets.1984410290 |
| Directory | /workspace/52.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/53.chip_sw_alert_handler_lpg_sleep_mode_alerts.3250973033 |
| Short name | T316 |
| Test name | |
| Test status | |
| Simulation time | 3526921328 ps |
| CPU time | 429.28 seconds |
| Started | Aug 13 07:38:37 PM PDT 24 |
| Finished | Aug 13 07:45:46 PM PDT 24 |
| Peak memory | 649436 kb |
| Host | smart-0e7b8bbc-1b51-42f9-b3f9-cab260dab834 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3250973033 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 53.chip_ sw_alert_handler_lpg_sleep_mode_alerts.3250973033 |
| Directory | /workspace/53.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/54.chip_sw_alert_handler_lpg_sleep_mode_alerts.1707540569 |
| Short name | T855 |
| Test name | |
| Test status | |
| Simulation time | 3890203996 ps |
| CPU time | 490.36 seconds |
| Started | Aug 13 07:39:41 PM PDT 24 |
| Finished | Aug 13 07:47:52 PM PDT 24 |
| Peak memory | 649488 kb |
| Host | smart-6373377c-e3c5-4161-a36f-b1a65a08f1d9 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1707540569 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 54.chip_ sw_alert_handler_lpg_sleep_mode_alerts.1707540569 |
| Directory | /workspace/54.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/56.chip_sw_alert_handler_lpg_sleep_mode_alerts.2626343163 |
| Short name | T778 |
| Test name | |
| Test status | |
| Simulation time | 3391334560 ps |
| CPU time | 466.31 seconds |
| Started | Aug 13 07:39:21 PM PDT 24 |
| Finished | Aug 13 07:47:07 PM PDT 24 |
| Peak memory | 649576 kb |
| Host | smart-1dc23a20-04e8-4961-8aa1-ed34936fbf53 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2626343163 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 56.chip_ sw_alert_handler_lpg_sleep_mode_alerts.2626343163 |
| Directory | /workspace/56.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/56.chip_sw_all_escalation_resets.1008282019 |
| Short name | T834 |
| Test name | |
| Test status | |
| Simulation time | 5160308484 ps |
| CPU time | 550.19 seconds |
| Started | Aug 13 07:42:09 PM PDT 24 |
| Finished | Aug 13 07:51:19 PM PDT 24 |
| Peak memory | 650696 kb |
| Host | smart-071144bb-16a9-4021-8db1-330188b6f65e |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 1008282019 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 56.chip_sw_all_escalation_resets.1008282019 |
| Directory | /workspace/56.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/57.chip_sw_alert_handler_lpg_sleep_mode_alerts.1167913198 |
| Short name | T996 |
| Test name | |
| Test status | |
| Simulation time | 3632332084 ps |
| CPU time | 393.09 seconds |
| Started | Aug 13 07:40:00 PM PDT 24 |
| Finished | Aug 13 07:46:33 PM PDT 24 |
| Peak memory | 649520 kb |
| Host | smart-0308ce71-b3cc-40f2-8db1-2f9da87cc633 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1167913198 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 57.chip_ sw_alert_handler_lpg_sleep_mode_alerts.1167913198 |
| Directory | /workspace/57.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/58.chip_sw_alert_handler_lpg_sleep_mode_alerts.4030399652 |
| Short name | T88 |
| Test name | |
| Test status | |
| Simulation time | 3919532564 ps |
| CPU time | 340.38 seconds |
| Started | Aug 13 07:39:08 PM PDT 24 |
| Finished | Aug 13 07:44:49 PM PDT 24 |
| Peak memory | 650048 kb |
| Host | smart-b41978da-18e2-4fa5-bdbf-973efba7b7c2 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4030399652 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 58.chip_ sw_alert_handler_lpg_sleep_mode_alerts.4030399652 |
| Directory | /workspace/58.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/58.chip_sw_all_escalation_resets.2675698944 |
| Short name | T825 |
| Test name | |
| Test status | |
| Simulation time | 5195513150 ps |
| CPU time | 647.2 seconds |
| Started | Aug 13 07:38:34 PM PDT 24 |
| Finished | Aug 13 07:49:21 PM PDT 24 |
| Peak memory | 650660 kb |
| Host | smart-dd0bb006-02ac-4e03-b956-7a8b78c22631 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 2675698944 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 58.chip_sw_all_escalation_resets.2675698944 |
| Directory | /workspace/58.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/59.chip_sw_alert_handler_lpg_sleep_mode_alerts.3290761240 |
| Short name | T781 |
| Test name | |
| Test status | |
| Simulation time | 3130535648 ps |
| CPU time | 369.61 seconds |
| Started | Aug 13 07:43:43 PM PDT 24 |
| Finished | Aug 13 07:49:53 PM PDT 24 |
| Peak memory | 649668 kb |
| Host | smart-bcec455d-64e4-468d-9bf6-1621ff2e6c89 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3290761240 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 59.chip_ sw_alert_handler_lpg_sleep_mode_alerts.3290761240 |
| Directory | /workspace/59.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/59.chip_sw_all_escalation_resets.745498700 |
| Short name | T1378 |
| Test name | |
| Test status | |
| Simulation time | 6024314568 ps |
| CPU time | 646.77 seconds |
| Started | Aug 13 07:39:25 PM PDT 24 |
| Finished | Aug 13 07:50:12 PM PDT 24 |
| Peak memory | 620624 kb |
| Host | smart-0c60fb6e-ff45-4e96-8b63-06fb3d550469 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 745498700 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 59.chip_sw_all_escalation_resets.745498700 |
| Directory | /workspace/59.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/6.chip_sw_csrng_edn_concurrency.3582452871 |
| Short name | T1176 |
| Test name | |
| Test status | |
| Simulation time | 29131207772 ps |
| CPU time | 5901.4 seconds |
| Started | Aug 13 07:32:26 PM PDT 24 |
| Finished | Aug 13 09:10:48 PM PDT 24 |
| Peak memory | 611088 kb |
| Host | smart-17053176-82ea-444c-9975-88f7214dbabf |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=140_000_000 +rng_srate_value_min=15 +rng_srate_value_max=20 +accelerate_cold_power_up_time=3 +accelerate_r egulators_power_up_time=2 +sw_build_device=sim_dv +sw_images=csrng_edn_concurrency_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3582452871 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd b -cm_log /dev/null -cm_name 6.chip_sw_csrng_edn_concurrency.3582452871 |
| Directory | /workspace/6.chip_sw_csrng_edn_concurrency/latest |
| Test location | /workspace/coverage/default/6.chip_sw_lc_ctrl_transition.655564226 |
| Short name | T1196 |
| Test name | |
| Test status | |
| Simulation time | 6851278741 ps |
| CPU time | 463.34 seconds |
| Started | Aug 13 07:35:32 PM PDT 24 |
| Finished | Aug 13 07:43:15 PM PDT 24 |
| Peak memory | 621792 kb |
| Host | smart-7e4f74f4-b038-47a7-84ce-a3a15ae6b3f7 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=lc_ctrl_transition_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=655564226 -assert nopostproc +UVM_TEST NAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_transition_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul t.vdb -cm_log /dev/null -cm_name 6.chip_sw_lc_ctrl_transition.655564226 |
| Directory | /workspace/6.chip_sw_lc_ctrl_transition/latest |
| Test location | /workspace/coverage/default/6.chip_sw_uart_rand_baudrate.2485230959 |
| Short name | T1228 |
| Test name | |
| Test status | |
| Simulation time | 8751188984 ps |
| CPU time | 1613.2 seconds |
| Started | Aug 13 07:32:37 PM PDT 24 |
| Finished | Aug 13 07:59:30 PM PDT 24 |
| Peak memory | 620076 kb |
| Host | smart-d4469342-2cc0-4f24-b431-362afc6250aa |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random _seed=2485230959 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.chip_sw_uart_rand_baudrate.2485230959 |
| Directory | /workspace/6.chip_sw_uart_rand_baudrate/latest |
| Test location | /workspace/coverage/default/60.chip_sw_alert_handler_lpg_sleep_mode_alerts.1996418968 |
| Short name | T784 |
| Test name | |
| Test status | |
| Simulation time | 3816499320 ps |
| CPU time | 402.43 seconds |
| Started | Aug 13 07:39:39 PM PDT 24 |
| Finished | Aug 13 07:46:22 PM PDT 24 |
| Peak memory | 649564 kb |
| Host | smart-2aa780ac-e393-42af-ba56-fa3107a7c709 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1996418968 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 60.chip_ sw_alert_handler_lpg_sleep_mode_alerts.1996418968 |
| Directory | /workspace/60.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/60.chip_sw_all_escalation_resets.1283298635 |
| Short name | T846 |
| Test name | |
| Test status | |
| Simulation time | 4929451720 ps |
| CPU time | 668.73 seconds |
| Started | Aug 13 07:39:04 PM PDT 24 |
| Finished | Aug 13 07:50:13 PM PDT 24 |
| Peak memory | 650752 kb |
| Host | smart-79b40de7-5a3f-4173-9389-d9c6ce18410b |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 1283298635 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 60.chip_sw_all_escalation_resets.1283298635 |
| Directory | /workspace/60.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/61.chip_sw_alert_handler_lpg_sleep_mode_alerts.3093434287 |
| Short name | T1299 |
| Test name | |
| Test status | |
| Simulation time | 3744192352 ps |
| CPU time | 363.11 seconds |
| Started | Aug 13 07:39:50 PM PDT 24 |
| Finished | Aug 13 07:45:53 PM PDT 24 |
| Peak memory | 649216 kb |
| Host | smart-49cb42ba-84af-4268-a862-af01ca4577e7 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3093434287 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 61.chip_ sw_alert_handler_lpg_sleep_mode_alerts.3093434287 |
| Directory | /workspace/61.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/62.chip_sw_alert_handler_lpg_sleep_mode_alerts.4285126430 |
| Short name | T378 |
| Test name | |
| Test status | |
| Simulation time | 3331085180 ps |
| CPU time | 351.83 seconds |
| Started | Aug 13 07:40:28 PM PDT 24 |
| Finished | Aug 13 07:46:20 PM PDT 24 |
| Peak memory | 649200 kb |
| Host | smart-aba12521-ba17-48e6-92fe-7b8d85bc9de6 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4285126430 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 62.chip_ sw_alert_handler_lpg_sleep_mode_alerts.4285126430 |
| Directory | /workspace/62.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/64.chip_sw_alert_handler_lpg_sleep_mode_alerts.3456014807 |
| Short name | T856 |
| Test name | |
| Test status | |
| Simulation time | 2899804904 ps |
| CPU time | 289.87 seconds |
| Started | Aug 13 07:39:58 PM PDT 24 |
| Finished | Aug 13 07:44:48 PM PDT 24 |
| Peak memory | 649476 kb |
| Host | smart-6c1de045-048a-4480-bdf1-d398c5f25753 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3456014807 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 64.chip_ sw_alert_handler_lpg_sleep_mode_alerts.3456014807 |
| Directory | /workspace/64.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/64.chip_sw_all_escalation_resets.1546028328 |
| Short name | T842 |
| Test name | |
| Test status | |
| Simulation time | 6296601804 ps |
| CPU time | 638.71 seconds |
| Started | Aug 13 07:38:51 PM PDT 24 |
| Finished | Aug 13 07:49:30 PM PDT 24 |
| Peak memory | 650868 kb |
| Host | smart-f2055e90-8fd2-4ef1-ba64-21b62f6ac506 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 1546028328 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 64.chip_sw_all_escalation_resets.1546028328 |
| Directory | /workspace/64.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/65.chip_sw_alert_handler_lpg_sleep_mode_alerts.3180713936 |
| Short name | T87 |
| Test name | |
| Test status | |
| Simulation time | 4318219728 ps |
| CPU time | 343.01 seconds |
| Started | Aug 13 07:39:59 PM PDT 24 |
| Finished | Aug 13 07:45:42 PM PDT 24 |
| Peak memory | 650144 kb |
| Host | smart-8da95396-e4e9-4cff-841b-a41199815379 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3180713936 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 65.chip_ sw_alert_handler_lpg_sleep_mode_alerts.3180713936 |
| Directory | /workspace/65.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/65.chip_sw_all_escalation_resets.1450165306 |
| Short name | T793 |
| Test name | |
| Test status | |
| Simulation time | 5594275784 ps |
| CPU time | 546.49 seconds |
| Started | Aug 13 07:39:13 PM PDT 24 |
| Finished | Aug 13 07:48:19 PM PDT 24 |
| Peak memory | 620616 kb |
| Host | smart-f0f1c75b-80a0-42c4-b3a3-1ef699a0167f |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 1450165306 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 65.chip_sw_all_escalation_resets.1450165306 |
| Directory | /workspace/65.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/66.chip_sw_alert_handler_lpg_sleep_mode_alerts.1865291950 |
| Short name | T790 |
| Test name | |
| Test status | |
| Simulation time | 3708151272 ps |
| CPU time | 345.87 seconds |
| Started | Aug 13 07:39:42 PM PDT 24 |
| Finished | Aug 13 07:45:28 PM PDT 24 |
| Peak memory | 649364 kb |
| Host | smart-fa626907-670a-469f-a6b3-e716a9217c11 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1865291950 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 66.chip_ sw_alert_handler_lpg_sleep_mode_alerts.1865291950 |
| Directory | /workspace/66.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/66.chip_sw_all_escalation_resets.4177575432 |
| Short name | T818 |
| Test name | |
| Test status | |
| Simulation time | 5517004164 ps |
| CPU time | 703.25 seconds |
| Started | Aug 13 07:39:28 PM PDT 24 |
| Finished | Aug 13 07:51:12 PM PDT 24 |
| Peak memory | 651076 kb |
| Host | smart-e0f3278f-d1f8-4f5a-a49c-dc771ba30fe0 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 4177575432 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 66.chip_sw_all_escalation_resets.4177575432 |
| Directory | /workspace/66.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/67.chip_sw_alert_handler_lpg_sleep_mode_alerts.2151398921 |
| Short name | T443 |
| Test name | |
| Test status | |
| Simulation time | 3834064224 ps |
| CPU time | 366.55 seconds |
| Started | Aug 13 07:40:19 PM PDT 24 |
| Finished | Aug 13 07:46:26 PM PDT 24 |
| Peak memory | 649664 kb |
| Host | smart-d940c1ef-ed12-47e9-9869-13a08ea4b4ad |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2151398921 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 67.chip_ sw_alert_handler_lpg_sleep_mode_alerts.2151398921 |
| Directory | /workspace/67.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/68.chip_sw_alert_handler_lpg_sleep_mode_alerts.1604551265 |
| Short name | T89 |
| Test name | |
| Test status | |
| Simulation time | 4238387862 ps |
| CPU time | 422.01 seconds |
| Started | Aug 13 07:40:53 PM PDT 24 |
| Finished | Aug 13 07:47:55 PM PDT 24 |
| Peak memory | 649796 kb |
| Host | smart-20098c8f-df18-4d46-86eb-5cb562b96bce |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1604551265 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 68.chip_ sw_alert_handler_lpg_sleep_mode_alerts.1604551265 |
| Directory | /workspace/68.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/68.chip_sw_all_escalation_resets.2574681969 |
| Short name | T165 |
| Test name | |
| Test status | |
| Simulation time | 3962347780 ps |
| CPU time | 416.14 seconds |
| Started | Aug 13 07:39:50 PM PDT 24 |
| Finished | Aug 13 07:46:46 PM PDT 24 |
| Peak memory | 619968 kb |
| Host | smart-6696c0f6-d6f2-44cb-9545-be32f394992f |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 2574681969 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 68.chip_sw_all_escalation_resets.2574681969 |
| Directory | /workspace/68.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/69.chip_sw_alert_handler_lpg_sleep_mode_alerts.3700474385 |
| Short name | T425 |
| Test name | |
| Test status | |
| Simulation time | 3993824232 ps |
| CPU time | 425.28 seconds |
| Started | Aug 13 07:41:37 PM PDT 24 |
| Finished | Aug 13 07:48:42 PM PDT 24 |
| Peak memory | 649364 kb |
| Host | smart-79ab52f9-e296-4194-baca-94624027532c |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3700474385 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 69.chip_ sw_alert_handler_lpg_sleep_mode_alerts.3700474385 |
| Directory | /workspace/69.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/69.chip_sw_all_escalation_resets.2751086047 |
| Short name | T273 |
| Test name | |
| Test status | |
| Simulation time | 5601625272 ps |
| CPU time | 566.29 seconds |
| Started | Aug 13 07:39:53 PM PDT 24 |
| Finished | Aug 13 07:49:20 PM PDT 24 |
| Peak memory | 650764 kb |
| Host | smart-604f0f56-267e-4d3f-b5c1-4fdedb32f157 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 2751086047 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 69.chip_sw_all_escalation_resets.2751086047 |
| Directory | /workspace/69.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/7.chip_sw_csrng_edn_concurrency.1467749 |
| Short name | T1394 |
| Test name | |
| Test status | |
| Simulation time | 17693307402 ps |
| CPU time | 4627.89 seconds |
| Started | Aug 13 07:34:49 PM PDT 24 |
| Finished | Aug 13 08:51:58 PM PDT 24 |
| Peak memory | 610884 kb |
| Host | smart-93313453-37d8-48ca-b80a-1aaa0f1404b6 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=140_000_000 +rng_srate_value_min=15 +rng_srate_value_max=20 +accelerate_cold_power_up_time=3 +accelerate_r egulators_power_up_time=2 +sw_build_device=sim_dv +sw_images=csrng_edn_concurrency_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1467749 -assert nopostproc +U VM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb - cm_log /dev/null -cm_name 7.chip_sw_csrng_edn_concurrency.1467749 |
| Directory | /workspace/7.chip_sw_csrng_edn_concurrency/latest |
| Test location | /workspace/coverage/default/7.chip_sw_lc_ctrl_transition.3492947362 |
| Short name | T197 |
| Test name | |
| Test status | |
| Simulation time | 7059410806 ps |
| CPU time | 449.59 seconds |
| Started | Aug 13 07:34:08 PM PDT 24 |
| Finished | Aug 13 07:41:38 PM PDT 24 |
| Peak memory | 622044 kb |
| Host | smart-162cdbf6-c0f1-44f5-9686-3ebc93c241c2 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=lc_ctrl_transition_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3492947362 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_transition_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau lt.vdb -cm_log /dev/null -cm_name 7.chip_sw_lc_ctrl_transition.3492947362 |
| Directory | /workspace/7.chip_sw_lc_ctrl_transition/latest |
| Test location | /workspace/coverage/default/7.chip_sw_uart_rand_baudrate.1481573127 |
| Short name | T1267 |
| Test name | |
| Test status | |
| Simulation time | 12603682076 ps |
| CPU time | 2287.14 seconds |
| Started | Aug 13 07:34:00 PM PDT 24 |
| Finished | Aug 13 08:12:07 PM PDT 24 |
| Peak memory | 620164 kb |
| Host | smart-680888a0-9c7f-49ba-b4e2-c2eb10a93952 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random _seed=1481573127 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.chip_sw_uart_rand_baudrate.1481573127 |
| Directory | /workspace/7.chip_sw_uart_rand_baudrate/latest |
| Test location | /workspace/coverage/default/70.chip_sw_alert_handler_lpg_sleep_mode_alerts.482492687 |
| Short name | T223 |
| Test name | |
| Test status | |
| Simulation time | 3010391202 ps |
| CPU time | 358.43 seconds |
| Started | Aug 13 07:40:11 PM PDT 24 |
| Finished | Aug 13 07:46:10 PM PDT 24 |
| Peak memory | 649588 kb |
| Host | smart-b49eed22-e753-47fe-bd8b-1375f8cf6413 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=482492687 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all _escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 70.chip_s w_alert_handler_lpg_sleep_mode_alerts.482492687 |
| Directory | /workspace/70.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/70.chip_sw_all_escalation_resets.1113128504 |
| Short name | T1271 |
| Test name | |
| Test status | |
| Simulation time | 5366453224 ps |
| CPU time | 720.13 seconds |
| Started | Aug 13 07:40:45 PM PDT 24 |
| Finished | Aug 13 07:52:45 PM PDT 24 |
| Peak memory | 620584 kb |
| Host | smart-54075464-55f0-432b-a271-d083d72513ef |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 1113128504 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 70.chip_sw_all_escalation_resets.1113128504 |
| Directory | /workspace/70.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/71.chip_sw_alert_handler_lpg_sleep_mode_alerts.2247350281 |
| Short name | T850 |
| Test name | |
| Test status | |
| Simulation time | 3697019032 ps |
| CPU time | 481.56 seconds |
| Started | Aug 13 07:40:18 PM PDT 24 |
| Finished | Aug 13 07:48:20 PM PDT 24 |
| Peak memory | 649584 kb |
| Host | smart-8c3d0fe2-0556-4287-9419-4a952da8bf35 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2247350281 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 71.chip_ sw_alert_handler_lpg_sleep_mode_alerts.2247350281 |
| Directory | /workspace/71.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/71.chip_sw_all_escalation_resets.2905217834 |
| Short name | T1262 |
| Test name | |
| Test status | |
| Simulation time | 5207210322 ps |
| CPU time | 569.13 seconds |
| Started | Aug 13 07:41:17 PM PDT 24 |
| Finished | Aug 13 07:50:46 PM PDT 24 |
| Peak memory | 620596 kb |
| Host | smart-ec0f9465-6424-49b8-964a-075e2709e1f6 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 2905217834 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 71.chip_sw_all_escalation_resets.2905217834 |
| Directory | /workspace/71.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/72.chip_sw_alert_handler_lpg_sleep_mode_alerts.2542106179 |
| Short name | T797 |
| Test name | |
| Test status | |
| Simulation time | 4032292870 ps |
| CPU time | 436.8 seconds |
| Started | Aug 13 07:42:00 PM PDT 24 |
| Finished | Aug 13 07:49:16 PM PDT 24 |
| Peak memory | 649528 kb |
| Host | smart-9b8bffd0-dcb7-4a36-8af1-b50881735dc2 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2542106179 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 72.chip_ sw_alert_handler_lpg_sleep_mode_alerts.2542106179 |
| Directory | /workspace/72.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/72.chip_sw_all_escalation_resets.2534200996 |
| Short name | T823 |
| Test name | |
| Test status | |
| Simulation time | 5414119972 ps |
| CPU time | 654.09 seconds |
| Started | Aug 13 07:39:34 PM PDT 24 |
| Finished | Aug 13 07:50:28 PM PDT 24 |
| Peak memory | 650812 kb |
| Host | smart-f1fbc94d-9a81-4686-8dea-0e54d2091bbb |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 2534200996 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 72.chip_sw_all_escalation_resets.2534200996 |
| Directory | /workspace/72.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/73.chip_sw_all_escalation_resets.3745105463 |
| Short name | T1167 |
| Test name | |
| Test status | |
| Simulation time | 5654334590 ps |
| CPU time | 695.5 seconds |
| Started | Aug 13 07:40:29 PM PDT 24 |
| Finished | Aug 13 07:52:05 PM PDT 24 |
| Peak memory | 620668 kb |
| Host | smart-8dc3d06f-1033-4f23-9d27-5bd5ebb1f54b |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 3745105463 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 73.chip_sw_all_escalation_resets.3745105463 |
| Directory | /workspace/73.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/75.chip_sw_alert_handler_lpg_sleep_mode_alerts.4054942653 |
| Short name | T1412 |
| Test name | |
| Test status | |
| Simulation time | 4189769480 ps |
| CPU time | 423.37 seconds |
| Started | Aug 13 07:40:14 PM PDT 24 |
| Finished | Aug 13 07:47:18 PM PDT 24 |
| Peak memory | 649592 kb |
| Host | smart-6eadd14d-f0d3-4b67-a317-f9468ae8f7af |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4054942653 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 75.chip_ sw_alert_handler_lpg_sleep_mode_alerts.4054942653 |
| Directory | /workspace/75.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/75.chip_sw_all_escalation_resets.2528461864 |
| Short name | T844 |
| Test name | |
| Test status | |
| Simulation time | 5232951204 ps |
| CPU time | 580.79 seconds |
| Started | Aug 13 07:40:03 PM PDT 24 |
| Finished | Aug 13 07:49:44 PM PDT 24 |
| Peak memory | 650760 kb |
| Host | smart-2ca49b3c-97b8-45a7-8ff0-6a75269d227b |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 2528461864 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 75.chip_sw_all_escalation_resets.2528461864 |
| Directory | /workspace/75.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/76.chip_sw_all_escalation_resets.1264482492 |
| Short name | T1335 |
| Test name | |
| Test status | |
| Simulation time | 4627766390 ps |
| CPU time | 477.07 seconds |
| Started | Aug 13 07:41:11 PM PDT 24 |
| Finished | Aug 13 07:49:09 PM PDT 24 |
| Peak memory | 650800 kb |
| Host | smart-6b4e3568-5bed-48e8-bf19-39e2b04237ab |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 1264482492 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 76.chip_sw_all_escalation_resets.1264482492 |
| Directory | /workspace/76.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/77.chip_sw_all_escalation_resets.636349404 |
| Short name | T798 |
| Test name | |
| Test status | |
| Simulation time | 4386700760 ps |
| CPU time | 550.42 seconds |
| Started | Aug 13 07:40:35 PM PDT 24 |
| Finished | Aug 13 07:49:46 PM PDT 24 |
| Peak memory | 650808 kb |
| Host | smart-2fd01052-1801-4659-ba35-e82c010c5459 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 636349404 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 77.chip_sw_all_escalation_resets.636349404 |
| Directory | /workspace/77.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/78.chip_sw_alert_handler_lpg_sleep_mode_alerts.3205207432 |
| Short name | T794 |
| Test name | |
| Test status | |
| Simulation time | 3545231490 ps |
| CPU time | 282.05 seconds |
| Started | Aug 13 07:41:17 PM PDT 24 |
| Finished | Aug 13 07:46:00 PM PDT 24 |
| Peak memory | 649552 kb |
| Host | smart-2f9d559c-0db3-43a8-a63a-2e4e4cb4ca6d |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3205207432 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 78.chip_ sw_alert_handler_lpg_sleep_mode_alerts.3205207432 |
| Directory | /workspace/78.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/78.chip_sw_all_escalation_resets.800829048 |
| Short name | T802 |
| Test name | |
| Test status | |
| Simulation time | 5447265260 ps |
| CPU time | 701.53 seconds |
| Started | Aug 13 07:41:24 PM PDT 24 |
| Finished | Aug 13 07:53:06 PM PDT 24 |
| Peak memory | 650856 kb |
| Host | smart-d2296c08-da4b-453e-9da1-e5033ee6d6c5 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 800829048 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 78.chip_sw_all_escalation_resets.800829048 |
| Directory | /workspace/78.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/79.chip_sw_alert_handler_lpg_sleep_mode_alerts.3689502445 |
| Short name | T805 |
| Test name | |
| Test status | |
| Simulation time | 4068336758 ps |
| CPU time | 359.83 seconds |
| Started | Aug 13 07:42:00 PM PDT 24 |
| Finished | Aug 13 07:48:00 PM PDT 24 |
| Peak memory | 649304 kb |
| Host | smart-350accd5-cb58-47da-b406-b3cdaa1f1a39 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3689502445 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 79.chip_ sw_alert_handler_lpg_sleep_mode_alerts.3689502445 |
| Directory | /workspace/79.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/79.chip_sw_all_escalation_resets.2583313503 |
| Short name | T1255 |
| Test name | |
| Test status | |
| Simulation time | 4838782080 ps |
| CPU time | 632.23 seconds |
| Started | Aug 13 07:41:04 PM PDT 24 |
| Finished | Aug 13 07:51:37 PM PDT 24 |
| Peak memory | 620568 kb |
| Host | smart-19950a71-86dc-40f8-a740-90013c5d4f0e |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 2583313503 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 79.chip_sw_all_escalation_resets.2583313503 |
| Directory | /workspace/79.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/8.chip_sw_alert_handler_lpg_sleep_mode_alerts.2925217182 |
| Short name | T322 |
| Test name | |
| Test status | |
| Simulation time | 3070756352 ps |
| CPU time | 413.07 seconds |
| Started | Aug 13 07:34:12 PM PDT 24 |
| Finished | Aug 13 07:41:06 PM PDT 24 |
| Peak memory | 649468 kb |
| Host | smart-006c7185-c457-4de1-b50d-2a64b8c25de1 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2925217182 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.chip_s w_alert_handler_lpg_sleep_mode_alerts.2925217182 |
| Directory | /workspace/8.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/8.chip_sw_all_escalation_resets.2100788825 |
| Short name | T1205 |
| Test name | |
| Test status | |
| Simulation time | 5397078308 ps |
| CPU time | 693.03 seconds |
| Started | Aug 13 07:34:26 PM PDT 24 |
| Finished | Aug 13 07:45:59 PM PDT 24 |
| Peak memory | 650652 kb |
| Host | smart-6f8ce733-201d-4e76-b695-5ee90f41c9a6 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 2100788825 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.chip_sw_all_escalation_resets.2100788825 |
| Directory | /workspace/8.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/8.chip_sw_csrng_edn_concurrency.2956291796 |
| Short name | T1403 |
| Test name | |
| Test status | |
| Simulation time | 21469729044 ps |
| CPU time | 4204.55 seconds |
| Started | Aug 13 07:35:06 PM PDT 24 |
| Finished | Aug 13 08:45:11 PM PDT 24 |
| Peak memory | 611172 kb |
| Host | smart-9e8e21dd-0cc3-410b-96f6-adeeb253cbee |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=140_000_000 +rng_srate_value_min=15 +rng_srate_value_max=20 +accelerate_cold_power_up_time=3 +accelerate_r egulators_power_up_time=2 +sw_build_device=sim_dv +sw_images=csrng_edn_concurrency_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2956291796 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd b -cm_log /dev/null -cm_name 8.chip_sw_csrng_edn_concurrency.2956291796 |
| Directory | /workspace/8.chip_sw_csrng_edn_concurrency/latest |
| Test location | /workspace/coverage/default/8.chip_sw_lc_ctrl_transition.4123129048 |
| Short name | T1209 |
| Test name | |
| Test status | |
| Simulation time | 6022350203 ps |
| CPU time | 595.76 seconds |
| Started | Aug 13 07:33:32 PM PDT 24 |
| Finished | Aug 13 07:43:28 PM PDT 24 |
| Peak memory | 621880 kb |
| Host | smart-bd232273-ef8b-44a0-bf86-b8a17711d0a5 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=lc_ctrl_transition_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4123129048 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_transition_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau lt.vdb -cm_log /dev/null -cm_name 8.chip_sw_lc_ctrl_transition.4123129048 |
| Directory | /workspace/8.chip_sw_lc_ctrl_transition/latest |
| Test location | /workspace/coverage/default/8.chip_sw_uart_rand_baudrate.3037293405 |
| Short name | T1236 |
| Test name | |
| Test status | |
| Simulation time | 3149814720 ps |
| CPU time | 462.46 seconds |
| Started | Aug 13 07:33:09 PM PDT 24 |
| Finished | Aug 13 07:40:52 PM PDT 24 |
| Peak memory | 620160 kb |
| Host | smart-b8e033d3-eb65-4f49-8954-615eb5bddce4 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random _seed=3037293405 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.chip_sw_uart_rand_baudrate.3037293405 |
| Directory | /workspace/8.chip_sw_uart_rand_baudrate/latest |
| Test location | /workspace/coverage/default/80.chip_sw_alert_handler_lpg_sleep_mode_alerts.3787916577 |
| Short name | T1112 |
| Test name | |
| Test status | |
| Simulation time | 4262674568 ps |
| CPU time | 428.06 seconds |
| Started | Aug 13 07:40:16 PM PDT 24 |
| Finished | Aug 13 07:47:25 PM PDT 24 |
| Peak memory | 649432 kb |
| Host | smart-e1d55db8-cccc-412b-adc4-6cb40cee6ff0 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3787916577 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 80.chip_ sw_alert_handler_lpg_sleep_mode_alerts.3787916577 |
| Directory | /workspace/80.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/81.chip_sw_alert_handler_lpg_sleep_mode_alerts.268331784 |
| Short name | T780 |
| Test name | |
| Test status | |
| Simulation time | 4685824300 ps |
| CPU time | 413.81 seconds |
| Started | Aug 13 07:40:40 PM PDT 24 |
| Finished | Aug 13 07:47:34 PM PDT 24 |
| Peak memory | 649624 kb |
| Host | smart-985ff9d2-6810-4f64-a2b3-46b15bd5c1d6 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=268331784 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all _escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 81.chip_s w_alert_handler_lpg_sleep_mode_alerts.268331784 |
| Directory | /workspace/81.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/81.chip_sw_all_escalation_resets.3650651410 |
| Short name | T185 |
| Test name | |
| Test status | |
| Simulation time | 5207607232 ps |
| CPU time | 522.61 seconds |
| Started | Aug 13 07:40:32 PM PDT 24 |
| Finished | Aug 13 07:49:15 PM PDT 24 |
| Peak memory | 650736 kb |
| Host | smart-c56dd625-6ef7-46b8-91cd-7c0de920f75a |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 3650651410 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 81.chip_sw_all_escalation_resets.3650651410 |
| Directory | /workspace/81.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/82.chip_sw_alert_handler_lpg_sleep_mode_alerts.452572421 |
| Short name | T832 |
| Test name | |
| Test status | |
| Simulation time | 3092502952 ps |
| CPU time | 328.11 seconds |
| Started | Aug 13 07:41:49 PM PDT 24 |
| Finished | Aug 13 07:47:17 PM PDT 24 |
| Peak memory | 649592 kb |
| Host | smart-ec2807da-2947-4a11-8d87-6021807f60ce |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=452572421 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all _escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 82.chip_s w_alert_handler_lpg_sleep_mode_alerts.452572421 |
| Directory | /workspace/82.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/82.chip_sw_all_escalation_resets.1184530463 |
| Short name | T85 |
| Test name | |
| Test status | |
| Simulation time | 5006292204 ps |
| CPU time | 574.19 seconds |
| Started | Aug 13 07:41:13 PM PDT 24 |
| Finished | Aug 13 07:50:47 PM PDT 24 |
| Peak memory | 651460 kb |
| Host | smart-d798b3e3-a7be-4956-b370-b61a00c96e80 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 1184530463 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 82.chip_sw_all_escalation_resets.1184530463 |
| Directory | /workspace/82.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/83.chip_sw_all_escalation_resets.1156649855 |
| Short name | T833 |
| Test name | |
| Test status | |
| Simulation time | 6118970864 ps |
| CPU time | 638.73 seconds |
| Started | Aug 13 07:40:52 PM PDT 24 |
| Finished | Aug 13 07:51:31 PM PDT 24 |
| Peak memory | 650456 kb |
| Host | smart-dcf2a8c1-1d0c-4607-85a2-23589ac777d5 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 1156649855 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 83.chip_sw_all_escalation_resets.1156649855 |
| Directory | /workspace/83.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/84.chip_sw_alert_handler_lpg_sleep_mode_alerts.993757698 |
| Short name | T252 |
| Test name | |
| Test status | |
| Simulation time | 3712725770 ps |
| CPU time | 335.89 seconds |
| Started | Aug 13 07:41:02 PM PDT 24 |
| Finished | Aug 13 07:46:38 PM PDT 24 |
| Peak memory | 649472 kb |
| Host | smart-9598fc61-ba24-47db-a29f-53b43f4dd0aa |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=993757698 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all _escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 84.chip_s w_alert_handler_lpg_sleep_mode_alerts.993757698 |
| Directory | /workspace/84.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/84.chip_sw_all_escalation_resets.4026443967 |
| Short name | T232 |
| Test name | |
| Test status | |
| Simulation time | 5061623668 ps |
| CPU time | 500.54 seconds |
| Started | Aug 13 07:40:58 PM PDT 24 |
| Finished | Aug 13 07:49:19 PM PDT 24 |
| Peak memory | 650924 kb |
| Host | smart-178a41b7-6053-4021-aa26-0e558968b66f |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 4026443967 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 84.chip_sw_all_escalation_resets.4026443967 |
| Directory | /workspace/84.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/85.chip_sw_alert_handler_lpg_sleep_mode_alerts.2794404571 |
| Short name | T377 |
| Test name | |
| Test status | |
| Simulation time | 3208527980 ps |
| CPU time | 403.15 seconds |
| Started | Aug 13 07:40:46 PM PDT 24 |
| Finished | Aug 13 07:47:29 PM PDT 24 |
| Peak memory | 649460 kb |
| Host | smart-a33f91ac-af6a-4313-8491-83bac7ca363f |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2794404571 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 85.chip_ sw_alert_handler_lpg_sleep_mode_alerts.2794404571 |
| Directory | /workspace/85.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/85.chip_sw_all_escalation_resets.2029098105 |
| Short name | T821 |
| Test name | |
| Test status | |
| Simulation time | 4114858440 ps |
| CPU time | 475.06 seconds |
| Started | Aug 13 07:40:20 PM PDT 24 |
| Finished | Aug 13 07:48:15 PM PDT 24 |
| Peak memory | 650588 kb |
| Host | smart-ff7aa325-4181-4724-9ab7-b816347e5ddf |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 2029098105 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 85.chip_sw_all_escalation_resets.2029098105 |
| Directory | /workspace/85.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/86.chip_sw_alert_handler_lpg_sleep_mode_alerts.2692175331 |
| Short name | T770 |
| Test name | |
| Test status | |
| Simulation time | 3757191160 ps |
| CPU time | 356.37 seconds |
| Started | Aug 13 07:41:29 PM PDT 24 |
| Finished | Aug 13 07:47:26 PM PDT 24 |
| Peak memory | 649492 kb |
| Host | smart-211c5d8a-dc23-4ef2-b5c4-91d44ee2d55e |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2692175331 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 86.chip_ sw_alert_handler_lpg_sleep_mode_alerts.2692175331 |
| Directory | /workspace/86.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/86.chip_sw_all_escalation_resets.3237098007 |
| Short name | T839 |
| Test name | |
| Test status | |
| Simulation time | 5877241600 ps |
| CPU time | 732.57 seconds |
| Started | Aug 13 07:41:08 PM PDT 24 |
| Finished | Aug 13 07:53:21 PM PDT 24 |
| Peak memory | 650804 kb |
| Host | smart-f971bd00-1a33-45cf-aa2a-d73e4ee3267f |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 3237098007 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 86.chip_sw_all_escalation_resets.3237098007 |
| Directory | /workspace/86.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/87.chip_sw_alert_handler_lpg_sleep_mode_alerts.1193184086 |
| Short name | T816 |
| Test name | |
| Test status | |
| Simulation time | 3549869496 ps |
| CPU time | 336.91 seconds |
| Started | Aug 13 07:42:00 PM PDT 24 |
| Finished | Aug 13 07:47:37 PM PDT 24 |
| Peak memory | 649832 kb |
| Host | smart-6d509366-1c84-4100-8e99-bbe75aeb4d9e |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1193184086 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 87.chip_ sw_alert_handler_lpg_sleep_mode_alerts.1193184086 |
| Directory | /workspace/87.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/87.chip_sw_all_escalation_resets.3664512849 |
| Short name | T824 |
| Test name | |
| Test status | |
| Simulation time | 4568629620 ps |
| CPU time | 587.52 seconds |
| Started | Aug 13 07:42:30 PM PDT 24 |
| Finished | Aug 13 07:52:18 PM PDT 24 |
| Peak memory | 650472 kb |
| Host | smart-39704096-cfe3-49c6-80fd-08d17bc40d4f |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 3664512849 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 87.chip_sw_all_escalation_resets.3664512849 |
| Directory | /workspace/87.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/88.chip_sw_all_escalation_resets.1292961810 |
| Short name | T268 |
| Test name | |
| Test status | |
| Simulation time | 4350879002 ps |
| CPU time | 492.4 seconds |
| Started | Aug 13 07:41:13 PM PDT 24 |
| Finished | Aug 13 07:49:25 PM PDT 24 |
| Peak memory | 650420 kb |
| Host | smart-933acdae-3b9a-422f-b838-c95f4aecbb80 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 1292961810 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 88.chip_sw_all_escalation_resets.1292961810 |
| Directory | /workspace/88.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/89.chip_sw_alert_handler_lpg_sleep_mode_alerts.1470892431 |
| Short name | T79 |
| Test name | |
| Test status | |
| Simulation time | 3788220040 ps |
| CPU time | 435.9 seconds |
| Started | Aug 13 07:41:12 PM PDT 24 |
| Finished | Aug 13 07:48:28 PM PDT 24 |
| Peak memory | 650060 kb |
| Host | smart-4c68abf8-b1eb-41a7-81b0-dd40028c7196 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1470892431 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 89.chip_ sw_alert_handler_lpg_sleep_mode_alerts.1470892431 |
| Directory | /workspace/89.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/9.chip_sw_alert_handler_lpg_sleep_mode_alerts.4064309735 |
| Short name | T381 |
| Test name | |
| Test status | |
| Simulation time | 4472642964 ps |
| CPU time | 422.19 seconds |
| Started | Aug 13 07:34:17 PM PDT 24 |
| Finished | Aug 13 07:41:19 PM PDT 24 |
| Peak memory | 649764 kb |
| Host | smart-95ede93d-d64c-44f1-9fff-b71b5b4094c2 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4064309735 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.chip_s w_alert_handler_lpg_sleep_mode_alerts.4064309735 |
| Directory | /workspace/9.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/9.chip_sw_all_escalation_resets.3705870175 |
| Short name | T1333 |
| Test name | |
| Test status | |
| Simulation time | 5685720000 ps |
| CPU time | 690.13 seconds |
| Started | Aug 13 07:33:52 PM PDT 24 |
| Finished | Aug 13 07:45:23 PM PDT 24 |
| Peak memory | 620588 kb |
| Host | smart-cf399b28-2b02-4987-ba9f-3ac5acca22c4 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 3705870175 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.chip_sw_all_escalation_resets.3705870175 |
| Directory | /workspace/9.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/9.chip_sw_csrng_edn_concurrency.1162880603 |
| Short name | T1037 |
| Test name | |
| Test status | |
| Simulation time | 15599254600 ps |
| CPU time | 3405.23 seconds |
| Started | Aug 13 07:35:01 PM PDT 24 |
| Finished | Aug 13 08:31:47 PM PDT 24 |
| Peak memory | 610796 kb |
| Host | smart-b4c8f753-d6ed-4d3c-aecb-d59a1237eff6 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=140_000_000 +rng_srate_value_min=15 +rng_srate_value_max=20 +accelerate_cold_power_up_time=3 +accelerate_r egulators_power_up_time=2 +sw_build_device=sim_dv +sw_images=csrng_edn_concurrency_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1162880603 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd b -cm_log /dev/null -cm_name 9.chip_sw_csrng_edn_concurrency.1162880603 |
| Directory | /workspace/9.chip_sw_csrng_edn_concurrency/latest |
| Test location | /workspace/coverage/default/9.chip_sw_lc_ctrl_transition.1586701431 |
| Short name | T286 |
| Test name | |
| Test status | |
| Simulation time | 6360516148 ps |
| CPU time | 593.85 seconds |
| Started | Aug 13 07:33:46 PM PDT 24 |
| Finished | Aug 13 07:43:40 PM PDT 24 |
| Peak memory | 621792 kb |
| Host | smart-4e33b38f-d3a8-4cbf-9a8c-93512a6ed59e |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=lc_ctrl_transition_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1586701431 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_transition_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau lt.vdb -cm_log /dev/null -cm_name 9.chip_sw_lc_ctrl_transition.1586701431 |
| Directory | /workspace/9.chip_sw_lc_ctrl_transition/latest |
| Test location | /workspace/coverage/default/9.chip_sw_uart_rand_baudrate.4075188570 |
| Short name | T1036 |
| Test name | |
| Test status | |
| Simulation time | 12920596804 ps |
| CPU time | 2610.25 seconds |
| Started | Aug 13 07:33:17 PM PDT 24 |
| Finished | Aug 13 08:16:48 PM PDT 24 |
| Peak memory | 620200 kb |
| Host | smart-be26b2e5-9b46-461b-8b3d-fb55f7ddb82e |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random _seed=4075188570 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.chip_sw_uart_rand_baudrate.4075188570 |
| Directory | /workspace/9.chip_sw_uart_rand_baudrate/latest |
| Test location | /workspace/coverage/default/90.chip_sw_all_escalation_resets.2399543868 |
| Short name | T783 |
| Test name | |
| Test status | |
| Simulation time | 5840315600 ps |
| CPU time | 522.85 seconds |
| Started | Aug 13 07:41:59 PM PDT 24 |
| Finished | Aug 13 07:50:42 PM PDT 24 |
| Peak memory | 651048 kb |
| Host | smart-98ee55e0-1c87-4d1b-a760-ff8e6234b192 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 2399543868 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 90.chip_sw_all_escalation_resets.2399543868 |
| Directory | /workspace/90.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/91.chip_sw_all_escalation_resets.3074566083 |
| Short name | T423 |
| Test name | |
| Test status | |
| Simulation time | 4911115090 ps |
| CPU time | 553.73 seconds |
| Started | Aug 13 07:42:06 PM PDT 24 |
| Finished | Aug 13 07:51:20 PM PDT 24 |
| Peak memory | 649028 kb |
| Host | smart-59a0a4cd-72d0-4244-a9f8-da53e179bcf6 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 3074566083 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 91.chip_sw_all_escalation_resets.3074566083 |
| Directory | /workspace/91.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/92.chip_sw_all_escalation_resets.2633970074 |
| Short name | T764 |
| Test name | |
| Test status | |
| Simulation time | 5290995236 ps |
| CPU time | 512.66 seconds |
| Started | Aug 13 07:41:06 PM PDT 24 |
| Finished | Aug 13 07:49:39 PM PDT 24 |
| Peak memory | 650772 kb |
| Host | smart-9373bb34-8544-4ee4-847b-b900b58ae4fc |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 2633970074 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 92.chip_sw_all_escalation_resets.2633970074 |
| Directory | /workspace/92.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/93.chip_sw_all_escalation_resets.1217708358 |
| Short name | T1370 |
| Test name | |
| Test status | |
| Simulation time | 5050543640 ps |
| CPU time | 619.28 seconds |
| Started | Aug 13 07:42:00 PM PDT 24 |
| Finished | Aug 13 07:52:20 PM PDT 24 |
| Peak memory | 650492 kb |
| Host | smart-a398ab04-8f31-4ded-b67f-81fa38d0c396 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 1217708358 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 93.chip_sw_all_escalation_resets.1217708358 |
| Directory | /workspace/93.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/94.chip_sw_all_escalation_resets.2322787626 |
| Short name | T1328 |
| Test name | |
| Test status | |
| Simulation time | 4543512256 ps |
| CPU time | 474.37 seconds |
| Started | Aug 13 07:42:34 PM PDT 24 |
| Finished | Aug 13 07:50:29 PM PDT 24 |
| Peak memory | 620628 kb |
| Host | smart-a1d83c85-99ec-4f8d-ae19-739d01bfbe3d |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 2322787626 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 94.chip_sw_all_escalation_resets.2322787626 |
| Directory | /workspace/94.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/95.chip_sw_all_escalation_resets.4149275417 |
| Short name | T800 |
| Test name | |
| Test status | |
| Simulation time | 4730242994 ps |
| CPU time | 629.95 seconds |
| Started | Aug 13 07:41:25 PM PDT 24 |
| Finished | Aug 13 07:51:55 PM PDT 24 |
| Peak memory | 650804 kb |
| Host | smart-d0f268be-4153-4963-826a-37770c0d42f6 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 4149275417 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 95.chip_sw_all_escalation_resets.4149275417 |
| Directory | /workspace/95.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/96.chip_sw_all_escalation_resets.4081879659 |
| Short name | T323 |
| Test name | |
| Test status | |
| Simulation time | 4908364550 ps |
| CPU time | 548.91 seconds |
| Started | Aug 13 07:42:46 PM PDT 24 |
| Finished | Aug 13 07:51:55 PM PDT 24 |
| Peak memory | 650748 kb |
| Host | smart-25cc5b29-0135-48c4-a6d8-645e1ed30680 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 4081879659 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 96.chip_sw_all_escalation_resets.4081879659 |
| Directory | /workspace/96.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/99.chip_sw_all_escalation_resets.1350236304 |
| Short name | T359 |
| Test name | |
| Test status | |
| Simulation time | 5600523402 ps |
| CPU time | 697.12 seconds |
| Started | Aug 13 07:41:51 PM PDT 24 |
| Finished | Aug 13 07:53:29 PM PDT 24 |
| Peak memory | 650528 kb |
| Host | smart-f29d8bd1-f7be-4832-80f1-05fb5709199f |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 1350236304 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 99.chip_sw_all_escalation_resets.1350236304 |
| Directory | /workspace/99.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/pad_ctrl_test_mode/2.chip_padctrl_attributes.3444893650 |
| Short name | T198 |
| Test name | |
| Test status | |
| Simulation time | 5159243328 ps |
| CPU time | 303.52 seconds |
| Started | Aug 13 06:32:02 PM PDT 24 |
| Finished | Aug 13 06:37:06 PM PDT 24 |
| Peak memory | 657868 kb |
| Host | smart-4529253e-ebb5-4dc3-a33f-51c79969b2c2 |
| User | root |
| Command | /workspace/pad_ctrl_test_mode/simv +use_otp_image=OtpTypeLcStProd +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3444893650 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TE ST_SEQ=chip_padctrl_attributes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/pad_ctrl_test_mode.vdb -cm_log /dev/ null -cm_name 2.chip_padctrl_attributes.3444893650 |
| Directory | /workspace/2.chip_padctrl_attributes/latest |
| Test location | /workspace/coverage/pad_ctrl_test_mode/3.chip_padctrl_attributes.1029802104 |
| Short name | T204 |
| Test name | |
| Test status | |
| Simulation time | 5132507834 ps |
| CPU time | 265.76 seconds |
| Started | Aug 13 06:31:55 PM PDT 24 |
| Finished | Aug 13 06:36:21 PM PDT 24 |
| Peak memory | 657128 kb |
| Host | smart-7fe7dd5c-e7bf-49e9-be18-35fc0c5cfc43 |
| User | root |
| Command | /workspace/pad_ctrl_test_mode/simv +use_otp_image=OtpTypeLcStProd +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1029802104 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TE ST_SEQ=chip_padctrl_attributes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/pad_ctrl_test_mode.vdb -cm_log /dev/ null -cm_name 3.chip_padctrl_attributes.1029802104 |
| Directory | /workspace/3.chip_padctrl_attributes/latest |
| Test location | /workspace/coverage/pad_ctrl_test_mode/4.chip_padctrl_attributes.2882537077 |
| Short name | T201 |
| Test name | |
| Test status | |
| Simulation time | 3741941530 ps |
| CPU time | 231.71 seconds |
| Started | Aug 13 06:31:50 PM PDT 24 |
| Finished | Aug 13 06:35:42 PM PDT 24 |
| Peak memory | 642236 kb |
| Host | smart-c781746a-d672-40e6-9d05-d86bb105ac90 |
| User | root |
| Command | /workspace/pad_ctrl_test_mode/simv +use_otp_image=OtpTypeLcStProd +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2882537077 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TE ST_SEQ=chip_padctrl_attributes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/pad_ctrl_test_mode.vdb -cm_log /dev/ null -cm_name 4.chip_padctrl_attributes.2882537077 |
| Directory | /workspace/4.chip_padctrl_attributes/latest |
| Test location | /workspace/coverage/pad_ctrl_test_mode/5.chip_padctrl_attributes.545032498 |
| Short name | T29 |
| Test name | |
| Test status | |
| Simulation time | 4201993156 ps |
| CPU time | 256.02 seconds |
| Started | Aug 13 06:32:17 PM PDT 24 |
| Finished | Aug 13 06:36:33 PM PDT 24 |
| Peak memory | 657848 kb |
| Host | smart-1ac939cf-ede2-4744-a24e-047967bd97e9 |
| User | root |
| Command | /workspace/pad_ctrl_test_mode/simv +use_otp_image=OtpTypeLcStProd +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=545032498 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TES T_SEQ=chip_padctrl_attributes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/pad_ctrl_test_mode.vdb -cm_log /dev/n ull -cm_name 5.chip_padctrl_attributes.545032498 |
| Directory | /workspace/5.chip_padctrl_attributes/latest |
| Test location | /workspace/coverage/pad_ctrl_test_mode/6.chip_padctrl_attributes.425694906 |
| Short name | T199 |
| Test name | |
| Test status | |
| Simulation time | 5579820551 ps |
| CPU time | 328.97 seconds |
| Started | Aug 13 06:31:51 PM PDT 24 |
| Finished | Aug 13 06:37:21 PM PDT 24 |
| Peak memory | 657852 kb |
| Host | smart-ae4e4bed-45d7-40fb-b76b-daba08f53f2d |
| User | root |
| Command | /workspace/pad_ctrl_test_mode/simv +use_otp_image=OtpTypeLcStProd +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=425694906 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TES T_SEQ=chip_padctrl_attributes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/pad_ctrl_test_mode.vdb -cm_log /dev/n ull -cm_name 6.chip_padctrl_attributes.425694906 |
| Directory | /workspace/6.chip_padctrl_attributes/latest |
| Test location | /workspace/coverage/pad_ctrl_test_mode/7.chip_padctrl_attributes.1487253681 |
| Short name | T200 |
| Test name | |
| Test status | |
| Simulation time | 4837907696 ps |
| CPU time | 311.23 seconds |
| Started | Aug 13 06:31:52 PM PDT 24 |
| Finished | Aug 13 06:37:03 PM PDT 24 |
| Peak memory | 644288 kb |
| Host | smart-f4d68b34-087a-4fcb-a989-c0c585d5f465 |
| User | root |
| Command | /workspace/pad_ctrl_test_mode/simv +use_otp_image=OtpTypeLcStProd +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1487253681 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TE ST_SEQ=chip_padctrl_attributes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/pad_ctrl_test_mode.vdb -cm_log /dev/ null -cm_name 7.chip_padctrl_attributes.1487253681 |
| Directory | /workspace/7.chip_padctrl_attributes/latest |
| Test location | /workspace/coverage/pad_ctrl_test_mode/8.chip_padctrl_attributes.495014914 |
| Short name | T203 |
| Test name | |
| Test status | |
| Simulation time | 4676077876 ps |
| CPU time | 243.61 seconds |
| Started | Aug 13 06:32:03 PM PDT 24 |
| Finished | Aug 13 06:36:07 PM PDT 24 |
| Peak memory | 657868 kb |
| Host | smart-89887e19-82f3-44ce-a47c-4cb1f4295ae6 |
| User | root |
| Command | /workspace/pad_ctrl_test_mode/simv +use_otp_image=OtpTypeLcStProd +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=495014914 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TES T_SEQ=chip_padctrl_attributes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/pad_ctrl_test_mode.vdb -cm_log /dev/n ull -cm_name 8.chip_padctrl_attributes.495014914 |
| Directory | /workspace/8.chip_padctrl_attributes/latest |
| Test location | /workspace/coverage/pad_ctrl_test_mode/9.chip_padctrl_attributes.2321294617 |
| Short name | T202 |
| Test name | |
| Test status | |
| Simulation time | 5342585530 ps |
| CPU time | 255.86 seconds |
| Started | Aug 13 06:31:50 PM PDT 24 |
| Finished | Aug 13 06:36:06 PM PDT 24 |
| Peak memory | 651836 kb |
| Host | smart-1d9ac96a-cb51-409e-af87-8e97d0e80101 |
| User | root |
| Command | /workspace/pad_ctrl_test_mode/simv +use_otp_image=OtpTypeLcStProd +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2321294617 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TE ST_SEQ=chip_padctrl_attributes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/pad_ctrl_test_mode.vdb -cm_log /dev/ null -cm_name 9.chip_padctrl_attributes.2321294617 |
| Directory | /workspace/9.chip_padctrl_attributes/latest |
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