| T703 |
/workspace/coverage/default/1.chip_sw_pwrmgr_random_sleep_all_reset_reqs.1145237101 |
|
|
Aug 14 05:51:06 PM PDT 24 |
Aug 14 06:40:05 PM PDT 24 |
19619864392 ps |
| T291 |
/workspace/coverage/default/5.chip_sw_data_integrity_escalation.2789073931 |
|
|
Aug 14 06:08:45 PM PDT 24 |
Aug 14 06:24:46 PM PDT 24 |
5676438128 ps |
| T704 |
/workspace/coverage/default/7.chip_sw_csrng_edn_concurrency.3756218928 |
|
|
Aug 14 06:11:37 PM PDT 24 |
Aug 14 06:55:36 PM PDT 24 |
13886884340 ps |
| T705 |
/workspace/coverage/default/2.chip_sw_sleep_pwm_pulses.26609411 |
|
|
Aug 14 05:56:09 PM PDT 24 |
Aug 14 06:18:04 PM PDT 24 |
9513938800 ps |
| T706 |
/workspace/coverage/default/3.chip_sw_lc_ctrl_transition.3404080601 |
|
|
Aug 14 06:11:33 PM PDT 24 |
Aug 14 06:20:52 PM PDT 24 |
6112042691 ps |
| T707 |
/workspace/coverage/default/0.chip_sw_adc_ctrl_sleep_debug_cable_wakeup.3480070814 |
|
|
Aug 14 05:47:12 PM PDT 24 |
Aug 14 05:56:34 PM PDT 24 |
18426568896 ps |
| T708 |
/workspace/coverage/default/1.chip_sw_example_flash.276088313 |
|
|
Aug 14 05:51:04 PM PDT 24 |
Aug 14 05:54:40 PM PDT 24 |
2661593482 ps |
| T541 |
/workspace/coverage/default/66.chip_sw_alert_handler_lpg_sleep_mode_alerts.2688858483 |
|
|
Aug 14 06:15:04 PM PDT 24 |
Aug 14 06:21:40 PM PDT 24 |
3720394826 ps |
| T469 |
/workspace/coverage/default/77.chip_sw_alert_handler_lpg_sleep_mode_alerts.383294113 |
|
|
Aug 14 06:15:14 PM PDT 24 |
Aug 14 06:21:32 PM PDT 24 |
3938460040 ps |
| T709 |
/workspace/coverage/default/66.chip_sw_all_escalation_resets.1306223613 |
|
|
Aug 14 06:16:07 PM PDT 24 |
Aug 14 06:27:35 PM PDT 24 |
5295546584 ps |
| T710 |
/workspace/coverage/default/2.chip_sw_aes_enc_jitter_en.2290999173 |
|
|
Aug 14 06:03:00 PM PDT 24 |
Aug 14 06:07:57 PM PDT 24 |
3767460610 ps |
| T711 |
/workspace/coverage/default/1.chip_sw_clkmgr_off_otbn_trans.4042361577 |
|
|
Aug 14 05:55:36 PM PDT 24 |
Aug 14 06:02:31 PM PDT 24 |
3763090312 ps |
| T253 |
/workspace/coverage/default/1.chip_sw_sysrst_ctrl_inputs.3361712092 |
|
|
Aug 14 05:55:24 PM PDT 24 |
Aug 14 06:03:03 PM PDT 24 |
3155635635 ps |
| T712 |
/workspace/coverage/default/0.chip_sw_pwrmgr_deep_sleep_power_glitch_reset.2611376067 |
|
|
Aug 14 05:48:57 PM PDT 24 |
Aug 14 05:57:38 PM PDT 24 |
7381659314 ps |
| T713 |
/workspace/coverage/default/0.chip_sw_entropy_src_ast_rng_req.2521882361 |
|
|
Aug 14 05:50:51 PM PDT 24 |
Aug 14 05:53:56 PM PDT 24 |
2941541710 ps |
| T714 |
/workspace/coverage/default/0.chip_sw_edn_kat.1920219105 |
|
|
Aug 14 05:52:45 PM PDT 24 |
Aug 14 06:05:00 PM PDT 24 |
3306394514 ps |
| T327 |
/workspace/coverage/default/0.chip_sw_sysrst_ctrl_ec_rst_l.270927447 |
|
|
Aug 14 05:46:55 PM PDT 24 |
Aug 14 06:44:49 PM PDT 24 |
21071436444 ps |
| T335 |
/workspace/coverage/default/0.chip_sw_keymgr_sideload_otbn.2331717883 |
|
|
Aug 14 05:51:07 PM PDT 24 |
Aug 14 06:47:06 PM PDT 24 |
13964403470 ps |
| T332 |
/workspace/coverage/default/1.chip_sw_keymgr_sideload_aes.1310376878 |
|
|
Aug 14 05:52:33 PM PDT 24 |
Aug 14 06:35:36 PM PDT 24 |
12821075576 ps |
| T320 |
/workspace/coverage/default/15.chip_sw_all_escalation_resets.1207984759 |
|
|
Aug 14 06:10:30 PM PDT 24 |
Aug 14 06:18:12 PM PDT 24 |
4895454412 ps |
| T715 |
/workspace/coverage/default/2.chip_sw_aes_masking_off.2670457789 |
|
|
Aug 14 06:03:13 PM PDT 24 |
Aug 14 06:07:26 PM PDT 24 |
2492680275 ps |
| T716 |
/workspace/coverage/default/0.chip_sw_clkmgr_jitter_reduced_freq.348046955 |
|
|
Aug 14 05:47:57 PM PDT 24 |
Aug 14 05:51:05 PM PDT 24 |
2523100991 ps |
| T717 |
/workspace/coverage/default/2.chip_sw_lc_ctrl_transition.197575422 |
|
|
Aug 14 05:59:14 PM PDT 24 |
Aug 14 06:15:16 PM PDT 24 |
12585139050 ps |
| T351 |
/workspace/coverage/default/2.chip_sw_sram_ctrl_scrambled_access.2120579373 |
|
|
Aug 14 06:05:14 PM PDT 24 |
Aug 14 06:16:02 PM PDT 24 |
5429957496 ps |
| T718 |
/workspace/coverage/default/2.chip_sw_kmac_mode_kmac_jitter_en_reduced_freq.991309713 |
|
|
Aug 14 06:06:27 PM PDT 24 |
Aug 14 06:12:37 PM PDT 24 |
2797881379 ps |
| T15 |
/workspace/coverage/default/0.rom_e2e_jtag_inject_dev.643009244 |
|
|
Aug 14 05:48:37 PM PDT 24 |
Aug 14 06:30:38 PM PDT 24 |
32251305443 ps |
| T719 |
/workspace/coverage/default/2.chip_sw_rv_core_ibex_rnd.1801196505 |
|
|
Aug 14 06:02:10 PM PDT 24 |
Aug 14 06:20:44 PM PDT 24 |
5726595200 ps |
| T720 |
/workspace/coverage/default/1.chip_sw_entropy_src_smoketest.166110244 |
|
|
Aug 14 05:55:20 PM PDT 24 |
Aug 14 06:05:32 PM PDT 24 |
3575207600 ps |
| T721 |
/workspace/coverage/default/65.chip_sw_alert_handler_lpg_sleep_mode_alerts.2957475474 |
|
|
Aug 14 06:14:01 PM PDT 24 |
Aug 14 06:21:19 PM PDT 24 |
4348672490 ps |
| T722 |
/workspace/coverage/default/2.rom_e2e_asm_init_prod_end.2957632304 |
|
|
Aug 14 06:14:54 PM PDT 24 |
Aug 14 07:16:56 PM PDT 24 |
16087214780 ps |
| T723 |
/workspace/coverage/default/0.chip_sw_clkmgr_off_hmac_trans.1185112904 |
|
|
Aug 14 05:53:15 PM PDT 24 |
Aug 14 06:03:35 PM PDT 24 |
5582876844 ps |
| T214 |
/workspace/coverage/default/2.chip_sw_lc_ctrl_program_error.376322569 |
|
|
Aug 14 06:05:25 PM PDT 24 |
Aug 14 06:16:39 PM PDT 24 |
4212322576 ps |
| T724 |
/workspace/coverage/default/0.rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0.13334891 |
|
|
Aug 14 05:54:52 PM PDT 24 |
Aug 14 06:40:26 PM PDT 24 |
11454332970 ps |
| T725 |
/workspace/coverage/default/2.chip_sw_entropy_src_smoketest.1127156415 |
|
|
Aug 14 06:10:42 PM PDT 24 |
Aug 14 06:21:34 PM PDT 24 |
3832482006 ps |
| T726 |
/workspace/coverage/default/2.chip_sw_flash_init.3125243521 |
|
|
Aug 14 05:59:49 PM PDT 24 |
Aug 14 06:39:20 PM PDT 24 |
26461850700 ps |
| T511 |
/workspace/coverage/default/29.chip_sw_all_escalation_resets.1899269918 |
|
|
Aug 14 06:13:00 PM PDT 24 |
Aug 14 06:21:38 PM PDT 24 |
4550763656 ps |
| T727 |
/workspace/coverage/default/0.chip_sw_clkmgr_smoketest.3605219078 |
|
|
Aug 14 05:51:37 PM PDT 24 |
Aug 14 05:56:47 PM PDT 24 |
2791633464 ps |
| T470 |
/workspace/coverage/default/11.chip_sw_all_escalation_resets.877600141 |
|
|
Aug 14 06:10:50 PM PDT 24 |
Aug 14 06:20:57 PM PDT 24 |
5339509816 ps |
| T728 |
/workspace/coverage/default/0.rom_e2e_shutdown_exception_c.252425578 |
|
|
Aug 14 05:52:51 PM PDT 24 |
Aug 14 06:44:57 PM PDT 24 |
14559509878 ps |
| T729 |
/workspace/coverage/default/1.chip_sw_csrng_edn_concurrency.382949630 |
|
|
Aug 14 05:56:24 PM PDT 24 |
Aug 14 07:02:42 PM PDT 24 |
16148185496 ps |
| T730 |
/workspace/coverage/default/1.rom_e2e_self_hash.2517185600 |
|
|
Aug 14 06:00:30 PM PDT 24 |
Aug 14 07:31:15 PM PDT 24 |
26337018668 ps |
| T117 |
/workspace/coverage/default/0.chip_sw_pwrmgr_normal_sleep_all_wake_ups.478038316 |
|
|
Aug 14 05:52:05 PM PDT 24 |
Aug 14 05:59:12 PM PDT 24 |
7591967674 ps |
| T731 |
/workspace/coverage/default/2.chip_sw_flash_ctrl_access_jitter_en_reduced_freq.2924584771 |
|
|
Aug 14 06:08:47 PM PDT 24 |
Aug 14 06:25:20 PM PDT 24 |
7501050883 ps |
| T508 |
/workspace/coverage/default/89.chip_sw_all_escalation_resets.4181144789 |
|
|
Aug 14 06:17:22 PM PDT 24 |
Aug 14 06:26:11 PM PDT 24 |
4990699088 ps |
| T342 |
/workspace/coverage/default/1.chip_sw_lc_walkthrough_prod.738564528 |
|
|
Aug 14 05:52:47 PM PDT 24 |
Aug 14 07:31:56 PM PDT 24 |
49661291258 ps |
| T732 |
/workspace/coverage/default/2.chip_sw_rv_timer_irq.3053918762 |
|
|
Aug 14 06:01:54 PM PDT 24 |
Aug 14 06:07:05 PM PDT 24 |
2925596744 ps |
| T733 |
/workspace/coverage/default/1.chip_sw_pwrmgr_main_power_glitch_reset.3559974305 |
|
|
Aug 14 05:48:45 PM PDT 24 |
Aug 14 05:53:15 PM PDT 24 |
4047122253 ps |
| T734 |
/workspace/coverage/default/0.chip_sw_aon_timer_wdog_bite_reset.2385189764 |
|
|
Aug 14 05:47:24 PM PDT 24 |
Aug 14 06:01:23 PM PDT 24 |
10106793846 ps |
| T29 |
/workspace/coverage/default/0.chip_sw_sleep_pin_mio_dio_val.2644060743 |
|
|
Aug 14 05:48:49 PM PDT 24 |
Aug 14 05:54:21 PM PDT 24 |
3284899921 ps |
| T735 |
/workspace/coverage/default/2.chip_sw_flash_ctrl_write_clear.1812177187 |
|
|
Aug 14 06:05:32 PM PDT 24 |
Aug 14 06:12:12 PM PDT 24 |
3812943592 ps |
| T465 |
/workspace/coverage/default/5.chip_sw_all_escalation_resets.1404013968 |
|
|
Aug 14 06:08:37 PM PDT 24 |
Aug 14 06:18:10 PM PDT 24 |
4828117272 ps |
| T736 |
/workspace/coverage/default/2.chip_sw_pwrmgr_deep_sleep_por_reset.3974809127 |
|
|
Aug 14 06:01:13 PM PDT 24 |
Aug 14 06:13:00 PM PDT 24 |
9046668500 ps |
| T737 |
/workspace/coverage/default/2.chip_sw_kmac_entropy.3359389390 |
|
|
Aug 14 05:59:25 PM PDT 24 |
Aug 14 06:03:33 PM PDT 24 |
2681910402 ps |
| T475 |
/workspace/coverage/default/47.chip_sw_alert_handler_lpg_sleep_mode_alerts.2876863207 |
|
|
Aug 14 06:12:27 PM PDT 24 |
Aug 14 06:18:42 PM PDT 24 |
3354747324 ps |
| T738 |
/workspace/coverage/default/2.chip_sw_rv_plic_smoketest.2365665358 |
|
|
Aug 14 06:07:36 PM PDT 24 |
Aug 14 06:12:42 PM PDT 24 |
2946617690 ps |
| T451 |
/workspace/coverage/default/57.chip_sw_alert_handler_lpg_sleep_mode_alerts.3604132182 |
|
|
Aug 14 06:14:29 PM PDT 24 |
Aug 14 06:19:55 PM PDT 24 |
3516740380 ps |
| T739 |
/workspace/coverage/default/1.chip_sw_uart_tx_rx_bootstrap.237756794 |
|
|
Aug 14 05:49:44 PM PDT 24 |
Aug 14 09:37:39 PM PDT 24 |
78466594732 ps |
| T740 |
/workspace/coverage/default/1.chip_sw_rom_ctrl_integrity_check.4119461805 |
|
|
Aug 14 05:55:12 PM PDT 24 |
Aug 14 06:06:55 PM PDT 24 |
8396669540 ps |
| T741 |
/workspace/coverage/default/2.chip_sw_hmac_multistream.2035230637 |
|
|
Aug 14 06:03:26 PM PDT 24 |
Aug 14 06:43:16 PM PDT 24 |
9325033656 ps |
| T742 |
/workspace/coverage/default/0.chip_sw_keymgr_key_derivation.1107188241 |
|
|
Aug 14 05:48:35 PM PDT 24 |
Aug 14 06:18:48 PM PDT 24 |
8738002696 ps |
| T436 |
/workspace/coverage/default/0.chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz.245200421 |
|
|
Aug 14 05:49:23 PM PDT 24 |
Aug 14 05:51:10 PM PDT 24 |
1986193767 ps |
| T487 |
/workspace/coverage/default/4.chip_sw_alert_handler_lpg_sleep_mode_alerts.1402839465 |
|
|
Aug 14 06:09:43 PM PDT 24 |
Aug 14 06:16:10 PM PDT 24 |
3545042300 ps |
| T743 |
/workspace/coverage/default/2.chip_sw_kmac_mode_cshake.3558010719 |
|
|
Aug 14 06:05:04 PM PDT 24 |
Aug 14 06:10:42 PM PDT 24 |
3324717840 ps |
| T744 |
/workspace/coverage/default/0.chip_sw_example_manufacturer.3882920027 |
|
|
Aug 14 05:48:21 PM PDT 24 |
Aug 14 05:51:54 PM PDT 24 |
3417878856 ps |
| T745 |
/workspace/coverage/default/0.rom_e2e_jtag_inject_rma.4079893781 |
|
|
Aug 14 05:54:09 PM PDT 24 |
Aug 14 06:48:07 PM PDT 24 |
26901688439 ps |
| T746 |
/workspace/coverage/default/1.chip_sw_uart_tx_rx.1956427370 |
|
|
Aug 14 05:50:48 PM PDT 24 |
Aug 14 06:02:10 PM PDT 24 |
4656469742 ps |
| T747 |
/workspace/coverage/default/1.chip_sw_clkmgr_jitter_frequency.2802866106 |
|
|
Aug 14 05:52:55 PM PDT 24 |
Aug 14 06:00:21 PM PDT 24 |
3496946000 ps |
| T748 |
/workspace/coverage/default/2.chip_sw_example_flash.2878570862 |
|
|
Aug 14 05:57:27 PM PDT 24 |
Aug 14 06:00:39 PM PDT 24 |
3478008100 ps |
| T749 |
/workspace/coverage/default/2.chip_sw_aon_timer_smoketest.251141006 |
|
|
Aug 14 06:06:37 PM PDT 24 |
Aug 14 06:12:37 PM PDT 24 |
2824324664 ps |
| T750 |
/workspace/coverage/default/1.chip_sw_clkmgr_off_aes_trans.1273759774 |
|
|
Aug 14 05:53:15 PM PDT 24 |
Aug 14 06:01:07 PM PDT 24 |
4633556330 ps |
| T751 |
/workspace/coverage/default/0.chip_sw_alert_handler_lpg_reset_toggle.2145893141 |
|
|
Aug 14 05:50:10 PM PDT 24 |
Aug 14 06:24:37 PM PDT 24 |
8180311480 ps |
| T752 |
/workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_bad_dev.1291319552 |
|
|
Aug 14 05:57:50 PM PDT 24 |
Aug 14 07:11:47 PM PDT 24 |
16371432780 ps |
| T144 |
/workspace/coverage/default/0.chip_sw_sensor_ctrl_alert.132910492 |
|
|
Aug 14 05:49:47 PM PDT 24 |
Aug 14 05:57:26 PM PDT 24 |
6434587638 ps |
| T753 |
/workspace/coverage/default/2.chip_sw_hmac_enc.1637645239 |
|
|
Aug 14 06:03:54 PM PDT 24 |
Aug 14 06:08:40 PM PDT 24 |
3463604000 ps |
| T754 |
/workspace/coverage/default/2.chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq.1367635385 |
|
|
Aug 14 06:07:10 PM PDT 24 |
Aug 14 07:12:20 PM PDT 24 |
24800182358 ps |
| T755 |
/workspace/coverage/default/0.chip_sw_flash_ctrl_clock_freqs.4275124176 |
|
|
Aug 14 05:48:22 PM PDT 24 |
Aug 14 06:07:55 PM PDT 24 |
6120515351 ps |
| T756 |
/workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_fast_rma.3011134096 |
|
|
Aug 14 05:54:48 PM PDT 24 |
Aug 14 06:05:39 PM PDT 24 |
4530836546 ps |
| T225 |
/workspace/coverage/default/0.chip_sw_csrng_lc_hw_debug_en_test.3692584962 |
|
|
Aug 14 05:50:58 PM PDT 24 |
Aug 14 06:03:26 PM PDT 24 |
5190047520 ps |
| T499 |
/workspace/coverage/default/21.chip_sw_all_escalation_resets.936051978 |
|
|
Aug 14 06:12:32 PM PDT 24 |
Aug 14 06:26:56 PM PDT 24 |
5196939072 ps |
| T757 |
/workspace/coverage/default/2.chip_sw_lc_walkthrough_rma.3163836237 |
|
|
Aug 14 06:00:16 PM PDT 24 |
Aug 14 07:26:58 PM PDT 24 |
46906057941 ps |
| T758 |
/workspace/coverage/default/0.rom_e2e_static_critical.4168860402 |
|
|
Aug 14 05:58:19 PM PDT 24 |
Aug 14 07:02:48 PM PDT 24 |
17036833104 ps |
| T759 |
/workspace/coverage/default/1.chip_sw_alert_handler_lpg_reset_toggle.181124769 |
|
|
Aug 14 05:51:41 PM PDT 24 |
Aug 14 06:25:27 PM PDT 24 |
8074285050 ps |
| T203 |
/workspace/coverage/default/1.chip_sw_otp_ctrl_vendor_test_csr_access.1892272571 |
|
|
Aug 14 05:53:46 PM PDT 24 |
Aug 14 05:55:28 PM PDT 24 |
2392455585 ps |
| T526 |
/workspace/coverage/default/35.chip_sw_alert_handler_lpg_sleep_mode_alerts.2163397945 |
|
|
Aug 14 06:14:17 PM PDT 24 |
Aug 14 06:21:51 PM PDT 24 |
3924004060 ps |
| T760 |
/workspace/coverage/default/84.chip_sw_all_escalation_resets.661986299 |
|
|
Aug 14 06:16:22 PM PDT 24 |
Aug 14 06:26:33 PM PDT 24 |
5830927056 ps |
| T226 |
/workspace/coverage/default/0.chip_sw_csrng_fuse_en_sw_app_read_test.952620702 |
|
|
Aug 14 05:52:05 PM PDT 24 |
Aug 14 06:02:37 PM PDT 24 |
4552794504 ps |
| T761 |
/workspace/coverage/default/1.chip_sw_entropy_src_ast_rng_req.1418722900 |
|
|
Aug 14 05:52:04 PM PDT 24 |
Aug 14 05:56:25 PM PDT 24 |
2141967860 ps |
| T762 |
/workspace/coverage/default/1.chip_sw_sleep_sram_ret_contents_scramble.1040341924 |
|
|
Aug 14 05:53:53 PM PDT 24 |
Aug 14 06:04:54 PM PDT 24 |
7649033690 ps |
| T763 |
/workspace/coverage/default/2.chip_sw_hmac_oneshot.2424657677 |
|
|
Aug 14 06:03:15 PM PDT 24 |
Aug 14 06:09:37 PM PDT 24 |
3438354580 ps |
| T764 |
/workspace/coverage/default/2.rom_e2e_static_critical.846814898 |
|
|
Aug 14 06:11:26 PM PDT 24 |
Aug 14 07:13:08 PM PDT 24 |
16778661368 ps |
| T765 |
/workspace/coverage/default/2.chip_sw_adc_ctrl_sleep_debug_cable_wakeup.3131627258 |
|
|
Aug 14 06:03:29 PM PDT 24 |
Aug 14 06:11:26 PM PDT 24 |
18436424470 ps |
| T63 |
/workspace/coverage/default/1.chip_sw_power_virus.2084950056 |
|
|
Aug 14 06:00:32 PM PDT 24 |
Aug 14 06:25:34 PM PDT 24 |
6393920280 ps |
| T324 |
/workspace/coverage/default/2.chip_sw_gpio_smoketest.2852852421 |
|
|
Aug 14 06:07:41 PM PDT 24 |
Aug 14 06:12:19 PM PDT 24 |
2209326430 ps |
| T766 |
/workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_bad_rma.2690807279 |
|
|
Aug 14 05:59:07 PM PDT 24 |
Aug 14 06:52:51 PM PDT 24 |
14301676820 ps |
| T118 |
/workspace/coverage/default/0.chip_sw_pwrmgr_random_sleep_all_wake_ups.3139659317 |
|
|
Aug 14 05:52:13 PM PDT 24 |
Aug 14 06:18:27 PM PDT 24 |
21922523778 ps |
| T254 |
/workspace/coverage/default/1.chip_sw_sysrst_ctrl_in_irq.1027792932 |
|
|
Aug 14 05:53:02 PM PDT 24 |
Aug 14 06:02:28 PM PDT 24 |
4208733606 ps |
| T767 |
/workspace/coverage/default/2.rom_e2e_asm_init_prod.635940861 |
|
|
Aug 14 06:10:43 PM PDT 24 |
Aug 14 07:11:34 PM PDT 24 |
15587348618 ps |
| T768 |
/workspace/coverage/default/2.chip_sw_clkmgr_off_peri.3167752369 |
|
|
Aug 14 06:05:08 PM PDT 24 |
Aug 14 06:30:04 PM PDT 24 |
10104325954 ps |
| T769 |
/workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_nothing_prod_end.3095071144 |
|
|
Aug 14 05:57:57 PM PDT 24 |
Aug 14 06:58:59 PM PDT 24 |
14747479539 ps |
| T770 |
/workspace/coverage/default/2.chip_sw_uart_tx_rx_bootstrap.3213329710 |
|
|
Aug 14 05:56:16 PM PDT 24 |
Aug 14 09:34:56 PM PDT 24 |
78450428062 ps |
| T771 |
/workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_fast_rma.121591370 |
|
|
Aug 14 05:50:59 PM PDT 24 |
Aug 14 06:02:18 PM PDT 24 |
4373223432 ps |
| T772 |
/workspace/coverage/default/4.chip_sw_aon_timer_sleep_wdog_sleep_pause.2336942868 |
|
|
Aug 14 06:09:35 PM PDT 24 |
Aug 14 06:17:22 PM PDT 24 |
7974742844 ps |
| T773 |
/workspace/coverage/default/2.chip_sw_otp_ctrl_lc_signals_rma.4077814059 |
|
|
Aug 14 06:00:10 PM PDT 24 |
Aug 14 06:23:30 PM PDT 24 |
8681731000 ps |
| T774 |
/workspace/coverage/default/1.chip_sw_pwrmgr_sleep_wake_5_bug.4287356365 |
|
|
Aug 14 05:52:22 PM PDT 24 |
Aug 14 06:00:37 PM PDT 24 |
6034934888 ps |
| T61 |
/workspace/coverage/default/1.chip_sw_spi_device_pass_through.3127640298 |
|
|
Aug 14 05:54:42 PM PDT 24 |
Aug 14 06:06:24 PM PDT 24 |
5550413601 ps |
| T775 |
/workspace/coverage/default/1.chip_sw_edn_entropy_reqs.807431164 |
|
|
Aug 14 05:50:30 PM PDT 24 |
Aug 14 06:06:09 PM PDT 24 |
5739973652 ps |
| T776 |
/workspace/coverage/default/2.chip_sw_data_integrity_escalation.3987462268 |
|
|
Aug 14 05:55:08 PM PDT 24 |
Aug 14 06:04:08 PM PDT 24 |
5124849064 ps |
| T437 |
/workspace/coverage/default/2.chip_sw_lc_ctrl_volatile_raw_unlock.1835653678 |
|
|
Aug 14 05:58:17 PM PDT 24 |
Aug 14 05:59:58 PM PDT 24 |
2515043272 ps |
| T230 |
/workspace/coverage/default/0.chip_plic_all_irqs_20.590156483 |
|
|
Aug 14 05:53:09 PM PDT 24 |
Aug 14 06:06:09 PM PDT 24 |
4108690594 ps |
| T497 |
/workspace/coverage/default/58.chip_sw_all_escalation_resets.366074047 |
|
|
Aug 14 06:13:35 PM PDT 24 |
Aug 14 06:21:32 PM PDT 24 |
5504295584 ps |
| T513 |
/workspace/coverage/default/24.chip_sw_alert_handler_lpg_sleep_mode_alerts.3501770501 |
|
|
Aug 14 06:11:29 PM PDT 24 |
Aug 14 06:16:59 PM PDT 24 |
3732541892 ps |
| T777 |
/workspace/coverage/default/1.chip_tap_straps_prod.819073765 |
|
|
Aug 14 05:54:11 PM PDT 24 |
Aug 14 06:10:07 PM PDT 24 |
8773876754 ps |
| T778 |
/workspace/coverage/default/1.chip_sw_uart_tx_rx_alt_clk_freq.668812153 |
|
|
Aug 14 05:50:04 PM PDT 24 |
Aug 14 06:23:01 PM PDT 24 |
9333642177 ps |
| T779 |
/workspace/coverage/default/0.chip_sw_lc_walkthrough_testunlocks.3167604564 |
|
|
Aug 14 05:50:55 PM PDT 24 |
Aug 14 06:29:03 PM PDT 24 |
27979822839 ps |
| T780 |
/workspace/coverage/default/0.chip_sw_aon_timer_smoketest.1341877044 |
|
|
Aug 14 05:49:09 PM PDT 24 |
Aug 14 05:54:34 PM PDT 24 |
2767749742 ps |
| T781 |
/workspace/coverage/default/1.chip_sw_edn_kat.1538997278 |
|
|
Aug 14 05:55:52 PM PDT 24 |
Aug 14 06:09:07 PM PDT 24 |
3028316260 ps |
| T782 |
/workspace/coverage/default/1.rom_e2e_asm_init_test_unlocked0.3888127830 |
|
|
Aug 14 05:59:25 PM PDT 24 |
Aug 14 06:46:41 PM PDT 24 |
11964166908 ps |
| T308 |
/workspace/coverage/default/2.chip_sw_rv_core_ibex_icache_invalidate.3135066928 |
|
|
Aug 14 06:05:56 PM PDT 24 |
Aug 14 06:11:06 PM PDT 24 |
2768321174 ps |
| T145 |
/workspace/coverage/default/0.chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup.1069862976 |
|
|
Aug 14 05:48:40 PM PDT 24 |
Aug 14 05:57:35 PM PDT 24 |
5012081400 ps |
| T783 |
/workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_bad_b_good_prod.1204849348 |
|
|
Aug 14 05:53:54 PM PDT 24 |
Aug 14 07:33:09 PM PDT 24 |
23610001876 ps |
| T784 |
/workspace/coverage/default/2.chip_sw_clkmgr_sleep_frequency.2915967128 |
|
|
Aug 14 06:05:56 PM PDT 24 |
Aug 14 06:18:18 PM PDT 24 |
4388104966 ps |
| T321 |
/workspace/coverage/default/81.chip_sw_all_escalation_resets.2324097482 |
|
|
Aug 14 06:18:16 PM PDT 24 |
Aug 14 06:27:29 PM PDT 24 |
5369826322 ps |
| T528 |
/workspace/coverage/default/49.chip_sw_all_escalation_resets.946245582 |
|
|
Aug 14 06:15:17 PM PDT 24 |
Aug 14 06:27:41 PM PDT 24 |
6035469570 ps |
| T785 |
/workspace/coverage/default/0.chip_sw_otbn_mem_scramble.2866543325 |
|
|
Aug 14 05:48:56 PM PDT 24 |
Aug 14 05:59:47 PM PDT 24 |
3637555860 ps |
| T202 |
/workspace/coverage/default/2.rom_raw_unlock.2679466945 |
|
|
Aug 14 06:06:34 PM PDT 24 |
Aug 14 06:10:54 PM PDT 24 |
5144064192 ps |
| T786 |
/workspace/coverage/default/1.rom_e2e_asm_init_prod_end.155995754 |
|
|
Aug 14 05:58:01 PM PDT 24 |
Aug 14 07:02:35 PM PDT 24 |
15410961929 ps |
| T485 |
/workspace/coverage/default/69.chip_sw_all_escalation_resets.1759827617 |
|
|
Aug 14 06:15:15 PM PDT 24 |
Aug 14 06:26:05 PM PDT 24 |
6011163070 ps |
| T391 |
/workspace/coverage/default/1.chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up.4052616749 |
|
|
Aug 14 05:54:11 PM PDT 24 |
Aug 14 06:01:32 PM PDT 24 |
5229855716 ps |
| T488 |
/workspace/coverage/default/14.chip_sw_all_escalation_resets.3446444837 |
|
|
Aug 14 06:11:38 PM PDT 24 |
Aug 14 06:22:00 PM PDT 24 |
5609016024 ps |
| T544 |
/workspace/coverage/default/19.chip_sw_all_escalation_resets.95833127 |
|
|
Aug 14 06:12:19 PM PDT 24 |
Aug 14 06:21:12 PM PDT 24 |
5231395582 ps |
| T540 |
/workspace/coverage/default/80.chip_sw_alert_handler_lpg_sleep_mode_alerts.2778040084 |
|
|
Aug 14 06:17:56 PM PDT 24 |
Aug 14 06:24:52 PM PDT 24 |
3856050576 ps |
| T787 |
/workspace/coverage/default/1.chip_sw_pwrmgr_smoketest.2206723234 |
|
|
Aug 14 05:57:56 PM PDT 24 |
Aug 14 06:06:47 PM PDT 24 |
6570256750 ps |
| T234 |
/workspace/coverage/default/1.chip_plic_all_irqs_0.1969715305 |
|
|
Aug 14 05:57:37 PM PDT 24 |
Aug 14 06:18:59 PM PDT 24 |
5517594588 ps |
| T551 |
/workspace/coverage/default/46.chip_sw_all_escalation_resets.378520222 |
|
|
Aug 14 06:13:17 PM PDT 24 |
Aug 14 06:24:29 PM PDT 24 |
4764612624 ps |
| T788 |
/workspace/coverage/default/0.chip_sw_uart_tx_rx_alt_clk_freq.1501499078 |
|
|
Aug 14 05:49:24 PM PDT 24 |
Aug 14 06:24:11 PM PDT 24 |
7863036544 ps |
| T789 |
/workspace/coverage/default/72.chip_sw_alert_handler_lpg_sleep_mode_alerts.1853405742 |
|
|
Aug 14 06:15:07 PM PDT 24 |
Aug 14 06:22:53 PM PDT 24 |
4168745248 ps |
| T790 |
/workspace/coverage/default/2.chip_sw_exit_test_unlocked_bootstrap.1073990304 |
|
|
Aug 14 05:56:48 PM PDT 24 |
Aug 14 08:37:37 PM PDT 24 |
57081447180 ps |
| T105 |
/workspace/coverage/default/33.chip_sw_alert_handler_lpg_sleep_mode_alerts.3284120009 |
|
|
Aug 14 06:11:23 PM PDT 24 |
Aug 14 06:17:19 PM PDT 24 |
3869773428 ps |
| T791 |
/workspace/coverage/default/2.chip_sw_alert_handler_reverse_ping_in_deep_sleep.357111902 |
|
|
Aug 14 06:02:31 PM PDT 24 |
Aug 14 09:38:01 PM PDT 24 |
255065009480 ps |
| T522 |
/workspace/coverage/default/8.chip_sw_all_escalation_resets.3909638825 |
|
|
Aug 14 06:11:06 PM PDT 24 |
Aug 14 06:18:14 PM PDT 24 |
4721004168 ps |
| T464 |
/workspace/coverage/default/18.chip_sw_all_escalation_resets.2779266364 |
|
|
Aug 14 06:11:31 PM PDT 24 |
Aug 14 06:21:00 PM PDT 24 |
4332495188 ps |
| T477 |
/workspace/coverage/default/0.chip_sw_alert_handler_lpg_sleep_mode_pings.3047619925 |
|
|
Aug 14 05:52:51 PM PDT 24 |
Aug 14 06:15:19 PM PDT 24 |
12571187718 ps |
| T792 |
/workspace/coverage/default/0.chip_tap_straps_rma.3528392868 |
|
|
Aug 14 05:50:42 PM PDT 24 |
Aug 14 05:59:52 PM PDT 24 |
6364753133 ps |
| T793 |
/workspace/coverage/default/0.chip_sw_pwrmgr_normal_sleep_por_reset.2878896442 |
|
|
Aug 14 05:51:22 PM PDT 24 |
Aug 14 06:06:36 PM PDT 24 |
6220135805 ps |
| T363 |
/workspace/coverage/default/2.chip_sw_pwrmgr_lowpower_cancel.1117894233 |
|
|
Aug 14 06:04:48 PM PDT 24 |
Aug 14 06:14:15 PM PDT 24 |
3859161544 ps |
| T47 |
/workspace/coverage/default/1.chip_sw_gpio.4057735088 |
|
|
Aug 14 05:51:12 PM PDT 24 |
Aug 14 05:58:16 PM PDT 24 |
3223891008 ps |
| T794 |
/workspace/coverage/default/7.chip_sw_uart_rand_baudrate.3485283114 |
|
|
Aug 14 06:08:53 PM PDT 24 |
Aug 14 06:31:44 PM PDT 24 |
8423751730 ps |
| T795 |
/workspace/coverage/default/1.chip_sw_lc_ctrl_otp_hw_cfg0.1812158070 |
|
|
Aug 14 05:52:49 PM PDT 24 |
Aug 14 05:58:15 PM PDT 24 |
2639675768 ps |
| T796 |
/workspace/coverage/default/2.chip_sw_pwrmgr_full_aon_reset.66047930 |
|
|
Aug 14 05:59:43 PM PDT 24 |
Aug 14 06:10:47 PM PDT 24 |
10157744452 ps |
| T797 |
/workspace/coverage/default/2.chip_sw_rstmgr_smoketest.1513628971 |
|
|
Aug 14 06:07:39 PM PDT 24 |
Aug 14 06:11:37 PM PDT 24 |
3391727500 ps |
| T798 |
/workspace/coverage/default/2.chip_sw_uart_tx_rx_idx3.2414558176 |
|
|
Aug 14 05:56:20 PM PDT 24 |
Aug 14 06:06:12 PM PDT 24 |
4339356454 ps |
| T486 |
/workspace/coverage/default/53.chip_sw_all_escalation_resets.3126985555 |
|
|
Aug 14 06:14:45 PM PDT 24 |
Aug 14 06:27:00 PM PDT 24 |
6083430472 ps |
| T16 |
/workspace/coverage/default/1.chip_sw_rv_dm_ndm_reset_req_when_cpu_halted.2227585424 |
|
|
Aug 14 05:53:56 PM PDT 24 |
Aug 14 06:02:25 PM PDT 24 |
3843034656 ps |
| T799 |
/workspace/coverage/default/1.chip_sw_example_manufacturer.4108554107 |
|
|
Aug 14 05:49:29 PM PDT 24 |
Aug 14 05:52:58 PM PDT 24 |
2850619516 ps |
| T83 |
/workspace/coverage/default/1.chip_sw_sleep_pin_wake.1949738528 |
|
|
Aug 14 05:52:52 PM PDT 24 |
Aug 14 05:57:04 PM PDT 24 |
3377054108 ps |
| T417 |
/workspace/coverage/default/1.chip_sival_flash_info_access.3625860848 |
|
|
Aug 14 05:51:45 PM PDT 24 |
Aug 14 05:56:56 PM PDT 24 |
3518199900 ps |
| T418 |
/workspace/coverage/default/0.chip_tap_straps_dev.436223239 |
|
|
Aug 14 05:48:07 PM PDT 24 |
Aug 14 06:06:37 PM PDT 24 |
9591067324 ps |
| T269 |
/workspace/coverage/default/2.chip_sw_power_sleep_load.2383892094 |
|
|
Aug 14 06:08:50 PM PDT 24 |
Aug 14 06:15:55 PM PDT 24 |
4328940778 ps |
| T419 |
/workspace/coverage/default/62.chip_sw_alert_handler_lpg_sleep_mode_alerts.3333428335 |
|
|
Aug 14 06:16:16 PM PDT 24 |
Aug 14 06:22:29 PM PDT 24 |
4278697848 ps |
| T62 |
/workspace/coverage/default/2.chip_sw_spi_device_pass_through.3035007811 |
|
|
Aug 14 05:59:48 PM PDT 24 |
Aug 14 06:10:52 PM PDT 24 |
6175114151 ps |
| T420 |
/workspace/coverage/default/0.chip_sw_rstmgr_sw_req.4195015329 |
|
|
Aug 14 05:49:17 PM PDT 24 |
Aug 14 05:57:47 PM PDT 24 |
4669903944 ps |
| T421 |
/workspace/coverage/default/0.rom_e2e_shutdown_output.3042371584 |
|
|
Aug 14 05:53:04 PM PDT 24 |
Aug 14 06:48:08 PM PDT 24 |
25986359210 ps |
| T422 |
/workspace/coverage/default/0.chip_sw_keymgr_key_derivation_jitter_en_reduced_freq.2594216994 |
|
|
Aug 14 05:50:00 PM PDT 24 |
Aug 14 06:22:11 PM PDT 24 |
12454135951 ps |
| T423 |
/workspace/coverage/default/43.chip_sw_all_escalation_resets.2595458387 |
|
|
Aug 14 06:12:23 PM PDT 24 |
Aug 14 06:22:29 PM PDT 24 |
6143314744 ps |
| T800 |
/workspace/coverage/default/1.chip_sw_flash_scrambling_smoketest.271134343 |
|
|
Aug 14 05:57:29 PM PDT 24 |
Aug 14 06:00:34 PM PDT 24 |
2689676722 ps |
| T449 |
/workspace/coverage/default/18.chip_sw_alert_handler_lpg_sleep_mode_alerts.1987983552 |
|
|
Aug 14 06:13:08 PM PDT 24 |
Aug 14 06:18:32 PM PDT 24 |
3478649432 ps |
| T801 |
/workspace/coverage/default/2.chip_sw_rv_timer_smoketest.2672060248 |
|
|
Aug 14 06:11:29 PM PDT 24 |
Aug 14 06:18:02 PM PDT 24 |
3016602888 ps |
| T802 |
/workspace/coverage/default/73.chip_sw_all_escalation_resets.3007751556 |
|
|
Aug 14 06:15:34 PM PDT 24 |
Aug 14 06:26:14 PM PDT 24 |
6070411694 ps |
| T270 |
/workspace/coverage/default/1.chip_sw_plic_sw_irq.401412333 |
|
|
Aug 14 05:50:27 PM PDT 24 |
Aug 14 05:54:23 PM PDT 24 |
2928402752 ps |
| T106 |
/workspace/coverage/default/20.chip_sw_alert_handler_lpg_sleep_mode_alerts.3427628434 |
|
|
Aug 14 06:13:20 PM PDT 24 |
Aug 14 06:20:01 PM PDT 24 |
3489689214 ps |
| T101 |
/workspace/coverage/default/2.chip_jtag_csr_rw.415199552 |
|
|
Aug 14 05:58:09 PM PDT 24 |
Aug 14 06:02:44 PM PDT 24 |
4378821652 ps |
| T803 |
/workspace/coverage/default/0.chip_sw_otp_ctrl_lc_signals_rma.3983293570 |
|
|
Aug 14 05:51:45 PM PDT 24 |
Aug 14 06:16:19 PM PDT 24 |
9482986046 ps |
| T804 |
/workspace/coverage/default/2.chip_sw_i2c_host_tx_rx.3532414520 |
|
|
Aug 14 05:58:54 PM PDT 24 |
Aug 14 06:13:42 PM PDT 24 |
4679269342 ps |
| T805 |
/workspace/coverage/default/0.rom_e2e_asm_init_test_unlocked0.1257572612 |
|
|
Aug 14 05:58:08 PM PDT 24 |
Aug 14 07:00:09 PM PDT 24 |
11404564200 ps |
| T806 |
/workspace/coverage/default/96.chip_sw_all_escalation_resets.2382975340 |
|
|
Aug 14 06:17:42 PM PDT 24 |
Aug 14 06:24:33 PM PDT 24 |
4076981720 ps |
| T59 |
/workspace/coverage/default/0.chip_sw_spi_device_tpm.2256443888 |
|
|
Aug 14 05:50:46 PM PDT 24 |
Aug 14 05:57:07 PM PDT 24 |
3032816283 ps |
| T807 |
/workspace/coverage/default/2.chip_sw_ast_clk_outputs.2784336409 |
|
|
Aug 14 06:06:14 PM PDT 24 |
Aug 14 06:24:35 PM PDT 24 |
6796966184 ps |
| T454 |
/workspace/coverage/default/78.chip_sw_all_escalation_resets.708999776 |
|
|
Aug 14 06:17:46 PM PDT 24 |
Aug 14 06:27:04 PM PDT 24 |
5412699752 ps |
| T808 |
/workspace/coverage/default/1.chip_sw_rv_core_ibex_rnd.1874707658 |
|
|
Aug 14 05:54:26 PM PDT 24 |
Aug 14 06:13:13 PM PDT 24 |
5491862760 ps |
| T809 |
/workspace/coverage/default/1.chip_sw_exit_test_unlocked_bootstrap.2684539020 |
|
|
Aug 14 05:49:13 PM PDT 24 |
Aug 14 08:31:51 PM PDT 24 |
59877713290 ps |
| T810 |
/workspace/coverage/default/2.chip_sw_otp_ctrl_lc_signals_test_unlocked0.3836180364 |
|
|
Aug 14 05:59:31 PM PDT 24 |
Aug 14 06:10:10 PM PDT 24 |
3838164070 ps |
| T57 |
/workspace/coverage/default/1.chip_sw_sysrst_ctrl_ulp_z3_wakeup.567172694 |
|
|
Aug 14 05:52:02 PM PDT 24 |
Aug 14 05:59:02 PM PDT 24 |
5373378922 ps |
| T520 |
/workspace/coverage/default/45.chip_sw_alert_handler_lpg_sleep_mode_alerts.3727148893 |
|
|
Aug 14 06:13:36 PM PDT 24 |
Aug 14 06:21:59 PM PDT 24 |
3067765546 ps |
| T811 |
/workspace/coverage/default/2.chip_sw_clkmgr_smoketest.527556157 |
|
|
Aug 14 06:08:54 PM PDT 24 |
Aug 14 06:12:38 PM PDT 24 |
2351706532 ps |
| T812 |
/workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_good_rma.2013279606 |
|
|
Aug 14 05:55:15 PM PDT 24 |
Aug 14 07:00:39 PM PDT 24 |
14629889104 ps |
| T52 |
/workspace/coverage/default/1.chip_sw_spi_host_tx_rx.1594829807 |
|
|
Aug 14 05:55:13 PM PDT 24 |
Aug 14 06:01:00 PM PDT 24 |
3020659000 ps |
| T813 |
/workspace/coverage/default/61.chip_sw_all_escalation_resets.3577065611 |
|
|
Aug 14 06:14:34 PM PDT 24 |
Aug 14 06:25:26 PM PDT 24 |
5510780840 ps |
| T814 |
/workspace/coverage/default/1.chip_sw_aon_timer_sleep_wdog_sleep_pause.1753051552 |
|
|
Aug 14 05:55:48 PM PDT 24 |
Aug 14 06:05:38 PM PDT 24 |
7203529268 ps |
| T207 |
/workspace/coverage/default/85.chip_sw_all_escalation_resets.3647461817 |
|
|
Aug 14 06:15:22 PM PDT 24 |
Aug 14 06:23:30 PM PDT 24 |
4951891698 ps |
| T815 |
/workspace/coverage/default/1.chip_sw_entropy_src_kat_test.2687731966 |
|
|
Aug 14 05:51:29 PM PDT 24 |
Aug 14 05:56:02 PM PDT 24 |
3214925352 ps |
| T379 |
/workspace/coverage/default/95.chip_sw_all_escalation_resets.1472255928 |
|
|
Aug 14 06:16:36 PM PDT 24 |
Aug 14 06:24:53 PM PDT 24 |
4366010512 ps |
| T816 |
/workspace/coverage/default/0.rom_e2e_sigverify_always_a_nothing_b_bad_dev.2433364442 |
|
|
Aug 14 05:59:01 PM PDT 24 |
Aug 14 07:12:26 PM PDT 24 |
15565131630 ps |
| T817 |
/workspace/coverage/default/0.chip_sw_example_rom.1889089112 |
|
|
Aug 14 05:47:36 PM PDT 24 |
Aug 14 05:50:12 PM PDT 24 |
2026920152 ps |
| T381 |
/workspace/coverage/default/2.chip_sw_pwrmgr_sleep_disabled.425891368 |
|
|
Aug 14 06:02:22 PM PDT 24 |
Aug 14 06:06:54 PM PDT 24 |
2482440260 ps |
| T818 |
/workspace/coverage/default/13.chip_sw_alert_handler_lpg_sleep_mode_alerts.1286637285 |
|
|
Aug 14 06:10:35 PM PDT 24 |
Aug 14 06:18:03 PM PDT 24 |
3899701060 ps |
| T819 |
/workspace/coverage/default/2.chip_sw_flash_ctrl_access_jitter_en.366918393 |
|
|
Aug 14 05:59:01 PM PDT 24 |
Aug 14 06:16:51 PM PDT 24 |
6449320544 ps |
| T820 |
/workspace/coverage/default/2.chip_sw_example_rom.874016898 |
|
|
Aug 14 05:55:17 PM PDT 24 |
Aug 14 05:57:22 PM PDT 24 |
2306849884 ps |
| T821 |
/workspace/coverage/default/3.chip_sw_uart_tx_rx_alt_clk_freq.871099847 |
|
|
Aug 14 06:08:43 PM PDT 24 |
Aug 14 06:30:43 PM PDT 24 |
7842724082 ps |
| T271 |
/workspace/coverage/default/2.chip_sw_plic_sw_irq.2804718557 |
|
|
Aug 14 06:05:25 PM PDT 24 |
Aug 14 06:09:25 PM PDT 24 |
2265575980 ps |
| T822 |
/workspace/coverage/default/2.chip_sw_keymgr_key_derivation_jitter_en.1902318974 |
|
|
Aug 14 06:03:52 PM PDT 24 |
Aug 14 06:26:51 PM PDT 24 |
8643249353 ps |
| T823 |
/workspace/coverage/default/2.chip_sw_keymgr_sideload_kmac.3863966498 |
|
|
Aug 14 06:03:57 PM PDT 24 |
Aug 14 06:26:02 PM PDT 24 |
6329087326 ps |
| T824 |
/workspace/coverage/default/0.chip_sw_clkmgr_jitter_frequency.1451092920 |
|
|
Aug 14 05:47:55 PM PDT 24 |
Aug 14 05:55:10 PM PDT 24 |
3975140410 ps |
| T825 |
/workspace/coverage/default/7.chip_sw_lc_ctrl_transition.3120586832 |
|
|
Aug 14 06:09:22 PM PDT 24 |
Aug 14 06:20:53 PM PDT 24 |
7607080388 ps |
| T545 |
/workspace/coverage/default/7.chip_sw_all_escalation_resets.2524357340 |
|
|
Aug 14 06:10:59 PM PDT 24 |
Aug 14 06:19:32 PM PDT 24 |
6127122368 ps |
| T555 |
/workspace/coverage/default/84.chip_sw_alert_handler_lpg_sleep_mode_alerts.1196812461 |
|
|
Aug 14 06:17:30 PM PDT 24 |
Aug 14 06:24:13 PM PDT 24 |
4170472598 ps |
| T495 |
/workspace/coverage/default/9.chip_sw_alert_handler_lpg_sleep_mode_alerts.446715004 |
|
|
Aug 14 06:09:36 PM PDT 24 |
Aug 14 06:15:37 PM PDT 24 |
3522135716 ps |
| T505 |
/workspace/coverage/default/98.chip_sw_all_escalation_resets.4150311657 |
|
|
Aug 14 06:16:42 PM PDT 24 |
Aug 14 06:26:02 PM PDT 24 |
5530267916 ps |
| T357 |
/workspace/coverage/default/0.chip_sw_i2c_host_tx_rx_idx1.532700464 |
|
|
Aug 14 05:49:14 PM PDT 24 |
Aug 14 06:06:27 PM PDT 24 |
5347496400 ps |
| T826 |
/workspace/coverage/default/0.chip_sw_flash_ctrl_write_clear.1164470900 |
|
|
Aug 14 05:49:41 PM PDT 24 |
Aug 14 05:57:22 PM PDT 24 |
2772810514 ps |
| T283 |
/workspace/coverage/default/42.chip_sw_all_escalation_resets.762267365 |
|
|
Aug 14 06:13:45 PM PDT 24 |
Aug 14 06:24:30 PM PDT 24 |
4378703640 ps |
| T231 |
/workspace/coverage/default/1.chip_plic_all_irqs_20.3715513551 |
|
|
Aug 14 05:54:56 PM PDT 24 |
Aug 14 06:08:21 PM PDT 24 |
5405410492 ps |
| T189 |
/workspace/coverage/default/0.chip_jtag_mem_access.2235357278 |
|
|
Aug 14 05:39:57 PM PDT 24 |
Aug 14 06:07:46 PM PDT 24 |
14306560120 ps |
| T358 |
/workspace/coverage/default/1.chip_sw_i2c_host_tx_rx_idx2.3182284526 |
|
|
Aug 14 05:53:05 PM PDT 24 |
Aug 14 06:11:41 PM PDT 24 |
5688630648 ps |
| T386 |
/workspace/coverage/default/38.chip_sw_all_escalation_resets.3621665469 |
|
|
Aug 14 06:16:03 PM PDT 24 |
Aug 14 06:24:04 PM PDT 24 |
4033113960 ps |
| T827 |
/workspace/coverage/default/1.chip_sw_flash_ctrl_access_jitter_en.142478082 |
|
|
Aug 14 05:49:13 PM PDT 24 |
Aug 14 06:08:37 PM PDT 24 |
5251057647 ps |
| T215 |
/workspace/coverage/default/1.chip_sw_lc_ctrl_program_error.3056361099 |
|
|
Aug 14 05:52:05 PM PDT 24 |
Aug 14 06:01:53 PM PDT 24 |
5404863600 ps |
| T255 |
/workspace/coverage/default/1.chip_sw_sysrst_ctrl_outputs.1758088791 |
|
|
Aug 14 05:50:37 PM PDT 24 |
Aug 14 05:55:39 PM PDT 24 |
4071571179 ps |
| T365 |
/workspace/coverage/default/0.chip_sw_pwrmgr_lowpower_cancel.3117038579 |
|
|
Aug 14 05:47:37 PM PDT 24 |
Aug 14 05:55:15 PM PDT 24 |
3476133940 ps |
| T828 |
/workspace/coverage/default/2.chip_sw_power_idle_load.3208283771 |
|
|
Aug 14 06:07:36 PM PDT 24 |
Aug 14 06:17:06 PM PDT 24 |
4494143252 ps |
| T829 |
/workspace/coverage/default/8.chip_sw_uart_rand_baudrate.3433986326 |
|
|
Aug 14 06:10:58 PM PDT 24 |
Aug 14 06:31:22 PM PDT 24 |
8373805148 ps |
| T830 |
/workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_bad_prod.1717861440 |
|
|
Aug 14 05:55:19 PM PDT 24 |
Aug 14 07:32:55 PM PDT 24 |
24073813750 ps |
| T490 |
/workspace/coverage/default/17.chip_sw_all_escalation_resets.3045065663 |
|
|
Aug 14 06:11:31 PM PDT 24 |
Aug 14 06:19:47 PM PDT 24 |
4272594214 ps |
| T107 |
/workspace/coverage/default/12.chip_sw_alert_handler_lpg_sleep_mode_alerts.1192664245 |
|
|
Aug 14 06:11:21 PM PDT 24 |
Aug 14 06:18:40 PM PDT 24 |
3933318294 ps |
| T831 |
/workspace/coverage/default/0.chip_sw_alert_handler_reverse_ping_in_deep_sleep.3936279941 |
|
|
Aug 14 05:50:34 PM PDT 24 |
Aug 14 09:02:47 PM PDT 24 |
255795936466 ps |
| T832 |
/workspace/coverage/default/9.chip_sw_csrng_edn_concurrency.549163075 |
|
|
Aug 14 06:11:35 PM PDT 24 |
Aug 14 08:05:23 PM PDT 24 |
35017355312 ps |
| T833 |
/workspace/coverage/default/2.chip_sw_pwrmgr_wdog_reset.817226155 |
|
|
Aug 14 06:03:30 PM PDT 24 |
Aug 14 06:12:16 PM PDT 24 |
4423763932 ps |
| T834 |
/workspace/coverage/default/1.chip_sw_otp_ctrl_lc_signals_dev.1817751266 |
|
|
Aug 14 05:49:54 PM PDT 24 |
Aug 14 06:13:50 PM PDT 24 |
7903844800 ps |
| T256 |
/workspace/coverage/default/2.chip_sw_sysrst_ctrl_outputs.4233579875 |
|
|
Aug 14 06:01:34 PM PDT 24 |
Aug 14 06:07:20 PM PDT 24 |
3261807848 ps |
| T257 |
/workspace/coverage/default/0.chip_sw_sysrst_ctrl_inputs.2750906639 |
|
|
Aug 14 05:48:32 PM PDT 24 |
Aug 14 05:56:41 PM PDT 24 |
3207005072 ps |
| T835 |
/workspace/coverage/default/0.chip_sw_exit_test_unlocked_bootstrap.2128342657 |
|
|
Aug 14 05:48:19 PM PDT 24 |
Aug 14 09:04:58 PM PDT 24 |
57784989096 ps |
| T433 |
/workspace/coverage/default/2.chip_sw_rv_dm_access_after_escalation_reset.2474672032 |
|
|
Aug 14 06:05:34 PM PDT 24 |
Aug 14 06:17:27 PM PDT 24 |
5638658006 ps |
| T836 |
/workspace/coverage/default/1.chip_sw_gpio_smoketest.3650459257 |
|
|
Aug 14 05:56:04 PM PDT 24 |
Aug 14 06:02:08 PM PDT 24 |
2445090074 ps |
| T837 |
/workspace/coverage/default/1.rom_e2e_smoke.1940295806 |
|
|
Aug 14 05:57:58 PM PDT 24 |
Aug 14 06:56:46 PM PDT 24 |
14517938596 ps |
| T838 |
/workspace/coverage/default/3.chip_sw_uart_tx_rx_alt_clk_freq_low_speed.2156560717 |
|
|
Aug 14 06:07:49 PM PDT 24 |
Aug 14 06:15:43 PM PDT 24 |
4425249365 ps |
| T839 |
/workspace/coverage/default/0.chip_sw_pwrmgr_full_aon_reset.953606827 |
|
|
Aug 14 05:47:47 PM PDT 24 |
Aug 14 05:58:55 PM PDT 24 |
7651578095 ps |
| T840 |
/workspace/coverage/default/1.chip_sw_clkmgr_sleep_frequency.1698009262 |
|
|
Aug 14 05:55:46 PM PDT 24 |
Aug 14 06:06:29 PM PDT 24 |
4886400500 ps |
| T194 |
/workspace/coverage/default/2.chip_sw_sram_ctrl_execution_main.2376986893 |
|
|
Aug 14 06:07:18 PM PDT 24 |
Aug 14 06:21:03 PM PDT 24 |
7165538164 ps |
| T193 |
/workspace/coverage/default/0.rom_e2e_jtag_debug_dev.163765351 |
|
|
Aug 14 05:50:58 PM PDT 24 |
Aug 14 06:24:35 PM PDT 24 |
10839441850 ps |
| T841 |
/workspace/coverage/default/2.chip_sw_uart_tx_rx_alt_clk_freq.3681957008 |
|
|
Aug 14 05:57:52 PM PDT 24 |
Aug 14 06:08:17 PM PDT 24 |
4781502336 ps |
| T842 |
/workspace/coverage/default/0.chip_sw_clkmgr_off_aes_trans.3378594684 |
|
|
Aug 14 05:48:47 PM PDT 24 |
Aug 14 05:57:31 PM PDT 24 |
4916618120 ps |
| T843 |
/workspace/coverage/default/1.rom_keymgr_functest.1277943753 |
|
|
Aug 14 05:57:00 PM PDT 24 |
Aug 14 06:11:35 PM PDT 24 |
5609098200 ps |
| T844 |
/workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_fast_rma.4727861 |
|
|
Aug 14 06:07:26 PM PDT 24 |
Aug 14 06:16:54 PM PDT 24 |
3844572224 ps |
| T845 |
/workspace/coverage/default/6.chip_sw_csrng_edn_concurrency.1210065176 |
|
|
Aug 14 06:10:44 PM PDT 24 |
Aug 14 07:49:33 PM PDT 24 |
31069848000 ps |
| T846 |
/workspace/coverage/default/1.chip_sw_alert_handler_lpg_clkoff.3697136905 |
|
|
Aug 14 05:52:47 PM PDT 24 |
Aug 14 06:15:28 PM PDT 24 |
6205200888 ps |
| T847 |
/workspace/coverage/default/0.chip_sw_hmac_enc_idle.198097912 |
|
|
Aug 14 05:48:52 PM PDT 24 |
Aug 14 05:53:21 PM PDT 24 |
3373311680 ps |
| T227 |
/workspace/coverage/default/1.chip_sw_csrng_fuse_en_sw_app_read_test.2070484428 |
|
|
Aug 14 05:53:05 PM PDT 24 |
Aug 14 05:59:51 PM PDT 24 |
3298885276 ps |
| T848 |
/workspace/coverage/default/2.chip_sw_clkmgr_off_kmac_trans.246978225 |
|
|
Aug 14 06:04:06 PM PDT 24 |
Aug 14 06:11:31 PM PDT 24 |
5065944658 ps |
| T312 |
/workspace/coverage/default/0.rom_e2e_jtag_debug_rma.1413043153 |
|
|
Aug 14 05:50:48 PM PDT 24 |
Aug 14 06:24:11 PM PDT 24 |
11703947572 ps |
| T509 |
/workspace/coverage/default/58.chip_sw_alert_handler_lpg_sleep_mode_alerts.568143593 |
|
|
Aug 14 06:14:43 PM PDT 24 |
Aug 14 06:20:23 PM PDT 24 |
2796828728 ps |
| T849 |
/workspace/coverage/default/2.chip_sw_sensor_ctrl_status.4229737611 |
|
|
Aug 14 06:04:08 PM PDT 24 |
Aug 14 06:07:47 PM PDT 24 |
2541033171 ps |