Unified Coverage Report

Total Coverage Summary

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
85.60	88.40	77.09	90.05		89.40	83.77	84.87

Total test records in report: 1034

T411	/workspace/coverage/default/2.chip_sw_pwrmgr_normal_sleep_all_wake_ups.2030489093	Aug 14 06:05:58 PM PDT 24	Aug 14 06:14:07 PM PDT 24	7269639800 ps
T514	/workspace/coverage/default/55.chip_sw_all_escalation_resets.670902966	Aug 14 06:15:36 PM PDT 24	Aug 14 06:24:46 PM PDT 24	5411490960 ps
T404	/workspace/coverage/default/0.chip_sw_edn_boot_mode.3978957145	Aug 14 05:51:11 PM PDT 24	Aug 14 06:01:37 PM PDT 24	3490471948 ps
T208	/workspace/coverage/default/41.chip_sw_all_escalation_resets.296563995	Aug 14 06:14:57 PM PDT 24	Aug 14 06:23:54 PM PDT 24	5363741440 ps
T1020	/workspace/coverage/default/0.chip_sw_edn_sw_mode.1827967769	Aug 14 05:52:09 PM PDT 24	Aug 14 06:11:39 PM PDT 24	5649476800 ps
T1021	/workspace/coverage/default/0.chip_sw_sysrst_ctrl_reset.829495278	Aug 14 05:46:32 PM PDT 24	Aug 14 06:10:41 PM PDT 24	24575410384 ps
T109	/workspace/coverage/default/36.chip_sw_all_escalation_resets.4088093558	Aug 14 06:14:12 PM PDT 24	Aug 14 06:24:34 PM PDT 24	6300653320 ps
T1022	/workspace/coverage/default/1.chip_sw_sram_ctrl_scrambled_access_jitter_en.3409374917	Aug 14 05:57:20 PM PDT 24	Aug 14 06:06:22 PM PDT 24	3950651311 ps
T1023	/workspace/coverage/default/1.chip_sw_ast_clk_outputs.2667036754	Aug 14 05:54:22 PM PDT 24	Aug 14 06:13:37 PM PDT 24	8282453208 ps
T1024	/workspace/coverage/default/1.chip_sw_alert_handler_ping_ok.2995717393	Aug 14 05:51:06 PM PDT 24	Aug 14 06:14:41 PM PDT 24	7429681688 ps
T1025	/workspace/coverage/default/2.chip_sw_uart_tx_rx_idx1.2716293055	Aug 14 05:58:49 PM PDT 24	Aug 14 06:11:31 PM PDT 24	4196753988 ps
T539	/workspace/coverage/default/37.chip_sw_all_escalation_resets.3215335215	Aug 14 06:17:14 PM PDT 24	Aug 14 06:26:46 PM PDT 24	4415171960 ps
T1026	/workspace/coverage/default/1.chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq.1336412859	Aug 14 05:53:33 PM PDT 24	Aug 14 06:56:41 PM PDT 24	24989080441 ps
T1027	/workspace/coverage/default/70.chip_sw_all_escalation_resets.2044648279	Aug 14 06:16:03 PM PDT 24	Aug 14 06:24:00 PM PDT 24	4768753196 ps
T77	/workspace/coverage/default/0.chip_sw_alert_test.646391053	Aug 14 05:51:58 PM PDT 24	Aug 14 05:57:07 PM PDT 24	3105702584 ps
T1028	/workspace/coverage/default/0.chip_sw_sram_ctrl_smoketest.4085785199	Aug 14 05:50:22 PM PDT 24	Aug 14 05:55:21 PM PDT 24	3327183340 ps
T1029	/workspace/coverage/default/2.rom_e2e_asm_init_rma.1392902459	Aug 14 06:10:34 PM PDT 24	Aug 14 07:26:22 PM PDT 24	15701049920 ps
T1030	/workspace/coverage/default/1.chip_sw_kmac_entropy.2524056160	Aug 14 05:50:30 PM PDT 24	Aug 14 05:55:49 PM PDT 24	3310328520 ps
T489	/workspace/coverage/default/79.chip_sw_all_escalation_resets.4132861100	Aug 14 06:15:40 PM PDT 24	Aug 14 06:24:49 PM PDT 24	5850405876 ps
T1031	/workspace/coverage/default/2.chip_sw_pwrmgr_sleep_wake_5_bug.4031628049	Aug 14 06:04:53 PM PDT 24	Aug 14 06:14:46 PM PDT 24	7297665584 ps
T252	/workspace/coverage/default/0.chip_sw_spi_device_pass_through.2347825709	Aug 14 05:48:44 PM PDT 24	Aug 14 06:02:57 PM PDT 24	8420484242 ps
T1032	/workspace/coverage/default/3.chip_sw_aon_timer_sleep_wdog_sleep_pause.2578331079	Aug 14 06:09:04 PM PDT 24	Aug 14 06:17:36 PM PDT 24	6973883780 ps
T1033	/workspace/coverage/default/2.chip_sw_keymgr_key_derivation_prod.388474712	Aug 14 06:03:47 PM PDT 24	Aug 14 06:29:13 PM PDT 24	8163341352 ps
T1034	/workspace/coverage/default/2.chip_sw_keymgr_key_derivation.2145332027	Aug 14 06:03:49 PM PDT 24	Aug 14 06:38:54 PM PDT 24	9597893000 ps
T49	/workspace/coverage/pad_ctrl_test_mode/5.chip_padctrl_attributes.357255758	Aug 14 05:39:03 PM PDT 24	Aug 14 05:44:00 PM PDT 24	5377638374 ps
T50	/workspace/coverage/pad_ctrl_test_mode/4.chip_padctrl_attributes.1494586566	Aug 14 05:39:03 PM PDT 24	Aug 14 05:44:10 PM PDT 24	4974650693 ps
T51	/workspace/coverage/pad_ctrl_test_mode/7.chip_padctrl_attributes.2759294692	Aug 14 05:39:03 PM PDT 24	Aug 14 05:43:25 PM PDT 24	5323029040 ps
T246	/workspace/coverage/pad_ctrl_test_mode/1.chip_padctrl_attributes.784049982	Aug 14 05:39:01 PM PDT 24	Aug 14 05:42:29 PM PDT 24	5571636176 ps
T165	/workspace/coverage/pad_ctrl_test_mode/9.chip_padctrl_attributes.41387924	Aug 14 05:39:05 PM PDT 24	Aug 14 05:43:51 PM PDT 24	5361615294 ps
T247	/workspace/coverage/pad_ctrl_test_mode/0.chip_padctrl_attributes.670755234	Aug 14 05:39:05 PM PDT 24	Aug 14 05:42:21 PM PDT 24	4669197960 ps
T248	/workspace/coverage/pad_ctrl_test_mode/8.chip_padctrl_attributes.3526503971	Aug 14 05:39:03 PM PDT 24	Aug 14 05:44:26 PM PDT 24	4823373940 ps
T249	/workspace/coverage/pad_ctrl_test_mode/6.chip_padctrl_attributes.1131544435	Aug 14 05:39:01 PM PDT 24	Aug 14 05:42:37 PM PDT 24	3673742772 ps
T250	/workspace/coverage/pad_ctrl_test_mode/3.chip_padctrl_attributes.507312334	Aug 14 05:39:01 PM PDT 24	Aug 14 05:42:55 PM PDT 24	4038861100 ps
T251	/workspace/coverage/pad_ctrl_test_mode/2.chip_padctrl_attributes.1706073002	Aug 14 05:39:08 PM PDT 24	Aug 14 05:43:54 PM PDT 24	4525177000 ps

Test location	/workspace/coverage/default/35.chip_sw_all_escalation_resets.1988017989
Short name	T1
Test name
Test status
Simulation time	5323805590 ps
CPU time	566.77 seconds
Started	Aug 14 06:17:10 PM PDT 24
Finished	Aug 14 06:26:37 PM PDT 24
Peak memory	650800 kb
Host	smart-73a835d6-0bec-475b-8efd-9a8982f74d88
User	root
Command	/workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 1988017989 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.chip_sw_all_escalation_resets.1988017989
Directory	/workspace/35.chip_sw_all_escalation_resets/latest

Test location	/workspace/coverage/default/1.chip_sw_alert_test.2683603476
Short name	T75
Test name
Test status
Simulation time	3134416724 ps
CPU time	291.48 seconds
Started	Aug 14 05:56:04 PM PDT 24
Finished	Aug 14 06:00:55 PM PDT 24
Peak memory	610360 kb
Host	smart-ca6c32c9-c168-4681-8220-0f3cca16c9f5
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=alert_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2683603476 -assert nopostproc +UVM_TESTNAME=chip_ba se_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 1.chip_sw_alert_test.2683603476
Directory	/workspace/1.chip_sw_alert_test/latest

Test location	/workspace/coverage/pad_ctrl_test_mode/5.chip_padctrl_attributes.357255758
Short name	T49
Test name
Test status
Simulation time	5377638374 ps
CPU time	296.77 seconds
Started	Aug 14 05:39:03 PM PDT 24
Finished	Aug 14 05:44:00 PM PDT 24
Peak memory	655604 kb
Host	smart-7c16fbee-fed1-415e-ae85-538394a04691
User	root
Command	/workspace/pad_ctrl_test_mode/simv +use_otp_image=OtpTypeLcStProd +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=357255758 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TES T_SEQ=chip_padctrl_attributes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/pad_ctrl_test_mode.vdb -cm_log /dev/n ull -cm_name 5.chip_padctrl_attributes.357255758
Directory	/workspace/5.chip_padctrl_attributes/latest

Test location	/workspace/coverage/default/0.chip_plic_all_irqs_10.909069242
Short name	T155
Test name
Test status
Simulation time	3946627180 ps
CPU time	698.44 seconds
Started	Aug 14 05:49:37 PM PDT 24
Finished	Aug 14 06:01:16 PM PDT 24
Peak memory	610576 kb
Host	smart-483e8d4c-151a-44f4-a804-f42ad86a1af9
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=plic_all_irqs_test_10:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=909069242 -assert nopostproc +UVM_TESTNA ME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 0.chip_plic_all_irqs_10.909069242
Directory	/workspace/0.chip_plic_all_irqs_10/latest

Test location	/workspace/coverage/default/1.chip_sw_sleep_pin_mio_dio_val.1502685443
Short name	T28
Test name
Test status
Simulation time	3607051188 ps
CPU time	334.56 seconds
Started	Aug 14 05:50:44 PM PDT 24
Finished	Aug 14 05:56:19 PM PDT 24
Peak memory	611396 kb
Host	smart-84fa4ae9-e1f8-4e8a-a194-ca09002a0cc6
User	root
Command	/workspace/default/simv +use_otp_image=OtpTypeLcStProd +sw_build_device=sim_dv +sw_images=sleep_pin_mio_dio_val_test:1:new_rules,test_rom:0 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1502 685443 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sleep_pin_mio_dio_val_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_sleep_pin_mio_dio_val.1502685443
Directory	/workspace/1.chip_sw_sleep_pin_mio_dio_val/latest

Test location	/workspace/coverage/default/1.chip_sw_keymgr_sideload_kmac.255495353
Short name	T135
Test name
Test status
Simulation time	8447787268 ps
CPU time	1454.28 seconds
Started	Aug 14 05:55:36 PM PDT 24
Finished	Aug 14 06:19:51 PM PDT 24
Peak memory	611640 kb
Host	smart-2d33d50f-fb33-481f-b2dc-ff5da682c1aa
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=20_000_000 +sw_build_device=sim_dv +sw_images=keymgr_sideload_kmac_test:1:new_rules,test_rom:0 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25549 5353 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_keymgr_sideload_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_keymgr_sideload_kmac.255495353
Directory	/workspace/1.chip_sw_keymgr_sideload_kmac/latest

Test location	/workspace/coverage/default/0.rom_e2e_keymgr_init_rom_ext_no_meas.211253893
Short name	T67
Test name
Test status
Simulation time	15958695510 ps
CPU time	3573.63 seconds
Started	Aug 14 05:59:45 PM PDT 24
Finished	Aug 14 06:59:19 PM PDT 24
Peak memory	610716 kb
Host	smart-7dd1963d-93ce-4566-8a0e-defc92e3a79d
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=40_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=rom_e2e_keymgr_init_otp_no_meas :1:new_rules,otp_img_keymgr_otp_no_meas:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=211253893 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_keymgr_init_rom_ext_ no_meas.211253893
Directory	/workspace/0.rom_e2e_keymgr_init_rom_ext_no_meas/latest

Test location	/workspace/coverage/default/1.chip_sw_pwrmgr_normal_sleep_all_wake_ups.2447468699
Short name	T37
Test name
Test status
Simulation time	7839092200 ps
CPU time	385.34 seconds
Started	Aug 14 05:54:54 PM PDT 24
Finished	Aug 14 06:01:20 PM PDT 24
Peak memory	611360 kb
Host	smart-e50f1d64-0472-4224-8419-30f6e7145cad
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_normal_sleep_all_wake_ups:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2447468699 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_pwrmgr_deep_sleep_all_wake_ups_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_pwrmgr_normal_sleep_all_wake_ups.2447468699
Directory	/workspace/1.chip_sw_pwrmgr_normal_sleep_all_wake_ups/latest

Test location	/workspace/coverage/default/0.chip_plic_all_irqs_0.978037554
Short name	T233
Test name
Test status
Simulation time	6162038672 ps
CPU time	1310.59 seconds
Started	Aug 14 05:49:36 PM PDT 24
Finished	Aug 14 06:11:28 PM PDT 24
Peak memory	610680 kb
Host	smart-d5986862-3b66-495d-824c-22f5b26ac2c7
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=plic_all_irqs_test_0:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=978037554 -assert nopostproc +UVM_TESTNAM E=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 0.chip_plic_all_irqs_0.978037554
Directory	/workspace/0.chip_plic_all_irqs_0/latest

Test location	/workspace/coverage/default/2.chip_sw_lc_walkthrough_prod.3070377154
Short name	T210
Test name
Test status
Simulation time	50158302457 ps
CPU time	5697.07 seconds
Started	Aug 14 05:59:20 PM PDT 24
Finished	Aug 14 07:34:19 PM PDT 24
Peak memory	621400 kb
Host	smart-060cdf9f-2f69-41ca-a293-07b89dc65ff9
User	root
Command	/workspace/default/simv +flash_program_latency=5 +use_otp_image=OtpTypeLcStRaw +dest_dec_state=DecLcStProd +sw_test_timeout_ns=200_000_000 +sw_build_d evice=sim_dv +sw_images=lc_walkthrough_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3070377154 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ= chip_sw_lc_walkthrough_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chi p_sw_lc_walkthrough_prod.3070377154
Directory	/workspace/2.chip_sw_lc_walkthrough_prod/latest

Test location	/workspace/coverage/default/0.chip_sw_power_virus.1208068063
Short name	T31
Test name
Test status
Simulation time	5704134356 ps
CPU time	1480.51 seconds
Started	Aug 14 05:58:07 PM PDT 24
Finished	Aug 14 06:22:47 PM PDT 24
Peak memory	625468 kb
Host	smart-28d6078b-c779-4990-b3df-8cf461f8fa96
User	root
Command	/workspace/default/simv +rng_srate_value_min=15 +rng_srate_value_max=20 +sw_test_timeout_ns=400_000_000 +use_otp_image=OtpTypeCustom +accelerate_cold_ power_up_time=3 +accelerate_regulators_power_up_time=2 +sw_build_device=sim_dv +sw_images=power_virus_systemtest:1:new_rules,power_virus_systemtes t_otp_img_rma:4,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d v/tools/sim.tcl +ntb_random_seed=1208068063 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_power_virus_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_power_virus.1208068063
Directory	/workspace/0.chip_sw_power_virus/latest

Test location	/workspace/coverage/default/1.chip_sw_rv_core_ibex_address_translation.577503505
Short name	T219
Test name
Test status
Simulation time	3750812430 ps
CPU time	343.17 seconds
Started	Aug 14 05:57:25 PM PDT 24
Finished	Aug 14 06:03:08 PM PDT 24
Peak memory	609196 kb
Host	smart-ef48c005-d36d-41fe-a9c6-dca171d2fdb0
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=7_000_000 +sw_build_device=sim_dv +sw_images=rv_core_ibex_address_translation_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random _seed=577503505 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_rv_core_ibex_address_translation.577503505
Directory	/workspace/1.chip_sw_rv_core_ibex_address_translation/latest

Test location	/workspace/coverage/default/2.chip_plic_all_irqs_20.259445654
Short name	T111
Test name
Test status
Simulation time	4464996568 ps
CPU time	757.36 seconds
Started	Aug 14 06:03:58 PM PDT 24
Finished	Aug 14 06:16:35 PM PDT 24
Peak memory	610724 kb
Host	smart-efd0f88c-133e-4832-924e-ab70778d34c5
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=plic_all_irqs_test_20:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=259445654 -assert nopostproc +UVM_TESTNA ME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 2.chip_plic_all_irqs_20.259445654
Directory	/workspace/2.chip_plic_all_irqs_20/latest

Test location	/workspace/coverage/default/2.chip_sw_sleep_pin_retention.2271130879
Short name	T45
Test name
Test status
Simulation time	3674794200 ps
CPU time	340.15 seconds
Started	Aug 14 05:58:33 PM PDT 24
Finished	Aug 14 06:04:13 PM PDT 24
Peak memory	609960 kb
Host	smart-a16e14f8-9154-4d92-9ce5-0b9bf83bb39f
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=sleep_pin_retention_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2271130879 -assert nopostproc +UVM_TE STNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sleep_pin_retention_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def ault.vdb -cm_log /dev/null -cm_name 2.chip_sw_sleep_pin_retention.2271130879
Directory	/workspace/2.chip_sw_sleep_pin_retention/latest

Test location	/workspace/coverage/default/61.chip_sw_alert_handler_lpg_sleep_mode_alerts.508484694
Short name	T18
Test name
Test status
Simulation time	3349160472 ps
CPU time	542.51 seconds
Started	Aug 14 06:15:39 PM PDT 24
Finished	Aug 14 06:24:42 PM PDT 24
Peak memory	649564 kb
Host	smart-c34926cf-fff7-436a-a0ce-17c117ed402b
User	root
Command	/workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrlstate_regs +avoid_ferr_ips_append=otp_ctrlu_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=508484694 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all _escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 61.chip_s w_alert_handler_lpg_sleep_mode_alerts.508484694
Directory	/workspace/61.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location	/workspace/coverage/default/40.chip_sw_all_escalation_resets.483541534
Short name	T93
Test name
Test status
Simulation time	6097957240 ps
CPU time	578.5 seconds
Started	Aug 14 06:13:45 PM PDT 24
Finished	Aug 14 06:23:24 PM PDT 24
Peak memory	651136 kb
Host	smart-0830189e-1133-4a81-a86a-cd4d3aa05538
User	root
Command	/workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 483541534 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.chip_sw_all_escalation_resets.483541534
Directory	/workspace/40.chip_sw_all_escalation_resets/latest

Test location	/workspace/coverage/default/2.chip_sw_sleep_pin_wake.2715153387
Short name	T84
Test name
Test status
Simulation time	2510013756 ps
CPU time	247.64 seconds
Started	Aug 14 05:56:34 PM PDT 24
Finished	Aug 14 06:00:41 PM PDT 24
Peak memory	610404 kb
Host	smart-29b66f8c-97a4-4be1-b584-f9ff70d47363
User	root
Command	/workspace/default/simv +use_otp_image=OtpTypeLcStProd +sw_build_device=sim_dv +sw_images=sleep_pin_wake_test:1:new_rules,test_rom:0 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2715153387 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sleep_pin_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_sleep_pin_wake.2715153387
Directory	/workspace/2.chip_sw_sleep_pin_wake/latest

Test location	/workspace/coverage/default/0.chip_sw_sleep_pin_wake.1065183361
Short name	T82
Test name
Test status
Simulation time	5877351900 ps
CPU time	554.9 seconds
Started	Aug 14 05:46:57 PM PDT 24
Finished	Aug 14 05:56:13 PM PDT 24
Peak memory	610884 kb
Host	smart-685a47d7-072b-417a-86f1-1a5a0e093afe
User	root
Command	/workspace/default/simv +use_otp_image=OtpTypeLcStProd +sw_build_device=sim_dv +sw_images=sleep_pin_wake_test:1:new_rules,test_rom:0 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1065183361 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sleep_pin_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_sleep_pin_wake.1065183361
Directory	/workspace/0.chip_sw_sleep_pin_wake/latest

Test location	/workspace/coverage/default/1.chip_sw_sleep_pin_wake.1949738528
Short name	T83
Test name
Test status
Simulation time	3377054108 ps
CPU time	251.72 seconds
Started	Aug 14 05:52:52 PM PDT 24
Finished	Aug 14 05:57:04 PM PDT 24
Peak memory	610412 kb
Host	smart-d8fc8aeb-b26b-463a-9d47-e86cd701d56c
User	root
Command	/workspace/default/simv +use_otp_image=OtpTypeLcStProd +sw_build_device=sim_dv +sw_images=sleep_pin_wake_test:1:new_rules,test_rom:0 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1949738528 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sleep_pin_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_sleep_pin_wake.1949738528
Directory	/workspace/1.chip_sw_sleep_pin_wake/latest

Test location	/workspace/coverage/default/1.chip_jtag_csr_rw.1581544171
Short name	T17
Test name
Test status
Simulation time	11910022560 ps
CPU time	1318.52 seconds
Started	Aug 14 05:42:59 PM PDT 24
Finished	Aug 14 06:04:58 PM PDT 24
Peak memory	608556 kb
Host	smart-cedd9e49-31ea-4e51-a538-4c54c13b5fe1
User	root
Command	/workspace/default/simv +en_scb=0 +csr_rw +create_jtag_riscv_map=1 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1581544171 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_T EST_SEQ=chip_jtag_csr_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.c hip_jtag_csr_rw.1581544171
Directory	/workspace/1.chip_jtag_csr_rw/latest

Test location	/workspace/coverage/default/1.chip_tap_straps_testunlock0.267356975
Short name	T13
Test name
Test status
Simulation time	4066048302 ps
CPU time	357.84 seconds
Started	Aug 14 05:54:14 PM PDT 24
Finished	Aug 14 06:00:12 PM PDT 24
Peak memory	633524 kb
Host	smart-1c62dfc7-1360-4bd7-a757-7eece57279ea
User	root
Command	/workspace/default/simv +use_otp_image=OtpTypeLcStTestUnlocked0 +create_jtag_riscv_map=1 +sw_build_device=sim_dv +sw_images=example_test_from_rom:0:te st_in_rom:new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=267356975 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_tap_straps_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_tap_straps_testunlock0.267356975
Directory	/workspace/1.chip_tap_straps_testunlock0/latest

Test location	/workspace/coverage/default/2.chip_sw_edn_entropy_reqs.1054602890
Short name	T183
Test name
Test status
Simulation time	6744376100 ps
CPU time	1015.47 seconds
Started	Aug 14 06:05:07 PM PDT 24
Finished	Aug 14 06:22:03 PM PDT 24
Peak memory	611612 kb
Host	smart-aa493021-c962-4ab5-9d62-8095ff628bd2
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=15000000 +rng_srate_value_min=15 +rng_srate_value_max=30 +sw_build_device=sim_dv +sw_images=entropy_src_ed n_reqs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1054602890 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_edn_entropy_reqs.1054602890
Directory	/workspace/2.chip_sw_edn_entropy_reqs/latest

Test location	/workspace/coverage/default/0.chip_sw_rstmgr_cpu_info.4111204684
Short name	T280
Test name
Test status
Simulation time	7859966160 ps
CPU time	976.52 seconds
Started	Aug 14 05:49:24 PM PDT 24
Finished	Aug 14 06:05:41 PM PDT 24
Peak memory	611300 kb
Host	smart-4521caf9-f82d-49db-ac9f-db27404e7854
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=rstmgr_cpu_info_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4111204684 -assert nopostproc +UVM_TESTNA ME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 0.chip_sw_rstmgr_cpu_info.4111204684
Directory	/workspace/0.chip_sw_rstmgr_cpu_info/latest

Test location	/workspace/coverage/default/1.chip_rv_dm_ndm_reset_req.1759384397
Short name	T198
Test name
Test status
Simulation time	4215137608 ps
CPU time	303.29 seconds
Started	Aug 14 05:56:36 PM PDT 24
Finished	Aug 14 06:01:40 PM PDT 24
Peak memory	620372 kb
Host	smart-1125fa68-cd9e-4c60-94d6-11d2f6030703
User	root
Command	/workspace/default/simv +en_scb_tl_err_chk=0 +use_jtag_dmi=1 +sw_build_device=sim_dv +sw_images=rv_dm_ndm_reset_req_rma:1:new_rules,test_rom:0 +cdc_in strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1 759384397 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_rv_dm_ndm_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_rv_dm_ndm_reset_req.1759384397
Directory	/workspace/1.chip_rv_dm_ndm_reset_req/latest

Test location	/workspace/coverage/default/1.rom_e2e_shutdown_output.720807150
Short name	T377
Test name
Test status
Simulation time	23486224541 ps
CPU time	3295.57 seconds
Started	Aug 14 06:01:26 PM PDT 24
Finished	Aug 14 06:56:22 PM PDT 24
Peak memory	612200 kb
Host	smart-f7e15391-87d9-4835-ba2d-1e2718607e24
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=20000000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_unsigned:1:ot_f lash_binary,otp_img_shutdown_output_test_unlocked0:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=720807150 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip _sw_rom_e2e_shutdown_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_e2e_shutdown_output.720807150
Directory	/workspace/1.rom_e2e_shutdown_output/latest

Test location	/workspace/coverage/default/0.chip_jtag_csr_rw.1514711722
Short name	T100
Test name
Test status
Simulation time	10601485228 ps
CPU time	987.23 seconds
Started	Aug 14 05:39:49 PM PDT 24
Finished	Aug 14 05:56:16 PM PDT 24
Peak memory	608496 kb
Host	smart-81cf8c72-3116-498f-818c-535cbd4a19b5
User	root
Command	/workspace/default/simv +en_scb=0 +csr_rw +create_jtag_riscv_map=1 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1514711722 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_T EST_SEQ=chip_jtag_csr_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.c hip_jtag_csr_rw.1514711722
Directory	/workspace/0.chip_jtag_csr_rw/latest

Test location	/workspace/coverage/default/2.chip_sw_sleep_pin_mio_dio_val.1137840202
Short name	T30
Test name
Test status
Simulation time	2587758014 ps
CPU time	238.44 seconds
Started	Aug 14 05:55:55 PM PDT 24
Finished	Aug 14 05:59:54 PM PDT 24
Peak memory	610608 kb
Host	smart-0264ea79-705b-46de-b2dd-a58dd221e17a
User	root
Command	/workspace/default/simv +use_otp_image=OtpTypeLcStProd +sw_build_device=sim_dv +sw_images=sleep_pin_mio_dio_val_test:1:new_rules,test_rom:0 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1137 840202 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sleep_pin_mio_dio_val_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_sleep_pin_mio_dio_val.1137840202
Directory	/workspace/2.chip_sw_sleep_pin_mio_dio_val/latest

Test location	/workspace/coverage/default/0.chip_sw_clkmgr_off_peri.3692746523
Short name	T4
Test name
Test status
Simulation time	12148713432 ps
CPU time	1338.9 seconds
Started	Aug 14 05:51:20 PM PDT 24
Finished	Aug 14 06:13:40 PM PDT 24
Peak memory	611212 kb
Host	smart-470600b2-adfa-49ff-80df-47c3ebe23734
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=30_000_000 +sw_build_device=sim_dv +sw_images=clkmgr_off_peri_test:1:new_rules,test_rom:0 +cdc_instrumenta tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3692746523 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/ coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_clkmgr_off_peri.3692746523
Directory	/workspace/0.chip_sw_clkmgr_off_peri/latest

Test location	/workspace/coverage/default/2.chip_sw_gpio.3555775949
Short name	T36
Test name
Test status
Simulation time	3799328232 ps
CPU time	480.11 seconds
Started	Aug 14 05:58:16 PM PDT 24
Finished	Aug 14 06:06:16 PM PDT 24
Peak memory	611100 kb
Host	smart-53b3b536-d314-4941-9be0-f7d0f50c29e7
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=gpio_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3555775949 -assert nopostproc +UVM_TESTNAME=chip_bas e_test +UVM_TEST_SEQ=chip_sw_gpio_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm _name 2.chip_sw_gpio.3555775949
Directory	/workspace/2.chip_sw_gpio/latest

Test location	/workspace/coverage/default/0.chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup.1069862976
Short name	T145
Test name
Test status
Simulation time	5012081400 ps
CPU time	534.1 seconds
Started	Aug 14 05:48:40 PM PDT 24
Finished	Aug 14 05:57:35 PM PDT 24
Peak memory	610688 kb
Host	smart-50d380c7-d4a6-4482-9aa6-3781623a0dbc
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=8_000_000 +sw_build_device=sim_dv +sw_images=sensor_ctrl_wakeup_test:1:new_rules,test_rom:0 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10698629 76 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac e/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup.1069862976
Directory	/workspace/0.chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup/latest

Test location	/workspace/coverage/default/1.chip_sw_alert_handler_lpg_sleep_mode_pings.823215803
Short name	T22
Test name
Test status
Simulation time	13323265352 ps
CPU time	1680.79 seconds
Started	Aug 14 05:51:10 PM PDT 24
Finished	Aug 14 06:19:12 PM PDT 24
Peak memory	611404 kb
Host	smart-382a29fd-6e18-49f7-a8c5-37bcb6fcc9e2
User	root
Command	/workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=alert_handler _lpg_sleep_mode_pings_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=823215803 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_alert_hand ler_shorten_ping_wait_cycle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_alert_handler_lpg_sleep_mode_pings.823215803
Directory	/workspace/1.chip_sw_alert_handler_lpg_sleep_mode_pings/latest

Test location	/workspace/coverage/default/9.chip_sw_lc_ctrl_transition.460550312
Short name	T70
Test name
Test status
Simulation time	4902149177 ps
CPU time	507.32 seconds
Started	Aug 14 06:09:14 PM PDT 24
Finished	Aug 14 06:17:42 PM PDT 24
Peak memory	621820 kb
Host	smart-d56e7fb2-8384-4b2c-83d9-db0b95f29724
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=lc_ctrl_transition_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=460550312 -assert nopostproc +UVM_TEST NAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_transition_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul t.vdb -cm_log /dev/null -cm_name 9.chip_sw_lc_ctrl_transition.460550312
Directory	/workspace/9.chip_sw_lc_ctrl_transition/latest

Test location	/workspace/coverage/default/4.chip_sw_data_integrity_escalation.3354749078
Short name	T164
Test name
Test status
Simulation time	5898328254 ps
CPU time	643.3 seconds
Started	Aug 14 06:09:40 PM PDT 24
Finished	Aug 14 06:20:24 PM PDT 24
Peak memory	611988 kb
Host	smart-0cfcb189-a52d-4877-8a3d-e7a1a7460d38
User	root
Command	/workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=data_integrity_escalation_reset_test:1:new_rules,test_ro m:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=3354749078 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_data_integrity_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.chip_sw_data_integrity_escalation.3354749078
Directory	/workspace/4.chip_sw_data_integrity_escalation/latest

Test location	/workspace/coverage/default/0.chip_sw_otp_ctrl_escalation.1995875712
Short name	T206
Test name
Test status
Simulation time	5112575590 ps
CPU time	591.82 seconds
Started	Aug 14 05:52:41 PM PDT 24
Finished	Aug 14 06:02:34 PM PDT 24
Peak memory	611992 kb
Host	smart-0ac3f9ae-f01e-4d3a-86b8-05ff35213816
User	root
Command	/workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 1995875712 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_otp_ctrl_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_otp_ctrl_escalation.1995875712
Directory	/workspace/0.chip_sw_otp_ctrl_escalation/latest

Test location	/workspace/coverage/default/0.chip_sw_flash_rma_unlocked.3596693592
Short name	T222
Test name
Test status
Simulation time	45107287162 ps
CPU time	4974.08 seconds
Started	Aug 14 05:48:38 PM PDT 24
Finished	Aug 14 07:11:34 PM PDT 24
Peak memory	625256 kb
Host	smart-c1d0173f-1b8d-4cb0-868c-582dfb1b560d
User	root
Command	/workspace/default/simv +flash_program_latency=5 +sw_test_timeout_ns=150_000_000 +sw_build_device=sim_dv +sw_images=flash_rma_unlocked_test:0:test_in_ rom:new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t cl +ntb_random_seed=3596693592 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_flash_rma_unlocked_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_flash_rma_unlocked.3596693592
Directory	/workspace/0.chip_sw_flash_rma_unlocked/latest

Test location	/workspace/coverage/default/1.chip_sw_sysrst_ctrl_reset.4190862959
Short name	T42
Test name
Test status
Simulation time	21862063230 ps
CPU time	1591.09 seconds
Started	Aug 14 05:50:40 PM PDT 24
Finished	Aug 14 06:17:11 PM PDT 24
Peak memory	613668 kb
Host	smart-81f3ae4b-647f-4595-8a94-2344e6c36acd
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=36_000_000 +sw_build_device=sim_dv +sw_images=sysrst_ctrl_reset_test:1:new_rules,test_rom:0 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41908629 59 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sysrst_ctrl_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_sysrst_ctrl_reset.4190862959
Directory	/workspace/1.chip_sw_sysrst_ctrl_reset/latest

Test location	/workspace/coverage/default/11.chip_sw_alert_handler_lpg_sleep_mode_alerts.1857172836
Short name	T264
Test name
Test status
Simulation time	4016880786 ps
CPU time	347.95 seconds
Started	Aug 14 06:10:15 PM PDT 24
Finished	Aug 14 06:16:03 PM PDT 24
Peak memory	649508 kb
Host	smart-d9699df1-62af-4dd3-9ee0-51a280e8f3a7
User	root
Command	/workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrlstate_regs +avoid_ferr_ips_append=otp_ctrlu_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1857172836 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.chip_ sw_alert_handler_lpg_sleep_mode_alerts.1857172836
Directory	/workspace/11.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location	/workspace/coverage/default/38.chip_sw_all_escalation_resets.3621665469
Short name	T386
Test name
Test status
Simulation time	4033113960 ps
CPU time	479.86 seconds
Started	Aug 14 06:16:03 PM PDT 24
Finished	Aug 14 06:24:04 PM PDT 24
Peak memory	650512 kb
Host	smart-35dab36c-3b8c-4e8a-bb5a-87965ea0e654
User	root
Command	/workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 3621665469 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.chip_sw_all_escalation_resets.3621665469
Directory	/workspace/38.chip_sw_all_escalation_resets/latest

Test location	/workspace/coverage/default/90.chip_sw_all_escalation_resets.2955420472
Short name	T104
Test name
Test status
Simulation time	4068592808 ps
CPU time	589.89 seconds
Started	Aug 14 06:16:25 PM PDT 24
Finished	Aug 14 06:26:15 PM PDT 24
Peak memory	650828 kb
Host	smart-beb50516-9d00-4126-bb1f-a38681e208cc
User	root
Command	/workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 2955420472 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 90.chip_sw_all_escalation_resets.2955420472
Directory	/workspace/90.chip_sw_all_escalation_resets/latest

Test location	/workspace/coverage/default/86.chip_sw_all_escalation_resets.3203048834
Short name	T380
Test name
Test status
Simulation time	4940655480 ps
CPU time	679.23 seconds
Started	Aug 14 06:17:11 PM PDT 24
Finished	Aug 14 06:28:31 PM PDT 24
Peak memory	651004 kb
Host	smart-58a7d51e-4ea9-43bc-a5cc-a30e7c55a43f
User	root
Command	/workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 3203048834 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 86.chip_sw_all_escalation_resets.3203048834
Directory	/workspace/86.chip_sw_all_escalation_resets/latest

Test location	/workspace/coverage/default/0.chip_sw_sleep_pin_mio_dio_val.2644060743
Short name	T29
Test name
Test status
Simulation time	3284899921 ps
CPU time	331.34 seconds
Started	Aug 14 05:48:49 PM PDT 24
Finished	Aug 14 05:54:21 PM PDT 24
Peak memory	611340 kb
Host	smart-685c8d83-0d57-4e74-a503-45e78b67b393
User	root
Command	/workspace/default/simv +use_otp_image=OtpTypeLcStProd +sw_build_device=sim_dv +sw_images=sleep_pin_mio_dio_val_test:1:new_rules,test_rom:0 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2644 060743 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sleep_pin_mio_dio_val_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_sleep_pin_mio_dio_val.2644060743
Directory	/workspace/0.chip_sw_sleep_pin_mio_dio_val/latest

Test location	/workspace/coverage/default/0.chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq.1457584032
Short name	T294
Test name
Test status
Simulation time	5091949376 ps
CPU time	581.91 seconds
Started	Aug 14 05:52:01 PM PDT 24
Finished	Aug 14 06:01:43 PM PDT 24
Peak memory	610432 kb
Host	smart-c36c2dfa-ac19-4663-abc5-01c050c61766
User	root
Command	/workspace/default/simv +mem_sel=main +sw_test_timeout_ns=12_000_000 +bypass_alert_ready_to_end_check=1 +en_jitter=1 +en_scb_tl_err_chk=0 +cal_sys_clk _70mhz=1 +sw_build_device=sim_dv +sw_images=sram_ctrl_scrambled_access_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1457584032 -assert nopostproc +UVM_TESTNA ME=chip_base_test +UVM_TEST_SEQ=chip_sw_sram_ctrl_scrambled_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/ default.vdb -cm_log /dev/null -cm_name 0.chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq.1457584032
Directory	/workspace/0.chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq/latest

Test location	/workspace/coverage/default/63.chip_sw_all_escalation_resets.4284335447
Short name	T92
Test name
Test status
Simulation time	5820297088 ps
CPU time	694.68 seconds
Started	Aug 14 06:13:46 PM PDT 24
Finished	Aug 14 06:25:20 PM PDT 24
Peak memory	650676 kb
Host	smart-6c71b616-8ce5-4785-8bec-ceaacd22e4bc
User	root
Command	/workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 4284335447 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 63.chip_sw_all_escalation_resets.4284335447
Directory	/workspace/63.chip_sw_all_escalation_resets/latest

Test location	/workspace/coverage/default/0.chip_sw_flash_ctrl_lc_rw_en.2593248528
Short name	T191
Test name
Test status
Simulation time	5077620669 ps
CPU time	408.69 seconds
Started	Aug 14 05:47:48 PM PDT 24
Finished	Aug 14 05:54:36 PM PDT 24
Peak memory	611580 kb
Host	smart-35499ae8-974f-4dc2-9cd4-f5f86b6b5585
User	root
Command	/workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=flash_ctrl_lc_rw_en_test:1:new_rules,test_rom:0 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25 93248528 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_flash_ctrl_lc_rw_en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_flash_ctrl_lc_rw_en.2593248528
Directory	/workspace/0.chip_sw_flash_ctrl_lc_rw_en/latest

Test location	/workspace/coverage/default/1.chip_sw_spi_device_pinmux_sleep_retention.3355381206
Short name	T80
Test name
Test status
Simulation time	4368108712 ps
CPU time	294.19 seconds
Started	Aug 14 05:56:08 PM PDT 24
Finished	Aug 14 06:01:03 PM PDT 24
Peak memory	620092 kb
Host	smart-5805b915-2d5c-4a99-a12c-1986df402e42
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=spi_device_sleep_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3355381206 -assert nopostproc +UVM_TESTN AME=chip_base_test +UVM_TEST_SEQ=chip_sw_spi_device_pinmux_sleep_retention_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/c overage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_spi_device_pinmux_sleep_retention.3355381206
Directory	/workspace/1.chip_sw_spi_device_pinmux_sleep_retention/latest

Test location	/workspace/coverage/default/67.chip_sw_all_escalation_resets.2452211226
Short name	T171
Test name
Test status
Simulation time	5881228960 ps
CPU time	517.87 seconds
Started	Aug 14 06:16:04 PM PDT 24
Finished	Aug 14 06:24:42 PM PDT 24
Peak memory	651036 kb
Host	smart-2c9840c6-9726-404f-a7a7-0ae997eaeaf2
User	root
Command	/workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 2452211226 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 67.chip_sw_all_escalation_resets.2452211226
Directory	/workspace/67.chip_sw_all_escalation_resets/latest

Test location	/workspace/coverage/default/65.chip_sw_all_escalation_resets.3859921177
Short name	T232
Test name
Test status
Simulation time	4893693050 ps
CPU time	684.22 seconds
Started	Aug 14 06:15:37 PM PDT 24
Finished	Aug 14 06:27:02 PM PDT 24
Peak memory	651132 kb
Host	smart-bdae93f4-a1d2-4d49-a345-a2517aab46a0
User	root
Command	/workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 3859921177 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 65.chip_sw_all_escalation_resets.3859921177
Directory	/workspace/65.chip_sw_all_escalation_resets/latest

Test location	/workspace/coverage/default/1.chip_sw_csrng_lc_hw_debug_en_test.3129832346
Short name	T188
Test name
Test status
Simulation time	6527319984 ps
CPU time	863.3 seconds
Started	Aug 14 05:52:09 PM PDT 24
Finished	Aug 14 06:06:34 PM PDT 24
Peak memory	611556 kb
Host	smart-e0806227-b384-4095-b159-cab5e29c1494
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=15_000_000 +rng_srate_value_min=15 +use_otp_image=OtpTypeLcStTestUnlocked0 +sw_build_device=sim_dv +sw_ima ges=csrng_lc_hw_debug_en_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3129832346 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_csrng_ lc_hw_debug_en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_csr ng_lc_hw_debug_en_test.3129832346
Directory	/workspace/1.chip_sw_csrng_lc_hw_debug_en_test/latest

Test location	/workspace/coverage/default/59.chip_sw_all_escalation_resets.707697946
Short name	T162
Test name
Test status
Simulation time	5946345474 ps
CPU time	462.94 seconds
Started	Aug 14 06:15:55 PM PDT 24
Finished	Aug 14 06:23:38 PM PDT 24
Peak memory	650708 kb
Host	smart-f5c01d41-d9ee-42f5-9789-98e087478a2b
User	root
Command	/workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 707697946 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 59.chip_sw_all_escalation_resets.707697946
Directory	/workspace/59.chip_sw_all_escalation_resets/latest

Test location	/workspace/coverage/default/14.chip_sw_all_escalation_resets.3446444837
Short name	T488
Test name
Test status
Simulation time	5609016024 ps
CPU time	620.91 seconds
Started	Aug 14 06:11:38 PM PDT 24
Finished	Aug 14 06:22:00 PM PDT 24
Peak memory	650852 kb
Host	smart-9c40aafe-9883-4eca-9ca7-d1fef151f24e
User	root
Command	/workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 3446444837 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.chip_sw_all_escalation_resets.3446444837
Directory	/workspace/14.chip_sw_all_escalation_resets/latest

Test location	/workspace/coverage/default/75.chip_sw_all_escalation_resets.1626136336
Short name	T173
Test name
Test status
Simulation time	5580684500 ps
CPU time	580.44 seconds
Started	Aug 14 06:16:15 PM PDT 24
Finished	Aug 14 06:25:55 PM PDT 24
Peak memory	650556 kb
Host	smart-9a173a69-5379-47de-9ad4-214fe0e9d745
User	root
Command	/workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 1626136336 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 75.chip_sw_all_escalation_resets.1626136336
Directory	/workspace/75.chip_sw_all_escalation_resets/latest

Test location	/workspace/coverage/default/0.chip_sw_alert_handler_lpg_sleep_mode_alerts.697883980
Short name	T108
Test name
Test status
Simulation time	3890205648 ps
CPU time	390.89 seconds
Started	Aug 14 05:51:51 PM PDT 24
Finished	Aug 14 05:58:22 PM PDT 24
Peak memory	649792 kb
Host	smart-5224c22c-727b-4796-b83b-51b973f5e489
User	root
Command	/workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrlstate_regs +avoid_ferr_ips_append=otp_ctrlu_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=697883980 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all _escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw _alert_handler_lpg_sleep_mode_alerts.697883980
Directory	/workspace/0.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location	/workspace/coverage/default/0.chip_sw_all_escalation_resets.2603524313
Short name	T452
Test name
Test status
Simulation time	5426593120 ps
CPU time	769.31 seconds
Started	Aug 14 05:48:30 PM PDT 24
Finished	Aug 14 06:01:20 PM PDT 24
Peak memory	650832 kb
Host	smart-379ada28-e102-4330-b216-aff349fb84c0
User	root
Command	/workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 2603524313 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_all_escalation_resets.2603524313
Directory	/workspace/0.chip_sw_all_escalation_resets/latest

Test location	/workspace/coverage/default/1.chip_sw_alert_handler_lpg_sleep_mode_alerts.1981430239
Short name	T450
Test name
Test status
Simulation time	4321385400 ps
CPU time	374.97 seconds
Started	Aug 14 05:51:22 PM PDT 24
Finished	Aug 14 05:57:38 PM PDT 24
Peak memory	649856 kb
Host	smart-62c62d52-a550-4e10-840b-566567eb247c
User	root
Command	/workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrlstate_regs +avoid_ferr_ips_append=otp_ctrlu_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1981430239 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_s w_alert_handler_lpg_sleep_mode_alerts.1981430239
Directory	/workspace/1.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location	/workspace/coverage/default/1.chip_sw_all_escalation_resets.3341942489
Short name	T493
Test name
Test status
Simulation time	5837048112 ps
CPU time	732.17 seconds
Started	Aug 14 05:56:05 PM PDT 24
Finished	Aug 14 06:08:17 PM PDT 24
Peak memory	650784 kb
Host	smart-1bc64a2c-7754-453b-b1ae-7ff75201bcf3
User	root
Command	/workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 3341942489 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_all_escalation_resets.3341942489
Directory	/workspace/1.chip_sw_all_escalation_resets/latest

Test location	/workspace/coverage/default/10.chip_sw_all_escalation_resets.3376795541
Short name	T1007
Test name
Test status
Simulation time	4651255018 ps
CPU time	588.46 seconds
Started	Aug 14 06:09:40 PM PDT 24
Finished	Aug 14 06:19:29 PM PDT 24
Peak memory	650828 kb
Host	smart-12e81c10-49aa-4e0b-9032-179e6b8ffe37
User	root
Command	/workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 3376795541 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.chip_sw_all_escalation_resets.3376795541
Directory	/workspace/10.chip_sw_all_escalation_resets/latest

Test location	/workspace/coverage/default/11.chip_sw_all_escalation_resets.877600141
Short name	T470
Test name
Test status
Simulation time	5339509816 ps
CPU time	605.88 seconds
Started	Aug 14 06:10:50 PM PDT 24
Finished	Aug 14 06:20:57 PM PDT 24
Peak memory	650528 kb
Host	smart-5b3decbd-1d26-42de-80c3-a3cd0ba116ea
User	root
Command	/workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 877600141 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.chip_sw_all_escalation_resets.877600141
Directory	/workspace/11.chip_sw_all_escalation_resets/latest

Test location	/workspace/coverage/default/13.chip_sw_alert_handler_lpg_sleep_mode_alerts.1286637285
Short name	T818
Test name
Test status
Simulation time	3899701060 ps
CPU time	447.8 seconds
Started	Aug 14 06:10:35 PM PDT 24
Finished	Aug 14 06:18:03 PM PDT 24
Peak memory	649580 kb
Host	smart-b672cc87-772b-445c-bfe3-3ee728a86a74
User	root
Command	/workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrlstate_regs +avoid_ferr_ips_append=otp_ctrlu_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1286637285 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.chip_ sw_alert_handler_lpg_sleep_mode_alerts.1286637285
Directory	/workspace/13.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location	/workspace/coverage/default/14.chip_sw_alert_handler_lpg_sleep_mode_alerts.2032355277
Short name	T479
Test name
Test status
Simulation time	3881010828 ps
CPU time	440.93 seconds
Started	Aug 14 06:10:29 PM PDT 24
Finished	Aug 14 06:17:50 PM PDT 24
Peak memory	649524 kb
Host	smart-bb60863f-5cb1-4d1d-8ce5-7d10569efdfa
User	root
Command	/workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrlstate_regs +avoid_ferr_ips_append=otp_ctrlu_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2032355277 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.chip_ sw_alert_handler_lpg_sleep_mode_alerts.2032355277
Directory	/workspace/14.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location	/workspace/coverage/default/15.chip_sw_alert_handler_lpg_sleep_mode_alerts.1008606446
Short name	T533
Test name
Test status
Simulation time	3972561652 ps
CPU time	456.22 seconds
Started	Aug 14 06:10:19 PM PDT 24
Finished	Aug 14 06:17:56 PM PDT 24
Peak memory	649828 kb
Host	smart-07a795d5-db2a-4a7a-909d-c5e5f87012ce
User	root
Command	/workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrlstate_regs +avoid_ferr_ips_append=otp_ctrlu_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1008606446 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.chip_ sw_alert_handler_lpg_sleep_mode_alerts.1008606446
Directory	/workspace/15.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location	/workspace/coverage/default/16.chip_sw_alert_handler_lpg_sleep_mode_alerts.4199319053
Short name	T459
Test name
Test status
Simulation time	3977690200 ps
CPU time	544.31 seconds
Started	Aug 14 06:10:12 PM PDT 24
Finished	Aug 14 06:19:17 PM PDT 24
Peak memory	649448 kb
Host	smart-977d5b8a-51bc-4557-ab42-48a31192bf47
User	root
Command	/workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrlstate_regs +avoid_ferr_ips_append=otp_ctrlu_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4199319053 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.chip_ sw_alert_handler_lpg_sleep_mode_alerts.4199319053
Directory	/workspace/16.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location	/workspace/coverage/default/16.chip_sw_all_escalation_resets.2399394796
Short name	T517
Test name
Test status
Simulation time	5502643368 ps
CPU time	785.75 seconds
Started	Aug 14 06:12:09 PM PDT 24
Finished	Aug 14 06:25:15 PM PDT 24
Peak memory	650784 kb
Host	smart-b58c2fb7-2eed-4787-91bd-2513a5b326fb
User	root
Command	/workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 2399394796 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.chip_sw_all_escalation_resets.2399394796
Directory	/workspace/16.chip_sw_all_escalation_resets/latest

Test location	/workspace/coverage/default/17.chip_sw_all_escalation_resets.3045065663
Short name	T490
Test name
Test status
Simulation time	4272594214 ps
CPU time	496.34 seconds
Started	Aug 14 06:11:31 PM PDT 24
Finished	Aug 14 06:19:47 PM PDT 24
Peak memory	650524 kb
Host	smart-63c6892d-40f1-4cb3-91da-9634db73d744
User	root
Command	/workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 3045065663 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.chip_sw_all_escalation_resets.3045065663
Directory	/workspace/17.chip_sw_all_escalation_resets/latest

Test location	/workspace/coverage/default/18.chip_sw_all_escalation_resets.2779266364
Short name	T464
Test name
Test status
Simulation time	4332495188 ps
CPU time	569.04 seconds
Started	Aug 14 06:11:31 PM PDT 24
Finished	Aug 14 06:21:00 PM PDT 24
Peak memory	650556 kb
Host	smart-af510309-563e-4414-865b-04873305ee53
User	root
Command	/workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 2779266364 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.chip_sw_all_escalation_resets.2779266364
Directory	/workspace/18.chip_sw_all_escalation_resets/latest

Test location	/workspace/coverage/default/19.chip_sw_all_escalation_resets.95833127
Short name	T544
Test name
Test status
Simulation time	5231395582 ps
CPU time	532.78 seconds
Started	Aug 14 06:12:19 PM PDT 24
Finished	Aug 14 06:21:12 PM PDT 24
Peak memory	650684 kb
Host	smart-5a3f7257-405e-451c-b89b-855f4a74cb06
User	root
Command	/workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 95833127 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.chip_sw_all_escalation_resets.95833127
Directory	/workspace/19.chip_sw_all_escalation_resets/latest

Test location	/workspace/coverage/default/2.chip_sw_all_escalation_resets.3190121761
Short name	T537
Test name
Test status
Simulation time	6605672658 ps
CPU time	625.01 seconds
Started	Aug 14 05:55:16 PM PDT 24
Finished	Aug 14 06:05:42 PM PDT 24
Peak memory	648116 kb
Host	smart-219c0f57-c618-4304-82ce-98619875eaa0
User	root
Command	/workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 3190121761 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_all_escalation_resets.3190121761
Directory	/workspace/2.chip_sw_all_escalation_resets/latest

Test location	/workspace/coverage/default/20.chip_sw_all_escalation_resets.1335042735
Short name	T478
Test name
Test status
Simulation time	5579683538 ps
CPU time	507.65 seconds
Started	Aug 14 06:13:30 PM PDT 24
Finished	Aug 14 06:21:58 PM PDT 24
Peak memory	650756 kb
Host	smart-d720b04b-aada-4b09-a293-daf842dd447a
User	root
Command	/workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 1335042735 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.chip_sw_all_escalation_resets.1335042735
Directory	/workspace/20.chip_sw_all_escalation_resets/latest

Test location	/workspace/coverage/default/21.chip_sw_alert_handler_lpg_sleep_mode_alerts.4204804100
Short name	T330
Test name
Test status
Simulation time	4192794580 ps
CPU time	326.15 seconds
Started	Aug 14 06:12:52 PM PDT 24
Finished	Aug 14 06:18:18 PM PDT 24
Peak memory	649616 kb
Host	smart-2ffd415f-358f-4660-9206-8cf416df8506
User	root
Command	/workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrlstate_regs +avoid_ferr_ips_append=otp_ctrlu_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4204804100 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.chip_ sw_alert_handler_lpg_sleep_mode_alerts.4204804100
Directory	/workspace/21.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location	/workspace/coverage/default/21.chip_sw_all_escalation_resets.936051978
Short name	T499
Test name
Test status
Simulation time	5196939072 ps
CPU time	863.15 seconds
Started	Aug 14 06:12:32 PM PDT 24
Finished	Aug 14 06:26:56 PM PDT 24
Peak memory	651160 kb
Host	smart-d1a495b6-43dd-4d4a-8222-136e85095334
User	root
Command	/workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 936051978 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.chip_sw_all_escalation_resets.936051978
Directory	/workspace/21.chip_sw_all_escalation_resets/latest

Test location	/workspace/coverage/default/23.chip_sw_all_escalation_resets.2338664184
Short name	T350
Test name
Test status
Simulation time	5146162600 ps
CPU time	617.09 seconds
Started	Aug 14 06:11:01 PM PDT 24
Finished	Aug 14 06:21:18 PM PDT 24
Peak memory	650500 kb
Host	smart-661d35a6-0114-44b7-82f1-2b1e047de1c0
User	root
Command	/workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 2338664184 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.chip_sw_all_escalation_resets.2338664184
Directory	/workspace/23.chip_sw_all_escalation_resets/latest

Test location	/workspace/coverage/default/24.chip_sw_alert_handler_lpg_sleep_mode_alerts.3501770501
Short name	T513
Test name
Test status
Simulation time	3732541892 ps
CPU time	329.97 seconds
Started	Aug 14 06:11:29 PM PDT 24
Finished	Aug 14 06:16:59 PM PDT 24
Peak memory	649604 kb
Host	smart-7562669b-d080-47a1-98c8-103b486998b8
User	root
Command	/workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrlstate_regs +avoid_ferr_ips_append=otp_ctrlu_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3501770501 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.chip_ sw_alert_handler_lpg_sleep_mode_alerts.3501770501
Directory	/workspace/24.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location	/workspace/coverage/default/24.chip_sw_all_escalation_resets.59405308
Short name	T501
Test name
Test status
Simulation time	5787871522 ps
CPU time	644.09 seconds
Started	Aug 14 06:11:09 PM PDT 24
Finished	Aug 14 06:21:54 PM PDT 24
Peak memory	650648 kb
Host	smart-08860c9b-8bea-44e0-966e-9fa4adf6fcbc
User	root
Command	/workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 59405308 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.chip_sw_all_escalation_resets.59405308
Directory	/workspace/24.chip_sw_all_escalation_resets/latest

Test location	/workspace/coverage/default/26.chip_sw_alert_handler_lpg_sleep_mode_alerts.1351198433
Short name	T442
Test name
Test status
Simulation time	3647174264 ps
CPU time	352.68 seconds
Started	Aug 14 06:12:26 PM PDT 24
Finished	Aug 14 06:18:19 PM PDT 24
Peak memory	649644 kb
Host	smart-53e14539-060a-49de-8b7e-5ee43d7881c9
User	root
Command	/workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrlstate_regs +avoid_ferr_ips_append=otp_ctrlu_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1351198433 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.chip_ sw_alert_handler_lpg_sleep_mode_alerts.1351198433
Directory	/workspace/26.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location	/workspace/coverage/default/26.chip_sw_all_escalation_resets.2448680340
Short name	T445
Test name
Test status
Simulation time	5753462372 ps
CPU time	782.99 seconds
Started	Aug 14 06:12:35 PM PDT 24
Finished	Aug 14 06:25:38 PM PDT 24
Peak memory	650724 kb
Host	smart-26788aef-e5e0-4708-a577-7f0b42aba2fb
User	root
Command	/workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 2448680340 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.chip_sw_all_escalation_resets.2448680340
Directory	/workspace/26.chip_sw_all_escalation_resets/latest

Test location	/workspace/coverage/default/27.chip_sw_alert_handler_lpg_sleep_mode_alerts.834011930
Short name	T112
Test name
Test status
Simulation time	3707129850 ps
CPU time	369.31 seconds
Started	Aug 14 06:11:13 PM PDT 24
Finished	Aug 14 06:17:23 PM PDT 24
Peak memory	649608 kb
Host	smart-76198b00-6fbc-4340-968f-e7d3832d952e
User	root
Command	/workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrlstate_regs +avoid_ferr_ips_append=otp_ctrlu_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=834011930 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all _escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.chip_s w_alert_handler_lpg_sleep_mode_alerts.834011930
Directory	/workspace/27.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location	/workspace/coverage/default/27.chip_sw_all_escalation_resets.1871469707
Short name	T506
Test name
Test status
Simulation time	4615826760 ps
CPU time	705.08 seconds
Started	Aug 14 06:14:18 PM PDT 24
Finished	Aug 14 06:26:03 PM PDT 24
Peak memory	650756 kb
Host	smart-555b55be-0468-45f8-9880-4c1be9ba68b9
User	root
Command	/workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 1871469707 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.chip_sw_all_escalation_resets.1871469707
Directory	/workspace/27.chip_sw_all_escalation_resets/latest

Test location	/workspace/coverage/default/3.chip_sw_alert_handler_lpg_sleep_mode_alerts.49105368
Short name	T521
Test name
Test status
Simulation time	3846907890 ps
CPU time	376.3 seconds
Started	Aug 14 06:08:57 PM PDT 24
Finished	Aug 14 06:15:15 PM PDT 24
Peak memory	649332 kb
Host	smart-e9365526-2255-4066-bcfa-1e2d87d231b7
User	root
Command	/workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrlstate_regs +avoid_ferr_ips_append=otp_ctrlu_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49105368 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_ escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.chip_sw_ alert_handler_lpg_sleep_mode_alerts.49105368
Directory	/workspace/3.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location	/workspace/coverage/default/3.chip_sw_all_escalation_resets.1407285796
Short name	T980
Test name
Test status
Simulation time	4465912100 ps
CPU time	667.72 seconds
Started	Aug 14 06:10:43 PM PDT 24
Finished	Aug 14 06:21:51 PM PDT 24
Peak memory	651104 kb
Host	smart-8172bfa1-bf27-49d2-8354-0fe402d31619
User	root
Command	/workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 1407285796 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.chip_sw_all_escalation_resets.1407285796
Directory	/workspace/3.chip_sw_all_escalation_resets/latest

Test location	/workspace/coverage/default/32.chip_sw_alert_handler_lpg_sleep_mode_alerts.616013443
Short name	T504
Test name
Test status
Simulation time	3684628392 ps
CPU time	420.35 seconds
Started	Aug 14 06:17:04 PM PDT 24
Finished	Aug 14 06:24:05 PM PDT 24
Peak memory	649600 kb
Host	smart-4e5488af-7865-4d91-a896-3257cda6676e
User	root
Command	/workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrlstate_regs +avoid_ferr_ips_append=otp_ctrlu_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=616013443 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all _escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.chip_s w_alert_handler_lpg_sleep_mode_alerts.616013443
Directory	/workspace/32.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location	/workspace/coverage/default/32.chip_sw_all_escalation_resets.4017906303
Short name	T446
Test name
Test status
Simulation time	6068171000 ps
CPU time	642.47 seconds
Started	Aug 14 06:11:15 PM PDT 24
Finished	Aug 14 06:21:58 PM PDT 24
Peak memory	650460 kb
Host	smart-33ac1e51-93eb-4707-a975-9fad76140540
User	root
Command	/workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 4017906303 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.chip_sw_all_escalation_resets.4017906303
Directory	/workspace/32.chip_sw_all_escalation_resets/latest

Test location	/workspace/coverage/default/35.chip_sw_alert_handler_lpg_sleep_mode_alerts.2163397945
Short name	T526
Test name
Test status
Simulation time	3924004060 ps
CPU time	454.37 seconds
Started	Aug 14 06:14:17 PM PDT 24
Finished	Aug 14 06:21:51 PM PDT 24
Peak memory	649276 kb
Host	smart-7604f081-54b3-42ce-b1d6-a1fb90a40aef
User	root
Command	/workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrlstate_regs +avoid_ferr_ips_append=otp_ctrlu_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2163397945 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.chip_ sw_alert_handler_lpg_sleep_mode_alerts.2163397945
Directory	/workspace/35.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location	/workspace/coverage/default/36.chip_sw_alert_handler_lpg_sleep_mode_alerts.3224808878
Short name	T482
Test name
Test status
Simulation time	4374598036 ps
CPU time	505.97 seconds
Started	Aug 14 06:14:03 PM PDT 24
Finished	Aug 14 06:22:29 PM PDT 24
Peak memory	649860 kb
Host	smart-5acaeafe-c776-43be-96e9-01236d36d666
User	root
Command	/workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrlstate_regs +avoid_ferr_ips_append=otp_ctrlu_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3224808878 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.chip_ sw_alert_handler_lpg_sleep_mode_alerts.3224808878
Directory	/workspace/36.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location	/workspace/coverage/default/37.chip_sw_all_escalation_resets.3215335215
Short name	T539
Test name
Test status
Simulation time	4415171960 ps
CPU time	572.19 seconds
Started	Aug 14 06:17:14 PM PDT 24
Finished	Aug 14 06:26:46 PM PDT 24
Peak memory	650716 kb
Host	smart-95975567-b2f9-42b2-b5bb-d9c14c1f8e0e
User	root
Command	/workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 3215335215 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.chip_sw_all_escalation_resets.3215335215
Directory	/workspace/37.chip_sw_all_escalation_resets/latest

Test location	/workspace/coverage/default/38.chip_sw_alert_handler_lpg_sleep_mode_alerts.1912127956
Short name	T457
Test name
Test status
Simulation time	4538016088 ps
CPU time	336.19 seconds
Started	Aug 14 06:11:17 PM PDT 24
Finished	Aug 14 06:16:53 PM PDT 24
Peak memory	649532 kb
Host	smart-7fa2e536-80c0-4722-be6c-783e5f0b5439
User	root
Command	/workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrlstate_regs +avoid_ferr_ips_append=otp_ctrlu_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1912127956 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.chip_ sw_alert_handler_lpg_sleep_mode_alerts.1912127956
Directory	/workspace/38.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location	/workspace/coverage/default/39.chip_sw_alert_handler_lpg_sleep_mode_alerts.2298089335
Short name	T401
Test name
Test status
Simulation time	4409569182 ps
CPU time	444.39 seconds
Started	Aug 14 06:13:18 PM PDT 24
Finished	Aug 14 06:20:42 PM PDT 24
Peak memory	650116 kb
Host	smart-40d5b6b2-eb52-416a-b34c-552105273faa
User	root
Command	/workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrlstate_regs +avoid_ferr_ips_append=otp_ctrlu_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2298089335 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.chip_ sw_alert_handler_lpg_sleep_mode_alerts.2298089335
Directory	/workspace/39.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location	/workspace/coverage/default/39.chip_sw_all_escalation_resets.2619978890
Short name	T353
Test name
Test status
Simulation time	5541160844 ps
CPU time	520.8 seconds
Started	Aug 14 06:17:12 PM PDT 24
Finished	Aug 14 06:25:53 PM PDT 24
Peak memory	650468 kb
Host	smart-144a6663-b334-4a49-a690-55dbed4446e7
User	root
Command	/workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 2619978890 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.chip_sw_all_escalation_resets.2619978890
Directory	/workspace/39.chip_sw_all_escalation_resets/latest

Test location	/workspace/coverage/default/40.chip_sw_alert_handler_lpg_sleep_mode_alerts.3216885078
Short name	T519
Test name
Test status
Simulation time	4071039000 ps
CPU time	406.63 seconds
Started	Aug 14 06:14:52 PM PDT 24
Finished	Aug 14 06:21:39 PM PDT 24
Peak memory	649632 kb
Host	smart-d69c8561-48c4-470c-8b1c-d606eddcc037
User	root
Command	/workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrlstate_regs +avoid_ferr_ips_append=otp_ctrlu_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3216885078 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.chip_ sw_alert_handler_lpg_sleep_mode_alerts.3216885078
Directory	/workspace/40.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location	/workspace/coverage/default/41.chip_sw_alert_handler_lpg_sleep_mode_alerts.880573998
Short name	T263
Test name
Test status
Simulation time	3366553234 ps
CPU time	482.7 seconds
Started	Aug 14 06:12:50 PM PDT 24
Finished	Aug 14 06:20:53 PM PDT 24
Peak memory	649504 kb
Host	smart-b035b94e-d5de-48eb-8fe7-a141cbd8c6fc
User	root
Command	/workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrlstate_regs +avoid_ferr_ips_append=otp_ctrlu_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=880573998 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all _escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.chip_s w_alert_handler_lpg_sleep_mode_alerts.880573998
Directory	/workspace/41.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location	/workspace/coverage/default/42.chip_sw_alert_handler_lpg_sleep_mode_alerts.1365941886
Short name	T461
Test name
Test status
Simulation time	4048136126 ps
CPU time	444.03 seconds
Started	Aug 14 06:15:21 PM PDT 24
Finished	Aug 14 06:22:45 PM PDT 24
Peak memory	649624 kb
Host	smart-5dbb06b7-f441-4a4b-8fad-dd135e7bfb43
User	root
Command	/workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrlstate_regs +avoid_ferr_ips_append=otp_ctrlu_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1365941886 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.chip_ sw_alert_handler_lpg_sleep_mode_alerts.1365941886
Directory	/workspace/42.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location	/workspace/coverage/default/42.chip_sw_all_escalation_resets.762267365
Short name	T283
Test name
Test status
Simulation time	4378703640 ps
CPU time	643.59 seconds
Started	Aug 14 06:13:45 PM PDT 24
Finished	Aug 14 06:24:30 PM PDT 24
Peak memory	650900 kb
Host	smart-b73dd622-4f14-427d-a7b0-edee9b5559c5
User	root
Command	/workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 762267365 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.chip_sw_all_escalation_resets.762267365
Directory	/workspace/42.chip_sw_all_escalation_resets/latest

Test location	/workspace/coverage/default/43.chip_sw_all_escalation_resets.2595458387
Short name	T423
Test name
Test status
Simulation time	6143314744 ps
CPU time	605.6 seconds
Started	Aug 14 06:12:23 PM PDT 24
Finished	Aug 14 06:22:29 PM PDT 24
Peak memory	650828 kb
Host	smart-5e6d5ae9-7b17-4340-86d1-eb1316beec65
User	root
Command	/workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 2595458387 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.chip_sw_all_escalation_resets.2595458387
Directory	/workspace/43.chip_sw_all_escalation_resets/latest

Test location	/workspace/coverage/default/44.chip_sw_alert_handler_lpg_sleep_mode_alerts.4215108881
Short name	T547
Test name
Test status
Simulation time	3370301624 ps
CPU time	313.49 seconds
Started	Aug 14 06:13:31 PM PDT 24
Finished	Aug 14 06:18:45 PM PDT 24
Peak memory	649568 kb
Host	smart-d763904b-67f6-4ab0-adc4-2bd1173129f2
User	root
Command	/workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrlstate_regs +avoid_ferr_ips_append=otp_ctrlu_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4215108881 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.chip_ sw_alert_handler_lpg_sleep_mode_alerts.4215108881
Directory	/workspace/44.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location	/workspace/coverage/default/46.chip_sw_all_escalation_resets.378520222
Short name	T551
Test name
Test status
Simulation time	4764612624 ps
CPU time	671.85 seconds
Started	Aug 14 06:13:17 PM PDT 24
Finished	Aug 14 06:24:29 PM PDT 24
Peak memory	650732 kb
Host	smart-b15491b4-26c0-41b0-baf2-99c52b4a6ee8
User	root
Command	/workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 378520222 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.chip_sw_all_escalation_resets.378520222
Directory	/workspace/46.chip_sw_all_escalation_resets/latest

Test location	/workspace/coverage/default/47.chip_sw_alert_handler_lpg_sleep_mode_alerts.2876863207
Short name	T475
Test name
Test status
Simulation time	3354747324 ps
CPU time	374.38 seconds
Started	Aug 14 06:12:27 PM PDT 24
Finished	Aug 14 06:18:42 PM PDT 24
Peak memory	649584 kb
Host	smart-ee0492cb-19ae-4b8c-8a46-678d074072c4
User	root
Command	/workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrlstate_regs +avoid_ferr_ips_append=otp_ctrlu_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2876863207 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.chip_ sw_alert_handler_lpg_sleep_mode_alerts.2876863207
Directory	/workspace/47.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location	/workspace/coverage/default/47.chip_sw_all_escalation_resets.2441963508
Short name	T532
Test name
Test status
Simulation time	5567590776 ps
CPU time	575.04 seconds
Started	Aug 14 06:13:47 PM PDT 24
Finished	Aug 14 06:23:23 PM PDT 24
Peak memory	650728 kb
Host	smart-eb890061-02f6-4303-b5a0-66aa61685bab
User	root
Command	/workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 2441963508 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.chip_sw_all_escalation_resets.2441963508
Directory	/workspace/47.chip_sw_all_escalation_resets/latest

Test location	/workspace/coverage/default/49.chip_sw_alert_handler_lpg_sleep_mode_alerts.1258880215
Short name	T453
Test name
Test status
Simulation time	3219121588 ps
CPU time	384.31 seconds
Started	Aug 14 06:12:56 PM PDT 24
Finished	Aug 14 06:19:21 PM PDT 24
Peak memory	649768 kb
Host	smart-17443a07-a43a-4351-8796-6e6ee52cb652
User	root
Command	/workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrlstate_regs +avoid_ferr_ips_append=otp_ctrlu_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1258880215 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.chip_ sw_alert_handler_lpg_sleep_mode_alerts.1258880215
Directory	/workspace/49.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location	/workspace/coverage/default/49.chip_sw_all_escalation_resets.946245582
Short name	T528
Test name
Test status
Simulation time	6035469570 ps
CPU time	743.5 seconds
Started	Aug 14 06:15:17 PM PDT 24
Finished	Aug 14 06:27:41 PM PDT 24
Peak memory	650708 kb
Host	smart-722697b6-8e17-468f-a712-f68aff28883f
User	root
Command	/workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 946245582 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.chip_sw_all_escalation_resets.946245582
Directory	/workspace/49.chip_sw_all_escalation_resets/latest

Test location	/workspace/coverage/default/50.chip_sw_alert_handler_lpg_sleep_mode_alerts.986594536
Short name	T524
Test name
Test status
Simulation time	3831919420 ps
CPU time	413.35 seconds
Started	Aug 14 06:14:57 PM PDT 24
Finished	Aug 14 06:21:50 PM PDT 24
Peak memory	649272 kb
Host	smart-354dcfd9-51ac-4529-a128-63282d90ae1d
User	root
Command	/workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrlstate_regs +avoid_ferr_ips_append=otp_ctrlu_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=986594536 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all _escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 50.chip_s w_alert_handler_lpg_sleep_mode_alerts.986594536
Directory	/workspace/50.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location	/workspace/coverage/default/53.chip_sw_all_escalation_resets.3126985555
Short name	T486
Test name
Test status
Simulation time	6083430472 ps
CPU time	734.34 seconds
Started	Aug 14 06:14:45 PM PDT 24
Finished	Aug 14 06:27:00 PM PDT 24
Peak memory	650676 kb
Host	smart-5bfb238d-d700-49ee-a0d5-343aa90ce9b0
User	root
Command	/workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 3126985555 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 53.chip_sw_all_escalation_resets.3126985555
Directory	/workspace/53.chip_sw_all_escalation_resets/latest

Test location	/workspace/coverage/default/55.chip_sw_alert_handler_lpg_sleep_mode_alerts.1441279622
Short name	T89
Test name
Test status
Simulation time	3959408824 ps
CPU time	421.69 seconds
Started	Aug 14 06:17:37 PM PDT 24
Finished	Aug 14 06:24:39 PM PDT 24
Peak memory	649572 kb
Host	smart-1f5c0da3-3043-41ec-b437-94807f133e9f
User	root
Command	/workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrlstate_regs +avoid_ferr_ips_append=otp_ctrlu_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1441279622 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 55.chip_ sw_alert_handler_lpg_sleep_mode_alerts.1441279622
Directory	/workspace/55.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location	/workspace/coverage/default/55.chip_sw_all_escalation_resets.670902966
Short name	T514
Test name
Test status
Simulation time	5411490960 ps
CPU time	548.94 seconds
Started	Aug 14 06:15:36 PM PDT 24
Finished	Aug 14 06:24:46 PM PDT 24
Peak memory	650968 kb
Host	smart-c12b3d01-db8b-42c7-841c-77113f0fe518
User	root
Command	/workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 670902966 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 55.chip_sw_all_escalation_resets.670902966
Directory	/workspace/55.chip_sw_all_escalation_resets/latest

Test location	/workspace/coverage/default/56.chip_sw_alert_handler_lpg_sleep_mode_alerts.4250016360
Short name	T123
Test name
Test status
Simulation time	3554265560 ps
CPU time	412.56 seconds
Started	Aug 14 06:17:25 PM PDT 24
Finished	Aug 14 06:24:18 PM PDT 24
Peak memory	649208 kb
Host	smart-5d020798-1dc9-4b17-8a2e-fcca0bc12460
User	root
Command	/workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrlstate_regs +avoid_ferr_ips_append=otp_ctrlu_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4250016360 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 56.chip_ sw_alert_handler_lpg_sleep_mode_alerts.4250016360
Directory	/workspace/56.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location	/workspace/coverage/default/58.chip_sw_alert_handler_lpg_sleep_mode_alerts.568143593
Short name	T509
Test name
Test status
Simulation time	2796828728 ps
CPU time	340.31 seconds
Started	Aug 14 06:14:43 PM PDT 24
Finished	Aug 14 06:20:23 PM PDT 24
Peak memory	649364 kb
Host	smart-699d1f64-7436-4b2f-af4b-d52b39974dd6
User	root
Command	/workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrlstate_regs +avoid_ferr_ips_append=otp_ctrlu_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=568143593 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all _escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 58.chip_s w_alert_handler_lpg_sleep_mode_alerts.568143593
Directory	/workspace/58.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location	/workspace/coverage/default/64.chip_sw_alert_handler_lpg_sleep_mode_alerts.3697555326
Short name	T553
Test name
Test status
Simulation time	3728905720 ps
CPU time	378.81 seconds
Started	Aug 14 06:15:02 PM PDT 24
Finished	Aug 14 06:21:21 PM PDT 24
Peak memory	649664 kb
Host	smart-5de47d7f-8f69-4ee4-8b22-4799c6f8fe9d
User	root
Command	/workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrlstate_regs +avoid_ferr_ips_append=otp_ctrlu_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3697555326 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 64.chip_ sw_alert_handler_lpg_sleep_mode_alerts.3697555326
Directory	/workspace/64.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location	/workspace/coverage/default/67.chip_sw_alert_handler_lpg_sleep_mode_alerts.3553041001
Short name	T466
Test name
Test status
Simulation time	3651467848 ps
CPU time	304.53 seconds
Started	Aug 14 06:17:44 PM PDT 24
Finished	Aug 14 06:22:49 PM PDT 24
Peak memory	649668 kb
Host	smart-b7fb0db2-a778-4b24-932f-9083e4c96b3e
User	root
Command	/workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrlstate_regs +avoid_ferr_ips_append=otp_ctrlu_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3553041001 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 67.chip_ sw_alert_handler_lpg_sleep_mode_alerts.3553041001
Directory	/workspace/67.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location	/workspace/coverage/default/68.chip_sw_all_escalation_resets.1035766392
Short name	T349
Test name
Test status
Simulation time	5062127344 ps
CPU time	535.61 seconds
Started	Aug 14 06:14:18 PM PDT 24
Finished	Aug 14 06:23:14 PM PDT 24
Peak memory	651096 kb
Host	smart-901d46c0-782f-44e8-b7e9-1f1a5336424a
User	root
Command	/workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 1035766392 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 68.chip_sw_all_escalation_resets.1035766392
Directory	/workspace/68.chip_sw_all_escalation_resets/latest

Test location	/workspace/coverage/default/71.chip_sw_alert_handler_lpg_sleep_mode_alerts.1066538361
Short name	T385
Test name
Test status
Simulation time	3822546664 ps
CPU time	445.92 seconds
Started	Aug 14 06:16:08 PM PDT 24
Finished	Aug 14 06:23:34 PM PDT 24
Peak memory	649524 kb
Host	smart-8dd446e7-8914-4843-a91a-b8dc7091ca27
User	root
Command	/workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrlstate_regs +avoid_ferr_ips_append=otp_ctrlu_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1066538361 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 71.chip_ sw_alert_handler_lpg_sleep_mode_alerts.1066538361
Directory	/workspace/71.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location	/workspace/coverage/default/8.chip_sw_alert_handler_lpg_sleep_mode_alerts.3238938059
Short name	T157
Test name
Test status
Simulation time	3898879060 ps
CPU time	489.57 seconds
Started	Aug 14 06:11:19 PM PDT 24
Finished	Aug 14 06:19:29 PM PDT 24
Peak memory	649536 kb
Host	smart-1026f34c-ed68-4221-8255-105d2e71da30
User	root
Command	/workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrlstate_regs +avoid_ferr_ips_append=otp_ctrlu_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3238938059 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.chip_s w_alert_handler_lpg_sleep_mode_alerts.3238938059
Directory	/workspace/8.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location	/workspace/coverage/default/8.chip_sw_all_escalation_resets.3909638825
Short name	T522
Test name
Test status
Simulation time	4721004168 ps
CPU time	427.43 seconds
Started	Aug 14 06:11:06 PM PDT 24
Finished	Aug 14 06:18:14 PM PDT 24
Peak memory	649864 kb
Host	smart-2bc1117b-6381-49de-a0e5-266f2cd405e8
User	root
Command	/workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 3909638825 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.chip_sw_all_escalation_resets.3909638825
Directory	/workspace/8.chip_sw_all_escalation_resets/latest

Test location	/workspace/coverage/default/82.chip_sw_all_escalation_resets.1564262822
Short name	T278
Test name
Test status
Simulation time	4758761416 ps
CPU time	579.53 seconds
Started	Aug 14 06:16:38 PM PDT 24
Finished	Aug 14 06:26:18 PM PDT 24
Peak memory	651168 kb
Host	smart-66939a17-21f0-4174-9efd-8deee6319bcf
User	root
Command	/workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 1564262822 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 82.chip_sw_all_escalation_resets.1564262822
Directory	/workspace/82.chip_sw_all_escalation_resets/latest

Test location	/workspace/coverage/default/89.chip_sw_all_escalation_resets.4181144789
Short name	T508
Test name
Test status
Simulation time	4990699088 ps
CPU time	527.96 seconds
Started	Aug 14 06:17:22 PM PDT 24
Finished	Aug 14 06:26:11 PM PDT 24
Peak memory	648980 kb
Host	smart-ce3f12cd-db5a-4ec5-b3e3-908367456cdb
User	root
Command	/workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 4181144789 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 89.chip_sw_all_escalation_resets.4181144789
Directory	/workspace/89.chip_sw_all_escalation_resets/latest

Test location	/workspace/coverage/default/1.chip_sw_spi_host_tx_rx.1594829807
Short name	T52
Test name
Test status
Simulation time	3020659000 ps
CPU time	346.83 seconds
Started	Aug 14 05:55:13 PM PDT 24
Finished	Aug 14 06:01:00 PM PDT 24
Peak memory	609708 kb
Host	smart-47f5718d-7788-46e6-a5ff-a4140ef968c4
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=spi_host_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1594829807 -assert nopostproc +UVM_TESTNAM E=chip_base_test +UVM_TEST_SEQ=chip_sw_spi_host_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb - cm_log /dev/null -cm_name 1.chip_sw_spi_host_tx_rx.1594829807
Directory	/workspace/1.chip_sw_spi_host_tx_rx/latest

Test location	/workspace/coverage/default/2.chip_sw_csrng_edn_concurrency_reduced_freq.3412419296
Short name	T136
Test name
Test status
Simulation time	27837798152 ps
CPU time	4202.2 seconds
Started	Aug 14 06:07:56 PM PDT 24
Finished	Aug 14 07:17:59 PM PDT 24
Peak memory	611084 kb
Host	smart-9085f3cb-c7ee-48e6-b980-53ceff8e690b
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=360_000_000 +rng_srate_value_min=15 +rng_srate_value_max=20 +cal_sys_clk_70mhz=1 +en_jitter=1 +accelerate_ cold_power_up_time=3 +accelerate_regulators_power_up_time=2 +sw_build_device=sim_dv +sw_images=csrng_edn_concurrency_test:1:new_rules,test_rom:0 + cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_ seed=3412419296 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_csrng_edn_concurrency_reduced_freq.3412419296
Directory	/workspace/2.chip_sw_csrng_edn_concurrency_reduced_freq/latest

Test location	/workspace/coverage/default/0.chip_sw_lc_ctrl_rand_to_scrap.3335819945
Short name	T71
Test name
Test status
Simulation time	3376427242 ps
CPU time	336.22 seconds
Started	Aug 14 05:49:16 PM PDT 24
Finished	Aug 14 05:54:53 PM PDT 24
Peak memory	622120 kb
Host	smart-c8d95309-471e-4de2-94c2-cdad74a3c11b
User	root
Command	/workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=lc_ctrl_scrap_test:1:new_rules,test_rom:0 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33358199 45 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_scrap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_lc_ctrl_rand_to_scrap.3335819945
Directory	/workspace/0.chip_sw_lc_ctrl_rand_to_scrap/latest

Test location	/workspace/coverage/default/0.chip_sw_uart_tx_rx_bootstrap.1587856144
Short name	T26
Test name
Test status
Simulation time	79015748680 ps
CPU time	14457 seconds
Started	Aug 14 05:47:11 PM PDT 24
Finished	Aug 14 09:48:11 PM PDT 24
Peak memory	634544 kb
Host	smart-c82fcd9e-11bc-4b18-99bb-d7331d9e36ae
User	root
Command	/workspace/default/simv +use_spi_load_bootstrap=1 +calibrate_usb_clk=1 +test_timeout_ns=160_000_000 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test :1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=1587856144 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_uart_tx_rx_bootstrap.1587856144
Directory	/workspace/0.chip_sw_uart_tx_rx_bootstrap/latest

Test location	/workspace/coverage/default/2.chip_sw_sensor_ctrl_alert.1911045134
Short name	T142
Test name
Test status
Simulation time	9063649936 ps
CPU time	950.78 seconds
Started	Aug 14 06:05:02 PM PDT 24
Finished	Aug 14 06:20:53 PM PDT 24
Peak memory	611272 kb
Host	smart-52d91d4a-ef4d-4ae3-862e-9136c2700ae4
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=40_000_000 +sw_build_device=sim_dv +sw_images=sensor_ctrl_alert_test:1:new_rules,test_rom:0 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19110451 34 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac e/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_sensor_ctrl_alert.1911045134
Directory	/workspace/2.chip_sw_sensor_ctrl_alert/latest

Test location	/workspace/coverage/default/2.chip_plic_all_irqs_0.2944717956
Short name	T235
Test name
Test status
Simulation time	5583120440 ps
CPU time	1087.22 seconds
Started	Aug 14 06:07:05 PM PDT 24
Finished	Aug 14 06:25:13 PM PDT 24
Peak memory	609788 kb
Host	smart-70d8a20b-df4c-481c-b3fd-03571e678924
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=plic_all_irqs_test_0:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2944717956 -assert nopostproc +UVM_TESTNA ME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 2.chip_plic_all_irqs_0.2944717956
Directory	/workspace/2.chip_plic_all_irqs_0/latest

Test location	/workspace/coverage/default/0.chip_sw_usbdev_pincfg.4152755177
Short name	T39
Test name
Test status
Simulation time	31644181968 ps
CPU time	6231.26 seconds
Started	Aug 14 05:49:31 PM PDT 24
Finished	Aug 14 07:33:24 PM PDT 24
Peak memory	610916 kb
Host	smart-4838a31a-f5dc-40e8-9e37-ef9cbf764dda
User	root
Command	/workspace/default/simv +uart_idx=0 +calibrate_usb_clk=1 +sw_test_timeout_ns=100_000_000 +sw_build_device=sim_dv +sw_images=usbdev_pincfg_test:1:new_r ules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim .tcl +ntb_random_seed=4152755177 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_usbdev_dpi_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_usbdev_pincfg.4152755177
Directory	/workspace/0.chip_sw_usbdev_pincfg/latest

Test location	/workspace/coverage/default/0.rom_e2e_jtag_debug_dev.163765351
Short name	T193
Test name
Test status
Simulation time	10839441850 ps
CPU time	2016.4 seconds
Started	Aug 14 05:50:58 PM PDT 24
Finished	Aug 14 06:24:35 PM PDT 24
Peak memory	624640 kb
Host	smart-efeab495-fc91-47cd-bb58-c89ad03745c4
User	root
Command	/workspace/default/simv +use_jtag_dmi=1 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=img_dev_exec_disabled:4,mask_rom:0 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16376 5351 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rom_e2e_jtag_debug_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_jtag_debug_dev.163765351
Directory	/workspace/0.rom_e2e_jtag_debug_dev/latest

Test location	/workspace/coverage/default/1.chip_plic_all_irqs_20.3715513551
Short name	T231
Test name
Test status
Simulation time	5405410492 ps
CPU time	803.76 seconds
Started	Aug 14 05:54:56 PM PDT 24
Finished	Aug 14 06:08:21 PM PDT 24
Peak memory	610316 kb
Host	smart-010d3e10-97df-4665-a948-336678edddd1
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=plic_all_irqs_test_20:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3715513551 -assert nopostproc +UVM_TESTN AME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log / dev/null -cm_name 1.chip_plic_all_irqs_20.3715513551
Directory	/workspace/1.chip_plic_all_irqs_20/latest

Test location	/workspace/coverage/default/2.chip_sw_sram_ctrl_scrambled_access.2120579373
Short name	T351
Test name
Test status
Simulation time	5429957496 ps
CPU time	647.35 seconds
Started	Aug 14 06:05:14 PM PDT 24
Finished	Aug 14 06:16:02 PM PDT 24
Peak memory	610504 kb
Host	smart-1703a375-90f2-4e72-aaa3-00d0455421bb
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=12_000_000 +en_scb_tl_err_chk=0 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=sram _ctrl_scrambled_access_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2120579373 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sram_ctr l_scrambled_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw _sram_ctrl_scrambled_access.2120579373
Directory	/workspace/2.chip_sw_sram_ctrl_scrambled_access/latest

Test location	/workspace/coverage/default/0.chip_sw_kmac_app_rom.1217211982
Short name	T662
Test name
Test status
Simulation time	2147344728 ps
CPU time	269.97 seconds
Started	Aug 14 05:53:09 PM PDT 24
Finished	Aug 14 05:57:39 PM PDT 24
Peak memory	610292 kb
Host	smart-f5beecb6-6955-4f29-ab4d-b52646a6ca44
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=kmac_app_rom_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1217211982 -assert nopostproc +UVM_TESTNAME= chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/ null -cm_name 0.chip_sw_kmac_app_rom.1217211982
Directory	/workspace/0.chip_sw_kmac_app_rom/latest

Test location	/workspace/coverage/default/2.chip_sw_flash_ctrl_ops_jitter_en.1229759114
Short name	T2
Test name
Test status
Simulation time	4826440021 ps
CPU time	760.84 seconds
Started	Aug 14 05:59:10 PM PDT 24
Finished	Aug 14 06:11:51 PM PDT 24
Peak memory	610864 kb
Host	smart-53546a31-e240-4c42-b6b2-3f34176f91e3
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=50_000_000 +en_jitter=1 +sw_build_device=sim_dv +sw_images=flash_ctrl_ops_test:1:new_rules,test_rom:0 +cdc _instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see d=1229759114 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_flash_ctrl_ops_jitter_en.1229759114
Directory	/workspace/2.chip_sw_flash_ctrl_ops_jitter_en/latest

Test location	/workspace/coverage/default/0.chip_sw_sysrst_ctrl_ulp_z3_wakeup.4140920706
Short name	T56
Test name
Test status
Simulation time	5720566208 ps
CPU time	501.27 seconds
Started	Aug 14 05:49:41 PM PDT 24
Finished	Aug 14 05:58:03 PM PDT 24
Peak memory	610444 kb
Host	smart-4e53700e-9080-448a-9357-31162bf228c2
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=sysrst_ctrl_ulp_z3_wakeup_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4140920706 -assert nopostproc + UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sysrst_ctrl_ulp_z3_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/ coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_sysrst_ctrl_ulp_z3_wakeup.4140920706
Directory	/workspace/0.chip_sw_sysrst_ctrl_ulp_z3_wakeup/latest

Test location	/workspace/coverage/pad_ctrl_test_mode/7.chip_padctrl_attributes.2759294692
Short name	T51
Test name
Test status
Simulation time	5323029040 ps
CPU time	262.24 seconds
Started	Aug 14 05:39:03 PM PDT 24
Finished	Aug 14 05:43:25 PM PDT 24
Peak memory	649660 kb
Host	smart-2c46f3d0-64f0-432a-a725-40d579b64731
User	root
Command	/workspace/pad_ctrl_test_mode/simv +use_otp_image=OtpTypeLcStProd +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2759294692 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TE ST_SEQ=chip_padctrl_attributes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/pad_ctrl_test_mode.vdb -cm_log /dev/ null -cm_name 7.chip_padctrl_attributes.2759294692
Directory	/workspace/7.chip_padctrl_attributes/latest

Test location	/workspace/coverage/default/4.chip_sw_uart_tx_rx_alt_clk_freq.1612197426
Short name	T34
Test name
Test status
Simulation time	9056244132 ps
CPU time	1408.73 seconds
Started	Aug 14 06:09:26 PM PDT 24
Finished	Aug 14 06:32:55 PM PDT 24
Peak memory	625064 kb
Host	smart-29c2e709-2cde-42f9-ab12-e103a3f2d61d
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=80_000_000 +chip_clock_source=ChipClockSourceExternal96Mhz +calibrate_usb_clk=1 +sw_build_device=sim_dv +s w_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1612197426 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_b audrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.chip_sw_uart_tx_rx _alt_clk_freq.1612197426
Directory	/workspace/4.chip_sw_uart_tx_rx_alt_clk_freq/latest

Test location	/workspace/coverage/default/15.chip_sw_all_escalation_resets.1207984759
Short name	T320
Test name
Test status
Simulation time	4895454412 ps
CPU time	461.68 seconds
Started	Aug 14 06:10:30 PM PDT 24
Finished	Aug 14 06:18:12 PM PDT 24
Peak memory	611740 kb
Host	smart-751161c5-f146-4d32-91cb-cfbea4415e50
User	root
Command	/workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 1207984759 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.chip_sw_all_escalation_resets.1207984759
Directory	/workspace/15.chip_sw_all_escalation_resets/latest

Test location	/workspace/coverage/default/0.chip_sw_flash_init.209174306
Short name	T216
Test name
Test status
Simulation time	20428292805 ps
CPU time	2102.9 seconds
Started	Aug 14 05:47:39 PM PDT 24
Finished	Aug 14 06:22:43 PM PDT 24
Peak memory	613080 kb
Host	smart-ff8ca6aa-ad14-4dbf-b4fd-70c432aa1274
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=25_000_000 +sw_build_device=sim_dv +sw_images=flash_init_test:0:test_in_rom:new_rules +cdc_instrumentation _enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=209174306 -ass ert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_flash_init_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace /coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_flash_init.209174306
Directory	/workspace/0.chip_sw_flash_init/latest

Test location	/workspace/coverage/default/2.chip_sw_flash_rma_unlocked.2197864360
Short name	T223
Test name
Test status
Simulation time	43930190785 ps
CPU time	4710.79 seconds
Started	Aug 14 05:57:46 PM PDT 24
Finished	Aug 14 07:16:17 PM PDT 24
Peak memory	624760 kb
Host	smart-255ba5bd-796c-416c-98b3-f886ff6d5494
User	root
Command	/workspace/default/simv +flash_program_latency=5 +sw_test_timeout_ns=150_000_000 +sw_build_device=sim_dv +sw_images=flash_rma_unlocked_test:0:test_in_ rom:new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t cl +ntb_random_seed=2197864360 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_flash_rma_unlocked_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_flash_rma_unlocked.2197864360
Directory	/workspace/2.chip_sw_flash_rma_unlocked/latest

Test location	/workspace/coverage/default/2.chip_jtag_csr_rw.415199552
Short name	T101
Test name
Test status
Simulation time	4378821652 ps
CPU time	274.07 seconds
Started	Aug 14 05:58:09 PM PDT 24
Finished	Aug 14 06:02:44 PM PDT 24
Peak memory	608484 kb
Host	smart-3f9d1dd4-f451-4d53-be5c-c01bd90373df
User	root
Command	/workspace/default/simv +en_scb=0 +csr_rw +create_jtag_riscv_map=1 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=415199552 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TE ST_SEQ=chip_jtag_csr_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.ch ip_jtag_csr_rw.415199552
Directory	/workspace/2.chip_jtag_csr_rw/latest

Test location	/workspace/coverage/default/0.chip_sw_sensor_ctrl_alert.132910492
Short name	T144
Test name
Test status
Simulation time	6434587638 ps
CPU time	458.97 seconds
Started	Aug 14 05:49:47 PM PDT 24
Finished	Aug 14 05:57:26 PM PDT 24
Peak memory	609984 kb
Host	smart-028fa60f-88cb-4093-a3a4-950b5b7251cd
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=40_000_000 +sw_build_device=sim_dv +sw_images=sensor_ctrl_alert_test:1:new_rules,test_rom:0 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13291049 2 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace /coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_sensor_ctrl_alert.132910492
Directory	/workspace/0.chip_sw_sensor_ctrl_alert/latest

Test location	/workspace/coverage/default/1.chip_sw_sensor_ctrl_alert.222439706
Short name	T150
Test name
Test status
Simulation time	8274758256 ps
CPU time	837.41 seconds
Started	Aug 14 05:51:40 PM PDT 24
Finished	Aug 14 06:05:38 PM PDT 24
Peak memory	610948 kb
Host	smart-b420c462-4df7-4e35-a2df-ca1dbde2b2e4
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=40_000_000 +sw_build_device=sim_dv +sw_images=sensor_ctrl_alert_test:1:new_rules,test_rom:0 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22243970 6 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace /coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_sensor_ctrl_alert.222439706
Directory	/workspace/1.chip_sw_sensor_ctrl_alert/latest

Test location	/workspace/coverage/default/1.chip_plic_all_irqs_10.2416229857
Short name	T161
Test name
Test status
Simulation time	3866273440 ps
CPU time	616.51 seconds
Started	Aug 14 05:53:40 PM PDT 24
Finished	Aug 14 06:03:57 PM PDT 24
Peak memory	610624 kb
Host	smart-16d2ba5d-3f6e-4a0f-8427-2dd57bb75a3a
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=plic_all_irqs_test_10:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2416229857 -assert nopostproc +UVM_TESTN AME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log / dev/null -cm_name 1.chip_plic_all_irqs_10.2416229857
Directory	/workspace/1.chip_plic_all_irqs_10/latest

Test location	/workspace/coverage/default/1.chip_sw_power_sleep_load.2095668869
Short name	T383
Test name
Test status
Simulation time	4205083760 ps
CPU time	358.48 seconds
Started	Aug 14 05:57:14 PM PDT 24
Finished	Aug 14 06:03:13 PM PDT 24
Peak memory	610416 kb
Host	smart-11cd3740-cf9b-49ee-80a1-dd8c6364132f
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=chip_power_sleep_load:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2095668869 -assert nopostproc +UVM_TESTN AME=chip_base_test +UVM_TEST_SEQ=chip_sw_power_sleep_load_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v db -cm_log /dev/null -cm_name 1.chip_sw_power_sleep_load.2095668869
Directory	/workspace/1.chip_sw_power_sleep_load/latest

Test location	/workspace/coverage/default/1.chip_sw_otp_ctrl_vendor_test_csr_access.1892272571
Short name	T203
Test name
Test status
Simulation time	2392455585 ps
CPU time	101.67 seconds
Started	Aug 14 05:53:46 PM PDT 24
Finished	Aug 14 05:55:28 PM PDT 24
Peak memory	622296 kb
Host	smart-236ba4e1-401c-4ff3-8c8f-de8fc453e5dc
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=otp_ctrl_vendor_test_csr_access_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1892272571 -assert nopost proc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_otp_ctrl_vendor_test_csr_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_otp_ctrl_vendor_test_csr_access.1892272571
Directory	/workspace/1.chip_sw_otp_ctrl_vendor_test_csr_access/latest

Test location	/workspace/coverage/default/1.chip_plic_all_irqs_0.1969715305
Short name	T234
Test name
Test status
Simulation time	5517594588 ps
CPU time	1281.25 seconds
Started	Aug 14 05:57:37 PM PDT 24
Finished	Aug 14 06:18:59 PM PDT 24
Peak memory	610336 kb
Host	smart-90a8a4b7-191f-413f-a295-b5518f5c4d0a
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=plic_all_irqs_test_0:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1969715305 -assert nopostproc +UVM_TESTNA ME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 1.chip_plic_all_irqs_0.1969715305
Directory	/workspace/1.chip_plic_all_irqs_0/latest

Test location	/workspace/coverage/default/0.chip_sw_ast_clk_rst_inputs.2824144296
Short name	T152
Test name
Test status
Simulation time	25989495262 ps
CPU time	3862.29 seconds
Started	Aug 14 05:48:16 PM PDT 24
Finished	Aug 14 06:52:40 PM PDT 24
Peak memory	611296 kb
Host	smart-3547f1a2-a281-4c5a-83d2-8adeee512510
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=200_000_000 +sw_build_device=sim_dv +sw_images=ast_clk_rst_inputs:1:new_rules,test_rom:0 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2824144296 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_ast_clk_rst_inputs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_ast_clk_rst_inputs.2824144296
Directory	/workspace/0.chip_sw_ast_clk_rst_inputs/latest

Test location	/workspace/coverage/default/0.chip_plic_all_irqs_20.590156483
Short name	T230
Test name
Test status
Simulation time	4108690594 ps
CPU time	779.4 seconds
Started	Aug 14 05:53:09 PM PDT 24
Finished	Aug 14 06:06:09 PM PDT 24
Peak memory	610348 kb
Host	smart-37bf9fa1-310d-491a-b3eb-b9dc6aacdcd9
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=plic_all_irqs_test_20:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=590156483 -assert nopostproc +UVM_TESTNA ME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 0.chip_plic_all_irqs_20.590156483
Directory	/workspace/0.chip_plic_all_irqs_20/latest

Test location	/workspace/coverage/default/0.chip_sw_spi_device_tpm.2256443888
Short name	T59
Test name
Test status
Simulation time	3032816283 ps
CPU time	380.68 seconds
Started	Aug 14 05:50:46 PM PDT 24
Finished	Aug 14 05:57:07 PM PDT 24
Peak memory	623840 kb
Host	smart-090e1591-5638-45b7-926e-b565f543a159
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=spi_device_tpm_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2256443888 -assert nopostproc +UVM_T ESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_spi_device_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default .vdb -cm_log /dev/null -cm_name 0.chip_sw_spi_device_tpm.2256443888
Directory	/workspace/0.chip_sw_spi_device_tpm/latest

Test location	/workspace/coverage/default/0.chip_tap_straps_rma.3528392868
Short name	T792
Test name
Test status
Simulation time	6364753133 ps
CPU time	549.64 seconds
Started	Aug 14 05:50:42 PM PDT 24
Finished	Aug 14 05:59:52 PM PDT 24
Peak memory	625624 kb
Host	smart-b1dfc027-6bac-460a-93f2-d6e33216ca61
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +sw_build_device=sim_dv +sw_images=example_test_from_rom:0:test_in_rom:new_rules +cdc_instrumentation _enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3528392868 -as sert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_tap_straps_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/c overage/default.vdb -cm_log /dev/null -cm_name 0.chip_tap_straps_rma.3528392868
Directory	/workspace/0.chip_tap_straps_rma/latest

Test location	/workspace/coverage/default/1.chip_sw_gpio.4057735088
Short name	T47
Test name
Test status
Simulation time	3223891008 ps
CPU time	423.57 seconds
Started	Aug 14 05:51:12 PM PDT 24
Finished	Aug 14 05:58:16 PM PDT 24
Peak memory	610712 kb
Host	smart-cf7cf68a-a3a8-45df-89ea-183a8a6cf415
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=gpio_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4057735088 -assert nopostproc +UVM_TESTNAME=chip_bas e_test +UVM_TEST_SEQ=chip_sw_gpio_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm _name 1.chip_sw_gpio.4057735088
Directory	/workspace/1.chip_sw_gpio/latest

Test location	/workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_slow_dev.1807164538
Short name	T73
Test name
Test status
Simulation time	4698996256 ps
CPU time	665.23 seconds
Started	Aug 14 05:51:05 PM PDT 24
Finished	Aug 14 06:02:12 PM PDT 24
Peak memory	614904 kb
Host	smart-f42b49b5-34a1-4eef-9dde-3da43a5e1526
User	root
Command	/workspace/default/simv +chip_clock_source=ChipClockSourceExternal48Mhz +calibrate_usb_clk=1 +src_dec_state=DecLcStDev +sw_build_device=sim_dv +sw_ima ges=clkmgr_external_clk_src_for_sw_slow_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1807164538 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ =chip_sw_lc_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_c lkmgr_external_clk_src_for_sw_slow_dev.1807164538
Directory	/workspace/0.chip_sw_clkmgr_external_clk_src_for_sw_slow_dev/latest

Test location	/workspace/coverage/default/1.chip_sw_flash_rma_unlocked.3444304045
Short name	T1014
Test name
Test status
Simulation time	43107286800 ps
CPU time	4959.76 seconds
Started	Aug 14 05:49:39 PM PDT 24
Finished	Aug 14 07:12:20 PM PDT 24
Peak memory	624844 kb
Host	smart-324ad154-31ec-4bdc-9468-6b4a7b22c4de
User	root
Command	/workspace/default/simv +flash_program_latency=5 +sw_test_timeout_ns=150_000_000 +sw_build_device=sim_dv +sw_images=flash_rma_unlocked_test:0:test_in_ rom:new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t cl +ntb_random_seed=3444304045 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_flash_rma_unlocked_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_flash_rma_unlocked.3444304045
Directory	/workspace/1.chip_sw_flash_rma_unlocked/latest

Test location	/workspace/coverage/default/0.chip_sw_pwrmgr_random_sleep_all_wake_ups.3139659317
Short name	T118
Test name
Test status
Simulation time	21922523778 ps
CPU time	1573.78 seconds
Started	Aug 14 05:52:13 PM PDT 24
Finished	Aug 14 06:18:27 PM PDT 24
Peak memory	611756 kb
Host	smart-a4924f6e-9171-4ea9-aae7-8db6567fa208
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=18_000_000 +do_random=1 +sw_build_device=sim_dv +sw_images=pwrmgr_random_sleep_all_wake_ups:1:new_rules,te st_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n tb_random_seed=3139659317 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_pwrmgr_deep_sleep_all_wake_ups_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_pwrmgr_random_sleep_all_wake_ups.3139659317
Directory	/workspace/0.chip_sw_pwrmgr_random_sleep_all_wake_ups/latest

Test location	/workspace/coverage/default/0.chip_jtag_mem_access.2235357278
Short name	T189
Test name
Test status
Simulation time	14306560120 ps
CPU time	1669.01 seconds
Started	Aug 14 05:39:57 PM PDT 24
Finished	Aug 14 06:07:46 PM PDT 24
Peak memory	608352 kb
Host	smart-765aeed9-d6c7-44e0-8f5d-3d1ebb554ea4
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2235357278 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_jtag_ mem_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_jtag_mem_access.2 235357278
Directory	/workspace/0.chip_jtag_mem_access/latest

Test location	/workspace/coverage/default/0.chip_sw_usbdev_aon_pullup.3556338891
Short name	T98
Test name
Test status
Simulation time	3997202260 ps
CPU time	535.59 seconds
Started	Aug 14 05:46:51 PM PDT 24
Finished	Aug 14 05:55:47 PM PDT 24
Peak memory	610532 kb
Host	smart-08d00d5f-756c-4932-b3dd-e6c32b2c8dcd
User	root
Command	/workspace/default/simv +uart_idx=0 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=usbdev_aon_pullup_test:1:new_rules,test_rom:0 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=355633 8891 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_usbdev_dpi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_usbdev_aon_pullup.3556338891
Directory	/workspace/0.chip_sw_usbdev_aon_pullup/latest

Test location	/workspace/coverage/default/0.chip_sw_rv_dm_access_after_escalation_reset.989269666
Short name	T434
Test name
Test status
Simulation time	4863309151 ps
CPU time	595.95 seconds
Started	Aug 14 05:51:45 PM PDT 24
Finished	Aug 14 06:01:42 PM PDT 24
Peak memory	625156 kb
Host	smart-cbb5cd05-64ce-4413-a720-5e8d154b063a
User	root
Command	/workspace/default/simv +use_jtag_dmi=1 +sw_build_device=sim_dv +sw_images=alert_handler_escalation_test:1:new_rules,test_rom:0 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=989269666 -asser t nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rv_dm_access_after_escalation_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_rv_dm_access_after_escalation_reset.989269666
Directory	/workspace/0.chip_sw_rv_dm_access_after_escalation_reset/latest

Test location	/workspace/coverage/default/0.chip_sw_uart_tx_rx_idx2.3553744870
Short name	T315
Test name
Test status
Simulation time	4418322862 ps
CPU time	695.59 seconds
Started	Aug 14 05:47:02 PM PDT 24
Finished	Aug 14 05:58:39 PM PDT 24
Peak memory	624680 kb
Host	smart-c332e4d3-37a7-4665-8412-8d667b530463
User	root
Command	/workspace/default/simv +uart_idx=2 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3553744870 -a ssert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ce/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_uart_tx_rx_idx2.3553744870
Directory	/workspace/0.chip_sw_uart_tx_rx_idx2/latest

Test location	/workspace/coverage/default/0.chip_sw_pwrmgr_normal_sleep_all_reset_reqs.3879276493
Short name	T163
Test name
Test status
Simulation time	10581496860 ps
CPU time	1239.58 seconds
Started	Aug 14 05:48:25 PM PDT 24
Finished	Aug 14 06:09:05 PM PDT 24
Peak memory	612240 kb
Host	smart-953312ea-2210-4fb4-addf-2ce38ea2c475
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_normal_sleep_all_reset_reqs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3879276493 -assert nop ostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_deep_sleep_all_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_pwrmgr_normal_sleep_all_reset_reqs.3879276493
Directory	/workspace/0.chip_sw_pwrmgr_normal_sleep_all_reset_reqs/latest

Test location	/workspace/coverage/default/1.chip_sw_uart_tx_rx.1956427370
Short name	T746
Test name
Test status
Simulation time	4656469742 ps
CPU time	681.91 seconds
Started	Aug 14 05:50:48 PM PDT 24
Finished	Aug 14 06:02:10 PM PDT 24
Peak memory	624616 kb
Host	smart-2d466018-2bfc-49ad-a98b-0df4baf90701
User	root
Command	/workspace/default/simv +uart_idx=0 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1956427370 -a ssert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ce/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_uart_tx_rx.1956427370
Directory	/workspace/1.chip_sw_uart_tx_rx/latest

Test location	/workspace/coverage/default/0.chip_sw_otp_ctrl_vendor_test_csr_access.1003312567
Short name	T205
Test name
Test status
Simulation time	3634519844 ps
CPU time	360.27 seconds
Started	Aug 14 05:50:10 PM PDT 24
Finished	Aug 14 05:56:10 PM PDT 24
Peak memory	623436 kb
Host	smart-b602482f-8911-4f4c-9ede-a130433c370f
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=otp_ctrl_vendor_test_csr_access_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1003312567 -assert nopost proc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_otp_ctrl_vendor_test_csr_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_otp_ctrl_vendor_test_csr_access.1003312567
Directory	/workspace/0.chip_sw_otp_ctrl_vendor_test_csr_access/latest

Test location	/workspace/coverage/default/1.chip_sw_keymgr_key_derivation.2709524342
Short name	T5
Test name
Test status
Simulation time	9404222684 ps
CPU time	1941.96 seconds
Started	Aug 14 05:52:50 PM PDT 24
Finished	Aug 14 06:25:12 PM PDT 24
Peak memory	617140 kb
Host	smart-678785b2-3ed8-4eaf-b3d4-b8382e720daa
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=20_000_000 +sw_build_device=sim_dv +sw_images=keymgr_key_derivation_test:1:new_rules,test_rom:0 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2709 524342 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_keymgr_key_derivation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_keymgr_key_derivation.2709524342
Directory	/workspace/1.chip_sw_keymgr_key_derivation/latest

Test location	/workspace/coverage/default/0.chip_sw_flash_ctrl_ops_jitter_en.3701626105
Short name	T24
Test name
Test status
Simulation time	4878737484 ps
CPU time	455.98 seconds
Started	Aug 14 05:46:51 PM PDT 24
Finished	Aug 14 05:54:27 PM PDT 24
Peak memory	610684 kb
Host	smart-68bc71fe-4144-4013-ad8a-139e0563ba01
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=50_000_000 +en_jitter=1 +sw_build_device=sim_dv +sw_images=flash_ctrl_ops_test:1:new_rules,test_rom:0 +cdc _instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see d=3701626105 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_flash_ctrl_ops_jitter_en.3701626105
Directory	/workspace/0.chip_sw_flash_ctrl_ops_jitter_en/latest

Test location	/workspace/coverage/default/0.chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up.4117052021
Short name	T388
Test name
Test status
Simulation time	5338615990 ps
CPU time	484.34 seconds
Started	Aug 14 05:49:55 PM PDT 24
Finished	Aug 14 05:58:00 PM PDT 24
Peak memory	611736 kb
Host	smart-321a3773-0c82-493b-9cd0-2d26d098e93c
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=18_000_000 +do_random=1 +sw_build_device=sim_dv +sw_images=pwrmgr_sensor_ctrl_deep_sleep_wake_up:1:new_rul es,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t cl +ntb_random_seed=4117052021 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_pwrmgr_sensor_ctrl_deep_s leep_wake_up.4117052021
Directory	/workspace/0.chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up/latest

Test location	/workspace/coverage/default/1.chip_sw_i2c_host_tx_rx_idx1.2613472561
Short name	T237
Test name
Test status
Simulation time	4348219254 ps
CPU time	661.35 seconds
Started	Aug 14 05:51:34 PM PDT 24
Finished	Aug 14 06:02:35 PM PDT 24
Peak memory	610420 kb
Host	smart-e0013154-c514-458a-aeb9-205d09aebb8d
User	root
Command	/workspace/default/simv +i2c_idx=1 +sw_build_device=sim_dv +sw_images=i2c_host_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2613472561 -assert nopostproc + UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_i2c_host_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de fault.vdb -cm_log /dev/null -cm_name 1.chip_sw_i2c_host_tx_rx_idx1.2613472561
Directory	/workspace/1.chip_sw_i2c_host_tx_rx_idx1/latest

Test location	/workspace/coverage/default/1.chip_sw_pwrmgr_lowpower_cancel.3644681515
Short name	T364
Test name
Test status
Simulation time	3917750016 ps
CPU time	444.18 seconds
Started	Aug 14 05:51:58 PM PDT 24
Finished	Aug 14 05:59:23 PM PDT 24
Peak memory	610620 kb
Host	smart-aebc06f7-4ae4-4080-aca3-58b0540e842f
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_lowpower_cancel_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3644681515 -assert nopostproc +UVM _TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm _log /dev/null -cm_name 1.chip_sw_pwrmgr_lowpower_cancel.3644681515
Directory	/workspace/1.chip_sw_pwrmgr_lowpower_cancel/latest

Test location	/workspace/coverage/default/1.chip_sw_rstmgr_alert_info.2868217354
Short name	T175
Test name
Test status
Simulation time	14366776328 ps
CPU time	1660.78 seconds
Started	Aug 14 05:54:45 PM PDT 24
Finished	Aug 14 06:22:27 PM PDT 24
Peak memory	611600 kb
Host	smart-f76f325f-a60e-440f-a86d-90c4d500b5d3
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=30_000_000 +en_scb_tl_err_chk=0 +sw_build_device=sim_dv +sw_images=rstmgr_alert_info_test:1:new_rules,test _rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb _random_seed=2868217354 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_rstmgr_alert_info.2868217354
Directory	/workspace/1.chip_sw_rstmgr_alert_info/latest

Test location	/workspace/coverage/default/0.chip_sw_adc_ctrl_sleep_debug_cable_wakeup.3480070814
Short name	T707
Test name
Test status
Simulation time	18426568896 ps
CPU time	560.64 seconds
Started	Aug 14 05:47:12 PM PDT 24
Finished	Aug 14 05:56:34 PM PDT 24
Peak memory	624620 kb
Host	smart-cdd11e4a-c2d7-48b3-b447-6dbf514644d0
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=adc_ctrl_sleep_debug_cable_wakeup_test:1:new_rules,test_rom: 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand om_seed=3480070814 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_adc_ctrl_sleep_debug_cable_wakeup_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_adc_ctrl_sleep_debug_cable_wakeup.3480070814
Directory	/workspace/0.chip_sw_adc_ctrl_sleep_debug_cable_wakeup/latest

Test location	/workspace/coverage/default/0.chip_sw_aon_timer_sleep_wdog_sleep_pause.2102956524
Short name	T873
Test name
Test status
Simulation time	7610573920 ps
CPU time	380.44 seconds
Started	Aug 14 05:48:05 PM PDT 24
Finished	Aug 14 05:54:26 PM PDT 24
Peak memory	611244 kb
Host	smart-1b6a28bd-132f-426a-b3c7-6b82af8b99f4
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=aon_timer_sleep_wdog_sleep_pause_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=2102956524 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_aon_timer_sleep_wdog_sleep_pause.2102956524
Directory	/workspace/0.chip_sw_aon_timer_sleep_wdog_sleep_pause/latest

Test location	/workspace/coverage/default/0.chip_sw_ast_clk_outputs.2106799875
Short name	T473
Test name
Test status
Simulation time	8125366424 ps
CPU time	1072.36 seconds
Started	Aug 14 05:52:12 PM PDT 24
Finished	Aug 14 06:10:05 PM PDT 24
Peak memory	617016 kb
Host	smart-38b65d56-21f2-4f3d-9339-ed096ef4b043
User	root
Command	/workspace/default/simv +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=ast_clk_outs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled= 1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2106799875 -assert nopo stproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_ast_clk_outputs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co verage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_ast_clk_outputs.2106799875
Directory	/workspace/0.chip_sw_ast_clk_outputs/latest

Test location	/workspace/coverage/default/0.chip_sw_lc_walkthrough_prod.902988745
Short name	T211
Test name
Test status
Simulation time	47088046834 ps
CPU time	5675.98 seconds
Started	Aug 14 05:51:01 PM PDT 24
Finished	Aug 14 07:25:39 PM PDT 24
Peak memory	621124 kb
Host	smart-112a630b-7687-430e-88ac-f5711a9d82a2
User	root
Command	/workspace/default/simv +flash_program_latency=5 +use_otp_image=OtpTypeLcStRaw +dest_dec_state=DecLcStProd +sw_test_timeout_ns=200_000_000 +sw_build_d evice=sim_dv +sw_images=lc_walkthrough_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=902988745 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=c hip_sw_lc_walkthrough_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip _sw_lc_walkthrough_prod.902988745
Directory	/workspace/0.chip_sw_lc_walkthrough_prod/latest

Test location	/workspace/coverage/default/0.chip_sw_pwrmgr_full_aon_reset.953606827
Short name	T839
Test name
Test status
Simulation time	7651578095 ps
CPU time	667.57 seconds
Started	Aug 14 05:47:47 PM PDT 24
Finished	Aug 14 05:58:55 PM PDT 24
Peak memory	610528 kb
Host	smart-15b6d090-7578-4c33-ad62-11597da7f076
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=rstmgr_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=953606827 -assert nopostproc +UVM_TESTNAME=ch ip_base_test +UVM_TEST_SEQ=chip_sw_full_aon_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l og /dev/null -cm_name 0.chip_sw_pwrmgr_full_aon_reset.953606827
Directory	/workspace/0.chip_sw_pwrmgr_full_aon_reset/latest

Test location	/workspace/coverage/default/2.chip_tap_straps_dev.4197498827
Short name	T435
Test name
Test status
Simulation time	12042032231 ps
CPU time	1136.77 seconds
Started	Aug 14 06:04:34 PM PDT 24
Finished	Aug 14 06:23:31 PM PDT 24
Peak memory	633856 kb
Host	smart-95309586-a150-4958-8590-0017847aea46
User	root
Command	/workspace/default/simv +use_otp_image=OtpTypeLcStDev +create_jtag_riscv_map=1 +sw_build_device=sim_dv +sw_images=example_test_from_rom:0:test_in_rom: new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=4197498827 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_tap_straps_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_tap_straps_dev.4197498827
Directory	/workspace/2.chip_tap_straps_dev/latest

Test location	/workspace/coverage/default/0.chip_sw_entropy_src_csrng.2206941932
Short name	T356
Test name
Test status
Simulation time	7325500244 ps
CPU time	1970.46 seconds
Started	Aug 14 05:47:23 PM PDT 24
Finished	Aug 14 06:20:14 PM PDT 24
Peak memory	610704 kb
Host	smart-c0ab6b27-3de0-4d81-a951-394ccfbbb3ae
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=50_000_000 +rng_srate_value_min=15 +rng_srate_value_max=30 +sw_build_device=sim_dv +sw_images=entropy_src_ csrng_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2206941932 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_entropy_src_csrng.2206941932
Directory	/workspace/0.chip_sw_entropy_src_csrng/latest

Test location	/workspace/coverage/default/0.chip_sw_gpio.1118647925
Short name	T48
Test name
Test status
Simulation time	3633598297 ps
CPU time	450.31 seconds
Started	Aug 14 05:46:57 PM PDT 24
Finished	Aug 14 05:54:27 PM PDT 24
Peak memory	609848 kb
Host	smart-b47bafbf-fd6c-4ddd-9b43-1936223f5768
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=gpio_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1118647925 -assert nopostproc +UVM_TESTNAME=chip_bas e_test +UVM_TEST_SEQ=chip_sw_gpio_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm _name 0.chip_sw_gpio.1118647925
Directory	/workspace/0.chip_sw_gpio/latest

Test location	/workspace/coverage/default/2.chip_plic_all_irqs_10.1929498433
Short name	T160
Test name
Test status
Simulation time	3617045842 ps
CPU time	489.85 seconds
Started	Aug 14 06:05:24 PM PDT 24
Finished	Aug 14 06:13:34 PM PDT 24
Peak memory	610572 kb
Host	smart-97853d19-0556-4818-b027-f392cbaeb11a
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=plic_all_irqs_test_10:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1929498433 -assert nopostproc +UVM_TESTN AME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log / dev/null -cm_name 2.chip_plic_all_irqs_10.1929498433
Directory	/workspace/2.chip_plic_all_irqs_10/latest

Test location	/workspace/coverage/default/0.chip_sw_spi_device_pass_through_collision.194454043
Short name	T158
Test name
Test status
Simulation time	5285688700 ps
CPU time	740.82 seconds
Started	Aug 14 05:49:34 PM PDT 24
Finished	Aug 14 06:01:55 PM PDT 24
Peak memory	625232 kb
Host	smart-ce9f83c5-1f10-426f-9de7-b845ac86cfaf
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=spi_passthrough_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=194454043 -assert nopostproc +UVM_TESTNAM E=chip_base_test +UVM_TEST_SEQ=chip_sw_spi_passthrough_collision_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de fault.vdb -cm_log /dev/null -cm_name 0.chip_sw_spi_device_pass_through_collision.194454043
Directory	/workspace/0.chip_sw_spi_device_pass_through_collision/latest

Test location	/workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0.2611177058
Short name	T265
Test name
Test status
Simulation time	18156077246 ps
CPU time	5596.48 seconds
Started	Aug 14 05:55:06 PM PDT 24
Finished	Aug 14 07:28:23 PM PDT 24
Peak memory	609964 kb
Host	smart-ecc7f51c-b5a6-4ea9-853a-ce6617e7b4e4
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=410_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_corrupted:1: ot_flash_binary:signed:fake_ecdsa_prod_key_0,empty_test_slot_b_fake_ecdsa_prod_key_0:2:ot_flash_binary,otp_img_boot_policy_valid_test_unlocked0:4, mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2611177058 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0.2611177058
Directory	/workspace/0.rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0/latest

Test location	/workspace/coverage/default/0.rom_raw_unlock.3121771732
Short name	T10
Test name
Test status
Simulation time	3818331004 ps
CPU time	293.3 seconds
Started	Aug 14 05:48:48 PM PDT 24
Finished	Aug 14 05:53:42 PM PDT 24
Peak memory	620360 kb
Host	smart-0d3da703-cc47-44f4-9ec7-d95d75d7c7cf
User	root
Command	/workspace/default/simv +do_creator_sw_cfg_ast_cfg=0 +sw_test_timeout_ns=200_000_000 +use_otp_image=OtpTypeLcStRaw +chip_clock_source=ChipClockSourceE xternal48Mhz +rom_prod_mode=1 +use_jtag_dmi=1 +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_test_key_0:1:ot_flash_binary,mask_ro m:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=3121771732 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_raw_unlock_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_raw_unlock.3121771732
Directory	/workspace/0.rom_raw_unlock/latest

Test location	/workspace/coverage/default/0.chip_sw_plic_sw_irq.1675049966
Short name	T382
Test name
Test status
Simulation time	2202385600 ps
CPU time	295.69 seconds
Started	Aug 14 05:52:17 PM PDT 24
Finished	Aug 14 05:57:13 PM PDT 24
Peak memory	609784 kb
Host	smart-572ce0c6-e993-4a86-be17-063ab68be3f1
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=plic_sw_irq_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1675049966 -assert nopostproc +UVM_TESTNAME=c hip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n ull -cm_name 0.chip_sw_plic_sw_irq.1675049966
Directory	/workspace/0.chip_sw_plic_sw_irq/latest

Test location	/workspace/coverage/default/0.chip_sw_spi_host_tx_rx.2742146
Short name	T53
Test name
Test status
Simulation time	2778016736 ps
CPU time	287.48 seconds
Started	Aug 14 05:46:57 PM PDT 24
Finished	Aug 14 05:51:45 PM PDT 24
Peak memory	610416 kb
Host	smart-ef9bd37c-6a2f-4205-8293-f4cef56ff62c
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=spi_host_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2742146 -assert nopostproc +UVM_TESTNAME=c hip_base_test +UVM_TEST_SEQ=chip_sw_spi_host_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_ log /dev/null -cm_name 0.chip_sw_spi_host_tx_rx.2742146
Directory	/workspace/0.chip_sw_spi_host_tx_rx/latest

Test location	/workspace/coverage/default/0.chip_sw_lc_ctrl_program_error.1154042599
Short name	T213
Test name
Test status
Simulation time	4715942576 ps
CPU time	472.3 seconds
Started	Aug 14 05:52:00 PM PDT 24
Finished	Aug 14 05:59:52 PM PDT 24
Peak memory	611736 kb
Host	smart-324a59b1-14e6-4528-a552-42a37e0b795d
User	root
Command	/workspace/default/simv +en_scb=0 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=lc_ctrl_program_error:1:new_rules,test_rom:0 + cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_ seed=1154042599 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_program_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_lc_ctrl_program_error.1154042599
Directory	/workspace/0.chip_sw_lc_ctrl_program_error/latest

Test location	/workspace/coverage/default/0.chip_sw_pwrmgr_deep_sleep_power_glitch_reset.2611376067
Short name	T712
Test name
Test status
Simulation time	7381659314 ps
CPU time	518.85 seconds
Started	Aug 14 05:48:57 PM PDT 24
Finished	Aug 14 05:57:38 PM PDT 24
Peak memory	618328 kb
Host	smart-851e600b-e579-4797-9da2-bd97c66f0067
User	root
Command	/workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=pwrmgr_deep_sleep_power_glitch_test:1:new_rules,test_rom :0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=2611376067 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_deep_power_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_pwrmgr_deep_sleep_power_glitch_reset.2611376067
Directory	/workspace/0.chip_sw_pwrmgr_deep_sleep_power_glitch_reset/latest

Test location	/workspace/coverage/default/0.chip_sw_rv_dm_ndm_reset_req_when_cpu_halted.2828273423
Short name	T318
Test name
Test status
Simulation time	4123661362 ps
CPU time	466.47 seconds
Started	Aug 14 05:49:47 PM PDT 24
Finished	Aug 14 05:57:34 PM PDT 24
Peak memory	620620 kb
Host	smart-6df97b62-23cc-4145-abdf-1647f2090c23
User	root
Command	/workspace/default/simv +use_jtag_dmi=1 +sw_build_device=sim_dv +sw_images=rv_dm_ndm_reset_req_when_cpu_halted_rma:1:new_rules,test_rom:0 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=282827 3423 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rv_dm_ndm_reset_when_cpu_halted_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_rv_dm_ndm_reset_req_when_cpu_halted.2828273423
Directory	/workspace/0.chip_sw_rv_dm_ndm_reset_req_when_cpu_halted/latest

Test location	/workspace/coverage/default/0.chip_sw_sram_ctrl_execution_main.1575215601
Short name	T195
Test name
Test status
Simulation time	6878816837 ps
CPU time	744.63 seconds
Started	Aug 14 05:48:54 PM PDT 24
Finished	Aug 14 06:01:19 PM PDT 24
Peak memory	611200 kb
Host	smart-0bfd01b4-7e48-41c7-a35e-97273bf9a1de
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=sram_ctrl_execution_main_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1575215601 -assert nopostproc +U VM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sram_ctrl_execution_main_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co verage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_sram_ctrl_execution_main.1575215601
Directory	/workspace/0.chip_sw_sram_ctrl_execution_main/latest

Test location	/workspace/coverage/default/2.chip_sw_otp_ctrl_vendor_test_csr_access.2727091871
Short name	T204
Test name
Test status
Simulation time	2647693396 ps
CPU time	274.02 seconds
Started	Aug 14 06:00:11 PM PDT 24
Finished	Aug 14 06:04:45 PM PDT 24
Peak memory	622372 kb
Host	smart-6b2c7394-84a8-4a76-b928-df0ec64240b3
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=otp_ctrl_vendor_test_csr_access_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2727091871 -assert nopost proc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_otp_ctrl_vendor_test_csr_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_otp_ctrl_vendor_test_csr_access.2727091871
Directory	/workspace/2.chip_sw_otp_ctrl_vendor_test_csr_access/latest

Test location	/workspace/coverage/default/0.chip_sw_i2c_device_tx_rx.3320299142
Short name	T236
Test name
Test status
Simulation time	4699575312 ps
CPU time	701.08 seconds
Started	Aug 14 05:49:47 PM PDT 24
Finished	Aug 14 06:01:31 PM PDT 24
Peak memory	610400 kb
Host	smart-33d4b659-404f-4d59-bff8-f08d7223b5c2
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=i2c_device_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3320299142 -assert nopostproc +UVM_TESTN AME=chip_base_test +UVM_TEST_SEQ=chip_sw_i2c_device_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v db -cm_log /dev/null -cm_name 0.chip_sw_i2c_device_tx_rx.3320299142
Directory	/workspace/0.chip_sw_i2c_device_tx_rx/latest

Test location	/workspace/coverage/default/0.chip_sw_i2c_host_tx_rx_idx2.3596606486
Short name	T114
Test name
Test status
Simulation time	5012202128 ps
CPU time	823.79 seconds
Started	Aug 14 05:47:51 PM PDT 24
Finished	Aug 14 06:01:36 PM PDT 24
Peak memory	611024 kb
Host	smart-e3c658ac-9136-4245-9baa-ed99a779c7a3
User	root
Command	/workspace/default/simv +i2c_idx=2 +sw_build_device=sim_dv +sw_images=i2c_host_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3596606486 -assert nopostproc + UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_i2c_host_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de fault.vdb -cm_log /dev/null -cm_name 0.chip_sw_i2c_host_tx_rx_idx2.3596606486
Directory	/workspace/0.chip_sw_i2c_host_tx_rx_idx2/latest

Test location	/workspace/coverage/default/0.chip_sw_pwrmgr_lowpower_cancel.3117038579
Short name	T365
Test name
Test status
Simulation time	3476133940 ps
CPU time	457.86 seconds
Started	Aug 14 05:47:37 PM PDT 24
Finished	Aug 14 05:55:15 PM PDT 24
Peak memory	610592 kb
Host	smart-c5418f12-8d64-4db6-bb77-cffdc812a358
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_lowpower_cancel_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3117038579 -assert nopostproc +UVM _TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm _log /dev/null -cm_name 0.chip_sw_pwrmgr_lowpower_cancel.3117038579
Directory	/workspace/0.chip_sw_pwrmgr_lowpower_cancel/latest

Test location	/workspace/coverage/default/0.chip_sw_rstmgr_alert_info.2330959948
Short name	T354
Test name
Test status
Simulation time	8970667738 ps
CPU time	1595.59 seconds
Started	Aug 14 05:52:37 PM PDT 24
Finished	Aug 14 06:19:13 PM PDT 24
Peak memory	611672 kb
Host	smart-d32831f6-c6e8-42c2-9e71-44fa3d048d58
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=30_000_000 +en_scb_tl_err_chk=0 +sw_build_device=sim_dv +sw_images=rstmgr_alert_info_test:1:new_rules,test _rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb _random_seed=2330959948 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_rstmgr_alert_info.2330959948
Directory	/workspace/0.chip_sw_rstmgr_alert_info/latest

Test location	/workspace/coverage/default/0.chip_sw_rv_core_ibex_nmi_irq.1106516516
Short name	T323
Test name
Test status
Simulation time	4498563126 ps
CPU time	833.31 seconds
Started	Aug 14 05:51:02 PM PDT 24
Finished	Aug 14 06:04:56 PM PDT 24
Peak memory	610876 kb
Host	smart-6fad28a8-2e29-4588-a6ae-cee6d764c4a1
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=10_000_000 +sw_build_device=sim_dv +sw_images=rv_core_ibex_nmi_irq_test:1:new_rules,test_rom:0 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11065 16516 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_rv_core_ibex_nmi_irq.1106516516
Directory	/workspace/0.chip_sw_rv_core_ibex_nmi_irq/latest

Test location	/workspace/coverage/default/0.chip_sw_aes_enc.2481708327
Short name	T573
Test name
Test status
Simulation time	3078758648 ps
CPU time	244.66 seconds
Started	Aug 14 05:47:53 PM PDT 24
Finished	Aug 14 05:51:58 PM PDT 24
Peak memory	610124 kb
Host	smart-d3a7a7fd-e309-4aba-8540-f166f752be6a
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=22_000_000 +sw_build_device=sim_dv +sw_images=aes_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2481708327 -asser t nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag e/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_aes_enc.2481708327
Directory	/workspace/0.chip_sw_aes_enc/latest

Test location	/workspace/coverage/default/0.chip_sw_edn_boot_mode.3978957145
Short name	T404
Test name
Test status
Simulation time	3490471948 ps
CPU time	626.03 seconds
Started	Aug 14 05:51:11 PM PDT 24
Finished	Aug 14 06:01:37 PM PDT 24
Peak memory	610740 kb
Host	smart-4e384f5d-f0ea-47cf-98c4-f05e4c11b114
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=18_000_000 +rng_srate_value=5 +accelerate_cold_power_up_time=3 +accelerate_regulators_power_up_time=2 +sw_ build_device=sim_dv +sw_images=edn_boot_mode:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3978957145 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ =chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_edn_ boot_mode.3978957145
Directory	/workspace/0.chip_sw_edn_boot_mode/latest

Test location	/workspace/coverage/default/0.chip_sw_keymgr_sideload_aes.197235630
Short name	T333
Test name
Test status
Simulation time	8745219208 ps
CPU time	2046.21 seconds
Started	Aug 14 05:49:23 PM PDT 24
Finished	Aug 14 06:23:31 PM PDT 24
Peak memory	612028 kb
Host	smart-2c8d282a-c51f-480b-b69a-1daadc7a64ab
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=20_000_000 +sw_build_device=sim_dv +sw_images=keymgr_sideload_aes_test:1:new_rules,test_rom:0 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=197235 630 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_keymgr_sideload_aes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_keymgr_sideload_aes.197235630
Directory	/workspace/0.chip_sw_keymgr_sideload_aes/latest

Test location	/workspace/coverage/default/0.chip_sw_keymgr_sideload_otbn.2331717883
Short name	T335
Test name
Test status
Simulation time	13964403470 ps
CPU time	3358.39 seconds
Started	Aug 14 05:51:07 PM PDT 24
Finished	Aug 14 06:47:06 PM PDT 24
Peak memory	611364 kb
Host	smart-46d50d1c-a1eb-441a-af09-912ae2b273a8
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=20_000_000 +sw_build_device=sim_dv +sw_images=keymgr_sideload_otbn_test:1:new_rules,test_rom:0 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23317 17883 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_keymgr_sideload_otbn.2331717883
Directory	/workspace/0.chip_sw_keymgr_sideload_otbn/latest

Test location	/workspace/coverage/default/0.chip_sw_otbn_ecdsa_op_irq_jitter_en.3074878202
Short name	T139
Test name
Test status
Simulation time	18596151705 ps
CPU time	3378.68 seconds
Started	Aug 14 05:49:09 PM PDT 24
Finished	Aug 14 06:45:28 PM PDT 24
Peak memory	611108 kb
Host	smart-cd93bb80-0918-4487-8cf2-2f55d09953fb
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=33_000_000 +rng_srate_value=30 +en_jitter=1 +sw_build_device=sim_dv +sw_images=otbn_ecdsa_op_irq_test:1:ne w_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/ sim.tcl +ntb_random_seed=3074878202 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tg l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_otbn_ecdsa_op_irq_jitter_en.3074878202
Directory	/workspace/0.chip_sw_otbn_ecdsa_op_irq_jitter_en/latest

Test location	/workspace/coverage/default/0.chip_sw_sleep_sram_ret_contents_scramble.3688431678
Short name	T218
Test name
Test status
Simulation time	6645586056 ps
CPU time	667.27 seconds
Started	Aug 14 05:53:09 PM PDT 24
Finished	Aug 14 06:04:16 PM PDT 24
Peak memory	611380 kb
Host	smart-807c3d7a-9299-417b-89c4-e19f21304737
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=20_000_000 +en_scb_tl_err_chk=0 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=sram _ctrl_sleep_sram_ret_contents_scramble_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3688431678 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ= chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_sleep _sram_ret_contents_scramble.3688431678
Directory	/workspace/0.chip_sw_sleep_sram_ret_contents_scramble/latest

Test location	/workspace/coverage/default/2.chip_sw_rv_core_ibex_lockstep_glitch.2030488802
Short name	T260
Test name
Test status
Simulation time	2657200432 ps
CPU time	156.47 seconds
Started	Aug 14 06:05:25 PM PDT 24
Finished	Aug 14 06:08:02 PM PDT 24
Peak memory	616184 kb
Host	smart-478d6cb9-a267-438b-bde8-375cd07a840e
User	root
Command	/workspace/default/simv +disable_assert_final_checks +sw_build_device=sim_dv +sw_images=aes_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2030488802 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rv_core_ibex_lockstep_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_rv_core_ibex_lockstep_glitch.2030488802
Directory	/workspace/2.chip_sw_rv_core_ibex_lockstep_glitch/latest

Test location	/workspace/coverage/default/0.chip_sw_csrng_fuse_en_sw_app_read_test.952620702
Short name	T226
Test name
Test status
Simulation time	4552794504 ps
CPU time	630.98 seconds
Started	Aug 14 05:52:05 PM PDT 24
Finished	Aug 14 06:02:37 PM PDT 24
Peak memory	611500 kb
Host	smart-afce2019-0bf9-45c9-a1fb-5ee7be4ec209
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=15_000_000 +sw_build_device=sim_dv +sw_images=csrng_fuse_en_sw_app_read:1:new_rules,test_rom:0 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=95262 0702 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_entropy_src_fuse_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_csrng_fuse_en_sw_app_read_test.952620702
Directory	/workspace/0.chip_sw_csrng_fuse_en_sw_app_read_test/latest

Test location	/workspace/coverage/default/0.chip_rv_dm_ndm_reset_req.566871522
Short name	T8
Test name
Test status
Simulation time	4339776790 ps
CPU time	460.19 seconds
Started	Aug 14 05:51:50 PM PDT 24
Finished	Aug 14 05:59:31 PM PDT 24
Peak memory	620132 kb
Host	smart-596f17ec-e54a-43d9-8f93-67aeb192f09e
User	root
Command	/workspace/default/simv +en_scb_tl_err_chk=0 +use_jtag_dmi=1 +sw_build_device=sim_dv +sw_images=rv_dm_ndm_reset_req_rma:1:new_rules,test_rom:0 +cdc_in strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=5 66871522 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_rv_dm_ndm_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_rv_dm_ndm_reset_req.566871522
Directory	/workspace/0.chip_rv_dm_ndm_reset_req/latest

Test location	/workspace/coverage/default/0.chip_sival_flash_info_access.900626031
Short name	T209
Test name
Test status
Simulation time	2404605496 ps
CPU time	304.69 seconds
Started	Aug 14 05:50:29 PM PDT 24
Finished	Aug 14 05:55:34 PM PDT 24
Peak memory	610680 kb
Host	smart-ddb2c8d4-dc89-4c7e-a057-faab1d6e0206
User	root
Command	/workspace/default/simv +use_otp_image=OtpTypeLcStTestUnlocked0 +sw_build_device=sim_dv +sw_images=flash_ctrl_info_access_lc:1:new_rules,test_rom:0 +c dc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_s eed=900626031 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sival_flash_info_access.900626031
Directory	/workspace/0.chip_sival_flash_info_access/latest

Test location	/workspace/coverage/default/0.chip_sw_aes_enc_jitter_en.196821130
Short name	T414
Test name
Test status
Simulation time	3302923919 ps
CPU time	377.64 seconds
Started	Aug 14 05:48:25 PM PDT 24
Finished	Aug 14 05:54:43 PM PDT 24
Peak memory	609184 kb
Host	smart-05608700-07da-4fb0-9a2d-d07e353862de
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=26_000_000 +en_jitter=1 +sw_build_device=sim_dv +sw_images=aes_smoketest:1:new_rules,test_rom:0 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1968 21130 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_aes_enc_jitter_en.196821130
Directory	/workspace/0.chip_sw_aes_enc_jitter_en/latest

Test location	/workspace/coverage/default/0.chip_sw_aes_enc_jitter_en_reduced_freq.106116581
Short name	T182
Test name
Test status
Simulation time	3274557218 ps
CPU time	293.95 seconds
Started	Aug 14 05:52:14 PM PDT 24
Finished	Aug 14 05:57:08 PM PDT 24
Peak memory	610424 kb
Host	smart-46fde6d0-3a12-4d3b-9d5f-01e6f2124426
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=26_000_000 +en_jitter=1 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=aes_smoketest:1:new_rules, test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=106116581 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_aes_enc_jitter_en_reduced_freq.106116581
Directory	/workspace/0.chip_sw_aes_enc_jitter_en_reduced_freq/latest

Test location	/workspace/coverage/default/0.chip_sw_aes_entropy.1641961324
Short name	T901
Test name
Test status
Simulation time	2947316352 ps
CPU time	326.64 seconds
Started	Aug 14 05:51:18 PM PDT 24
Finished	Aug 14 05:56:45 PM PDT 24
Peak memory	610428 kb
Host	smart-c8a1d151-4ed1-4a93-aeb4-d6044661d757
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=15_000_000 +sw_build_device=sim_dv +sw_images=aes_entropy_test:1:new_rules,test_rom:0 +cdc_instrumentation _enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1641961324 -as sert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove rage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_aes_entropy.1641961324
Directory	/workspace/0.chip_sw_aes_entropy/latest

Test location	/workspace/coverage/default/0.chip_sw_aes_idle.2184707182
Short name	T577
Test name
Test status
Simulation time	2370001118 ps
CPU time	259.64 seconds
Started	Aug 14 05:49:39 PM PDT 24
Finished	Aug 14 05:53:59 PM PDT 24
Peak memory	609804 kb
Host	smart-f5d26bcb-f479-4bd2-b79c-452a58f6f4ed
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=25_000_000 +sw_build_device=sim_dv +sw_images=aes_idle_test:1:new_rules,test_rom:0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2184707182 -asser t nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag e/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_aes_idle.2184707182
Directory	/workspace/0.chip_sw_aes_idle/latest

Test location	/workspace/coverage/default/0.chip_sw_aes_masking_off.2388640683
Short name	T480
Test name
Test status
Simulation time	3125663940 ps
CPU time	419.12 seconds
Started	Aug 14 05:49:35 PM PDT 24
Finished	Aug 14 05:56:36 PM PDT 24
Peak memory	610392 kb
Host	smart-f7b0dfa5-c156-48e0-8728-e89bea13b69e
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=aes_masking_off_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2388640683 -assert nopostproc +UVM_TESTNA ME=chip_base_test +UVM_TEST_SEQ=chip_sw_aes_masking_off_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_aes_masking_off.2388640683
Directory	/workspace/0.chip_sw_aes_masking_off/latest

Test location	/workspace/coverage/default/0.chip_sw_aes_smoketest.2124417561
Short name	T594
Test name
Test status
Simulation time	3376623098 ps
CPU time	308.39 seconds
Started	Aug 14 05:53:04 PM PDT 24
Finished	Aug 14 05:58:13 PM PDT 24
Peak memory	610476 kb
Host	smart-35eb3a4c-0333-4a1b-ad4a-57cfafb4e1e8
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=aes_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2124417561 -assert nopostproc +UVM_TESTNAME=chip _base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_aes_smoketest.2124417561
Directory	/workspace/0.chip_sw_aes_smoketest/latest

Test location	/workspace/coverage/default/0.chip_sw_alert_handler_entropy.483366861
Short name	T23
Test name
Test status
Simulation time	3658378528 ps
CPU time	360.45 seconds
Started	Aug 14 05:51:39 PM PDT 24
Finished	Aug 14 05:57:40 PM PDT 24
Peak memory	610368 kb
Host	smart-997f01b4-6b0c-48df-8401-bf7da28dc95c
User	root
Command	/workspace/default/simv +en_scb=0 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=alert_handler_entropy_test:1:new_rules,test_ro m:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=483366861 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_alert_handler_entropy.483366861
Directory	/workspace/0.chip_sw_alert_handler_entropy/latest

Test location	/workspace/coverage/default/0.chip_sw_alert_handler_escalation.1781380768
Short name	T983
Test name
Test status
Simulation time	5664499834 ps
CPU time	427.38 seconds
Started	Aug 14 05:49:22 PM PDT 24
Finished	Aug 14 05:56:30 PM PDT 24
Peak memory	620308 kb
Host	smart-b7879c53-df71-4714-b288-0b170c00a1ff
User	root
Command	/workspace/default/simv +en_scb=0 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=alert_handler_escalation_test:1:new_rules,test _rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb _random_seed=1781380768 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_alert_handler_escalation_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_alert_handler_escalation.1781380768
Directory	/workspace/0.chip_sw_alert_handler_escalation/latest

Test location	/workspace/coverage/default/0.chip_sw_alert_handler_lpg_clkoff.2736924649
Short name	T229
Test name
Test status
Simulation time	6716269260 ps
CPU time	1600.76 seconds
Started	Aug 14 05:52:30 PM PDT 24
Finished	Aug 14 06:19:11 PM PDT 24
Peak memory	610696 kb
Host	smart-f4314382-aa89-478b-a248-df6549916cae
User	root
Command	/workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +sw_build_device=sim_dv +sw_images=alert_handler_lpg_clkoff_test:1:new_rules,test_r om:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r andom_seed=2736924649 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_alert_handler_lpg_clkoff_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_alert_handler_lpg_clkoff.2736924649
Directory	/workspace/0.chip_sw_alert_handler_lpg_clkoff/latest

Test location	/workspace/coverage/default/0.chip_sw_alert_handler_lpg_reset_toggle.2145893141
Short name	T751
Test name
Test status
Simulation time	8180311480 ps
CPU time	2065.8 seconds
Started	Aug 14 05:50:10 PM PDT 24
Finished	Aug 14 06:24:37 PM PDT 24
Peak memory	610928 kb
Host	smart-c3bfc71e-3186-4399-a190-cf79e0e7596e
User	root
Command	/workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +sw_build_device=sim_dv +sw_images=alert_handler_lpg_reset_toggle_test:1:new_rules, test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2145893141 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_alert_handler_shorten_ping_wait_cycle_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_alert_handler_lpg_reset_togg le.2145893141
Directory	/workspace/0.chip_sw_alert_handler_lpg_reset_toggle/latest

Test location	/workspace/coverage/default/0.chip_sw_alert_handler_lpg_sleep_mode_pings.3047619925
Short name	T477
Test name
Test status
Simulation time	12571187718 ps
CPU time	1347.61 seconds
Started	Aug 14 05:52:51 PM PDT 24
Finished	Aug 14 06:15:19 PM PDT 24
Peak memory	611468 kb
Host	smart-7908e78d-11f5-46d0-8e75-cf7df36abbf9
User	root
Command	/workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=alert_handler _lpg_sleep_mode_pings_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3047619925 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_alert_han dler_shorten_ping_wait_cycle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_alert_handler_lpg_sleep_mode_pings.3047619925
Directory	/workspace/0.chip_sw_alert_handler_lpg_sleep_mode_pings/latest

Test location	/workspace/coverage/default/0.chip_sw_alert_handler_ping_ok.2780322656
Short name	T892
Test name
Test status
Simulation time	7264949394 ps
CPU time	1247.02 seconds
Started	Aug 14 05:47:44 PM PDT 24
Finished	Aug 14 06:08:32 PM PDT 24
Peak memory	609700 kb
Host	smart-e0d71d86-9d8a-46e3-94fd-24721b816601
User	root
Command	/workspace/default/simv +en_scb=0 +sw_test_timeout_ns=24000000 +sw_build_device=sim_dv +sw_images=alert_handler_ping_ok_test:1:new_rules,test_rom:0 +c dc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_s eed=2780322656 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_alert_handler_ping_ok.2780322656
Directory	/workspace/0.chip_sw_alert_handler_ping_ok/latest

Test location	/workspace/coverage/default/0.chip_sw_alert_handler_ping_timeout.2884691036
Short name	T569
Test name
Test status
Simulation time	5629949464 ps
CPU time	597.3 seconds
Started	Aug 14 05:51:34 PM PDT 24
Finished	Aug 14 06:01:32 PM PDT 24
Peak memory	610804 kb
Host	smart-3a7ca2d4-ccbf-47cc-ac7f-6d0fcec77ce8
User	root
Command	/workspace/default/simv +en_scb=0 +sw_test_timeout_ns=24000000 +sw_build_device=sim_dv +sw_images=alert_handler_ping_timeout_test:1:new_rules,test_rom :0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=2884691036 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_alert_handler_ping_timeout.2884691036
Directory	/workspace/0.chip_sw_alert_handler_ping_timeout/latest

Test location	/workspace/coverage/default/0.chip_sw_alert_handler_reverse_ping_in_deep_sleep.3936279941
Short name	T831
Test name
Test status
Simulation time	255795936466 ps
CPU time	11531.1 seconds
Started	Aug 14 05:50:34 PM PDT 24
Finished	Aug 14 09:02:47 PM PDT 24
Peak memory	611604 kb
Host	smart-504feb09-7192-4274-9615-4d72c421a230
User	root
Command	/workspace/default/simv +en_scb=0 +sw_test_timeout_ns=300_000_000 +sw_build_device=sim_dv +sw_images=alert_handler_reverse_ping_in_deep_sleep_test:1:n ew_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3936279941 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_alert_handler_reverse_ping_in_deep_sleep.3936279941
Directory	/workspace/0.chip_sw_alert_handler_reverse_ping_in_deep_sleep/latest

Test location	/workspace/coverage/default/0.chip_sw_alert_test.646391053
Short name	T77
Test name
Test status
Simulation time	3105702584 ps
CPU time	308.59 seconds
Started	Aug 14 05:51:58 PM PDT 24
Finished	Aug 14 05:57:07 PM PDT 24
Peak memory	609816 kb
Host	smart-3fc526a6-302c-4abc-8fb9-749a2bbc068a
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=alert_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=646391053 -assert nopostproc +UVM_TESTNAME=chip_bas e_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm _name 0.chip_sw_alert_test.646391053
Directory	/workspace/0.chip_sw_alert_test/latest

Test location	/workspace/coverage/default/0.chip_sw_aon_timer_irq.3806139653
Short name	T922
Test name
Test status
Simulation time	3993351600 ps
CPU time	447.79 seconds
Started	Aug 14 05:47:22 PM PDT 24
Finished	Aug 14 05:54:50 PM PDT 24
Peak memory	610456 kb
Host	smart-0bbe8692-0338-4378-a866-54fb6350ea9a
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=aon_timer_irq_test:1:new_rules,test_rom:0 +cdc_instrumentati on_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3806139653 - assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co verage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_aon_timer_irq.3806139653
Directory	/workspace/0.chip_sw_aon_timer_irq/latest

Test location	/workspace/coverage/default/0.chip_sw_aon_timer_smoketest.1341877044
Short name	T780
Test name
Test status
Simulation time	2767749742 ps
CPU time	325.07 seconds
Started	Aug 14 05:49:09 PM PDT 24
Finished	Aug 14 05:54:34 PM PDT 24
Peak memory	610508 kb
Host	smart-2c9b70e5-e44c-4fa1-84b7-92b6f50e88a0
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=aon_timer_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1341877044 -assert nopostproc +UVM_TESTNAM E=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 0.chip_sw_aon_timer_smoketest.1341877044
Directory	/workspace/0.chip_sw_aon_timer_smoketest/latest

Test location	/workspace/coverage/default/0.chip_sw_aon_timer_wdog_bite_reset.2385189764
Short name	T734
Test name
Test status
Simulation time	10106793846 ps
CPU time	837.52 seconds
Started	Aug 14 05:47:24 PM PDT 24
Finished	Aug 14 06:01:23 PM PDT 24
Peak memory	611168 kb
Host	smart-0c642692-d6b3-4e60-aec5-47e0ab21b0ed
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=aon_timer_wdog_bite_reset_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 2385189764 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_aon_timer_wdog_bite_reset.2385189764
Directory	/workspace/0.chip_sw_aon_timer_wdog_bite_reset/latest

Test location	/workspace/coverage/default/0.chip_sw_aon_timer_wdog_lc_escalate.1334931987
Short name	T352
Test name
Test status
Simulation time	4716663288 ps
CPU time	740.75 seconds
Started	Aug 14 05:51:56 PM PDT 24
Finished	Aug 14 06:04:18 PM PDT 24
Peak memory	610172 kb
Host	smart-ffb028a2-67ee-4dd8-96b4-4983b2907666
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=aon_timer_wdog_lc_escalate_test:1:new_rules,test_rom:0 +cdc_ instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed =1334931987 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_aon_timer_wdog_lc_escalate.1334931987
Directory	/workspace/0.chip_sw_aon_timer_wdog_lc_escalate/latest

Test location	/workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_lc.2170639085
Short name	T623
Test name
Test status
Simulation time	5469697160 ps
CPU time	420.63 seconds
Started	Aug 14 05:51:36 PM PDT 24
Finished	Aug 14 05:58:37 PM PDT 24
Peak memory	622112 kb
Host	smart-f4fbc859-d8fc-41b5-98f3-3122f6641c73
User	root
Command	/workspace/default/simv +chip_clock_source=ChipClockSourceExternal48Mhz +sw_build_device=sim_dv +sw_images=clkmgr_external_clk_src_for_lc_test:1:new_r ules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim .tcl +ntb_random_seed=2170639085 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_transition_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_clkmgr_external_clk_src_for_lc.2170639085
Directory	/workspace/0.chip_sw_clkmgr_external_clk_src_for_lc/latest

Test location	/workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_fast_dev.2158604178
Short name	T659
Test name
Test status
Simulation time	3746641650 ps
CPU time	645.72 seconds
Started	Aug 14 05:49:24 PM PDT 24
Finished	Aug 14 06:00:10 PM PDT 24
Peak memory	613884 kb
Host	smart-67ca6871-bf7b-48a0-a12e-3447552c8e28
User	root
Command	/workspace/default/simv +chip_clock_source=ChipClockSourceExternal96Mhz +calibrate_usb_clk=1 +src_dec_state=DecLcStDev +sw_build_device=sim_dv +sw_ima ges=clkmgr_external_clk_src_for_sw_fast_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2158604178 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ =chip_sw_lc_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_c lkmgr_external_clk_src_for_sw_fast_dev.2158604178
Directory	/workspace/0.chip_sw_clkmgr_external_clk_src_for_sw_fast_dev/latest

Test location	/workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_fast_rma.121591370
Short name	T771
Test name
Test status
Simulation time	4373223432 ps
CPU time	678.78 seconds
Started	Aug 14 05:50:59 PM PDT 24
Finished	Aug 14 06:02:18 PM PDT 24
Peak memory	613708 kb
Host	smart-cf9d3a1d-e3ed-4ab5-9bb7-86257dd9ac49
User	root
Command	/workspace/default/simv +chip_clock_source=ChipClockSourceExternal96Mhz +calibrate_usb_clk=1 +src_dec_state=DecLcStRma +sw_build_device=sim_dv +sw_ima ges=clkmgr_external_clk_src_for_sw_fast_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=121591370 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ= chip_sw_lc_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_cl kmgr_external_clk_src_for_sw_fast_rma.121591370
Directory	/workspace/0.chip_sw_clkmgr_external_clk_src_for_sw_fast_rma/latest

Test location	/workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0.2320678011
Short name	T698
Test name
Test status
Simulation time	4127896120 ps
CPU time	670.12 seconds
Started	Aug 14 05:51:07 PM PDT 24
Finished	Aug 14 06:02:18 PM PDT 24
Peak memory	614812 kb
Host	smart-4878f7f0-1021-432a-985f-c0cd998be5c9
User	root
Command	/workspace/default/simv +chip_clock_source=ChipClockSourceExternal96Mhz +calibrate_usb_clk=1 +src_dec_state=DecLcStTestUnlocked0 +sw_build_device=sim_ dv +sw_images=clkmgr_external_clk_src_for_sw_fast_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2320678011 -assert nopostproc +UVM_TESTNAME=chip_base_test +UV M_TEST_SEQ=chip_sw_lc_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0 .chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0.2320678011
Directory	/workspace/0.chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0/latest

Test location	/workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_slow_rma.764089071
Short name	T608
Test name
Test status
Simulation time	4962065020 ps
CPU time	712.57 seconds
Started	Aug 14 05:48:15 PM PDT 24
Finished	Aug 14 06:00:08 PM PDT 24
Peak memory	614860 kb
Host	smart-d86eb7fe-11f5-4415-b638-d47b8200e1ff
User	root
Command	/workspace/default/simv +chip_clock_source=ChipClockSourceExternal48Mhz +calibrate_usb_clk=1 +src_dec_state=DecLcStRma +sw_build_device=sim_dv +sw_ima ges=clkmgr_external_clk_src_for_sw_slow_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=764089071 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ= chip_sw_lc_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_cl kmgr_external_clk_src_for_sw_slow_rma.764089071
Directory	/workspace/0.chip_sw_clkmgr_external_clk_src_for_sw_slow_rma/latest

Test location	/workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0.3524758816
Short name	T956
Test name
Test status
Simulation time	3978964728 ps
CPU time	601.63 seconds
Started	Aug 14 05:47:25 PM PDT 24
Finished	Aug 14 05:57:27 PM PDT 24
Peak memory	614900 kb
Host	smart-fe0a154d-7833-4218-9600-25251e8541bc
User	root
Command	/workspace/default/simv +chip_clock_source=ChipClockSourceExternal48Mhz +calibrate_usb_clk=1 +src_dec_state=DecLcStTestUnlocked0 +sw_build_device=sim_ dv +sw_images=clkmgr_external_clk_src_for_sw_slow_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3524758816 -assert nopostproc +UVM_TESTNAME=chip_base_test +UV M_TEST_SEQ=chip_sw_lc_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0 .chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0.3524758816
Directory	/workspace/0.chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0/latest

Test location	/workspace/coverage/default/0.chip_sw_clkmgr_jitter.3198027418
Short name	T303
Test name
Test status
Simulation time	2203056386 ps
CPU time	203.13 seconds
Started	Aug 14 05:52:48 PM PDT 24
Finished	Aug 14 05:56:13 PM PDT 24
Peak memory	609836 kb
Host	smart-ba7ca133-4907-40bf-b7c3-89e24508d5f1
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=clkmgr_jitter_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3198027418 -assert nopostproc +UVM_TESTNAME =chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 0.chip_sw_clkmgr_jitter.3198027418
Directory	/workspace/0.chip_sw_clkmgr_jitter/latest

Test location	/workspace/coverage/default/0.chip_sw_clkmgr_jitter_frequency.1451092920
Short name	T824
Test name
Test status
Simulation time	3975140410 ps
CPU time	434.46 seconds
Started	Aug 14 05:47:55 PM PDT 24
Finished	Aug 14 05:55:10 PM PDT 24
Peak memory	610564 kb
Host	smart-63180642-fee3-4466-a9b1-405cc269753e
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=clkmgr_jitter_frequency_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1451092920 -assert nopostproc +UV M_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -c m_log /dev/null -cm_name 0.chip_sw_clkmgr_jitter_frequency.1451092920
Directory	/workspace/0.chip_sw_clkmgr_jitter_frequency/latest

Test location	/workspace/coverage/default/0.chip_sw_clkmgr_jitter_reduced_freq.348046955
Short name	T716
Test name
Test status
Simulation time	2523100991 ps
CPU time	187.88 seconds
Started	Aug 14 05:47:57 PM PDT 24
Finished	Aug 14 05:51:05 PM PDT 24
Peak memory	610304 kb
Host	smart-b5e4735c-006b-4750-b5d0-5e3a92fcb9de
User	root
Command	/workspace/default/simv +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=clkmgr_jitter_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=348046955 -assert nopo stproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defa ult.vdb -cm_log /dev/null -cm_name 0.chip_sw_clkmgr_jitter_reduced_freq.348046955
Directory	/workspace/0.chip_sw_clkmgr_jitter_reduced_freq/latest

Test location	/workspace/coverage/default/0.chip_sw_clkmgr_off_aes_trans.3378594684
Short name	T842
Test name
Test status
Simulation time	4916618120 ps
CPU time	523.46 seconds
Started	Aug 14 05:48:47 PM PDT 24
Finished	Aug 14 05:57:31 PM PDT 24
Peak memory	610352 kb
Host	smart-b00d5635-bd51-474a-9ce7-0a44f6b8c7b9
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=clkmgr_off_aes_trans_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3378594684 -assert nopostproc +UVM_T ESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l og /dev/null -cm_name 0.chip_sw_clkmgr_off_aes_trans.3378594684
Directory	/workspace/0.chip_sw_clkmgr_off_aes_trans/latest

Test location	/workspace/coverage/default/0.chip_sw_clkmgr_off_hmac_trans.1185112904
Short name	T723
Test name
Test status
Simulation time	5582876844 ps
CPU time	618.95 seconds
Started	Aug 14 05:53:15 PM PDT 24
Finished	Aug 14 06:03:35 PM PDT 24
Peak memory	610912 kb
Host	smart-85532345-2696-42da-a413-36de6f8f3408
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=clkmgr_off_hmac_trans_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1185112904 -assert nopostproc +UVM_ TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_ log /dev/null -cm_name 0.chip_sw_clkmgr_off_hmac_trans.1185112904
Directory	/workspace/0.chip_sw_clkmgr_off_hmac_trans/latest

Test location	/workspace/coverage/default/0.chip_sw_clkmgr_off_kmac_trans.1407769253
Short name	T984
Test name
Test status
Simulation time	5549991428 ps
CPU time	562.51 seconds
Started	Aug 14 05:48:35 PM PDT 24
Finished	Aug 14 05:57:57 PM PDT 24
Peak memory	610924 kb
Host	smart-a2096825-25c8-4aa4-abdf-6fb0e7687177
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=clkmgr_off_kmac_trans_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1407769253 -assert nopostproc +UVM_ TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_ log /dev/null -cm_name 0.chip_sw_clkmgr_off_kmac_trans.1407769253
Directory	/workspace/0.chip_sw_clkmgr_off_kmac_trans/latest

Test location	/workspace/coverage/default/0.chip_sw_clkmgr_off_otbn_trans.3632750672
Short name	T907
Test name
Test status
Simulation time	4689820270 ps
CPU time	712.2 seconds
Started	Aug 14 05:52:46 PM PDT 24
Finished	Aug 14 06:04:40 PM PDT 24
Peak memory	611116 kb
Host	smart-cadf747d-0e08-4098-b2f1-afce746cd05c
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=clkmgr_off_otbn_trans_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3632750672 -assert nopostproc +UVM_ TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_ log /dev/null -cm_name 0.chip_sw_clkmgr_off_otbn_trans.3632750672
Directory	/workspace/0.chip_sw_clkmgr_off_otbn_trans/latest

Test location	/workspace/coverage/default/0.chip_sw_clkmgr_reset_frequency.2683351716
Short name	T586
Test name
Test status
Simulation time	3711948488 ps
CPU time	366.2 seconds
Started	Aug 14 05:48:13 PM PDT 24
Finished	Aug 14 05:54:20 PM PDT 24
Peak memory	610636 kb
Host	smart-64913738-1362-432b-ae2d-e3cd8be021f7
User	root
Command	/workspace/default/simv +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=clkmgr_reset_frequency_test:1:new_rules,test_rom:0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2683351716 -a ssert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov erage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_clkmgr_reset_frequency.2683351716
Directory	/workspace/0.chip_sw_clkmgr_reset_frequency/latest

Test location	/workspace/coverage/default/0.chip_sw_clkmgr_sleep_frequency.293600150
Short name	T443
Test name
Test status
Simulation time	4625763922 ps
CPU time	630.13 seconds
Started	Aug 14 05:51:52 PM PDT 24
Finished	Aug 14 06:02:22 PM PDT 24
Peak memory	610996 kb
Host	smart-123b58c0-1b6d-4568-9943-38e7c80f74e1
User	root
Command	/workspace/default/simv +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=clkmgr_sleep_frequency_test:1:new_rules,test_rom:0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=293600150 -as sert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove rage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_clkmgr_sleep_frequency.293600150
Directory	/workspace/0.chip_sw_clkmgr_sleep_frequency/latest

Test location	/workspace/coverage/default/0.chip_sw_clkmgr_smoketest.3605219078
Short name	T727
Test name
Test status
Simulation time	2791633464 ps
CPU time	309.61 seconds
Started	Aug 14 05:51:37 PM PDT 24
Finished	Aug 14 05:56:47 PM PDT 24
Peak memory	610328 kb
Host	smart-d1ce4559-c2a3-4fe2-af38-096745385ebc
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=clkmgr_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3605219078 -assert nopostproc +UVM_TESTNAME=c hip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n ull -cm_name 0.chip_sw_clkmgr_smoketest.3605219078
Directory	/workspace/0.chip_sw_clkmgr_smoketest/latest

Test location	/workspace/coverage/default/0.chip_sw_coremark.3496996182
Short name	T398
Test name
Test status
Simulation time	71543246400 ps
CPU time	15455.9 seconds
Started	Aug 14 05:52:29 PM PDT 24
Finished	Aug 14 10:10:07 PM PDT 24
Peak memory	612396 kb
Host	smart-1c5ba6f9-cbf3-416a-8a84-28dc7724d866
User	root
Command	/workspace/default/simv +en_uart_logger=1 +sw_test_timeout_ns=200_000_000 +sw_build_device=sim_dv +sw_images=coremark_test:1:new_rules,test_rom:0 +cdc _instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see d=3496996182 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_coremark.3496996182
Directory	/workspace/0.chip_sw_coremark/latest

Test location	/workspace/coverage/default/0.chip_sw_csrng_edn_concurrency.2698450342
Short name	T620
Test name
Test status
Simulation time	8773947560 ps
CPU time	2310.79 seconds
Started	Aug 14 05:52:20 PM PDT 24
Finished	Aug 14 06:30:51 PM PDT 24
Peak memory	610748 kb
Host	smart-4cd9f84d-92c5-4f4b-8aba-84fda2ee345e
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=140_000_000 +rng_srate_value_min=15 +rng_srate_value_max=20 +accelerate_cold_power_up_time=3 +accelerate_r egulators_power_up_time=2 +sw_build_device=sim_dv +sw_images=csrng_edn_concurrency_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2698450342 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd b -cm_log /dev/null -cm_name 0.chip_sw_csrng_edn_concurrency.2698450342
Directory	/workspace/0.chip_sw_csrng_edn_concurrency/latest

Test location	/workspace/coverage/default/0.chip_sw_csrng_edn_concurrency_reduced_freq.214470329
Short name	T137
Test name
Test status
Simulation time	32976772206 ps
CPU time	5395.62 seconds
Started	Aug 14 05:53:17 PM PDT 24
Finished	Aug 14 07:23:13 PM PDT 24
Peak memory	610832 kb
Host	smart-94240dea-864e-4ab4-a752-966a18ed835f
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=360_000_000 +rng_srate_value_min=15 +rng_srate_value_max=20 +cal_sys_clk_70mhz=1 +en_jitter=1 +accelerate_ cold_power_up_time=3 +accelerate_regulators_power_up_time=2 +sw_build_device=sim_dv +sw_images=csrng_edn_concurrency_test:1:new_rules,test_rom:0 + cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_ seed=214470329 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_csrng_edn_concurrency_reduced_freq.214470329
Directory	/workspace/0.chip_sw_csrng_edn_concurrency_reduced_freq/latest

Test location	/workspace/coverage/default/0.chip_sw_csrng_kat_test.3096793488
Short name	T1016
Test name
Test status
Simulation time	3151566776 ps
CPU time	324.65 seconds
Started	Aug 14 05:49:42 PM PDT 24
Finished	Aug 14 05:55:07 PM PDT 24
Peak memory	610436 kb
Host	smart-25826cd5-c2cf-4af2-9449-b274c069d4c1
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=csrng_kat_test:1:new_rules,test_rom:0 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3096793488 -asse rt nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera ge/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_csrng_kat_test.3096793488
Directory	/workspace/0.chip_sw_csrng_kat_test/latest

Test location	/workspace/coverage/default/0.chip_sw_csrng_lc_hw_debug_en_test.3692584962
Short name	T225
Test name
Test status
Simulation time	5190047520 ps
CPU time	747.19 seconds
Started	Aug 14 05:50:58 PM PDT 24
Finished	Aug 14 06:03:26 PM PDT 24
Peak memory	611824 kb
Host	smart-e5381676-8f29-4ccd-80c1-e60fca390f85
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=15_000_000 +rng_srate_value_min=15 +use_otp_image=OtpTypeLcStTestUnlocked0 +sw_build_device=sim_dv +sw_ima ges=csrng_lc_hw_debug_en_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3692584962 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_csrng_ lc_hw_debug_en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_csr ng_lc_hw_debug_en_test.3692584962
Directory	/workspace/0.chip_sw_csrng_lc_hw_debug_en_test/latest

Test location	/workspace/coverage/default/0.chip_sw_csrng_smoketest.1674356564
Short name	T590
Test name
Test status
Simulation time	3275370352 ps
CPU time	270.23 seconds
Started	Aug 14 05:47:35 PM PDT 24
Finished	Aug 14 05:52:05 PM PDT 24
Peak memory	610376 kb
Host	smart-73f1b1e5-0dcf-4b68-bbba-5fee28f00386
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=csrng_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1674356564 -assert nopostproc +UVM_TESTNAME=ch ip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu ll -cm_name 0.chip_sw_csrng_smoketest.1674356564
Directory	/workspace/0.chip_sw_csrng_smoketest/latest

Test location	/workspace/coverage/default/0.chip_sw_data_integrity_escalation.1585329629
Short name	T292
Test name
Test status
Simulation time	4722568880 ps
CPU time	956.36 seconds
Started	Aug 14 05:50:22 PM PDT 24
Finished	Aug 14 06:06:20 PM PDT 24
Peak memory	611980 kb
Host	smart-dc11d452-b87a-46d7-a63c-47c7f6b1e760
User	root
Command	/workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=data_integrity_escalation_reset_test:1:new_rules,test_ro m:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=1585329629 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_data_integrity_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_data_integrity_escalation.1585329629
Directory	/workspace/0.chip_sw_data_integrity_escalation/latest

Test location	/workspace/coverage/default/0.chip_sw_edn_auto_mode.3974603802
Short name	T1015
Test name
Test status
Simulation time	7007074600 ps
CPU time	2324.24 seconds
Started	Aug 14 05:52:53 PM PDT 24
Finished	Aug 14 06:31:39 PM PDT 24
Peak memory	610988 kb
Host	smart-969aa353-250a-405c-9aea-c76ebad7e9ff
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=18_000_000 +rng_srate_value=5 +accelerate_cold_power_up_time=3 +accelerate_regulators_power_up_time=2 +sw_ build_device=sim_dv +sw_images=edn_auto_mode:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3974603802 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ =chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_edn_ auto_mode.3974603802
Directory	/workspace/0.chip_sw_edn_auto_mode/latest

Test location	/workspace/coverage/default/0.chip_sw_edn_entropy_reqs.4067690060
Short name	T675
Test name
Test status
Simulation time	7180272280 ps
CPU time	1614.88 seconds
Started	Aug 14 05:51:03 PM PDT 24
Finished	Aug 14 06:17:58 PM PDT 24
Peak memory	611684 kb
Host	smart-279940b5-5f21-49a0-be33-c0f64e2aec79
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=15000000 +rng_srate_value_min=15 +rng_srate_value_max=30 +sw_build_device=sim_dv +sw_images=entropy_src_ed n_reqs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=4067690060 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_edn_entropy_reqs.4067690060
Directory	/workspace/0.chip_sw_edn_entropy_reqs/latest

Test location	/workspace/coverage/default/0.chip_sw_edn_entropy_reqs_jitter.1423306418
Short name	T877
Test name
Test status
Simulation time	6764993412 ps
CPU time	1207.32 seconds
Started	Aug 14 05:51:39 PM PDT 24
Finished	Aug 14 06:11:47 PM PDT 24
Peak memory	611664 kb
Host	smart-7030127c-8749-41da-908e-c0cc6a2e4f1c
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=15000000 +rng_srate_value_min=15 +rng_srate_value_max=30 +en_jitter=1 +sw_build_device=sim_dv +sw_images=e ntropy_src_edn_reqs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1423306418 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_edn_entropy_reqs_jitter.1423306418
Directory	/workspace/0.chip_sw_edn_entropy_reqs_jitter/latest

Test location	/workspace/coverage/default/0.chip_sw_edn_kat.1920219105
Short name	T714
Test name
Test status
Simulation time	3306394514 ps
CPU time	735.02 seconds
Started	Aug 14 05:52:45 PM PDT 24
Finished	Aug 14 06:05:00 PM PDT 24
Peak memory	617224 kb
Host	smart-a63f7c39-3f4c-485b-a4d6-4c1b174d6346
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=18_000_000 +rng_srate_value=5 +disable_assert_edn_output_diff_from_prev=1 +accelerate_cold_power_up_time=3 +accelerate_regulators_power_up_time=2 +sw_build_device=sim_dv +sw_images=edn_kat:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1920219105 -assert nopostproc +UVM _TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm _log /dev/null -cm_name 0.chip_sw_edn_kat.1920219105
Directory	/workspace/0.chip_sw_edn_kat/latest

Test location	/workspace/coverage/default/0.chip_sw_edn_sw_mode.1827967769
Short name	T1020
Test name
Test status
Simulation time	5649476800 ps
CPU time	1168.32 seconds
Started	Aug 14 05:52:09 PM PDT 24
Finished	Aug 14 06:11:39 PM PDT 24
Peak memory	609840 kb
Host	smart-6dcc8bd3-20ed-4b33-8987-a88761ef2fbf
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=edn_sw_mode:1:new_rules,test_rom:0 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1827967769 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/ default.vdb -cm_log /dev/null -cm_name 0.chip_sw_edn_sw_mode.1827967769
Directory	/workspace/0.chip_sw_edn_sw_mode/latest

Test location	/workspace/coverage/default/0.chip_sw_entropy_src_ast_rng_req.2521882361
Short name	T713
Test name
Test status
Simulation time	2941541710 ps
CPU time	184.21 seconds
Started	Aug 14 05:50:51 PM PDT 24
Finished	Aug 14 05:53:56 PM PDT 24
Peak memory	609896 kb
Host	smart-985a0c53-0b98-4d68-abe7-5d6199937eca
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=15_000_000 +sw_build_device=sim_dv +sw_images=entropy_src_ast_rng_req_test:1:new_rules,test_rom:0 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25 21882361 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_entropy_src_ast_rng_req.2521882361
Directory	/workspace/0.chip_sw_entropy_src_ast_rng_req/latest

Test location	/workspace/coverage/default/0.chip_sw_entropy_src_kat_test.1301504204
Short name	T649
Test name
Test status
Simulation time	2935295280 ps
CPU time	246.82 seconds
Started	Aug 14 05:48:06 PM PDT 24
Finished	Aug 14 05:52:14 PM PDT 24
Peak memory	610428 kb
Host	smart-14df5a14-436d-425f-8473-d64b292c2471
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=entropy_src_kat_test:1:new_rules,test_rom:0 +cdc_instrumenta tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1301504204 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/ coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_entropy_src_kat_test.1301504204
Directory	/workspace/0.chip_sw_entropy_src_kat_test/latest

Test location	/workspace/coverage/default/0.chip_sw_entropy_src_smoketest.1375199814
Short name	T967
Test name
Test status
Simulation time	3681773880 ps
CPU time	664.63 seconds
Started	Aug 14 05:55:17 PM PDT 24
Finished	Aug 14 06:06:22 PM PDT 24
Peak memory	610340 kb
Host	smart-139671b4-7e6c-4467-8960-39975279bb28
User	root
Command	/workspace/default/simv +rng_srate_value_min=15 +rng_srate_value_max=30 +sw_build_device=sim_dv +sw_images=entropy_src_smoketest:1:new_rules,test_rom: 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand om_seed=1375199814 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_entropy_src_smoketest.1375199814
Directory	/workspace/0.chip_sw_entropy_src_smoketest/latest

Test location	/workspace/coverage/default/0.chip_sw_example_concurrency.309959878
Short name	T597
Test name
Test status
Simulation time	2607013140 ps
CPU time	202.73 seconds
Started	Aug 14 05:46:38 PM PDT 24
Finished	Aug 14 05:50:02 PM PDT 24
Peak memory	609832 kb
Host	smart-fa1281f1-1fc5-4fba-9b5c-59fb1a78934d
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=example_concurrency_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=309959878 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_example_concurrency.309959878
Directory	/workspace/0.chip_sw_example_concurrency/latest

Test location	/workspace/coverage/default/0.chip_sw_example_flash.817116318
Short name	T937
Test name
Test status
Simulation time	2556825164 ps
CPU time	289.06 seconds
Started	Aug 14 05:47:02 PM PDT 24
Finished	Aug 14 05:51:52 PM PDT 24
Peak memory	609780 kb
Host	smart-bf6a2777-b100-45f8-82ad-7f0fe38bb0b3
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=example_test_from_flash:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=817116318 -assert nopostproc +UVM_TEST NAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_example_flash.817116318
Directory	/workspace/0.chip_sw_example_flash/latest

Test location	/workspace/coverage/default/0.chip_sw_example_manufacturer.3882920027
Short name	T744
Test name
Test status
Simulation time	3417878856 ps
CPU time	212.15 seconds
Started	Aug 14 05:48:21 PM PDT 24
Finished	Aug 14 05:51:54 PM PDT 24
Peak memory	610240 kb
Host	smart-be950525-d195-43f9-8561-1bb90b99cd52
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=example_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3882920027 -assert nopostproc +UVM_TESTNAME=chip_ base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_example_manufacturer.3882920027
Directory	/workspace/0.chip_sw_example_manufacturer/latest

Test location	/workspace/coverage/default/0.chip_sw_example_rom.1889089112
Short name	T817
Test name
Test status
Simulation time	2026920152 ps
CPU time	155.92 seconds
Started	Aug 14 05:47:36 PM PDT 24
Finished	Aug 14 05:50:12 PM PDT 24
Peak memory	609856 kb
Host	smart-f08d305c-adb1-4655-aa25-9e6b38e36874
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=example_test_from_rom:0:test_in_rom:new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1889089112 -assert nopostproc +UVM_TEST NAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_example_rom.1889089112
Directory	/workspace/0.chip_sw_example_rom/latest

Test location	/workspace/coverage/default/0.chip_sw_exit_test_unlocked_bootstrap.2128342657
Short name	T835
Test name
Test status
Simulation time	57784989096 ps
CPU time	11797.5 seconds
Started	Aug 14 05:48:19 PM PDT 24
Finished	Aug 14 09:04:58 PM PDT 24
Peak memory	625288 kb
Host	smart-0e3f45c2-e83d-40e2-a627-df75ae5fc19e
User	root
Command	/workspace/default/simv +flash_program_latency=5 +sw_test_timeout_ns=150_000_000 +sw_build_device=sim_dv +sw_images=exit_test_unlocked_bootstrap:1:new _rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/s im.tcl +ntb_random_seed=2128342657 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_exit_test_unlocked_bootstrap_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_exit_test_unlocked_bootstrap.2128342657
Directory	/workspace/0.chip_sw_exit_test_unlocked_bootstrap/latest

Test location	/workspace/coverage/default/0.chip_sw_flash_crash_alert.1353028233
Short name	T425
Test name
Test status
Simulation time	5096789360 ps
CPU time	616.25 seconds
Started	Aug 14 05:52:34 PM PDT 24
Finished	Aug 14 06:02:51 PM PDT 24
Peak memory	611968 kb
Host	smart-aa33b0d5-cd73-4525-9e9b-5577f65d3511
User	root
Command	/workspace/default/simv +test_timeout_ns=8_000_000 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1: new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tool s/sim.tcl +ntb_random_seed=1353028233 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_flash_host_gnt_err_inj_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_flash_crash_alert.1353028233
Directory	/workspace/0.chip_sw_flash_crash_alert/latest

Test location	/workspace/coverage/default/0.chip_sw_flash_ctrl_access.1795667865
Short name	T565
Test name
Test status
Simulation time	6053003162 ps
CPU time	1325.31 seconds
Started	Aug 14 05:47:41 PM PDT 24
Finished	Aug 14 06:09:48 PM PDT 24
Peak memory	610584 kb
Host	smart-7d0566fa-bfaa-4a73-9fdc-c13fe4cd9833
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=flash_ctrl_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1795667865 -assert nopostproc +UVM_TESTNAME=ch ip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu ll -cm_name 0.chip_sw_flash_ctrl_access.1795667865
Directory	/workspace/0.chip_sw_flash_ctrl_access/latest

Test location	/workspace/coverage/default/0.chip_sw_flash_ctrl_access_jitter_en.4045106094
Short name	T103
Test name
Test status
Simulation time	6066199687 ps
CPU time	1124.14 seconds
Started	Aug 14 05:50:18 PM PDT 24
Finished	Aug 14 06:09:03 PM PDT 24
Peak memory	610340 kb
Host	smart-283188c1-5655-48b5-baed-1721cdb56dce
User	root
Command	/workspace/default/simv +en_jitter=1 +sw_build_device=sim_dv +sw_images=flash_ctrl_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4045106094 -assert nopostproc +UV M_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -c m_log /dev/null -cm_name 0.chip_sw_flash_ctrl_access_jitter_en.4045106094
Directory	/workspace/0.chip_sw_flash_ctrl_access_jitter_en/latest

Test location	/workspace/coverage/default/0.chip_sw_flash_ctrl_access_jitter_en_reduced_freq.2629364327
Short name	T633
Test name
Test status
Simulation time	7495073066 ps
CPU time	1347.42 seconds
Started	Aug 14 05:53:00 PM PDT 24
Finished	Aug 14 06:15:27 PM PDT 24
Peak memory	610892 kb
Host	smart-c0c84f46-3d36-4a04-83b2-a0be35ef5947
User	root
Command	/workspace/default/simv +en_jitter=1 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=flash_ctrl_test:1:new_rules,test_rom:0 +cdc_instrumentati on_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2629364327 - assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co verage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_flash_ctrl_access_jitter_en_reduced_freq.2629364327
Directory	/workspace/0.chip_sw_flash_ctrl_access_jitter_en_reduced_freq/latest

Test location	/workspace/coverage/default/0.chip_sw_flash_ctrl_clock_freqs.4275124176
Short name	T755
Test name
Test status
Simulation time	6120515351 ps
CPU time	1172.58 seconds
Started	Aug 14 05:48:22 PM PDT 24
Finished	Aug 14 06:07:55 PM PDT 24
Peak memory	610740 kb
Host	smart-8723aa8f-fc57-48f8-8742-118008aa5dc5
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=flash_ctrl_clock_freqs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4275124176 -assert nopostproc +UVM _TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm _log /dev/null -cm_name 0.chip_sw_flash_ctrl_clock_freqs.4275124176
Directory	/workspace/0.chip_sw_flash_ctrl_clock_freqs/latest

Test location	/workspace/coverage/default/0.chip_sw_flash_ctrl_idle_low_power.576125925
Short name	T697
Test name
Test status
Simulation time	3152650300 ps
CPU time	284.64 seconds
Started	Aug 14 05:47:01 PM PDT 24
Finished	Aug 14 05:51:46 PM PDT 24
Peak memory	610620 kb
Host	smart-e4ccf254-634f-4ab8-becc-9441efe370cb
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=flash_ctrl_idle_low_power_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=576125925 -assert nopostproc +U VM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb - cm_log /dev/null -cm_name 0.chip_sw_flash_ctrl_idle_low_power.576125925
Directory	/workspace/0.chip_sw_flash_ctrl_idle_low_power/latest

Test location	/workspace/coverage/default/0.chip_sw_flash_ctrl_mem_protection.3500420857
Short name	T629
Test name
Test status
Simulation time	5434560204 ps
CPU time	1278.42 seconds
Started	Aug 14 05:50:28 PM PDT 24
Finished	Aug 14 06:11:47 PM PDT 24
Peak memory	609928 kb
Host	smart-04642395-fa9f-4a99-9868-f824ada37181
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=flash_ctrl_mem_protection_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3500420857 -assert nopostproc + UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_flash_ctrl_mem_protection.3500420857
Directory	/workspace/0.chip_sw_flash_ctrl_mem_protection/latest

Test location	/workspace/coverage/default/0.chip_sw_flash_ctrl_ops.2897470249
Short name	T589
Test name
Test status
Simulation time	4149617416 ps
CPU time	618.58 seconds
Started	Aug 14 05:52:44 PM PDT 24
Finished	Aug 14 06:03:03 PM PDT 24
Peak memory	610636 kb
Host	smart-25131c3e-3796-41ea-a138-cd65bb1002b0
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=50_000_000 +sw_build_device=sim_dv +sw_images=flash_ctrl_ops_test:1:new_rules,test_rom:0 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2897470249 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/c overage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_flash_ctrl_ops.2897470249
Directory	/workspace/0.chip_sw_flash_ctrl_ops/latest

Test location	/workspace/coverage/default/0.chip_sw_flash_ctrl_ops_jitter_en_reduced_freq.257270447
Short name	T938
Test name
Test status
Simulation time	4611491808 ps
CPU time	759.01 seconds
Started	Aug 14 05:51:46 PM PDT 24
Finished	Aug 14 06:04:25 PM PDT 24
Peak memory	610952 kb
Host	smart-3be90e1c-d212-43c2-a10a-988f1ff800af
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=50_000_000 +en_jitter=1 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=flash_ctrl_ops_test:1:new_ rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si m.tcl +ntb_random_seed=257270447 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_flash_ctrl_ops_jitter_en_reduced_freq.257270447
Directory	/workspace/0.chip_sw_flash_ctrl_ops_jitter_en_reduced_freq/latest

Test location	/workspace/coverage/default/0.chip_sw_flash_ctrl_write_clear.1164470900
Short name	T826
Test name
Test status
Simulation time	2772810514 ps
CPU time	459.75 seconds
Started	Aug 14 05:49:41 PM PDT 24
Finished	Aug 14 05:57:22 PM PDT 24
Peak memory	610412 kb
Host	smart-d4e78b1c-b6c5-4bd9-9b0e-89ec28fa2ccc
User	root
Command	/workspace/default/simv +test_timeout_ns=8_000_000 +sw_build_device=sim_dv +sw_images=flash_ctrl_write_clear_test:1:new_rules,test_rom:0 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1164470 900 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ce/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_flash_ctrl_write_clear.1164470900
Directory	/workspace/0.chip_sw_flash_ctrl_write_clear/latest

Test location	/workspace/coverage/default/0.chip_sw_flash_init_reduced_freq.1173704223
Short name	T982
Test name
Test status
Simulation time	20165379843 ps
CPU time	2373.02 seconds
Started	Aug 14 05:48:16 PM PDT 24
Finished	Aug 14 06:27:50 PM PDT 24
Peak memory	614212 kb
Host	smart-e517eb9b-e4c4-4920-8b32-374f08880872
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=25_000_000 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=flash_init_test:0:test_in_rom:new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=1173704223 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_flash_init_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_flash_init_reduced_freq.1173704223
Directory	/workspace/0.chip_sw_flash_init_reduced_freq/latest

Test location	/workspace/coverage/default/0.chip_sw_flash_scrambling_smoketest.3666472381
Short name	T595
Test name
Test status
Simulation time	2567995134 ps
CPU time	184.46 seconds
Started	Aug 14 05:54:49 PM PDT 24
Finished	Aug 14 05:57:53 PM PDT 24
Peak memory	609892 kb
Host	smart-587cd81b-84fa-4ebf-be39-c5733038fb3d
User	root
Command	/workspace/default/simv +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=flash_scrambling_smoketest:1:new_rules,flash_scrambling_smoket est_otp_img_rma:4,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=3666472381 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_flash_scrambling_smoketest.3666472381
Directory	/workspace/0.chip_sw_flash_scrambling_smoketest/latest

Test location	/workspace/coverage/default/0.chip_sw_gpio_smoketest.2782777014
Short name	T912
Test name
Test status
Simulation time	3034652423 ps
CPU time	321.73 seconds
Started	Aug 14 05:55:15 PM PDT 24
Finished	Aug 14 06:00:37 PM PDT 24
Peak memory	612264 kb
Host	smart-fb8c0f3b-04ae-4408-ad37-2c129b4582c4
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=gpio_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2782777014 -assert nopostproc +UVM_TESTNAME=chi p_base_test +UVM_TEST_SEQ=chip_sw_gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 0.chip_sw_gpio_smoketest.2782777014
Directory	/workspace/0.chip_sw_gpio_smoketest/latest

Test location	/workspace/coverage/default/0.chip_sw_hmac_enc.1692110415
Short name	T245
Test name
Test status
Simulation time	3235811910 ps
CPU time	328.79 seconds
Started	Aug 14 05:53:14 PM PDT 24
Finished	Aug 14 05:58:43 PM PDT 24
Peak memory	610468 kb
Host	smart-9a48b459-2234-450d-92d3-4e8c35d11fee
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=hmac_enc_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1692110415 -assert nopostproc +UVM_TESTNAME=chip _base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_hmac_enc.1692110415
Directory	/workspace/0.chip_sw_hmac_enc/latest

Test location	/workspace/coverage/default/0.chip_sw_hmac_enc_idle.198097912
Short name	T847
Test name
Test status
Simulation time	3373311680 ps
CPU time	269.35 seconds
Started	Aug 14 05:48:52 PM PDT 24
Finished	Aug 14 05:53:21 PM PDT 24
Peak memory	609848 kb
Host	smart-a69c338b-b9ac-4e00-8c8e-0c2731afbef5
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=hmac_enc_idle_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=198097912 -assert nopostproc +UVM_TESTNAME= chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/ null -cm_name 0.chip_sw_hmac_enc_idle.198097912
Directory	/workspace/0.chip_sw_hmac_enc_idle/latest

Test location	/workspace/coverage/default/0.chip_sw_hmac_enc_jitter_en.2465339433
Short name	T615
Test name
Test status
Simulation time	2934668722 ps
CPU time	251.42 seconds
Started	Aug 14 05:49:45 PM PDT 24
Finished	Aug 14 05:53:57 PM PDT 24
Peak memory	610476 kb
Host	smart-f46034f5-f0d0-40bc-a4d2-d5828e7c56df
User	root
Command	/workspace/default/simv +en_jitter=1 +sw_build_device=sim_dv +sw_images=hmac_enc_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2465339433 -assert nopostproc +UVM_ TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_ log /dev/null -cm_name 0.chip_sw_hmac_enc_jitter_en.2465339433
Directory	/workspace/0.chip_sw_hmac_enc_jitter_en/latest

Test location	/workspace/coverage/default/0.chip_sw_hmac_enc_jitter_en_reduced_freq.3693791304
Short name	T870
Test name
Test status
Simulation time	3853058528 ps
CPU time	321.38 seconds
Started	Aug 14 05:52:16 PM PDT 24
Finished	Aug 14 05:57:39 PM PDT 24
Peak memory	609280 kb
Host	smart-1186f3cc-44df-474b-9b6c-c549ae1a5c7a
User	root
Command	/workspace/default/simv +en_jitter=1 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=hmac_enc_test:1:new_rules,test_rom:0 +cdc_instrumentation _enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3693791304 -as sert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove rage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_hmac_enc_jitter_en_reduced_freq.3693791304
Directory	/workspace/0.chip_sw_hmac_enc_jitter_en_reduced_freq/latest

Test location	/workspace/coverage/default/0.chip_sw_hmac_multistream.176420495
Short name	T678
Test name
Test status
Simulation time	7502218756 ps
CPU time	1909.54 seconds
Started	Aug 14 05:49:28 PM PDT 24
Finished	Aug 14 06:21:19 PM PDT 24
Peak memory	609864 kb
Host	smart-33439f7f-80ae-4442-a99a-2ccf1db02624
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=hmac_multistream_functest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=176420495 -assert nopostproc +UVM_TE STNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_lo g /dev/null -cm_name 0.chip_sw_hmac_multistream.176420495
Directory	/workspace/0.chip_sw_hmac_multistream/latest

Test location	/workspace/coverage/default/0.chip_sw_hmac_oneshot.762242814
Short name	T867
Test name
Test status
Simulation time	3241854508 ps
CPU time	435.73 seconds
Started	Aug 14 05:51:37 PM PDT 24
Finished	Aug 14 05:58:53 PM PDT 24
Peak memory	610540 kb
Host	smart-5aa094c3-de3f-422b-9bbc-55b4bc0b5093
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=hmac_functest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=762242814 -assert nopostproc +UVM_TESTNAME=chip_ base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_hmac_oneshot.762242814
Directory	/workspace/0.chip_sw_hmac_oneshot/latest

Test location	/workspace/coverage/default/0.chip_sw_hmac_smoketest.575558340
Short name	T667
Test name
Test status
Simulation time	3259772220 ps
CPU time	336.79 seconds
Started	Aug 14 05:55:09 PM PDT 24
Finished	Aug 14 06:00:46 PM PDT 24
Peak memory	610384 kb
Host	smart-6fd8c2a8-86a4-4aeb-9a74-dbb545423fc3
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=hmac_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=575558340 -assert nopostproc +UVM_TESTNAME=chip _base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_hmac_smoketest.575558340
Directory	/workspace/0.chip_sw_hmac_smoketest/latest

Test location	/workspace/coverage/default/0.chip_sw_i2c_host_tx_rx.3809243311
Short name	T243
Test name
Test status
Simulation time	4911007950 ps
CPU time	816.68 seconds
Started	Aug 14 05:49:42 PM PDT 24
Finished	Aug 14 06:03:19 PM PDT 24
Peak memory	610420 kb
Host	smart-928bfb89-a75e-49a0-af17-58d3c1547af5
User	root
Command	/workspace/default/simv +i2c_idx=0 +sw_build_device=sim_dv +sw_images=i2c_host_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3809243311 -assert nopostproc + UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_i2c_host_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de fault.vdb -cm_log /dev/null -cm_name 0.chip_sw_i2c_host_tx_rx.3809243311
Directory	/workspace/0.chip_sw_i2c_host_tx_rx/latest

Test location	/workspace/coverage/default/0.chip_sw_i2c_host_tx_rx_idx1.532700464
Short name	T357
Test name
Test status
Simulation time	5347496400 ps
CPU time	1031.18 seconds
Started	Aug 14 05:49:14 PM PDT 24
Finished	Aug 14 06:06:27 PM PDT 24
Peak memory	610428 kb
Host	smart-57b6fed4-6232-424d-867b-565d475d6a33
User	root
Command	/workspace/default/simv +i2c_idx=1 +sw_build_device=sim_dv +sw_images=i2c_host_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=532700464 -assert nopostproc +U VM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_i2c_host_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def ault.vdb -cm_log /dev/null -cm_name 0.chip_sw_i2c_host_tx_rx_idx1.532700464
Directory	/workspace/0.chip_sw_i2c_host_tx_rx_idx1/latest

Test location	/workspace/coverage/default/0.chip_sw_inject_scramble_seed.3837426540
Short name	T116
Test name
Test status
Simulation time	65388233605 ps
CPU time	11739.7 seconds
Started	Aug 14 05:50:26 PM PDT 24
Finished	Aug 14 09:06:07 PM PDT 24
Peak memory	625256 kb
Host	smart-7da98725-071e-4021-ad0b-70ae19f14481
User	root
Command	/workspace/default/simv +lc_at_prod=1 +flash_program_latency=5 +sw_test_timeout_ns=150_000_000 +sw_build_device=sim_dv +sw_images=inject_scramble_seed :1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=3837426540 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_inject_scramble_seed_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_inject_scramble_seed.3837426540
Directory	/workspace/0.chip_sw_inject_scramble_seed/latest

Test location	/workspace/coverage/default/0.chip_sw_keymgr_key_derivation.1107188241
Short name	T742
Test name
Test status
Simulation time	8738002696 ps
CPU time	1812.79 seconds
Started	Aug 14 05:48:35 PM PDT 24
Finished	Aug 14 06:18:48 PM PDT 24
Peak memory	618500 kb
Host	smart-dda39f06-170e-4bc8-80af-3f308b408229
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=20_000_000 +sw_build_device=sim_dv +sw_images=keymgr_key_derivation_test:1:new_rules,test_rom:0 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1107 188241 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_keymgr_key_derivation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_keymgr_key_derivation.1107188241
Directory	/workspace/0.chip_sw_keymgr_key_derivation/latest

Test location	/workspace/coverage/default/0.chip_sw_keymgr_key_derivation_jitter_en.2398279031
Short name	T628
Test name
Test status
Simulation time	8777764049 ps
CPU time	1410.91 seconds
Started	Aug 14 05:51:03 PM PDT 24
Finished	Aug 14 06:14:35 PM PDT 24
Peak memory	617156 kb
Host	smart-a7b1bcca-0aef-47ad-8a03-c56aedf2e0cf
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=20_000_000 +en_jitter=1 +sw_build_device=sim_dv +sw_images=keymgr_key_derivation_test:1:new_rules,test_rom :0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=2398279031 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_keymgr_key_derivation_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_keymgr_key_derivation_jitter_en.2398279031
Directory	/workspace/0.chip_sw_keymgr_key_derivation_jitter_en/latest

Test location	/workspace/coverage/default/0.chip_sw_keymgr_key_derivation_jitter_en_reduced_freq.2594216994
Short name	T422
Test name
Test status
Simulation time	12454135951 ps
CPU time	1929.68 seconds
Started	Aug 14 05:50:00 PM PDT 24
Finished	Aug 14 06:22:11 PM PDT 24
Peak memory	618572 kb
Host	smart-e0bc1357-b2c9-4cb5-9e8f-362ef44e49d4
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=20_000_000 +en_jitter=1 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=keymgr_key_derivation_test :1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=2594216994 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_keymgr_key_derivation_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_keymgr_key_derivation_jitter_en _reduced_freq.2594216994
Directory	/workspace/0.chip_sw_keymgr_key_derivation_jitter_en_reduced_freq/latest

Test location	/workspace/coverage/default/0.chip_sw_keymgr_key_derivation_prod.3077351118
Short name	T641
Test name
Test status
Simulation time	6648339416 ps
CPU time	1075.6 seconds
Started	Aug 14 05:52:06 PM PDT 24
Finished	Aug 14 06:10:02 PM PDT 24
Peak memory	618720 kb
Host	smart-614cd55f-fc4e-4709-afe9-0351e23949ad
User	root
Command	/workspace/default/simv +lc_at_prod=1 +sw_test_timeout_ns=20_000_000 +sw_build_device=sim_dv +sw_images=keymgr_key_derivation_test:1:new_rules,test_ro m:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=3077351118 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_keymgr_key_derivation_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_keymgr_key_derivation_prod.3077351118
Directory	/workspace/0.chip_sw_keymgr_key_derivation_prod/latest

Test location	/workspace/coverage/default/0.chip_sw_keymgr_sideload_kmac.1099139874
Short name	T896
Test name
Test status
Simulation time	7699041036 ps
CPU time	1690.6 seconds
Started	Aug 14 05:49:51 PM PDT 24
Finished	Aug 14 06:18:03 PM PDT 24
Peak memory	611764 kb
Host	smart-5c5a7b51-ab00-40ff-8c8e-202fd7ca54d8
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=20_000_000 +sw_build_device=sim_dv +sw_images=keymgr_sideload_kmac_test:1:new_rules,test_rom:0 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10991 39874 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_keymgr_sideload_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_keymgr_sideload_kmac.1099139874
Directory	/workspace/0.chip_sw_keymgr_sideload_kmac/latest

Test location	/workspace/coverage/default/0.chip_sw_kmac_entropy.1348261882
Short name	T943
Test name
Test status
Simulation time	3256428338 ps
CPU time	341.81 seconds
Started	Aug 14 05:50:33 PM PDT 24
Finished	Aug 14 05:56:16 PM PDT 24
Peak memory	610508 kb
Host	smart-a88aa8cf-42e3-41d5-9eee-830da7afc7cc
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=kmac_entropy_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1348261882 -assert nopostproc +UVM_TESTNAME= chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/ null -cm_name 0.chip_sw_kmac_entropy.1348261882
Directory	/workspace/0.chip_sw_kmac_entropy/latest

Test location	/workspace/coverage/default/0.chip_sw_kmac_idle.415368495
Short name	T683
Test name
Test status
Simulation time	2468409026 ps
CPU time	213.05 seconds
Started	Aug 14 05:47:26 PM PDT 24
Finished	Aug 14 05:51:00 PM PDT 24
Peak memory	610472 kb
Host	smart-8a92a9d5-6588-47dd-9e59-3cf5026b9010
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=kmac_idle_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=415368495 -assert nopostproc +UVM_TESTNAME=chip _base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_kmac_idle.415368495
Directory	/workspace/0.chip_sw_kmac_idle/latest

Test location	/workspace/coverage/default/0.chip_sw_kmac_mode_cshake.119801184
Short name	T934
Test name
Test status
Simulation time	3384689118 ps
CPU time	165.58 seconds
Started	Aug 14 05:47:19 PM PDT 24
Finished	Aug 14 05:50:05 PM PDT 24
Peak memory	610116 kb
Host	smart-b73c6b63-48c4-4797-91e8-596aa358b471
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=kmac_mode_cshake_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=119801184 -assert nopostproc +UVM_TESTNA ME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 0.chip_sw_kmac_mode_cshake.119801184
Directory	/workspace/0.chip_sw_kmac_mode_cshake/latest

Test location	/workspace/coverage/default/0.chip_sw_kmac_mode_kmac.34413071
Short name	T1013
Test name
Test status
Simulation time	3124353038 ps
CPU time	362.19 seconds
Started	Aug 14 05:48:47 PM PDT 24
Finished	Aug 14 05:54:49 PM PDT 24
Peak memory	610212 kb
Host	smart-0a0ba9c1-a532-4788-8fe1-74103e4ef71c
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=kmac_mode_kmac_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34413071 -assert nopostproc +UVM_TESTNAME= chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/ null -cm_name 0.chip_sw_kmac_mode_kmac.34413071
Directory	/workspace/0.chip_sw_kmac_mode_kmac/latest

Test location	/workspace/coverage/default/0.chip_sw_kmac_mode_kmac_jitter_en.1854661731
Short name	T571
Test name
Test status
Simulation time	2742150860 ps
CPU time	348.45 seconds
Started	Aug 14 05:50:30 PM PDT 24
Finished	Aug 14 05:56:19 PM PDT 24
Peak memory	610496 kb
Host	smart-bb84e54f-018b-415a-94fc-f54836f9ab24
User	root
Command	/workspace/default/simv +en_jitter=1 +sw_build_device=sim_dv +sw_images=kmac_mode_kmac_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1854661731 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd b -cm_log /dev/null -cm_name 0.chip_sw_kmac_mode_kmac_jitter_en.1854661731
Directory	/workspace/0.chip_sw_kmac_mode_kmac_jitter_en/latest

Test location	/workspace/coverage/default/0.chip_sw_kmac_mode_kmac_jitter_en_reduced_freq.2487322091
Short name	T957
Test name
Test status
Simulation time	3529780709 ps
CPU time	337.74 seconds
Started	Aug 14 05:53:11 PM PDT 24
Finished	Aug 14 05:58:49 PM PDT 24
Peak memory	610496 kb
Host	smart-a7422571-42d5-49b9-871a-e18d3038c195
User	root
Command	/workspace/default/simv +en_jitter=1 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=kmac_mode_kmac_test:1:new_rules,test_rom:0 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24873220 91 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac e/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_kmac_mode_kmac_jitter_en_reduced_freq.2487322091
Directory	/workspace/0.chip_sw_kmac_mode_kmac_jitter_en_reduced_freq/latest

Test location	/workspace/coverage/default/0.chip_sw_kmac_smoketest.3601612900
Short name	T916
Test name
Test status
Simulation time	2695824218 ps
CPU time	281.09 seconds
Started	Aug 14 05:49:02 PM PDT 24
Finished	Aug 14 05:53:44 PM PDT 24
Peak memory	609780 kb
Host	smart-cae414a8-0e9b-4b06-90b2-e68257dad67d
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=kmac_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3601612900 -assert nopostproc +UVM_TESTNAME=chi p_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul l -cm_name 0.chip_sw_kmac_smoketest.3601612900
Directory	/workspace/0.chip_sw_kmac_smoketest/latest

Test location	/workspace/coverage/default/0.chip_sw_lc_ctrl_otp_hw_cfg0.934520610
Short name	T904
Test name
Test status
Simulation time	3538917240 ps
CPU time	312.98 seconds
Started	Aug 14 05:48:33 PM PDT 24
Finished	Aug 14 05:53:47 PM PDT 24
Peak memory	610348 kb
Host	smart-5dca6dfb-bf5d-47f0-b7dc-f88b06710ad3
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=lc_ctrl_otp_hw_cfg0_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=934520610 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_lc_ctrl_otp_hw_cfg0.934520610
Directory	/workspace/0.chip_sw_lc_ctrl_otp_hw_cfg0/latest

Test location	/workspace/coverage/default/0.chip_sw_lc_ctrl_raw_to_scrap.2998505917
Short name	T920
Test name
Test status
Simulation time	3040491826 ps
CPU time	155.97 seconds
Started	Aug 14 05:47:30 PM PDT 24
Finished	Aug 14 05:50:06 PM PDT 24
Peak memory	620576 kb
Host	smart-ffaa6701-0cae-4185-9392-dc8703fbd78d
User	root
Command	/workspace/default/simv +bypass_alert_ready_to_end_check=1 +src_dec_state=DecLcStRaw +sw_build_device=sim_dv +sw_images=lc_ctrl_scrap_test:1:new_rules ,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2998505917 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_scrap_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_lc_ctrl_raw_to_scrap.2998505917
Directory	/workspace/0.chip_sw_lc_ctrl_raw_to_scrap/latest

Test location	/workspace/coverage/default/0.chip_sw_lc_ctrl_rma_to_scrap.618828101
Short name	T217
Test name
Test status
Simulation time	3439552050 ps
CPU time	301.07 seconds
Started	Aug 14 05:48:28 PM PDT 24
Finished	Aug 14 05:53:31 PM PDT 24
Peak memory	622140 kb
Host	smart-17e43700-6b50-4a11-9e22-09d04697b71c
User	root
Command	/workspace/default/simv +bypass_alert_ready_to_end_check=1 +src_dec_state=DecLcStRma +sw_build_device=sim_dv +sw_images=lc_ctrl_scrap_test:1:new_rules ,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=618828101 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_scrap_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_lc_ctrl_rma_to_scrap.618828101
Directory	/workspace/0.chip_sw_lc_ctrl_rma_to_scrap/latest

Test location	/workspace/coverage/default/0.chip_sw_lc_ctrl_test_locked0_to_scrap.2690022368
Short name	T427
Test name
Test status
Simulation time	3836704399 ps
CPU time	163.77 seconds
Started	Aug 14 05:49:12 PM PDT 24
Finished	Aug 14 05:51:57 PM PDT 24
Peak memory	620672 kb
Host	smart-feb097b5-5f5e-4ca1-a6ea-ca9df5f0f028
User	root
Command	/workspace/default/simv +bypass_alert_ready_to_end_check=1 +src_dec_state=DecLcStTestLocked0 +sw_build_device=sim_dv +sw_images=lc_ctrl_scrap_test:1:n ew_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2690022368 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_scrap_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_lc_ctrl_test_locked0_to_scrap.2690022368
Directory	/workspace/0.chip_sw_lc_ctrl_test_locked0_to_scrap/latest

Test location	/workspace/coverage/default/0.chip_sw_lc_ctrl_transition.2973587325
Short name	T212
Test name
Test status
Simulation time	6022925743 ps
CPU time	482.6 seconds
Started	Aug 14 05:51:35 PM PDT 24
Finished	Aug 14 05:59:39 PM PDT 24
Peak memory	622020 kb
Host	smart-21c44627-7cc9-4ff1-92fb-f2f5f1c151f9
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=lc_ctrl_transition_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2973587325 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_transition_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau lt.vdb -cm_log /dev/null -cm_name 0.chip_sw_lc_ctrl_transition.2973587325
Directory	/workspace/0.chip_sw_lc_ctrl_transition/latest

Test location	/workspace/coverage/default/0.chip_sw_lc_ctrl_volatile_raw_unlock.177636348
Short name	T963
Test name
Test status
Simulation time	2037934250 ps
CPU time	147.75 seconds
Started	Aug 14 05:49:26 PM PDT 24
Finished	Aug 14 05:51:55 PM PDT 24
Peak memory	621308 kb
Host	smart-3cfba586-29c5-4ec6-8193-bef477cca4f0
User	root
Command	/workspace/default/simv +use_otp_image=OtpTypeLcStRaw +exp_volatile_raw_unlock_en=0 +sw_build_device=sim_dv +sw_images=lc_ctrl_volatile_raw_unlock_tes t:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/ tools/sim.tcl +ntb_random_seed=177636348 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_volatile_raw_unlock_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_lc_ctrl_volatile_raw_unlock.177636348
Directory	/workspace/0.chip_sw_lc_ctrl_volatile_raw_unlock/latest

Test location	/workspace/coverage/default/0.chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz.245200421
Short name	T436
Test name
Test status
Simulation time	1986193767 ps
CPU time	106.43 seconds
Started	Aug 14 05:49:23 PM PDT 24
Finished	Aug 14 05:51:10 PM PDT 24
Peak memory	618244 kb
Host	smart-2004887c-394a-4eff-a5c2-cc16442ef34a
User	root
Command	/workspace/default/simv +use_otp_image=OtpTypeLcStRaw +chip_clock_source=ChipClockSourceExternal48Mhz +exp_volatile_raw_unlock_en=0 +sw_build_device=s im_dv +sw_images=lc_ctrl_volatile_raw_unlock_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=245200421 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST _SEQ=chip_sw_lc_volatile_raw_unlock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 0.chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz.245200421
Directory	/workspace/0.chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz/latest

Test location	/workspace/coverage/default/0.chip_sw_lc_walkthrough_dev.2879549669
Short name	T942
Test name
Test status
Simulation time	48981709908 ps
CPU time	5617.26 seconds
Started	Aug 14 05:47:26 PM PDT 24
Finished	Aug 14 07:21:05 PM PDT 24
Peak memory	621168 kb
Host	smart-3b5be16f-0dd5-4c18-a17d-37801d7e68ca
User	root
Command	/workspace/default/simv +flash_program_latency=5 +use_otp_image=OtpTypeLcStRaw +dest_dec_state=DecLcStDev +sw_test_timeout_ns=200_000_000 +sw_build_de vice=sim_dv +sw_images=lc_walkthrough_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2879549669 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=c hip_sw_lc_walkthrough_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip _sw_lc_walkthrough_dev.2879549669
Directory	/workspace/0.chip_sw_lc_walkthrough_dev/latest

Test location	/workspace/coverage/default/0.chip_sw_lc_walkthrough_prodend.1644463193
Short name	T663
Test name
Test status
Simulation time	10285592856 ps
CPU time	1033.56 seconds
Started	Aug 14 05:49:26 PM PDT 24
Finished	Aug 14 06:06:41 PM PDT 24
Peak memory	620756 kb
Host	smart-e9342c3f-4f19-4f83-a856-4d5a17f5d9a9
User	root
Command	/workspace/default/simv +flash_program_latency=5 +use_otp_image=OtpTypeLcStRaw +dest_dec_state=DecLcStProdEnd +sw_build_device=sim_dv +sw_images=lc_wa lkthrough_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1644463193 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_walkthrough_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_lc_walkthrough_prodend.1644463193
Directory	/workspace/0.chip_sw_lc_walkthrough_prodend/latest

Test location	/workspace/coverage/default/0.chip_sw_lc_walkthrough_rma.2145703450
Short name	T950
Test name
Test status
Simulation time	47055787186 ps
CPU time	5056.96 seconds
Started	Aug 14 05:48:31 PM PDT 24
Finished	Aug 14 07:12:49 PM PDT 24
Peak memory	621116 kb
Host	smart-028b6536-2ba3-4f07-a12a-17d72255a89c
User	root
Command	/workspace/default/simv +use_otp_image=OtpTypeLcStRaw +dest_dec_state=DecLcStRma +flash_program_latency=5 +sw_test_timeout_ns=200_000_000 +sw_build_de vice=sim_dv +sw_images=lc_walkthrough_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2145703450 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=c hip_sw_lc_walkthrough_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip _sw_lc_walkthrough_rma.2145703450
Directory	/workspace/0.chip_sw_lc_walkthrough_rma/latest

Test location	/workspace/coverage/default/0.chip_sw_lc_walkthrough_testunlocks.3167604564
Short name	T779
Test name
Test status
Simulation time	27979822839 ps
CPU time	2287.54 seconds
Started	Aug 14 05:50:55 PM PDT 24
Finished	Aug 14 06:29:03 PM PDT 24
Peak memory	622056 kb
Host	smart-a2900749-a1cb-4ec4-b5dc-ed8993d26365
User	root
Command	/workspace/default/simv +use_otp_image=OtpTypeLcStRaw +dest_dec_state=DecLcStTestUnlock7 +sw_build_device=sim_dv +sw_images=lc_walkthrough_testunlocks _test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=3167604564 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_walkthrough_testunlocks_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_lc_walkthrough_testun locks.3167604564
Directory	/workspace/0.chip_sw_lc_walkthrough_testunlocks/latest

Test location	/workspace/coverage/default/0.chip_sw_otbn_ecdsa_op_irq.302520154
Short name	T973
Test name
Test status
Simulation time	17779718600 ps
CPU time	3657.47 seconds
Started	Aug 14 05:50:14 PM PDT 24
Finished	Aug 14 06:51:13 PM PDT 24
Peak memory	611064 kb
Host	smart-5b9b191b-1052-4b50-a692-b425516f31b0
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=28_000_000 +rng_srate_value=30 +sw_build_device=sim_dv +sw_images=otbn_ecdsa_op_irq_test:1:new_rules,test_ rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ random_seed=302520154 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_otbn_ecdsa_op_irq.302520154
Directory	/workspace/0.chip_sw_otbn_ecdsa_op_irq/latest

Test location	/workspace/coverage/default/0.chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq.44683396
Short name	T141
Test name
Test status
Simulation time	24642960493 ps
CPU time	3346.6 seconds
Started	Aug 14 05:52:33 PM PDT 24
Finished	Aug 14 06:48:20 PM PDT 24
Peak memory	611028 kb
Host	smart-ea2149f7-2aea-4ba9-86f5-755fb0bd2753
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=33_000_000 +rng_srate_value=30 +en_jitter=1 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=otbn_e cdsa_op_irq_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/ repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=44683396 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_otbn_ecdsa_op_irq_jitter_en_reduce d_freq.44683396
Directory	/workspace/0.chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq/latest

Test location	/workspace/coverage/default/0.chip_sw_otbn_mem_scramble.2866543325
Short name	T785
Test name
Test status
Simulation time	3637555860 ps
CPU time	650.48 seconds
Started	Aug 14 05:48:56 PM PDT 24
Finished	Aug 14 05:59:47 PM PDT 24
Peak memory	610280 kb
Host	smart-6ec58c63-6a2c-4b62-950b-d429ef559afe
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=15_000_000 +en_scb_tl_err_chk=0 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=otbn _mem_scramble_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2866543325 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_otbn_mem_scramble.2866543325
Directory	/workspace/0.chip_sw_otbn_mem_scramble/latest

Test location	/workspace/coverage/default/0.chip_sw_otbn_randomness.476327122
Short name	T923
Test name
Test status
Simulation time	6313778048 ps
CPU time	1029.33 seconds
Started	Aug 14 05:51:48 PM PDT 24
Finished	Aug 14 06:08:58 PM PDT 24
Peak memory	611132 kb
Host	smart-7270a59a-e1b0-4069-8d96-def152943561
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=18_000_000 +rng_srate_value=30 +sw_build_device=sim_dv +sw_images=otbn_randomness_test:1:new_rules,test_ro m:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=476327122 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_otbn_randomness.476327122
Directory	/workspace/0.chip_sw_otbn_randomness/latest

Test location	/workspace/coverage/default/0.chip_sw_otbn_smoketest.1373602486
Short name	T917
Test name
Test status
Simulation time	6218853064 ps
CPU time	1568.61 seconds
Started	Aug 14 05:54:11 PM PDT 24
Finished	Aug 14 06:20:21 PM PDT 24
Peak memory	609900 kb
Host	smart-1930cc2f-a52c-4abd-890e-a07da2b6aed4
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=otbn_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1373602486 -assert nopostproc +UVM_TESTNAME=chi p_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul l -cm_name 0.chip_sw_otbn_smoketest.1373602486
Directory	/workspace/0.chip_sw_otbn_smoketest/latest

Test location	/workspace/coverage/default/0.chip_sw_otp_ctrl_dai_lock.4247762464
Short name	T994
Test name
Test status
Simulation time	27941474400 ps
CPU time	5471.08 seconds
Started	Aug 14 05:49:14 PM PDT 24
Finished	Aug 14 07:20:26 PM PDT 24
Peak memory	609876 kb
Host	smart-1a5777f6-367d-42a4-ab22-2b619ad1104b
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=30_000_000 +sw_build_device=sim_dv +sw_images=otp_ctrl_mem_access_test:1:new_rules,test_rom:0 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=424776 2464 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_otp_ctrl_dai_lock.4247762464
Directory	/workspace/0.chip_sw_otp_ctrl_dai_lock/latest

Test location	/workspace/coverage/default/0.chip_sw_otp_ctrl_ecc_error_vendor_test.636380354
Short name	T871
Test name
Test status
Simulation time	3235618798 ps
CPU time	245.42 seconds
Started	Aug 14 05:47:02 PM PDT 24
Finished	Aug 14 05:51:09 PM PDT 24
Peak memory	610568 kb
Host	smart-51d5e7ab-4f15-412d-a734-0ce6d70c9b75
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=otp_ctrl_vendor_test_ecc_error_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=636380354 -assert nopostpr oc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_otp_ctrl_vendor_test_ecc_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_otp_ctrl_ecc_error_vendor_test.636380354
Directory	/workspace/0.chip_sw_otp_ctrl_ecc_error_vendor_test/latest

Test location	/workspace/coverage/default/0.chip_sw_otp_ctrl_lc_signals_dev.1131071579
Short name	T885
Test name
Test status
Simulation time	8485555300 ps
CPU time	1317.87 seconds
Started	Aug 14 05:52:25 PM PDT 24
Finished	Aug 14 06:14:24 PM PDT 24
Peak memory	611344 kb
Host	smart-bb3afc36-d0a2-4b3c-b49f-71ca49f85177
User	root
Command	/workspace/default/simv +use_otp_image=OtpTypeLcStDev +otp_clear_secret2=1 +sw_build_device=sim_dv +sw_images=otp_ctrl_lc_signals_test:1:new_rules,tes t_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +nt b_random_seed=1131071579 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_otp_ctrl_lc_signals_dev.1131071579
Directory	/workspace/0.chip_sw_otp_ctrl_lc_signals_dev/latest

Test location	/workspace/coverage/default/0.chip_sw_otp_ctrl_lc_signals_prod.2580928431
Short name	T192
Test name
Test status
Simulation time	6768073520 ps
CPU time	1294.74 seconds
Started	Aug 14 05:49:04 PM PDT 24
Finished	Aug 14 06:10:41 PM PDT 24
Peak memory	611380 kb
Host	smart-327d3974-9434-413f-8b7c-2e6b96593ab5
User	root
Command	/workspace/default/simv +use_otp_image=OtpTypeLcStProd +otp_clear_secret2=1 +sw_build_device=sim_dv +sw_images=otp_ctrl_lc_signals_test:1:new_rules,te st_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n tb_random_seed=2580928431 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_otp_ctrl_lc_signals_prod.2580928431
Directory	/workspace/0.chip_sw_otp_ctrl_lc_signals_prod/latest

Test location	/workspace/coverage/default/0.chip_sw_otp_ctrl_lc_signals_rma.3983293570
Short name	T803
Test name
Test status
Simulation time	9482986046 ps
CPU time	1473.8 seconds
Started	Aug 14 05:51:45 PM PDT 24
Finished	Aug 14 06:16:19 PM PDT 24
Peak memory	611392 kb
Host	smart-4966addd-220e-4fe4-8183-ff3f7f3a984a
User	root
Command	/workspace/default/simv +use_otp_image=OtpTypeLcStRma +otp_clear_secret2=1 +sw_build_device=sim_dv +sw_images=otp_ctrl_lc_signals_test:1:new_rules,tes t_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +nt b_random_seed=3983293570 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_otp_ctrl_lc_signals_rma.3983293570
Directory	/workspace/0.chip_sw_otp_ctrl_lc_signals_rma/latest

Test location	/workspace/coverage/default/0.chip_sw_otp_ctrl_lc_signals_test_unlocked0.1724038891
Short name	T652
Test name
Test status
Simulation time	4762501558 ps
CPU time	813.02 seconds
Started	Aug 14 05:47:55 PM PDT 24
Finished	Aug 14 06:01:28 PM PDT 24
Peak memory	610588 kb
Host	smart-73dc1fb9-45d0-4af9-b7f7-b44c6033f8bf
User	root
Command	/workspace/default/simv +use_otp_image=OtpTypeLcStTestUnlocked0 +otp_clear_secret2=1 +sw_build_device=sim_dv +sw_images=otp_ctrl_lc_signals_test:1:new _rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/s im.tcl +ntb_random_seed=1724038891 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_otp_ctrl_lc_signals_test_unlocked0.1724038891
Directory	/workspace/0.chip_sw_otp_ctrl_lc_signals_test_unlocked0/latest

Test location	/workspace/coverage/default/0.chip_sw_otp_ctrl_smoketest.4028148860
Short name	T924
Test name
Test status
Simulation time	2795872332 ps
CPU time	233.95 seconds
Started	Aug 14 05:54:57 PM PDT 24
Finished	Aug 14 05:58:51 PM PDT 24
Peak memory	610420 kb
Host	smart-c64e644a-81ba-4945-b544-f2f0f3f52a6f
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=otp_ctrl_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4028148860 -assert nopostproc +UVM_TESTNAME =chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 0.chip_sw_otp_ctrl_smoketest.4028148860
Directory	/workspace/0.chip_sw_otp_ctrl_smoketest/latest

Test location	/workspace/coverage/default/0.chip_sw_pattgen_ios.1530196012
Short name	T316
Test name
Test status
Simulation time	3097590356 ps
CPU time	214.13 seconds
Started	Aug 14 05:49:34 PM PDT 24
Finished	Aug 14 05:53:10 PM PDT 24
Peak memory	614076 kb
Host	smart-e0df1591-df2b-4940-9242-d1bf612184bb
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=5_000_000 +sw_build_device=sim_dv +sw_images=pattgen_ios_test:1:new_rules,test_rom:0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1530196012 -ass ert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_patt_ios_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/c overage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_pattgen_ios.1530196012
Directory	/workspace/0.chip_sw_pattgen_ios/latest

Test location	/workspace/coverage/default/0.chip_sw_power_idle_load.3561125195
Short name	T154
Test name
Test status
Simulation time	4733308218 ps
CPU time	669.15 seconds
Started	Aug 14 05:52:05 PM PDT 24
Finished	Aug 14 06:03:14 PM PDT 24
Peak memory	610888 kb
Host	smart-07f711e4-e928-4cf9-aa2b-270aca31a9aa
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=chip_power_idle_load:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3561125195 -assert nopostproc +UVM_TESTNA ME=chip_base_test +UVM_TEST_SEQ=chip_sw_power_idle_load_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_power_idle_load.3561125195
Directory	/workspace/0.chip_sw_power_idle_load/latest

Test location	/workspace/coverage/default/0.chip_sw_power_sleep_load.728071719
Short name	T317
Test name
Test status
Simulation time	11256019640 ps
CPU time	444.91 seconds
Started	Aug 14 05:50:25 PM PDT 24
Finished	Aug 14 05:57:51 PM PDT 24
Peak memory	610700 kb
Host	smart-165002cf-7e9d-485b-83bc-c3d9cd24a4be
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=chip_power_sleep_load:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=728071719 -assert nopostproc +UVM_TESTNA ME=chip_base_test +UVM_TEST_SEQ=chip_sw_power_sleep_load_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd b -cm_log /dev/null -cm_name 0.chip_sw_power_sleep_load.728071719
Directory	/workspace/0.chip_sw_power_sleep_load/latest

Test location	/workspace/coverage/default/0.chip_sw_pwrmgr_all_reset_reqs.2538806786
Short name	T991
Test name
Test status
Simulation time	12392093476 ps
CPU time	1701.54 seconds
Started	Aug 14 05:49:11 PM PDT 24
Finished	Aug 14 06:17:33 PM PDT 24
Peak memory	612100 kb
Host	smart-cbfe916c-7231-4326-91e2-8877302fd9f7
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=50_000_000 +sw_build_device=sim_dv +sw_images=pwrmgr_all_reset_reqs_test:1:new_rules,test_rom:0 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2538 806786 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_deep_sleep_all_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_pwrmgr_all_reset_reqs.2538806786
Directory	/workspace/0.chip_sw_pwrmgr_all_reset_reqs/latest

Test location	/workspace/coverage/default/0.chip_sw_pwrmgr_b2b_sleep_reset_req.70306758
Short name	T574
Test name
Test status
Simulation time	27991579115 ps
CPU time	2550.96 seconds
Started	Aug 14 05:49:39 PM PDT 24
Finished	Aug 14 06:32:11 PM PDT 24
Peak memory	611548 kb
Host	smart-ba336b82-e212-4f3c-985b-f4c494078ed0
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=35_000_000 +sw_build_device=sim_dv +sw_images=pwrmgr_b2b_sleep_reset_test:1:new_rules,test_rom:0 +cdc_inst rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=703 06758 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_repeat_reset_wkup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_pwrmgr_b2b_sleep_reset_req.70306758
Directory	/workspace/0.chip_sw_pwrmgr_b2b_sleep_reset_req/latest

Test location	/workspace/coverage/default/0.chip_sw_pwrmgr_deep_sleep_all_reset_reqs.3594397779
Short name	T400
Test name
Test status
Simulation time	15850398469 ps
CPU time	1762.39 seconds
Started	Aug 14 05:51:04 PM PDT 24
Finished	Aug 14 06:20:28 PM PDT 24
Peak memory	612244 kb
Host	smart-ac1eb724-21ce-48a7-9def-ee8127f37c1b
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=50_000_000 +sw_build_device=sim_dv +sw_images=pwrmgr_deep_sleep_all_reset_reqs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=3594397779 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_deep_sleep_all_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_pwrmgr_deep_sleep_all_reset_reqs.3594397779
Directory	/workspace/0.chip_sw_pwrmgr_deep_sleep_all_reset_reqs/latest

Test location	/workspace/coverage/default/0.chip_sw_pwrmgr_deep_sleep_all_wake_ups.141241280
Short name	T409
Test name
Test status
Simulation time	22295598306 ps
CPU time	1683.03 seconds
Started	Aug 14 05:51:37 PM PDT 24
Finished	Aug 14 06:19:41 PM PDT 24
Peak memory	611240 kb
Host	smart-978bac6a-9b1d-48db-b7bb-1a7d3ac44f36
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=pwrmgr_deep_sleep_all_wake_ups:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 141241280 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_pwrmgr_deep_sleep_all_wake_ups_vseq +en_cov=1 -cm line+cond+fsm+tg l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_pwrmgr_deep_sleep_all_wake_ups.141241280
Directory	/workspace/0.chip_sw_pwrmgr_deep_sleep_all_wake_ups/latest

Test location	/workspace/coverage/default/0.chip_sw_pwrmgr_deep_sleep_por_reset.2985225693
Short name	T996
Test name
Test status
Simulation time	7305180798 ps
CPU time	961.26 seconds
Started	Aug 14 05:48:24 PM PDT 24
Finished	Aug 14 06:04:26 PM PDT 24
Peak memory	611584 kb
Host	smart-ab01ca17-a041-482a-ab5f-dafb697e06f7
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_deep_sleep_por_reset_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2985225693 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sleep_por_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage /default.vdb -cm_log /dev/null -cm_name 0.chip_sw_pwrmgr_deep_sleep_por_reset.2985225693
Directory	/workspace/0.chip_sw_pwrmgr_deep_sleep_por_reset/latest

Test location	/workspace/coverage/default/0.chip_sw_pwrmgr_main_power_glitch_reset.2627083137
Short name	T600
Test name
Test status
Simulation time	4648493354 ps
CPU time	331.57 seconds
Started	Aug 14 05:51:37 PM PDT 24
Finished	Aug 14 05:57:10 PM PDT 24
Peak memory	618176 kb
Host	smart-32b9f745-76fe-4885-8131-37bacc51b053
User	root
Command	/workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=pwrmgr_main_power_glitch_test:1:new_rules,test_rom:0 +cd c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se ed=2627083137 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_main_power_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_pwrmgr_main_power_glitch_reset.2627083137
Directory	/workspace/0.chip_sw_pwrmgr_main_power_glitch_reset/latest

Test location	/workspace/coverage/default/0.chip_sw_pwrmgr_normal_sleep_all_wake_ups.478038316
Short name	T117
Test name
Test status
Simulation time	7591967674 ps
CPU time	424.25 seconds
Started	Aug 14 05:52:05 PM PDT 24
Finished	Aug 14 05:59:12 PM PDT 24
Peak memory	611116 kb
Host	smart-41cc5c60-4d4a-4bd9-b742-de3ce5459c35
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_normal_sleep_all_wake_ups:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=478038316 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_pwrmgr_deep_sleep_all_wake_ups_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work space/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_pwrmgr_normal_sleep_all_wake_ups.478038316
Directory	/workspace/0.chip_sw_pwrmgr_normal_sleep_all_wake_ups/latest

Test location	/workspace/coverage/default/0.chip_sw_pwrmgr_normal_sleep_por_reset.2878896442
Short name	T793
Test name
Test status
Simulation time	6220135805 ps
CPU time	912.67 seconds
Started	Aug 14 05:51:22 PM PDT 24
Finished	Aug 14 06:06:36 PM PDT 24
Peak memory	611524 kb
Host	smart-ab048031-8f7b-4985-a921-fc48da45b038
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_normal_sleep_por_reset_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2878896442 -assert nopostpr oc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sleep_por_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera ge/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_pwrmgr_normal_sleep_por_reset.2878896442
Directory	/workspace/0.chip_sw_pwrmgr_normal_sleep_por_reset/latest

Test location	/workspace/coverage/default/0.chip_sw_pwrmgr_random_sleep_all_reset_reqs.1599668228
Short name	T668
Test name
Test status
Simulation time	22291520785 ps
CPU time	2686.16 seconds
Started	Aug 14 05:50:51 PM PDT 24
Finished	Aug 14 06:35:38 PM PDT 24
Peak memory	612260 kb
Host	smart-9aa62046-5e4d-43ff-a9c0-f1ebf694c0ea
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=50_000_000 +sw_build_device=sim_dv +sw_images=pwrmgr_random_sleep_all_reset_reqs_test:1:new_rules,test_rom :0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=1599668228 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_deep_sleep_all_reset_vseq +en_cov=1 -cm line+cond+fsm+tg l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_pwrmgr_random_sleep_all_reset_reqs.1599668228
Directory	/workspace/0.chip_sw_pwrmgr_random_sleep_all_reset_reqs/latest

Test location	/workspace/coverage/default/0.chip_sw_pwrmgr_random_sleep_power_glitch_reset.2413844638
Short name	T889
Test name
Test status
Simulation time	39499568418 ps
CPU time	3052.3 seconds
Started	Aug 14 05:48:48 PM PDT 24
Finished	Aug 14 06:39:42 PM PDT 24
Peak memory	612692 kb
Host	smart-079b089d-da95-46b4-a2a7-1a84c4179e01
User	root
Command	/workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_test_timeout_ns=24_000_000 +sw_build_device=sim_dv +sw_images=pwrmgr_random_sleep_power _glitch_reset_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2413844638 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_random_power_glit ch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_pwrmgr_random_s leep_power_glitch_reset.2413844638
Directory	/workspace/0.chip_sw_pwrmgr_random_sleep_power_glitch_reset/latest

Test location	/workspace/coverage/default/0.chip_sw_pwrmgr_sleep_disabled.874808983
Short name	T305
Test name
Test status
Simulation time	2785283844 ps
CPU time	331.88 seconds
Started	Aug 14 05:48:27 PM PDT 24
Finished	Aug 14 05:53:59 PM PDT 24
Peak memory	610512 kb
Host	smart-3a737344-b90b-446f-bc20-b3382a732096
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_sleep_disabled_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=874808983 -assert nopostproc +UVM_T ESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l og /dev/null -cm_name 0.chip_sw_pwrmgr_sleep_disabled.874808983
Directory	/workspace/0.chip_sw_pwrmgr_sleep_disabled/latest

Test location	/workspace/coverage/default/0.chip_sw_pwrmgr_sleep_power_glitch_reset.1007881920
Short name	T616
Test name
Test status
Simulation time	4493716405 ps
CPU time	589.48 seconds
Started	Aug 14 05:51:50 PM PDT 24
Finished	Aug 14 06:01:41 PM PDT 24
Peak memory	618468 kb
Host	smart-6923c05b-b840-438e-8da1-3d391b4aac8a
User	root
Command	/workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=pwrmgr_sleep_power_glitch_test:1:new_rules,test_rom:0 +c dc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_s eed=1007881920 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_main_power_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_pwrmgr_sleep_power_glitch_reset.1007881920
Directory	/workspace/0.chip_sw_pwrmgr_sleep_power_glitch_reset/latest

Test location	/workspace/coverage/default/0.chip_sw_pwrmgr_sleep_wake_5_bug.2031637400
Short name	T149
Test name
Test status
Simulation time	5766632954 ps
CPU time	645.88 seconds
Started	Aug 14 05:48:08 PM PDT 24
Finished	Aug 14 05:58:54 PM PDT 24
Peak memory	611224 kb
Host	smart-3dc4afd9-ba19-4245-9c38-a61c53c1b98e
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=18_000_000 +do_random=1 +sw_build_device=sim_dv +sw_images=pwrmgr_sleep_wake_5_bug_test:1:new_rules,test_r om:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r andom_seed=2031637400 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_pwrmgr_sleep_wake_5_bug.2031637400
Directory	/workspace/0.chip_sw_pwrmgr_sleep_wake_5_bug/latest

Test location	/workspace/coverage/default/0.chip_sw_pwrmgr_smoketest.1520923073
Short name	T593
Test name
Test status
Simulation time	5541602256 ps
CPU time	365.09 seconds
Started	Aug 14 05:49:31 PM PDT 24
Finished	Aug 14 05:55:36 PM PDT 24
Peak memory	610372 kb
Host	smart-06998e89-63b0-40f9-a75a-e460af9beff8
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=10000000 +sw_build_device=sim_dv +sw_images=pwrmgr_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1520923073 -asse rt nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera ge/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_pwrmgr_smoketest.1520923073
Directory	/workspace/0.chip_sw_pwrmgr_smoketest/latest

Test location	/workspace/coverage/default/0.chip_sw_pwrmgr_sysrst_ctrl_reset.3140059963
Short name	T949
Test name
Test status
Simulation time	7731209212 ps
CPU time	956.61 seconds
Started	Aug 14 05:50:23 PM PDT 24
Finished	Aug 14 06:06:21 PM PDT 24
Peak memory	610256 kb
Host	smart-4af068b4-1bbe-4475-a93e-7675f52df870
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_sysrst_ctrl_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3140059963 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sysrst_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_pwrmgr_sysrst_ctrl_reset.3140059963
Directory	/workspace/0.chip_sw_pwrmgr_sysrst_ctrl_reset/latest

Test location	/workspace/coverage/default/0.chip_sw_pwrmgr_usb_clk_disabled_when_active.3125568848
Short name	T177
Test name
Test status
Simulation time	4602156776 ps
CPU time	484.09 seconds
Started	Aug 14 05:47:48 PM PDT 24
Finished	Aug 14 05:55:53 PM PDT 24
Peak memory	611172 kb
Host	smart-48b888ad-a4d9-43d8-841f-2f5c66285b00
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_usb_clk_disabled_when_active_test:1:new_rules,test_rom:0 +cdc_instrumentation_enable d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3125568848 -assert no postproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de fault.vdb -cm_log /dev/null -cm_name 0.chip_sw_pwrmgr_usb_clk_disabled_when_active.3125568848
Directory	/workspace/0.chip_sw_pwrmgr_usb_clk_disabled_when_active/latest

Test location	/workspace/coverage/default/0.chip_sw_pwrmgr_usbdev_smoketest.2977217829
Short name	T673
Test name
Test status
Simulation time	5995832590 ps
CPU time	638.22 seconds
Started	Aug 14 05:54:01 PM PDT 24
Finished	Aug 14 06:04:40 PM PDT 24
Peak memory	610360 kb
Host	smart-390a58f6-9ffe-4411-b3b5-08e3142b61da
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_usbdev_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2977217829 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_pwrmgr_usbdev_smoketest.2977217829
Directory	/workspace/0.chip_sw_pwrmgr_usbdev_smoketest/latest

Test location	/workspace/coverage/default/0.chip_sw_pwrmgr_wdog_reset.1781887503
Short name	T940
Test name
Test status
Simulation time	4984277750 ps
CPU time	628.52 seconds
Started	Aug 14 05:50:45 PM PDT 24
Finished	Aug 14 06:01:14 PM PDT 24
Peak memory	611172 kb
Host	smart-c53ddab1-5ebc-4983-8499-c177553c98c9
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=pwrmgr_wdog_reset_reqs_test:1:new_rules,test_rom:0 +cdc_inst rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=178 1887503 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_pwrmgr_wdog_reset.1781887503
Directory	/workspace/0.chip_sw_pwrmgr_wdog_reset/latest

Test location	/workspace/coverage/default/0.chip_sw_rom_ctrl_integrity_check.3623465937
Short name	T903
Test name
Test status
Simulation time	9087142212 ps
CPU time	507.02 seconds
Started	Aug 14 05:50:13 PM PDT 24
Finished	Aug 14 05:58:41 PM PDT 24
Peak memory	624280 kb
Host	smart-7d969d46-bafd-4f3b-93dc-97b98e6eb6dc
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=rom_ctrl_integrity_check_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3623465937 -assert nopostproc +U VM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rom_ctrl_integrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co verage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_rom_ctrl_integrity_check.3623465937
Directory	/workspace/0.chip_sw_rom_ctrl_integrity_check/latest

Test location	/workspace/coverage/default/0.chip_sw_rstmgr_rst_cnsty_escalation.4088419619
Short name	T471
Test name
Test status
Simulation time	4834423550 ps
CPU time	725.26 seconds
Started	Aug 14 05:49:53 PM PDT 24
Finished	Aug 14 06:02:00 PM PDT 24
Peak memory	642428 kb
Host	smart-a0e3bfe8-96a5-46e7-ba2a-5b6db1b0583f
User	root
Command	/workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 4088419619 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rstmgr_cnsty_fault_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_rstmgr_rst_cnsty_escalation.4088419619
Directory	/workspace/0.chip_sw_rstmgr_rst_cnsty_escalation/latest

Test location	/workspace/coverage/default/0.chip_sw_rstmgr_smoketest.1804841041
Short name	T576
Test name
Test status
Simulation time	2664388960 ps
CPU time	267.06 seconds
Started	Aug 14 05:51:44 PM PDT 24
Finished	Aug 14 05:56:11 PM PDT 24
Peak memory	610268 kb
Host	smart-4e708aec-5f34-42a4-945d-b235024ea4a2
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=rstmgr_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1804841041 -assert nopostproc +UVM_TESTNAME=c hip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n ull -cm_name 0.chip_sw_rstmgr_smoketest.1804841041
Directory	/workspace/0.chip_sw_rstmgr_smoketest/latest

Test location	/workspace/coverage/default/0.chip_sw_rstmgr_sw_req.4195015329
Short name	T420
Test name
Test status
Simulation time	4669903944 ps
CPU time	509.31 seconds
Started	Aug 14 05:49:17 PM PDT 24
Finished	Aug 14 05:57:47 PM PDT 24
Peak memory	610300 kb
Host	smart-e1e01350-a5e4-429f-8dce-df0c2307b723
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=rstmgr_sw_req_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4195015329 -assert nopostproc +UVM_TESTNAME =chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 0.chip_sw_rstmgr_sw_req.4195015329
Directory	/workspace/0.chip_sw_rstmgr_sw_req/latest

Test location	/workspace/coverage/default/0.chip_sw_rstmgr_sw_rst.1787047119
Short name	T238
Test name
Test status
Simulation time	2796450550 ps
CPU time	295.78 seconds
Started	Aug 14 05:46:57 PM PDT 24
Finished	Aug 14 05:51:53 PM PDT 24
Peak memory	610492 kb
Host	smart-e3afdad2-abe8-4044-88b3-953f0a3bf239
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=rstmgr_sw_rst_ctrl_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1787047119 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_rstmgr_sw_rst.1787047119
Directory	/workspace/0.chip_sw_rstmgr_sw_rst/latest

Test location	/workspace/coverage/default/0.chip_sw_rv_core_ibex_address_translation.38789760
Short name	T309
Test name
Test status
Simulation time	3539062698 ps
CPU time	311.26 seconds
Started	Aug 14 05:52:15 PM PDT 24
Finished	Aug 14 05:57:27 PM PDT 24
Peak memory	610512 kb
Host	smart-5d1c8d57-aff7-4afd-82d8-4a00b69f94e5
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=7_000_000 +sw_build_device=sim_dv +sw_images=rv_core_ibex_address_translation_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random _seed=38789760 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_rv_core_ibex_address_translation.38789760
Directory	/workspace/0.chip_sw_rv_core_ibex_address_translation/latest

Test location	/workspace/coverage/default/0.chip_sw_rv_core_ibex_icache_invalidate.2638231273
Short name	T220
Test name
Test status
Simulation time	2772548143 ps
CPU time	225.63 seconds
Started	Aug 14 05:51:06 PM PDT 24
Finished	Aug 14 05:54:52 PM PDT 24
Peak memory	610524 kb
Host	smart-9a5aeb1c-3c00-4ad9-baa5-9550fd10cf8a
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=rv_core_ibex_icache_invalidate_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2638231273 -assert nopostp roc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rv_core_ibex_icache_invalidate_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_rv_core_ibex_icache_invalidate.2638231273
Directory	/workspace/0.chip_sw_rv_core_ibex_icache_invalidate/latest

Test location	/workspace/coverage/default/0.chip_sw_rv_core_ibex_lockstep_glitch.1844381192
Short name	T259
Test name
Test status
Simulation time	2302110592 ps
CPU time	161.9 seconds
Started	Aug 14 05:51:35 PM PDT 24
Finished	Aug 14 05:54:18 PM PDT 24
Peak memory	634680 kb
Host	smart-b5908fd7-f1ab-4f8a-82a6-6bd6826e50a8
User	root
Command	/workspace/default/simv +disable_assert_final_checks +sw_build_device=sim_dv +sw_images=aes_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1844381192 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rv_core_ibex_lockstep_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_rv_core_ibex_lockstep_glitch.1844381192
Directory	/workspace/0.chip_sw_rv_core_ibex_lockstep_glitch/latest

Test location	/workspace/coverage/default/0.chip_sw_rv_core_ibex_rnd.1690499104
Short name	T681
Test name
Test status
Simulation time	5306447856 ps
CPU time	1194.82 seconds
Started	Aug 14 05:50:45 PM PDT 24
Finished	Aug 14 06:10:40 PM PDT 24
Peak memory	609476 kb
Host	smart-8d5c6151-25eb-41d4-a82d-c5c2a18e34c8
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=20_000_000 +rng_srate_value_max=32 +sw_build_device=sim_dv +sw_images=rv_core_ibex_rnd_test:1:new_rules,te st_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n tb_random_seed=1690499104 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_rv_core_ibex_rnd.1690499104
Directory	/workspace/0.chip_sw_rv_core_ibex_rnd/latest

Test location	/workspace/coverage/default/0.chip_sw_rv_dm_access_after_wakeup.572101036
Short name	T9
Test name
Test status
Simulation time	7376354268 ps
CPU time	594.09 seconds
Started	Aug 14 05:51:02 PM PDT 24
Finished	Aug 14 06:00:57 PM PDT 24
Peak memory	621244 kb
Host	smart-adbd8661-0b44-4a23-a7cb-7aa485a94c50
User	root
Command	/workspace/default/simv +use_jtag_dmi=1 +sw_build_device=sim_dv +sw_images=rv_dm_access_after_wakeup_rma:1:new_rules,test_rom:0 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=572101036 -asser t nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rv_dm_access_after_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_rv_dm_access_after_wakeup.572101036
Directory	/workspace/0.chip_sw_rv_dm_access_after_wakeup/latest

Test location	/workspace/coverage/default/0.chip_sw_rv_plic_smoketest.3773010433
Short name	T989
Test name
Test status
Simulation time	2875357320 ps
CPU time	363.66 seconds
Started	Aug 14 05:51:11 PM PDT 24
Finished	Aug 14 05:57:15 PM PDT 24
Peak memory	610104 kb
Host	smart-7c3d0f02-9191-4526-8107-113b5797d2df
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=rv_plic_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3773010433 -assert nopostproc +UVM_TESTNAME= chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/ null -cm_name 0.chip_sw_rv_plic_smoketest.3773010433
Directory	/workspace/0.chip_sw_rv_plic_smoketest/latest

Test location	/workspace/coverage/default/0.chip_sw_rv_timer_irq.3972068454
Short name	T925
Test name
Test status
Simulation time	3273635312 ps
CPU time	354.42 seconds
Started	Aug 14 05:49:06 PM PDT 24
Finished	Aug 14 05:55:00 PM PDT 24
Peak memory	610384 kb
Host	smart-376d14fd-a46a-4604-8b3e-4a25c3d29fcc
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=rv_timer_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3972068454 -assert nopostproc +UVM_TESTNAME =chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 0.chip_sw_rv_timer_irq.3972068454
Directory	/workspace/0.chip_sw_rv_timer_irq/latest

Test location	/workspace/coverage/default/0.chip_sw_rv_timer_smoketest.1232080088
Short name	T978
Test name
Test status
Simulation time	2923975432 ps
CPU time	206.2 seconds
Started	Aug 14 05:49:01 PM PDT 24
Finished	Aug 14 05:52:28 PM PDT 24
Peak memory	610396 kb
Host	smart-22f86478-c1fb-426a-bf13-d2cc3c418d76
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=rv_timer_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1232080088 -assert nopostproc +UVM_TESTNAME =chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 0.chip_sw_rv_timer_smoketest.1232080088
Directory	/workspace/0.chip_sw_rv_timer_smoketest/latest

Test location	/workspace/coverage/default/0.chip_sw_sensor_ctrl_status.2489665975
Short name	T126
Test name
Test status
Simulation time	2926595455 ps
CPU time	344.79 seconds
Started	Aug 14 05:52:40 PM PDT 24
Finished	Aug 14 05:58:26 PM PDT 24
Peak memory	611500 kb
Host	smart-74d4279e-eed3-40d0-98e6-3f141df34185
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=40_000_000 +sw_build_device=sim_dv +sw_images=sensor_ctrl_status_test:1:new_rules,test_rom:0 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2489665 975 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sensor_ctrl_status_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_sensor_ctrl_status.2489665975
Directory	/workspace/0.chip_sw_sensor_ctrl_status/latest

Test location	/workspace/coverage/default/0.chip_sw_sleep_pin_retention.429939694
Short name	T79
Test name
Test status
Simulation time	3135395516 ps
CPU time	293.68 seconds
Started	Aug 14 05:48:38 PM PDT 24
Finished	Aug 14 05:53:32 PM PDT 24
Peak memory	610392 kb
Host	smart-1a96e3b6-3db2-41d0-b74b-53d3d2450007
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=sleep_pin_retention_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=429939694 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sleep_pin_retention_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defa ult.vdb -cm_log /dev/null -cm_name 0.chip_sw_sleep_pin_retention.429939694
Directory	/workspace/0.chip_sw_sleep_pin_retention/latest

Test location	/workspace/coverage/default/0.chip_sw_sleep_pwm_pulses.3542889032
Short name	T300
Test name
Test status
Simulation time	8863659340 ps
CPU time	1591.2 seconds
Started	Aug 14 05:49:17 PM PDT 24
Finished	Aug 14 06:15:50 PM PDT 24
Peak memory	611540 kb
Host	smart-d88540e9-3b50-4bd3-8c8e-ba7593e7f83e
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=sleep_pwm_pulses_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3542889032 -assert nopostproc +UVM_TESTN AME=chip_base_test +UVM_TEST_SEQ=chip_sw_pwm_pulses_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm _log /dev/null -cm_name 0.chip_sw_sleep_pwm_pulses.3542889032
Directory	/workspace/0.chip_sw_sleep_pwm_pulses/latest

Test location	/workspace/coverage/default/0.chip_sw_sleep_sram_ret_contents_no_scramble.2062671508
Short name	T929
Test name
Test status
Simulation time	9632212088 ps
CPU time	992.21 seconds
Started	Aug 14 05:49:09 PM PDT 24
Finished	Aug 14 06:05:42 PM PDT 24
Peak memory	611284 kb
Host	smart-500dc668-cb4e-4ea4-9265-7618a6364556
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=20_000_000 +en_scb_tl_err_chk=0 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=sram _ctrl_sleep_sram_ret_contents_no_scramble_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2062671508 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_S EQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_sl eep_sram_ret_contents_no_scramble.2062671508
Directory	/workspace/0.chip_sw_sleep_sram_ret_contents_no_scramble/latest

Test location	/workspace/coverage/default/0.chip_sw_spi_device_pass_through.2347825709
Short name	T252
Test name
Test status
Simulation time	8420484242 ps
CPU time	851.74 seconds
Started	Aug 14 05:48:44 PM PDT 24
Finished	Aug 14 06:02:57 PM PDT 24
Peak memory	625340 kb
Host	smart-4303c6f3-51ad-46ea-9ee1-f83ca315822a
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=spi_passthrough_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2347825709 -assert nopostproc +UVM_TESTNA ME=chip_base_test +UVM_TEST_SEQ=chip_sw_spi_passthrough_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_spi_device_pass_through.2347825709
Directory	/workspace/0.chip_sw_spi_device_pass_through/latest

Test location	/workspace/coverage/default/0.chip_sw_spi_device_pinmux_sleep_retention.275008573
Short name	T81
Test name
Test status
Simulation time	4093338338 ps
CPU time	400.64 seconds
Started	Aug 14 05:47:56 PM PDT 24
Finished	Aug 14 05:54:38 PM PDT 24
Peak memory	619776 kb
Host	smart-ea66d8fa-6894-4530-819b-525ab61cf5e7
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=spi_device_sleep_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=275008573 -assert nopostproc +UVM_TESTNA ME=chip_base_test +UVM_TEST_SEQ=chip_sw_spi_device_pinmux_sleep_retention_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co verage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_spi_device_pinmux_sleep_retention.275008573
Directory	/workspace/0.chip_sw_spi_device_pinmux_sleep_retention/latest

Test location	/workspace/coverage/default/0.chip_sw_sram_ctrl_scrambled_access.898352096
Short name	T853
Test name
Test status
Simulation time	4853998312 ps
CPU time	555.83 seconds
Started	Aug 14 05:50:40 PM PDT 24
Finished	Aug 14 05:59:56 PM PDT 24
Peak memory	611400 kb
Host	smart-8b00a49b-1d76-42b9-832f-b2dfb64a2fe3
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=12_000_000 +en_scb_tl_err_chk=0 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=sram _ctrl_scrambled_access_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=898352096 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sram_ctrl _scrambled_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_ sram_ctrl_scrambled_access.898352096
Directory	/workspace/0.chip_sw_sram_ctrl_scrambled_access/latest

Test location	/workspace/coverage/default/0.chip_sw_sram_ctrl_scrambled_access_jitter_en.688553527
Short name	T197
Test name
Test status
Simulation time	4462072234 ps
CPU time	576.91 seconds
Started	Aug 14 05:51:48 PM PDT 24
Finished	Aug 14 06:01:25 PM PDT 24
Peak memory	610712 kb
Host	smart-392c0b97-3eb2-4822-a164-898c267aaa0d
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=12_000_000 +bypass_alert_ready_to_end_check=1 +en_jitter=1 +en_scb_tl_err_chk=0 +sw_build_device=sim_dv +s w_images=sram_ctrl_scrambled_access_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=688553527 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip _sw_sram_ctrl_scrambled_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na me 0.chip_sw_sram_ctrl_scrambled_access_jitter_en.688553527
Directory	/workspace/0.chip_sw_sram_ctrl_scrambled_access_jitter_en/latest

Test location	/workspace/coverage/default/0.chip_sw_sram_ctrl_smoketest.4085785199
Short name	T1028
Test name
Test status
Simulation time	3327183340 ps
CPU time	299.15 seconds
Started	Aug 14 05:50:22 PM PDT 24
Finished	Aug 14 05:55:21 PM PDT 24
Peak memory	609892 kb
Host	smart-6984fd94-ae53-4a49-acbc-9a6e1bf3f8b6
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=sram_ctrl_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4085785199 -assert nopostproc +UVM_TESTNAM E=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 0.chip_sw_sram_ctrl_smoketest.4085785199
Directory	/workspace/0.chip_sw_sram_ctrl_smoketest/latest

Test location	/workspace/coverage/default/0.chip_sw_sysrst_ctrl_ec_rst_l.270927447
Short name	T327
Test name
Test status
Simulation time	21071436444 ps
CPU time	3472.34 seconds
Started	Aug 14 05:46:55 PM PDT 24
Finished	Aug 14 06:44:49 PM PDT 24
Peak memory	611536 kb
Host	smart-5560410b-1b60-406e-bc23-a27a17d4d5da
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=sysrst_ctrl_ec_rst_l_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=270927447 -assert nopostproc +UVM_TE STNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sysrst_ctrl_ec_rst_l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de fault.vdb -cm_log /dev/null -cm_name 0.chip_sw_sysrst_ctrl_ec_rst_l.270927447
Directory	/workspace/0.chip_sw_sysrst_ctrl_ec_rst_l/latest

Test location	/workspace/coverage/default/0.chip_sw_sysrst_ctrl_in_irq.2974211295
Short name	T955
Test name
Test status
Simulation time	5164848978 ps
CPU time	593.2 seconds
Started	Aug 14 05:51:22 PM PDT 24
Finished	Aug 14 06:01:18 PM PDT 24
Peak memory	614204 kb
Host	smart-5844214b-8a48-40f1-a2fe-2ebf97153e92
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=sysrst_ctrl_in_irq_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2974211295 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sysrst_ctrl_in_irq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau lt.vdb -cm_log /dev/null -cm_name 0.chip_sw_sysrst_ctrl_in_irq.2974211295
Directory	/workspace/0.chip_sw_sysrst_ctrl_in_irq/latest

Test location	/workspace/coverage/default/0.chip_sw_sysrst_ctrl_inputs.2750906639
Short name	T257
Test name
Test status
Simulation time	3207005072 ps
CPU time	486.67 seconds
Started	Aug 14 05:48:32 PM PDT 24
Finished	Aug 14 05:56:41 PM PDT 24
Peak memory	614096 kb
Host	smart-fad6e17a-e081-47e8-a708-7a6788b7cff3
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=sysrst_ctrl_inputs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2750906639 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sysrst_ctrl_inputs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau lt.vdb -cm_log /dev/null -cm_name 0.chip_sw_sysrst_ctrl_inputs.2750906639
Directory	/workspace/0.chip_sw_sysrst_ctrl_inputs/latest

Test location	/workspace/coverage/default/0.chip_sw_sysrst_ctrl_outputs.2178362692
Short name	T41
Test name
Test status
Simulation time	2994273076 ps
CPU time	327.48 seconds
Started	Aug 14 05:48:20 PM PDT 24
Finished	Aug 14 05:53:48 PM PDT 24
Peak memory	610612 kb
Host	smart-68a6c4a3-a820-4764-9275-da750c974b3f
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=sysrst_ctrl_outputs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2178362692 -assert nopostproc +UVM_TE STNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sysrst_ctrl_outputs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def ault.vdb -cm_log /dev/null -cm_name 0.chip_sw_sysrst_ctrl_outputs.2178362692
Directory	/workspace/0.chip_sw_sysrst_ctrl_outputs/latest

Test location	/workspace/coverage/default/0.chip_sw_sysrst_ctrl_reset.829495278
Short name	T1021
Test name
Test status
Simulation time	24575410384 ps
CPU time	1448.67 seconds
Started	Aug 14 05:46:32 PM PDT 24
Finished	Aug 14 06:10:41 PM PDT 24
Peak memory	615928 kb
Host	smart-9e22e9a0-7086-4483-9dbf-8497743d50f0
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=36_000_000 +sw_build_device=sim_dv +sw_images=sysrst_ctrl_reset_test:1:new_rules,test_rom:0 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82949527 8 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sysrst_ctrl_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_sysrst_ctrl_reset.829495278
Directory	/workspace/0.chip_sw_sysrst_ctrl_reset/latest

Test location	/workspace/coverage/default/0.chip_sw_uart_rand_baudrate.2705701331
Short name	T986
Test name
Test status
Simulation time	12956566642 ps
CPU time	2587.67 seconds
Started	Aug 14 05:50:14 PM PDT 24
Finished	Aug 14 06:33:22 PM PDT 24
Peak memory	620184 kb
Host	smart-5957fb30-23d0-4452-8c67-c023db304815
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random _seed=2705701331 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_uart_rand_baudrate.2705701331
Directory	/workspace/0.chip_sw_uart_rand_baudrate/latest

Test location	/workspace/coverage/default/0.chip_sw_uart_smoketest.1817925010
Short name	T941
Test name
Test status
Simulation time	3372433236 ps
CPU time	282.47 seconds
Started	Aug 14 05:52:18 PM PDT 24
Finished	Aug 14 05:57:01 PM PDT 24
Peak memory	612948 kb
Host	smart-70530e3b-c0b6-485d-afe2-2098380e5704
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=uart_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1817925010 -assert nopostproc +UVM_TESTNAME=chi p_base_test +UVM_TEST_SEQ=chip_sw_uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 0.chip_sw_uart_smoketest.1817925010
Directory	/workspace/0.chip_sw_uart_smoketest/latest

Test location	/workspace/coverage/default/0.chip_sw_uart_tx_rx.2492479492
Short name	T988
Test name
Test status
Simulation time	5096692744 ps
CPU time	710.58 seconds
Started	Aug 14 05:46:35 PM PDT 24
Finished	Aug 14 05:58:27 PM PDT 24
Peak memory	624640 kb
Host	smart-810b6841-b67a-4bc2-af39-f4dc1eed1854
User	root
Command	/workspace/default/simv +uart_idx=0 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2492479492 -a ssert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ce/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_uart_tx_rx.2492479492
Directory	/workspace/0.chip_sw_uart_tx_rx/latest

Test location	/workspace/coverage/default/0.chip_sw_uart_tx_rx_alt_clk_freq.1501499078
Short name	T788
Test name
Test status
Simulation time	7863036544 ps
CPU time	2085.6 seconds
Started	Aug 14 05:49:24 PM PDT 24
Finished	Aug 14 06:24:11 PM PDT 24
Peak memory	624768 kb
Host	smart-d81c107e-7ade-42ee-b525-7ef36fe3de09
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=80_000_000 +chip_clock_source=ChipClockSourceExternal96Mhz +calibrate_usb_clk=1 +sw_build_device=sim_dv +s w_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1501499078 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_b audrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_uart_tx_rx _alt_clk_freq.1501499078
Directory	/workspace/0.chip_sw_uart_tx_rx_alt_clk_freq/latest

Test location	/workspace/coverage/default/0.chip_sw_uart_tx_rx_alt_clk_freq_low_speed.83993776
Short name	T35
Test name
Test status
Simulation time	4678468679 ps
CPU time	501.13 seconds
Started	Aug 14 05:51:41 PM PDT 24
Finished	Aug 14 06:00:03 PM PDT 24
Peak memory	625036 kb
Host	smart-80290b30-3eb6-45c3-84c3-937ae57aec2c
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +chip_clock_source=ChipClockSourceExternal48Mhz +sw_build_device=sim_dv +s w_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=83993776 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_bau drate_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_uart_tx_rx_a lt_clk_freq_low_speed.83993776
Directory	/workspace/0.chip_sw_uart_tx_rx_alt_clk_freq_low_speed/latest

Test location	/workspace/coverage/default/0.chip_sw_uart_tx_rx_idx1.4165572197
Short name	T869
Test name
Test status
Simulation time	4921265696 ps
CPU time	776.04 seconds
Started	Aug 14 05:47:33 PM PDT 24
Finished	Aug 14 06:00:29 PM PDT 24
Peak memory	624892 kb
Host	smart-ff17b82e-1c39-45b3-921f-81fad0ec1019
User	root
Command	/workspace/default/simv +uart_idx=1 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4165572197 -a ssert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ce/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_uart_tx_rx_idx1.4165572197
Directory	/workspace/0.chip_sw_uart_tx_rx_idx1/latest

Test location	/workspace/coverage/default/0.chip_sw_uart_tx_rx_idx3.1609115870
Short name	T371
Test name
Test status
Simulation time	3989796772 ps
CPU time	641.26 seconds
Started	Aug 14 05:49:33 PM PDT 24
Finished	Aug 14 06:00:16 PM PDT 24
Peak memory	620552 kb
Host	smart-684f84e0-8944-46a9-a74c-0c1536fe4eee
User	root
Command	/workspace/default/simv +uart_idx=3 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1609115870 -a ssert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ce/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_uart_tx_rx_idx3.1609115870
Directory	/workspace/0.chip_sw_uart_tx_rx_idx3/latest

Test location	/workspace/coverage/default/0.chip_sw_usb_ast_clk_calib.3169928032
Short name	T408
Test name
Test status
Simulation time	2908078503 ps
CPU time	378.33 seconds
Started	Aug 14 05:51:15 PM PDT 24
Finished	Aug 14 05:57:34 PM PDT 24
Peak memory	610384 kb
Host	smart-a31252ad-ecf6-4318-95ed-eed06dde3840
User	root
Command	/workspace/default/simv +usb_max_drift=1 +usb_fast_sof=1 +sw_build_device=sim_dv +sw_images=ast_usb_clk_calib:1:new_rules,test_rom:0 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3169928032 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_usb_ast_clk_calib_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_usb_ast_clk_calib.3169928032
Directory	/workspace/0.chip_sw_usb_ast_clk_calib/latest

Test location	/workspace/coverage/default/0.chip_sw_usbdev_config_host.2965113243
Short name	T863
Test name
Test status
Simulation time	7680589128 ps
CPU time	2046.91 seconds
Started	Aug 14 05:49:36 PM PDT 24
Finished	Aug 14 06:23:44 PM PDT 24
Peak memory	609628 kb
Host	smart-732deb69-a0d5-46e0-896f-d11cba0faece
User	root
Command	/workspace/default/simv +uart_idx=0 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=usbdev_config_host_test:1:new_rules,test_rom:0 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29651 13243 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_usbdev_dpi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_usbdev_config_host.2965113243
Directory	/workspace/0.chip_sw_usbdev_config_host/latest

Test location	/workspace/coverage/default/0.chip_sw_usbdev_dpi.3486534668
Short name	T40
Test name
Test status
Simulation time	11850347540 ps
CPU time	3029.76 seconds
Started	Aug 14 05:51:41 PM PDT 24
Finished	Aug 14 06:42:12 PM PDT 24
Peak memory	609536 kb
Host	smart-7b1ab9b7-026b-4481-9993-e94e68759d3d
User	root
Command	/workspace/default/simv +uart_idx=0 +calibrate_usb_clk=1 +sw_test_timeout_ns=30_000_000 +sw_build_device=sim_dv +sw_images=usbdev_test:1:new_rules,tes t_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +nt b_random_seed=3486534668 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_usbdev_dpi_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_usbdev_dpi.3486534668
Directory	/workspace/0.chip_sw_usbdev_dpi/latest

Test location	/workspace/coverage/default/0.chip_sw_usbdev_pullup.4118758147
Short name	T97
Test name
Test status
Simulation time	3292773528 ps
CPU time	268.99 seconds
Started	Aug 14 05:51:19 PM PDT 24
Finished	Aug 14 05:55:49 PM PDT 24
Peak memory	610488 kb
Host	smart-7005919d-99a4-4f4d-9464-85527ae41f2d
User	root
Command	/workspace/default/simv +uart_idx=0 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=usbdev_pullup_test:1:new_rules,test_rom:0 +cdc_instrumenta tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4118758147 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_usbdev_dpi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work space/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_usbdev_pullup.4118758147
Directory	/workspace/0.chip_sw_usbdev_pullup/latest

Test location	/workspace/coverage/default/0.chip_sw_usbdev_setuprx.1492386437
Short name	T44
Test name
Test status
Simulation time	4436830220 ps
CPU time	601.28 seconds
Started	Aug 14 05:47:12 PM PDT 24
Finished	Aug 14 05:57:14 PM PDT 24
Peak memory	610768 kb
Host	smart-2e0d76e5-93ec-48b6-9806-5e647f36e5dc
User	root
Command	/workspace/default/simv +uart_idx=0 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=usbdev_setuprx_test:1:new_rules,test_rom:0 +cdc_instrument ation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=149238643 7 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_usbdev_dpi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_usbdev_setuprx.1492386437
Directory	/workspace/0.chip_sw_usbdev_setuprx/latest

Test location	/workspace/coverage/default/0.chip_sw_usbdev_stream.3323794249
Short name	T930
Test name
Test status
Simulation time	19146102382 ps
CPU time	4205.99 seconds
Started	Aug 14 05:47:58 PM PDT 24
Finished	Aug 14 06:58:05 PM PDT 24
Peak memory	610940 kb
Host	smart-9ba61dc0-cfea-4878-827c-0fcc16143a44
User	root
Command	/workspace/default/simv +uart_idx=0 +calibrate_usb_clk=1 +sw_test_timeout_ns=60_000_000 +sw_build_device=sim_dv +sw_images=usbdev_stream_test:1:new_ru les,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim. tcl +ntb_random_seed=3323794249 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_usbdev_stream_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_usbdev_stream.3323794249
Directory	/workspace/0.chip_sw_usbdev_stream/latest

Test location	/workspace/coverage/default/0.chip_sw_usbdev_vbus.1749419697
Short name	T102
Test name
Test status
Simulation time	2431639022 ps
CPU time	200.17 seconds
Started	Aug 14 05:47:48 PM PDT 24
Finished	Aug 14 05:51:08 PM PDT 24
Peak memory	610488 kb
Host	smart-3f427d4c-088b-460a-b55c-0d08e7521098
User	root
Command	/workspace/default/simv +uart_idx=0 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=usbdev_vbus_test:1:new_rules,test_rom:0 +cdc_instrumentati on_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1749419697 - assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_usbdev_dpi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_usbdev_vbus.1749419697
Directory	/workspace/0.chip_sw_usbdev_vbus/latest

Test location	/workspace/coverage/default/0.chip_tap_straps_dev.436223239
Short name	T418
Test name
Test status
Simulation time	9591067324 ps
CPU time	1109.04 seconds
Started	Aug 14 05:48:07 PM PDT 24
Finished	Aug 14 06:06:37 PM PDT 24
Peak memory	625688 kb
Host	smart-367d9cfc-a0bf-4e07-b38b-c5f662b12ea4
User	root
Command	/workspace/default/simv +use_otp_image=OtpTypeLcStDev +create_jtag_riscv_map=1 +sw_build_device=sim_dv +sw_images=example_test_from_rom:0:test_in_rom: new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=436223239 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_tap_straps_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_tap_straps_dev.436223239
Directory	/workspace/0.chip_tap_straps_dev/latest

Test location	/workspace/coverage/default/0.chip_tap_straps_prod.3515788905
Short name	T96
Test name
Test status
Simulation time	8508754718 ps
CPU time	937.7 seconds
Started	Aug 14 05:51:42 PM PDT 24
Finished	Aug 14 06:07:22 PM PDT 24
Peak memory	625564 kb
Host	smart-84e09ac3-5fec-4849-9dcc-66b6a244d7bd
User	root
Command	/workspace/default/simv +use_otp_image=OtpTypeLcStProd +create_jtag_riscv_map=1 +sw_build_device=sim_dv +sw_images=example_test_from_rom:0:test_in_rom :new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3515788905 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_tap_straps_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_tap_straps_prod.3515788905
Directory	/workspace/0.chip_tap_straps_prod/latest

Test location	/workspace/coverage/default/0.chip_tap_straps_testunlock0.2433451232
Short name	T94
Test name
Test status
Simulation time	2891566972 ps
CPU time	196.79 seconds
Started	Aug 14 05:49:54 PM PDT 24
Finished	Aug 14 05:53:12 PM PDT 24
Peak memory	633888 kb
Host	smart-725d0023-1995-4739-aad6-25109f8045b9
User	root
Command	/workspace/default/simv +use_otp_image=OtpTypeLcStTestUnlocked0 +create_jtag_riscv_map=1 +sw_build_device=sim_dv +sw_images=example_test_from_rom:0:te st_in_rom:new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2433451232 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_tap_straps_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_tap_straps_testunlock0.2433451232
Directory	/workspace/0.chip_tap_straps_testunlock0/latest

Test location	/workspace/coverage/default/0.rom_e2e_asm_init_dev.2966699942
Short name	T985
Test name
Test status
Simulation time	15148177442 ps
CPU time	3453.37 seconds
Started	Aug 14 05:55:35 PM PDT 24
Finished	Aug 14 06:53:09 PM PDT 24
Peak memory	610936 kb
Host	smart-67430e75-2740-4741-a820-f6ebf74575d3
User	root
Command	/workspace/default/simv +use_otp_image=OtpTypeCustom +sw_test_timeout_ns=20000000 +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_prod _key_0:1:ot_flash_binary,otp_img_e2e_bootstrap_entry_dev:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2966699942 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_S EQ=chip_sw_rom_e2e_asm_init_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_asm_init_dev.2966699942
Directory	/workspace/0.rom_e2e_asm_init_dev/latest

Test location	/workspace/coverage/default/0.rom_e2e_asm_init_prod.2713058972
Short name	T336
Test name
Test status
Simulation time	15798505548 ps
CPU time	3403.64 seconds
Started	Aug 14 05:53:33 PM PDT 24
Finished	Aug 14 06:50:17 PM PDT 24
Peak memory	610900 kb
Host	smart-49b349f8-009a-4ad9-9583-d8e688231c49
User	root
Command	/workspace/default/simv +use_otp_image=OtpTypeCustom +sw_test_timeout_ns=20000000 +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_prod _key_0:1:ot_flash_binary,otp_img_e2e_bootstrap_entry_prod:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2713058972 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_ SEQ=chip_sw_rom_e2e_asm_init_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_asm_init_prod.2713058972
Directory	/workspace/0.rom_e2e_asm_init_prod/latest

Test location	/workspace/coverage/default/0.rom_e2e_asm_init_prod_end.2523020504
Short name	T390
Test name
Test status
Simulation time	16003079805 ps
CPU time	3899.58 seconds
Started	Aug 14 05:55:43 PM PDT 24
Finished	Aug 14 07:00:43 PM PDT 24
Peak memory	610672 kb
Host	smart-47387571-b5f1-49d1-8279-0c97ecd97d94
User	root
Command	/workspace/default/simv +use_otp_image=OtpTypeCustom +sw_test_timeout_ns=20000000 +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_prod _key_0:1:ot_flash_binary,otp_img_e2e_bootstrap_entry_prod_end:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2523020504 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_T EST_SEQ=chip_sw_rom_e2e_asm_init_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 0.rom_e2e_asm_init_prod_end.2523020504
Directory	/workspace/0.rom_e2e_asm_init_prod_end/latest

Test location	/workspace/coverage/default/0.rom_e2e_asm_init_rma.2175227750
Short name	T1004
Test name
Test status
Simulation time	15195708872 ps
CPU time	3504.86 seconds
Started	Aug 14 05:58:22 PM PDT 24
Finished	Aug 14 06:56:47 PM PDT 24
Peak memory	610648 kb
Host	smart-f053a1c9-9d5e-4901-b292-4d69e8c2ba5f
User	root
Command	/workspace/default/simv +use_otp_image=OtpTypeCustom +sw_test_timeout_ns=20000000 +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_prod _key_0:1:ot_flash_binary,otp_img_e2e_bootstrap_entry_rma:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2175227750 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_S EQ=chip_sw_rom_e2e_asm_init_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_asm_init_rma.2175227750
Directory	/workspace/0.rom_e2e_asm_init_rma/latest

Test location	/workspace/coverage/default/0.rom_e2e_asm_init_test_unlocked0.1257572612
Short name	T805
Test name
Test status
Simulation time	11404564200 ps
CPU time	3721.09 seconds
Started	Aug 14 05:58:08 PM PDT 24
Finished	Aug 14 07:00:09 PM PDT 24
Peak memory	609964 kb
Host	smart-f12926c2-eb7e-491a-ad7a-977ce9ae650a
User	root
Command	/workspace/default/simv +use_otp_image=OtpTypeCustom +sw_test_timeout_ns=410_000_000 +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_p rod_key_0:1:ot_flash_binary,otp_img_e2e_bootstrap_entry_test_unlocked0:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY =UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1257572612 -assert nopostproc +UVM_TESTNAME=chip_base_te st +UVM_TEST_SEQ=chip_sw_rom_e2e_asm_init_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/ null -cm_name 0.rom_e2e_asm_init_test_unlocked0.1257572612
Directory	/workspace/0.rom_e2e_asm_init_test_unlocked0/latest

Test location	/workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_bad_b_good_dev.1185412103
Short name	T267
Test name
Test status
Simulation time	23925825538 ps
CPU time	6837.78 seconds
Started	Aug 14 05:56:06 PM PDT 24
Finished	Aug 14 07:50:05 PM PDT 24
Peak memory	611540 kb
Host	smart-3f45a67d-46e6-42ef-8586-e8edcafd0565
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=100_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_corrupted:1: ot_flash_binary:signed:fake_ecdsa_prod_key_0,empty_test_slot_b_fake_ecdsa_prod_key_0:2:ot_flash_binary,otp_img_boot_policy_valid_dev:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random _seed=1185412103 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_boot_policy_valid_a_bad_b_good_dev.1185412103
Directory	/workspace/0.rom_e2e_boot_policy_valid_a_bad_b_good_dev/latest

Test location	/workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_bad_b_good_prod.1204849348
Short name	T783
Test name
Test status
Simulation time	23610001876 ps
CPU time	5954.25 seconds
Started	Aug 14 05:53:54 PM PDT 24
Finished	Aug 14 07:33:09 PM PDT 24
Peak memory	611448 kb
Host	smart-f112100b-6f14-489d-8cb1-aa38b03dbef7
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=100_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_corrupted:1: ot_flash_binary:signed:fake_ecdsa_prod_key_0,empty_test_slot_b_fake_ecdsa_prod_key_0:2:ot_flash_binary,otp_img_boot_policy_valid_prod:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=1204849348 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_boot_policy_valid_a_bad_b_good_prod.1204849348
Directory	/workspace/0.rom_e2e_boot_policy_valid_a_bad_b_good_prod/latest

Test location	/workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_bad_b_good_prod_end.482111310
Short name	T972
Test name
Test status
Simulation time	23520724314 ps
CPU time	5776.24 seconds
Started	Aug 14 05:56:52 PM PDT 24
Finished	Aug 14 07:33:09 PM PDT 24
Peak memory	610552 kb
Host	smart-088f7522-241d-4e80-bde8-0c374989da54
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=100_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_corrupted:1: ot_flash_binary:signed:fake_ecdsa_prod_key_0,empty_test_slot_b_fake_ecdsa_prod_key_0:2:ot_flash_binary,otp_img_boot_policy_valid_prod_end:4,mask_r om:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r andom_seed=482111310 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_boot_policy_valid_a_bad_b_good_prod_end.482111310
Directory	/workspace/0.rom_e2e_boot_policy_valid_a_bad_b_good_prod_end/latest

Test location	/workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_bad_b_good_rma.118738907
Short name	T266
Test name
Test status
Simulation time	23892846092 ps
CPU time	6119.41 seconds
Started	Aug 14 05:54:50 PM PDT 24
Finished	Aug 14 07:36:50 PM PDT 24
Peak memory	611496 kb
Host	smart-e4c03ed6-50f8-462d-beaf-81a48e97489e
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=100_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_corrupted:1: ot_flash_binary:signed:fake_ecdsa_prod_key_0,empty_test_slot_b_fake_ecdsa_prod_key_0:2:ot_flash_binary,otp_img_boot_policy_valid_rma:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random _seed=118738907 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_boot_policy_valid_a_bad_b_good_rma.118738907
Directory	/workspace/0.rom_e2e_boot_policy_valid_a_bad_b_good_rma/latest

Test location	/workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_bad_dev.1291319552
Short name	T752
Test name
Test status
Simulation time	16371432780 ps
CPU time	4436.33 seconds
Started	Aug 14 05:57:50 PM PDT 24
Finished	Aug 14 07:11:47 PM PDT 24
Peak memory	611428 kb
Host	smart-6b591d63-12b6-4b8e-89e6-b494d6e2e752
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=100_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_p rod_key_0:1:ot_flash_binary,empty_test_slot_b_corrupted:2:ot_flash_binary:signed:fake_ecdsa_prod_key_0,otp_img_boot_policy_valid_dev:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random _seed=1291319552 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_boot_policy_valid_a_good_b_bad_dev.1291319552
Directory	/workspace/0.rom_e2e_boot_policy_valid_a_good_b_bad_dev/latest

Test location	/workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_bad_prod.3590520701
Short name	T627
Test name
Test status
Simulation time	15570979056 ps
CPU time	3726.38 seconds
Started	Aug 14 05:56:13 PM PDT 24
Finished	Aug 14 06:58:19 PM PDT 24
Peak memory	611508 kb
Host	smart-4b834dc0-8c9e-4fb9-b9c2-58db1e14cb84
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=100_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_p rod_key_0:1:ot_flash_binary,empty_test_slot_b_corrupted:2:ot_flash_binary:signed:fake_ecdsa_prod_key_0,otp_img_boot_policy_valid_prod:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=3590520701 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_boot_policy_valid_a_good_b_bad_prod.3590520701
Directory	/workspace/0.rom_e2e_boot_policy_valid_a_good_b_bad_prod/latest

Test location	/workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_bad_prod_end.457665714
Short name	T995
Test name
Test status
Simulation time	15459884122 ps
CPU time	3378.76 seconds
Started	Aug 14 05:52:57 PM PDT 24
Finished	Aug 14 06:49:17 PM PDT 24
Peak memory	609960 kb
Host	smart-f0064c6c-a8d7-4ae6-ac88-3a070e4953a3
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=100_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_p rod_key_0:1:ot_flash_binary,empty_test_slot_b_corrupted:2:ot_flash_binary:signed:fake_ecdsa_prod_key_0,otp_img_boot_policy_valid_prod_end:4,mask_r om:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r andom_seed=457665714 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_boot_policy_valid_a_good_b_bad_prod_end.457665714
Directory	/workspace/0.rom_e2e_boot_policy_valid_a_good_b_bad_prod_end/latest

Test location	/workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_bad_rma.2690807279
Short name	T766
Test name
Test status
Simulation time	14301676820 ps
CPU time	3223.39 seconds
Started	Aug 14 05:59:07 PM PDT 24
Finished	Aug 14 06:52:51 PM PDT 24
Peak memory	611452 kb
Host	smart-9622c2ed-a069-4217-aee6-7c9a3bfcaec8
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=100_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_p rod_key_0:1:ot_flash_binary,empty_test_slot_b_corrupted:2:ot_flash_binary:signed:fake_ecdsa_prod_key_0,otp_img_boot_policy_valid_rma:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random _seed=2690807279 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_boot_policy_valid_a_good_b_bad_rma.2690807279
Directory	/workspace/0.rom_e2e_boot_policy_valid_a_good_b_bad_rma/latest

Test location	/workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0.1661988020
Short name	T905
Test name
Test status
Simulation time	11227034120 ps
CPU time	3074.32 seconds
Started	Aug 14 05:57:43 PM PDT 24
Finished	Aug 14 06:48:58 PM PDT 24
Peak memory	611500 kb
Host	smart-6a9e8148-25cb-4f19-8e92-ce62f10a98fa
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=410_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_p rod_key_0:1:ot_flash_binary,empty_test_slot_b_corrupted:2:ot_flash_binary:signed:fake_ecdsa_prod_key_0,otp_img_boot_policy_valid_test_unlocked0:4, mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1661988020 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0.1661988020
Directory	/workspace/0.rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0/latest

Test location	/workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_good_dev.1495369111
Short name	T918
Test name
Test status
Simulation time	15833409208 ps
CPU time	3672.04 seconds
Started	Aug 14 05:52:36 PM PDT 24
Finished	Aug 14 06:53:49 PM PDT 24
Peak memory	611540 kb
Host	smart-86ba2e22-0532-4d21-8f28-b23d796d798e
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=100_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_p rod_key_0:1:ot_flash_binary,empty_test_slot_b_fake_ecdsa_prod_key_0:2:ot_flash_binary,otp_img_boot_policy_valid_dev:4,mask_rom:0 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1495369111 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/c overage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_boot_policy_valid_a_good_b_good_dev.1495369111
Directory	/workspace/0.rom_e2e_boot_policy_valid_a_good_b_good_dev/latest

Test location	/workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_good_prod.3695789043
Short name	T699
Test name
Test status
Simulation time	15473045284 ps
CPU time	4361.68 seconds
Started	Aug 14 05:58:02 PM PDT 24
Finished	Aug 14 07:10:44 PM PDT 24
Peak memory	611600 kb
Host	smart-3bbf0c1f-a376-429f-bd59-88670d53b38c
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=100_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_p rod_key_0:1:ot_flash_binary,empty_test_slot_b_fake_ecdsa_prod_key_0:2:ot_flash_binary,otp_img_boot_policy_valid_prod:4,mask_rom:0 +cdc_instrumenta tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3695789043 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/ coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_boot_policy_valid_a_good_b_good_prod.3695789043
Directory	/workspace/0.rom_e2e_boot_policy_valid_a_good_b_good_prod/latest

Test location	/workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_good_prod_end.3914245332
Short name	T389
Test name
Test status
Simulation time	14822768788 ps
CPU time	4075.02 seconds
Started	Aug 14 05:54:21 PM PDT 24
Finished	Aug 14 07:02:17 PM PDT 24
Peak memory	609916 kb
Host	smart-e7f508a6-fa31-4a3a-8f4c-f5e3695f8e34
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=100_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_p rod_key_0:1:ot_flash_binary,empty_test_slot_b_fake_ecdsa_prod_key_0:2:ot_flash_binary,otp_img_boot_policy_valid_prod_end:4,mask_rom:0 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=391424 5332 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_boot_policy_valid_a_good_b_good_prod_end.3914245332
Directory	/workspace/0.rom_e2e_boot_policy_valid_a_good_b_good_prod_end/latest

Test location	/workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_good_rma.2013279606
Short name	T812
Test name
Test status
Simulation time	14629889104 ps
CPU time	3923.28 seconds
Started	Aug 14 05:55:15 PM PDT 24
Finished	Aug 14 07:00:39 PM PDT 24
Peak memory	610764 kb
Host	smart-81064769-19e7-4fe9-9685-19826717c03a
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=100_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_p rod_key_0:1:ot_flash_binary,empty_test_slot_b_fake_ecdsa_prod_key_0:2:ot_flash_binary,otp_img_boot_policy_valid_rma:4,mask_rom:0 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2013279606 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/c overage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_boot_policy_valid_a_good_b_good_rma.2013279606
Directory	/workspace/0.rom_e2e_boot_policy_valid_a_good_b_good_rma/latest

Test location	/workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_good_test_unlocked0.769343367
Short name	T890
Test name
Test status
Simulation time	11285567982 ps
CPU time	3391.84 seconds
Started	Aug 14 05:58:28 PM PDT 24
Finished	Aug 14 06:55:00 PM PDT 24
Peak memory	610476 kb
Host	smart-c16a3a76-70da-430d-8c01-05b3f328e4ff
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=410_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_p rod_key_0:1:ot_flash_binary,empty_test_slot_b_fake_ecdsa_prod_key_0:2:ot_flash_binary,otp_img_boot_policy_valid_test_unlocked0:4,mask_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 769343367 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_boot_policy_valid_a_good_b_good_test_unlocked0.769343367
Directory	/workspace/0.rom_e2e_boot_policy_valid_a_good_b_good_test_unlocked0/latest

Test location	/workspace/coverage/default/0.rom_e2e_jtag_debug_rma.1413043153
Short name	T312
Test name
Test status
Simulation time	11703947572 ps
CPU time	2000.67 seconds
Started	Aug 14 05:50:48 PM PDT 24
Finished	Aug 14 06:24:11 PM PDT 24
Peak memory	625228 kb
Host	smart-a8290d83-fd78-4a0a-9958-c3c1df9cb5e1
User	root
Command	/workspace/default/simv +use_jtag_dmi=1 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=img_rma_exec_disabled:4,mask_rom:0 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14130 43153 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rom_e2e_jtag_debug_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_jtag_debug_rma.1413043153
Directory	/workspace/0.rom_e2e_jtag_debug_rma/latest

Test location	/workspace/coverage/default/0.rom_e2e_jtag_debug_test_unlocked0.3082388561
Short name	T319
Test name
Test status
Simulation time	10651394463 ps
CPU time	1994.38 seconds
Started	Aug 14 05:52:43 PM PDT 24
Finished	Aug 14 06:25:59 PM PDT 24
Peak memory	624676 kb
Host	smart-92214799-1726-45a2-88ff-788e69a25d13
User	root
Command	/workspace/default/simv +use_jtag_dmi=1 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=img_test_unlocked0_exec_disabled:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random _seed=3082388561 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rom_e2e_jtag_debug_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_jtag_debug_test_unlocked0.3082388561
Directory	/workspace/0.rom_e2e_jtag_debug_test_unlocked0/latest

Test location	/workspace/coverage/default/0.rom_e2e_jtag_inject_dev.643009244
Short name	T15
Test name
Test status
Simulation time	32251305443 ps
CPU time	2520.71 seconds
Started	Aug 14 05:48:37 PM PDT 24
Finished	Aug 14 06:30:38 PM PDT 24
Peak memory	619512 kb
Host	smart-e23550ce-d4b1-424b-911c-89c04a4dac63
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=40_000_000 +use_jtag_dmi=1 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=img_dev_exec_di sabled:4,sram_program:5,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=643009244 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rom_e2e_jtag_inject_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_jtag_inject_dev.643009244
Directory	/workspace/0.rom_e2e_jtag_inject_dev/latest

Test location	/workspace/coverage/default/0.rom_e2e_jtag_inject_rma.4079893781
Short name	T745
Test name
Test status
Simulation time	26901688439 ps
CPU time	3236.99 seconds
Started	Aug 14 05:54:09 PM PDT 24
Finished	Aug 14 06:48:07 PM PDT 24
Peak memory	619436 kb
Host	smart-08962f51-20ed-4488-9077-8b2e9da5619b
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=40_000_000 +use_jtag_dmi=1 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=img_rma_exec_di sabled:4,sram_program:5,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=4079893781 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rom_e2e_jtag_inject_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_jtag_inject_rma.4079893781
Directory	/workspace/0.rom_e2e_jtag_inject_rma/latest

Test location	/workspace/coverage/default/0.rom_e2e_jtag_inject_test_unlocked0.135295439
Short name	T14
Test name
Test status
Simulation time	24947533668 ps
CPU time	2020.53 seconds
Started	Aug 14 05:50:10 PM PDT 24
Finished	Aug 14 06:23:51 PM PDT 24
Peak memory	619436 kb
Host	smart-7f72775d-5678-47d2-a6b7-2e3d208cda13
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=40_000_000 +use_jtag_dmi=1 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=img_test_unlock ed0_exec_disabled:4,sram_program:5,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=135295439 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rom_e2e_jtag_i nject_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_jtag_inject_ test_unlocked0.135295439
Directory	/workspace/0.rom_e2e_jtag_inject_test_unlocked0/latest

Test location	/workspace/coverage/default/0.rom_e2e_keymgr_init_rom_ext_invalid_meas.1061490038
Short name	T862
Test name
Test status
Simulation time	14658817700 ps
CPU time	3121.73 seconds
Started	Aug 14 05:58:35 PM PDT 24
Finished	Aug 14 06:50:37 PM PDT 24
Peak memory	610464 kb
Host	smart-b47d22f1-6c4a-4a89-9f19-af8836feae8a
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=40_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=rom_e2e_keymgr_init_otp_invalid _meas:1:new_rules,otp_img_keymgr_otp_invalid_meas:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1061490038 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip _sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_keymgr_in it_rom_ext_invalid_meas.1061490038
Directory	/workspace/0.rom_e2e_keymgr_init_rom_ext_invalid_meas/latest

Test location	/workspace/coverage/default/0.rom_e2e_keymgr_init_rom_ext_meas.797425561
Short name	T69
Test name
Test status
Simulation time	15108823412 ps
CPU time	3864.34 seconds
Started	Aug 14 05:55:18 PM PDT 24
Finished	Aug 14 06:59:43 PM PDT 24
Peak memory	609976 kb
Host	smart-02b5921c-c85e-4f76-822b-b47f855fe7f9
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=40_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=rom_e2e_keymgr_init_otp_meas:1: new_rules,otp_img_keymgr_otp_meas:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=797425561 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_keymgr_init_rom_ext_meas.797425561
Directory	/workspace/0.rom_e2e_keymgr_init_rom_ext_meas/latest

Test location	/workspace/coverage/default/0.rom_e2e_self_hash.3316653571
Short name	T581
Test name
Test status
Simulation time	25128116084 ps
CPU time	5329.01 seconds
Started	Aug 14 05:54:14 PM PDT 24
Finished	Aug 14 07:23:04 PM PDT 24
Peak memory	610916 kb
Host	smart-67ced952-6c78-4641-8997-f405334c7ee3
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=200_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=rom_e2e_self_hash_test:1:new_r ules,otp_img_sigverify_spx_prod:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3316653571 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_self_hash.3316653571
Directory	/workspace/0.rom_e2e_self_hash/latest

Test location	/workspace/coverage/default/0.rom_e2e_shutdown_exception_c.252425578
Short name	T728
Test name
Test status
Simulation time	14559509878 ps
CPU time	3126.46 seconds
Started	Aug 14 05:52:51 PM PDT 24
Finished	Aug 14 06:44:57 PM PDT 24
Peak memory	610080 kb
Host	smart-9af1e46d-322a-4e4b-a314-f700358c216d
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=40000000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=rom_e2e_shutdown_exception_c:1:ne w_rules,otp_img_secret2_locked_rma:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=252425578 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rom_e2e_shut down_exception_c_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_s hutdown_exception_c.252425578
Directory	/workspace/0.rom_e2e_shutdown_exception_c/latest

Test location	/workspace/coverage/default/0.rom_e2e_shutdown_output.3042371584
Short name	T421
Test name
Test status
Simulation time	25986359210 ps
CPU time	3303.94 seconds
Started	Aug 14 05:53:04 PM PDT 24
Finished	Aug 14 06:48:08 PM PDT 24
Peak memory	612452 kb
Host	smart-c9c7f2fa-7329-4177-94b6-2deb235e5090
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=20000000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_unsigned:1:ot_f lash_binary,otp_img_shutdown_output_test_unlocked0:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3042371584 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chi p_sw_rom_e2e_shutdown_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_shutdown_output.3042371584
Directory	/workspace/0.rom_e2e_shutdown_output/latest

Test location	/workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_bad_dev.951064512
Short name	T882
Test name
Test status
Simulation time	22872253856 ps
CPU time	5689.89 seconds
Started	Aug 14 05:58:13 PM PDT 24
Finished	Aug 14 07:33:04 PM PDT 24
Peak memory	611332 kb
Host	smart-41039f0b-8d0f-43a9-8f10-c126078bf880
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=100_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_corrupted:1: ot_flash_binary:signed:fake_ecdsa_dev_key_0,empty_test_slot_b_corrupted:2:ot_flash_binary:signed:fake_ecdsa_dev_key_0,otp_img_sigverify_always_dev :4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t cl +ntb_random_seed=951064512 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rom_e2e_sigverify_always_a_bad_b_bad_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_sigverify_always_a_bad_b_bad_dev.951064512
Directory	/workspace/0.rom_e2e_sigverify_always_a_bad_b_bad_dev/latest

Test location	/workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_bad_prod.1717861440
Short name	T830
Test name
Test status
Simulation time	24073813750 ps
CPU time	5855.82 seconds
Started	Aug 14 05:55:19 PM PDT 24
Finished	Aug 14 07:32:55 PM PDT 24
Peak memory	611040 kb
Host	smart-50ceea23-c601-477c-92d7-7c61e781ffd6
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=100_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_corrupted:1: ot_flash_binary:signed:fake_ecdsa_prod_key_0,empty_test_slot_b_corrupted:2:ot_flash_binary:signed:fake_ecdsa_prod_key_0,otp_img_sigverify_always_p rod:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si m.tcl +ntb_random_seed=1717861440 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rom_e2e_sigverify_always_a_bad_b_bad_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_sigverify_always_a_bad_ b_bad_prod.1717861440
Directory	/workspace/0.rom_e2e_sigverify_always_a_bad_b_bad_prod/latest

Test location	/workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_bad_prod_end.285438408
Short name	T898
Test name
Test status
Simulation time	24196042887 ps
CPU time	5899.68 seconds
Started	Aug 14 05:55:06 PM PDT 24
Finished	Aug 14 07:33:26 PM PDT 24
Peak memory	610532 kb
Host	smart-8de3dc85-0817-4529-96e0-727c7e780e14
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=100_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_corrupted:1: ot_flash_binary:signed:fake_ecdsa_prod_key_0,empty_test_slot_b_corrupted:2:ot_flash_binary:signed:fake_ecdsa_prod_key_0,otp_img_sigverify_always_p rod_end:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tool s/sim.tcl +ntb_random_seed=285438408 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rom_e2e_sigverify_always_a_bad_b_bad_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_sigverify_always_a_b ad_b_bad_prod_end.285438408
Directory	/workspace/0.rom_e2e_sigverify_always_a_bad_b_bad_prod_end/latest

Test location	/workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_bad_rma.3962293532
Short name	T684
Test name
Test status
Simulation time	23172708306 ps
CPU time	6747.04 seconds
Started	Aug 14 05:55:25 PM PDT 24
Finished	Aug 14 07:47:53 PM PDT 24
Peak memory	611672 kb
Host	smart-0e48762b-4731-47d3-a3aa-ed3e6f75e483
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=100_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_corrupted:1: ot_flash_binary:signed:fake_ecdsa_prod_key_0,empty_test_slot_b_corrupted:2:ot_flash_binary:signed:fake_ecdsa_prod_key_0,otp_img_sigverify_always_r ma:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim .tcl +ntb_random_seed=3962293532 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rom_e2e_sigverify_always_a_bad_b_bad_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_sigverify_always_a_bad_b _bad_rma.3962293532
Directory	/workspace/0.rom_e2e_sigverify_always_a_bad_b_bad_rma/latest

Test location	/workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0.1530557408
Short name	T289
Test name
Test status
Simulation time	18207671416 ps
CPU time	4593.61 seconds
Started	Aug 14 05:57:51 PM PDT 24
Finished	Aug 14 07:14:26 PM PDT 24
Peak memory	611012 kb
Host	smart-bfe86c4c-de85-455f-a74c-ec9da761e70f
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=600_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_corrupted:1: ot_flash_binary:signed:fake_ecdsa_test_key_0,empty_test_slot_b_corrupted:2:ot_flash_binary:signed:fake_ecdsa_test_key_0,otp_img_sigverify_always_t est_unlocked0:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d v/tools/sim.tcl +ntb_random_seed=1530557408 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rom_e2e_sigverify_always_a_bad_b _bad_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_sigverify_alw ays_a_bad_b_bad_test_unlocked0.1530557408
Directory	/workspace/0.rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0/latest

Test location	/workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_nothing_dev.3851080574
Short name	T660
Test name
Test status
Simulation time	15284295825 ps
CPU time	3743.85 seconds
Started	Aug 14 05:54:51 PM PDT 24
Finished	Aug 14 06:57:15 PM PDT 24
Peak memory	611124 kb
Host	smart-277ababe-f61c-4b79-8850-906e04982966
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=100_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_corrupted:1: ot_flash_binary:signed:fake_ecdsa_dev_key_0,otp_img_sigverify_always_dev:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3851080574 -assert nopostproc +UVM_TESTNAME=chip_base_ test +UVM_TEST_SEQ=chip_sw_rom_e2e_sigverify_always_a_bad_b_bad_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def ault.vdb -cm_log /dev/null -cm_name 0.rom_e2e_sigverify_always_a_bad_b_nothing_dev.3851080574
Directory	/workspace/0.rom_e2e_sigverify_always_a_bad_b_nothing_dev/latest

Test location	/workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_nothing_prod.2863251951
Short name	T290
Test name
Test status
Simulation time	14406219857 ps
CPU time	3541.84 seconds
Started	Aug 14 05:54:31 PM PDT 24
Finished	Aug 14 06:53:34 PM PDT 24
Peak memory	611020 kb
Host	smart-5ac76ae7-a863-43df-9ee9-1ea21cdc229c
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=100_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_corrupted:1: ot_flash_binary:signed:fake_ecdsa_prod_key_0,otp_img_sigverify_always_prod:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2863251951 -assert nopostproc +UVM_TESTNAME=chip_bas e_test +UVM_TEST_SEQ=chip_sw_rom_e2e_sigverify_always_a_bad_b_bad_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/d efault.vdb -cm_log /dev/null -cm_name 0.rom_e2e_sigverify_always_a_bad_b_nothing_prod.2863251951
Directory	/workspace/0.rom_e2e_sigverify_always_a_bad_b_nothing_prod/latest

Test location	/workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_nothing_prod_end.3095071144
Short name	T769
Test name
Test status
Simulation time	14747479539 ps
CPU time	3660.83 seconds
Started	Aug 14 05:57:57 PM PDT 24
Finished	Aug 14 06:58:59 PM PDT 24
Peak memory	610996 kb
Host	smart-adf9b9a1-f7fc-4e75-aea0-a70069c6d4db
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=100_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_corrupted:1: ot_flash_binary:signed:fake_ecdsa_prod_key_0,otp_img_sigverify_always_prod_end:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3095071144 -assert nopostproc +UVM_TESTNAME=chip _base_test +UVM_TEST_SEQ=chip_sw_rom_e2e_sigverify_always_a_bad_b_bad_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera ge/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_sigverify_always_a_bad_b_nothing_prod_end.3095071144
Directory	/workspace/0.rom_e2e_sigverify_always_a_bad_b_nothing_prod_end/latest

Test location	/workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_nothing_rma.1719370097
Short name	T66
Test name
Test status
Simulation time	13576957382 ps
CPU time	3134.97 seconds
Started	Aug 14 05:56:04 PM PDT 24
Finished	Aug 14 06:48:20 PM PDT 24
Peak memory	610496 kb
Host	smart-bada0421-c3d9-4d75-a417-f1a5fccd1cc0
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=100_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_corrupted:1: ot_flash_binary:signed:fake_ecdsa_prod_key_0,otp_img_sigverify_always_rma:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1719370097 -assert nopostproc +UVM_TESTNAME=chip_base _test +UVM_TEST_SEQ=chip_sw_rom_e2e_sigverify_always_a_bad_b_bad_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de fault.vdb -cm_log /dev/null -cm_name 0.rom_e2e_sigverify_always_a_bad_b_nothing_rma.1719370097
Directory	/workspace/0.rom_e2e_sigverify_always_a_bad_b_nothing_rma/latest

Test location	/workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0.2650309838
Short name	T65
Test name
Test status
Simulation time	11161728473 ps
CPU time	2459.36 seconds
Started	Aug 14 05:55:29 PM PDT 24
Finished	Aug 14 06:36:28 PM PDT 24
Peak memory	612052 kb
Host	smart-7ceddb46-4652-4d81-be47-159d59fc9c93
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=410_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_corrupted:1: ot_flash_binary:signed:fake_ecdsa_test_key_0:new_rules,otp_img_sigverify_always_test_unlocked0:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2650309838 -assert nopostproc +U VM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rom_e2e_sigverify_always_a_bad_b_bad_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0.2650309838
Directory	/workspace/0.rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0/latest

Test location	/workspace/coverage/default/0.rom_e2e_sigverify_always_a_nothing_b_bad_dev.2433364442
Short name	T816
Test name
Test status
Simulation time	15565131630 ps
CPU time	4404.71 seconds
Started	Aug 14 05:59:01 PM PDT 24
Finished	Aug 14 07:12:26 PM PDT 24
Peak memory	611768 kb
Host	smart-5a213c83-896e-48c2-af17-a321e5f25abb
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=100_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_b_corrupted:1: ot_flash_binary:signed:fake_ecdsa_dev_key_0,otp_img_sigverify_always_dev:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2433364442 -assert nopostproc +UVM_TESTNAME=chip_base_ test +UVM_TEST_SEQ=chip_sw_rom_e2e_sigverify_always_a_bad_b_bad_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def ault.vdb -cm_log /dev/null -cm_name 0.rom_e2e_sigverify_always_a_nothing_b_bad_dev.2433364442
Directory	/workspace/0.rom_e2e_sigverify_always_a_nothing_b_bad_dev/latest

Test location	/workspace/coverage/default/0.rom_e2e_sigverify_always_a_nothing_b_bad_prod.1151564628
Short name	T685
Test name
Test status
Simulation time	14065777004 ps
CPU time	3657.87 seconds
Started	Aug 14 05:57:09 PM PDT 24
Finished	Aug 14 06:58:07 PM PDT 24
Peak memory	610840 kb
Host	smart-f4772a1e-eb3b-4129-b1e2-2a91979cd7b4
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=100_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_b_corrupted:1: ot_flash_binary:signed:fake_ecdsa_prod_key_0,otp_img_sigverify_always_prod:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1151564628 -assert nopostproc +UVM_TESTNAME=chip_bas e_test +UVM_TEST_SEQ=chip_sw_rom_e2e_sigverify_always_a_bad_b_bad_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/d efault.vdb -cm_log /dev/null -cm_name 0.rom_e2e_sigverify_always_a_nothing_b_bad_prod.1151564628
Directory	/workspace/0.rom_e2e_sigverify_always_a_nothing_b_bad_prod/latest

Test location	/workspace/coverage/default/0.rom_e2e_sigverify_always_a_nothing_b_bad_prod_end.322193222
Short name	T858
Test name
Test status
Simulation time	13611721637 ps
CPU time	3515.83 seconds
Started	Aug 14 05:55:39 PM PDT 24
Finished	Aug 14 06:54:15 PM PDT 24
Peak memory	610544 kb
Host	smart-39530d30-2177-41ff-a399-94509c6d3eff
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=100_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_b_corrupted:1: ot_flash_binary:signed:fake_ecdsa_prod_key_0,otp_img_sigverify_always_prod_end:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=322193222 -assert nopostproc +UVM_TESTNAME=chip_ base_test +UVM_TEST_SEQ=chip_sw_rom_e2e_sigverify_always_a_bad_b_bad_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag e/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_sigverify_always_a_nothing_b_bad_prod_end.322193222
Directory	/workspace/0.rom_e2e_sigverify_always_a_nothing_b_bad_prod_end/latest

Test location	/workspace/coverage/default/0.rom_e2e_sigverify_always_a_nothing_b_bad_rma.2197818103
Short name	T64
Test name
Test status
Simulation time	14487891366 ps
CPU time	3220.37 seconds
Started	Aug 14 05:57:11 PM PDT 24
Finished	Aug 14 06:50:52 PM PDT 24
Peak memory	610964 kb
Host	smart-3baad0a3-7f67-47a9-ba90-b30f704a5209
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=100_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_b_corrupted:1: ot_flash_binary:signed:fake_ecdsa_prod_key_0,otp_img_sigverify_always_rma:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2197818103 -assert nopostproc +UVM_TESTNAME=chip_base _test +UVM_TEST_SEQ=chip_sw_rom_e2e_sigverify_always_a_bad_b_bad_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de fault.vdb -cm_log /dev/null -cm_name 0.rom_e2e_sigverify_always_a_nothing_b_bad_rma.2197818103
Directory	/workspace/0.rom_e2e_sigverify_always_a_nothing_b_bad_rma/latest

Test location	/workspace/coverage/default/0.rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0.13334891
Short name	T724
Test name
Test status
Simulation time	11454332970 ps
CPU time	2734.23 seconds
Started	Aug 14 05:54:52 PM PDT 24
Finished	Aug 14 06:40:26 PM PDT 24
Peak memory	611312 kb
Host	smart-20818a0d-3360-476b-894c-2ae6805ee9c1
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=410_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_b_corrupted:1: ot_flash_binary:signed:fake_ecdsa_test_key_0,otp_img_sigverify_always_test_unlocked0:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13334891 -assert nopostproc +UVM_TESTNAME= chip_base_test +UVM_TEST_SEQ=chip_sw_rom_e2e_sigverify_always_a_bad_b_bad_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co verage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0.13334891
Directory	/workspace/0.rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0/latest

Test location	/workspace/coverage/default/0.rom_e2e_smoke.1421288190
Short name	T976
Test name
Test status
Simulation time	14764502648 ps
CPU time	3355.08 seconds
Started	Aug 14 05:52:41 PM PDT 24
Finished	Aug 14 06:48:37 PM PDT 24
Peak memory	610720 kb
Host	smart-adb2917a-3804-483b-ad14-23e001248835
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=40000000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=rom_e2e_smoke:1:new_rules,otp_img _secret2_locked_rma:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_to p/hw/dv/tools/sim.tcl +ntb_random_seed=1421288190 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_smoke.1421288190
Directory	/workspace/0.rom_e2e_smoke/latest

Test location	/workspace/coverage/default/0.rom_e2e_static_critical.4168860402
Short name	T758
Test name
Test status
Simulation time	17036833104 ps
CPU time	3868.5 seconds
Started	Aug 14 05:58:19 PM PDT 24
Finished	Aug 14 07:02:48 PM PDT 24
Peak memory	610660 kb
Host	smart-b53c89c8-9614-4e08-94bf-d6c5fca5bbce
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=40000000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=rom_e2e_static_critical:1:new_rul es,otp_img_secret2_locked_rma:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4168860402 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_static_critical.4168860402
Directory	/workspace/0.rom_e2e_static_critical/latest

Test location	/workspace/coverage/default/0.rom_keymgr_functest.2078191108
Short name	T1005
Test name
Test status
Simulation time	3697254630 ps
CPU time	516.09 seconds
Started	Aug 14 05:52:24 PM PDT 24
Finished	Aug 14 06:01:01 PM PDT 24
Peak memory	610776 kb
Host	smart-3947d53f-c864-4378-8aae-7d863b8b5343
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=10_000_000 +sw_build_device=sim_dv +sw_images=keymgr_functest:1:new_rules,test_rom:0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2078191108 -ass ert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 0.rom_keymgr_functest.2078191108
Directory	/workspace/0.rom_keymgr_functest/latest

Test location	/workspace/coverage/default/0.rom_volatile_raw_unlock.1697031067
Short name	T91
Test name
Test status
Simulation time	2702573846 ps
CPU time	110.02 seconds
Started	Aug 14 05:50:00 PM PDT 24
Finished	Aug 14 05:51:50 PM PDT 24
Peak memory	618184 kb
Host	smart-dbda556a-6397-4ea0-8e68-7e250d5da4d4
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=200_000_000 +use_otp_image=OtpTypeLcStRaw +chip_clock_source=ChipClockSourceExternal48Mhz +rom_prod_mode=1 +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_test_key_0:1:ot_flash_binary,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1697031067 -assert nopostproc +UVM_ TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_volatile_raw_unlock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag e/default.vdb -cm_log /dev/null -cm_name 0.rom_volatile_raw_unlock.1697031067
Directory	/workspace/0.rom_volatile_raw_unlock/latest

Test location	/workspace/coverage/default/1.chip_jtag_mem_access.3462386704
Short name	T99
Test name
Test status
Simulation time	14345801120 ps
CPU time	1421.61 seconds
Started	Aug 14 05:43:19 PM PDT 24
Finished	Aug 14 06:07:00 PM PDT 24
Peak memory	608468 kb
Host	smart-21aa64b7-2f8f-41d7-922c-190ec07edfa1
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3462386704 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_jtag_ mem_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_jtag_mem_access.3 462386704
Directory	/workspace/1.chip_jtag_mem_access/latest

Test location	/workspace/coverage/default/1.chip_sival_flash_info_access.3625860848
Short name	T417
Test name
Test status
Simulation time	3518199900 ps
CPU time	311.16 seconds
Started	Aug 14 05:51:45 PM PDT 24
Finished	Aug 14 05:56:56 PM PDT 24
Peak memory	610680 kb
Host	smart-00677606-fd3f-41b4-b4c0-8acd9e191408
User	root
Command	/workspace/default/simv +use_otp_image=OtpTypeLcStTestUnlocked0 +sw_build_device=sim_dv +sw_images=flash_ctrl_info_access_lc:1:new_rules,test_rom:0 +c dc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_s eed=3625860848 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sival_flash_info_access.3625860848
Directory	/workspace/1.chip_sival_flash_info_access/latest

Test location	/workspace/coverage/default/1.chip_sw_adc_ctrl_sleep_debug_cable_wakeup.3131190547
Short name	T88
Test name
Test status
Simulation time	18963773648 ps
CPU time	442.68 seconds
Started	Aug 14 05:56:07 PM PDT 24
Finished	Aug 14 06:03:30 PM PDT 24
Peak memory	620008 kb
Host	smart-8d760238-1946-414f-99c7-cfb8e89da028
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=adc_ctrl_sleep_debug_cable_wakeup_test:1:new_rules,test_rom: 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand om_seed=3131190547 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_adc_ctrl_sleep_debug_cable_wakeup_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_adc_ctrl_sleep_debug_cable_wakeup.3131190547
Directory	/workspace/1.chip_sw_adc_ctrl_sleep_debug_cable_wakeup/latest

Test location	/workspace/coverage/default/1.chip_sw_aes_enc.2916048157
Short name	T187
Test name
Test status
Simulation time	2421282628 ps
CPU time	193.19 seconds
Started	Aug 14 05:53:45 PM PDT 24
Finished	Aug 14 05:56:58 PM PDT 24
Peak memory	610464 kb
Host	smart-c25fdc38-bd32-4824-a484-443cee676d37
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=22_000_000 +sw_build_device=sim_dv +sw_images=aes_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2916048157 -asser t nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag e/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_aes_enc.2916048157
Directory	/workspace/1.chip_sw_aes_enc/latest

Test location	/workspace/coverage/default/1.chip_sw_aes_enc_jitter_en.1017953218
Short name	T694
Test name
Test status
Simulation time	2884085174 ps
CPU time	301.52 seconds
Started	Aug 14 05:53:26 PM PDT 24
Finished	Aug 14 05:58:28 PM PDT 24
Peak memory	609180 kb
Host	smart-72488a47-fc43-48f1-989e-d73c271e71fa
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=26_000_000 +en_jitter=1 +sw_build_device=sim_dv +sw_images=aes_smoketest:1:new_rules,test_rom:0 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1017 953218 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work space/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_aes_enc_jitter_en.1017953218
Directory	/workspace/1.chip_sw_aes_enc_jitter_en/latest

Test location	/workspace/coverage/default/1.chip_sw_aes_enc_jitter_en_reduced_freq.2769607870
Short name	T656
Test name
Test status
Simulation time	2869457970 ps
CPU time	269.57 seconds
Started	Aug 14 05:56:04 PM PDT 24
Finished	Aug 14 06:00:33 PM PDT 24
Peak memory	610388 kb
Host	smart-e85d22f8-e50c-4862-9323-49e1c00fd91f
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=26_000_000 +en_jitter=1 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=aes_smoketest:1:new_rules, test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2769607870 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_aes_enc_jitter_en_reduced_freq.2769607870
Directory	/workspace/1.chip_sw_aes_enc_jitter_en_reduced_freq/latest

Test location	/workspace/coverage/default/1.chip_sw_aes_entropy.3303485186
Short name	T1008
Test name
Test status
Simulation time	2550716860 ps
CPU time	307.02 seconds
Started	Aug 14 05:51:31 PM PDT 24
Finished	Aug 14 05:56:38 PM PDT 24
Peak memory	609824 kb
Host	smart-67cbdc0c-1a7f-47c6-a1b7-0dbd4795149c
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=15_000_000 +sw_build_device=sim_dv +sw_images=aes_entropy_test:1:new_rules,test_rom:0 +cdc_instrumentation _enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3303485186 -as sert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove rage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_aes_entropy.3303485186
Directory	/workspace/1.chip_sw_aes_entropy/latest

Test location	/workspace/coverage/default/1.chip_sw_aes_idle.1499040954
Short name	T572
Test name
Test status
Simulation time	2899464088 ps
CPU time	197.74 seconds
Started	Aug 14 05:55:54 PM PDT 24
Finished	Aug 14 05:59:12 PM PDT 24
Peak memory	610440 kb
Host	smart-e083bd2c-3c19-4f79-8370-6a3459ebf879
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=25_000_000 +sw_build_device=sim_dv +sw_images=aes_idle_test:1:new_rules,test_rom:0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1499040954 -asser t nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag e/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_aes_idle.1499040954
Directory	/workspace/1.chip_sw_aes_idle/latest

Test location	/workspace/coverage/default/1.chip_sw_aes_masking_off.1911974217
Short name	T992
Test name
Test status
Simulation time	2961789903 ps
CPU time	299.72 seconds
Started	Aug 14 05:53:28 PM PDT 24
Finished	Aug 14 05:58:28 PM PDT 24
Peak memory	610436 kb
Host	smart-dfdbd1b1-8574-444e-a8f2-17a5caf4da2c
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=aes_masking_off_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1911974217 -assert nopostproc +UVM_TESTNA ME=chip_base_test +UVM_TEST_SEQ=chip_sw_aes_masking_off_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_aes_masking_off.1911974217
Directory	/workspace/1.chip_sw_aes_masking_off/latest

Test location	/workspace/coverage/default/1.chip_sw_aes_smoketest.3372406833
Short name	T584
Test name
Test status
Simulation time	3313456416 ps
CPU time	357.61 seconds
Started	Aug 14 05:55:06 PM PDT 24
Finished	Aug 14 06:01:04 PM PDT 24
Peak memory	610348 kb
Host	smart-49aa0747-c237-4b1d-ba4b-d90659f3cf49
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=aes_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3372406833 -assert nopostproc +UVM_TESTNAME=chip _base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_aes_smoketest.3372406833
Directory	/workspace/1.chip_sw_aes_smoketest/latest

Test location	/workspace/coverage/default/1.chip_sw_alert_handler_entropy.226744497
Short name	T21
Test name
Test status
Simulation time	3157302665 ps
CPU time	336.81 seconds
Started	Aug 14 05:51:47 PM PDT 24
Finished	Aug 14 05:57:25 PM PDT 24
Peak memory	610332 kb
Host	smart-ccd6fb45-b63b-46b3-8af9-c1355b5ff168
User	root
Command	/workspace/default/simv +en_scb=0 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=alert_handler_entropy_test:1:new_rules,test_ro m:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=226744497 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_alert_handler_entropy.226744497
Directory	/workspace/1.chip_sw_alert_handler_entropy/latest

Test location	/workspace/coverage/default/1.chip_sw_alert_handler_escalation.89964312
Short name	T878
Test name
Test status
Simulation time	4403166224 ps
CPU time	523.42 seconds
Started	Aug 14 05:55:33 PM PDT 24
Finished	Aug 14 06:04:17 PM PDT 24
Peak memory	620308 kb
Host	smart-f447571d-1b99-42fa-9a64-b12766b9aa79
User	root
Command	/workspace/default/simv +en_scb=0 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=alert_handler_escalation_test:1:new_rules,test _rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb _random_seed=89964312 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_alert_handler_escalation_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_alert_handler_escalation.89964312
Directory	/workspace/1.chip_sw_alert_handler_escalation/latest

Test location	/workspace/coverage/default/1.chip_sw_alert_handler_lpg_clkoff.3697136905
Short name	T846
Test name
Test status
Simulation time	6205200888 ps
CPU time	1360.65 seconds
Started	Aug 14 05:52:47 PM PDT 24
Finished	Aug 14 06:15:28 PM PDT 24
Peak memory	610728 kb
Host	smart-566c68a1-1863-4ff5-8289-e770b39fcbc8
User	root
Command	/workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +sw_build_device=sim_dv +sw_images=alert_handler_lpg_clkoff_test:1:new_rules,test_r om:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r andom_seed=3697136905 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_alert_handler_lpg_clkoff_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_alert_handler_lpg_clkoff.3697136905
Directory	/workspace/1.chip_sw_alert_handler_lpg_clkoff/latest

Test location	/workspace/coverage/default/1.chip_sw_alert_handler_lpg_reset_toggle.181124769
Short name	T759
Test name
Test status
Simulation time	8074285050 ps
CPU time	2026.53 seconds
Started	Aug 14 05:51:41 PM PDT 24
Finished	Aug 14 06:25:27 PM PDT 24
Peak memory	610916 kb
Host	smart-84cb2c6f-1c03-47e5-9610-63feff0bd82e
User	root
Command	/workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +sw_build_device=sim_dv +sw_images=alert_handler_lpg_reset_toggle_test:1:new_rules, test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=181124769 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_alert_handler_shorten_ping_wait_cycle_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_alert_handler_lpg_reset_toggle.181124769
Directory	/workspace/1.chip_sw_alert_handler_lpg_reset_toggle/latest

Test location	/workspace/coverage/default/1.chip_sw_alert_handler_ping_ok.2995717393
Short name	T1024
Test name
Test status
Simulation time	7429681688 ps
CPU time	1415.12 seconds
Started	Aug 14 05:51:06 PM PDT 24
Finished	Aug 14 06:14:41 PM PDT 24
Peak memory	609712 kb
Host	smart-8b1b5be5-dd2e-435d-b900-35f9f331fd8c
User	root
Command	/workspace/default/simv +en_scb=0 +sw_test_timeout_ns=24000000 +sw_build_device=sim_dv +sw_images=alert_handler_ping_ok_test:1:new_rules,test_rom:0 +c dc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_s eed=2995717393 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_alert_handler_ping_ok.2995717393
Directory	/workspace/1.chip_sw_alert_handler_ping_ok/latest

Test location	/workspace/coverage/default/1.chip_sw_alert_handler_ping_timeout.1982940549
Short name	T655
Test name
Test status
Simulation time	3788038360 ps
CPU time	345.14 seconds
Started	Aug 14 05:55:38 PM PDT 24
Finished	Aug 14 06:01:23 PM PDT 24
Peak memory	609596 kb
Host	smart-cf9e9459-3555-4fa2-8703-9c5a92cec2a6
User	root
Command	/workspace/default/simv +en_scb=0 +sw_test_timeout_ns=24000000 +sw_build_device=sim_dv +sw_images=alert_handler_ping_timeout_test:1:new_rules,test_rom :0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=1982940549 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_alert_handler_ping_timeout.1982940549
Directory	/workspace/1.chip_sw_alert_handler_ping_timeout/latest

Test location	/workspace/coverage/default/1.chip_sw_alert_handler_reverse_ping_in_deep_sleep.3842652171
Short name	T902
Test name
Test status
Simulation time	255649805900 ps
CPU time	12240.2 seconds
Started	Aug 14 05:51:02 PM PDT 24
Finished	Aug 14 09:15:04 PM PDT 24
Peak memory	610508 kb
Host	smart-62ba8826-edbe-496b-bd91-190a5cbb32d3
User	root
Command	/workspace/default/simv +en_scb=0 +sw_test_timeout_ns=300_000_000 +sw_build_device=sim_dv +sw_images=alert_handler_reverse_ping_in_deep_sleep_test:1:n ew_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3842652171 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_alert_handler_reverse_ping_in_deep_sleep.3842652171
Directory	/workspace/1.chip_sw_alert_handler_reverse_ping_in_deep_sleep/latest

Test location	/workspace/coverage/default/1.chip_sw_aon_timer_irq.1931223770
Short name	T395
Test name
Test status
Simulation time	3213084568 ps
CPU time	335.96 seconds
Started	Aug 14 05:55:36 PM PDT 24
Finished	Aug 14 06:01:12 PM PDT 24
Peak memory	610132 kb
Host	smart-d6210cd6-48b6-44ad-99c5-78bca059656f
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=aon_timer_irq_test:1:new_rules,test_rom:0 +cdc_instrumentati on_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1931223770 - assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co verage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_aon_timer_irq.1931223770
Directory	/workspace/1.chip_sw_aon_timer_irq/latest

Test location	/workspace/coverage/default/1.chip_sw_aon_timer_sleep_wdog_sleep_pause.1753051552
Short name	T814
Test name
Test status
Simulation time	7203529268 ps
CPU time	589.92 seconds
Started	Aug 14 05:55:48 PM PDT 24
Finished	Aug 14 06:05:38 PM PDT 24
Peak memory	610968 kb
Host	smart-016cf3cf-5d37-46a5-9fc6-30177a88e081
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=aon_timer_sleep_wdog_sleep_pause_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=1753051552 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_aon_timer_sleep_wdog_sleep_pause.1753051552
Directory	/workspace/1.chip_sw_aon_timer_sleep_wdog_sleep_pause/latest

Test location	/workspace/coverage/default/1.chip_sw_aon_timer_smoketest.1622058237
Short name	T430
Test name
Test status
Simulation time	2912962040 ps
CPU time	311.73 seconds
Started	Aug 14 05:57:46 PM PDT 24
Finished	Aug 14 06:02:58 PM PDT 24
Peak memory	609880 kb
Host	smart-b19a17aa-b2c5-47c3-9c5e-b0f9e0f43027
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=aon_timer_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1622058237 -assert nopostproc +UVM_TESTNAM E=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 1.chip_sw_aon_timer_smoketest.1622058237
Directory	/workspace/1.chip_sw_aon_timer_smoketest/latest

Test location	/workspace/coverage/default/1.chip_sw_aon_timer_wdog_bite_reset.3753953976
Short name	T304
Test name
Test status
Simulation time	10233610312 ps
CPU time	1065.34 seconds
Started	Aug 14 05:54:31 PM PDT 24
Finished	Aug 14 06:12:17 PM PDT 24
Peak memory	610032 kb
Host	smart-e4623cf8-3a25-4a4b-ad18-4d58d141cb86
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=aon_timer_wdog_bite_reset_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 3753953976 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_aon_timer_wdog_bite_reset.3753953976
Directory	/workspace/1.chip_sw_aon_timer_wdog_bite_reset/latest

Test location	/workspace/coverage/default/1.chip_sw_aon_timer_wdog_lc_escalate.3109830836
Short name	T587
Test name
Test status
Simulation time	5903316120 ps
CPU time	496.02 seconds
Started	Aug 14 05:54:01 PM PDT 24
Finished	Aug 14 06:02:17 PM PDT 24
Peak memory	611124 kb
Host	smart-c2a670c5-4720-4f9c-b951-c9b75ec5daca
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=aon_timer_wdog_lc_escalate_test:1:new_rules,test_rom:0 +cdc_ instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed =3109830836 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_aon_timer_wdog_lc_escalate.3109830836
Directory	/workspace/1.chip_sw_aon_timer_wdog_lc_escalate/latest

Test location	/workspace/coverage/default/1.chip_sw_ast_clk_outputs.2667036754
Short name	T1023
Test name
Test status
Simulation time	8282453208 ps
CPU time	1154.19 seconds
Started	Aug 14 05:54:22 PM PDT 24
Finished	Aug 14 06:13:37 PM PDT 24
Peak memory	618108 kb
Host	smart-6def2de3-267c-497e-a881-9841b405f0cc
User	root
Command	/workspace/default/simv +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=ast_clk_outs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled= 1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2667036754 -assert nopo stproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_ast_clk_outputs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co verage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_ast_clk_outputs.2667036754
Directory	/workspace/1.chip_sw_ast_clk_outputs/latest

Test location	/workspace/coverage/default/1.chip_sw_ast_clk_rst_inputs.1423093163
Short name	T151
Test name
Test status
Simulation time	20628233871 ps
CPU time	2899.65 seconds
Started	Aug 14 05:54:34 PM PDT 24
Finished	Aug 14 06:42:55 PM PDT 24
Peak memory	611796 kb
Host	smart-02e83af9-8671-4ae3-aaad-4c9a2e9e5f57
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=200_000_000 +sw_build_device=sim_dv +sw_images=ast_clk_rst_inputs:1:new_rules,test_rom:0 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1423093163 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_ast_clk_rst_inputs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_ast_clk_rst_inputs.1423093163
Directory	/workspace/1.chip_sw_ast_clk_rst_inputs/latest

Test location	/workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_lc.2195777155
Short name	T688
Test name
Test status
Simulation time	6789513448 ps
CPU time	568.87 seconds
Started	Aug 14 05:56:21 PM PDT 24
Finished	Aug 14 06:05:51 PM PDT 24
Peak memory	622108 kb
Host	smart-d930663c-b567-4716-a2bd-e4649d013880
User	root
Command	/workspace/default/simv +chip_clock_source=ChipClockSourceExternal48Mhz +sw_build_device=sim_dv +sw_images=clkmgr_external_clk_src_for_lc_test:1:new_r ules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim .tcl +ntb_random_seed=2195777155 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_transition_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_clkmgr_external_clk_src_for_lc.2195777155
Directory	/workspace/1.chip_sw_clkmgr_external_clk_src_for_lc/latest

Test location	/workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_fast_dev.3202893259
Short name	T852
Test name
Test status
Simulation time	3913536156 ps
CPU time	455.44 seconds
Started	Aug 14 05:49:29 PM PDT 24
Finished	Aug 14 05:57:05 PM PDT 24
Peak memory	612160 kb
Host	smart-51f0c32e-f6e6-4b39-8efb-a7c20b8a0381
User	root
Command	/workspace/default/simv +chip_clock_source=ChipClockSourceExternal96Mhz +calibrate_usb_clk=1 +src_dec_state=DecLcStDev +sw_build_device=sim_dv +sw_ima ges=clkmgr_external_clk_src_for_sw_fast_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3202893259 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ =chip_sw_lc_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_c lkmgr_external_clk_src_for_sw_fast_dev.3202893259
Directory	/workspace/1.chip_sw_clkmgr_external_clk_src_for_sw_fast_dev/latest

Test location	/workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_fast_rma.3011134096
Short name	T756
Test name
Test status
Simulation time	4530836546 ps
CPU time	650.52 seconds
Started	Aug 14 05:54:48 PM PDT 24
Finished	Aug 14 06:05:39 PM PDT 24
Peak memory	614804 kb
Host	smart-84b34f7a-3914-407b-9207-f6b10d752c21
User	root
Command	/workspace/default/simv +chip_clock_source=ChipClockSourceExternal96Mhz +calibrate_usb_clk=1 +src_dec_state=DecLcStRma +sw_build_device=sim_dv +sw_ima ges=clkmgr_external_clk_src_for_sw_fast_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3011134096 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ =chip_sw_lc_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_c lkmgr_external_clk_src_for_sw_fast_rma.3011134096
Directory	/workspace/1.chip_sw_clkmgr_external_clk_src_for_sw_fast_rma/latest

Test location	/workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0.767247582
Short name	T607
Test name
Test status
Simulation time	3329243192 ps
CPU time	652.63 seconds
Started	Aug 14 05:54:32 PM PDT 24
Finished	Aug 14 06:05:26 PM PDT 24
Peak memory	614912 kb
Host	smart-31f9d846-fc64-40f1-b3b6-8fc91f388389
User	root
Command	/workspace/default/simv +chip_clock_source=ChipClockSourceExternal96Mhz +calibrate_usb_clk=1 +src_dec_state=DecLcStTestUnlocked0 +sw_build_device=sim_ dv +sw_images=clkmgr_external_clk_src_for_sw_fast_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=767247582 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM _TEST_SEQ=chip_sw_lc_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1. chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0.767247582
Directory	/workspace/1.chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0/latest

Test location	/workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_slow_dev.1094173170
Short name	T881
Test name
Test status
Simulation time	4833744320 ps
CPU time	585.14 seconds
Started	Aug 14 05:54:06 PM PDT 24
Finished	Aug 14 06:03:52 PM PDT 24
Peak memory	614860 kb
Host	smart-81759ef5-4f07-42be-a7ca-b5008a6c3408
User	root
Command	/workspace/default/simv +chip_clock_source=ChipClockSourceExternal48Mhz +calibrate_usb_clk=1 +src_dec_state=DecLcStDev +sw_build_device=sim_dv +sw_ima ges=clkmgr_external_clk_src_for_sw_slow_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1094173170 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ =chip_sw_lc_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_c lkmgr_external_clk_src_for_sw_slow_dev.1094173170
Directory	/workspace/1.chip_sw_clkmgr_external_clk_src_for_sw_slow_dev/latest

Test location	/workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_slow_rma.2359424595
Short name	T921
Test name
Test status
Simulation time	5169545960 ps
CPU time	609.49 seconds
Started	Aug 14 05:52:11 PM PDT 24
Finished	Aug 14 06:02:21 PM PDT 24
Peak memory	614640 kb
Host	smart-a39b6012-f11d-48c8-84a5-c854714e6d72
User	root
Command	/workspace/default/simv +chip_clock_source=ChipClockSourceExternal48Mhz +calibrate_usb_clk=1 +src_dec_state=DecLcStRma +sw_build_device=sim_dv +sw_ima ges=clkmgr_external_clk_src_for_sw_slow_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2359424595 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ =chip_sw_lc_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_c lkmgr_external_clk_src_for_sw_slow_rma.2359424595
Directory	/workspace/1.chip_sw_clkmgr_external_clk_src_for_sw_slow_rma/latest

Test location	/workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0.2773390131
Short name	T631
Test name
Test status
Simulation time	4360240420 ps
CPU time	707.63 seconds
Started	Aug 14 05:53:58 PM PDT 24
Finished	Aug 14 06:05:46 PM PDT 24
Peak memory	614872 kb
Host	smart-7917a820-32e4-4d84-857f-966a620e77f3
User	root
Command	/workspace/default/simv +chip_clock_source=ChipClockSourceExternal48Mhz +calibrate_usb_clk=1 +src_dec_state=DecLcStTestUnlocked0 +sw_build_device=sim_ dv +sw_images=clkmgr_external_clk_src_for_sw_slow_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2773390131 -assert nopostproc +UVM_TESTNAME=chip_base_test +UV M_TEST_SEQ=chip_sw_lc_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1 .chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0.2773390131
Directory	/workspace/1.chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0/latest

Test location	/workspace/coverage/default/1.chip_sw_clkmgr_jitter.1147058293
Short name	T617
Test name
Test status
Simulation time	2590705595 ps
CPU time	244.67 seconds
Started	Aug 14 05:52:26 PM PDT 24
Finished	Aug 14 05:56:31 PM PDT 24
Peak memory	610144 kb
Host	smart-89572a90-5656-4b9b-afc9-6d5a6a8db968
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=clkmgr_jitter_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1147058293 -assert nopostproc +UVM_TESTNAME =chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 1.chip_sw_clkmgr_jitter.1147058293
Directory	/workspace/1.chip_sw_clkmgr_jitter/latest

Test location	/workspace/coverage/default/1.chip_sw_clkmgr_jitter_frequency.2802866106
Short name	T747
Test name
Test status
Simulation time	3496946000 ps
CPU time	444.94 seconds
Started	Aug 14 05:52:55 PM PDT 24
Finished	Aug 14 06:00:21 PM PDT 24
Peak memory	610424 kb
Host	smart-3d602b56-97ff-4612-ad72-1db91f11faeb
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=clkmgr_jitter_frequency_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2802866106 -assert nopostproc +UV M_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -c m_log /dev/null -cm_name 1.chip_sw_clkmgr_jitter_frequency.2802866106
Directory	/workspace/1.chip_sw_clkmgr_jitter_frequency/latest

Test location	/workspace/coverage/default/1.chip_sw_clkmgr_jitter_reduced_freq.2282733949
Short name	T859
Test name
Test status
Simulation time	2648411434 ps
CPU time	235.04 seconds
Started	Aug 14 05:53:01 PM PDT 24
Finished	Aug 14 05:56:56 PM PDT 24
Peak memory	609888 kb
Host	smart-80852516-108f-452c-bd12-891fde9f42a3
User	root
Command	/workspace/default/simv +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=clkmgr_jitter_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2282733949 -assert nop ostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def ault.vdb -cm_log /dev/null -cm_name 1.chip_sw_clkmgr_jitter_reduced_freq.2282733949
Directory	/workspace/1.chip_sw_clkmgr_jitter_reduced_freq/latest

Test location	/workspace/coverage/default/1.chip_sw_clkmgr_off_aes_trans.1273759774
Short name	T750
Test name
Test status
Simulation time	4633556330 ps
CPU time	472.13 seconds
Started	Aug 14 05:53:15 PM PDT 24
Finished	Aug 14 06:01:07 PM PDT 24
Peak memory	611208 kb
Host	smart-134bb309-e2eb-456e-a06b-bf486bf1a06a
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=clkmgr_off_aes_trans_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1273759774 -assert nopostproc +UVM_T ESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l og /dev/null -cm_name 1.chip_sw_clkmgr_off_aes_trans.1273759774
Directory	/workspace/1.chip_sw_clkmgr_off_aes_trans/latest

Test location	/workspace/coverage/default/1.chip_sw_clkmgr_off_hmac_trans.1035591937
Short name	T184
Test name
Test status
Simulation time	5181356944 ps
CPU time	401.13 seconds
Started	Aug 14 05:58:57 PM PDT 24
Finished	Aug 14 06:05:38 PM PDT 24
Peak memory	611136 kb
Host	smart-5023080a-2b92-4a11-95d4-715e03709f92
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=clkmgr_off_hmac_trans_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1035591937 -assert nopostproc +UVM_ TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_ log /dev/null -cm_name 1.chip_sw_clkmgr_off_hmac_trans.1035591937
Directory	/workspace/1.chip_sw_clkmgr_off_hmac_trans/latest

Test location	/workspace/coverage/default/1.chip_sw_clkmgr_off_kmac_trans.2568403517
Short name	T914
Test name
Test status
Simulation time	3619510100 ps
CPU time	406.02 seconds
Started	Aug 14 05:55:28 PM PDT 24
Finished	Aug 14 06:02:14 PM PDT 24
Peak memory	610352 kb
Host	smart-284a0ea8-60e8-4570-a29f-d58d1ae7c390
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=clkmgr_off_kmac_trans_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2568403517 -assert nopostproc +UVM_ TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_ log /dev/null -cm_name 1.chip_sw_clkmgr_off_kmac_trans.2568403517
Directory	/workspace/1.chip_sw_clkmgr_off_kmac_trans/latest

Test location	/workspace/coverage/default/1.chip_sw_clkmgr_off_otbn_trans.4042361577
Short name	T711
Test name
Test status
Simulation time	3763090312 ps
CPU time	415.5 seconds
Started	Aug 14 05:55:36 PM PDT 24
Finished	Aug 14 06:02:31 PM PDT 24
Peak memory	610912 kb
Host	smart-60bcfa80-f64b-448e-8595-802abe142d57
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=clkmgr_off_otbn_trans_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4042361577 -assert nopostproc +UVM_ TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_ log /dev/null -cm_name 1.chip_sw_clkmgr_off_otbn_trans.4042361577
Directory	/workspace/1.chip_sw_clkmgr_off_otbn_trans/latest

Test location	/workspace/coverage/default/1.chip_sw_clkmgr_off_peri.2135185776
Short name	T176
Test name
Test status
Simulation time	10941579720 ps
CPU time	1552.23 seconds
Started	Aug 14 05:56:10 PM PDT 24
Finished	Aug 14 06:22:02 PM PDT 24
Peak memory	611080 kb
Host	smart-c149ec07-8edf-4459-8878-51147dddc400
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=30_000_000 +sw_build_device=sim_dv +sw_images=clkmgr_off_peri_test:1:new_rules,test_rom:0 +cdc_instrumenta tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2135185776 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/ coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_clkmgr_off_peri.2135185776
Directory	/workspace/1.chip_sw_clkmgr_off_peri/latest

Test location	/workspace/coverage/default/1.chip_sw_clkmgr_reset_frequency.4240119786
Short name	T122
Test name
Test status
Simulation time	4124669832 ps
CPU time	400.17 seconds
Started	Aug 14 05:57:12 PM PDT 24
Finished	Aug 14 06:03:53 PM PDT 24
Peak memory	610568 kb
Host	smart-5a877aac-d790-4f8f-aec8-dea39fb1e554
User	root
Command	/workspace/default/simv +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=clkmgr_reset_frequency_test:1:new_rules,test_rom:0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4240119786 -a ssert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov erage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_clkmgr_reset_frequency.4240119786
Directory	/workspace/1.chip_sw_clkmgr_reset_frequency/latest

Test location	/workspace/coverage/default/1.chip_sw_clkmgr_sleep_frequency.1698009262
Short name	T840
Test name
Test status
Simulation time	4886400500 ps
CPU time	643.32 seconds
Started	Aug 14 05:55:46 PM PDT 24
Finished	Aug 14 06:06:29 PM PDT 24
Peak memory	611056 kb
Host	smart-befeba06-ece0-411c-927b-ef3b29107162
User	root
Command	/workspace/default/simv +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=clkmgr_sleep_frequency_test:1:new_rules,test_rom:0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1698009262 -a ssert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov erage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_clkmgr_sleep_frequency.1698009262
Directory	/workspace/1.chip_sw_clkmgr_sleep_frequency/latest

Test location	/workspace/coverage/default/1.chip_sw_clkmgr_smoketest.1663056862
Short name	T872
Test name
Test status
Simulation time	2524573894 ps
CPU time	240.65 seconds
Started	Aug 14 05:55:55 PM PDT 24
Finished	Aug 14 05:59:56 PM PDT 24
Peak memory	609832 kb
Host	smart-d2ec8c77-5547-4331-9eea-3a27a863c57e
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=clkmgr_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1663056862 -assert nopostproc +UVM_TESTNAME=c hip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n ull -cm_name 1.chip_sw_clkmgr_smoketest.1663056862
Directory	/workspace/1.chip_sw_clkmgr_smoketest/latest

Test location	/workspace/coverage/default/1.chip_sw_csrng_edn_concurrency.382949630
Short name	T729
Test name
Test status
Simulation time	16148185496 ps
CPU time	3977.08 seconds
Started	Aug 14 05:56:24 PM PDT 24
Finished	Aug 14 07:02:42 PM PDT 24
Peak memory	610852 kb
Host	smart-fd0d4653-a031-4491-a6d0-1e4b1d86862d
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=140_000_000 +rng_srate_value_min=15 +rng_srate_value_max=20 +accelerate_cold_power_up_time=3 +accelerate_r egulators_power_up_time=2 +sw_build_device=sim_dv +sw_images=csrng_edn_concurrency_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=382949630 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_csrng_edn_concurrency.382949630
Directory	/workspace/1.chip_sw_csrng_edn_concurrency/latest

Test location	/workspace/coverage/default/1.chip_sw_csrng_edn_concurrency_reduced_freq.2902169486
Short name	T138
Test name
Test status
Simulation time	15172438856 ps
CPU time	2524.68 seconds
Started	Aug 14 05:56:59 PM PDT 24
Finished	Aug 14 06:39:04 PM PDT 24
Peak memory	611136 kb
Host	smart-72e1e7f6-4304-4d83-8c72-fc8dabadeede
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=360_000_000 +rng_srate_value_min=15 +rng_srate_value_max=20 +cal_sys_clk_70mhz=1 +en_jitter=1 +accelerate_ cold_power_up_time=3 +accelerate_regulators_power_up_time=2 +sw_build_device=sim_dv +sw_images=csrng_edn_concurrency_test:1:new_rules,test_rom:0 + cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_ seed=2902169486 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_csrng_edn_concurrency_reduced_freq.2902169486
Directory	/workspace/1.chip_sw_csrng_edn_concurrency_reduced_freq/latest

Test location	/workspace/coverage/default/1.chip_sw_csrng_fuse_en_sw_app_read_test.2070484428
Short name	T227
Test name
Test status
Simulation time	3298885276 ps
CPU time	405.44 seconds
Started	Aug 14 05:53:05 PM PDT 24
Finished	Aug 14 05:59:51 PM PDT 24
Peak memory	611092 kb
Host	smart-44693101-0765-4b40-8648-db25b8f09d26
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=15_000_000 +sw_build_device=sim_dv +sw_images=csrng_fuse_en_sw_app_read:1:new_rules,test_rom:0 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20704 84428 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_entropy_src_fuse_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_csrng_fuse_en_sw_app_read_test.2070484428
Directory	/workspace/1.chip_sw_csrng_fuse_en_sw_app_read_test/latest

Test location	/workspace/coverage/default/1.chip_sw_csrng_kat_test.2254560831
Short name	T302
Test name
Test status
Simulation time	2841663788 ps
CPU time	243.56 seconds
Started	Aug 14 05:55:56 PM PDT 24
Finished	Aug 14 06:00:00 PM PDT 24
Peak memory	610444 kb
Host	smart-d7761451-98bb-4468-bc6d-841e47bc2e08
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=csrng_kat_test:1:new_rules,test_rom:0 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2254560831 -asse rt nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera ge/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_csrng_kat_test.2254560831
Directory	/workspace/1.chip_sw_csrng_kat_test/latest

Test location	/workspace/coverage/default/1.chip_sw_csrng_smoketest.669438021
Short name	T405
Test name
Test status
Simulation time	2829894048 ps
CPU time	289.21 seconds
Started	Aug 14 05:53:34 PM PDT 24
Finished	Aug 14 05:58:23 PM PDT 24
Peak memory	610196 kb
Host	smart-8d293631-dffe-4f91-91b1-5dbe246d158a
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=csrng_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=669438021 -assert nopostproc +UVM_TESTNAME=chi p_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul l -cm_name 1.chip_sw_csrng_smoketest.669438021
Directory	/workspace/1.chip_sw_csrng_smoketest/latest

Test location	/workspace/coverage/default/1.chip_sw_data_integrity_escalation.1822174275
Short name	T298
Test name
Test status
Simulation time	4821582388 ps
CPU time	469.5 seconds
Started	Aug 14 05:53:04 PM PDT 24
Finished	Aug 14 06:00:54 PM PDT 24
Peak memory	611584 kb
Host	smart-1e0f26e4-61b1-4d1c-928b-757bde043bee
User	root
Command	/workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=data_integrity_escalation_reset_test:1:new_rules,test_ro m:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=1822174275 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_data_integrity_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_data_integrity_escalation.1822174275
Directory	/workspace/1.chip_sw_data_integrity_escalation/latest

Test location	/workspace/coverage/default/1.chip_sw_edn_auto_mode.1089498756
Short name	T964
Test name
Test status
Simulation time	4145514640 ps
CPU time	1072.05 seconds
Started	Aug 14 05:49:58 PM PDT 24
Finished	Aug 14 06:07:51 PM PDT 24
Peak memory	610440 kb
Host	smart-9e6df9c6-78fc-44cf-8eb1-abd02a6d632b
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=18_000_000 +rng_srate_value=5 +accelerate_cold_power_up_time=3 +accelerate_regulators_power_up_time=2 +sw_ build_device=sim_dv +sw_images=edn_auto_mode:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1089498756 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ =chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_edn_ auto_mode.1089498756
Directory	/workspace/1.chip_sw_edn_auto_mode/latest

Test location	/workspace/coverage/default/1.chip_sw_edn_boot_mode.658330892
Short name	T133
Test name
Test status
Simulation time	3487557754 ps
CPU time	622.6 seconds
Started	Aug 14 05:56:28 PM PDT 24
Finished	Aug 14 06:06:52 PM PDT 24
Peak memory	610808 kb
Host	smart-b5c0bba4-940c-4181-9660-fc120df1aa7a
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=18_000_000 +rng_srate_value=5 +accelerate_cold_power_up_time=3 +accelerate_regulators_power_up_time=2 +sw_ build_device=sim_dv +sw_images=edn_boot_mode:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=658330892 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ= chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_edn_b oot_mode.658330892
Directory	/workspace/1.chip_sw_edn_boot_mode/latest

Test location	/workspace/coverage/default/1.chip_sw_edn_entropy_reqs.807431164
Short name	T775
Test name
Test status
Simulation time	5739973652 ps
CPU time	937.99 seconds
Started	Aug 14 05:50:30 PM PDT 24
Finished	Aug 14 06:06:09 PM PDT 24
Peak memory	611636 kb
Host	smart-cd6a3ac4-0404-421a-9fc4-dd49d91c49bf
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=15000000 +rng_srate_value_min=15 +rng_srate_value_max=30 +sw_build_device=sim_dv +sw_images=entropy_src_ed n_reqs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=807431164 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_edn_entropy_reqs.807431164
Directory	/workspace/1.chip_sw_edn_entropy_reqs/latest

Test location	/workspace/coverage/default/1.chip_sw_edn_entropy_reqs_jitter.3327198636
Short name	T702
Test name
Test status
Simulation time	6677385285 ps
CPU time	1182.88 seconds
Started	Aug 14 05:54:49 PM PDT 24
Finished	Aug 14 06:14:32 PM PDT 24
Peak memory	611688 kb
Host	smart-d6c0d5dc-5d0f-4b75-9967-f219c1d21f47
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=15000000 +rng_srate_value_min=15 +rng_srate_value_max=30 +en_jitter=1 +sw_build_device=sim_dv +sw_images=e ntropy_src_edn_reqs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3327198636 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_edn_entropy_reqs_jitter.3327198636
Directory	/workspace/1.chip_sw_edn_entropy_reqs_jitter/latest

Test location	/workspace/coverage/default/1.chip_sw_edn_kat.1538997278
Short name	T781
Test name
Test status
Simulation time	3028316260 ps
CPU time	794.87 seconds
Started	Aug 14 05:55:52 PM PDT 24
Finished	Aug 14 06:09:07 PM PDT 24
Peak memory	617232 kb
Host	smart-3bfcac75-6d51-4556-b298-0083c0606bb6
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=18_000_000 +rng_srate_value=5 +disable_assert_edn_output_diff_from_prev=1 +accelerate_cold_power_up_time=3 +accelerate_regulators_power_up_time=2 +sw_build_device=sim_dv +sw_images=edn_kat:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1538997278 -assert nopostproc +UVM _TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm _log /dev/null -cm_name 1.chip_sw_edn_kat.1538997278
Directory	/workspace/1.chip_sw_edn_kat/latest

Test location	/workspace/coverage/default/1.chip_sw_edn_sw_mode.1209140554
Short name	T426
Test name
Test status
Simulation time	9982971736 ps
CPU time	2395.65 seconds
Started	Aug 14 05:55:36 PM PDT 24
Finished	Aug 14 06:35:32 PM PDT 24
Peak memory	610404 kb
Host	smart-4732fdc7-51cd-470d-a781-36afc12af47e
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=edn_sw_mode:1:new_rules,test_rom:0 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1209140554 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/ default.vdb -cm_log /dev/null -cm_name 1.chip_sw_edn_sw_mode.1209140554
Directory	/workspace/1.chip_sw_edn_sw_mode/latest

Test location	/workspace/coverage/default/1.chip_sw_entropy_src_ast_rng_req.1418722900
Short name	T761
Test name
Test status
Simulation time	2141967860 ps
CPU time	261.1 seconds
Started	Aug 14 05:52:04 PM PDT 24
Finished	Aug 14 05:56:25 PM PDT 24
Peak memory	610412 kb
Host	smart-0bcf1b8c-db33-4f1d-98ea-c35b32dbe275
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=15_000_000 +sw_build_device=sim_dv +sw_images=entropy_src_ast_rng_req_test:1:new_rules,test_rom:0 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14 18722900 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_entropy_src_ast_rng_req.1418722900
Directory	/workspace/1.chip_sw_entropy_src_ast_rng_req/latest

Test location	/workspace/coverage/default/1.chip_sw_entropy_src_csrng.4153917169
Short name	T355
Test name
Test status
Simulation time	7436898550 ps
CPU time	1729.2 seconds
Started	Aug 14 05:54:12 PM PDT 24
Finished	Aug 14 06:23:01 PM PDT 24
Peak memory	610960 kb
Host	smart-227ebcbf-a6dc-4d0a-8ba8-fa2e22414912
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=50_000_000 +rng_srate_value_min=15 +rng_srate_value_max=30 +sw_build_device=sim_dv +sw_images=entropy_src_ csrng_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=4153917169 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_entropy_src_csrng.4153917169
Directory	/workspace/1.chip_sw_entropy_src_csrng/latest

Test location	/workspace/coverage/default/1.chip_sw_entropy_src_kat_test.2687731966
Short name	T815
Test name
Test status
Simulation time	3214925352 ps
CPU time	272.86 seconds
Started	Aug 14 05:51:29 PM PDT 24
Finished	Aug 14 05:56:02 PM PDT 24
Peak memory	610432 kb
Host	smart-62ec6739-58c6-486c-bf03-ca1166aee3af
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=entropy_src_kat_test:1:new_rules,test_rom:0 +cdc_instrumenta tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2687731966 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/ coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_entropy_src_kat_test.2687731966
Directory	/workspace/1.chip_sw_entropy_src_kat_test/latest

Test location	/workspace/coverage/default/1.chip_sw_entropy_src_smoketest.166110244
Short name	T720
Test name
Test status
Simulation time	3575207600 ps
CPU time	611.71 seconds
Started	Aug 14 05:55:20 PM PDT 24
Finished	Aug 14 06:05:32 PM PDT 24
Peak memory	610468 kb
Host	smart-cb0b7dd9-98de-42a5-8aeb-01afebaf5a07
User	root
Command	/workspace/default/simv +rng_srate_value_min=15 +rng_srate_value_max=30 +sw_build_device=sim_dv +sw_images=entropy_src_smoketest:1:new_rules,test_rom: 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand om_seed=166110244 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_entropy_src_smoketest.166110244
Directory	/workspace/1.chip_sw_entropy_src_smoketest/latest

Test location	/workspace/coverage/default/1.chip_sw_example_concurrency.581397730
Short name	T987
Test name
Test status
Simulation time	2920504672 ps
CPU time	301.99 seconds
Started	Aug 14 05:54:06 PM PDT 24
Finished	Aug 14 05:59:09 PM PDT 24
Peak memory	610492 kb
Host	smart-8a50e0be-e105-4c58-9842-b13fe358a64d
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=example_concurrency_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=581397730 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_example_concurrency.581397730
Directory	/workspace/1.chip_sw_example_concurrency/latest

Test location	/workspace/coverage/default/1.chip_sw_example_flash.276088313
Short name	T708
Test name
Test status
Simulation time	2661593482 ps
CPU time	216.47 seconds
Started	Aug 14 05:51:04 PM PDT 24
Finished	Aug 14 05:54:40 PM PDT 24
Peak memory	610200 kb
Host	smart-5da1de37-34dd-45ae-916a-d1a5b5c55aab
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=example_test_from_flash:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=276088313 -assert nopostproc +UVM_TEST NAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_example_flash.276088313
Directory	/workspace/1.chip_sw_example_flash/latest

Test location	/workspace/coverage/default/1.chip_sw_example_manufacturer.4108554107
Short name	T799
Test name
Test status
Simulation time	2850619516 ps
CPU time	209.08 seconds
Started	Aug 14 05:49:29 PM PDT 24
Finished	Aug 14 05:52:58 PM PDT 24
Peak memory	610488 kb
Host	smart-a53c8e9b-03f3-44ee-9d92-6268b9ba79b8
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=example_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4108554107 -assert nopostproc +UVM_TESTNAME=chip_ base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_example_manufacturer.4108554107
Directory	/workspace/1.chip_sw_example_manufacturer/latest

Test location	/workspace/coverage/default/1.chip_sw_example_rom.3663383188
Short name	T913
Test name
Test status
Simulation time	2419880968 ps
CPU time	123.6 seconds
Started	Aug 14 05:52:55 PM PDT 24
Finished	Aug 14 05:54:59 PM PDT 24
Peak memory	609972 kb
Host	smart-55ceb7c2-c1ea-42d7-ad94-58a1fef1cd2e
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=example_test_from_rom:0:test_in_rom:new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3663383188 -assert nopostproc +UVM_TEST NAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_example_rom.3663383188
Directory	/workspace/1.chip_sw_example_rom/latest

Test location	/workspace/coverage/default/1.chip_sw_exit_test_unlocked_bootstrap.2684539020
Short name	T809
Test name
Test status
Simulation time	59877713290 ps
CPU time	9757.37 seconds
Started	Aug 14 05:49:13 PM PDT 24
Finished	Aug 14 08:31:51 PM PDT 24
Peak memory	625256 kb
Host	smart-f0261cbc-0560-4ca0-86b4-d760df5c4d30
User	root
Command	/workspace/default/simv +flash_program_latency=5 +sw_test_timeout_ns=150_000_000 +sw_build_device=sim_dv +sw_images=exit_test_unlocked_bootstrap:1:new _rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/s im.tcl +ntb_random_seed=2684539020 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_exit_test_unlocked_bootstrap_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_exit_test_unlocked_bootstrap.2684539020
Directory	/workspace/1.chip_sw_exit_test_unlocked_bootstrap/latest

Test location	/workspace/coverage/default/1.chip_sw_flash_crash_alert.3714815314
Short name	T575
Test name
Test status
Simulation time	5162249496 ps
CPU time	691.31 seconds
Started	Aug 14 05:53:34 PM PDT 24
Finished	Aug 14 06:05:05 PM PDT 24
Peak memory	611624 kb
Host	smart-2782c99e-90df-4d79-afda-918f343da9b9
User	root
Command	/workspace/default/simv +test_timeout_ns=8_000_000 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1: new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tool s/sim.tcl +ntb_random_seed=3714815314 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_flash_host_gnt_err_inj_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_flash_crash_alert.3714815314
Directory	/workspace/1.chip_sw_flash_crash_alert/latest

Test location	/workspace/coverage/default/1.chip_sw_flash_ctrl_access.2975864292
Short name	T438
Test name
Test status
Simulation time	5612753392 ps
CPU time	1089.09 seconds
Started	Aug 14 05:49:23 PM PDT 24
Finished	Aug 14 06:07:32 PM PDT 24
Peak memory	610684 kb
Host	smart-2a8f25b0-db47-47db-acf9-23a67cf4f80e
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=flash_ctrl_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2975864292 -assert nopostproc +UVM_TESTNAME=ch ip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu ll -cm_name 1.chip_sw_flash_ctrl_access.2975864292
Directory	/workspace/1.chip_sw_flash_ctrl_access/latest

Test location	/workspace/coverage/default/1.chip_sw_flash_ctrl_access_jitter_en.142478082
Short name	T827
Test name
Test status
Simulation time	5251057647 ps
CPU time	1163.36 seconds
Started	Aug 14 05:49:13 PM PDT 24
Finished	Aug 14 06:08:37 PM PDT 24
Peak memory	610624 kb
Host	smart-311fb60b-e0d3-4d2f-82ea-94aa5d0f836b
User	root
Command	/workspace/default/simv +en_jitter=1 +sw_build_device=sim_dv +sw_images=flash_ctrl_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=142478082 -assert nopostproc +UVM _TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm _log /dev/null -cm_name 1.chip_sw_flash_ctrl_access_jitter_en.142478082
Directory	/workspace/1.chip_sw_flash_ctrl_access_jitter_en/latest

Test location	/workspace/coverage/default/1.chip_sw_flash_ctrl_access_jitter_en_reduced_freq.1102193936
Short name	T860
Test name
Test status
Simulation time	7439843430 ps
CPU time	1191.04 seconds
Started	Aug 14 05:53:59 PM PDT 24
Finished	Aug 14 06:13:50 PM PDT 24
Peak memory	610780 kb
Host	smart-ff7e0b21-cc35-4fe2-bf32-ed1e6e401ac6
User	root
Command	/workspace/default/simv +en_jitter=1 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=flash_ctrl_test:1:new_rules,test_rom:0 +cdc_instrumentati on_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1102193936 - assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co verage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_flash_ctrl_access_jitter_en_reduced_freq.1102193936
Directory	/workspace/1.chip_sw_flash_ctrl_access_jitter_en_reduced_freq/latest

Test location	/workspace/coverage/default/1.chip_sw_flash_ctrl_clock_freqs.804194549
Short name	T883
Test name
Test status
Simulation time	6448009041 ps
CPU time	1357.17 seconds
Started	Aug 14 05:55:28 PM PDT 24
Finished	Aug 14 06:18:06 PM PDT 24
Peak memory	610760 kb
Host	smart-e38413c3-9085-4267-8eeb-64f70c5e1d7e
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=flash_ctrl_clock_freqs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=804194549 -assert nopostproc +UVM_ TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_ log /dev/null -cm_name 1.chip_sw_flash_ctrl_clock_freqs.804194549
Directory	/workspace/1.chip_sw_flash_ctrl_clock_freqs/latest

Test location	/workspace/coverage/default/1.chip_sw_flash_ctrl_idle_low_power.723564718
Short name	T672
Test name
Test status
Simulation time	4106934662 ps
CPU time	474.55 seconds
Started	Aug 14 05:51:20 PM PDT 24
Finished	Aug 14 05:59:15 PM PDT 24
Peak memory	610444 kb
Host	smart-4d63d7d3-a42f-4d9d-8262-a2d0306865ec
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=flash_ctrl_idle_low_power_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=723564718 -assert nopostproc +U VM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb - cm_log /dev/null -cm_name 1.chip_sw_flash_ctrl_idle_low_power.723564718
Directory	/workspace/1.chip_sw_flash_ctrl_idle_low_power/latest

Test location	/workspace/coverage/default/1.chip_sw_flash_ctrl_lc_rw_en.2008079590
Short name	T341
Test name
Test status
Simulation time	5157971512 ps
CPU time	652.4 seconds
Started	Aug 14 05:53:17 PM PDT 24
Finished	Aug 14 06:04:10 PM PDT 24
Peak memory	611552 kb
Host	smart-0b64a42d-094e-40ee-adbd-198d81ee8c63
User	root
Command	/workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=flash_ctrl_lc_rw_en_test:1:new_rules,test_rom:0 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20 08079590 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_flash_ctrl_lc_rw_en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_flash_ctrl_lc_rw_en.2008079590
Directory	/workspace/1.chip_sw_flash_ctrl_lc_rw_en/latest

Test location	/workspace/coverage/default/1.chip_sw_flash_ctrl_mem_protection.574470026
Short name	T1001
Test name
Test status
Simulation time	5520300742 ps
CPU time	1306.88 seconds
Started	Aug 14 05:53:20 PM PDT 24
Finished	Aug 14 06:15:08 PM PDT 24
Peak memory	609936 kb
Host	smart-dc38e28b-3d34-4693-b56c-b2467ce99f92
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=flash_ctrl_mem_protection_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=574470026 -assert nopostproc +U VM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb - cm_log /dev/null -cm_name 1.chip_sw_flash_ctrl_mem_protection.574470026
Directory	/workspace/1.chip_sw_flash_ctrl_mem_protection/latest

Test location	/workspace/coverage/default/1.chip_sw_flash_ctrl_ops.1266854703
Short name	T366
Test name
Test status
Simulation time	3758448382 ps
CPU time	585.2 seconds
Started	Aug 14 05:48:43 PM PDT 24
Finished	Aug 14 05:58:29 PM PDT 24
Peak memory	610616 kb
Host	smart-3aba41cc-4cb1-4859-bca2-ef160e825820
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=50_000_000 +sw_build_device=sim_dv +sw_images=flash_ctrl_ops_test:1:new_rules,test_rom:0 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1266854703 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/c overage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_flash_ctrl_ops.1266854703
Directory	/workspace/1.chip_sw_flash_ctrl_ops/latest

Test location	/workspace/coverage/default/1.chip_sw_flash_ctrl_ops_jitter_en.2197540592
Short name	T299
Test name
Test status
Simulation time	3910968724 ps
CPU time	890.27 seconds
Started	Aug 14 05:54:31 PM PDT 24
Finished	Aug 14 06:09:22 PM PDT 24
Peak memory	610568 kb
Host	smart-811c7822-66f8-45cf-96bf-d00224acdfa6
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=50_000_000 +en_jitter=1 +sw_build_device=sim_dv +sw_images=flash_ctrl_ops_test:1:new_rules,test_rom:0 +cdc _instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see d=2197540592 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_flash_ctrl_ops_jitter_en.2197540592
Directory	/workspace/1.chip_sw_flash_ctrl_ops_jitter_en/latest

Test location	/workspace/coverage/default/1.chip_sw_flash_ctrl_ops_jitter_en_reduced_freq.1056202695
Short name	T368
Test name
Test status
Simulation time	4804005218 ps
CPU time	636.08 seconds
Started	Aug 14 05:56:28 PM PDT 24
Finished	Aug 14 06:07:05 PM PDT 24
Peak memory	610948 kb
Host	smart-de5d6cf1-d923-4a76-be13-9c72ca8bbd1d
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=50_000_000 +en_jitter=1 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=flash_ctrl_ops_test:1:new_ rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si m.tcl +ntb_random_seed=1056202695 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_flash_ctrl_ops_jitter_en_reduced_freq.1056202695
Directory	/workspace/1.chip_sw_flash_ctrl_ops_jitter_en_reduced_freq/latest

Test location	/workspace/coverage/default/1.chip_sw_flash_ctrl_write_clear.3368157383
Short name	T556
Test name
Test status
Simulation time	3359674760 ps
CPU time	327.75 seconds
Started	Aug 14 05:54:36 PM PDT 24
Finished	Aug 14 06:00:04 PM PDT 24
Peak memory	610420 kb
Host	smart-938ddc9a-0bae-4e45-9b34-d2adb8d18fdd
User	root
Command	/workspace/default/simv +test_timeout_ns=8_000_000 +sw_build_device=sim_dv +sw_images=flash_ctrl_write_clear_test:1:new_rules,test_rom:0 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3368157 383 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ce/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_flash_ctrl_write_clear.3368157383
Directory	/workspace/1.chip_sw_flash_ctrl_write_clear/latest

Test location	/workspace/coverage/default/1.chip_sw_flash_init.3503280728
Short name	T338
Test name
Test status
Simulation time	19362451290 ps
CPU time	2456.4 seconds
Started	Aug 14 05:49:00 PM PDT 24
Finished	Aug 14 06:29:57 PM PDT 24
Peak memory	613164 kb
Host	smart-8787378e-60cd-49cb-bb51-00839a040d7f
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=25_000_000 +sw_build_device=sim_dv +sw_images=flash_init_test:0:test_in_rom:new_rules +cdc_instrumentation _enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3503280728 -as sert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_flash_init_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac e/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_flash_init.3503280728
Directory	/workspace/1.chip_sw_flash_init/latest

Test location	/workspace/coverage/default/1.chip_sw_flash_init_reduced_freq.3027709872
Short name	T339
Test name
Test status
Simulation time	20239486271 ps
CPU time	1927.65 seconds
Started	Aug 14 05:52:36 PM PDT 24
Finished	Aug 14 06:24:44 PM PDT 24
Peak memory	614060 kb
Host	smart-ac35de05-dced-49c4-b04f-982e0a94de3f
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=25_000_000 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=flash_init_test:0:test_in_rom:new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=3027709872 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_flash_init_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_flash_init_reduced_freq.3027709872
Directory	/workspace/1.chip_sw_flash_init_reduced_freq/latest

Test location	/workspace/coverage/default/1.chip_sw_flash_scrambling_smoketest.271134343
Short name	T800
Test name
Test status
Simulation time	2689676722 ps
CPU time	184.22 seconds
Started	Aug 14 05:57:29 PM PDT 24
Finished	Aug 14 06:00:34 PM PDT 24
Peak memory	610552 kb
Host	smart-761e19cf-1b16-4f36-833b-f9d60e2cf6fd
User	root
Command	/workspace/default/simv +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=flash_scrambling_smoketest:1:new_rules,flash_scrambling_smoket est_otp_img_rma:4,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=271134343 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_flash_scrambling_smoketest.271134343
Directory	/workspace/1.chip_sw_flash_scrambling_smoketest/latest

Test location	/workspace/coverage/default/1.chip_sw_gpio_smoketest.3650459257
Short name	T836
Test name
Test status
Simulation time	2445090074 ps
CPU time	363.77 seconds
Started	Aug 14 05:56:04 PM PDT 24
Finished	Aug 14 06:02:08 PM PDT 24
Peak memory	610568 kb
Host	smart-080d3e8f-abad-4958-8884-143ef8c19f93
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=gpio_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3650459257 -assert nopostproc +UVM_TESTNAME=chi p_base_test +UVM_TEST_SEQ=chip_sw_gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 1.chip_sw_gpio_smoketest.3650459257
Directory	/workspace/1.chip_sw_gpio_smoketest/latest

Test location	/workspace/coverage/default/1.chip_sw_hmac_enc.3359857288
Short name	T592
Test name
Test status
Simulation time	3415179110 ps
CPU time	304.13 seconds
Started	Aug 14 05:54:12 PM PDT 24
Finished	Aug 14 05:59:17 PM PDT 24
Peak memory	610508 kb
Host	smart-31fe663d-c0a8-406f-8161-d8c689f65b36
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=hmac_enc_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3359857288 -assert nopostproc +UVM_TESTNAME=chip _base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_hmac_enc.3359857288
Directory	/workspace/1.chip_sw_hmac_enc/latest

Test location	/workspace/coverage/default/1.chip_sw_hmac_enc_idle.616373301
Short name	T676
Test name
Test status
Simulation time	2627137144 ps
CPU time	226.31 seconds
Started	Aug 14 05:54:52 PM PDT 24
Finished	Aug 14 05:58:38 PM PDT 24
Peak memory	610364 kb
Host	smart-304804ec-c9e1-49ea-8c87-0887c9078745
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=hmac_enc_idle_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=616373301 -assert nopostproc +UVM_TESTNAME= chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/ null -cm_name 1.chip_sw_hmac_enc_idle.616373301
Directory	/workspace/1.chip_sw_hmac_enc_idle/latest

Test location	/workspace/coverage/default/1.chip_sw_hmac_enc_jitter_en.2984576844
Short name	T244
Test name
Test status
Simulation time	2946338322 ps
CPU time	321.08 seconds
Started	Aug 14 05:52:50 PM PDT 24
Finished	Aug 14 05:58:11 PM PDT 24
Peak memory	610192 kb
Host	smart-adaee43a-37fd-4a08-a4c0-46d70c5cdd5e
User	root
Command	/workspace/default/simv +en_jitter=1 +sw_build_device=sim_dv +sw_images=hmac_enc_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2984576844 -assert nopostproc +UVM_ TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_ log /dev/null -cm_name 1.chip_sw_hmac_enc_jitter_en.2984576844
Directory	/workspace/1.chip_sw_hmac_enc_jitter_en/latest

Test location	/workspace/coverage/default/1.chip_sw_hmac_enc_jitter_en_reduced_freq.1913352854
Short name	T952
Test name
Test status
Simulation time	3160863641 ps
CPU time	195.09 seconds
Started	Aug 14 05:52:27 PM PDT 24
Finished	Aug 14 05:55:43 PM PDT 24
Peak memory	610564 kb
Host	smart-20f6952c-7098-4403-a1d0-e70ce73d7d99
User	root
Command	/workspace/default/simv +en_jitter=1 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=hmac_enc_test:1:new_rules,test_rom:0 +cdc_instrumentation _enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1913352854 -as sert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove rage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_hmac_enc_jitter_en_reduced_freq.1913352854
Directory	/workspace/1.chip_sw_hmac_enc_jitter_en_reduced_freq/latest

Test location	/workspace/coverage/default/1.chip_sw_hmac_multistream.595510471
Short name	T559
Test name
Test status
Simulation time	7643176104 ps
CPU time	1721.38 seconds
Started	Aug 14 05:52:13 PM PDT 24
Finished	Aug 14 06:20:55 PM PDT 24
Peak memory	610796 kb
Host	smart-60fa1d03-7cc9-4921-b8de-3dc727bb0a1e
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=hmac_multistream_functest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=595510471 -assert nopostproc +UVM_TE STNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_lo g /dev/null -cm_name 1.chip_sw_hmac_multistream.595510471
Directory	/workspace/1.chip_sw_hmac_multistream/latest

Test location	/workspace/coverage/default/1.chip_sw_hmac_oneshot.25828448
Short name	T3
Test name
Test status
Simulation time	3138411246 ps
CPU time	385.19 seconds
Started	Aug 14 05:56:27 PM PDT 24
Finished	Aug 14 06:02:52 PM PDT 24
Peak memory	609812 kb
Host	smart-f6cead51-5564-4949-8900-0cab8cc0dc73
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=hmac_functest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25828448 -assert nopostproc +UVM_TESTNAME=chip_b ase_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 1.chip_sw_hmac_oneshot.25828448
Directory	/workspace/1.chip_sw_hmac_oneshot/latest

Test location	/workspace/coverage/default/1.chip_sw_hmac_smoketest.351978601
Short name	T682
Test name
Test status
Simulation time	2974923586 ps
CPU time	392.13 seconds
Started	Aug 14 05:55:16 PM PDT 24
Finished	Aug 14 06:01:48 PM PDT 24
Peak memory	610248 kb
Host	smart-5ef4abba-9f64-4d3c-b46f-0eb149066dc5
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=hmac_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=351978601 -assert nopostproc +UVM_TESTNAME=chip _base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_hmac_smoketest.351978601
Directory	/workspace/1.chip_sw_hmac_smoketest/latest

Test location	/workspace/coverage/default/1.chip_sw_i2c_device_tx_rx.1606632428
Short name	T361
Test name
Test status
Simulation time	3924629352 ps
CPU time	557.82 seconds
Started	Aug 14 05:57:09 PM PDT 24
Finished	Aug 14 06:06:27 PM PDT 24
Peak memory	611276 kb
Host	smart-c49b6570-7488-49b7-8e87-e6cdc31566ae
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=i2c_device_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1606632428 -assert nopostproc +UVM_TESTN AME=chip_base_test +UVM_TEST_SEQ=chip_sw_i2c_device_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v db -cm_log /dev/null -cm_name 1.chip_sw_i2c_device_tx_rx.1606632428
Directory	/workspace/1.chip_sw_i2c_device_tx_rx/latest

Test location	/workspace/coverage/default/1.chip_sw_i2c_host_tx_rx.1307699472
Short name	T242
Test name
Test status
Simulation time	5476307440 ps
CPU time	977.06 seconds
Started	Aug 14 05:56:25 PM PDT 24
Finished	Aug 14 06:12:42 PM PDT 24
Peak memory	610952 kb
Host	smart-53b2f754-4dc7-4e19-b427-f6e9c4ce36ae
User	root
Command	/workspace/default/simv +i2c_idx=0 +sw_build_device=sim_dv +sw_images=i2c_host_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1307699472 -assert nopostproc + UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_i2c_host_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de fault.vdb -cm_log /dev/null -cm_name 1.chip_sw_i2c_host_tx_rx.1307699472
Directory	/workspace/1.chip_sw_i2c_host_tx_rx/latest

Test location	/workspace/coverage/default/1.chip_sw_i2c_host_tx_rx_idx2.3182284526
Short name	T358
Test name
Test status
Simulation time	5688630648 ps
CPU time	1115.29 seconds
Started	Aug 14 05:53:05 PM PDT 24
Finished	Aug 14 06:11:41 PM PDT 24
Peak memory	611016 kb
Host	smart-8999a459-8764-4582-b083-eaaee66d088f
User	root
Command	/workspace/default/simv +i2c_idx=2 +sw_build_device=sim_dv +sw_images=i2c_host_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3182284526 -assert nopostproc + UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_i2c_host_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de fault.vdb -cm_log /dev/null -cm_name 1.chip_sw_i2c_host_tx_rx_idx2.3182284526
Directory	/workspace/1.chip_sw_i2c_host_tx_rx_idx2/latest

Test location	/workspace/coverage/default/1.chip_sw_inject_scramble_seed.1434025047
Short name	T156
Test name
Test status
Simulation time	62832370959 ps
CPU time	10688.5 seconds
Started	Aug 14 05:52:01 PM PDT 24
Finished	Aug 14 08:50:11 PM PDT 24
Peak memory	625264 kb
Host	smart-dc7c7773-9ec4-4ebc-84a4-9eb6694d18ed
User	root
Command	/workspace/default/simv +lc_at_prod=1 +flash_program_latency=5 +sw_test_timeout_ns=150_000_000 +sw_build_device=sim_dv +sw_images=inject_scramble_seed :1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=1434025047 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_inject_scramble_seed_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_inject_scramble_seed.1434025047
Directory	/workspace/1.chip_sw_inject_scramble_seed/latest

Test location	/workspace/coverage/default/1.chip_sw_keymgr_key_derivation_jitter_en.1384933120
Short name	T140
Test name
Test status
Simulation time	8281067545 ps
CPU time	1880.33 seconds
Started	Aug 14 05:52:13 PM PDT 24
Finished	Aug 14 06:23:34 PM PDT 24
Peak memory	618504 kb
Host	smart-bebd9580-bec3-452a-b024-aebdaeb88a3c
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=20_000_000 +en_jitter=1 +sw_build_device=sim_dv +sw_images=keymgr_key_derivation_test:1:new_rules,test_rom :0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=1384933120 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_keymgr_key_derivation_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_keymgr_key_derivation_jitter_en.1384933120
Directory	/workspace/1.chip_sw_keymgr_key_derivation_jitter_en/latest

Test location	/workspace/coverage/default/1.chip_sw_keymgr_key_derivation_jitter_en_reduced_freq.496831129
Short name	T128
Test name
Test status
Simulation time	8036448995 ps
CPU time	1338.05 seconds
Started	Aug 14 05:57:03 PM PDT 24
Finished	Aug 14 06:19:22 PM PDT 24
Peak memory	618232 kb
Host	smart-1ed90772-6da0-4208-b4bc-970cf6af62ce
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=20_000_000 +en_jitter=1 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=keymgr_key_derivation_test :1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=496831129 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_keymgr_key_derivation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_keymgr_key_derivation_jitter_en_ reduced_freq.496831129
Directory	/workspace/1.chip_sw_keymgr_key_derivation_jitter_en_reduced_freq/latest

Test location	/workspace/coverage/default/1.chip_sw_keymgr_key_derivation_prod.340483355
Short name	T134
Test name
Test status
Simulation time	8116477990 ps
CPU time	1071.86 seconds
Started	Aug 14 05:49:39 PM PDT 24
Finished	Aug 14 06:07:31 PM PDT 24
Peak memory	618424 kb
Host	smart-dcca55bc-0e67-4e0a-8264-b297c9c621b3
User	root
Command	/workspace/default/simv +lc_at_prod=1 +sw_test_timeout_ns=20_000_000 +sw_build_device=sim_dv +sw_images=keymgr_key_derivation_test:1:new_rules,test_ro m:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=340483355 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_keymgr_key_derivation_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_keymgr_key_derivation_prod.340483355
Directory	/workspace/1.chip_sw_keymgr_key_derivation_prod/latest

Test location	/workspace/coverage/default/1.chip_sw_keymgr_sideload_aes.1310376878
Short name	T332
Test name
Test status
Simulation time	12821075576 ps
CPU time	2582.49 seconds
Started	Aug 14 05:52:33 PM PDT 24
Finished	Aug 14 06:35:36 PM PDT 24
Peak memory	612104 kb
Host	smart-884b2a02-91f4-4972-8f17-52e6da45eb54
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=20_000_000 +sw_build_device=sim_dv +sw_images=keymgr_sideload_aes_test:1:new_rules,test_rom:0 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=131037 6878 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_keymgr_sideload_aes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_keymgr_sideload_aes.1310376878
Directory	/workspace/1.chip_sw_keymgr_sideload_aes/latest

Test location	/workspace/coverage/default/1.chip_sw_keymgr_sideload_otbn.1967807946
Short name	T334
Test name
Test status
Simulation time	14882868982 ps
CPU time	3789.75 seconds
Started	Aug 14 05:52:03 PM PDT 24
Finished	Aug 14 06:55:13 PM PDT 24
Peak memory	611348 kb
Host	smart-9efabd8e-b616-4f6d-b3db-ac2da933a0b0
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=20_000_000 +sw_build_device=sim_dv +sw_images=keymgr_sideload_otbn_test:1:new_rules,test_rom:0 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19678 07946 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_keymgr_sideload_otbn.1967807946
Directory	/workspace/1.chip_sw_keymgr_sideload_otbn/latest

Test location	/workspace/coverage/default/1.chip_sw_kmac_app_rom.784473626
Short name	T170
Test name
Test status
Simulation time	2280622560 ps
CPU time	191.06 seconds
Started	Aug 14 05:53:42 PM PDT 24
Finished	Aug 14 05:56:54 PM PDT 24
Peak memory	610332 kb
Host	smart-496c98a8-5c33-4f9c-be14-57f7b89adca2
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=kmac_app_rom_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=784473626 -assert nopostproc +UVM_TESTNAME=c hip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n ull -cm_name 1.chip_sw_kmac_app_rom.784473626
Directory	/workspace/1.chip_sw_kmac_app_rom/latest

Test location	/workspace/coverage/default/1.chip_sw_kmac_entropy.2524056160
Short name	T1030
Test name
Test status
Simulation time	3310328520 ps
CPU time	317.97 seconds
Started	Aug 14 05:50:30 PM PDT 24
Finished	Aug 14 05:55:49 PM PDT 24
Peak memory	610356 kb
Host	smart-9b39ff42-7720-4c0d-847e-a13e5026d4c2
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=kmac_entropy_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2524056160 -assert nopostproc +UVM_TESTNAME= chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/ null -cm_name 1.chip_sw_kmac_entropy.2524056160
Directory	/workspace/1.chip_sw_kmac_entropy/latest

Test location	/workspace/coverage/default/1.chip_sw_kmac_idle.1096623323
Short name	T645
Test name
Test status
Simulation time	2533868072 ps
CPU time	292.49 seconds
Started	Aug 14 05:56:50 PM PDT 24
Finished	Aug 14 06:01:43 PM PDT 24
Peak memory	610424 kb
Host	smart-395ee6db-b235-4aee-a7a0-f2d096e22eff
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=kmac_idle_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1096623323 -assert nopostproc +UVM_TESTNAME=chi p_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul l -cm_name 1.chip_sw_kmac_idle.1096623323
Directory	/workspace/1.chip_sw_kmac_idle/latest

Test location	/workspace/coverage/default/1.chip_sw_kmac_mode_cshake.3251514393
Short name	T558
Test name
Test status
Simulation time	3318715180 ps
CPU time	293.48 seconds
Started	Aug 14 05:54:03 PM PDT 24
Finished	Aug 14 05:58:57 PM PDT 24
Peak memory	610476 kb
Host	smart-74195a5d-fcbe-4c71-adcc-cd593649e69d
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=kmac_mode_cshake_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3251514393 -assert nopostproc +UVM_TESTN AME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log / dev/null -cm_name 1.chip_sw_kmac_mode_cshake.3251514393
Directory	/workspace/1.chip_sw_kmac_mode_cshake/latest

Test location	/workspace/coverage/default/1.chip_sw_kmac_mode_kmac.2996459309
Short name	T181
Test name
Test status
Simulation time	3005629300 ps
CPU time	292.79 seconds
Started	Aug 14 05:54:43 PM PDT 24
Finished	Aug 14 05:59:36 PM PDT 24
Peak memory	610276 kb
Host	smart-82dd21f7-5dd4-41a8-8ea1-bdacf9fe6306
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=kmac_mode_kmac_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2996459309 -assert nopostproc +UVM_TESTNAM E=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 1.chip_sw_kmac_mode_kmac.2996459309
Directory	/workspace/1.chip_sw_kmac_mode_kmac/latest

Test location	/workspace/coverage/default/1.chip_sw_kmac_mode_kmac_jitter_en.2555574119
Short name	T696
Test name
Test status
Simulation time	3290843652 ps
CPU time	281.56 seconds
Started	Aug 14 05:54:50 PM PDT 24
Finished	Aug 14 05:59:32 PM PDT 24
Peak memory	610468 kb
Host	smart-e1d08418-0011-4b77-bb44-b210a8937dbc
User	root
Command	/workspace/default/simv +en_jitter=1 +sw_build_device=sim_dv +sw_images=kmac_mode_kmac_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2555574119 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd b -cm_log /dev/null -cm_name 1.chip_sw_kmac_mode_kmac_jitter_en.2555574119
Directory	/workspace/1.chip_sw_kmac_mode_kmac_jitter_en/latest

Test location	/workspace/coverage/default/1.chip_sw_kmac_mode_kmac_jitter_en_reduced_freq.2164755795
Short name	T643
Test name
Test status
Simulation time	3149198481 ps
CPU time	309.88 seconds
Started	Aug 14 05:52:32 PM PDT 24
Finished	Aug 14 05:57:42 PM PDT 24
Peak memory	610444 kb
Host	smart-e7f5d774-cfb2-4031-b9e3-5c5d665c14e9
User	root
Command	/workspace/default/simv +en_jitter=1 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=kmac_mode_kmac_test:1:new_rules,test_rom:0 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21647557 95 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac e/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_kmac_mode_kmac_jitter_en_reduced_freq.2164755795
Directory	/workspace/1.chip_sw_kmac_mode_kmac_jitter_en_reduced_freq/latest

Test location	/workspace/coverage/default/1.chip_sw_kmac_smoketest.3873841496
Short name	T588
Test name
Test status
Simulation time	2745718458 ps
CPU time	283.22 seconds
Started	Aug 14 05:56:24 PM PDT 24
Finished	Aug 14 06:01:07 PM PDT 24
Peak memory	610204 kb
Host	smart-a4cf569e-1197-46aa-8f5b-aeef892ff1dc
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=kmac_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3873841496 -assert nopostproc +UVM_TESTNAME=chi p_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul l -cm_name 1.chip_sw_kmac_smoketest.3873841496
Directory	/workspace/1.chip_sw_kmac_smoketest/latest

Test location	/workspace/coverage/default/1.chip_sw_lc_ctrl_otp_hw_cfg0.1812158070
Short name	T795
Test name
Test status
Simulation time	2639675768 ps
CPU time	325.89 seconds
Started	Aug 14 05:52:49 PM PDT 24
Finished	Aug 14 05:58:15 PM PDT 24
Peak memory	610348 kb
Host	smart-5800ad7e-c211-4ed1-9ce6-55e71bb7f9fe
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=lc_ctrl_otp_hw_cfg0_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1812158070 -assert nopostproc +UVM_TE STNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_lo g /dev/null -cm_name 1.chip_sw_lc_ctrl_otp_hw_cfg0.1812158070
Directory	/workspace/1.chip_sw_lc_ctrl_otp_hw_cfg0/latest

Test location	/workspace/coverage/default/1.chip_sw_lc_ctrl_program_error.3056361099
Short name	T215
Test name
Test status
Simulation time	5404863600 ps
CPU time	587.25 seconds
Started	Aug 14 05:52:05 PM PDT 24
Finished	Aug 14 06:01:53 PM PDT 24
Peak memory	611468 kb
Host	smart-23a69e2b-9205-49c6-af7c-f09e4658f9f5
User	root
Command	/workspace/default/simv +en_scb=0 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=lc_ctrl_program_error:1:new_rules,test_rom:0 + cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_ seed=3056361099 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_program_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_lc_ctrl_program_error.3056361099
Directory	/workspace/1.chip_sw_lc_ctrl_program_error/latest

Test location	/workspace/coverage/default/1.chip_sw_lc_ctrl_rand_to_scrap.215964421
Short name	T951
Test name
Test status
Simulation time	2418637326 ps
CPU time	137.21 seconds
Started	Aug 14 05:54:29 PM PDT 24
Finished	Aug 14 05:56:46 PM PDT 24
Peak memory	620588 kb
Host	smart-4b5d4758-9067-4fd5-b57b-42bffc5de37c
User	root
Command	/workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=lc_ctrl_scrap_test:1:new_rules,test_rom:0 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21596442 1 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_scrap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_lc_ctrl_rand_to_scrap.215964421
Directory	/workspace/1.chip_sw_lc_ctrl_rand_to_scrap/latest

Test location	/workspace/coverage/default/1.chip_sw_lc_ctrl_transition.2235019686
Short name	T900
Test name
Test status
Simulation time	11768029432 ps
CPU time	928.55 seconds
Started	Aug 14 05:49:39 PM PDT 24
Finished	Aug 14 06:05:08 PM PDT 24
Peak memory	622124 kb
Host	smart-1067c6ff-f200-4e3b-bc62-af4c8e222758
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=lc_ctrl_transition_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2235019686 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_transition_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau lt.vdb -cm_log /dev/null -cm_name 1.chip_sw_lc_ctrl_transition.2235019686
Directory	/workspace/1.chip_sw_lc_ctrl_transition/latest

Test location	/workspace/coverage/default/1.chip_sw_lc_ctrl_volatile_raw_unlock.2285678844
Short name	T286
Test name
Test status
Simulation time	2224927348 ps
CPU time	105.44 seconds
Started	Aug 14 05:53:50 PM PDT 24
Finished	Aug 14 05:55:36 PM PDT 24
Peak memory	619000 kb
Host	smart-15fda145-f4dc-4bd0-a9a0-cce1602f31da
User	root
Command	/workspace/default/simv +use_otp_image=OtpTypeLcStRaw +exp_volatile_raw_unlock_en=0 +sw_build_device=sim_dv +sw_images=lc_ctrl_volatile_raw_unlock_tes t:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/ tools/sim.tcl +ntb_random_seed=2285678844 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_volatile_raw_unlock_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_lc_ctrl_volatile_raw_unlock.2285678844
Directory	/workspace/1.chip_sw_lc_ctrl_volatile_raw_unlock/latest

Test location	/workspace/coverage/default/1.chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz.3263838522
Short name	T287
Test name
Test status
Simulation time	2603247600 ps
CPU time	119.18 seconds
Started	Aug 14 05:54:49 PM PDT 24
Finished	Aug 14 05:56:49 PM PDT 24
Peak memory	617980 kb
Host	smart-daebfe46-ba3a-4515-88a0-75e7dc2797af
User	root
Command	/workspace/default/simv +use_otp_image=OtpTypeLcStRaw +chip_clock_source=ChipClockSourceExternal48Mhz +exp_volatile_raw_unlock_en=0 +sw_build_device=s im_dv +sw_images=lc_ctrl_volatile_raw_unlock_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3263838522 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TES T_SEQ=chip_sw_lc_volatile_raw_unlock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz.3263838522
Directory	/workspace/1.chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz/latest

Test location	/workspace/coverage/default/1.chip_sw_lc_walkthrough_dev.496216531
Short name	T340
Test name
Test status
Simulation time	50167509420 ps
CPU time	5059.12 seconds
Started	Aug 14 05:54:15 PM PDT 24
Finished	Aug 14 07:18:35 PM PDT 24
Peak memory	620224 kb
Host	smart-a9cc27d8-e08f-433f-b398-915273196293
User	root
Command	/workspace/default/simv +flash_program_latency=5 +use_otp_image=OtpTypeLcStRaw +dest_dec_state=DecLcStDev +sw_test_timeout_ns=200_000_000 +sw_build_de vice=sim_dv +sw_images=lc_walkthrough_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=496216531 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=ch ip_sw_lc_walkthrough_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_ sw_lc_walkthrough_dev.496216531
Directory	/workspace/1.chip_sw_lc_walkthrough_dev/latest

Test location	/workspace/coverage/default/1.chip_sw_lc_walkthrough_prod.738564528
Short name	T342
Test name
Test status
Simulation time	49661291258 ps
CPU time	5948.12 seconds
Started	Aug 14 05:52:47 PM PDT 24
Finished	Aug 14 07:31:56 PM PDT 24
Peak memory	624932 kb
Host	smart-643dbfe6-c018-4d1e-b43d-45409b36b0c1
User	root
Command	/workspace/default/simv +flash_program_latency=5 +use_otp_image=OtpTypeLcStRaw +dest_dec_state=DecLcStProd +sw_test_timeout_ns=200_000_000 +sw_build_d evice=sim_dv +sw_images=lc_walkthrough_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=738564528 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=c hip_sw_lc_walkthrough_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip _sw_lc_walkthrough_prod.738564528
Directory	/workspace/1.chip_sw_lc_walkthrough_prod/latest

Test location	/workspace/coverage/default/1.chip_sw_lc_walkthrough_prodend.1840569515
Short name	T658
Test name
Test status
Simulation time	9602237485 ps
CPU time	898.51 seconds
Started	Aug 14 05:52:34 PM PDT 24
Finished	Aug 14 06:07:34 PM PDT 24
Peak memory	619572 kb
Host	smart-edff5b6d-0450-415f-9504-98de2d4dbf6f
User	root
Command	/workspace/default/simv +flash_program_latency=5 +use_otp_image=OtpTypeLcStRaw +dest_dec_state=DecLcStProdEnd +sw_build_device=sim_dv +sw_images=lc_wa lkthrough_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1840569515 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_walkthrough_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_lc_walkthrough_prodend.1840569515
Directory	/workspace/1.chip_sw_lc_walkthrough_prodend/latest

Test location	/workspace/coverage/default/1.chip_sw_lc_walkthrough_rma.1302333054
Short name	T337
Test name
Test status
Simulation time	46551097052 ps
CPU time	5693.19 seconds
Started	Aug 14 05:53:31 PM PDT 24
Finished	Aug 14 07:28:25 PM PDT 24
Peak memory	620124 kb
Host	smart-3457a3b0-1336-428a-b040-3dc5c8ef11d8
User	root
Command	/workspace/default/simv +use_otp_image=OtpTypeLcStRaw +dest_dec_state=DecLcStRma +flash_program_latency=5 +sw_test_timeout_ns=200_000_000 +sw_build_de vice=sim_dv +sw_images=lc_walkthrough_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1302333054 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=c hip_sw_lc_walkthrough_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip _sw_lc_walkthrough_rma.1302333054
Directory	/workspace/1.chip_sw_lc_walkthrough_rma/latest

Test location	/workspace/coverage/default/1.chip_sw_lc_walkthrough_testunlocks.67758915
Short name	T690
Test name
Test status
Simulation time	24124489525 ps
CPU time	2062.47 seconds
Started	Aug 14 05:52:03 PM PDT 24
Finished	Aug 14 06:26:26 PM PDT 24
Peak memory	621488 kb
Host	smart-47fb3997-927a-4576-8d9e-0277255cb18b
User	root
Command	/workspace/default/simv +use_otp_image=OtpTypeLcStRaw +dest_dec_state=DecLcStTestUnlock7 +sw_build_device=sim_dv +sw_images=lc_walkthrough_testunlocks _test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=67758915 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_walkthrough_testunlocks_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_lc_walkthrough_testunlocks.67758915
Directory	/workspace/1.chip_sw_lc_walkthrough_testunlocks/latest

Test location	/workspace/coverage/default/1.chip_sw_otbn_ecdsa_op_irq.3712513311
Short name	T906
Test name
Test status
Simulation time	17578632936 ps
CPU time	3618.65 seconds
Started	Aug 14 05:51:37 PM PDT 24
Finished	Aug 14 06:51:56 PM PDT 24
Peak memory	610984 kb
Host	smart-c7f07e09-d8c8-4aaf-986c-d65b777a2858
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=28_000_000 +rng_srate_value=30 +sw_build_device=sim_dv +sw_images=otbn_ecdsa_op_irq_test:1:new_rules,test_ rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ random_seed=3712513311 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_otbn_ecdsa_op_irq.3712513311
Directory	/workspace/1.chip_sw_otbn_ecdsa_op_irq/latest

Test location	/workspace/coverage/default/1.chip_sw_otbn_ecdsa_op_irq_jitter_en.2193364676
Short name	T609
Test name
Test status
Simulation time	18516347258 ps
CPU time	3141.05 seconds
Started	Aug 14 05:48:15 PM PDT 24
Finished	Aug 14 06:40:36 PM PDT 24
Peak memory	608112 kb
Host	smart-29a0e39e-e973-4001-a680-5a81dc07b688
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=33_000_000 +rng_srate_value=30 +en_jitter=1 +sw_build_device=sim_dv +sw_images=otbn_ecdsa_op_irq_test:1:ne w_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/ sim.tcl +ntb_random_seed=2193364676 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tg l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_otbn_ecdsa_op_irq_jitter_en.2193364676
Directory	/workspace/1.chip_sw_otbn_ecdsa_op_irq_jitter_en/latest

Test location	/workspace/coverage/default/1.chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq.1336412859
Short name	T1026
Test name
Test status
Simulation time	24989080441 ps
CPU time	3787.57 seconds
Started	Aug 14 05:53:33 PM PDT 24
Finished	Aug 14 06:56:41 PM PDT 24
Peak memory	611128 kb
Host	smart-feadf8c8-22fa-4a4b-aa92-50e79bdd5c9f
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=33_000_000 +rng_srate_value=30 +en_jitter=1 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=otbn_e cdsa_op_irq_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/ repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1336412859 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_otbn_ecdsa_op_irq_jitter_en_redu ced_freq.1336412859
Directory	/workspace/1.chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq/latest

Test location	/workspace/coverage/default/1.chip_sw_otbn_mem_scramble.2743372566
Short name	T296
Test name
Test status
Simulation time	3119035350 ps
CPU time	613.38 seconds
Started	Aug 14 05:55:36 PM PDT 24
Finished	Aug 14 06:05:50 PM PDT 24
Peak memory	610348 kb
Host	smart-45d56313-f67a-45e0-a5c7-df2de156ffc6
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=15_000_000 +en_scb_tl_err_chk=0 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=otbn _mem_scramble_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2743372566 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_otbn_mem_scramble.2743372566
Directory	/workspace/1.chip_sw_otbn_mem_scramble/latest

Test location	/workspace/coverage/default/1.chip_sw_otbn_randomness.1973538530
Short name	T884
Test name
Test status
Simulation time	6056083576 ps
CPU time	1127.12 seconds
Started	Aug 14 05:50:52 PM PDT 24
Finished	Aug 14 06:09:40 PM PDT 24
Peak memory	611132 kb
Host	smart-498313f8-91fc-435e-8f11-d92da01334e3
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=18_000_000 +rng_srate_value=30 +sw_build_device=sim_dv +sw_images=otbn_randomness_test:1:new_rules,test_ro m:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=1973538530 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_otbn_randomness.1973538530
Directory	/workspace/1.chip_sw_otbn_randomness/latest

Test location	/workspace/coverage/default/1.chip_sw_otbn_smoketest.3442109870
Short name	T200
Test name
Test status
Simulation time	5484569470 ps
CPU time	984.6 seconds
Started	Aug 14 05:53:27 PM PDT 24
Finished	Aug 14 06:09:51 PM PDT 24
Peak memory	610748 kb
Host	smart-98e6c06c-78f2-49bf-bb4d-0b18c2c266d7
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=otbn_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3442109870 -assert nopostproc +UVM_TESTNAME=chi p_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul l -cm_name 1.chip_sw_otbn_smoketest.3442109870
Directory	/workspace/1.chip_sw_otbn_smoketest/latest

Test location	/workspace/coverage/default/1.chip_sw_otp_ctrl_ecc_error_vendor_test.3528294953
Short name	T666
Test name
Test status
Simulation time	2581890960 ps
CPU time	221.86 seconds
Started	Aug 14 05:52:35 PM PDT 24
Finished	Aug 14 05:56:17 PM PDT 24
Peak memory	609176 kb
Host	smart-54a0657f-419c-4f60-b554-25173e3bce52
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=otp_ctrl_vendor_test_ecc_error_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3528294953 -assert nopostp roc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_otp_ctrl_vendor_test_ecc_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_otp_ctrl_ecc_error_vendor_test.3528294953
Directory	/workspace/1.chip_sw_otp_ctrl_ecc_error_vendor_test/latest

Test location	/workspace/coverage/default/1.chip_sw_otp_ctrl_lc_signals_dev.1817751266
Short name	T834
Test name
Test status
Simulation time	7903844800 ps
CPU time	1435.85 seconds
Started	Aug 14 05:49:54 PM PDT 24
Finished	Aug 14 06:13:50 PM PDT 24
Peak memory	610488 kb
Host	smart-33ad169a-aaa7-416c-b719-e68df6e5aea5
User	root
Command	/workspace/default/simv +use_otp_image=OtpTypeLcStDev +otp_clear_secret2=1 +sw_build_device=sim_dv +sw_images=otp_ctrl_lc_signals_test:1:new_rules,tes t_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +nt b_random_seed=1817751266 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_otp_ctrl_lc_signals_dev.1817751266
Directory	/workspace/1.chip_sw_otp_ctrl_lc_signals_dev/latest

Test location	/workspace/coverage/default/1.chip_sw_otp_ctrl_lc_signals_prod.2306312186
Short name	T970
Test name
Test status
Simulation time	8827760814 ps
CPU time	1626.18 seconds
Started	Aug 14 05:52:20 PM PDT 24
Finished	Aug 14 06:19:26 PM PDT 24
Peak memory	611416 kb
Host	smart-7991ccb9-0e9a-43bb-a475-3edd23fef5b0
User	root
Command	/workspace/default/simv +use_otp_image=OtpTypeLcStProd +otp_clear_secret2=1 +sw_build_device=sim_dv +sw_images=otp_ctrl_lc_signals_test:1:new_rules,te st_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n tb_random_seed=2306312186 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_otp_ctrl_lc_signals_prod.2306312186
Directory	/workspace/1.chip_sw_otp_ctrl_lc_signals_prod/latest

Test location	/workspace/coverage/default/1.chip_sw_otp_ctrl_lc_signals_rma.2057814697
Short name	T1017
Test name
Test status
Simulation time	9062574872 ps
CPU time	1274.88 seconds
Started	Aug 14 05:48:57 PM PDT 24
Finished	Aug 14 06:10:13 PM PDT 24
Peak memory	610820 kb
Host	smart-562ba5cd-6642-4bea-aba1-ce659c5ccde4
User	root
Command	/workspace/default/simv +use_otp_image=OtpTypeLcStRma +otp_clear_secret2=1 +sw_build_device=sim_dv +sw_images=otp_ctrl_lc_signals_test:1:new_rules,tes t_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +nt b_random_seed=2057814697 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_otp_ctrl_lc_signals_rma.2057814697
Directory	/workspace/1.chip_sw_otp_ctrl_lc_signals_rma/latest

Test location	/workspace/coverage/default/1.chip_sw_otp_ctrl_lc_signals_test_unlocked0.1970597838
Short name	T861
Test name
Test status
Simulation time	4525934664 ps
CPU time	718.65 seconds
Started	Aug 14 05:50:22 PM PDT 24
Finished	Aug 14 06:02:21 PM PDT 24
Peak memory	610352 kb
Host	smart-545e2b7f-61b5-4cdd-86fa-1c750ecae6bb
User	root
Command	/workspace/default/simv +use_otp_image=OtpTypeLcStTestUnlocked0 +otp_clear_secret2=1 +sw_build_device=sim_dv +sw_images=otp_ctrl_lc_signals_test:1:new _rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/s im.tcl +ntb_random_seed=1970597838 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_otp_ctrl_lc_signals_test_unlocked0.1970597838
Directory	/workspace/1.chip_sw_otp_ctrl_lc_signals_test_unlocked0/latest

Test location	/workspace/coverage/default/1.chip_sw_otp_ctrl_smoketest.3104693398
Short name	T311
Test name
Test status
Simulation time	2513863064 ps
CPU time	220.71 seconds
Started	Aug 14 05:56:00 PM PDT 24
Finished	Aug 14 05:59:41 PM PDT 24
Peak memory	610500 kb
Host	smart-783bf08b-e12e-4522-bcb9-d5a37dc165b7
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=otp_ctrl_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3104693398 -assert nopostproc +UVM_TESTNAME =chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 1.chip_sw_otp_ctrl_smoketest.3104693398
Directory	/workspace/1.chip_sw_otp_ctrl_smoketest/latest

Test location	/workspace/coverage/default/1.chip_sw_pattgen_ios.3365307363
Short name	T372
Test name
Test status
Simulation time	2657805252 ps
CPU time	222.15 seconds
Started	Aug 14 05:52:02 PM PDT 24
Finished	Aug 14 05:55:45 PM PDT 24
Peak memory	613840 kb
Host	smart-bb3c687f-c487-4cc2-bf29-f2fdcb737e17
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=5_000_000 +sw_build_device=sim_dv +sw_images=pattgen_ios_test:1:new_rules,test_rom:0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3365307363 -ass ert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_patt_ios_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/c overage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_pattgen_ios.3365307363
Directory	/workspace/1.chip_sw_pattgen_ios/latest

Test location	/workspace/coverage/default/1.chip_sw_plic_sw_irq.401412333
Short name	T270
Test name
Test status
Simulation time	2928402752 ps
CPU time	235.61 seconds
Started	Aug 14 05:50:27 PM PDT 24
Finished	Aug 14 05:54:23 PM PDT 24
Peak memory	609824 kb
Host	smart-eb244021-dfc7-4c2d-b853-7847b30a0c3a
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=plic_sw_irq_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=401412333 -assert nopostproc +UVM_TESTNAME=ch ip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu ll -cm_name 1.chip_sw_plic_sw_irq.401412333
Directory	/workspace/1.chip_sw_plic_sw_irq/latest

Test location	/workspace/coverage/default/1.chip_sw_power_idle_load.2348362624
Short name	T997
Test name
Test status
Simulation time	4646159448 ps
CPU time	620.15 seconds
Started	Aug 14 05:53:04 PM PDT 24
Finished	Aug 14 06:03:24 PM PDT 24
Peak memory	610340 kb
Host	smart-ba473482-0645-44d4-b543-8f4410995deb
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=chip_power_idle_load:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2348362624 -assert nopostproc +UVM_TESTNA ME=chip_base_test +UVM_TEST_SEQ=chip_sw_power_idle_load_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_power_idle_load.2348362624
Directory	/workspace/1.chip_sw_power_idle_load/latest

Test location	/workspace/coverage/default/1.chip_sw_power_virus.2084950056
Short name	T63
Test name
Test status
Simulation time	6393920280 ps
CPU time	1502.4 seconds
Started	Aug 14 06:00:32 PM PDT 24
Finished	Aug 14 06:25:34 PM PDT 24
Peak memory	625480 kb
Host	smart-f49a0c25-1572-48d4-b733-20acb05fbaed
User	root
Command	/workspace/default/simv +rng_srate_value_min=15 +rng_srate_value_max=20 +sw_test_timeout_ns=400_000_000 +use_otp_image=OtpTypeCustom +accelerate_cold_ power_up_time=3 +accelerate_regulators_power_up_time=2 +sw_build_device=sim_dv +sw_images=power_virus_systemtest:1:new_rules,power_virus_systemtes t_otp_img_rma:4,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d v/tools/sim.tcl +ntb_random_seed=2084950056 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_power_virus_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_power_virus.2084950056
Directory	/workspace/1.chip_sw_power_virus/latest

Test location	/workspace/coverage/default/1.chip_sw_pwrmgr_all_reset_reqs.2250437278
Short name	T1002
Test name
Test status
Simulation time	11530754395 ps
CPU time	1333.5 seconds
Started	Aug 14 05:53:45 PM PDT 24
Finished	Aug 14 06:15:59 PM PDT 24
Peak memory	611952 kb
Host	smart-593a81ff-e263-4a70-8d59-e9d236320f38
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=50_000_000 +sw_build_device=sim_dv +sw_images=pwrmgr_all_reset_reqs_test:1:new_rules,test_rom:0 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2250 437278 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_deep_sleep_all_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_pwrmgr_all_reset_reqs.2250437278
Directory	/workspace/1.chip_sw_pwrmgr_all_reset_reqs/latest

Test location	/workspace/coverage/default/1.chip_sw_pwrmgr_b2b_sleep_reset_req.1404013861
Short name	T27
Test name
Test status
Simulation time	21758833252 ps
CPU time	2072.71 seconds
Started	Aug 14 05:55:40 PM PDT 24
Finished	Aug 14 06:30:13 PM PDT 24
Peak memory	611556 kb
Host	smart-ec9b0fc7-db1d-49e4-b7d7-3d73e81e6a67
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=35_000_000 +sw_build_device=sim_dv +sw_images=pwrmgr_b2b_sleep_reset_test:1:new_rules,test_rom:0 +cdc_inst rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=140 4013861 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_repeat_reset_wkup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_pwrmgr_b2b_sleep_reset_req.1404013861
Directory	/workspace/1.chip_sw_pwrmgr_b2b_sleep_reset_req/latest

Test location	/workspace/coverage/default/1.chip_sw_pwrmgr_deep_sleep_all_reset_reqs.1167350573
Short name	T582
Test name
Test status
Simulation time	15591220396 ps
CPU time	1828.38 seconds
Started	Aug 14 05:54:22 PM PDT 24
Finished	Aug 14 06:24:51 PM PDT 24
Peak memory	612044 kb
Host	smart-de387d57-df29-4e8f-8c39-d7a1a2b55116
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=50_000_000 +sw_build_device=sim_dv +sw_images=pwrmgr_deep_sleep_all_reset_reqs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=1167350573 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_deep_sleep_all_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_pwrmgr_deep_sleep_all_reset_reqs.1167350573
Directory	/workspace/1.chip_sw_pwrmgr_deep_sleep_all_reset_reqs/latest

Test location	/workspace/coverage/default/1.chip_sw_pwrmgr_deep_sleep_all_wake_ups.1950508654
Short name	T410
Test name
Test status
Simulation time	26631273892 ps
CPU time	1867.15 seconds
Started	Aug 14 05:59:11 PM PDT 24
Finished	Aug 14 06:30:18 PM PDT 24
Peak memory	611468 kb
Host	smart-98727af1-b7fc-4f26-8ca0-865135975e68
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=pwrmgr_deep_sleep_all_wake_ups:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 1950508654 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_pwrmgr_deep_sleep_all_wake_ups_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_pwrmgr_deep_sleep_all_wake_ups.1950508654
Directory	/workspace/1.chip_sw_pwrmgr_deep_sleep_all_wake_ups/latest

Test location	/workspace/coverage/default/1.chip_sw_pwrmgr_deep_sleep_por_reset.3971983509
Short name	T947
Test name
Test status
Simulation time	7576988358 ps
CPU time	862.5 seconds
Started	Aug 14 05:53:58 PM PDT 24
Finished	Aug 14 06:08:21 PM PDT 24
Peak memory	611592 kb
Host	smart-616be5a3-b394-469a-875d-e6362e8751d3
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_deep_sleep_por_reset_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3971983509 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sleep_por_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage /default.vdb -cm_log /dev/null -cm_name 1.chip_sw_pwrmgr_deep_sleep_por_reset.3971983509
Directory	/workspace/1.chip_sw_pwrmgr_deep_sleep_por_reset/latest

Test location	/workspace/coverage/default/1.chip_sw_pwrmgr_deep_sleep_power_glitch_reset.1320238644
Short name	T686
Test name
Test status
Simulation time	7114338520 ps
CPU time	619.41 seconds
Started	Aug 14 05:52:16 PM PDT 24
Finished	Aug 14 06:02:35 PM PDT 24
Peak memory	618340 kb
Host	smart-4b983dd1-2f4e-430e-83b3-a7019c661392
User	root
Command	/workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=pwrmgr_deep_sleep_power_glitch_test:1:new_rules,test_rom :0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=1320238644 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_deep_power_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_pwrmgr_deep_sleep_power_glitch_reset.1320238644
Directory	/workspace/1.chip_sw_pwrmgr_deep_sleep_power_glitch_reset/latest

Test location	/workspace/coverage/default/1.chip_sw_pwrmgr_full_aon_reset.3945403307
Short name	T125
Test name
Test status
Simulation time	7348040644 ps
CPU time	536.54 seconds
Started	Aug 14 05:51:12 PM PDT 24
Finished	Aug 14 06:00:09 PM PDT 24
Peak memory	610572 kb
Host	smart-ae9b0135-a08a-4774-9ddc-607955983626
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=rstmgr_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3945403307 -assert nopostproc +UVM_TESTNAME=c hip_base_test +UVM_TEST_SEQ=chip_sw_full_aon_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_ log /dev/null -cm_name 1.chip_sw_pwrmgr_full_aon_reset.3945403307
Directory	/workspace/1.chip_sw_pwrmgr_full_aon_reset/latest

Test location	/workspace/coverage/default/1.chip_sw_pwrmgr_main_power_glitch_reset.3559974305
Short name	T733
Test name
Test status
Simulation time	4047122253 ps
CPU time	269.95 seconds
Started	Aug 14 05:48:45 PM PDT 24
Finished	Aug 14 05:53:15 PM PDT 24
Peak memory	617996 kb
Host	smart-fd791a23-0711-4543-800c-0f07eb7cedc5
User	root
Command	/workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=pwrmgr_main_power_glitch_test:1:new_rules,test_rom:0 +cd c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se ed=3559974305 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_main_power_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_pwrmgr_main_power_glitch_reset.3559974305
Directory	/workspace/1.chip_sw_pwrmgr_main_power_glitch_reset/latest

Test location	/workspace/coverage/default/1.chip_sw_pwrmgr_normal_sleep_all_reset_reqs.1580324880
Short name	T374
Test name
Test status
Simulation time	12713745956 ps
CPU time	1736.7 seconds
Started	Aug 14 05:50:43 PM PDT 24
Finished	Aug 14 06:19:40 PM PDT 24
Peak memory	612000 kb
Host	smart-bea69984-f6ff-403a-9c57-352de4e2e48d
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_normal_sleep_all_reset_reqs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1580324880 -assert nop ostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_deep_sleep_all_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_pwrmgr_normal_sleep_all_reset_reqs.1580324880
Directory	/workspace/1.chip_sw_pwrmgr_normal_sleep_all_reset_reqs/latest

Test location	/workspace/coverage/default/1.chip_sw_pwrmgr_normal_sleep_por_reset.4050740371
Short name	T680
Test name
Test status
Simulation time	7407651167 ps
CPU time	770.43 seconds
Started	Aug 14 05:56:16 PM PDT 24
Finished	Aug 14 06:09:07 PM PDT 24
Peak memory	610836 kb
Host	smart-d26c8b2b-ef6e-4265-a9af-bbec994031b1
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_normal_sleep_por_reset_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4050740371 -assert nopostpr oc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sleep_por_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera ge/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_pwrmgr_normal_sleep_por_reset.4050740371
Directory	/workspace/1.chip_sw_pwrmgr_normal_sleep_por_reset/latest

Test location	/workspace/coverage/default/1.chip_sw_pwrmgr_random_sleep_all_reset_reqs.1145237101
Short name	T703
Test name
Test status
Simulation time	19619864392 ps
CPU time	2938.17 seconds
Started	Aug 14 05:51:06 PM PDT 24
Finished	Aug 14 06:40:05 PM PDT 24
Peak memory	612320 kb
Host	smart-9fa8ece8-059b-46f4-a9b3-a703b12d61a9
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=50_000_000 +sw_build_device=sim_dv +sw_images=pwrmgr_random_sleep_all_reset_reqs_test:1:new_rules,test_rom :0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=1145237101 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_deep_sleep_all_reset_vseq +en_cov=1 -cm line+cond+fsm+tg l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_pwrmgr_random_sleep_all_reset_reqs.1145237101
Directory	/workspace/1.chip_sw_pwrmgr_random_sleep_all_reset_reqs/latest

Test location	/workspace/coverage/default/1.chip_sw_pwrmgr_random_sleep_all_wake_ups.3426471728
Short name	T85
Test name
Test status
Simulation time	23136451620 ps
CPU time	1387.08 seconds
Started	Aug 14 05:54:12 PM PDT 24
Finished	Aug 14 06:17:19 PM PDT 24
Peak memory	611384 kb
Host	smart-fe15a703-fe3c-4f0c-b3d7-df286a24c31c
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=18_000_000 +do_random=1 +sw_build_device=sim_dv +sw_images=pwrmgr_random_sleep_all_wake_ups:1:new_rules,te st_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n tb_random_seed=3426471728 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_pwrmgr_deep_sleep_all_wake_ups_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_pwrmgr_random_sleep_all_wake_ups.3426471728
Directory	/workspace/1.chip_sw_pwrmgr_random_sleep_all_wake_ups/latest

Test location	/workspace/coverage/default/1.chip_sw_pwrmgr_random_sleep_power_glitch_reset.103355688
Short name	T969
Test name
Test status
Simulation time	43880686236 ps
CPU time	3229.81 seconds
Started	Aug 14 05:50:19 PM PDT 24
Finished	Aug 14 06:44:09 PM PDT 24
Peak memory	612336 kb
Host	smart-90e5090d-badb-419c-abed-44c7ffc9cf57
User	root
Command	/workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_test_timeout_ns=24_000_000 +sw_build_device=sim_dv +sw_images=pwrmgr_random_sleep_power _glitch_reset_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=103355688 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_random_power_glitc h_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_pwrmgr_random_sl eep_power_glitch_reset.103355688
Directory	/workspace/1.chip_sw_pwrmgr_random_sleep_power_glitch_reset/latest

Test location	/workspace/coverage/default/1.chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up.4052616749
Short name	T391
Test name
Test status
Simulation time	5229855716 ps
CPU time	441.03 seconds
Started	Aug 14 05:54:11 PM PDT 24
Finished	Aug 14 06:01:32 PM PDT 24
Peak memory	611932 kb
Host	smart-51672b7a-e86a-4a6d-9d30-fcdfc4633954
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=18_000_000 +do_random=1 +sw_build_device=sim_dv +sw_images=pwrmgr_sensor_ctrl_deep_sleep_wake_up:1:new_rul es,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t cl +ntb_random_seed=4052616749 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_pwrmgr_sensor_ctrl_deep_s leep_wake_up.4052616749
Directory	/workspace/1.chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up/latest

Test location	/workspace/coverage/default/1.chip_sw_pwrmgr_sleep_disabled.3634318076
Short name	T285
Test name
Test status
Simulation time	3240723548 ps
CPU time	287.85 seconds
Started	Aug 14 05:55:32 PM PDT 24
Finished	Aug 14 06:00:20 PM PDT 24
Peak memory	610548 kb
Host	smart-11246e65-7c98-403f-b68f-3adaf833c69d
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_sleep_disabled_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3634318076 -assert nopostproc +UVM_ TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_ log /dev/null -cm_name 1.chip_sw_pwrmgr_sleep_disabled.3634318076
Directory	/workspace/1.chip_sw_pwrmgr_sleep_disabled/latest

Test location	/workspace/coverage/default/1.chip_sw_pwrmgr_sleep_power_glitch_reset.2843187963
Short name	T566
Test name
Test status
Simulation time	4675782294 ps
CPU time	374.18 seconds
Started	Aug 14 05:51:53 PM PDT 24
Finished	Aug 14 05:58:08 PM PDT 24
Peak memory	616924 kb
Host	smart-d64eb94b-dc96-47e4-9bfa-3da0c0d37ac4
User	root
Command	/workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=pwrmgr_sleep_power_glitch_test:1:new_rules,test_rom:0 +c dc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_s eed=2843187963 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_main_power_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_pwrmgr_sleep_power_glitch_reset.2843187963
Directory	/workspace/1.chip_sw_pwrmgr_sleep_power_glitch_reset/latest

Test location	/workspace/coverage/default/1.chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup.2150440901
Short name	T143
Test name
Test status
Simulation time	4599644680 ps
CPU time	426.18 seconds
Started	Aug 14 05:52:46 PM PDT 24
Finished	Aug 14 05:59:53 PM PDT 24
Peak memory	609392 kb
Host	smart-9362d55b-32a8-4d91-9d77-d5535a937861
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=8_000_000 +sw_build_device=sim_dv +sw_images=sensor_ctrl_wakeup_test:1:new_rules,test_rom:0 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21504409 01 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac e/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup.2150440901
Directory	/workspace/1.chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup/latest

Test location	/workspace/coverage/default/1.chip_sw_pwrmgr_sleep_wake_5_bug.4287356365
Short name	T774
Test name
Test status
Simulation time	6034934888 ps
CPU time	494.08 seconds
Started	Aug 14 05:52:22 PM PDT 24
Finished	Aug 14 06:00:37 PM PDT 24
Peak memory	611168 kb
Host	smart-f03100ab-aee5-4a08-8732-10e3c54ba0ef
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=18_000_000 +do_random=1 +sw_build_device=sim_dv +sw_images=pwrmgr_sleep_wake_5_bug_test:1:new_rules,test_r om:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r andom_seed=4287356365 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_pwrmgr_sleep_wake_5_bug.4287356365
Directory	/workspace/1.chip_sw_pwrmgr_sleep_wake_5_bug/latest

Test location	/workspace/coverage/default/1.chip_sw_pwrmgr_smoketest.2206723234
Short name	T787
Test name
Test status
Simulation time	6570256750 ps
CPU time	531.26 seconds
Started	Aug 14 05:57:56 PM PDT 24
Finished	Aug 14 06:06:47 PM PDT 24
Peak memory	611240 kb
Host	smart-8cf4f434-fec1-474c-96c2-c945361e5d23
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=10000000 +sw_build_device=sim_dv +sw_images=pwrmgr_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2206723234 -asse rt nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera ge/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_pwrmgr_smoketest.2206723234
Directory	/workspace/1.chip_sw_pwrmgr_smoketest/latest

Test location	/workspace/coverage/default/1.chip_sw_pwrmgr_sysrst_ctrl_reset.1395772951
Short name	T954
Test name
Test status
Simulation time	7736484120 ps
CPU time	1188.67 seconds
Started	Aug 14 05:49:55 PM PDT 24
Finished	Aug 14 06:09:44 PM PDT 24
Peak memory	611672 kb
Host	smart-c2818be8-d687-4292-a34b-18240f8ebb32
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_sysrst_ctrl_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1395772951 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sysrst_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_pwrmgr_sysrst_ctrl_reset.1395772951
Directory	/workspace/1.chip_sw_pwrmgr_sysrst_ctrl_reset/latest

Test location	/workspace/coverage/default/1.chip_sw_pwrmgr_usb_clk_disabled_when_active.4029103526
Short name	T178
Test name
Test status
Simulation time	5528372098 ps
CPU time	554.33 seconds
Started	Aug 14 05:51:35 PM PDT 24
Finished	Aug 14 06:00:50 PM PDT 24
Peak memory	611052 kb
Host	smart-f4bd0703-b024-409b-b958-85a0c1645c93
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_usb_clk_disabled_when_active_test:1:new_rules,test_rom:0 +cdc_instrumentation_enable d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4029103526 -assert no postproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de fault.vdb -cm_log /dev/null -cm_name 1.chip_sw_pwrmgr_usb_clk_disabled_when_active.4029103526
Directory	/workspace/1.chip_sw_pwrmgr_usb_clk_disabled_when_active/latest

Test location	/workspace/coverage/default/1.chip_sw_pwrmgr_usbdev_smoketest.1684339560
Short name	T38
Test name
Test status
Simulation time	6262322680 ps
CPU time	474.99 seconds
Started	Aug 14 05:58:03 PM PDT 24
Finished	Aug 14 06:05:58 PM PDT 24
Peak memory	610884 kb
Host	smart-6a19dd58-853d-4d33-81e8-8e729cc309ae
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_usbdev_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1684339560 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_pwrmgr_usbdev_smoketest.1684339560
Directory	/workspace/1.chip_sw_pwrmgr_usbdev_smoketest/latest

Test location	/workspace/coverage/default/1.chip_sw_pwrmgr_wdog_reset.1837492992
Short name	T1010
Test name
Test status
Simulation time	3983685376 ps
CPU time	566.78 seconds
Started	Aug 14 05:54:19 PM PDT 24
Finished	Aug 14 06:03:46 PM PDT 24
Peak memory	610728 kb
Host	smart-96a2a926-63d2-454b-ad34-beab9e41b7f5
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=pwrmgr_wdog_reset_reqs_test:1:new_rules,test_rom:0 +cdc_inst rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=183 7492992 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_pwrmgr_wdog_reset.1837492992
Directory	/workspace/1.chip_sw_pwrmgr_wdog_reset/latest

Test location	/workspace/coverage/default/1.chip_sw_rom_ctrl_integrity_check.4119461805
Short name	T740
Test name
Test status
Simulation time	8396669540 ps
CPU time	702.6 seconds
Started	Aug 14 05:55:12 PM PDT 24
Finished	Aug 14 06:06:55 PM PDT 24
Peak memory	624716 kb
Host	smart-2d44f02e-8865-498a-ac92-8352af253571
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=rom_ctrl_integrity_check_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4119461805 -assert nopostproc +U VM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rom_ctrl_integrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co verage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_rom_ctrl_integrity_check.4119461805
Directory	/workspace/1.chip_sw_rom_ctrl_integrity_check/latest

Test location	/workspace/coverage/default/1.chip_sw_rstmgr_cpu_info.3192806884
Short name	T279
Test name
Test status
Simulation time	6449774880 ps
CPU time	761.86 seconds
Started	Aug 14 05:52:08 PM PDT 24
Finished	Aug 14 06:04:50 PM PDT 24
Peak memory	611320 kb
Host	smart-0449c6cc-6cf1-4761-8c1f-99c219ddd48b
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=rstmgr_cpu_info_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3192806884 -assert nopostproc +UVM_TESTNA ME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 1.chip_sw_rstmgr_cpu_info.3192806884
Directory	/workspace/1.chip_sw_rstmgr_cpu_info/latest

Test location	/workspace/coverage/default/1.chip_sw_rstmgr_rst_cnsty_escalation.1561397918
Short name	T415
Test name
Test status
Simulation time	5374023304 ps
CPU time	723.39 seconds
Started	Aug 14 05:49:28 PM PDT 24
Finished	Aug 14 06:01:32 PM PDT 24
Peak memory	642464 kb
Host	smart-6e16cb64-7662-432c-a77d-f095f39aa61a
User	root
Command	/workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 1561397918 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rstmgr_cnsty_fault_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_rstmgr_rst_cnsty_escalation.1561397918
Directory	/workspace/1.chip_sw_rstmgr_rst_cnsty_escalation/latest

Test location	/workspace/coverage/default/1.chip_sw_rstmgr_smoketest.3182290659
Short name	T971
Test name
Test status
Simulation time	2794261306 ps
CPU time	169.29 seconds
Started	Aug 14 05:54:19 PM PDT 24
Finished	Aug 14 05:57:09 PM PDT 24
Peak memory	610456 kb
Host	smart-eccf8e6b-273a-4a62-996b-7c8d605751f0
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=rstmgr_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3182290659 -assert nopostproc +UVM_TESTNAME=c hip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n ull -cm_name 1.chip_sw_rstmgr_smoketest.3182290659
Directory	/workspace/1.chip_sw_rstmgr_smoketest/latest

Test location	/workspace/coverage/default/1.chip_sw_rstmgr_sw_req.3026768145
Short name	T635
Test name
Test status
Simulation time	4948798072 ps
CPU time	508.76 seconds
Started	Aug 14 05:53:03 PM PDT 24
Finished	Aug 14 06:01:32 PM PDT 24
Peak memory	610352 kb
Host	smart-1449c9dd-439e-4b94-8ffc-cf34c4281f58
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=rstmgr_sw_req_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3026768145 -assert nopostproc +UVM_TESTNAME =chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 1.chip_sw_rstmgr_sw_req.3026768145
Directory	/workspace/1.chip_sw_rstmgr_sw_req/latest

Test location	/workspace/coverage/default/1.chip_sw_rstmgr_sw_rst.3497970786
Short name	T879
Test name
Test status
Simulation time	2757754312 ps
CPU time	200 seconds
Started	Aug 14 05:48:26 PM PDT 24
Finished	Aug 14 05:51:47 PM PDT 24
Peak memory	610468 kb
Host	smart-fc8a5d85-81de-4dd0-8f25-facbb78f6ce2
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=rstmgr_sw_rst_ctrl_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3497970786 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_rstmgr_sw_rst.3497970786
Directory	/workspace/1.chip_sw_rstmgr_sw_rst/latest

Test location	/workspace/coverage/default/1.chip_sw_rv_core_ibex_icache_invalidate.1270390544
Short name	T221
Test name
Test status
Simulation time	3533024572 ps
CPU time	220.19 seconds
Started	Aug 14 05:52:31 PM PDT 24
Finished	Aug 14 05:56:11 PM PDT 24
Peak memory	610800 kb
Host	smart-72fd3363-8da8-478d-a1a7-ea7e4b56e47b
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=rv_core_ibex_icache_invalidate_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1270390544 -assert nopostp roc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rv_core_ibex_icache_invalidate_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_rv_core_ibex_icache_invalidate.1270390544
Directory	/workspace/1.chip_sw_rv_core_ibex_icache_invalidate/latest

Test location	/workspace/coverage/default/1.chip_sw_rv_core_ibex_lockstep_glitch.2800685560
Short name	T998
Test name
Test status
Simulation time	2728042748 ps
CPU time	275.33 seconds
Started	Aug 14 05:56:41 PM PDT 24
Finished	Aug 14 06:01:17 PM PDT 24
Peak memory	617344 kb
Host	smart-452d68a6-b5f6-4867-87a1-b9a20ac6723a
User	root
Command	/workspace/default/simv +disable_assert_final_checks +sw_build_device=sim_dv +sw_images=aes_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2800685560 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rv_core_ibex_lockstep_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_rv_core_ibex_lockstep_glitch.2800685560
Directory	/workspace/1.chip_sw_rv_core_ibex_lockstep_glitch/latest

Test location	/workspace/coverage/default/1.chip_sw_rv_core_ibex_nmi_irq.2436918818
Short name	T432
Test name
Test status
Simulation time	4584574736 ps
CPU time	901.72 seconds
Started	Aug 14 05:50:57 PM PDT 24
Finished	Aug 14 06:05:59 PM PDT 24
Peak memory	610932 kb
Host	smart-487b4ba2-4ff4-4b91-a0da-d52fcdf264c9
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=10_000_000 +sw_build_device=sim_dv +sw_images=rv_core_ibex_nmi_irq_test:1:new_rules,test_rom:0 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24369 18818 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_rv_core_ibex_nmi_irq.2436918818
Directory	/workspace/1.chip_sw_rv_core_ibex_nmi_irq/latest

Test location	/workspace/coverage/default/1.chip_sw_rv_core_ibex_rnd.1874707658
Short name	T808
Test name
Test status
Simulation time	5491862760 ps
CPU time	1125.58 seconds
Started	Aug 14 05:54:26 PM PDT 24
Finished	Aug 14 06:13:13 PM PDT 24
Peak memory	610800 kb
Host	smart-7e933f6b-debf-4d17-889e-ba667a5ac7dd
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=20_000_000 +rng_srate_value_max=32 +sw_build_device=sim_dv +sw_images=rv_core_ibex_rnd_test:1:new_rules,te st_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n tb_random_seed=1874707658 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_rv_core_ibex_rnd.1874707658
Directory	/workspace/1.chip_sw_rv_core_ibex_rnd/latest

Test location	/workspace/coverage/default/1.chip_sw_rv_dm_access_after_escalation_reset.4238937363
Short name	T261
Test name
Test status
Simulation time	5226015724 ps
CPU time	618.99 seconds
Started	Aug 14 05:53:57 PM PDT 24
Finished	Aug 14 06:04:16 PM PDT 24
Peak memory	625228 kb
Host	smart-888a2ec7-186c-4c19-b55f-914295c347a7
User	root
Command	/workspace/default/simv +use_jtag_dmi=1 +sw_build_device=sim_dv +sw_images=alert_handler_escalation_test:1:new_rules,test_rom:0 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4238937363 -asse rt nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rv_dm_access_after_escalation_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_rv_dm_access_after_escalation_reset.4238937363
Directory	/workspace/1.chip_sw_rv_dm_access_after_escalation_reset/latest

Test location	/workspace/coverage/default/1.chip_sw_rv_dm_access_after_wakeup.3347157429
Short name	T11
Test name
Test status
Simulation time	5158148040 ps
CPU time	416.91 seconds
Started	Aug 14 05:55:29 PM PDT 24
Finished	Aug 14 06:02:27 PM PDT 24
Peak memory	620028 kb
Host	smart-58c6295f-7019-45f8-9451-c6dc2fafe149
User	root
Command	/workspace/default/simv +use_jtag_dmi=1 +sw_build_device=sim_dv +sw_images=rv_dm_access_after_wakeup_rma:1:new_rules,test_rom:0 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3347157429 -asse rt nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rv_dm_access_after_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_rv_dm_access_after_wakeup.3347157429
Directory	/workspace/1.chip_sw_rv_dm_access_after_wakeup/latest

Test location	/workspace/coverage/default/1.chip_sw_rv_dm_ndm_reset_req_when_cpu_halted.2227585424
Short name	T16
Test name
Test status
Simulation time	3843034656 ps
CPU time	508.7 seconds
Started	Aug 14 05:53:56 PM PDT 24
Finished	Aug 14 06:02:25 PM PDT 24
Peak memory	620516 kb
Host	smart-b9d2f724-c6e0-4e09-855c-95bace475d79
User	root
Command	/workspace/default/simv +use_jtag_dmi=1 +sw_build_device=sim_dv +sw_images=rv_dm_ndm_reset_req_when_cpu_halted_rma:1:new_rules,test_rom:0 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=222758 5424 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rv_dm_ndm_reset_when_cpu_halted_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_rv_dm_ndm_reset_req_when_cpu_halted.2227585424
Directory	/workspace/1.chip_sw_rv_dm_ndm_reset_req_when_cpu_halted/latest

Test location	/workspace/coverage/default/1.chip_sw_rv_plic_smoketest.3315377686
Short name	T344
Test name
Test status
Simulation time	2664311880 ps
CPU time	170.41 seconds
Started	Aug 14 05:55:51 PM PDT 24
Finished	Aug 14 05:58:42 PM PDT 24
Peak memory	610356 kb
Host	smart-c445c32e-e948-403b-a16b-00bb5e984efb
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=rv_plic_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3315377686 -assert nopostproc +UVM_TESTNAME= chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/ null -cm_name 1.chip_sw_rv_plic_smoketest.3315377686
Directory	/workspace/1.chip_sw_rv_plic_smoketest/latest

Test location	/workspace/coverage/default/1.chip_sw_rv_timer_irq.2942960191
Short name	T273
Test name
Test status
Simulation time	2837609338 ps
CPU time	250.64 seconds
Started	Aug 14 05:54:05 PM PDT 24
Finished	Aug 14 05:58:16 PM PDT 24
Peak memory	610380 kb
Host	smart-d4d6f143-dd37-4a50-a3fc-87e48e065af3
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=rv_timer_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2942960191 -assert nopostproc +UVM_TESTNAME =chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 1.chip_sw_rv_timer_irq.2942960191
Directory	/workspace/1.chip_sw_rv_timer_irq/latest

Test location	/workspace/coverage/default/1.chip_sw_rv_timer_smoketest.1079711451
Short name	T272
Test name
Test status
Simulation time	3199398390 ps
CPU time	338.76 seconds
Started	Aug 14 05:57:19 PM PDT 24
Finished	Aug 14 06:02:58 PM PDT 24
Peak memory	610360 kb
Host	smart-99760156-b269-4a5c-ab18-deb7f9d41d66
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=rv_timer_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1079711451 -assert nopostproc +UVM_TESTNAME =chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 1.chip_sw_rv_timer_smoketest.1079711451
Directory	/workspace/1.chip_sw_rv_timer_smoketest/latest

Test location	/workspace/coverage/default/1.chip_sw_sensor_ctrl_status.3297799181
Short name	T124
Test name
Test status
Simulation time	3298190973 ps
CPU time	260.6 seconds
Started	Aug 14 05:51:54 PM PDT 24
Finished	Aug 14 05:56:15 PM PDT 24
Peak memory	611504 kb
Host	smart-8437aad1-069b-400c-837e-bc9f06069afc
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=40_000_000 +sw_build_device=sim_dv +sw_images=sensor_ctrl_status_test:1:new_rules,test_rom:0 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3297799 181 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sensor_ctrl_status_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_sensor_ctrl_status.3297799181
Directory	/workspace/1.chip_sw_sensor_ctrl_status/latest

Test location	/workspace/coverage/default/1.chip_sw_sleep_pin_retention.2612612553
Short name	T46
Test name
Test status
Simulation time	4142341642 ps
CPU time	414.42 seconds
Started	Aug 14 05:52:10 PM PDT 24
Finished	Aug 14 05:59:05 PM PDT 24
Peak memory	610424 kb
Host	smart-14642327-9518-426e-b6d2-d822b3d25d62
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=sleep_pin_retention_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2612612553 -assert nopostproc +UVM_TE STNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sleep_pin_retention_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def ault.vdb -cm_log /dev/null -cm_name 1.chip_sw_sleep_pin_retention.2612612553
Directory	/workspace/1.chip_sw_sleep_pin_retention/latest

Test location	/workspace/coverage/default/1.chip_sw_sleep_pwm_pulses.1991199721
Short name	T127
Test name
Test status
Simulation time	7855386970 ps
CPU time	1132.49 seconds
Started	Aug 14 05:51:41 PM PDT 24
Finished	Aug 14 06:10:34 PM PDT 24
Peak memory	611608 kb
Host	smart-a095559c-0afb-4fd3-b4e2-b13d7049eed2
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=sleep_pwm_pulses_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1991199721 -assert nopostproc +UVM_TESTN AME=chip_base_test +UVM_TEST_SEQ=chip_sw_pwm_pulses_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm _log /dev/null -cm_name 1.chip_sw_sleep_pwm_pulses.1991199721
Directory	/workspace/1.chip_sw_sleep_pwm_pulses/latest

Test location	/workspace/coverage/default/1.chip_sw_sleep_sram_ret_contents_no_scramble.3751662143
Short name	T441
Test name
Test status
Simulation time	8671566446 ps
CPU time	555.36 seconds
Started	Aug 14 05:54:40 PM PDT 24
Finished	Aug 14 06:03:56 PM PDT 24
Peak memory	611408 kb
Host	smart-b58ee9e6-a4e2-4218-b138-18c155fc1d4f
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=20_000_000 +en_scb_tl_err_chk=0 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=sram _ctrl_sleep_sram_ret_contents_no_scramble_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3751662143 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_S EQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_sl eep_sram_ret_contents_no_scramble.3751662143
Directory	/workspace/1.chip_sw_sleep_sram_ret_contents_no_scramble/latest

Test location	/workspace/coverage/default/1.chip_sw_sleep_sram_ret_contents_scramble.1040341924
Short name	T762
Test name
Test status
Simulation time	7649033690 ps
CPU time	660.57 seconds
Started	Aug 14 05:53:53 PM PDT 24
Finished	Aug 14 06:04:54 PM PDT 24
Peak memory	611064 kb
Host	smart-eff28202-eb53-4b07-8609-d8d81c98f154
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=20_000_000 +en_scb_tl_err_chk=0 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=sram _ctrl_sleep_sram_ret_contents_scramble_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1040341924 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ= chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_sleep _sram_ret_contents_scramble.1040341924
Directory	/workspace/1.chip_sw_sleep_sram_ret_contents_scramble/latest

Test location	/workspace/coverage/default/1.chip_sw_spi_device_pass_through.3127640298
Short name	T61
Test name
Test status
Simulation time	5550413601 ps
CPU time	701.56 seconds
Started	Aug 14 05:54:42 PM PDT 24
Finished	Aug 14 06:06:24 PM PDT 24
Peak memory	625272 kb
Host	smart-562e1932-9694-4d4f-837f-db5723f400e0
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=spi_passthrough_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3127640298 -assert nopostproc +UVM_TESTNA ME=chip_base_test +UVM_TEST_SEQ=chip_sw_spi_passthrough_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_spi_device_pass_through.3127640298
Directory	/workspace/1.chip_sw_spi_device_pass_through/latest

Test location	/workspace/coverage/default/1.chip_sw_spi_device_pass_through_collision.1565968800
Short name	T33
Test name
Test status
Simulation time	4452801790 ps
CPU time	544.31 seconds
Started	Aug 14 05:50:50 PM PDT 24
Finished	Aug 14 05:59:56 PM PDT 24
Peak memory	625364 kb
Host	smart-05cdf7a3-5208-486e-86ae-a430edb78fe2
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=spi_passthrough_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1565968800 -assert nopostproc +UVM_TESTNA ME=chip_base_test +UVM_TEST_SEQ=chip_sw_spi_passthrough_collision_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/d efault.vdb -cm_log /dev/null -cm_name 1.chip_sw_spi_device_pass_through_collision.1565968800
Directory	/workspace/1.chip_sw_spi_device_pass_through_collision/latest

Test location	/workspace/coverage/default/1.chip_sw_spi_device_tpm.117993546
Short name	T58
Test name
Test status
Simulation time	3700442271 ps
CPU time	328.54 seconds
Started	Aug 14 05:51:41 PM PDT 24
Finished	Aug 14 05:57:11 PM PDT 24
Peak memory	619920 kb
Host	smart-0f00e0f9-6dcb-4cd0-8d6e-4a2760900786
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=spi_device_tpm_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=117993546 -assert nopostproc +UVM_TE STNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_spi_device_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 1.chip_sw_spi_device_tpm.117993546
Directory	/workspace/1.chip_sw_spi_device_tpm/latest

Test location	/workspace/coverage/default/1.chip_sw_sram_ctrl_execution_main.3842032522
Short name	T196
Test name
Test status
Simulation time	8880396001 ps
CPU time	1199.23 seconds
Started	Aug 14 05:51:26 PM PDT 24
Finished	Aug 14 06:11:25 PM PDT 24
Peak memory	611172 kb
Host	smart-0abfa91e-cada-4192-95c7-4676ea5b1cf7
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=sram_ctrl_execution_main_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3842032522 -assert nopostproc +U VM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sram_ctrl_execution_main_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co verage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_sram_ctrl_execution_main.3842032522
Directory	/workspace/1.chip_sw_sram_ctrl_execution_main/latest

Test location	/workspace/coverage/default/1.chip_sw_sram_ctrl_scrambled_access.3025246182
Short name	T293
Test name
Test status
Simulation time	4227988400 ps
CPU time	618.76 seconds
Started	Aug 14 05:56:43 PM PDT 24
Finished	Aug 14 06:07:02 PM PDT 24
Peak memory	611396 kb
Host	smart-bb8d5da8-ac73-48e2-99c8-7063f4585c4f
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=12_000_000 +en_scb_tl_err_chk=0 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=sram _ctrl_scrambled_access_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3025246182 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sram_ctr l_scrambled_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw _sram_ctrl_scrambled_access.3025246182
Directory	/workspace/1.chip_sw_sram_ctrl_scrambled_access/latest

Test location	/workspace/coverage/default/1.chip_sw_sram_ctrl_scrambled_access_jitter_en.3409374917
Short name	T1022
Test name
Test status
Simulation time	3950651311 ps
CPU time	541.39 seconds
Started	Aug 14 05:57:20 PM PDT 24
Finished	Aug 14 06:06:22 PM PDT 24
Peak memory	611420 kb
Host	smart-d4d53b6e-0c50-4d28-882a-226962a4faa3
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=12_000_000 +bypass_alert_ready_to_end_check=1 +en_jitter=1 +en_scb_tl_err_chk=0 +sw_build_device=sim_dv +s w_images=sram_ctrl_scrambled_access_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3409374917 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chi p_sw_sram_ctrl_scrambled_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n ame 1.chip_sw_sram_ctrl_scrambled_access_jitter_en.3409374917
Directory	/workspace/1.chip_sw_sram_ctrl_scrambled_access_jitter_en/latest

Test location	/workspace/coverage/default/1.chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq.750554258
Short name	T129
Test name
Test status
Simulation time	3865277442 ps
CPU time	498.28 seconds
Started	Aug 14 05:55:59 PM PDT 24
Finished	Aug 14 06:04:18 PM PDT 24
Peak memory	611052 kb
Host	smart-b27119ab-4614-4dd8-8281-f5cae528f003
User	root
Command	/workspace/default/simv +mem_sel=main +sw_test_timeout_ns=12_000_000 +bypass_alert_ready_to_end_check=1 +en_jitter=1 +en_scb_tl_err_chk=0 +cal_sys_clk _70mhz=1 +sw_build_device=sim_dv +sw_images=sram_ctrl_scrambled_access_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=750554258 -assert nopostproc +UVM_TESTNAM E=chip_base_test +UVM_TEST_SEQ=chip_sw_sram_ctrl_scrambled_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/d efault.vdb -cm_log /dev/null -cm_name 1.chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq.750554258
Directory	/workspace/1.chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq/latest

Test location	/workspace/coverage/default/1.chip_sw_sram_ctrl_smoketest.1347915626
Short name	T855
Test name
Test status
Simulation time	2974758390 ps
CPU time	237.49 seconds
Started	Aug 14 05:55:18 PM PDT 24
Finished	Aug 14 05:59:16 PM PDT 24
Peak memory	609900 kb
Host	smart-a0988848-58b8-4ce9-9ecd-1f84e0c8d640
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=sram_ctrl_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1347915626 -assert nopostproc +UVM_TESTNAM E=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 1.chip_sw_sram_ctrl_smoketest.1347915626
Directory	/workspace/1.chip_sw_sram_ctrl_smoketest/latest

Test location	/workspace/coverage/default/1.chip_sw_sysrst_ctrl_ec_rst_l.2723175052
Short name	T43
Test name
Test status
Simulation time	21182450795 ps
CPU time	3376.84 seconds
Started	Aug 14 05:51:43 PM PDT 24
Finished	Aug 14 06:48:01 PM PDT 24
Peak memory	611572 kb
Host	smart-23b4400c-116a-4ff3-8753-7a08daec8fd9
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=sysrst_ctrl_ec_rst_l_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2723175052 -assert nopostproc +UVM_T ESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sysrst_ctrl_ec_rst_l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/d efault.vdb -cm_log /dev/null -cm_name 1.chip_sw_sysrst_ctrl_ec_rst_l.2723175052
Directory	/workspace/1.chip_sw_sysrst_ctrl_ec_rst_l/latest

Test location	/workspace/coverage/default/1.chip_sw_sysrst_ctrl_in_irq.1027792932
Short name	T254
Test name
Test status
Simulation time	4208733606 ps
CPU time	562.05 seconds
Started	Aug 14 05:53:02 PM PDT 24
Finished	Aug 14 06:02:28 PM PDT 24
Peak memory	613936 kb
Host	smart-10f79d3f-4cd4-43b5-9e0b-9c4267635732
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=sysrst_ctrl_in_irq_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1027792932 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sysrst_ctrl_in_irq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau lt.vdb -cm_log /dev/null -cm_name 1.chip_sw_sysrst_ctrl_in_irq.1027792932
Directory	/workspace/1.chip_sw_sysrst_ctrl_in_irq/latest

Test location	/workspace/coverage/default/1.chip_sw_sysrst_ctrl_inputs.3361712092
Short name	T253
Test name
Test status
Simulation time	3155635635 ps
CPU time	456.87 seconds
Started	Aug 14 05:55:24 PM PDT 24
Finished	Aug 14 06:03:03 PM PDT 24
Peak memory	614100 kb
Host	smart-7ca1abc0-fd8b-462c-bdf8-77e7f5e3ac34
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=sysrst_ctrl_inputs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3361712092 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sysrst_ctrl_inputs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau lt.vdb -cm_log /dev/null -cm_name 1.chip_sw_sysrst_ctrl_inputs.3361712092
Directory	/workspace/1.chip_sw_sysrst_ctrl_inputs/latest

Test location	/workspace/coverage/default/1.chip_sw_sysrst_ctrl_outputs.1758088791
Short name	T255
Test name
Test status
Simulation time	4071571179 ps
CPU time	300.95 seconds
Started	Aug 14 05:50:37 PM PDT 24
Finished	Aug 14 05:55:39 PM PDT 24
Peak memory	610832 kb
Host	smart-857416b4-cfc2-4bd8-90ed-d184b2048834
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=sysrst_ctrl_outputs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1758088791 -assert nopostproc +UVM_TE STNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sysrst_ctrl_outputs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def ault.vdb -cm_log /dev/null -cm_name 1.chip_sw_sysrst_ctrl_outputs.1758088791
Directory	/workspace/1.chip_sw_sysrst_ctrl_outputs/latest

Test location	/workspace/coverage/default/1.chip_sw_sysrst_ctrl_ulp_z3_wakeup.567172694
Short name	T57
Test name
Test status
Simulation time	5373378922 ps
CPU time	419.51 seconds
Started	Aug 14 05:52:02 PM PDT 24
Finished	Aug 14 05:59:02 PM PDT 24
Peak memory	610028 kb
Host	smart-e20f8350-3427-4f5e-b3ce-5b6a1313d583
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=sysrst_ctrl_ulp_z3_wakeup_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=567172694 -assert nopostproc +U VM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sysrst_ctrl_ulp_z3_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/c overage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_sysrst_ctrl_ulp_z3_wakeup.567172694
Directory	/workspace/1.chip_sw_sysrst_ctrl_ulp_z3_wakeup/latest

Test location	/workspace/coverage/default/1.chip_sw_uart_rand_baudrate.1280219704
Short name	T908
Test name
Test status
Simulation time	4495966234 ps
CPU time	740.85 seconds
Started	Aug 14 05:49:13 PM PDT 24
Finished	Aug 14 06:01:35 PM PDT 24
Peak memory	620168 kb
Host	smart-30f0888c-b7dd-41f1-89ff-085a9d1677a4
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random _seed=1280219704 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_uart_rand_baudrate.1280219704
Directory	/workspace/1.chip_sw_uart_rand_baudrate/latest

Test location	/workspace/coverage/default/1.chip_sw_uart_smoketest.957193756
Short name	T679
Test name
Test status
Simulation time	2582888920 ps
CPU time	288.1 seconds
Started	Aug 14 05:54:53 PM PDT 24
Finished	Aug 14 05:59:41 PM PDT 24
Peak memory	612724 kb
Host	smart-ecd63cd8-5071-4785-a4c3-1f32d1cad12c
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=uart_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=957193756 -assert nopostproc +UVM_TESTNAME=chip _base_test +UVM_TEST_SEQ=chip_sw_uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 1.chip_sw_uart_smoketest.957193756
Directory	/workspace/1.chip_sw_uart_smoketest/latest

Test location	/workspace/coverage/default/1.chip_sw_uart_tx_rx_alt_clk_freq.668812153
Short name	T778
Test name
Test status
Simulation time	9333642177 ps
CPU time	1976.23 seconds
Started	Aug 14 05:50:04 PM PDT 24
Finished	Aug 14 06:23:01 PM PDT 24
Peak memory	625060 kb
Host	smart-d0df0d87-bae8-47da-980a-ef96cc1e04db
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=80_000_000 +chip_clock_source=ChipClockSourceExternal96Mhz +calibrate_usb_clk=1 +sw_build_device=sim_dv +s w_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=668812153 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_ba udrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_uart_tx_rx_ alt_clk_freq.668812153
Directory	/workspace/1.chip_sw_uart_tx_rx_alt_clk_freq/latest

Test location	/workspace/coverage/default/1.chip_sw_uart_tx_rx_alt_clk_freq_low_speed.679452224
Short name	T880
Test name
Test status
Simulation time	8777437725 ps
CPU time	1157.23 seconds
Started	Aug 14 05:54:17 PM PDT 24
Finished	Aug 14 06:13:35 PM PDT 24
Peak memory	624768 kb
Host	smart-ca103589-ded9-4bd2-99c0-80d3654179c7
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +chip_clock_source=ChipClockSourceExternal48Mhz +sw_build_device=sim_dv +s w_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=679452224 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_ba udrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_uart_tx_rx_ alt_clk_freq_low_speed.679452224
Directory	/workspace/1.chip_sw_uart_tx_rx_alt_clk_freq_low_speed/latest

Test location	/workspace/coverage/default/1.chip_sw_uart_tx_rx_bootstrap.237756794
Short name	T739
Test name
Test status
Simulation time	78466594732 ps
CPU time	13672.6 seconds
Started	Aug 14 05:49:44 PM PDT 24
Finished	Aug 14 09:37:39 PM PDT 24
Peak memory	636620 kb
Host	smart-e6e6fd08-43f2-49a5-b11a-7d31d81c68a1
User	root
Command	/workspace/default/simv +use_spi_load_bootstrap=1 +calibrate_usb_clk=1 +test_timeout_ns=160_000_000 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test :1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=237756794 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_uart_tx_rx_bootstrap.237756794
Directory	/workspace/1.chip_sw_uart_tx_rx_bootstrap/latest

Test location	/workspace/coverage/default/1.chip_sw_uart_tx_rx_idx1.2989231560
Short name	T1009
Test name
Test status
Simulation time	4207143800 ps
CPU time	650.6 seconds
Started	Aug 14 05:53:44 PM PDT 24
Finished	Aug 14 06:04:35 PM PDT 24
Peak memory	620428 kb
Host	smart-1ed14372-3df8-4bb3-b95e-f01840b43b27
User	root
Command	/workspace/default/simv +uart_idx=1 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2989231560 -a ssert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ce/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_uart_tx_rx_idx1.2989231560
Directory	/workspace/1.chip_sw_uart_tx_rx_idx1/latest

Test location	/workspace/coverage/default/1.chip_sw_uart_tx_rx_idx2.3096714175
Short name	T664
Test name
Test status
Simulation time	4310651608 ps
CPU time	610.31 seconds
Started	Aug 14 05:54:20 PM PDT 24
Finished	Aug 14 06:04:31 PM PDT 24
Peak memory	620744 kb
Host	smart-ab293275-54db-433a-b582-887363c856cf
User	root
Command	/workspace/default/simv +uart_idx=2 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3096714175 -a ssert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ce/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_uart_tx_rx_idx2.3096714175
Directory	/workspace/1.chip_sw_uart_tx_rx_idx2/latest

Test location	/workspace/coverage/default/1.chip_sw_uart_tx_rx_idx3.4175503932
Short name	T701
Test name
Test status
Simulation time	4754394592 ps
CPU time	645.76 seconds
Started	Aug 14 05:52:46 PM PDT 24
Finished	Aug 14 06:03:32 PM PDT 24
Peak memory	620828 kb
Host	smart-d9450b0c-25b8-4883-849d-a66f38a49b74
User	root
Command	/workspace/default/simv +uart_idx=3 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4175503932 -a ssert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ce/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_uart_tx_rx_idx3.4175503932
Directory	/workspace/1.chip_sw_uart_tx_rx_idx3/latest

Test location	/workspace/coverage/default/1.chip_tap_straps_dev.716464500
Short name	T74
Test name
Test status
Simulation time	2508745566 ps
CPU time	147.94 seconds
Started	Aug 14 05:57:15 PM PDT 24
Finished	Aug 14 05:59:43 PM PDT 24
Peak memory	624856 kb
Host	smart-cc657874-858e-4206-a96c-8e02bccb5031
User	root
Command	/workspace/default/simv +use_otp_image=OtpTypeLcStDev +create_jtag_riscv_map=1 +sw_build_device=sim_dv +sw_images=example_test_from_rom:0:test_in_rom: new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=716464500 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_tap_straps_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_tap_straps_dev.716464500
Directory	/workspace/1.chip_tap_straps_dev/latest

Test location	/workspace/coverage/default/1.chip_tap_straps_prod.819073765
Short name	T777
Test name
Test status
Simulation time	8773876754 ps
CPU time	955.6 seconds
Started	Aug 14 05:54:11 PM PDT 24
Finished	Aug 14 06:10:07 PM PDT 24
Peak memory	625600 kb
Host	smart-28b3d670-7418-43a9-8ced-022379025a7e
User	root
Command	/workspace/default/simv +use_otp_image=OtpTypeLcStProd +create_jtag_riscv_map=1 +sw_build_device=sim_dv +sw_images=example_test_from_rom:0:test_in_rom :new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=819073765 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_tap_straps_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_tap_straps_prod.819073765
Directory	/workspace/1.chip_tap_straps_prod/latest

Test location	/workspace/coverage/default/1.chip_tap_straps_rma.3875453113
Short name	T619
Test name
Test status
Simulation time	8561279259 ps
CPU time	908.18 seconds
Started	Aug 14 05:52:42 PM PDT 24
Finished	Aug 14 06:07:50 PM PDT 24
Peak memory	625616 kb
Host	smart-d2449bba-714c-4d4f-a77c-a21b042c2901
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +sw_build_device=sim_dv +sw_images=example_test_from_rom:0:test_in_rom:new_rules +cdc_instrumentation _enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3875453113 -as sert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_tap_straps_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/c overage/default.vdb -cm_log /dev/null -cm_name 1.chip_tap_straps_rma.3875453113
Directory	/workspace/1.chip_tap_straps_rma/latest

Test location	/workspace/coverage/default/1.rom_e2e_asm_init_dev.1245508339
Short name	T387
Test name
Test status
Simulation time	15294884101 ps
CPU time	3275.06 seconds
Started	Aug 14 05:56:45 PM PDT 24
Finished	Aug 14 06:51:20 PM PDT 24
Peak memory	610880 kb
Host	smart-6b9870b6-fad8-4460-8b9f-494d6cb2cd47
User	root
Command	/workspace/default/simv +use_otp_image=OtpTypeCustom +sw_test_timeout_ns=20000000 +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_prod _key_0:1:ot_flash_binary,otp_img_e2e_bootstrap_entry_dev:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1245508339 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_S EQ=chip_sw_rom_e2e_asm_init_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_e2e_asm_init_dev.1245508339
Directory	/workspace/1.rom_e2e_asm_init_dev/latest

Test location	/workspace/coverage/default/1.rom_e2e_asm_init_prod.3340994521
Short name	T605
Test name
Test status
Simulation time	15295026386 ps
CPU time	3842.53 seconds
Started	Aug 14 05:56:52 PM PDT 24
Finished	Aug 14 07:00:55 PM PDT 24
Peak memory	610688 kb
Host	smart-06ddb24d-60fc-4c56-abd9-afd130c6c851
User	root
Command	/workspace/default/simv +use_otp_image=OtpTypeCustom +sw_test_timeout_ns=20000000 +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_prod _key_0:1:ot_flash_binary,otp_img_e2e_bootstrap_entry_prod:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3340994521 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_ SEQ=chip_sw_rom_e2e_asm_init_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_e2e_asm_init_prod.3340994521
Directory	/workspace/1.rom_e2e_asm_init_prod/latest

Test location	/workspace/coverage/default/1.rom_e2e_asm_init_prod_end.155995754
Short name	T786
Test name
Test status
Simulation time	15410961929 ps
CPU time	3872.56 seconds
Started	Aug 14 05:58:01 PM PDT 24
Finished	Aug 14 07:02:35 PM PDT 24
Peak memory	610936 kb
Host	smart-5619f485-0162-43e4-9fe4-ae84edd0879b
User	root
Command	/workspace/default/simv +use_otp_image=OtpTypeCustom +sw_test_timeout_ns=20000000 +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_prod _key_0:1:ot_flash_binary,otp_img_e2e_bootstrap_entry_prod_end:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=155995754 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TE ST_SEQ=chip_sw_rom_e2e_asm_init_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n ame 1.rom_e2e_asm_init_prod_end.155995754
Directory	/workspace/1.rom_e2e_asm_init_prod_end/latest

Test location	/workspace/coverage/default/1.rom_e2e_asm_init_rma.3132522652
Short name	T661
Test name
Test status
Simulation time	15047125448 ps
CPU time	3473.69 seconds
Started	Aug 14 05:57:15 PM PDT 24
Finished	Aug 14 06:55:09 PM PDT 24
Peak memory	610968 kb
Host	smart-08f87ef6-e70f-409d-a458-daa90c44bda4
User	root
Command	/workspace/default/simv +use_otp_image=OtpTypeCustom +sw_test_timeout_ns=20000000 +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_prod _key_0:1:ot_flash_binary,otp_img_e2e_bootstrap_entry_rma:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3132522652 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_S EQ=chip_sw_rom_e2e_asm_init_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_e2e_asm_init_rma.3132522652
Directory	/workspace/1.rom_e2e_asm_init_rma/latest

Test location	/workspace/coverage/default/1.rom_e2e_asm_init_test_unlocked0.3888127830
Short name	T782
Test name
Test status
Simulation time	11964166908 ps
CPU time	2835.61 seconds
Started	Aug 14 05:59:25 PM PDT 24
Finished	Aug 14 06:46:41 PM PDT 24
Peak memory	610092 kb
Host	smart-68b5d928-7f1a-4a3d-9ddf-86ca678a2d9d
User	root
Command	/workspace/default/simv +use_otp_image=OtpTypeCustom +sw_test_timeout_ns=410_000_000 +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_p rod_key_0:1:ot_flash_binary,otp_img_e2e_bootstrap_entry_test_unlocked0:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY =UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3888127830 -assert nopostproc +UVM_TESTNAME=chip_base_te st +UVM_TEST_SEQ=chip_sw_rom_e2e_asm_init_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/ null -cm_name 1.rom_e2e_asm_init_test_unlocked0.3888127830
Directory	/workspace/1.rom_e2e_asm_init_test_unlocked0/latest

Test location	/workspace/coverage/default/1.rom_e2e_keymgr_init_rom_ext_invalid_meas.3980866757
Short name	T68
Test name
Test status
Simulation time	15715321144 ps
CPU time	3834.74 seconds
Started	Aug 14 06:02:06 PM PDT 24
Finished	Aug 14 07:06:02 PM PDT 24
Peak memory	610568 kb
Host	smart-91c0b00e-d591-4ac2-b225-0088ad7e7ebb
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=40_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=rom_e2e_keymgr_init_otp_invalid _meas:1:new_rules,otp_img_keymgr_otp_invalid_meas:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3980866757 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip _sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_e2e_keymgr_in it_rom_ext_invalid_meas.3980866757
Directory	/workspace/1.rom_e2e_keymgr_init_rom_ext_invalid_meas/latest

Test location	/workspace/coverage/default/1.rom_e2e_keymgr_init_rom_ext_meas.580877906
Short name	T642
Test name
Test status
Simulation time	14912447170 ps
CPU time	3754.44 seconds
Started	Aug 14 05:59:07 PM PDT 24
Finished	Aug 14 07:01:42 PM PDT 24
Peak memory	610032 kb
Host	smart-f565c66a-d015-426d-84f9-58978783afba
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=40_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=rom_e2e_keymgr_init_otp_meas:1: new_rules,otp_img_keymgr_otp_meas:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=580877906 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_e2e_keymgr_init_rom_ext_meas.580877906
Directory	/workspace/1.rom_e2e_keymgr_init_rom_ext_meas/latest

Test location	/workspace/coverage/default/1.rom_e2e_keymgr_init_rom_ext_no_meas.787463827
Short name	T602
Test name
Test status
Simulation time	14756697564 ps
CPU time	4960.79 seconds
Started	Aug 14 05:58:56 PM PDT 24
Finished	Aug 14 07:21:38 PM PDT 24
Peak memory	610980 kb
Host	smart-9340ed6e-eef5-4e1d-bbf7-c3c552e297da
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=40_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=rom_e2e_keymgr_init_otp_no_meas :1:new_rules,otp_img_keymgr_otp_no_meas:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=787463827 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_e2e_keymgr_init_rom_ext_ no_meas.787463827
Directory	/workspace/1.rom_e2e_keymgr_init_rom_ext_no_meas/latest

Test location	/workspace/coverage/default/1.rom_e2e_self_hash.2517185600
Short name	T730
Test name
Test status
Simulation time	26337018668 ps
CPU time	5443.32 seconds
Started	Aug 14 06:00:30 PM PDT 24
Finished	Aug 14 07:31:15 PM PDT 24
Peak memory	611000 kb
Host	smart-893ba871-8edc-4991-9ae3-4d49cd14e03b
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=200_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=rom_e2e_self_hash_test:1:new_r ules,otp_img_sigverify_spx_prod:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2517185600 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_e2e_self_hash.2517185600
Directory	/workspace/1.rom_e2e_self_hash/latest

Test location	/workspace/coverage/default/1.rom_e2e_shutdown_exception_c.3453957903
Short name	T856
Test name
Test status
Simulation time	14511266209 ps
CPU time	3741.43 seconds
Started	Aug 14 05:58:52 PM PDT 24
Finished	Aug 14 07:01:14 PM PDT 24
Peak memory	611008 kb
Host	smart-d360e71d-b65a-4cab-afa6-3065a2412326
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=40000000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=rom_e2e_shutdown_exception_c:1:ne w_rules,otp_img_secret2_locked_rma:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3453957903 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rom_e2e_shu tdown_exception_c_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_e2e_ shutdown_exception_c.3453957903
Directory	/workspace/1.rom_e2e_shutdown_exception_c/latest

Test location	/workspace/coverage/default/1.rom_e2e_smoke.1940295806
Short name	T837
Test name
Test status
Simulation time	14517938596 ps
CPU time	3528.19 seconds
Started	Aug 14 05:57:58 PM PDT 24
Finished	Aug 14 06:56:46 PM PDT 24
Peak memory	610548 kb
Host	smart-185b79a8-fa5b-4201-b30f-32479f809397
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=40000000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=rom_e2e_smoke:1:new_rules,otp_img _secret2_locked_rma:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_to p/hw/dv/tools/sim.tcl +ntb_random_seed=1940295806 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_e2e_smoke.1940295806
Directory	/workspace/1.rom_e2e_smoke/latest

Test location	/workspace/coverage/default/1.rom_e2e_static_critical.751883290
Short name	T637
Test name
Test status
Simulation time	17497901354 ps
CPU time	4618.83 seconds
Started	Aug 14 06:00:00 PM PDT 24
Finished	Aug 14 07:17:00 PM PDT 24
Peak memory	610672 kb
Host	smart-463f8f7b-4b38-4dcd-beb4-40c5b7502d22
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=40000000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=rom_e2e_static_critical:1:new_rul es,otp_img_secret2_locked_rma:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=751883290 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_e2e_static_critical.751883290
Directory	/workspace/1.rom_e2e_static_critical/latest

Test location	/workspace/coverage/default/1.rom_keymgr_functest.1277943753
Short name	T843
Test name
Test status
Simulation time	5609098200 ps
CPU time	874.47 seconds
Started	Aug 14 05:57:00 PM PDT 24
Finished	Aug 14 06:11:35 PM PDT 24
Peak memory	610416 kb
Host	smart-5adfb912-f6d0-4b12-be0b-ccc6702448a3
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=10_000_000 +sw_build_device=sim_dv +sw_images=keymgr_functest:1:new_rules,test_rom:0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1277943753 -ass ert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 1.rom_keymgr_functest.1277943753
Directory	/workspace/1.rom_keymgr_functest/latest

Test location	/workspace/coverage/default/1.rom_raw_unlock.3980904325
Short name	T174
Test name
Test status
Simulation time	5631097835 ps
CPU time	250.8 seconds
Started	Aug 14 05:54:22 PM PDT 24
Finished	Aug 14 05:58:33 PM PDT 24
Peak memory	620120 kb
Host	smart-71d26f5b-0878-4c85-b47c-aeb2e8c13f78
User	root
Command	/workspace/default/simv +do_creator_sw_cfg_ast_cfg=0 +sw_test_timeout_ns=200_000_000 +use_otp_image=OtpTypeLcStRaw +chip_clock_source=ChipClockSourceE xternal48Mhz +rom_prod_mode=1 +use_jtag_dmi=1 +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_test_key_0:1:ot_flash_binary,mask_ro m:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=3980904325 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_raw_unlock_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_raw_unlock.3980904325
Directory	/workspace/1.rom_raw_unlock/latest

Test location	/workspace/coverage/default/1.rom_volatile_raw_unlock.731134528
Short name	T90
Test name
Test status
Simulation time	2453411273 ps
CPU time	109.29 seconds
Started	Aug 14 05:57:29 PM PDT 24
Finished	Aug 14 05:59:19 PM PDT 24
Peak memory	618096 kb
Host	smart-12e03274-eec5-4e79-9a02-dd48f12e9de2
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=200_000_000 +use_otp_image=OtpTypeLcStRaw +chip_clock_source=ChipClockSourceExternal48Mhz +rom_prod_mode=1 +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_test_key_0:1:ot_flash_binary,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=731134528 -assert nopostproc +UVM_T ESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_volatile_raw_unlock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage /default.vdb -cm_log /dev/null -cm_name 1.rom_volatile_raw_unlock.731134528
Directory	/workspace/1.rom_volatile_raw_unlock/latest

Test location	/workspace/coverage/default/10.chip_sw_alert_handler_lpg_sleep_mode_alerts.1939461744
Short name	T416
Test name
Test status
Simulation time	3414462840 ps
CPU time	407.98 seconds
Started	Aug 14 06:10:04 PM PDT 24
Finished	Aug 14 06:16:52 PM PDT 24
Peak memory	649564 kb
Host	smart-4bc3e4c6-ee24-4ccf-99c5-185d18d06bab
User	root
Command	/workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrlstate_regs +avoid_ferr_ips_append=otp_ctrlu_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1939461744 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.chip_ sw_alert_handler_lpg_sleep_mode_alerts.1939461744
Directory	/workspace/10.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location	/workspace/coverage/default/10.chip_sw_lc_ctrl_transition.2949642801
Short name	T591
Test name
Test status
Simulation time	12330093143 ps
CPU time	1000.03 seconds
Started	Aug 14 06:10:53 PM PDT 24
Finished	Aug 14 06:27:33 PM PDT 24
Peak memory	622136 kb
Host	smart-db28e00d-0bf8-42ac-83af-953d1a005dce
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=lc_ctrl_transition_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2949642801 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_transition_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau lt.vdb -cm_log /dev/null -cm_name 10.chip_sw_lc_ctrl_transition.2949642801
Directory	/workspace/10.chip_sw_lc_ctrl_transition/latest

Test location	/workspace/coverage/default/10.chip_sw_uart_rand_baudrate.2095954423
Short name	T153
Test name
Test status
Simulation time	4468651730 ps
CPU time	639.25 seconds
Started	Aug 14 06:10:12 PM PDT 24
Finished	Aug 14 06:20:51 PM PDT 24
Peak memory	620148 kb
Host	smart-13f65321-43a5-4dab-b122-15f71edd5d97
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random _seed=2095954423 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.chip_sw_uart_rand_baudrate.2095954423
Directory	/workspace/10.chip_sw_uart_rand_baudrate/latest

Test location	/workspace/coverage/default/11.chip_sw_lc_ctrl_transition.2760905552
Short name	T618
Test name
Test status
Simulation time	7414095846 ps
CPU time	613.8 seconds
Started	Aug 14 06:10:34 PM PDT 24
Finished	Aug 14 06:20:48 PM PDT 24
Peak memory	622064 kb
Host	smart-5e5292c3-6998-451c-b6a3-f528bef550a8
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=lc_ctrl_transition_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2760905552 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_transition_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau lt.vdb -cm_log /dev/null -cm_name 11.chip_sw_lc_ctrl_transition.2760905552
Directory	/workspace/11.chip_sw_lc_ctrl_transition/latest

Test location	/workspace/coverage/default/11.chip_sw_uart_rand_baudrate.2815729780
Short name	T693
Test name
Test status
Simulation time	4368550712 ps
CPU time	645.15 seconds
Started	Aug 14 06:09:57 PM PDT 24
Finished	Aug 14 06:20:44 PM PDT 24
Peak memory	620160 kb
Host	smart-38b0f65b-2089-4db4-90fd-8170f26dfd48
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random _seed=2815729780 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.chip_sw_uart_rand_baudrate.2815729780
Directory	/workspace/11.chip_sw_uart_rand_baudrate/latest

Test location	/workspace/coverage/default/12.chip_sw_alert_handler_lpg_sleep_mode_alerts.1192664245
Short name	T107
Test name
Test status
Simulation time	3933318294 ps
CPU time	438.85 seconds
Started	Aug 14 06:11:21 PM PDT 24
Finished	Aug 14 06:18:40 PM PDT 24
Peak memory	649812 kb
Host	smart-7061de59-f211-4a0e-8305-13934ca1cbdf
User	root
Command	/workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrlstate_regs +avoid_ferr_ips_append=otp_ctrlu_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1192664245 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.chip_ sw_alert_handler_lpg_sleep_mode_alerts.1192664245
Directory	/workspace/12.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location	/workspace/coverage/default/12.chip_sw_all_escalation_resets.2798808499
Short name	T468
Test name
Test status
Simulation time	5581115968 ps
CPU time	809.46 seconds
Started	Aug 14 06:11:38 PM PDT 24
Finished	Aug 14 06:25:08 PM PDT 24
Peak memory	620580 kb
Host	smart-521b4e10-79e0-4e55-85c8-eff3541d3626
User	root
Command	/workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 2798808499 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.chip_sw_all_escalation_resets.2798808499
Directory	/workspace/12.chip_sw_all_escalation_resets/latest

Test location	/workspace/coverage/default/12.chip_sw_lc_ctrl_transition.2332640500
Short name	T583
Test name
Test status
Simulation time	6877775315 ps
CPU time	587.24 seconds
Started	Aug 14 06:10:36 PM PDT 24
Finished	Aug 14 06:20:23 PM PDT 24
Peak memory	622128 kb
Host	smart-d4b947f3-ebe3-4ceb-aa4a-e09eb477e65b
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=lc_ctrl_transition_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2332640500 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_transition_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau lt.vdb -cm_log /dev/null -cm_name 12.chip_sw_lc_ctrl_transition.2332640500
Directory	/workspace/12.chip_sw_lc_ctrl_transition/latest

Test location	/workspace/coverage/default/12.chip_sw_uart_rand_baudrate.3311817046
Short name	T639
Test name
Test status
Simulation time	7791273672 ps
CPU time	1324.47 seconds
Started	Aug 14 06:10:50 PM PDT 24
Finished	Aug 14 06:32:56 PM PDT 24
Peak memory	619368 kb
Host	smart-8f327aad-abcb-4e7b-bb2b-5059f9185fc1
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random _seed=3311817046 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.chip_sw_uart_rand_baudrate.3311817046
Directory	/workspace/12.chip_sw_uart_rand_baudrate/latest

Test location	/workspace/coverage/default/13.chip_sw_all_escalation_resets.2819537970
Short name	T530
Test name
Test status
Simulation time	5046563598 ps
CPU time	590.61 seconds
Started	Aug 14 06:10:30 PM PDT 24
Finished	Aug 14 06:20:21 PM PDT 24
Peak memory	650812 kb
Host	smart-59d8671b-06af-4927-8b50-6a7f63988241
User	root
Command	/workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 2819537970 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.chip_sw_all_escalation_resets.2819537970
Directory	/workspace/13.chip_sw_all_escalation_resets/latest

Test location	/workspace/coverage/default/13.chip_sw_lc_ctrl_transition.3852137876
Short name	T854
Test name
Test status
Simulation time	6379373293 ps
CPU time	579.09 seconds
Started	Aug 14 06:11:54 PM PDT 24
Finished	Aug 14 06:21:33 PM PDT 24
Peak memory	622188 kb
Host	smart-a22bbc32-fe80-4247-b684-cfffea625a99
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=lc_ctrl_transition_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3852137876 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_transition_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau lt.vdb -cm_log /dev/null -cm_name 13.chip_sw_lc_ctrl_transition.3852137876
Directory	/workspace/13.chip_sw_lc_ctrl_transition/latest

Test location	/workspace/coverage/default/13.chip_sw_uart_rand_baudrate.1724338929
Short name	T981
Test name
Test status
Simulation time	12655780684 ps
CPU time	2421.26 seconds
Started	Aug 14 06:10:39 PM PDT 24
Finished	Aug 14 06:51:01 PM PDT 24
Peak memory	619424 kb
Host	smart-85c7edbf-011f-44d4-af15-9ac0f60ebd89
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random _seed=1724338929 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.chip_sw_uart_rand_baudrate.1724338929
Directory	/workspace/13.chip_sw_uart_rand_baudrate/latest

Test location	/workspace/coverage/default/14.chip_sw_lc_ctrl_transition.2585573117
Short name	T968
Test name
Test status
Simulation time	6613668312 ps
CPU time	499.82 seconds
Started	Aug 14 06:09:29 PM PDT 24
Finished	Aug 14 06:17:49 PM PDT 24
Peak memory	622196 kb
Host	smart-8a79f68a-7ac4-435c-8ae4-431254aae5fa
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=lc_ctrl_transition_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2585573117 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_transition_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau lt.vdb -cm_log /dev/null -cm_name 14.chip_sw_lc_ctrl_transition.2585573117
Directory	/workspace/14.chip_sw_lc_ctrl_transition/latest

Test location	/workspace/coverage/default/14.chip_sw_uart_rand_baudrate.1734302930
Short name	T887
Test name
Test status
Simulation time	7474685830 ps
CPU time	1380.87 seconds
Started	Aug 14 06:10:57 PM PDT 24
Finished	Aug 14 06:33:59 PM PDT 24
Peak memory	620116 kb
Host	smart-51c448af-eda2-4201-b9df-ac48ff6ee62c
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random _seed=1734302930 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.chip_sw_uart_rand_baudrate.1734302930
Directory	/workspace/14.chip_sw_uart_rand_baudrate/latest

Test location	/workspace/coverage/default/15.chip_sw_uart_rand_baudrate.4265899017
Short name	T370
Test name
Test status
Simulation time	12421889476 ps
CPU time	2286.18 seconds
Started	Aug 14 06:11:22 PM PDT 24
Finished	Aug 14 06:49:29 PM PDT 24
Peak memory	619416 kb
Host	smart-7a6d1943-3588-46b7-9dcc-b772c6ec5aa4
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random _seed=4265899017 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.chip_sw_uart_rand_baudrate.4265899017
Directory	/workspace/15.chip_sw_uart_rand_baudrate/latest

Test location	/workspace/coverage/default/16.chip_sw_uart_rand_baudrate.22756391
Short name	T677
Test name
Test status
Simulation time	13219302088 ps
CPU time	2272.63 seconds
Started	Aug 14 06:10:54 PM PDT 24
Finished	Aug 14 06:48:47 PM PDT 24
Peak memory	620120 kb
Host	smart-1c65bb96-bc05-496a-a065-b8cfb9dd2c23
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random _seed=22756391 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.chip_sw_uart_rand_baudrate.22756391
Directory	/workspace/16.chip_sw_uart_rand_baudrate/latest

Test location	/workspace/coverage/default/17.chip_sw_alert_handler_lpg_sleep_mode_alerts.3204210868
Short name	T440
Test name
Test status
Simulation time	3752213252 ps
CPU time	472.96 seconds
Started	Aug 14 06:11:27 PM PDT 24
Finished	Aug 14 06:19:21 PM PDT 24
Peak memory	649844 kb
Host	smart-1e1e649a-3840-4237-9cd9-a622a03bafde
User	root
Command	/workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrlstate_regs +avoid_ferr_ips_append=otp_ctrlu_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3204210868 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.chip_ sw_alert_handler_lpg_sleep_mode_alerts.3204210868
Directory	/workspace/17.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location	/workspace/coverage/default/17.chip_sw_uart_rand_baudrate.41120200
Short name	T343
Test name
Test status
Simulation time	3876088404 ps
CPU time	447.94 seconds
Started	Aug 14 06:11:21 PM PDT 24
Finished	Aug 14 06:18:49 PM PDT 24
Peak memory	620192 kb
Host	smart-cbe59811-931a-40c3-92fc-4f13a0191bf3
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random _seed=41120200 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.chip_sw_uart_rand_baudrate.41120200
Directory	/workspace/17.chip_sw_uart_rand_baudrate/latest

Test location	/workspace/coverage/default/18.chip_sw_alert_handler_lpg_sleep_mode_alerts.1987983552
Short name	T449
Test name
Test status
Simulation time	3478649432 ps
CPU time	323.48 seconds
Started	Aug 14 06:13:08 PM PDT 24
Finished	Aug 14 06:18:32 PM PDT 24
Peak memory	649464 kb
Host	smart-45b9e554-2cd7-49de-807f-0352e2dd28ba
User	root
Command	/workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrlstate_regs +avoid_ferr_ips_append=otp_ctrlu_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1987983552 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.chip_ sw_alert_handler_lpg_sleep_mode_alerts.1987983552
Directory	/workspace/18.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location	/workspace/coverage/default/18.chip_sw_uart_rand_baudrate.2157673183
Short name	T346
Test name
Test status
Simulation time	4021760520 ps
CPU time	418.38 seconds
Started	Aug 14 06:12:23 PM PDT 24
Finished	Aug 14 06:19:22 PM PDT 24
Peak memory	620124 kb
Host	smart-a086912c-6598-4620-9d05-a7c70dbf931b
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random _seed=2157673183 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.chip_sw_uart_rand_baudrate.2157673183
Directory	/workspace/18.chip_sw_uart_rand_baudrate/latest

Test location	/workspace/coverage/default/19.chip_sw_alert_handler_lpg_sleep_mode_alerts.2870813608
Short name	T444
Test name
Test status
Simulation time	4364159728 ps
CPU time	611.06 seconds
Started	Aug 14 06:11:56 PM PDT 24
Finished	Aug 14 06:22:08 PM PDT 24
Peak memory	649528 kb
Host	smart-157b43df-8f14-417e-964d-32310973210f
User	root
Command	/workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrlstate_regs +avoid_ferr_ips_append=otp_ctrlu_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2870813608 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.chip_ sw_alert_handler_lpg_sleep_mode_alerts.2870813608
Directory	/workspace/19.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location	/workspace/coverage/default/19.chip_sw_uart_rand_baudrate.363061838
Short name	T606
Test name
Test status
Simulation time	8363880936 ps
CPU time	1526.69 seconds
Started	Aug 14 06:12:06 PM PDT 24
Finished	Aug 14 06:37:33 PM PDT 24
Peak memory	619348 kb
Host	smart-b4a1ff89-81a6-49fd-b445-a63e5a8a53fc
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random _seed=363061838 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.chip_sw_uart_rand_baudrate.363061838
Directory	/workspace/19.chip_sw_uart_rand_baudrate/latest

Test location	/workspace/coverage/default/2.chip_jtag_mem_access.4155263942
Short name	T190
Test name
Test status
Simulation time	13694480440 ps
CPU time	1376.93 seconds
Started	Aug 14 05:57:52 PM PDT 24
Finished	Aug 14 06:20:49 PM PDT 24
Peak memory	608488 kb
Host	smart-df51849d-e74b-457c-a99b-dda4a85d544b
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4155263942 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_jtag_ mem_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_jtag_mem_access.4 155263942
Directory	/workspace/2.chip_jtag_mem_access/latest

Test location	/workspace/coverage/default/2.chip_rv_dm_ndm_reset_req.2825779027
Short name	T6
Test name
Test status
Simulation time	3919104948 ps
CPU time	431.5 seconds
Started	Aug 14 06:05:22 PM PDT 24
Finished	Aug 14 06:12:34 PM PDT 24
Peak memory	621128 kb
Host	smart-9bc8f91c-e778-45d5-a745-7cd60c65416c
User	root
Command	/workspace/default/simv +en_scb_tl_err_chk=0 +use_jtag_dmi=1 +sw_build_device=sim_dv +sw_images=rv_dm_ndm_reset_req_rma:1:new_rules,test_rom:0 +cdc_in strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2 825779027 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_rv_dm_ndm_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_rv_dm_ndm_reset_req.2825779027
Directory	/workspace/2.chip_rv_dm_ndm_reset_req/latest

Test location	/workspace/coverage/default/2.chip_sival_flash_info_access.2766432882
Short name	T626
Test name
Test status
Simulation time	3758113172 ps
CPU time	313.91 seconds
Started	Aug 14 05:56:01 PM PDT 24
Finished	Aug 14 06:01:15 PM PDT 24
Peak memory	610712 kb
Host	smart-631e89d0-8f8f-4bd5-846a-5127e52c1792
User	root
Command	/workspace/default/simv +use_otp_image=OtpTypeLcStTestUnlocked0 +sw_build_device=sim_dv +sw_images=flash_ctrl_info_access_lc:1:new_rules,test_rom:0 +c dc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_s eed=2766432882 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sival_flash_info_access.2766432882
Directory	/workspace/2.chip_sival_flash_info_access/latest

Test location	/workspace/coverage/default/2.chip_sw_adc_ctrl_sleep_debug_cable_wakeup.3131627258
Short name	T765
Test name
Test status
Simulation time	18436424470 ps
CPU time	476.3 seconds
Started	Aug 14 06:03:29 PM PDT 24
Finished	Aug 14 06:11:26 PM PDT 24
Peak memory	619736 kb
Host	smart-40f1cceb-1721-4911-ad9d-ac05734b43eb
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=adc_ctrl_sleep_debug_cable_wakeup_test:1:new_rules,test_rom: 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand om_seed=3131627258 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_adc_ctrl_sleep_debug_cable_wakeup_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_adc_ctrl_sleep_debug_cable_wakeup.3131627258
Directory	/workspace/2.chip_sw_adc_ctrl_sleep_debug_cable_wakeup/latest

Test location	/workspace/coverage/default/2.chip_sw_aes_enc.2728768814
Short name	T568
Test name
Test status
Simulation time	3721347200 ps
CPU time	360.69 seconds
Started	Aug 14 06:01:41 PM PDT 24
Finished	Aug 14 06:07:42 PM PDT 24
Peak memory	610444 kb
Host	smart-f41f8e9c-a51d-4db3-a4ea-e57d77c2e260
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=22_000_000 +sw_build_device=sim_dv +sw_images=aes_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2728768814 -asser t nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag e/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_aes_enc.2728768814
Directory	/workspace/2.chip_sw_aes_enc/latest

Test location	/workspace/coverage/default/2.chip_sw_aes_enc_jitter_en.2290999173
Short name	T710
Test name
Test status
Simulation time	3767460610 ps
CPU time	297.35 seconds
Started	Aug 14 06:03:00 PM PDT 24
Finished	Aug 14 06:07:57 PM PDT 24
Peak memory	610508 kb
Host	smart-74448011-2326-4680-aff7-ebe2094f56d0
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=26_000_000 +en_jitter=1 +sw_build_device=sim_dv +sw_images=aes_smoketest:1:new_rules,test_rom:0 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2290 999173 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work space/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_aes_enc_jitter_en.2290999173
Directory	/workspace/2.chip_sw_aes_enc_jitter_en/latest

Test location	/workspace/coverage/default/2.chip_sw_aes_enc_jitter_en_reduced_freq.3389190390
Short name	T653
Test name
Test status
Simulation time	2415687609 ps
CPU time	288.89 seconds
Started	Aug 14 06:07:42 PM PDT 24
Finished	Aug 14 06:12:31 PM PDT 24
Peak memory	610552 kb
Host	smart-aab2e7de-e454-46a1-9898-d59ebee7af8b
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=26_000_000 +en_jitter=1 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=aes_smoketest:1:new_rules, test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3389190390 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_aes_enc_jitter_en_reduced_freq.3389190390
Directory	/workspace/2.chip_sw_aes_enc_jitter_en_reduced_freq/latest

Test location	/workspace/coverage/default/2.chip_sw_aes_entropy.2779743869
Short name	T603
Test name
Test status
Simulation time	3153905674 ps
CPU time	293.26 seconds
Started	Aug 14 06:02:49 PM PDT 24
Finished	Aug 14 06:07:43 PM PDT 24
Peak memory	610476 kb
Host	smart-2c134a5c-f188-4482-9e21-3379fab55a17
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=15_000_000 +sw_build_device=sim_dv +sw_images=aes_entropy_test:1:new_rules,test_rom:0 +cdc_instrumentation _enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2779743869 -as sert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove rage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_aes_entropy.2779743869
Directory	/workspace/2.chip_sw_aes_entropy/latest

Test location	/workspace/coverage/default/2.chip_sw_aes_idle.2991549210
Short name	T965
Test name
Test status
Simulation time	3269599048 ps
CPU time	363.28 seconds
Started	Aug 14 06:02:24 PM PDT 24
Finished	Aug 14 06:08:27 PM PDT 24
Peak memory	610464 kb
Host	smart-b17d9aea-a951-419f-a49a-c8f2bc2d9054
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=25_000_000 +sw_build_device=sim_dv +sw_images=aes_idle_test:1:new_rules,test_rom:0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2991549210 -asser t nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag e/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_aes_idle.2991549210
Directory	/workspace/2.chip_sw_aes_idle/latest

Test location	/workspace/coverage/default/2.chip_sw_aes_masking_off.2670457789
Short name	T715
Test name
Test status
Simulation time	2492680275 ps
CPU time	252.9 seconds
Started	Aug 14 06:03:13 PM PDT 24
Finished	Aug 14 06:07:26 PM PDT 24
Peak memory	610736 kb
Host	smart-e0fa3948-5c55-4b9e-9769-b29a347e1b00
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=aes_masking_off_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2670457789 -assert nopostproc +UVM_TESTNA ME=chip_base_test +UVM_TEST_SEQ=chip_sw_aes_masking_off_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_aes_masking_off.2670457789
Directory	/workspace/2.chip_sw_aes_masking_off/latest

Test location	/workspace/coverage/default/2.chip_sw_aes_smoketest.338953215
Short name	T431
Test name
Test status
Simulation time	3041935512 ps
CPU time	269.83 seconds
Started	Aug 14 06:07:47 PM PDT 24
Finished	Aug 14 06:12:17 PM PDT 24
Peak memory	610460 kb
Host	smart-bb80c1e9-d13c-4ff9-aff9-24ef638888a4
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=aes_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=338953215 -assert nopostproc +UVM_TESTNAME=chip_ base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_aes_smoketest.338953215
Directory	/workspace/2.chip_sw_aes_smoketest/latest

Test location	/workspace/coverage/default/2.chip_sw_alert_handler_entropy.1902749014
Short name	T19
Test name
Test status
Simulation time	3342222451 ps
CPU time	400.09 seconds
Started	Aug 14 06:03:10 PM PDT 24
Finished	Aug 14 06:09:51 PM PDT 24
Peak memory	610104 kb
Host	smart-2864fc12-438e-4945-9a5b-e59925c13ed7
User	root
Command	/workspace/default/simv +en_scb=0 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=alert_handler_entropy_test:1:new_rules,test_ro m:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=1902749014 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_alert_handler_entropy.1902749014
Directory	/workspace/2.chip_sw_alert_handler_entropy/latest

Test location	/workspace/coverage/default/2.chip_sw_alert_handler_escalation.1173347076
Short name	T262
Test name
Test status
Simulation time	5822403728 ps
CPU time	672.23 seconds
Started	Aug 14 06:03:46 PM PDT 24
Finished	Aug 14 06:14:59 PM PDT 24
Peak memory	620368 kb
Host	smart-c931b42d-f19f-4158-9c3e-2a296d51011a
User	root
Command	/workspace/default/simv +en_scb=0 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=alert_handler_escalation_test:1:new_rules,test _rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb _random_seed=1173347076 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_alert_handler_escalation_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_alert_handler_escalation.1173347076
Directory	/workspace/2.chip_sw_alert_handler_escalation/latest

Test location	/workspace/coverage/default/2.chip_sw_alert_handler_lpg_clkoff.644592039
Short name	T563
Test name
Test status
Simulation time	7747478936 ps
CPU time	1641.78 seconds
Started	Aug 14 06:05:25 PM PDT 24
Finished	Aug 14 06:32:47 PM PDT 24
Peak memory	610900 kb
Host	smart-8328ac25-1789-462e-ab18-1dcf1c27bd9d
User	root
Command	/workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +sw_build_device=sim_dv +sw_images=alert_handler_lpg_clkoff_test:1:new_rules,test_r om:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r andom_seed=644592039 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_alert_handler_lpg_clkoff_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_alert_handler_lpg_clkoff.644592039
Directory	/workspace/2.chip_sw_alert_handler_lpg_clkoff/latest

Test location	/workspace/coverage/default/2.chip_sw_alert_handler_lpg_reset_toggle.2418528435
Short name	T671
Test name
Test status
Simulation time	7647603192 ps
CPU time	1526.62 seconds
Started	Aug 14 06:03:26 PM PDT 24
Finished	Aug 14 06:28:52 PM PDT 24
Peak memory	610688 kb
Host	smart-543ec7f0-6421-46bd-9710-8595f30cb447
User	root
Command	/workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +sw_build_device=sim_dv +sw_images=alert_handler_lpg_reset_toggle_test:1:new_rules, test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2418528435 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_alert_handler_shorten_ping_wait_cycle_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_alert_handler_lpg_reset_togg le.2418528435
Directory	/workspace/2.chip_sw_alert_handler_lpg_reset_toggle/latest

Test location	/workspace/coverage/default/2.chip_sw_alert_handler_lpg_sleep_mode_alerts.4171697155
Short name	T550
Test name
Test status
Simulation time	3046854304 ps
CPU time	452.55 seconds
Started	Aug 14 06:02:39 PM PDT 24
Finished	Aug 14 06:10:12 PM PDT 24
Peak memory	649208 kb
Host	smart-eb52143e-a0ad-475f-b370-6f65b34da1b0
User	root
Command	/workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrlstate_regs +avoid_ferr_ips_append=otp_ctrlu_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4171697155 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_s w_alert_handler_lpg_sleep_mode_alerts.4171697155
Directory	/workspace/2.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location	/workspace/coverage/default/2.chip_sw_alert_handler_lpg_sleep_mode_pings.3668341477
Short name	T476
Test name
Test status
Simulation time	11619422500 ps
CPU time	1337.42 seconds
Started	Aug 14 06:02:04 PM PDT 24
Finished	Aug 14 06:24:21 PM PDT 24
Peak memory	611660 kb
Host	smart-41dae853-45b9-4427-955f-277315cc4a82
User	root
Command	/workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=alert_handler _lpg_sleep_mode_pings_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3668341477 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_alert_han dler_shorten_ping_wait_cycle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_alert_handler_lpg_sleep_mode_pings.3668341477
Directory	/workspace/2.chip_sw_alert_handler_lpg_sleep_mode_pings/latest

Test location	/workspace/coverage/default/2.chip_sw_alert_handler_ping_ok.1759511302
Short name	T897
Test name
Test status
Simulation time	7637888472 ps
CPU time	1231.59 seconds
Started	Aug 14 06:03:50 PM PDT 24
Finished	Aug 14 06:24:22 PM PDT 24
Peak memory	609736 kb
Host	smart-1f37a487-948e-4d4c-9be1-36d29d621731
User	root
Command	/workspace/default/simv +en_scb=0 +sw_test_timeout_ns=24000000 +sw_build_device=sim_dv +sw_images=alert_handler_ping_ok_test:1:new_rules,test_rom:0 +c dc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_s eed=1759511302 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_alert_handler_ping_ok.1759511302
Directory	/workspace/2.chip_sw_alert_handler_ping_ok/latest

Test location	/workspace/coverage/default/2.chip_sw_alert_handler_ping_timeout.176976909
Short name	T687
Test name
Test status
Simulation time	3638244742 ps
CPU time	475.32 seconds
Started	Aug 14 06:04:43 PM PDT 24
Finished	Aug 14 06:12:40 PM PDT 24
Peak memory	610264 kb
Host	smart-a73bf2ee-6a17-4e6f-8cb5-d5236aa1ab29
User	root
Command	/workspace/default/simv +en_scb=0 +sw_test_timeout_ns=24000000 +sw_build_device=sim_dv +sw_images=alert_handler_ping_timeout_test:1:new_rules,test_rom :0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=176976909 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_alert_handler_ping_timeout.176976909
Directory	/workspace/2.chip_sw_alert_handler_ping_timeout/latest

Test location	/workspace/coverage/default/2.chip_sw_alert_handler_reverse_ping_in_deep_sleep.357111902
Short name	T791
Test name
Test status
Simulation time	255065009480 ps
CPU time	12927.7 seconds
Started	Aug 14 06:02:31 PM PDT 24
Finished	Aug 14 09:38:01 PM PDT 24
Peak memory	611508 kb
Host	smart-0eb51883-a7be-490d-abd8-73af61ccbe4a
User	root
Command	/workspace/default/simv +en_scb=0 +sw_test_timeout_ns=300_000_000 +sw_build_device=sim_dv +sw_images=alert_handler_reverse_ping_in_deep_sleep_test:1:n ew_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=357111902 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tg l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_alert_handler_reverse_ping_in_deep_sleep.357111902
Directory	/workspace/2.chip_sw_alert_handler_reverse_ping_in_deep_sleep/latest

Test location	/workspace/coverage/default/2.chip_sw_alert_test.1645554855
Short name	T76
Test name
Test status
Simulation time	3130431026 ps
CPU time	351.93 seconds
Started	Aug 14 06:03:05 PM PDT 24
Finished	Aug 14 06:08:58 PM PDT 24
Peak memory	610476 kb
Host	smart-abc0ae38-7348-46b6-b50b-4f48e3edc068
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=alert_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1645554855 -assert nopostproc +UVM_TESTNAME=chip_ba se_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 2.chip_sw_alert_test.1645554855
Directory	/workspace/2.chip_sw_alert_test/latest

Test location	/workspace/coverage/default/2.chip_sw_aon_timer_irq.2250092850
Short name	T990
Test name
Test status
Simulation time	3667633992 ps
CPU time	351.28 seconds
Started	Aug 14 06:02:21 PM PDT 24
Finished	Aug 14 06:08:13 PM PDT 24
Peak memory	610496 kb
Host	smart-72771e2d-6643-4767-bcc1-7bd1e7c70afc
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=aon_timer_irq_test:1:new_rules,test_rom:0 +cdc_instrumentati on_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2250092850 - assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co verage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_aon_timer_irq.2250092850
Directory	/workspace/2.chip_sw_aon_timer_irq/latest

Test location	/workspace/coverage/default/2.chip_sw_aon_timer_sleep_wdog_sleep_pause.1923374262
Short name	T596
Test name
Test status
Simulation time	8164664780 ps
CPU time	610.22 seconds
Started	Aug 14 06:03:25 PM PDT 24
Finished	Aug 14 06:13:35 PM PDT 24
Peak memory	611204 kb
Host	smart-ccb572cb-fd26-4311-9b2f-447f6d03fa16
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=aon_timer_sleep_wdog_sleep_pause_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=1923374262 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_aon_timer_sleep_wdog_sleep_pause.1923374262
Directory	/workspace/2.chip_sw_aon_timer_sleep_wdog_sleep_pause/latest

Test location	/workspace/coverage/default/2.chip_sw_aon_timer_smoketest.251141006
Short name	T749
Test name
Test status
Simulation time	2824324664 ps
CPU time	360.55 seconds
Started	Aug 14 06:06:37 PM PDT 24
Finished	Aug 14 06:12:37 PM PDT 24
Peak memory	610424 kb
Host	smart-65f44742-3567-44b2-8055-cd809408bd48
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=aon_timer_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=251141006 -assert nopostproc +UVM_TESTNAME =chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 2.chip_sw_aon_timer_smoketest.251141006
Directory	/workspace/2.chip_sw_aon_timer_smoketest/latest

Test location	/workspace/coverage/default/2.chip_sw_aon_timer_wdog_bite_reset.4136851538
Short name	T306
Test name
Test status
Simulation time	6592261040 ps
CPU time	702.75 seconds
Started	Aug 14 06:03:34 PM PDT 24
Finished	Aug 14 06:15:17 PM PDT 24
Peak memory	611244 kb
Host	smart-44ed82f9-e4af-43ff-a4d1-9a62cc8689c4
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=aon_timer_wdog_bite_reset_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 4136851538 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_aon_timer_wdog_bite_reset.4136851538
Directory	/workspace/2.chip_sw_aon_timer_wdog_bite_reset/latest

Test location	/workspace/coverage/default/2.chip_sw_aon_timer_wdog_lc_escalate.2131077994
Short name	T700
Test name
Test status
Simulation time	5755936466 ps
CPU time	560.67 seconds
Started	Aug 14 06:02:18 PM PDT 24
Finished	Aug 14 06:11:39 PM PDT 24
Peak memory	611416 kb
Host	smart-3938dfcd-b0d3-4674-9325-02e1168a68fd
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=aon_timer_wdog_lc_escalate_test:1:new_rules,test_rom:0 +cdc_ instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed =2131077994 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_aon_timer_wdog_lc_escalate.2131077994
Directory	/workspace/2.chip_sw_aon_timer_wdog_lc_escalate/latest

Test location	/workspace/coverage/default/2.chip_sw_ast_clk_outputs.2784336409
Short name	T807
Test name
Test status
Simulation time	6796966184 ps
CPU time	1101.12 seconds
Started	Aug 14 06:06:14 PM PDT 24
Finished	Aug 14 06:24:35 PM PDT 24
Peak memory	618072 kb
Host	smart-53a508af-82f6-4b62-a168-172027096b23
User	root
Command	/workspace/default/simv +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=ast_clk_outs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled= 1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2784336409 -assert nopo stproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_ast_clk_outputs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co verage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_ast_clk_outputs.2784336409
Directory	/workspace/2.chip_sw_ast_clk_outputs/latest

Test location	/workspace/coverage/default/2.chip_sw_ast_clk_rst_inputs.2261426396
Short name	T148
Test name
Test status
Simulation time	22553776838 ps
CPU time	2918.79 seconds
Started	Aug 14 06:06:47 PM PDT 24
Finished	Aug 14 06:55:28 PM PDT 24
Peak memory	611552 kb
Host	smart-be3e07ae-f182-4286-a6d7-d1f2b37a9c21
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=200_000_000 +sw_build_device=sim_dv +sw_images=ast_clk_rst_inputs:1:new_rules,test_rom:0 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2261426396 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_ast_clk_rst_inputs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_ast_clk_rst_inputs.2261426396
Directory	/workspace/2.chip_sw_ast_clk_rst_inputs/latest

Test location	/workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_lc.371467360
Short name	T428
Test name
Test status
Simulation time	12004568013 ps
CPU time	957.94 seconds
Started	Aug 14 06:04:59 PM PDT 24
Finished	Aug 14 06:20:57 PM PDT 24
Peak memory	622180 kb
Host	smart-4f8ca6e0-46fc-4af8-af23-086ec1b6e22e
User	root
Command	/workspace/default/simv +chip_clock_source=ChipClockSourceExternal48Mhz +sw_build_device=sim_dv +sw_images=clkmgr_external_clk_src_for_lc_test:1:new_r ules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim .tcl +ntb_random_seed=371467360 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_transition_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_clkmgr_external_clk_src_for_lc.371467360
Directory	/workspace/2.chip_sw_clkmgr_external_clk_src_for_lc/latest

Test location	/workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_fast_dev.2735759658
Short name	T72
Test name
Test status
Simulation time	4047686950 ps
CPU time	764.45 seconds
Started	Aug 14 06:04:42 PM PDT 24
Finished	Aug 14 06:17:27 PM PDT 24
Peak memory	614584 kb
Host	smart-e143d414-e0d6-4bfe-a3d0-0bb541239c87
User	root
Command	/workspace/default/simv +chip_clock_source=ChipClockSourceExternal96Mhz +calibrate_usb_clk=1 +src_dec_state=DecLcStDev +sw_build_device=sim_dv +sw_ima ges=clkmgr_external_clk_src_for_sw_fast_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2735759658 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ =chip_sw_lc_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_c lkmgr_external_clk_src_for_sw_fast_dev.2735759658
Directory	/workspace/2.chip_sw_clkmgr_external_clk_src_for_sw_fast_dev/latest

Test location	/workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_fast_rma.4727861
Short name	T844
Test name
Test status
Simulation time	3844572224 ps
CPU time	568.47 seconds
Started	Aug 14 06:07:26 PM PDT 24
Finished	Aug 14 06:16:54 PM PDT 24
Peak memory	614824 kb
Host	smart-af073f4d-ab18-41d4-bee2-ca07df6a3ff7
User	root
Command	/workspace/default/simv +chip_clock_source=ChipClockSourceExternal96Mhz +calibrate_usb_clk=1 +src_dec_state=DecLcStRma +sw_build_device=sim_dv +sw_ima ges=clkmgr_external_clk_src_for_sw_fast_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4727861 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=ch ip_sw_lc_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_clkm gr_external_clk_src_for_sw_fast_rma.4727861
Directory	/workspace/2.chip_sw_clkmgr_external_clk_src_for_sw_fast_rma/latest

Test location	/workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0.492467840
Short name	T935
Test name
Test status
Simulation time	4442272540 ps
CPU time	742.15 seconds
Started	Aug 14 06:04:08 PM PDT 24
Finished	Aug 14 06:16:31 PM PDT 24
Peak memory	614944 kb
Host	smart-962db453-83fe-426d-ac77-26b0f9c9aafe
User	root
Command	/workspace/default/simv +chip_clock_source=ChipClockSourceExternal96Mhz +calibrate_usb_clk=1 +src_dec_state=DecLcStTestUnlocked0 +sw_build_device=sim_ dv +sw_images=clkmgr_external_clk_src_for_sw_fast_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=492467840 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM _TEST_SEQ=chip_sw_lc_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2. chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0.492467840
Directory	/workspace/2.chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0/latest

Test location	/workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_slow_dev.1279413782
Short name	T644
Test name
Test status
Simulation time	4681570364 ps
CPU time	642.5 seconds
Started	Aug 14 06:04:27 PM PDT 24
Finished	Aug 14 06:15:10 PM PDT 24
Peak memory	613796 kb
Host	smart-e2b4c725-063f-444b-9200-14ef59707721
User	root
Command	/workspace/default/simv +chip_clock_source=ChipClockSourceExternal48Mhz +calibrate_usb_clk=1 +src_dec_state=DecLcStDev +sw_build_device=sim_dv +sw_ima ges=clkmgr_external_clk_src_for_sw_slow_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1279413782 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ =chip_sw_lc_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_c lkmgr_external_clk_src_for_sw_slow_dev.1279413782
Directory	/workspace/2.chip_sw_clkmgr_external_clk_src_for_sw_slow_dev/latest

Test location	/workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_slow_rma.2692196951
Short name	T130
Test name
Test status
Simulation time	4702677960 ps
CPU time	556.65 seconds
Started	Aug 14 06:06:24 PM PDT 24
Finished	Aug 14 06:15:41 PM PDT 24
Peak memory	613956 kb
Host	smart-32906699-71cc-4a25-801c-2e9aab3ada9e
User	root
Command	/workspace/default/simv +chip_clock_source=ChipClockSourceExternal48Mhz +calibrate_usb_clk=1 +src_dec_state=DecLcStRma +sw_build_device=sim_dv +sw_ima ges=clkmgr_external_clk_src_for_sw_slow_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2692196951 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ =chip_sw_lc_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_c lkmgr_external_clk_src_for_sw_slow_rma.2692196951
Directory	/workspace/2.chip_sw_clkmgr_external_clk_src_for_sw_slow_rma/latest

Test location	/workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0.2449893406
Short name	T560
Test name
Test status
Simulation time	4732018472 ps
CPU time	704.8 seconds
Started	Aug 14 06:04:30 PM PDT 24
Finished	Aug 14 06:16:15 PM PDT 24
Peak memory	614852 kb
Host	smart-6196cae8-f621-4f39-a243-5ea8b1e0c8d2
User	root
Command	/workspace/default/simv +chip_clock_source=ChipClockSourceExternal48Mhz +calibrate_usb_clk=1 +src_dec_state=DecLcStTestUnlocked0 +sw_build_device=sim_ dv +sw_images=clkmgr_external_clk_src_for_sw_slow_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2449893406 -assert nopostproc +UVM_TESTNAME=chip_base_test +UV M_TEST_SEQ=chip_sw_lc_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2 .chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0.2449893406
Directory	/workspace/2.chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0/latest

Test location	/workspace/coverage/default/2.chip_sw_clkmgr_jitter.3835819115
Short name	T1019
Test name
Test status
Simulation time	3337969327 ps
CPU time	168.28 seconds
Started	Aug 14 06:05:42 PM PDT 24
Finished	Aug 14 06:08:31 PM PDT 24
Peak memory	610348 kb
Host	smart-5ad1a495-968e-413a-9c30-53ad41341542
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=clkmgr_jitter_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3835819115 -assert nopostproc +UVM_TESTNAME =chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 2.chip_sw_clkmgr_jitter.3835819115
Directory	/workspace/2.chip_sw_clkmgr_jitter/latest

Test location	/workspace/coverage/default/2.chip_sw_clkmgr_jitter_frequency.872058532
Short name	T933
Test name
Test status
Simulation time	3550677500 ps
CPU time	489.72 seconds
Started	Aug 14 06:05:53 PM PDT 24
Finished	Aug 14 06:14:03 PM PDT 24
Peak memory	610616 kb
Host	smart-37390d72-4dc2-4d39-951b-3a981bcc312f
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=clkmgr_jitter_frequency_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=872058532 -assert nopostproc +UVM _TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm _log /dev/null -cm_name 2.chip_sw_clkmgr_jitter_frequency.872058532
Directory	/workspace/2.chip_sw_clkmgr_jitter_frequency/latest

Test location	/workspace/coverage/default/2.chip_sw_clkmgr_jitter_reduced_freq.3473373804
Short name	T621
Test name
Test status
Simulation time	2942430684 ps
CPU time	181.66 seconds
Started	Aug 14 06:04:35 PM PDT 24
Finished	Aug 14 06:07:37 PM PDT 24
Peak memory	608948 kb
Host	smart-47bc1c75-0c96-4f61-9b8f-df4e91f413bc
User	root
Command	/workspace/default/simv +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=clkmgr_jitter_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3473373804 -assert nop ostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def ault.vdb -cm_log /dev/null -cm_name 2.chip_sw_clkmgr_jitter_reduced_freq.3473373804
Directory	/workspace/2.chip_sw_clkmgr_jitter_reduced_freq/latest

Test location	/workspace/coverage/default/2.chip_sw_clkmgr_off_aes_trans.3962042993
Short name	T562
Test name
Test status
Simulation time	4736759500 ps
CPU time	605.58 seconds
Started	Aug 14 06:04:52 PM PDT 24
Finished	Aug 14 06:14:58 PM PDT 24
Peak memory	610932 kb
Host	smart-635558a1-251c-46ed-a24d-62b13cadbae1
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=clkmgr_off_aes_trans_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3962042993 -assert nopostproc +UVM_T ESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l og /dev/null -cm_name 2.chip_sw_clkmgr_off_aes_trans.3962042993
Directory	/workspace/2.chip_sw_clkmgr_off_aes_trans/latest

Test location	/workspace/coverage/default/2.chip_sw_clkmgr_off_hmac_trans.796090901
Short name	T186
Test name
Test status
Simulation time	4750252968 ps
CPU time	565.68 seconds
Started	Aug 14 06:05:31 PM PDT 24
Finished	Aug 14 06:14:57 PM PDT 24
Peak memory	611184 kb
Host	smart-6b58d4c3-b54d-4a6f-8ce9-657b05bb752b
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=clkmgr_off_hmac_trans_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=796090901 -assert nopostproc +UVM_T ESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l og /dev/null -cm_name 2.chip_sw_clkmgr_off_hmac_trans.796090901
Directory	/workspace/2.chip_sw_clkmgr_off_hmac_trans/latest

Test location	/workspace/coverage/default/2.chip_sw_clkmgr_off_kmac_trans.246978225
Short name	T848
Test name
Test status
Simulation time	5065944658 ps
CPU time	445.19 seconds
Started	Aug 14 06:04:06 PM PDT 24
Finished	Aug 14 06:11:31 PM PDT 24
Peak memory	611188 kb
Host	smart-35272618-c3e0-4c70-8eaf-0c7ab2e151f7
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=clkmgr_off_kmac_trans_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=246978225 -assert nopostproc +UVM_T ESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l og /dev/null -cm_name 2.chip_sw_clkmgr_off_kmac_trans.246978225
Directory	/workspace/2.chip_sw_clkmgr_off_kmac_trans/latest

Test location	/workspace/coverage/default/2.chip_sw_clkmgr_off_otbn_trans.929053786
Short name	T396
Test name
Test status
Simulation time	3635159176 ps
CPU time	445.63 seconds
Started	Aug 14 06:05:06 PM PDT 24
Finished	Aug 14 06:12:32 PM PDT 24
Peak memory	610580 kb
Host	smart-6abd95be-403d-49f2-b380-4a72bbe65304
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=clkmgr_off_otbn_trans_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=929053786 -assert nopostproc +UVM_T ESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l og /dev/null -cm_name 2.chip_sw_clkmgr_off_otbn_trans.929053786
Directory	/workspace/2.chip_sw_clkmgr_off_otbn_trans/latest

Test location	/workspace/coverage/default/2.chip_sw_clkmgr_off_peri.3167752369
Short name	T768
Test name
Test status
Simulation time	10104325954 ps
CPU time	1495.63 seconds
Started	Aug 14 06:05:08 PM PDT 24
Finished	Aug 14 06:30:04 PM PDT 24
Peak memory	611188 kb
Host	smart-59a0a757-73b8-4809-90f1-09ca3cab6e0e
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=30_000_000 +sw_build_device=sim_dv +sw_images=clkmgr_off_peri_test:1:new_rules,test_rom:0 +cdc_instrumenta tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3167752369 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/ coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_clkmgr_off_peri.3167752369
Directory	/workspace/2.chip_sw_clkmgr_off_peri/latest

Test location	/workspace/coverage/default/2.chip_sw_clkmgr_reset_frequency.1514848694
Short name	T886
Test name
Test status
Simulation time	3132895368 ps
CPU time	471.57 seconds
Started	Aug 14 06:05:51 PM PDT 24
Finished	Aug 14 06:13:43 PM PDT 24
Peak memory	610664 kb
Host	smart-43ed6140-7291-4149-855e-28b603b6a2cc
User	root
Command	/workspace/default/simv +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=clkmgr_reset_frequency_test:1:new_rules,test_rom:0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1514848694 -a ssert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov erage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_clkmgr_reset_frequency.1514848694
Directory	/workspace/2.chip_sw_clkmgr_reset_frequency/latest

Test location	/workspace/coverage/default/2.chip_sw_clkmgr_sleep_frequency.2915967128
Short name	T784
Test name
Test status
Simulation time	4388104966 ps
CPU time	741.27 seconds
Started	Aug 14 06:05:56 PM PDT 24
Finished	Aug 14 06:18:18 PM PDT 24
Peak memory	610756 kb
Host	smart-005d2fd0-5bf7-4ad4-be60-5c63b0086ff6
User	root
Command	/workspace/default/simv +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=clkmgr_sleep_frequency_test:1:new_rules,test_rom:0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2915967128 -a ssert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov erage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_clkmgr_sleep_frequency.2915967128
Directory	/workspace/2.chip_sw_clkmgr_sleep_frequency/latest

Test location	/workspace/coverage/default/2.chip_sw_clkmgr_smoketest.527556157
Short name	T811
Test name
Test status
Simulation time	2351706532 ps
CPU time	223.62 seconds
Started	Aug 14 06:08:54 PM PDT 24
Finished	Aug 14 06:12:38 PM PDT 24
Peak memory	610156 kb
Host	smart-0cb72d38-aca9-4f82-a7ca-d9399eb7ccb7
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=clkmgr_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=527556157 -assert nopostproc +UVM_TESTNAME=ch ip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu ll -cm_name 2.chip_sw_clkmgr_smoketest.527556157
Directory	/workspace/2.chip_sw_clkmgr_smoketest/latest

Test location	/workspace/coverage/default/2.chip_sw_csrng_edn_concurrency.621411540
Short name	T669
Test name
Test status
Simulation time	23036749340 ps
CPU time	5088.41 seconds
Started	Aug 14 06:04:13 PM PDT 24
Finished	Aug 14 07:29:03 PM PDT 24
Peak memory	611180 kb
Host	smart-41c2601b-85ea-46b6-a426-94e44a7d961b
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=140_000_000 +rng_srate_value_min=15 +rng_srate_value_max=20 +accelerate_cold_power_up_time=3 +accelerate_r egulators_power_up_time=2 +sw_build_device=sim_dv +sw_images=csrng_edn_concurrency_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=621411540 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_csrng_edn_concurrency.621411540
Directory	/workspace/2.chip_sw_csrng_edn_concurrency/latest

Test location	/workspace/coverage/default/2.chip_sw_csrng_fuse_en_sw_app_read_test.4210568200
Short name	T224
Test name
Test status
Simulation time	4378944052 ps
CPU time	673.4 seconds
Started	Aug 14 06:04:32 PM PDT 24
Finished	Aug 14 06:15:45 PM PDT 24
Peak memory	611548 kb
Host	smart-7edd94a8-2e3e-4d6c-a14c-cd9640da487e
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=15_000_000 +sw_build_device=sim_dv +sw_images=csrng_fuse_en_sw_app_read:1:new_rules,test_rom:0 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42105 68200 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_entropy_src_fuse_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_csrng_fuse_en_sw_app_read_test.4210568200
Directory	/workspace/2.chip_sw_csrng_fuse_en_sw_app_read_test/latest

Test location	/workspace/coverage/default/2.chip_sw_csrng_kat_test.313935292
Short name	T578
Test name
Test status
Simulation time	2444234174 ps
CPU time	283.8 seconds
Started	Aug 14 06:02:41 PM PDT 24
Finished	Aug 14 06:07:25 PM PDT 24
Peak memory	609720 kb
Host	smart-ea44436c-4706-4306-ba70-39d64e5368f5
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=csrng_kat_test:1:new_rules,test_rom:0 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=313935292 -asser t nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag e/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_csrng_kat_test.313935292
Directory	/workspace/2.chip_sw_csrng_kat_test/latest

Test location	/workspace/coverage/default/2.chip_sw_csrng_lc_hw_debug_en_test.2470563069
Short name	T993
Test name
Test status
Simulation time	5976347652 ps
CPU time	731.88 seconds
Started	Aug 14 06:03:22 PM PDT 24
Finished	Aug 14 06:15:35 PM PDT 24
Peak memory	611340 kb
Host	smart-6e45e281-ec43-4c7c-8c0b-93f3c28b72ba
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=15_000_000 +rng_srate_value_min=15 +use_otp_image=OtpTypeLcStTestUnlocked0 +sw_build_device=sim_dv +sw_ima ges=csrng_lc_hw_debug_en_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2470563069 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_csrng_ lc_hw_debug_en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_csr ng_lc_hw_debug_en_test.2470563069
Directory	/workspace/2.chip_sw_csrng_lc_hw_debug_en_test/latest

Test location	/workspace/coverage/default/2.chip_sw_csrng_smoketest.2724008846
Short name	T850
Test name
Test status
Simulation time	3095751800 ps
CPU time	293.07 seconds
Started	Aug 14 06:07:22 PM PDT 24
Finished	Aug 14 06:12:16 PM PDT 24
Peak memory	610396 kb
Host	smart-fdd951b3-968b-44e2-b4de-9e828fab2bc5
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=csrng_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2724008846 -assert nopostproc +UVM_TESTNAME=ch ip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu ll -cm_name 2.chip_sw_csrng_smoketest.2724008846
Directory	/workspace/2.chip_sw_csrng_smoketest/latest

Test location	/workspace/coverage/default/2.chip_sw_data_integrity_escalation.3987462268
Short name	T776
Test name
Test status
Simulation time	5124849064 ps
CPU time	540.23 seconds
Started	Aug 14 05:55:08 PM PDT 24
Finished	Aug 14 06:04:08 PM PDT 24
Peak memory	609252 kb
Host	smart-1e01a019-b7a0-45c9-b6d5-276f15c99981
User	root
Command	/workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=data_integrity_escalation_reset_test:1:new_rules,test_ro m:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=3987462268 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_data_integrity_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_data_integrity_escalation.3987462268
Directory	/workspace/2.chip_sw_data_integrity_escalation/latest

Test location	/workspace/coverage/default/2.chip_sw_edn_auto_mode.520808838
Short name	T131
Test name
Test status
Simulation time	4655394850 ps
CPU time	1025.75 seconds
Started	Aug 14 06:06:25 PM PDT 24
Finished	Aug 14 06:23:31 PM PDT 24
Peak memory	610760 kb
Host	smart-9abc0e2e-4a18-4a7c-a0cd-c2fc13473410
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=18_000_000 +rng_srate_value=5 +accelerate_cold_power_up_time=3 +accelerate_regulators_power_up_time=2 +sw_ build_device=sim_dv +sw_images=edn_auto_mode:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=520808838 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ= chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_edn_a uto_mode.520808838
Directory	/workspace/2.chip_sw_edn_auto_mode/latest

Test location	/workspace/coverage/default/2.chip_sw_edn_boot_mode.487613608
Short name	T110
Test name
Test status
Simulation time	2983768508 ps
CPU time	595.14 seconds
Started	Aug 14 06:04:01 PM PDT 24
Finished	Aug 14 06:13:57 PM PDT 24
Peak memory	610768 kb
Host	smart-e0dcf81d-d28f-4083-8eac-b7e6fbef8fec
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=18_000_000 +rng_srate_value=5 +accelerate_cold_power_up_time=3 +accelerate_regulators_power_up_time=2 +sw_ build_device=sim_dv +sw_images=edn_boot_mode:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=487613608 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ= chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_edn_b oot_mode.487613608
Directory	/workspace/2.chip_sw_edn_boot_mode/latest

Test location	/workspace/coverage/default/2.chip_sw_edn_entropy_reqs_jitter.2922234599
Short name	T961
Test name
Test status
Simulation time	8010141264 ps
CPU time	1217.38 seconds
Started	Aug 14 06:05:45 PM PDT 24
Finished	Aug 14 06:26:03 PM PDT 24
Peak memory	611360 kb
Host	smart-9734ef2f-ada5-463d-8a73-155e50dfd218
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=15000000 +rng_srate_value_min=15 +rng_srate_value_max=30 +en_jitter=1 +sw_build_device=sim_dv +sw_images=e ntropy_src_edn_reqs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2922234599 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_edn_entropy_reqs_jitter.2922234599
Directory	/workspace/2.chip_sw_edn_entropy_reqs_jitter/latest

Test location	/workspace/coverage/default/2.chip_sw_edn_kat.3427894
Short name	T403
Test name
Test status
Simulation time	3651736030 ps
CPU time	760.52 seconds
Started	Aug 14 06:04:00 PM PDT 24
Finished	Aug 14 06:16:41 PM PDT 24
Peak memory	617200 kb
Host	smart-a9e81061-cfef-4b0d-9e1a-b362e7971eb4
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=18_000_000 +rng_srate_value=5 +disable_assert_edn_output_diff_from_prev=1 +accelerate_cold_power_up_time=3 +accelerate_regulators_power_up_time=2 +sw_build_device=sim_dv +sw_images=edn_kat:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3427894 -assert nopostproc +UVM_TE STNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_lo g /dev/null -cm_name 2.chip_sw_edn_kat.3427894
Directory	/workspace/2.chip_sw_edn_kat/latest

Test location	/workspace/coverage/default/2.chip_sw_edn_sw_mode.2831718181
Short name	T999
Test name
Test status
Simulation time	9973820292 ps
CPU time	2035.43 seconds
Started	Aug 14 06:03:43 PM PDT 24
Finished	Aug 14 06:37:39 PM PDT 24
Peak memory	610764 kb
Host	smart-293917d3-c2d1-4bdd-bbf0-3267cc00fb80
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=edn_sw_mode:1:new_rules,test_rom:0 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2831718181 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/ default.vdb -cm_log /dev/null -cm_name 2.chip_sw_edn_sw_mode.2831718181
Directory	/workspace/2.chip_sw_edn_sw_mode/latest

Test location	/workspace/coverage/default/2.chip_sw_entropy_src_ast_rng_req.3942461255
Short name	T1000
Test name
Test status
Simulation time	2251611310 ps
CPU time	197.99 seconds
Started	Aug 14 06:03:24 PM PDT 24
Finished	Aug 14 06:06:42 PM PDT 24
Peak memory	609904 kb
Host	smart-39454109-7c61-48bb-a4d7-e030da47da98
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=15_000_000 +sw_build_device=sim_dv +sw_images=entropy_src_ast_rng_req_test:1:new_rules,test_rom:0 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39 42461255 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_entropy_src_ast_rng_req.3942461255
Directory	/workspace/2.chip_sw_entropy_src_ast_rng_req/latest

Test location	/workspace/coverage/default/2.chip_sw_entropy_src_csrng.2497712740
Short name	T132
Test name
Test status
Simulation time	5887333160 ps
CPU time	1275.38 seconds
Started	Aug 14 06:06:22 PM PDT 24
Finished	Aug 14 06:27:38 PM PDT 24
Peak memory	611004 kb
Host	smart-56d767f8-856f-464c-aa88-272713874d1a
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=50_000_000 +rng_srate_value_min=15 +rng_srate_value_max=30 +sw_build_device=sim_dv +sw_images=entropy_src_ csrng_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2497712740 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_entropy_src_csrng.2497712740
Directory	/workspace/2.chip_sw_entropy_src_csrng/latest

Test location	/workspace/coverage/default/2.chip_sw_entropy_src_kat_test.3388655392
Short name	T632
Test name
Test status
Simulation time	3020967600 ps
CPU time	297.32 seconds
Started	Aug 14 06:02:52 PM PDT 24
Finished	Aug 14 06:07:50 PM PDT 24
Peak memory	610428 kb
Host	smart-b9b08e33-f90c-4dcc-b900-93915b04ea63
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=entropy_src_kat_test:1:new_rules,test_rom:0 +cdc_instrumenta tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3388655392 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/ coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_entropy_src_kat_test.3388655392
Directory	/workspace/2.chip_sw_entropy_src_kat_test/latest

Test location	/workspace/coverage/default/2.chip_sw_entropy_src_smoketest.1127156415
Short name	T725
Test name
Test status
Simulation time	3832482006 ps
CPU time	651.57 seconds
Started	Aug 14 06:10:42 PM PDT 24
Finished	Aug 14 06:21:34 PM PDT 24
Peak memory	610516 kb
Host	smart-e5cbbd3b-04f0-4e9e-8bf0-39fd4ccf3345
User	root
Command	/workspace/default/simv +rng_srate_value_min=15 +rng_srate_value_max=30 +sw_build_device=sim_dv +sw_images=entropy_src_smoketest:1:new_rules,test_rom: 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand om_seed=1127156415 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_entropy_src_smoketest.1127156415
Directory	/workspace/2.chip_sw_entropy_src_smoketest/latest

Test location	/workspace/coverage/default/2.chip_sw_example_concurrency.1053477995
Short name	T960
Test name
Test status
Simulation time	3176496560 ps
CPU time	263.59 seconds
Started	Aug 14 05:57:09 PM PDT 24
Finished	Aug 14 06:01:33 PM PDT 24
Peak memory	610356 kb
Host	smart-52e328c3-92af-4b57-9670-21401f3a2954
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=example_concurrency_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1053477995 -assert nopostproc +UVM_TE STNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_lo g /dev/null -cm_name 2.chip_sw_example_concurrency.1053477995
Directory	/workspace/2.chip_sw_example_concurrency/latest

Test location	/workspace/coverage/default/2.chip_sw_example_flash.2878570862
Short name	T748
Test name
Test status
Simulation time	3478008100 ps
CPU time	191.94 seconds
Started	Aug 14 05:57:27 PM PDT 24
Finished	Aug 14 06:00:39 PM PDT 24
Peak memory	610308 kb
Host	smart-899b4c56-7f15-41fe-8932-01af9cf4489e
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=example_test_from_flash:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2878570862 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_example_flash.2878570862
Directory	/workspace/2.chip_sw_example_flash/latest

Test location	/workspace/coverage/default/2.chip_sw_example_manufacturer.1910382191
Short name	T691
Test name
Test status
Simulation time	2620296542 ps
CPU time	229.39 seconds
Started	Aug 14 05:57:28 PM PDT 24
Finished	Aug 14 06:01:17 PM PDT 24
Peak memory	610296 kb
Host	smart-329ca355-2029-4dfd-bf6f-2eab9b6c7bac
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=example_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1910382191 -assert nopostproc +UVM_TESTNAME=chip_ base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_example_manufacturer.1910382191
Directory	/workspace/2.chip_sw_example_manufacturer/latest

Test location	/workspace/coverage/default/2.chip_sw_example_rom.874016898
Short name	T820
Test name
Test status
Simulation time	2306849884 ps
CPU time	125.08 seconds
Started	Aug 14 05:55:17 PM PDT 24
Finished	Aug 14 05:57:22 PM PDT 24
Peak memory	610016 kb
Host	smart-fa682005-5476-4fb0-953c-2d517f159217
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=example_test_from_rom:0:test_in_rom:new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=874016898 -assert nopostproc +UVM_TESTN AME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log / dev/null -cm_name 2.chip_sw_example_rom.874016898
Directory	/workspace/2.chip_sw_example_rom/latest

Test location	/workspace/coverage/default/2.chip_sw_exit_test_unlocked_bootstrap.1073990304
Short name	T790
Test name
Test status
Simulation time	57081447180 ps
CPU time	9648.15 seconds
Started	Aug 14 05:56:48 PM PDT 24
Finished	Aug 14 08:37:37 PM PDT 24
Peak memory	625276 kb
Host	smart-e00221ce-be82-4be8-ae69-786f042402b2
User	root
Command	/workspace/default/simv +flash_program_latency=5 +sw_test_timeout_ns=150_000_000 +sw_build_device=sim_dv +sw_images=exit_test_unlocked_bootstrap:1:new _rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/s im.tcl +ntb_random_seed=1073990304 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_exit_test_unlocked_bootstrap_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_exit_test_unlocked_bootstrap.1073990304
Directory	/workspace/2.chip_sw_exit_test_unlocked_bootstrap/latest

Test location	/workspace/coverage/default/2.chip_sw_flash_crash_alert.707539618
Short name	T650
Test name
Test status
Simulation time	5700328840 ps
CPU time	539.6 seconds
Started	Aug 14 06:07:56 PM PDT 24
Finished	Aug 14 06:16:56 PM PDT 24
Peak memory	611952 kb
Host	smart-3688baf1-589a-48ba-a814-fa69a96259f2
User	root
Command	/workspace/default/simv +test_timeout_ns=8_000_000 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1: new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tool s/sim.tcl +ntb_random_seed=707539618 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_flash_host_gnt_err_inj_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_flash_crash_alert.707539618
Directory	/workspace/2.chip_sw_flash_crash_alert/latest

Test location	/workspace/coverage/default/2.chip_sw_flash_ctrl_access.2975280405
Short name	T868
Test name
Test status
Simulation time	5037701912 ps
CPU time	1076.57 seconds
Started	Aug 14 06:00:47 PM PDT 24
Finished	Aug 14 06:18:44 PM PDT 24
Peak memory	610292 kb
Host	smart-f10fe4e1-26ab-4e0d-90e4-635910da1afc
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=flash_ctrl_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2975280405 -assert nopostproc +UVM_TESTNAME=ch ip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu ll -cm_name 2.chip_sw_flash_ctrl_access.2975280405
Directory	/workspace/2.chip_sw_flash_ctrl_access/latest

Test location	/workspace/coverage/default/2.chip_sw_flash_ctrl_access_jitter_en.366918393
Short name	T819
Test name
Test status
Simulation time	6449320544 ps
CPU time	1070.01 seconds
Started	Aug 14 05:59:01 PM PDT 24
Finished	Aug 14 06:16:51 PM PDT 24
Peak memory	610848 kb
Host	smart-87f28bfc-369a-4304-9089-682294abec91
User	root
Command	/workspace/default/simv +en_jitter=1 +sw_build_device=sim_dv +sw_images=flash_ctrl_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=366918393 -assert nopostproc +UVM _TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm _log /dev/null -cm_name 2.chip_sw_flash_ctrl_access_jitter_en.366918393
Directory	/workspace/2.chip_sw_flash_ctrl_access_jitter_en/latest

Test location	/workspace/coverage/default/2.chip_sw_flash_ctrl_access_jitter_en_reduced_freq.2924584771
Short name	T731
Test name
Test status
Simulation time	7501050883 ps
CPU time	992.32 seconds
Started	Aug 14 06:08:47 PM PDT 24
Finished	Aug 14 06:25:20 PM PDT 24
Peak memory	610892 kb
Host	smart-5f94f9f9-37f1-4aea-97d4-fd37ac90b3cc
User	root
Command	/workspace/default/simv +en_jitter=1 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=flash_ctrl_test:1:new_rules,test_rom:0 +cdc_instrumentati on_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2924584771 - assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co verage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_flash_ctrl_access_jitter_en_reduced_freq.2924584771
Directory	/workspace/2.chip_sw_flash_ctrl_access_jitter_en_reduced_freq/latest

Test location	/workspace/coverage/default/2.chip_sw_flash_ctrl_clock_freqs.3611894296
Short name	T640
Test name
Test status
Simulation time	5505345634 ps
CPU time	1120.04 seconds
Started	Aug 14 06:00:03 PM PDT 24
Finished	Aug 14 06:18:46 PM PDT 24
Peak memory	610848 kb
Host	smart-e765c448-1490-43d0-869f-440035f2cbb2
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=flash_ctrl_clock_freqs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3611894296 -assert nopostproc +UVM _TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm _log /dev/null -cm_name 2.chip_sw_flash_ctrl_clock_freqs.3611894296
Directory	/workspace/2.chip_sw_flash_ctrl_clock_freqs/latest

Test location	/workspace/coverage/default/2.chip_sw_flash_ctrl_idle_low_power.1510596232
Short name	T375
Test name
Test status
Simulation time	3890594748 ps
CPU time	376.42 seconds
Started	Aug 14 05:58:08 PM PDT 24
Finished	Aug 14 06:04:25 PM PDT 24
Peak memory	610652 kb
Host	smart-e1e01519-ed6e-468f-bf79-d3acaf34f028
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=flash_ctrl_idle_low_power_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1510596232 -assert nopostproc + UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_flash_ctrl_idle_low_power.1510596232
Directory	/workspace/2.chip_sw_flash_ctrl_idle_low_power/latest

Test location	/workspace/coverage/default/2.chip_sw_flash_ctrl_lc_rw_en.2753031489
Short name	T429
Test name
Test status
Simulation time	6303320492 ps
CPU time	753.26 seconds
Started	Aug 14 05:59:28 PM PDT 24
Finished	Aug 14 06:12:01 PM PDT 24
Peak memory	611628 kb
Host	smart-605e0d46-6e2b-4eaa-9b03-2b4419bf0126
User	root
Command	/workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=flash_ctrl_lc_rw_en_test:1:new_rules,test_rom:0 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27 53031489 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_flash_ctrl_lc_rw_en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_flash_ctrl_lc_rw_en.2753031489
Directory	/workspace/2.chip_sw_flash_ctrl_lc_rw_en/latest

Test location	/workspace/coverage/default/2.chip_sw_flash_ctrl_mem_protection.416282870
Short name	T614
Test name
Test status
Simulation time	5751866250 ps
CPU time	1117.2 seconds
Started	Aug 14 06:07:11 PM PDT 24
Finished	Aug 14 06:25:49 PM PDT 24
Peak memory	610760 kb
Host	smart-2da2a910-e204-4627-9911-a7be20d60199
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=flash_ctrl_mem_protection_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=416282870 -assert nopostproc +U VM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb - cm_log /dev/null -cm_name 2.chip_sw_flash_ctrl_mem_protection.416282870
Directory	/workspace/2.chip_sw_flash_ctrl_mem_protection/latest

Test location	/workspace/coverage/default/2.chip_sw_flash_ctrl_ops.1200661014
Short name	T367
Test name
Test status
Simulation time	4470327032 ps
CPU time	686.01 seconds
Started	Aug 14 05:58:40 PM PDT 24
Finished	Aug 14 06:10:07 PM PDT 24
Peak memory	610980 kb
Host	smart-4272e503-8d1c-4726-a626-854e5f7188b7
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=50_000_000 +sw_build_device=sim_dv +sw_images=flash_ctrl_ops_test:1:new_rules,test_rom:0 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1200661014 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/c overage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_flash_ctrl_ops.1200661014
Directory	/workspace/2.chip_sw_flash_ctrl_ops/latest

Test location	/workspace/coverage/default/2.chip_sw_flash_ctrl_ops_jitter_en_reduced_freq.2621739608
Short name	T121
Test name
Test status
Simulation time	4837687201 ps
CPU time	798.5 seconds
Started	Aug 14 06:06:39 PM PDT 24
Finished	Aug 14 06:19:58 PM PDT 24
Peak memory	610908 kb
Host	smart-e4b1eded-1e15-4d08-9a2b-053fc18af1c4
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=50_000_000 +en_jitter=1 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=flash_ctrl_ops_test:1:new_ rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si m.tcl +ntb_random_seed=2621739608 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_flash_ctrl_ops_jitter_en_reduced_freq.2621739608
Directory	/workspace/2.chip_sw_flash_ctrl_ops_jitter_en_reduced_freq/latest

Test location	/workspace/coverage/default/2.chip_sw_flash_ctrl_write_clear.1812177187
Short name	T735
Test name
Test status
Simulation time	3812943592 ps
CPU time	399.02 seconds
Started	Aug 14 06:05:32 PM PDT 24
Finished	Aug 14 06:12:12 PM PDT 24
Peak memory	609916 kb
Host	smart-5edeef38-d8f4-475a-9804-0aa158c266e8
User	root
Command	/workspace/default/simv +test_timeout_ns=8_000_000 +sw_build_device=sim_dv +sw_images=flash_ctrl_write_clear_test:1:new_rules,test_rom:0 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1812177 187 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ce/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_flash_ctrl_write_clear.1812177187
Directory	/workspace/2.chip_sw_flash_ctrl_write_clear/latest

Test location	/workspace/coverage/default/2.chip_sw_flash_init.3125243521
Short name	T726
Test name
Test status
Simulation time	26461850700 ps
CPU time	2370.04 seconds
Started	Aug 14 05:59:49 PM PDT 24
Finished	Aug 14 06:39:20 PM PDT 24
Peak memory	615140 kb
Host	smart-bca8800a-a2fc-4b6d-9d39-b175e2f54ff9
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=25_000_000 +sw_build_device=sim_dv +sw_images=flash_init_test:0:test_in_rom:new_rules +cdc_instrumentation _enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3125243521 -as sert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_flash_init_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac e/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_flash_init.3125243521
Directory	/workspace/2.chip_sw_flash_init/latest

Test location	/workspace/coverage/default/2.chip_sw_flash_init_reduced_freq.2949388467
Short name	T936
Test name
Test status
Simulation time	27309054899 ps
CPU time	2512.42 seconds
Started	Aug 14 06:05:53 PM PDT 24
Finished	Aug 14 06:47:47 PM PDT 24
Peak memory	614468 kb
Host	smart-8afc4a7c-4ba3-4944-a3d3-625781a32140
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=25_000_000 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=flash_init_test:0:test_in_rom:new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=2949388467 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_flash_init_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_flash_init_reduced_freq.2949388467
Directory	/workspace/2.chip_sw_flash_init_reduced_freq/latest

Test location	/workspace/coverage/default/2.chip_sw_flash_scrambling_smoketest.2278625088
Short name	T166
Test name
Test status
Simulation time	3462162060 ps
CPU time	267.69 seconds
Started	Aug 14 06:11:30 PM PDT 24
Finished	Aug 14 06:15:58 PM PDT 24
Peak memory	610492 kb
Host	smart-025910a3-2849-4431-80ee-4434c602471f
User	root
Command	/workspace/default/simv +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=flash_scrambling_smoketest:1:new_rules,flash_scrambling_smoket est_otp_img_rma:4,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=2278625088 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_flash_scrambling_smoketest.2278625088
Directory	/workspace/2.chip_sw_flash_scrambling_smoketest/latest

Test location	/workspace/coverage/default/2.chip_sw_gpio_smoketest.2852852421
Short name	T324
Test name
Test status
Simulation time	2209326430 ps
CPU time	278.14 seconds
Started	Aug 14 06:07:41 PM PDT 24
Finished	Aug 14 06:12:19 PM PDT 24
Peak memory	612400 kb
Host	smart-f7cf7190-c83e-4363-b200-3df290f16be3
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=gpio_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2852852421 -assert nopostproc +UVM_TESTNAME=chi p_base_test +UVM_TEST_SEQ=chip_sw_gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 2.chip_sw_gpio_smoketest.2852852421
Directory	/workspace/2.chip_sw_gpio_smoketest/latest

Test location	/workspace/coverage/default/2.chip_sw_hmac_enc.1637645239
Short name	T753
Test name
Test status
Simulation time	3463604000 ps
CPU time	285.73 seconds
Started	Aug 14 06:03:54 PM PDT 24
Finished	Aug 14 06:08:40 PM PDT 24
Peak memory	610320 kb
Host	smart-0cb5db32-19e4-496f-bda1-a139e3c17977
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=hmac_enc_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1637645239 -assert nopostproc +UVM_TESTNAME=chip _base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_hmac_enc.1637645239
Directory	/workspace/2.chip_sw_hmac_enc/latest

Test location	/workspace/coverage/default/2.chip_sw_hmac_enc_idle.2393943685
Short name	T865
Test name
Test status
Simulation time	3149962178 ps
CPU time	334.49 seconds
Started	Aug 14 06:03:32 PM PDT 24
Finished	Aug 14 06:09:06 PM PDT 24
Peak memory	610484 kb
Host	smart-047e7e0e-2f90-457b-bb2e-89c8b7d676e1
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=hmac_enc_idle_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2393943685 -assert nopostproc +UVM_TESTNAME =chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 2.chip_sw_hmac_enc_idle.2393943685
Directory	/workspace/2.chip_sw_hmac_enc_idle/latest

Test location	/workspace/coverage/default/2.chip_sw_hmac_enc_jitter_en.1225340624
Short name	T179
Test name
Test status
Simulation time	2395377416 ps
CPU time	309.67 seconds
Started	Aug 14 06:04:01 PM PDT 24
Finished	Aug 14 06:09:11 PM PDT 24
Peak memory	610512 kb
Host	smart-42dbb034-9cf9-4102-a15f-eca754e9e950
User	root
Command	/workspace/default/simv +en_jitter=1 +sw_build_device=sim_dv +sw_images=hmac_enc_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1225340624 -assert nopostproc +UVM_ TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_ log /dev/null -cm_name 2.chip_sw_hmac_enc_jitter_en.1225340624
Directory	/workspace/2.chip_sw_hmac_enc_jitter_en/latest

Test location	/workspace/coverage/default/2.chip_sw_hmac_enc_jitter_en_reduced_freq.1232999406
Short name	T946
Test name
Test status
Simulation time	2609873474 ps
CPU time	257.11 seconds
Started	Aug 14 06:06:21 PM PDT 24
Finished	Aug 14 06:10:38 PM PDT 24
Peak memory	610588 kb
Host	smart-6a94c2af-d9cf-485f-b3d7-2514354b453d
User	root
Command	/workspace/default/simv +en_jitter=1 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=hmac_enc_test:1:new_rules,test_rom:0 +cdc_instrumentation _enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1232999406 -as sert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove rage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_hmac_enc_jitter_en_reduced_freq.1232999406
Directory	/workspace/2.chip_sw_hmac_enc_jitter_en_reduced_freq/latest

Test location	/workspace/coverage/default/2.chip_sw_hmac_multistream.2035230637
Short name	T741
Test name
Test status
Simulation time	9325033656 ps
CPU time	2390.47 seconds
Started	Aug 14 06:03:26 PM PDT 24
Finished	Aug 14 06:43:16 PM PDT 24
Peak memory	610856 kb
Host	smart-b104c8fd-da81-40b9-b1f7-9b91e969be10
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=hmac_multistream_functest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2035230637 -assert nopostproc +UVM_T ESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l og /dev/null -cm_name 2.chip_sw_hmac_multistream.2035230637
Directory	/workspace/2.chip_sw_hmac_multistream/latest

Test location	/workspace/coverage/default/2.chip_sw_hmac_oneshot.2424657677
Short name	T763
Test name
Test status
Simulation time	3438354580 ps
CPU time	381.39 seconds
Started	Aug 14 06:03:15 PM PDT 24
Finished	Aug 14 06:09:37 PM PDT 24
Peak memory	610352 kb
Host	smart-908d0bd7-5237-483c-8d73-49a646a38492
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=hmac_functest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2424657677 -assert nopostproc +UVM_TESTNAME=chip _base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_hmac_oneshot.2424657677
Directory	/workspace/2.chip_sw_hmac_oneshot/latest

Test location	/workspace/coverage/default/2.chip_sw_hmac_smoketest.2680093805
Short name	T180
Test name
Test status
Simulation time	2928136300 ps
CPU time	442.12 seconds
Started	Aug 14 06:11:25 PM PDT 24
Finished	Aug 14 06:18:47 PM PDT 24
Peak memory	610496 kb
Host	smart-a1e60021-2b7a-4c9c-8e7f-f37c3f435552
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=hmac_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2680093805 -assert nopostproc +UVM_TESTNAME=chi p_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul l -cm_name 2.chip_sw_hmac_smoketest.2680093805
Directory	/workspace/2.chip_sw_hmac_smoketest/latest

Test location	/workspace/coverage/default/2.chip_sw_i2c_device_tx_rx.1624674684
Short name	T362
Test name
Test status
Simulation time	3732292936 ps
CPU time	549.45 seconds
Started	Aug 14 05:58:32 PM PDT 24
Finished	Aug 14 06:07:43 PM PDT 24
Peak memory	611604 kb
Host	smart-ff82f3fd-0d6e-4d54-984c-b53f9f1b2c4f
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=i2c_device_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1624674684 -assert nopostproc +UVM_TESTN AME=chip_base_test +UVM_TEST_SEQ=chip_sw_i2c_device_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v db -cm_log /dev/null -cm_name 2.chip_sw_i2c_device_tx_rx.1624674684
Directory	/workspace/2.chip_sw_i2c_device_tx_rx/latest

Test location	/workspace/coverage/default/2.chip_sw_i2c_host_tx_rx.3532414520
Short name	T804
Test name
Test status
Simulation time	4679269342 ps
CPU time	888.43 seconds
Started	Aug 14 05:58:54 PM PDT 24
Finished	Aug 14 06:13:42 PM PDT 24
Peak memory	610416 kb
Host	smart-a3ff7c66-e7ce-46d5-98c1-59853ad62f0d
User	root
Command	/workspace/default/simv +i2c_idx=0 +sw_build_device=sim_dv +sw_images=i2c_host_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3532414520 -assert nopostproc + UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_i2c_host_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de fault.vdb -cm_log /dev/null -cm_name 2.chip_sw_i2c_host_tx_rx.3532414520
Directory	/workspace/2.chip_sw_i2c_host_tx_rx/latest

Test location	/workspace/coverage/default/2.chip_sw_i2c_host_tx_rx_idx1.705480966
Short name	T893
Test name
Test status
Simulation time	4644118820 ps
CPU time	721.85 seconds
Started	Aug 14 05:59:06 PM PDT 24
Finished	Aug 14 06:11:08 PM PDT 24
Peak memory	610416 kb
Host	smart-ae9c0983-b29b-4036-8fd8-a14dc84be336
User	root
Command	/workspace/default/simv +i2c_idx=1 +sw_build_device=sim_dv +sw_images=i2c_host_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=705480966 -assert nopostproc +U VM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_i2c_host_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def ault.vdb -cm_log /dev/null -cm_name 2.chip_sw_i2c_host_tx_rx_idx1.705480966
Directory	/workspace/2.chip_sw_i2c_host_tx_rx_idx1/latest

Test location	/workspace/coverage/default/2.chip_sw_i2c_host_tx_rx_idx2.1195804873
Short name	T241
Test name
Test status
Simulation time	4688179800 ps
CPU time	777.78 seconds
Started	Aug 14 05:59:05 PM PDT 24
Finished	Aug 14 06:12:03 PM PDT 24
Peak memory	610764 kb
Host	smart-c006cb5b-c029-40fc-9346-07f70edd7cbf
User	root
Command	/workspace/default/simv +i2c_idx=2 +sw_build_device=sim_dv +sw_images=i2c_host_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1195804873 -assert nopostproc + UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_i2c_host_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de fault.vdb -cm_log /dev/null -cm_name 2.chip_sw_i2c_host_tx_rx_idx2.1195804873
Directory	/workspace/2.chip_sw_i2c_host_tx_rx_idx2/latest

Test location	/workspace/coverage/default/2.chip_sw_inject_scramble_seed.3878279337
Short name	T953
Test name
Test status
Simulation time	64710991223 ps
CPU time	11915.3 seconds
Started	Aug 14 05:57:12 PM PDT 24
Finished	Aug 14 09:15:49 PM PDT 24
Peak memory	625296 kb
Host	smart-dc482cdc-0bc8-4f92-bc8a-8c7b0dae10f8
User	root
Command	/workspace/default/simv +lc_at_prod=1 +flash_program_latency=5 +sw_test_timeout_ns=150_000_000 +sw_build_device=sim_dv +sw_images=inject_scramble_seed :1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=3878279337 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_inject_scramble_seed_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_inject_scramble_seed.3878279337
Directory	/workspace/2.chip_sw_inject_scramble_seed/latest

Test location	/workspace/coverage/default/2.chip_sw_keymgr_key_derivation.2145332027
Short name	T1034
Test name
Test status
Simulation time	9597893000 ps
CPU time	2104.6 seconds
Started	Aug 14 06:03:49 PM PDT 24
Finished	Aug 14 06:38:54 PM PDT 24
Peak memory	618400 kb
Host	smart-ac7dcf7a-620a-46b7-afc3-2705d47e71d0
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=20_000_000 +sw_build_device=sim_dv +sw_images=keymgr_key_derivation_test:1:new_rules,test_rom:0 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2145 332027 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_keymgr_key_derivation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_keymgr_key_derivation.2145332027
Directory	/workspace/2.chip_sw_keymgr_key_derivation/latest

Test location	/workspace/coverage/default/2.chip_sw_keymgr_key_derivation_jitter_en.1902318974
Short name	T822
Test name
Test status
Simulation time	8643249353 ps
CPU time	1378.95 seconds
Started	Aug 14 06:03:52 PM PDT 24
Finished	Aug 14 06:26:51 PM PDT 24
Peak memory	618256 kb
Host	smart-111ad408-77e1-40db-bf41-e4dd47412290
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=20_000_000 +en_jitter=1 +sw_build_device=sim_dv +sw_images=keymgr_key_derivation_test:1:new_rules,test_rom :0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=1902318974 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_keymgr_key_derivation_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_keymgr_key_derivation_jitter_en.1902318974
Directory	/workspace/2.chip_sw_keymgr_key_derivation_jitter_en/latest

Test location	/workspace/coverage/default/2.chip_sw_keymgr_key_derivation_jitter_en_reduced_freq.1583898278
Short name	T966
Test name
Test status
Simulation time	9293240808 ps
CPU time	1355.87 seconds
Started	Aug 14 06:06:19 PM PDT 24
Finished	Aug 14 06:28:55 PM PDT 24
Peak memory	617212 kb
Host	smart-5da3964d-1b69-4ee8-975d-dc6f96ae56bf
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=20_000_000 +en_jitter=1 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=keymgr_key_derivation_test :1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=1583898278 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_keymgr_key_derivation_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_keymgr_key_derivation_jitter_en _reduced_freq.1583898278
Directory	/workspace/2.chip_sw_keymgr_key_derivation_jitter_en_reduced_freq/latest

Test location	/workspace/coverage/default/2.chip_sw_keymgr_key_derivation_prod.388474712
Short name	T1033
Test name
Test status
Simulation time	8163341352 ps
CPU time	1525.34 seconds
Started	Aug 14 06:03:47 PM PDT 24
Finished	Aug 14 06:29:13 PM PDT 24
Peak memory	618508 kb
Host	smart-ddfba353-8454-4651-87a0-c20189e9260c
User	root
Command	/workspace/default/simv +lc_at_prod=1 +sw_test_timeout_ns=20_000_000 +sw_build_device=sim_dv +sw_images=keymgr_key_derivation_test:1:new_rules,test_ro m:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=388474712 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_keymgr_key_derivation_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_keymgr_key_derivation_prod.388474712
Directory	/workspace/2.chip_sw_keymgr_key_derivation_prod/latest

Test location	/workspace/coverage/default/2.chip_sw_keymgr_sideload_aes.335545549
Short name	T331
Test name
Test status
Simulation time	7473741420 ps
CPU time	1700.64 seconds
Started	Aug 14 06:05:29 PM PDT 24
Finished	Aug 14 06:33:51 PM PDT 24
Peak memory	611468 kb
Host	smart-ef027e6e-f1f2-4821-a2d5-fe0472cc7d39
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=20_000_000 +sw_build_device=sim_dv +sw_images=keymgr_sideload_aes_test:1:new_rules,test_rom:0 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=335545 549 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_keymgr_sideload_aes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_keymgr_sideload_aes.335545549
Directory	/workspace/2.chip_sw_keymgr_sideload_aes/latest

Test location	/workspace/coverage/default/2.chip_sw_keymgr_sideload_kmac.3863966498
Short name	T823
Test name
Test status
Simulation time	6329087326 ps
CPU time	1324.08 seconds
Started	Aug 14 06:03:57 PM PDT 24
Finished	Aug 14 06:26:02 PM PDT 24
Peak memory	612012 kb
Host	smart-aa98b912-e6f7-4d1c-8b49-e89ce7d02b1e
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=20_000_000 +sw_build_device=sim_dv +sw_images=keymgr_sideload_kmac_test:1:new_rules,test_rom:0 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38639 66498 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_keymgr_sideload_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_keymgr_sideload_kmac.3863966498
Directory	/workspace/2.chip_sw_keymgr_sideload_kmac/latest

Test location	/workspace/coverage/default/2.chip_sw_keymgr_sideload_otbn.2403280703
Short name	T329
Test name
Test status
Simulation time	16253286456 ps
CPU time	3915.36 seconds
Started	Aug 14 06:03:24 PM PDT 24
Finished	Aug 14 07:08:40 PM PDT 24
Peak memory	611592 kb
Host	smart-9b952d3c-6ecd-4d61-ada4-c7a86fcff488
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=20_000_000 +sw_build_device=sim_dv +sw_images=keymgr_sideload_otbn_test:1:new_rules,test_rom:0 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24032 80703 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_keymgr_sideload_otbn.2403280703
Directory	/workspace/2.chip_sw_keymgr_sideload_otbn/latest

Test location	/workspace/coverage/default/2.chip_sw_kmac_app_rom.2482923758
Short name	T168
Test name
Test status
Simulation time	2707852472 ps
CPU time	264.35 seconds
Started	Aug 14 06:04:05 PM PDT 24
Finished	Aug 14 06:08:30 PM PDT 24
Peak memory	610344 kb
Host	smart-dd9e692e-21c1-49b3-bc40-3c3e7921fd1e
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=kmac_app_rom_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2482923758 -assert nopostproc +UVM_TESTNAME= chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/ null -cm_name 2.chip_sw_kmac_app_rom.2482923758
Directory	/workspace/2.chip_sw_kmac_app_rom/latest

Test location	/workspace/coverage/default/2.chip_sw_kmac_entropy.3359389390
Short name	T737
Test name
Test status
Simulation time	2681910402 ps
CPU time	248.39 seconds
Started	Aug 14 05:59:25 PM PDT 24
Finished	Aug 14 06:03:33 PM PDT 24
Peak memory	610364 kb
Host	smart-d7ec5fc9-81de-4f05-a7b4-3157b59ae296
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=kmac_entropy_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3359389390 -assert nopostproc +UVM_TESTNAME= chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/ null -cm_name 2.chip_sw_kmac_entropy.3359389390
Directory	/workspace/2.chip_sw_kmac_entropy/latest

Test location	/workspace/coverage/default/2.chip_sw_kmac_idle.4152116885
Short name	T1012
Test name
Test status
Simulation time	3027358400 ps
CPU time	308.98 seconds
Started	Aug 14 06:04:56 PM PDT 24
Finished	Aug 14 06:10:05 PM PDT 24
Peak memory	610420 kb
Host	smart-b66a3a6e-32bc-4f28-9e64-548c84d651a4
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=kmac_idle_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4152116885 -assert nopostproc +UVM_TESTNAME=chi p_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul l -cm_name 2.chip_sw_kmac_idle.4152116885
Directory	/workspace/2.chip_sw_kmac_idle/latest

Test location	/workspace/coverage/default/2.chip_sw_kmac_mode_cshake.3558010719
Short name	T743
Test name
Test status
Simulation time	3324717840 ps
CPU time	336.75 seconds
Started	Aug 14 06:05:04 PM PDT 24
Finished	Aug 14 06:10:42 PM PDT 24
Peak memory	610204 kb
Host	smart-e03bd297-9742-4950-b66d-66dd8ca652bb
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=kmac_mode_cshake_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3558010719 -assert nopostproc +UVM_TESTN AME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log / dev/null -cm_name 2.chip_sw_kmac_mode_cshake.3558010719
Directory	/workspace/2.chip_sw_kmac_mode_cshake/latest

Test location	/workspace/coverage/default/2.chip_sw_kmac_mode_kmac.3089762908
Short name	T301
Test name
Test status
Simulation time	2976354548 ps
CPU time	323.77 seconds
Started	Aug 14 06:04:15 PM PDT 24
Finished	Aug 14 06:09:39 PM PDT 24
Peak memory	610348 kb
Host	smart-007fc303-2cb7-45e1-836a-b4a8555a92f1
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=kmac_mode_kmac_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3089762908 -assert nopostproc +UVM_TESTNAM E=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 2.chip_sw_kmac_mode_kmac.3089762908
Directory	/workspace/2.chip_sw_kmac_mode_kmac/latest

Test location	/workspace/coverage/default/2.chip_sw_kmac_mode_kmac_jitter_en.1116822143
Short name	T413
Test name
Test status
Simulation time	2968257459 ps
CPU time	292.54 seconds
Started	Aug 14 06:04:46 PM PDT 24
Finished	Aug 14 06:09:39 PM PDT 24
Peak memory	610480 kb
Host	smart-72b13fee-2183-4231-b713-5095334e3a5c
User	root
Command	/workspace/default/simv +en_jitter=1 +sw_build_device=sim_dv +sw_images=kmac_mode_kmac_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1116822143 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd b -cm_log /dev/null -cm_name 2.chip_sw_kmac_mode_kmac_jitter_en.1116822143
Directory	/workspace/2.chip_sw_kmac_mode_kmac_jitter_en/latest

Test location	/workspace/coverage/default/2.chip_sw_kmac_mode_kmac_jitter_en_reduced_freq.991309713
Short name	T718
Test name
Test status
Simulation time	2797881379 ps
CPU time	369.19 seconds
Started	Aug 14 06:06:27 PM PDT 24
Finished	Aug 14 06:12:37 PM PDT 24
Peak memory	609144 kb
Host	smart-49fb6d19-d4ba-480a-ad92-ecd2a53dc82b
User	root
Command	/workspace/default/simv +en_jitter=1 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=kmac_mode_kmac_test:1:new_rules,test_rom:0 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=99130971 3 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace /coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_kmac_mode_kmac_jitter_en_reduced_freq.991309713
Directory	/workspace/2.chip_sw_kmac_mode_kmac_jitter_en_reduced_freq/latest

Test location	/workspace/coverage/default/2.chip_sw_kmac_smoketest.1424697573
Short name	T909
Test name
Test status
Simulation time	3318733856 ps
CPU time	367.55 seconds
Started	Aug 14 06:10:45 PM PDT 24
Finished	Aug 14 06:16:53 PM PDT 24
Peak memory	609812 kb
Host	smart-8fb61714-a3b0-4634-84b8-3f7f659ae756
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=kmac_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1424697573 -assert nopostproc +UVM_TESTNAME=chi p_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul l -cm_name 2.chip_sw_kmac_smoketest.1424697573
Directory	/workspace/2.chip_sw_kmac_smoketest/latest

Test location	/workspace/coverage/default/2.chip_sw_lc_ctrl_otp_hw_cfg0.1665000305
Short name	T910
Test name
Test status
Simulation time	3455643200 ps
CPU time	370.13 seconds
Started	Aug 14 05:59:14 PM PDT 24
Finished	Aug 14 06:05:25 PM PDT 24
Peak memory	609888 kb
Host	smart-b00924f1-b538-4d49-82cf-65e02f7fada8
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=lc_ctrl_otp_hw_cfg0_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1665000305 -assert nopostproc +UVM_TE STNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_lo g /dev/null -cm_name 2.chip_sw_lc_ctrl_otp_hw_cfg0.1665000305
Directory	/workspace/2.chip_sw_lc_ctrl_otp_hw_cfg0/latest

Test location	/workspace/coverage/default/2.chip_sw_lc_ctrl_program_error.376322569
Short name	T214
Test name
Test status
Simulation time	4212322576 ps
CPU time	673.4 seconds
Started	Aug 14 06:05:25 PM PDT 24
Finished	Aug 14 06:16:39 PM PDT 24
Peak memory	611480 kb
Host	smart-28c1d2a3-1b33-4ff6-bf60-f5bf81686967
User	root
Command	/workspace/default/simv +en_scb=0 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=lc_ctrl_program_error:1:new_rules,test_rom:0 + cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_ seed=376322569 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_program_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_lc_ctrl_program_error.376322569
Directory	/workspace/2.chip_sw_lc_ctrl_program_error/latest

Test location	/workspace/coverage/default/2.chip_sw_lc_ctrl_rand_to_scrap.2025220958
Short name	T113
Test name
Test status
Simulation time	3653713259 ps
CPU time	147.46 seconds
Started	Aug 14 05:58:47 PM PDT 24
Finished	Aug 14 06:01:14 PM PDT 24
Peak memory	620540 kb
Host	smart-031401cc-4fd9-4836-9a22-c87c725a5a70
User	root
Command	/workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=lc_ctrl_scrap_test:1:new_rules,test_rom:0 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20252209 58 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_scrap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_lc_ctrl_rand_to_scrap.2025220958
Directory	/workspace/2.chip_sw_lc_ctrl_rand_to_scrap/latest

Test location	/workspace/coverage/default/2.chip_sw_lc_ctrl_transition.197575422
Short name	T717
Test name
Test status
Simulation time	12585139050 ps
CPU time	961.16 seconds
Started	Aug 14 05:59:14 PM PDT 24
Finished	Aug 14 06:15:16 PM PDT 24
Peak memory	622140 kb
Host	smart-d78b2dc6-c959-43d1-abf5-06e6413174ac
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=lc_ctrl_transition_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=197575422 -assert nopostproc +UVM_TEST NAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_transition_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul t.vdb -cm_log /dev/null -cm_name 2.chip_sw_lc_ctrl_transition.197575422
Directory	/workspace/2.chip_sw_lc_ctrl_transition/latest

Test location	/workspace/coverage/default/2.chip_sw_lc_ctrl_volatile_raw_unlock.1835653678
Short name	T437
Test name
Test status
Simulation time	2515043272 ps
CPU time	101.54 seconds
Started	Aug 14 05:58:17 PM PDT 24
Finished	Aug 14 05:59:58 PM PDT 24
Peak memory	622428 kb
Host	smart-1e5eb191-16a4-453e-a5f7-787eba3a1f07
User	root
Command	/workspace/default/simv +use_otp_image=OtpTypeLcStRaw +exp_volatile_raw_unlock_en=0 +sw_build_device=sim_dv +sw_images=lc_ctrl_volatile_raw_unlock_tes t:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/ tools/sim.tcl +ntb_random_seed=1835653678 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_volatile_raw_unlock_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_lc_ctrl_volatile_raw_unlock.1835653678
Directory	/workspace/2.chip_sw_lc_ctrl_volatile_raw_unlock/latest

Test location	/workspace/coverage/default/2.chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz.3271668458
Short name	T945
Test name
Test status
Simulation time	2610675393 ps
CPU time	124.82 seconds
Started	Aug 14 06:00:15 PM PDT 24
Finished	Aug 14 06:02:20 PM PDT 24
Peak memory	617960 kb
Host	smart-f48aa844-4ad6-489d-82f4-f09f8b74ad22
User	root
Command	/workspace/default/simv +use_otp_image=OtpTypeLcStRaw +chip_clock_source=ChipClockSourceExternal48Mhz +exp_volatile_raw_unlock_en=0 +sw_build_device=s im_dv +sw_images=lc_ctrl_volatile_raw_unlock_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3271668458 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TES T_SEQ=chip_sw_lc_volatile_raw_unlock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz.3271668458
Directory	/workspace/2.chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz/latest

Test location	/workspace/coverage/default/2.chip_sw_lc_walkthrough_dev.54077757
Short name	T926
Test name
Test status
Simulation time	45976979635 ps
CPU time	5295.62 seconds
Started	Aug 14 06:00:20 PM PDT 24
Finished	Aug 14 07:28:36 PM PDT 24
Peak memory	617336 kb
Host	smart-751882a2-7adf-48c9-b934-f9c4201258d2
User	root
Command	/workspace/default/simv +flash_program_latency=5 +use_otp_image=OtpTypeLcStRaw +dest_dec_state=DecLcStDev +sw_test_timeout_ns=200_000_000 +sw_build_de vice=sim_dv +sw_images=lc_walkthrough_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=54077757 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chi p_sw_lc_walkthrough_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_s w_lc_walkthrough_dev.54077757
Directory	/workspace/2.chip_sw_lc_walkthrough_dev/latest

Test location	/workspace/coverage/default/2.chip_sw_lc_walkthrough_prodend.2416739929
Short name	T692
Test name
Test status
Simulation time	8923941435 ps
CPU time	1208.35 seconds
Started	Aug 14 06:00:35 PM PDT 24
Finished	Aug 14 06:20:44 PM PDT 24
Peak memory	624796 kb
Host	smart-6bf028be-8412-4546-bfae-155eaf717cfc
User	root
Command	/workspace/default/simv +flash_program_latency=5 +use_otp_image=OtpTypeLcStRaw +dest_dec_state=DecLcStProdEnd +sw_build_device=sim_dv +sw_images=lc_wa lkthrough_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2416739929 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_walkthrough_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_lc_walkthrough_prodend.2416739929
Directory	/workspace/2.chip_sw_lc_walkthrough_prodend/latest

Test location	/workspace/coverage/default/2.chip_sw_lc_walkthrough_rma.3163836237
Short name	T757
Test name
Test status
Simulation time	46906057941 ps
CPU time	5201.47 seconds
Started	Aug 14 06:00:16 PM PDT 24
Finished	Aug 14 07:26:58 PM PDT 24
Peak memory	620164 kb
Host	smart-8f468efa-3503-4b17-ba11-38fa86a805d8
User	root
Command	/workspace/default/simv +use_otp_image=OtpTypeLcStRaw +dest_dec_state=DecLcStRma +flash_program_latency=5 +sw_test_timeout_ns=200_000_000 +sw_build_de vice=sim_dv +sw_images=lc_walkthrough_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3163836237 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=c hip_sw_lc_walkthrough_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip _sw_lc_walkthrough_rma.3163836237
Directory	/workspace/2.chip_sw_lc_walkthrough_rma/latest

Test location	/workspace/coverage/default/2.chip_sw_lc_walkthrough_testunlocks.405492032
Short name	T851
Test name
Test status
Simulation time	22640086069 ps
CPU time	1746.27 seconds
Started	Aug 14 06:00:51 PM PDT 24
Finished	Aug 14 06:29:58 PM PDT 24
Peak memory	620760 kb
Host	smart-18816785-f001-4ccc-9a35-74d58a404a9f
User	root
Command	/workspace/default/simv +use_otp_image=OtpTypeLcStRaw +dest_dec_state=DecLcStTestUnlock7 +sw_build_device=sim_dv +sw_images=lc_walkthrough_testunlocks _test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=405492032 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_walkthrough_testunlocks_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_lc_walkthrough_testunl ocks.405492032
Directory	/workspace/2.chip_sw_lc_walkthrough_testunlocks/latest

Test location	/workspace/coverage/default/2.chip_sw_otbn_ecdsa_op_irq.4099706287
Short name	T201
Test name
Test status
Simulation time	17020597790 ps
CPU time	3162.3 seconds
Started	Aug 14 06:05:02 PM PDT 24
Finished	Aug 14 06:57:45 PM PDT 24
Peak memory	610948 kb
Host	smart-44939116-11e5-4eb2-9126-9f375838e245
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=28_000_000 +rng_srate_value=30 +sw_build_device=sim_dv +sw_images=otbn_ecdsa_op_irq_test:1:new_rules,test_ rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ random_seed=4099706287 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_otbn_ecdsa_op_irq.4099706287
Directory	/workspace/2.chip_sw_otbn_ecdsa_op_irq/latest

Test location	/workspace/coverage/default/2.chip_sw_otbn_ecdsa_op_irq_jitter_en.825954272
Short name	T857
Test name
Test status
Simulation time	18839855542 ps
CPU time	2940.06 seconds
Started	Aug 14 06:02:28 PM PDT 24
Finished	Aug 14 06:51:28 PM PDT 24
Peak memory	611060 kb
Host	smart-d0160093-9e31-4481-a797-0b0c520be263
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=33_000_000 +rng_srate_value=30 +en_jitter=1 +sw_build_device=sim_dv +sw_images=otbn_ecdsa_op_irq_test:1:ne w_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/ sim.tcl +ntb_random_seed=825954272 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_otbn_ecdsa_op_irq_jitter_en.825954272
Directory	/workspace/2.chip_sw_otbn_ecdsa_op_irq_jitter_en/latest

Test location	/workspace/coverage/default/2.chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq.1367635385
Short name	T754
Test name
Test status
Simulation time	24800182358 ps
CPU time	3909.03 seconds
Started	Aug 14 06:07:10 PM PDT 24
Finished	Aug 14 07:12:20 PM PDT 24
Peak memory	611064 kb
Host	smart-b261ae92-4b38-4784-bc5f-2ded51f0782c
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=33_000_000 +rng_srate_value=30 +en_jitter=1 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=otbn_e cdsa_op_irq_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/ repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1367635385 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_otbn_ecdsa_op_irq_jitter_en_redu ced_freq.1367635385
Directory	/workspace/2.chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq/latest

Test location	/workspace/coverage/default/2.chip_sw_otbn_mem_scramble.1306161135
Short name	T295
Test name
Test status
Simulation time	4179703880 ps
CPU time	726.53 seconds
Started	Aug 14 06:05:10 PM PDT 24
Finished	Aug 14 06:17:18 PM PDT 24
Peak memory	610628 kb
Host	smart-cb7f2ed1-f078-4f38-b726-fd16b9b361d8
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=15_000_000 +en_scb_tl_err_chk=0 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=otbn _mem_scramble_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1306161135 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_otbn_mem_scramble.1306161135
Directory	/workspace/2.chip_sw_otbn_mem_scramble/latest

Test location	/workspace/coverage/default/2.chip_sw_otbn_randomness.1975146024
Short name	T359
Test name
Test status
Simulation time	5784939600 ps
CPU time	1030.54 seconds
Started	Aug 14 06:02:23 PM PDT 24
Finished	Aug 14 06:19:34 PM PDT 24
Peak memory	609708 kb
Host	smart-a495c599-f85e-4dd1-bb26-222bf5a09846
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=18_000_000 +rng_srate_value=30 +sw_build_device=sim_dv +sw_images=otbn_randomness_test:1:new_rules,test_ro m:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=1975146024 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_otbn_randomness.1975146024
Directory	/workspace/2.chip_sw_otbn_randomness/latest

Test location	/workspace/coverage/default/2.chip_sw_otbn_smoketest.3542603150
Short name	T931
Test name
Test status
Simulation time	6464075210 ps
CPU time	1086.62 seconds
Started	Aug 14 06:08:20 PM PDT 24
Finished	Aug 14 06:26:27 PM PDT 24
Peak memory	610708 kb
Host	smart-33ad4fe3-8138-4f81-9c3d-6e29d859c4d9
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=otbn_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3542603150 -assert nopostproc +UVM_TESTNAME=chi p_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul l -cm_name 2.chip_sw_otbn_smoketest.3542603150
Directory	/workspace/2.chip_sw_otbn_smoketest/latest

Test location	/workspace/coverage/default/2.chip_sw_otp_ctrl_ecc_error_vendor_test.3170119904
Short name	T567
Test name
Test status
Simulation time	3108732071 ps
CPU time	314.01 seconds
Started	Aug 14 05:59:45 PM PDT 24
Finished	Aug 14 06:05:00 PM PDT 24
Peak memory	609588 kb
Host	smart-d4576318-76fa-45c8-bbc4-6061c18896da
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=otp_ctrl_vendor_test_ecc_error_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3170119904 -assert nopostp roc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_otp_ctrl_vendor_test_ecc_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_otp_ctrl_ecc_error_vendor_test.3170119904
Directory	/workspace/2.chip_sw_otp_ctrl_ecc_error_vendor_test/latest

Test location	/workspace/coverage/default/2.chip_sw_otp_ctrl_lc_signals_dev.2130763439
Short name	T406
Test name
Test status
Simulation time	8273463208 ps
CPU time	1249.08 seconds
Started	Aug 14 05:58:58 PM PDT 24
Finished	Aug 14 06:19:47 PM PDT 24
Peak memory	609900 kb
Host	smart-06e4a332-10bf-44b0-b7e0-ed664c1cc81a
User	root
Command	/workspace/default/simv +use_otp_image=OtpTypeLcStDev +otp_clear_secret2=1 +sw_build_device=sim_dv +sw_images=otp_ctrl_lc_signals_test:1:new_rules,tes t_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +nt b_random_seed=2130763439 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_otp_ctrl_lc_signals_dev.2130763439
Directory	/workspace/2.chip_sw_otp_ctrl_lc_signals_dev/latest

Test location	/workspace/coverage/default/2.chip_sw_otp_ctrl_lc_signals_prod.3319503274
Short name	T611
Test name
Test status
Simulation time	7962861244 ps
CPU time	1603.01 seconds
Started	Aug 14 06:03:26 PM PDT 24
Finished	Aug 14 06:30:10 PM PDT 24
Peak memory	610560 kb
Host	smart-f9372e91-6fe0-412c-a1c8-8572a04089b7
User	root
Command	/workspace/default/simv +use_otp_image=OtpTypeLcStProd +otp_clear_secret2=1 +sw_build_device=sim_dv +sw_images=otp_ctrl_lc_signals_test:1:new_rules,te st_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n tb_random_seed=3319503274 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_otp_ctrl_lc_signals_prod.3319503274
Directory	/workspace/2.chip_sw_otp_ctrl_lc_signals_prod/latest

Test location	/workspace/coverage/default/2.chip_sw_otp_ctrl_lc_signals_rma.4077814059
Short name	T773
Test name
Test status
Simulation time	8681731000 ps
CPU time	1399.43 seconds
Started	Aug 14 06:00:10 PM PDT 24
Finished	Aug 14 06:23:30 PM PDT 24
Peak memory	611444 kb
Host	smart-78e3f229-a1ee-4313-b458-d392029a33c0
User	root
Command	/workspace/default/simv +use_otp_image=OtpTypeLcStRma +otp_clear_secret2=1 +sw_build_device=sim_dv +sw_images=otp_ctrl_lc_signals_test:1:new_rules,tes t_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +nt b_random_seed=4077814059 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_otp_ctrl_lc_signals_rma.4077814059
Directory	/workspace/2.chip_sw_otp_ctrl_lc_signals_rma/latest

Test location	/workspace/coverage/default/2.chip_sw_otp_ctrl_lc_signals_test_unlocked0.3836180364
Short name	T810
Test name
Test status
Simulation time	3838164070 ps
CPU time	638.27 seconds
Started	Aug 14 05:59:31 PM PDT 24
Finished	Aug 14 06:10:10 PM PDT 24
Peak memory	610252 kb
Host	smart-38c743f2-9b69-468c-8f8e-a28e3d6b20f1
User	root
Command	/workspace/default/simv +use_otp_image=OtpTypeLcStTestUnlocked0 +otp_clear_secret2=1 +sw_build_device=sim_dv +sw_images=otp_ctrl_lc_signals_test:1:new _rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/s im.tcl +ntb_random_seed=3836180364 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_otp_ctrl_lc_signals_test_unlocked0.3836180364
Directory	/workspace/2.chip_sw_otp_ctrl_lc_signals_test_unlocked0/latest

Test location	/workspace/coverage/default/2.chip_sw_otp_ctrl_smoketest.365613142
Short name	T561
Test name
Test status
Simulation time	3327219590 ps
CPU time	308.85 seconds
Started	Aug 14 06:09:19 PM PDT 24
Finished	Aug 14 06:14:28 PM PDT 24
Peak memory	609828 kb
Host	smart-b2397aa7-d06a-4ed8-871a-786ebfe4d586
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=otp_ctrl_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=365613142 -assert nopostproc +UVM_TESTNAME= chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/ null -cm_name 2.chip_sw_otp_ctrl_smoketest.365613142
Directory	/workspace/2.chip_sw_otp_ctrl_smoketest/latest

Test location	/workspace/coverage/default/2.chip_sw_pattgen_ios.1768582460
Short name	T119
Test name
Test status
Simulation time	3402922392 ps
CPU time	272.06 seconds
Started	Aug 14 05:57:51 PM PDT 24
Finished	Aug 14 06:02:24 PM PDT 24
Peak memory	614076 kb
Host	smart-dc30305b-f438-41c3-8ed0-a8d7d473f2ef
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=5_000_000 +sw_build_device=sim_dv +sw_images=pattgen_ios_test:1:new_rules,test_rom:0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1768582460 -ass ert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_patt_ios_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/c overage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_pattgen_ios.1768582460
Directory	/workspace/2.chip_sw_pattgen_ios/latest

Test location	/workspace/coverage/default/2.chip_sw_plic_sw_irq.2804718557
Short name	T271
Test name
Test status
Simulation time	2265575980 ps
CPU time	240.08 seconds
Started	Aug 14 06:05:25 PM PDT 24
Finished	Aug 14 06:09:25 PM PDT 24
Peak memory	610452 kb
Host	smart-c1eb62cb-3954-49ab-8e36-82c3b8375e4b
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=plic_sw_irq_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2804718557 -assert nopostproc +UVM_TESTNAME=c hip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n ull -cm_name 2.chip_sw_plic_sw_irq.2804718557
Directory	/workspace/2.chip_sw_plic_sw_irq/latest

Test location	/workspace/coverage/default/2.chip_sw_power_idle_load.3208283771
Short name	T828
Test name
Test status
Simulation time	4494143252 ps
CPU time	569.21 seconds
Started	Aug 14 06:07:36 PM PDT 24
Finished	Aug 14 06:17:06 PM PDT 24
Peak memory	610352 kb
Host	smart-6a0dc6cb-171b-4225-8057-093ecd7426f3
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=chip_power_idle_load:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3208283771 -assert nopostproc +UVM_TESTNA ME=chip_base_test +UVM_TEST_SEQ=chip_sw_power_idle_load_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_power_idle_load.3208283771
Directory	/workspace/2.chip_sw_power_idle_load/latest

Test location	/workspace/coverage/default/2.chip_sw_power_sleep_load.2383892094
Short name	T269
Test name
Test status
Simulation time	4328940778 ps
CPU time	424.83 seconds
Started	Aug 14 06:08:50 PM PDT 24
Finished	Aug 14 06:15:55 PM PDT 24
Peak memory	611244 kb
Host	smart-d7af2180-bb6d-465d-879b-c595d94154c5
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=chip_power_sleep_load:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2383892094 -assert nopostproc +UVM_TESTN AME=chip_base_test +UVM_TEST_SEQ=chip_sw_power_sleep_load_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v db -cm_log /dev/null -cm_name 2.chip_sw_power_sleep_load.2383892094
Directory	/workspace/2.chip_sw_power_sleep_load/latest

Test location	/workspace/coverage/default/2.chip_sw_power_virus.1235249792
Short name	T32
Test name
Test status
Simulation time	5612190600 ps
CPU time	1440.85 seconds
Started	Aug 14 06:13:58 PM PDT 24
Finished	Aug 14 06:37:59 PM PDT 24
Peak memory	625480 kb
Host	smart-22fd4bff-085f-47c3-afbe-5821b797d46e
User	root
Command	/workspace/default/simv +rng_srate_value_min=15 +rng_srate_value_max=20 +sw_test_timeout_ns=400_000_000 +use_otp_image=OtpTypeCustom +accelerate_cold_ power_up_time=3 +accelerate_regulators_power_up_time=2 +sw_build_device=sim_dv +sw_images=power_virus_systemtest:1:new_rules,power_virus_systemtes t_otp_img_rma:4,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d v/tools/sim.tcl +ntb_random_seed=1235249792 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_power_virus_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_power_virus.1235249792
Directory	/workspace/2.chip_sw_power_virus/latest

Test location	/workspace/coverage/default/2.chip_sw_pwrmgr_all_reset_reqs.791857791
Short name	T348
Test name
Test status
Simulation time	11550757897 ps
CPU time	1491.01 seconds
Started	Aug 14 06:00:10 PM PDT 24
Finished	Aug 14 06:25:02 PM PDT 24
Peak memory	612200 kb
Host	smart-9c080f1e-86a7-439f-8279-9ed05b732853
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=50_000_000 +sw_build_device=sim_dv +sw_images=pwrmgr_all_reset_reqs_test:1:new_rules,test_rom:0 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=7918 57791 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_deep_sleep_all_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_pwrmgr_all_reset_reqs.791857791
Directory	/workspace/2.chip_sw_pwrmgr_all_reset_reqs/latest

Test location	/workspace/coverage/default/2.chip_sw_pwrmgr_b2b_sleep_reset_req.2415446890
Short name	T25
Test name
Test status
Simulation time	26768721996 ps
CPU time	3738.71 seconds
Started	Aug 14 06:05:57 PM PDT 24
Finished	Aug 14 07:08:18 PM PDT 24
Peak memory	611628 kb
Host	smart-242cf9a7-6e35-4e25-bdc9-872aa6995240
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=35_000_000 +sw_build_device=sim_dv +sw_images=pwrmgr_b2b_sleep_reset_test:1:new_rules,test_rom:0 +cdc_inst rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=241 5446890 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_repeat_reset_wkup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_pwrmgr_b2b_sleep_reset_req.2415446890
Directory	/workspace/2.chip_sw_pwrmgr_b2b_sleep_reset_req/latest

Test location	/workspace/coverage/default/2.chip_sw_pwrmgr_deep_sleep_all_reset_reqs.2689233553
Short name	T275
Test name
Test status
Simulation time	15662931895 ps
CPU time	1747.4 seconds
Started	Aug 14 06:00:50 PM PDT 24
Finished	Aug 14 06:29:58 PM PDT 24
Peak memory	611984 kb
Host	smart-7c6daf7d-b4da-4f6e-8887-ddeea2f0f8c9
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=50_000_000 +sw_build_device=sim_dv +sw_images=pwrmgr_deep_sleep_all_reset_reqs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=2689233553 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_deep_sleep_all_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_pwrmgr_deep_sleep_all_reset_reqs.2689233553
Directory	/workspace/2.chip_sw_pwrmgr_deep_sleep_all_reset_reqs/latest

Test location	/workspace/coverage/default/2.chip_sw_pwrmgr_deep_sleep_all_wake_ups.586526382
Short name	T86
Test name
Test status
Simulation time	23703848390 ps
CPU time	1314.27 seconds
Started	Aug 14 06:06:52 PM PDT 24
Finished	Aug 14 06:28:46 PM PDT 24
Peak memory	611248 kb
Host	smart-520f0afd-5faf-41e2-8807-5f574b7ff523
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=pwrmgr_deep_sleep_all_wake_ups:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 586526382 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_pwrmgr_deep_sleep_all_wake_ups_vseq +en_cov=1 -cm line+cond+fsm+tg l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_pwrmgr_deep_sleep_all_wake_ups.586526382
Directory	/workspace/2.chip_sw_pwrmgr_deep_sleep_all_wake_ups/latest

Test location	/workspace/coverage/default/2.chip_sw_pwrmgr_deep_sleep_por_reset.3974809127
Short name	T736
Test name
Test status
Simulation time	9046668500 ps
CPU time	707.11 seconds
Started	Aug 14 06:01:13 PM PDT 24
Finished	Aug 14 06:13:00 PM PDT 24
Peak memory	610424 kb
Host	smart-ffd14994-d298-4153-8e49-dc0238adcdf1
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_deep_sleep_por_reset_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3974809127 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sleep_por_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage /default.vdb -cm_log /dev/null -cm_name 2.chip_sw_pwrmgr_deep_sleep_por_reset.3974809127
Directory	/workspace/2.chip_sw_pwrmgr_deep_sleep_por_reset/latest

Test location	/workspace/coverage/default/2.chip_sw_pwrmgr_deep_sleep_power_glitch_reset.1358816591
Short name	T654
Test name
Test status
Simulation time	6519635408 ps
CPU time	494.11 seconds
Started	Aug 14 06:01:21 PM PDT 24
Finished	Aug 14 06:09:36 PM PDT 24
Peak memory	618048 kb
Host	smart-43d342be-bef4-4826-b638-46c2ffdfbdb2
User	root
Command	/workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=pwrmgr_deep_sleep_power_glitch_test:1:new_rules,test_rom :0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=1358816591 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_deep_power_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_pwrmgr_deep_sleep_power_glitch_reset.1358816591
Directory	/workspace/2.chip_sw_pwrmgr_deep_sleep_power_glitch_reset/latest

Test location	/workspace/coverage/default/2.chip_sw_pwrmgr_full_aon_reset.66047930
Short name	T796
Test name
Test status
Simulation time	10157744452 ps
CPU time	663.71 seconds
Started	Aug 14 05:59:43 PM PDT 24
Finished	Aug 14 06:10:47 PM PDT 24
Peak memory	611260 kb
Host	smart-33d65eb7-ed6d-42c0-8550-02c857ddd7a1
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=rstmgr_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=66047930 -assert nopostproc +UVM_TESTNAME=chi p_base_test +UVM_TEST_SEQ=chip_sw_full_aon_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_lo g /dev/null -cm_name 2.chip_sw_pwrmgr_full_aon_reset.66047930
Directory	/workspace/2.chip_sw_pwrmgr_full_aon_reset/latest

Test location	/workspace/coverage/default/2.chip_sw_pwrmgr_lowpower_cancel.1117894233
Short name	T363
Test name
Test status
Simulation time	3859161544 ps
CPU time	567.33 seconds
Started	Aug 14 06:04:48 PM PDT 24
Finished	Aug 14 06:14:15 PM PDT 24
Peak memory	610608 kb
Host	smart-13f34be4-f0f4-4915-b8a3-54d906242791
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_lowpower_cancel_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1117894233 -assert nopostproc +UVM _TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm _log /dev/null -cm_name 2.chip_sw_pwrmgr_lowpower_cancel.1117894233
Directory	/workspace/2.chip_sw_pwrmgr_lowpower_cancel/latest

Test location	/workspace/coverage/default/2.chip_sw_pwrmgr_main_power_glitch_reset.1466529155
Short name	T651
Test name
Test status
Simulation time	5521773588 ps
CPU time	566.01 seconds
Started	Aug 14 06:01:05 PM PDT 24
Finished	Aug 14 06:10:31 PM PDT 24
Peak memory	618240 kb
Host	smart-9cecdd66-c539-41cd-9ca1-eba02c3291fc
User	root
Command	/workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=pwrmgr_main_power_glitch_test:1:new_rules,test_rom:0 +cd c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se ed=1466529155 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_main_power_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_pwrmgr_main_power_glitch_reset.1466529155
Directory	/workspace/2.chip_sw_pwrmgr_main_power_glitch_reset/latest

Test location	/workspace/coverage/default/2.chip_sw_pwrmgr_normal_sleep_all_reset_reqs.3424700763
Short name	T274
Test name
Test status
Simulation time	10318227047 ps
CPU time	1433.43 seconds
Started	Aug 14 06:00:56 PM PDT 24
Finished	Aug 14 06:24:49 PM PDT 24
Peak memory	612240 kb
Host	smart-b54d1c62-ffa8-41bb-8804-e454703aa12c
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_normal_sleep_all_reset_reqs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3424700763 -assert nop ostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_deep_sleep_all_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_pwrmgr_normal_sleep_all_reset_reqs.3424700763
Directory	/workspace/2.chip_sw_pwrmgr_normal_sleep_all_reset_reqs/latest

Test location	/workspace/coverage/default/2.chip_sw_pwrmgr_normal_sleep_all_wake_ups.2030489093
Short name	T411
Test name
Test status
Simulation time	7269639800 ps
CPU time	488.26 seconds
Started	Aug 14 06:05:58 PM PDT 24
Finished	Aug 14 06:14:07 PM PDT 24
Peak memory	611428 kb
Host	smart-5cdb565c-9c2e-44e6-93d5-7ab26c736aca
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_normal_sleep_all_wake_ups:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2030489093 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_pwrmgr_deep_sleep_all_wake_ups_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_pwrmgr_normal_sleep_all_wake_ups.2030489093
Directory	/workspace/2.chip_sw_pwrmgr_normal_sleep_all_wake_ups/latest

Test location	/workspace/coverage/default/2.chip_sw_pwrmgr_normal_sleep_por_reset.3735121792
Short name	T601
Test name
Test status
Simulation time	6101915500 ps
CPU time	496.49 seconds
Started	Aug 14 06:01:30 PM PDT 24
Finished	Aug 14 06:09:47 PM PDT 24
Peak memory	611288 kb
Host	smart-0892f4f4-4916-48e1-ae21-6726d4bffb5b
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_normal_sleep_por_reset_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3735121792 -assert nopostpr oc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sleep_por_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera ge/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_pwrmgr_normal_sleep_por_reset.3735121792
Directory	/workspace/2.chip_sw_pwrmgr_normal_sleep_por_reset/latest

Test location	/workspace/coverage/default/2.chip_sw_pwrmgr_random_sleep_all_reset_reqs.3986876188
Short name	T1018
Test name
Test status
Simulation time	21307337060 ps
CPU time	1965.2 seconds
Started	Aug 14 06:00:18 PM PDT 24
Finished	Aug 14 06:33:04 PM PDT 24
Peak memory	612240 kb
Host	smart-63790c6f-9f68-4a7f-acfe-74070cf7f41b
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=50_000_000 +sw_build_device=sim_dv +sw_images=pwrmgr_random_sleep_all_reset_reqs_test:1:new_rules,test_rom :0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=3986876188 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_deep_sleep_all_reset_vseq +en_cov=1 -cm line+cond+fsm+tg l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_pwrmgr_random_sleep_all_reset_reqs.3986876188
Directory	/workspace/2.chip_sw_pwrmgr_random_sleep_all_reset_reqs/latest

Test location	/workspace/coverage/default/2.chip_sw_pwrmgr_random_sleep_all_wake_ups.3764479108
Short name	T199
Test name
Test status
Simulation time	24521931196 ps
CPU time	1628.47 seconds
Started	Aug 14 06:06:05 PM PDT 24
Finished	Aug 14 06:33:13 PM PDT 24
Peak memory	611780 kb
Host	smart-ee03e571-a539-4e6a-bd02-c332a59b99f3
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=18_000_000 +do_random=1 +sw_build_device=sim_dv +sw_images=pwrmgr_random_sleep_all_wake_ups:1:new_rules,te st_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n tb_random_seed=3764479108 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_pwrmgr_deep_sleep_all_wake_ups_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_pwrmgr_random_sleep_all_wake_ups.3764479108
Directory	/workspace/2.chip_sw_pwrmgr_random_sleep_all_wake_ups/latest

Test location	/workspace/coverage/default/2.chip_sw_pwrmgr_random_sleep_power_glitch_reset.274276076
Short name	T579
Test name
Test status
Simulation time	31665080325 ps
CPU time	3021.75 seconds
Started	Aug 14 06:04:03 PM PDT 24
Finished	Aug 14 06:54:26 PM PDT 24
Peak memory	612688 kb
Host	smart-85f75074-8a9a-46b0-a89a-8d35ac7b8d69
User	root
Command	/workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_test_timeout_ns=24_000_000 +sw_build_device=sim_dv +sw_images=pwrmgr_random_sleep_power _glitch_reset_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=274276076 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_random_power_glitc h_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_pwrmgr_random_sl eep_power_glitch_reset.274276076
Directory	/workspace/2.chip_sw_pwrmgr_random_sleep_power_glitch_reset/latest

Test location	/workspace/coverage/default/2.chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up.2538232362
Short name	T392
Test name
Test status
Simulation time	6550889320 ps
CPU time	414.84 seconds
Started	Aug 14 06:03:55 PM PDT 24
Finished	Aug 14 06:10:50 PM PDT 24
Peak memory	611740 kb
Host	smart-9d38e35d-080e-48a7-8c3b-1566e0700155
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=18_000_000 +do_random=1 +sw_build_device=sim_dv +sw_images=pwrmgr_sensor_ctrl_deep_sleep_wake_up:1:new_rul es,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t cl +ntb_random_seed=2538232362 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_pwrmgr_sensor_ctrl_deep_s leep_wake_up.2538232362
Directory	/workspace/2.chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up/latest

Test location	/workspace/coverage/default/2.chip_sw_pwrmgr_sleep_disabled.425891368
Short name	T381
Test name
Test status
Simulation time	2482440260 ps
CPU time	270.67 seconds
Started	Aug 14 06:02:22 PM PDT 24
Finished	Aug 14 06:06:54 PM PDT 24
Peak memory	610460 kb
Host	smart-7d33adc2-bf1c-4d57-85ca-5c519f77f409
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_sleep_disabled_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=425891368 -assert nopostproc +UVM_T ESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l og /dev/null -cm_name 2.chip_sw_pwrmgr_sleep_disabled.425891368
Directory	/workspace/2.chip_sw_pwrmgr_sleep_disabled/latest

Test location	/workspace/coverage/default/2.chip_sw_pwrmgr_sleep_power_glitch_reset.1045518089
Short name	T564
Test name
Test status
Simulation time	5760037421 ps
CPU time	588 seconds
Started	Aug 14 06:00:40 PM PDT 24
Finished	Aug 14 06:10:28 PM PDT 24
Peak memory	618164 kb
Host	smart-bda53ed7-0f11-4a21-ab72-a5555b881e3b
User	root
Command	/workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=pwrmgr_sleep_power_glitch_test:1:new_rules,test_rom:0 +c dc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_s eed=1045518089 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_main_power_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_pwrmgr_sleep_power_glitch_reset.1045518089
Directory	/workspace/2.chip_sw_pwrmgr_sleep_power_glitch_reset/latest

Test location	/workspace/coverage/default/2.chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup.4199516827
Short name	T147
Test name
Test status
Simulation time	5504464906 ps
CPU time	526.22 seconds
Started	Aug 14 06:04:06 PM PDT 24
Finished	Aug 14 06:12:52 PM PDT 24
Peak memory	610644 kb
Host	smart-aa0d90a6-de58-42fa-9a40-73103550d032
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=8_000_000 +sw_build_device=sim_dv +sw_images=sensor_ctrl_wakeup_test:1:new_rules,test_rom:0 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41995168 27 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac e/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup.4199516827
Directory	/workspace/2.chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup/latest

Test location	/workspace/coverage/default/2.chip_sw_pwrmgr_sleep_wake_5_bug.4031628049
Short name	T1031
Test name
Test status
Simulation time	7297665584 ps
CPU time	592.54 seconds
Started	Aug 14 06:04:53 PM PDT 24
Finished	Aug 14 06:14:46 PM PDT 24
Peak memory	611180 kb
Host	smart-5165be86-8211-4b8f-afa3-ac1268f232ae
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=18_000_000 +do_random=1 +sw_build_device=sim_dv +sw_images=pwrmgr_sleep_wake_5_bug_test:1:new_rules,test_r om:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r andom_seed=4031628049 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_pwrmgr_sleep_wake_5_bug.4031628049
Directory	/workspace/2.chip_sw_pwrmgr_sleep_wake_5_bug/latest

Test location	/workspace/coverage/default/2.chip_sw_pwrmgr_smoketest.3357801106
Short name	T580
Test name
Test status
Simulation time	6064128932 ps
CPU time	416.66 seconds
Started	Aug 14 06:07:35 PM PDT 24
Finished	Aug 14 06:14:32 PM PDT 24
Peak memory	610432 kb
Host	smart-7f0e812b-8cd4-497c-a883-b5351397dfca
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=10000000 +sw_build_device=sim_dv +sw_images=pwrmgr_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3357801106 -asse rt nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera ge/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_pwrmgr_smoketest.3357801106
Directory	/workspace/2.chip_sw_pwrmgr_smoketest/latest

Test location	/workspace/coverage/default/2.chip_sw_pwrmgr_sysrst_ctrl_reset.30966058
Short name	T557
Test name
Test status
Simulation time	7299599990 ps
CPU time	1175.26 seconds
Started	Aug 14 05:59:54 PM PDT 24
Finished	Aug 14 06:19:30 PM PDT 24
Peak memory	611276 kb
Host	smart-4a622137-3282-4a77-8920-6277f7efd99f
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_sysrst_ctrl_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30966058 -assert nopostproc +UVM_TESTN AME=chip_base_test +UVM_TEST_SEQ=chip_sw_sysrst_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -c m_log /dev/null -cm_name 2.chip_sw_pwrmgr_sysrst_ctrl_reset.30966058
Directory	/workspace/2.chip_sw_pwrmgr_sysrst_ctrl_reset/latest

Test location	/workspace/coverage/default/2.chip_sw_pwrmgr_usb_clk_disabled_when_active.299217343
Short name	T891
Test name
Test status
Simulation time	4163534326 ps
CPU time	384.43 seconds
Started	Aug 14 06:00:47 PM PDT 24
Finished	Aug 14 06:07:12 PM PDT 24
Peak memory	610952 kb
Host	smart-2e6c099c-41d3-4fcb-952b-d3cc22d216e8
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_usb_clk_disabled_when_active_test:1:new_rules,test_rom:0 +cdc_instrumentation_enable d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=299217343 -assert nop ostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def ault.vdb -cm_log /dev/null -cm_name 2.chip_sw_pwrmgr_usb_clk_disabled_when_active.299217343
Directory	/workspace/2.chip_sw_pwrmgr_usb_clk_disabled_when_active/latest

Test location	/workspace/coverage/default/2.chip_sw_pwrmgr_usbdev_smoketest.3856678252
Short name	T87
Test name
Test status
Simulation time	6830571144 ps
CPU time	579.54 seconds
Started	Aug 14 06:07:33 PM PDT 24
Finished	Aug 14 06:17:13 PM PDT 24
Peak memory	611172 kb
Host	smart-bb0265e3-b79c-4869-9b59-a8a10f2b5241
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_usbdev_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3856678252 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_pwrmgr_usbdev_smoketest.3856678252
Directory	/workspace/2.chip_sw_pwrmgr_usbdev_smoketest/latest

Test location	/workspace/coverage/default/2.chip_sw_pwrmgr_wdog_reset.817226155
Short name	T833
Test name
Test status
Simulation time	4423763932 ps
CPU time	525.16 seconds
Started	Aug 14 06:03:30 PM PDT 24
Finished	Aug 14 06:12:16 PM PDT 24
Peak memory	609840 kb
Host	smart-97c24009-6d67-4256-8a0a-eeabc25b3f05
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=pwrmgr_wdog_reset_reqs_test:1:new_rules,test_rom:0 +cdc_inst rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=817 226155 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work space/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_pwrmgr_wdog_reset.817226155
Directory	/workspace/2.chip_sw_pwrmgr_wdog_reset/latest

Test location	/workspace/coverage/default/2.chip_sw_rom_ctrl_integrity_check.1434217752
Short name	T167
Test name
Test status
Simulation time	8949516554 ps
CPU time	606.74 seconds
Started	Aug 14 06:03:47 PM PDT 24
Finished	Aug 14 06:13:54 PM PDT 24
Peak memory	624248 kb
Host	smart-0aea34b2-c4a9-4915-a023-62377ee05407
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=rom_ctrl_integrity_check_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1434217752 -assert nopostproc +U VM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rom_ctrl_integrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co verage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_rom_ctrl_integrity_check.1434217752
Directory	/workspace/2.chip_sw_rom_ctrl_integrity_check/latest

Test location	/workspace/coverage/default/2.chip_sw_rstmgr_alert_info.335018995
Short name	T314
Test name
Test status
Simulation time	11469735000 ps
CPU time	1691.44 seconds
Started	Aug 14 06:00:05 PM PDT 24
Finished	Aug 14 06:28:17 PM PDT 24
Peak memory	611344 kb
Host	smart-44ce7584-d649-4480-907a-28df8224788e
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=30_000_000 +en_scb_tl_err_chk=0 +sw_build_device=sim_dv +sw_images=rstmgr_alert_info_test:1:new_rules,test _rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb _random_seed=335018995 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_rstmgr_alert_info.335018995
Directory	/workspace/2.chip_sw_rstmgr_alert_info/latest

Test location	/workspace/coverage/default/2.chip_sw_rstmgr_cpu_info.3492744099
Short name	T282
Test name
Test status
Simulation time	6125240460 ps
CPU time	771.56 seconds
Started	Aug 14 06:00:35 PM PDT 24
Finished	Aug 14 06:13:28 PM PDT 24
Peak memory	610500 kb
Host	smart-85e072a4-d3cf-46a5-b72e-a8bca71524e8
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=rstmgr_cpu_info_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3492744099 -assert nopostproc +UVM_TESTNA ME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 2.chip_sw_rstmgr_cpu_info.3492744099
Directory	/workspace/2.chip_sw_rstmgr_cpu_info/latest

Test location	/workspace/coverage/default/2.chip_sw_rstmgr_rst_cnsty_escalation.2267841330
Short name	T399
Test name
Test status
Simulation time	5972483992 ps
CPU time	927.73 seconds
Started	Aug 14 05:57:59 PM PDT 24
Finished	Aug 14 06:13:27 PM PDT 24
Peak memory	642436 kb
Host	smart-a8556250-039c-4dfc-883f-2323f88f924e
User	root
Command	/workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 2267841330 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rstmgr_cnsty_fault_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_rstmgr_rst_cnsty_escalation.2267841330
Directory	/workspace/2.chip_sw_rstmgr_rst_cnsty_escalation/latest

Test location	/workspace/coverage/default/2.chip_sw_rstmgr_smoketest.1513628971
Short name	T797
Test name
Test status
Simulation time	3391727500 ps
CPU time	238.02 seconds
Started	Aug 14 06:07:39 PM PDT 24
Finished	Aug 14 06:11:37 PM PDT 24
Peak memory	610284 kb
Host	smart-877a9835-e073-4be1-8394-d75f52767e8b
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=rstmgr_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1513628971 -assert nopostproc +UVM_TESTNAME=c hip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n ull -cm_name 2.chip_sw_rstmgr_smoketest.1513628971
Directory	/workspace/2.chip_sw_rstmgr_smoketest/latest

Test location	/workspace/coverage/default/2.chip_sw_rstmgr_sw_req.2417324672
Short name	T439
Test name
Test status
Simulation time	4701067832 ps
CPU time	453.59 seconds
Started	Aug 14 06:03:11 PM PDT 24
Finished	Aug 14 06:10:45 PM PDT 24
Peak memory	611208 kb
Host	smart-af038bfd-10dd-4350-8f44-78202f729dc0
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=rstmgr_sw_req_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2417324672 -assert nopostproc +UVM_TESTNAME =chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 2.chip_sw_rstmgr_sw_req.2417324672
Directory	/workspace/2.chip_sw_rstmgr_sw_req/latest

Test location	/workspace/coverage/default/2.chip_sw_rstmgr_sw_rst.3899334366
Short name	T948
Test name
Test status
Simulation time	3159629952 ps
CPU time	295.47 seconds
Started	Aug 14 06:00:40 PM PDT 24
Finished	Aug 14 06:05:36 PM PDT 24
Peak memory	610468 kb
Host	smart-3fb30f05-fe4e-4287-b182-6d121aae2365
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=rstmgr_sw_rst_ctrl_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3899334366 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_rstmgr_sw_rst.3899334366
Directory	/workspace/2.chip_sw_rstmgr_sw_rst/latest

Test location	/workspace/coverage/default/2.chip_sw_rv_core_ibex_address_translation.2028464839
Short name	T307
Test name
Test status
Simulation time	2866460200 ps
CPU time	318.16 seconds
Started	Aug 14 06:06:56 PM PDT 24
Finished	Aug 14 06:12:15 PM PDT 24
Peak memory	610572 kb
Host	smart-a2e2e5b2-d1a6-440d-8a1d-2b33b95619d4
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=7_000_000 +sw_build_device=sim_dv +sw_images=rv_core_ibex_address_translation_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random _seed=2028464839 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_rv_core_ibex_address_translation.2028464839
Directory	/workspace/2.chip_sw_rv_core_ibex_address_translation/latest

Test location	/workspace/coverage/default/2.chip_sw_rv_core_ibex_icache_invalidate.3135066928
Short name	T308
Test name
Test status
Simulation time	2768321174 ps
CPU time	308.81 seconds
Started	Aug 14 06:05:56 PM PDT 24
Finished	Aug 14 06:11:06 PM PDT 24
Peak memory	610512 kb
Host	smart-db72e975-7f1f-4d22-b83c-61882c8a83b1
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=rv_core_ibex_icache_invalidate_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3135066928 -assert nopostp roc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rv_core_ibex_icache_invalidate_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_rv_core_ibex_icache_invalidate.3135066928
Directory	/workspace/2.chip_sw_rv_core_ibex_icache_invalidate/latest

Test location	/workspace/coverage/default/2.chip_sw_rv_core_ibex_nmi_irq.3154300869
Short name	T322
Test name
Test status
Simulation time	4357146110 ps
CPU time	814.68 seconds
Started	Aug 14 06:02:20 PM PDT 24
Finished	Aug 14 06:15:55 PM PDT 24
Peak memory	609964 kb
Host	smart-492b9ca8-9e62-48a7-95f5-3b4a083fe7f4
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=10_000_000 +sw_build_device=sim_dv +sw_images=rv_core_ibex_nmi_irq_test:1:new_rules,test_rom:0 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31543 00869 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_rv_core_ibex_nmi_irq.3154300869
Directory	/workspace/2.chip_sw_rv_core_ibex_nmi_irq/latest

Test location	/workspace/coverage/default/2.chip_sw_rv_core_ibex_rnd.1801196505
Short name	T719
Test name
Test status
Simulation time	5726595200 ps
CPU time	1114.55 seconds
Started	Aug 14 06:02:10 PM PDT 24
Finished	Aug 14 06:20:44 PM PDT 24
Peak memory	610852 kb
Host	smart-7dcf1be3-f306-4a14-8a81-36312693641b
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=20_000_000 +rng_srate_value_max=32 +sw_build_device=sim_dv +sw_images=rv_core_ibex_rnd_test:1:new_rules,te st_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n tb_random_seed=1801196505 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_rv_core_ibex_rnd.1801196505
Directory	/workspace/2.chip_sw_rv_core_ibex_rnd/latest

Test location	/workspace/coverage/default/2.chip_sw_rv_dm_access_after_escalation_reset.2474672032
Short name	T433
Test name
Test status
Simulation time	5638658006 ps
CPU time	712.89 seconds
Started	Aug 14 06:05:34 PM PDT 24
Finished	Aug 14 06:17:27 PM PDT 24
Peak memory	624680 kb
Host	smart-924459db-81ec-48c9-802a-77c7b6569f14
User	root
Command	/workspace/default/simv +use_jtag_dmi=1 +sw_build_device=sim_dv +sw_images=alert_handler_escalation_test:1:new_rules,test_rom:0 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2474672032 -asse rt nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rv_dm_access_after_escalation_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_rv_dm_access_after_escalation_reset.2474672032
Directory	/workspace/2.chip_sw_rv_dm_access_after_escalation_reset/latest

Test location	/workspace/coverage/default/2.chip_sw_rv_dm_access_after_wakeup.3792600712
Short name	T646
Test name
Test status
Simulation time	6440059378 ps
CPU time	625.14 seconds
Started	Aug 14 06:05:47 PM PDT 24
Finished	Aug 14 06:16:13 PM PDT 24
Peak memory	620580 kb
Host	smart-19cfa6a2-4b17-4e4f-b8c2-5738df48411c
User	root
Command	/workspace/default/simv +use_jtag_dmi=1 +sw_build_device=sim_dv +sw_images=rv_dm_access_after_wakeup_rma:1:new_rules,test_rom:0 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3792600712 -asse rt nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rv_dm_access_after_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_rv_dm_access_after_wakeup.3792600712
Directory	/workspace/2.chip_sw_rv_dm_access_after_wakeup/latest

Test location	/workspace/coverage/default/2.chip_sw_rv_dm_ndm_reset_req_when_cpu_halted.3170726790
Short name	T7
Test name
Test status
Simulation time	3978529636 ps
CPU time	468.16 seconds
Started	Aug 14 06:06:12 PM PDT 24
Finished	Aug 14 06:14:01 PM PDT 24
Peak memory	620644 kb
Host	smart-01438c09-d3a9-485c-b11d-f80fc4d1d417
User	root
Command	/workspace/default/simv +use_jtag_dmi=1 +sw_build_device=sim_dv +sw_images=rv_dm_ndm_reset_req_when_cpu_halted_rma:1:new_rules,test_rom:0 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=317072 6790 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rv_dm_ndm_reset_when_cpu_halted_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_rv_dm_ndm_reset_req_when_cpu_halted.3170726790
Directory	/workspace/2.chip_sw_rv_dm_ndm_reset_req_when_cpu_halted/latest

Test location	/workspace/coverage/default/2.chip_sw_rv_plic_smoketest.2365665358
Short name	T738
Test name
Test status
Simulation time	2946617690 ps
CPU time	305.22 seconds
Started	Aug 14 06:07:36 PM PDT 24
Finished	Aug 14 06:12:42 PM PDT 24
Peak memory	610372 kb
Host	smart-097e5868-deb8-4464-b849-a0d671038dea
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=rv_plic_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2365665358 -assert nopostproc +UVM_TESTNAME= chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/ null -cm_name 2.chip_sw_rv_plic_smoketest.2365665358
Directory	/workspace/2.chip_sw_rv_plic_smoketest/latest

Test location	/workspace/coverage/default/2.chip_sw_rv_timer_irq.3053918762
Short name	T732
Test name
Test status
Simulation time	2925596744 ps
CPU time	311.01 seconds
Started	Aug 14 06:01:54 PM PDT 24
Finished	Aug 14 06:07:05 PM PDT 24
Peak memory	609824 kb
Host	smart-dc741250-00c6-46f6-8fb3-fe66ebce098a
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=rv_timer_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3053918762 -assert nopostproc +UVM_TESTNAME =chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 2.chip_sw_rv_timer_irq.3053918762
Directory	/workspace/2.chip_sw_rv_timer_irq/latest

Test location	/workspace/coverage/default/2.chip_sw_rv_timer_smoketest.2672060248
Short name	T801
Test name
Test status
Simulation time	3016602888 ps
CPU time	392.36 seconds
Started	Aug 14 06:11:29 PM PDT 24
Finished	Aug 14 06:18:02 PM PDT 24
Peak memory	610412 kb
Host	smart-245d461e-e164-4e18-ab2c-20cc73252c43
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=rv_timer_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2672060248 -assert nopostproc +UVM_TESTNAME =chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 2.chip_sw_rv_timer_smoketest.2672060248
Directory	/workspace/2.chip_sw_rv_timer_smoketest/latest

Test location	/workspace/coverage/default/2.chip_sw_sensor_ctrl_status.4229737611
Short name	T849
Test name
Test status
Simulation time	2541033171 ps
CPU time	218.76 seconds
Started	Aug 14 06:04:08 PM PDT 24
Finished	Aug 14 06:07:47 PM PDT 24
Peak memory	610028 kb
Host	smart-abf9fff0-c1c2-4a1a-96a6-c69ce10670f2
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=40_000_000 +sw_build_device=sim_dv +sw_images=sensor_ctrl_status_test:1:new_rules,test_rom:0 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4229737 611 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sensor_ctrl_status_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_sensor_ctrl_status.4229737611
Directory	/workspace/2.chip_sw_sensor_ctrl_status/latest

Test location	/workspace/coverage/default/2.chip_sw_sleep_pwm_pulses.26609411
Short name	T705
Test name
Test status
Simulation time	9513938800 ps
CPU time	1314.82 seconds
Started	Aug 14 05:56:09 PM PDT 24
Finished	Aug 14 06:18:04 PM PDT 24
Peak memory	611600 kb
Host	smart-45e9729e-ef60-4ed4-88d1-389ac0f3a62b
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=sleep_pwm_pulses_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26609411 -assert nopostproc +UVM_TESTNAM E=chip_base_test +UVM_TEST_SEQ=chip_sw_pwm_pulses_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l og /dev/null -cm_name 2.chip_sw_sleep_pwm_pulses.26609411
Directory	/workspace/2.chip_sw_sleep_pwm_pulses/latest

Test location	/workspace/coverage/default/2.chip_sw_sleep_sram_ret_contents_no_scramble.2059838066
Short name	T1006
Test name
Test status
Simulation time	8118526600 ps
CPU time	710.07 seconds
Started	Aug 14 06:07:21 PM PDT 24
Finished	Aug 14 06:19:11 PM PDT 24
Peak memory	611312 kb
Host	smart-3fe27483-6499-4420-a33a-ee2228260063
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=20_000_000 +en_scb_tl_err_chk=0 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=sram _ctrl_sleep_sram_ret_contents_no_scramble_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2059838066 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_S EQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_sl eep_sram_ret_contents_no_scramble.2059838066
Directory	/workspace/2.chip_sw_sleep_sram_ret_contents_no_scramble/latest

Test location	/workspace/coverage/default/2.chip_sw_sleep_sram_ret_contents_scramble.443693350
Short name	T297
Test name
Test status
Simulation time	8391007002 ps
CPU time	700.6 seconds
Started	Aug 14 06:05:07 PM PDT 24
Finished	Aug 14 06:16:48 PM PDT 24
Peak memory	611392 kb
Host	smart-ae891588-0d1d-40c4-9dd4-1f216b77b7f7
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=20_000_000 +en_scb_tl_err_chk=0 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=sram _ctrl_sleep_sram_ret_contents_scramble_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=443693350 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=c hip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_sleep_ sram_ret_contents_scramble.443693350
Directory	/workspace/2.chip_sw_sleep_sram_ret_contents_scramble/latest

Test location	/workspace/coverage/default/2.chip_sw_spi_device_pass_through.3035007811
Short name	T62
Test name
Test status
Simulation time	6175114151 ps
CPU time	664.67 seconds
Started	Aug 14 05:59:48 PM PDT 24
Finished	Aug 14 06:10:52 PM PDT 24
Peak memory	625332 kb
Host	smart-cca2dd56-83b4-4bdb-8c56-5496b7715af8
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=spi_passthrough_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3035007811 -assert nopostproc +UVM_TESTNA ME=chip_base_test +UVM_TEST_SEQ=chip_sw_spi_passthrough_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_spi_device_pass_through.3035007811
Directory	/workspace/2.chip_sw_spi_device_pass_through/latest

Test location	/workspace/coverage/default/2.chip_sw_spi_device_pass_through_collision.1515059698
Short name	T159
Test name
Test status
Simulation time	5317262474 ps
CPU time	523.7 seconds
Started	Aug 14 05:59:50 PM PDT 24
Finished	Aug 14 06:08:35 PM PDT 24
Peak memory	625364 kb
Host	smart-ec38e79a-c228-42f5-9f0b-4db1de4f000d
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=spi_passthrough_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1515059698 -assert nopostproc +UVM_TESTNA ME=chip_base_test +UVM_TEST_SEQ=chip_sw_spi_passthrough_collision_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/d efault.vdb -cm_log /dev/null -cm_name 2.chip_sw_spi_device_pass_through_collision.1515059698
Directory	/workspace/2.chip_sw_spi_device_pass_through_collision/latest

Test location	/workspace/coverage/default/2.chip_sw_spi_device_pinmux_sleep_retention.3460257071
Short name	T78
Test name
Test status
Simulation time	3510334606 ps
CPU time	296.63 seconds
Started	Aug 14 05:58:31 PM PDT 24
Finished	Aug 14 06:03:28 PM PDT 24
Peak memory	619792 kb
Host	smart-f7c9a47b-61c6-41e3-82ba-036ca5fbd96e
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=spi_device_sleep_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3460257071 -assert nopostproc +UVM_TESTN AME=chip_base_test +UVM_TEST_SEQ=chip_sw_spi_device_pinmux_sleep_retention_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/c overage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_spi_device_pinmux_sleep_retention.3460257071
Directory	/workspace/2.chip_sw_spi_device_pinmux_sleep_retention/latest

Test location	/workspace/coverage/default/2.chip_sw_spi_device_tpm.2002876322
Short name	T60
Test name
Test status
Simulation time	3296675645 ps
CPU time	374.4 seconds
Started	Aug 14 05:59:54 PM PDT 24
Finished	Aug 14 06:06:08 PM PDT 24
Peak memory	620228 kb
Host	smart-748aac97-4a6b-4365-953b-b1fd373b6c61
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=spi_device_tpm_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2002876322 -assert nopostproc +UVM_T ESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_spi_device_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default .vdb -cm_log /dev/null -cm_name 2.chip_sw_spi_device_tpm.2002876322
Directory	/workspace/2.chip_sw_spi_device_tpm/latest

Test location	/workspace/coverage/default/2.chip_sw_spi_host_tx_rx.4212819594
Short name	T54
Test name
Test status
Simulation time	3169936338 ps
CPU time	296.13 seconds
Started	Aug 14 05:58:07 PM PDT 24
Finished	Aug 14 06:03:04 PM PDT 24
Peak memory	609676 kb
Host	smart-3573c9e5-fbbd-41d4-8ecc-f53fe775dcf2
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=spi_host_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4212819594 -assert nopostproc +UVM_TESTNAM E=chip_base_test +UVM_TEST_SEQ=chip_sw_spi_host_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb - cm_log /dev/null -cm_name 2.chip_sw_spi_host_tx_rx.4212819594
Directory	/workspace/2.chip_sw_spi_host_tx_rx/latest

Test location	/workspace/coverage/default/2.chip_sw_sram_ctrl_execution_main.2376986893
Short name	T194
Test name
Test status
Simulation time	7165538164 ps
CPU time	824 seconds
Started	Aug 14 06:07:18 PM PDT 24
Finished	Aug 14 06:21:03 PM PDT 24
Peak memory	610576 kb
Host	smart-8136f4b0-ec37-43aa-84f1-f15b2a116948
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=sram_ctrl_execution_main_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2376986893 -assert nopostproc +U VM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sram_ctrl_execution_main_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co verage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_sram_ctrl_execution_main.2376986893
Directory	/workspace/2.chip_sw_sram_ctrl_execution_main/latest

Test location	/workspace/coverage/default/2.chip_sw_sram_ctrl_scrambled_access_jitter_en.753575252
Short name	T874
Test name
Test status
Simulation time	5541601660 ps
CPU time	638.71 seconds
Started	Aug 14 06:03:30 PM PDT 24
Finished	Aug 14 06:14:10 PM PDT 24
Peak memory	611768 kb
Host	smart-7185f3e8-1487-4d4b-ab3d-4e4e4527c83a
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=12_000_000 +bypass_alert_ready_to_end_check=1 +en_jitter=1 +en_scb_tl_err_chk=0 +sw_build_device=sim_dv +s w_images=sram_ctrl_scrambled_access_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=753575252 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip _sw_sram_ctrl_scrambled_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na me 2.chip_sw_sram_ctrl_scrambled_access_jitter_en.753575252
Directory	/workspace/2.chip_sw_sram_ctrl_scrambled_access_jitter_en/latest

Test location	/workspace/coverage/default/2.chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq.2831869671
Short name	T120
Test name
Test status
Simulation time	5241976351 ps
CPU time	704.61 seconds
Started	Aug 14 06:06:10 PM PDT 24
Finished	Aug 14 06:17:55 PM PDT 24
Peak memory	610500 kb
Host	smart-cda0d0b9-0cf5-4533-b57f-a1519a516f0c
User	root
Command	/workspace/default/simv +mem_sel=main +sw_test_timeout_ns=12_000_000 +bypass_alert_ready_to_end_check=1 +en_jitter=1 +en_scb_tl_err_chk=0 +cal_sys_clk _70mhz=1 +sw_build_device=sim_dv +sw_images=sram_ctrl_scrambled_access_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2831869671 -assert nopostproc +UVM_TESTNA ME=chip_base_test +UVM_TEST_SEQ=chip_sw_sram_ctrl_scrambled_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/ default.vdb -cm_log /dev/null -cm_name 2.chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq.2831869671
Directory	/workspace/2.chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq/latest

Test location	/workspace/coverage/default/2.chip_sw_sram_ctrl_smoketest.2530374983
Short name	T977
Test name
Test status
Simulation time	2923396856 ps
CPU time	246.32 seconds
Started	Aug 14 06:07:06 PM PDT 24
Finished	Aug 14 06:11:13 PM PDT 24
Peak memory	609896 kb
Host	smart-031f95ba-bbcf-4412-96eb-4ca988054ec4
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=sram_ctrl_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2530374983 -assert nopostproc +UVM_TESTNAM E=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 2.chip_sw_sram_ctrl_smoketest.2530374983
Directory	/workspace/2.chip_sw_sram_ctrl_smoketest/latest

Test location	/workspace/coverage/default/2.chip_sw_sysrst_ctrl_ec_rst_l.2614301713
Short name	T895
Test name
Test status
Simulation time	19978471641 ps
CPU time	4370.36 seconds
Started	Aug 14 06:02:15 PM PDT 24
Finished	Aug 14 07:15:06 PM PDT 24
Peak memory	611068 kb
Host	smart-ff9267f6-1a99-4a8b-9331-8dcb68df6c6b
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=sysrst_ctrl_ec_rst_l_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2614301713 -assert nopostproc +UVM_T ESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sysrst_ctrl_ec_rst_l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/d efault.vdb -cm_log /dev/null -cm_name 2.chip_sw_sysrst_ctrl_ec_rst_l.2614301713
Directory	/workspace/2.chip_sw_sysrst_ctrl_ec_rst_l/latest

Test location	/workspace/coverage/default/2.chip_sw_sysrst_ctrl_in_irq.325561092
Short name	T894
Test name
Test status
Simulation time	4732238143 ps
CPU time	747.87 seconds
Started	Aug 14 06:01:18 PM PDT 24
Finished	Aug 14 06:13:48 PM PDT 24
Peak memory	614520 kb
Host	smart-49f9dc9b-4956-4072-99e8-81ab9c58c745
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=sysrst_ctrl_in_irq_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=325561092 -assert nopostproc +UVM_TEST NAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sysrst_ctrl_in_irq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul t.vdb -cm_log /dev/null -cm_name 2.chip_sw_sysrst_ctrl_in_irq.325561092
Directory	/workspace/2.chip_sw_sysrst_ctrl_in_irq/latest

Test location	/workspace/coverage/default/2.chip_sw_sysrst_ctrl_inputs.794436298
Short name	T962
Test name
Test status
Simulation time	3078174109 ps
CPU time	284.29 seconds
Started	Aug 14 06:01:25 PM PDT 24
Finished	Aug 14 06:06:10 PM PDT 24
Peak memory	614100 kb
Host	smart-8d9f2783-4b13-4669-b21e-ca426cf28b35
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=sysrst_ctrl_inputs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=794436298 -assert nopostproc +UVM_TEST NAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sysrst_ctrl_inputs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul t.vdb -cm_log /dev/null -cm_name 2.chip_sw_sysrst_ctrl_inputs.794436298
Directory	/workspace/2.chip_sw_sysrst_ctrl_inputs/latest

Test location	/workspace/coverage/default/2.chip_sw_sysrst_ctrl_outputs.4233579875
Short name	T256
Test name
Test status
Simulation time	3261807848 ps
CPU time	345.4 seconds
Started	Aug 14 06:01:34 PM PDT 24
Finished	Aug 14 06:07:20 PM PDT 24
Peak memory	610604 kb
Host	smart-89653ffd-d552-4acc-81ee-d10729b351e8
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=sysrst_ctrl_outputs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4233579875 -assert nopostproc +UVM_TE STNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sysrst_ctrl_outputs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def ault.vdb -cm_log /dev/null -cm_name 2.chip_sw_sysrst_ctrl_outputs.4233579875
Directory	/workspace/2.chip_sw_sysrst_ctrl_outputs/latest

Test location	/workspace/coverage/default/2.chip_sw_sysrst_ctrl_reset.210398001
Short name	T424
Test name
Test status
Simulation time	24136083054 ps
CPU time	1643.56 seconds
Started	Aug 14 06:01:42 PM PDT 24
Finished	Aug 14 06:29:06 PM PDT 24
Peak memory	615676 kb
Host	smart-e827590d-d626-4eae-ab1b-f1fc311e2349
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=36_000_000 +sw_build_device=sim_dv +sw_images=sysrst_ctrl_reset_test:1:new_rules,test_rom:0 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21039800 1 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sysrst_ctrl_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_sysrst_ctrl_reset.210398001
Directory	/workspace/2.chip_sw_sysrst_ctrl_reset/latest

Test location	/workspace/coverage/default/2.chip_sw_sysrst_ctrl_ulp_z3_wakeup.1688288219
Short name	T55
Test name
Test status
Simulation time	6677039960 ps
CPU time	470.33 seconds
Started	Aug 14 06:01:33 PM PDT 24
Finished	Aug 14 06:09:23 PM PDT 24
Peak memory	610480 kb
Host	smart-4ba3bf74-7758-4823-9d0a-1ec79098c61f
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=sysrst_ctrl_ulp_z3_wakeup_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1688288219 -assert nopostproc + UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sysrst_ctrl_ulp_z3_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/ coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_sysrst_ctrl_ulp_z3_wakeup.1688288219
Directory	/workspace/2.chip_sw_sysrst_ctrl_ulp_z3_wakeup/latest

Test location	/workspace/coverage/default/2.chip_sw_uart_rand_baudrate.4173428860
Short name	T864
Test name
Test status
Simulation time	8400653988 ps
CPU time	1436.97 seconds
Started	Aug 14 05:57:39 PM PDT 24
Finished	Aug 14 06:21:37 PM PDT 24
Peak memory	620172 kb
Host	smart-40827dcc-c701-4698-baed-1a235f09848e
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random _seed=4173428860 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_uart_rand_baudrate.4173428860
Directory	/workspace/2.chip_sw_uart_rand_baudrate/latest

Test location	/workspace/coverage/default/2.chip_sw_uart_smoketest.2736377752
Short name	T928
Test name
Test status
Simulation time	2656426158 ps
CPU time	211.82 seconds
Started	Aug 14 06:07:22 PM PDT 24
Finished	Aug 14 06:10:54 PM PDT 24
Peak memory	612660 kb
Host	smart-eada38e8-7569-4d37-8eec-5f9bdcae141a
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=uart_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2736377752 -assert nopostproc +UVM_TESTNAME=chi p_base_test +UVM_TEST_SEQ=chip_sw_uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 2.chip_sw_uart_smoketest.2736377752
Directory	/workspace/2.chip_sw_uart_smoketest/latest

Test location	/workspace/coverage/default/2.chip_sw_uart_tx_rx.819885283
Short name	T932
Test name
Test status
Simulation time	4161300360 ps
CPU time	731.64 seconds
Started	Aug 14 05:56:55 PM PDT 24
Finished	Aug 14 06:09:07 PM PDT 24
Peak memory	624348 kb
Host	smart-f24447af-32a0-4711-b6eb-4a96b6e09319
User	root
Command	/workspace/default/simv +uart_idx=0 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=819885283 -as sert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac e/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_uart_tx_rx.819885283
Directory	/workspace/2.chip_sw_uart_tx_rx/latest

Test location	/workspace/coverage/default/2.chip_sw_uart_tx_rx_alt_clk_freq.3681957008
Short name	T841
Test name
Test status
Simulation time	4781502336 ps
CPU time	624.29 seconds
Started	Aug 14 05:57:52 PM PDT 24
Finished	Aug 14 06:08:17 PM PDT 24
Peak memory	625064 kb
Host	smart-51fc9e61-a2c5-431a-b218-369effe6e355
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=80_000_000 +chip_clock_source=ChipClockSourceExternal96Mhz +calibrate_usb_clk=1 +sw_build_device=sim_dv +s w_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3681957008 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_b audrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_uart_tx_rx _alt_clk_freq.3681957008
Directory	/workspace/2.chip_sw_uart_tx_rx_alt_clk_freq/latest

Test location	/workspace/coverage/default/2.chip_sw_uart_tx_rx_alt_clk_freq_low_speed.3889957345
Short name	T888
Test name
Test status
Simulation time	4642367982 ps
CPU time	589.72 seconds
Started	Aug 14 05:58:46 PM PDT 24
Finished	Aug 14 06:08:36 PM PDT 24
Peak memory	619640 kb
Host	smart-93b27341-0bc9-41d4-9be4-ac536b8ab650
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +chip_clock_source=ChipClockSourceExternal48Mhz +sw_build_device=sim_dv +s w_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3889957345 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_b audrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_uart_tx_rx _alt_clk_freq_low_speed.3889957345
Directory	/workspace/2.chip_sw_uart_tx_rx_alt_clk_freq_low_speed/latest

Test location	/workspace/coverage/default/2.chip_sw_uart_tx_rx_bootstrap.3213329710
Short name	T770
Test name
Test status
Simulation time	78450428062 ps
CPU time	13118.2 seconds
Started	Aug 14 05:56:16 PM PDT 24
Finished	Aug 14 09:34:56 PM PDT 24
Peak memory	634576 kb
Host	smart-ea073291-9b35-4d44-a7ce-24aa2d748089
User	root
Command	/workspace/default/simv +use_spi_load_bootstrap=1 +calibrate_usb_clk=1 +test_timeout_ns=160_000_000 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test :1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=3213329710 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_uart_tx_rx_bootstrap.3213329710
Directory	/workspace/2.chip_sw_uart_tx_rx_bootstrap/latest

Test location	/workspace/coverage/default/2.chip_sw_uart_tx_rx_idx1.2716293055
Short name	T1025
Test name
Test status
Simulation time	4196753988 ps
CPU time	760.05 seconds
Started	Aug 14 05:58:49 PM PDT 24
Finished	Aug 14 06:11:31 PM PDT 24
Peak memory	620528 kb
Host	smart-25a6822c-73a0-43f2-b240-108b77af8646
User	root
Command	/workspace/default/simv +uart_idx=1 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2716293055 -a ssert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ce/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_uart_tx_rx_idx1.2716293055
Directory	/workspace/2.chip_sw_uart_tx_rx_idx1/latest

Test location	/workspace/coverage/default/2.chip_sw_uart_tx_rx_idx2.1680419242
Short name	T959
Test name
Test status
Simulation time	4115252694 ps
CPU time	787.58 seconds
Started	Aug 14 05:59:13 PM PDT 24
Finished	Aug 14 06:12:21 PM PDT 24
Peak memory	624696 kb
Host	smart-85d3fb14-314f-49fe-beb2-b9dab948be04
User	root
Command	/workspace/default/simv +uart_idx=2 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1680419242 -a ssert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ce/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_uart_tx_rx_idx2.1680419242
Directory	/workspace/2.chip_sw_uart_tx_rx_idx2/latest

Test location	/workspace/coverage/default/2.chip_sw_uart_tx_rx_idx3.2414558176
Short name	T798
Test name
Test status
Simulation time	4339356454 ps
CPU time	590.99 seconds
Started	Aug 14 05:56:20 PM PDT 24
Finished	Aug 14 06:06:12 PM PDT 24
Peak memory	624384 kb
Host	smart-11505f43-70d8-4f7f-a8bc-97457638fde3
User	root
Command	/workspace/default/simv +uart_idx=3 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2414558176 -a ssert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ce/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_uart_tx_rx_idx3.2414558176
Directory	/workspace/2.chip_sw_uart_tx_rx_idx3/latest

Test location	/workspace/coverage/default/2.chip_tap_straps_prod.1242323927
Short name	T665
Test name
Test status
Simulation time	2064200774 ps
CPU time	145.3 seconds
Started	Aug 14 06:04:34 PM PDT 24
Finished	Aug 14 06:07:00 PM PDT 24
Peak memory	624612 kb
Host	smart-487d5515-56bf-4bd8-aa94-701e318ad15d
User	root
Command	/workspace/default/simv +use_otp_image=OtpTypeLcStProd +create_jtag_riscv_map=1 +sw_build_device=sim_dv +sw_images=example_test_from_rom:0:test_in_rom :new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1242323927 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_tap_straps_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_tap_straps_prod.1242323927
Directory	/workspace/2.chip_tap_straps_prod/latest

Test location	/workspace/coverage/default/2.chip_tap_straps_rma.2451885209
Short name	T12
Test name
Test status
Simulation time	4501640124 ps
CPU time	433.79 seconds
Started	Aug 14 06:04:03 PM PDT 24
Finished	Aug 14 06:11:18 PM PDT 24
Peak memory	633784 kb
Host	smart-e056fbe8-ceba-446e-9272-cebead2afbaf
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +sw_build_device=sim_dv +sw_images=example_test_from_rom:0:test_in_rom:new_rules +cdc_instrumentation _enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2451885209 -as sert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_tap_straps_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/c overage/default.vdb -cm_log /dev/null -cm_name 2.chip_tap_straps_rma.2451885209
Directory	/workspace/2.chip_tap_straps_rma/latest

Test location	/workspace/coverage/default/2.chip_tap_straps_testunlock0.609902902
Short name	T598
Test name
Test status
Simulation time	2944422621 ps
CPU time	254.94 seconds
Started	Aug 14 06:05:11 PM PDT 24
Finished	Aug 14 06:09:26 PM PDT 24
Peak memory	625692 kb
Host	smart-8f17b151-a615-4587-9914-2bb07ea667c1
User	root
Command	/workspace/default/simv +use_otp_image=OtpTypeLcStTestUnlocked0 +create_jtag_riscv_map=1 +sw_build_device=sim_dv +sw_images=example_test_from_rom:0:te st_in_rom:new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=609902902 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_tap_straps_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_tap_straps_testunlock0.609902902
Directory	/workspace/2.chip_tap_straps_testunlock0/latest

Test location	/workspace/coverage/default/2.rom_e2e_asm_init_dev.616156740
Short name	T625
Test name
Test status
Simulation time	16019407120 ps
CPU time	3087.55 seconds
Started	Aug 14 06:10:47 PM PDT 24
Finished	Aug 14 07:02:15 PM PDT 24
Peak memory	610948 kb
Host	smart-5a004676-afe9-4599-95bd-9aa46c3dc0ca
User	root
Command	/workspace/default/simv +use_otp_image=OtpTypeCustom +sw_test_timeout_ns=20000000 +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_prod _key_0:1:ot_flash_binary,otp_img_e2e_bootstrap_entry_dev:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=616156740 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SE Q=chip_sw_rom_e2e_asm_init_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2 .rom_e2e_asm_init_dev.616156740
Directory	/workspace/2.rom_e2e_asm_init_dev/latest

Test location	/workspace/coverage/default/2.rom_e2e_asm_init_prod.635940861
Short name	T767
Test name
Test status
Simulation time	15587348618 ps
CPU time	3649.65 seconds
Started	Aug 14 06:10:43 PM PDT 24
Finished	Aug 14 07:11:34 PM PDT 24
Peak memory	610688 kb
Host	smart-988b391d-7e68-4d01-847d-9f08ae972a89
User	root
Command	/workspace/default/simv +use_otp_image=OtpTypeCustom +sw_test_timeout_ns=20000000 +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_prod _key_0:1:ot_flash_binary,otp_img_e2e_bootstrap_entry_prod:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=635940861 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_S EQ=chip_sw_rom_e2e_asm_init_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_e2e_asm_init_prod.635940861
Directory	/workspace/2.rom_e2e_asm_init_prod/latest

Test location	/workspace/coverage/default/2.rom_e2e_asm_init_prod_end.2957632304
Short name	T722
Test name
Test status
Simulation time	16087214780 ps
CPU time	3721.53 seconds
Started	Aug 14 06:14:54 PM PDT 24
Finished	Aug 14 07:16:56 PM PDT 24
Peak memory	610908 kb
Host	smart-7b09dfcf-ee28-4edc-bb60-d52c5329b0cd
User	root
Command	/workspace/default/simv +use_otp_image=OtpTypeCustom +sw_test_timeout_ns=20000000 +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_prod _key_0:1:ot_flash_binary,otp_img_e2e_bootstrap_entry_prod_end:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2957632304 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_T EST_SEQ=chip_sw_rom_e2e_asm_init_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 2.rom_e2e_asm_init_prod_end.2957632304
Directory	/workspace/2.rom_e2e_asm_init_prod_end/latest

Test location	/workspace/coverage/default/2.rom_e2e_asm_init_rma.1392902459
Short name	T1029
Test name
Test status
Simulation time	15701049920 ps
CPU time	4546.38 seconds
Started	Aug 14 06:10:34 PM PDT 24
Finished	Aug 14 07:26:22 PM PDT 24
Peak memory	611008 kb
Host	smart-b784976c-0976-4c4f-9a50-fadeb4682c7b
User	root
Command	/workspace/default/simv +use_otp_image=OtpTypeCustom +sw_test_timeout_ns=20000000 +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_prod _key_0:1:ot_flash_binary,otp_img_e2e_bootstrap_entry_rma:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1392902459 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_S EQ=chip_sw_rom_e2e_asm_init_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_e2e_asm_init_rma.1392902459
Directory	/workspace/2.rom_e2e_asm_init_rma/latest

Test location	/workspace/coverage/default/2.rom_e2e_asm_init_test_unlocked0.2358822811
Short name	T585
Test name
Test status
Simulation time	11420974738 ps
CPU time	2610.4 seconds
Started	Aug 14 06:12:24 PM PDT 24
Finished	Aug 14 06:55:55 PM PDT 24
Peak memory	610548 kb
Host	smart-fe525e59-fe90-4656-a83b-d02463401ebe
User	root
Command	/workspace/default/simv +use_otp_image=OtpTypeCustom +sw_test_timeout_ns=410_000_000 +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_p rod_key_0:1:ot_flash_binary,otp_img_e2e_bootstrap_entry_test_unlocked0:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY =UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2358822811 -assert nopostproc +UVM_TESTNAME=chip_base_te st +UVM_TEST_SEQ=chip_sw_rom_e2e_asm_init_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/ null -cm_name 2.rom_e2e_asm_init_test_unlocked0.2358822811
Directory	/workspace/2.rom_e2e_asm_init_test_unlocked0/latest

Test location	/workspace/coverage/default/2.rom_e2e_keymgr_init_rom_ext_invalid_meas.4149538037
Short name	T634
Test name
Test status
Simulation time	15166137210 ps
CPU time	3279.24 seconds
Started	Aug 14 06:11:43 PM PDT 24
Finished	Aug 14 07:06:23 PM PDT 24
Peak memory	610812 kb
Host	smart-56c2d558-0022-49fc-a314-0c2bffab8954
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=40_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=rom_e2e_keymgr_init_otp_invalid _meas:1:new_rules,otp_img_keymgr_otp_invalid_meas:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4149538037 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip _sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_e2e_keymgr_in it_rom_ext_invalid_meas.4149538037
Directory	/workspace/2.rom_e2e_keymgr_init_rom_ext_invalid_meas/latest

Test location	/workspace/coverage/default/2.rom_e2e_keymgr_init_rom_ext_meas.586172961
Short name	T1003
Test name
Test status
Simulation time	15737198600 ps
CPU time	4056.18 seconds
Started	Aug 14 06:11:28 PM PDT 24
Finished	Aug 14 07:19:04 PM PDT 24
Peak memory	610940 kb
Host	smart-fc036860-cd8e-4340-85e3-832f61184e5a
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=40_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=rom_e2e_keymgr_init_otp_meas:1: new_rules,otp_img_keymgr_otp_meas:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=586172961 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_e2e_keymgr_init_rom_ext_meas.586172961
Directory	/workspace/2.rom_e2e_keymgr_init_rom_ext_meas/latest

Test location	/workspace/coverage/default/2.rom_e2e_keymgr_init_rom_ext_no_meas.3587168177
Short name	T397
Test name
Test status
Simulation time	15137461264 ps
CPU time	3615.94 seconds
Started	Aug 14 06:13:33 PM PDT 24
Finished	Aug 14 07:13:50 PM PDT 24
Peak memory	610800 kb
Host	smart-bbdbbb59-ae89-46de-87eb-d2d0cdf7dd56
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=40_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=rom_e2e_keymgr_init_otp_no_meas :1:new_rules,otp_img_keymgr_otp_no_meas:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3587168177 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_e2e_keymgr_init_rom_ext _no_meas.3587168177
Directory	/workspace/2.rom_e2e_keymgr_init_rom_ext_no_meas/latest

Test location	/workspace/coverage/default/2.rom_e2e_self_hash.948315323
Short name	T638
Test name
Test status
Simulation time	26327198516 ps
CPU time	5485.92 seconds
Started	Aug 14 06:13:36 PM PDT 24
Finished	Aug 14 07:45:02 PM PDT 24
Peak memory	610940 kb
Host	smart-65caaee7-8893-4169-b575-f1057dc890eb
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=200_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=rom_e2e_self_hash_test:1:new_r ules,otp_img_sigverify_spx_prod:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=948315323 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_e2e_self_hash.948315323
Directory	/workspace/2.rom_e2e_self_hash/latest

Test location	/workspace/coverage/default/2.rom_e2e_shutdown_exception_c.4225766210
Short name	T268
Test name
Test status
Simulation time	14265715285 ps
CPU time	3320.53 seconds
Started	Aug 14 06:11:01 PM PDT 24
Finished	Aug 14 07:06:22 PM PDT 24
Peak memory	612280 kb
Host	smart-9c6c5305-6bc6-47d4-a6fa-c7e398d8e19f
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=40000000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=rom_e2e_shutdown_exception_c:1:ne w_rules,otp_img_secret2_locked_rma:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4225766210 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rom_e2e_shu tdown_exception_c_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_e2e_ shutdown_exception_c.4225766210
Directory	/workspace/2.rom_e2e_shutdown_exception_c/latest

Test location	/workspace/coverage/default/2.rom_e2e_shutdown_output.3207959012
Short name	T919
Test name
Test status
Simulation time	23307533907 ps
CPU time	3560.31 seconds
Started	Aug 14 06:11:39 PM PDT 24
Finished	Aug 14 07:11:00 PM PDT 24
Peak memory	612256 kb
Host	smart-09804177-13e3-4b82-84e3-d0c5b5f799f2
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=20000000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_unsigned:1:ot_f lash_binary,otp_img_shutdown_output_test_unlocked0:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3207959012 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chi p_sw_rom_e2e_shutdown_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_e2e_shutdown_output.3207959012
Directory	/workspace/2.rom_e2e_shutdown_output/latest

Test location	/workspace/coverage/default/2.rom_e2e_smoke.1407146013
Short name	T927
Test name
Test status
Simulation time	14510883386 ps
CPU time	3063.85 seconds
Started	Aug 14 06:14:45 PM PDT 24
Finished	Aug 14 07:05:49 PM PDT 24
Peak memory	610760 kb
Host	smart-63418577-534b-4437-a765-1bbe24d63210
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=40000000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=rom_e2e_smoke:1:new_rules,otp_img _secret2_locked_rma:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_to p/hw/dv/tools/sim.tcl +ntb_random_seed=1407146013 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_e2e_smoke.1407146013
Directory	/workspace/2.rom_e2e_smoke/latest

Test location	/workspace/coverage/default/2.rom_e2e_static_critical.846814898
Short name	T764
Test name
Test status
Simulation time	16778661368 ps
CPU time	3701.44 seconds
Started	Aug 14 06:11:26 PM PDT 24
Finished	Aug 14 07:13:08 PM PDT 24
Peak memory	610644 kb
Host	smart-8a020880-1d6d-4979-86a5-dca38aefecfd
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=40000000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=rom_e2e_static_critical:1:new_rul es,otp_img_secret2_locked_rma:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=846814898 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_e2e_static_critical.846814898
Directory	/workspace/2.rom_e2e_static_critical/latest

Test location	/workspace/coverage/default/2.rom_keymgr_functest.3539318608
Short name	T648
Test name
Test status
Simulation time	3501180234 ps
CPU time	582 seconds
Started	Aug 14 06:07:10 PM PDT 24
Finished	Aug 14 06:16:53 PM PDT 24
Peak memory	610300 kb
Host	smart-3b4259d7-cbf6-4f76-ae7d-3d6f4709eb22
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=10_000_000 +sw_build_device=sim_dv +sw_images=keymgr_functest:1:new_rules,test_rom:0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3539318608 -ass ert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 2.rom_keymgr_functest.3539318608
Directory	/workspace/2.rom_keymgr_functest/latest

Test location	/workspace/coverage/default/2.rom_raw_unlock.2679466945
Short name	T202
Test name
Test status
Simulation time	5144064192 ps
CPU time	259.4 seconds
Started	Aug 14 06:06:34 PM PDT 24
Finished	Aug 14 06:10:54 PM PDT 24
Peak memory	620344 kb
Host	smart-3717cdc9-82b2-4543-806a-724463326a9a
User	root
Command	/workspace/default/simv +do_creator_sw_cfg_ast_cfg=0 +sw_test_timeout_ns=200_000_000 +use_otp_image=OtpTypeLcStRaw +chip_clock_source=ChipClockSourceE xternal48Mhz +rom_prod_mode=1 +use_jtag_dmi=1 +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_test_key_0:1:ot_flash_binary,mask_ro m:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=2679466945 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_raw_unlock_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_raw_unlock.2679466945
Directory	/workspace/2.rom_raw_unlock/latest

Test location	/workspace/coverage/default/2.rom_volatile_raw_unlock.1510844559
Short name	T288
Test name
Test status
Simulation time	2342765112 ps
CPU time	115.54 seconds
Started	Aug 14 06:06:57 PM PDT 24
Finished	Aug 14 06:08:53 PM PDT 24
Peak memory	617972 kb
Host	smart-dda498f3-ae85-4405-8902-fce106003a82
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=200_000_000 +use_otp_image=OtpTypeLcStRaw +chip_clock_source=ChipClockSourceExternal48Mhz +rom_prod_mode=1 +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_test_key_0:1:ot_flash_binary,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1510844559 -assert nopostproc +UVM_ TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_volatile_raw_unlock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag e/default.vdb -cm_log /dev/null -cm_name 2.rom_volatile_raw_unlock.1510844559
Directory	/workspace/2.rom_volatile_raw_unlock/latest

Test location	/workspace/coverage/default/20.chip_sw_alert_handler_lpg_sleep_mode_alerts.3427628434
Short name	T106
Test name
Test status
Simulation time	3489689214 ps
CPU time	401.64 seconds
Started	Aug 14 06:13:20 PM PDT 24
Finished	Aug 14 06:20:01 PM PDT 24
Peak memory	650140 kb
Host	smart-bdbac45b-9aa3-44a6-a8b4-a0d8419a1baf
User	root
Command	/workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrlstate_regs +avoid_ferr_ips_append=otp_ctrlu_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3427628434 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.chip_ sw_alert_handler_lpg_sleep_mode_alerts.3427628434
Directory	/workspace/20.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location	/workspace/coverage/default/22.chip_sw_alert_handler_lpg_sleep_mode_alerts.2238890551
Short name	T876
Test name
Test status
Simulation time	3950805810 ps
CPU time	353.72 seconds
Started	Aug 14 06:13:09 PM PDT 24
Finished	Aug 14 06:19:03 PM PDT 24
Peak memory	649568 kb
Host	smart-8de2c724-9467-41aa-aaac-ccfd3a5b45f4
User	root
Command	/workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrlstate_regs +avoid_ferr_ips_append=otp_ctrlu_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2238890551 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.chip_ sw_alert_handler_lpg_sleep_mode_alerts.2238890551
Directory	/workspace/22.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location	/workspace/coverage/default/22.chip_sw_all_escalation_resets.1971381781
Short name	T599
Test name
Test status
Simulation time	4430311676 ps
CPU time	744.08 seconds
Started	Aug 14 06:10:39 PM PDT 24
Finished	Aug 14 06:23:04 PM PDT 24
Peak memory	650736 kb
Host	smart-755463b6-f2c3-4a46-b6b5-38b2ed866eb0
User	root
Command	/workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 1971381781 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.chip_sw_all_escalation_resets.1971381781
Directory	/workspace/22.chip_sw_all_escalation_resets/latest

Test location	/workspace/coverage/default/23.chip_sw_alert_handler_lpg_sleep_mode_alerts.235544124
Short name	T448
Test name
Test status
Simulation time	4340940564 ps
CPU time	406.13 seconds
Started	Aug 14 06:11:42 PM PDT 24
Finished	Aug 14 06:18:28 PM PDT 24
Peak memory	649928 kb
Host	smart-4ef3301c-07b1-4fef-9822-126900d6da47
User	root
Command	/workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrlstate_regs +avoid_ferr_ips_append=otp_ctrlu_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=235544124 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all _escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.chip_s w_alert_handler_lpg_sleep_mode_alerts.235544124
Directory	/workspace/23.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location	/workspace/coverage/default/25.chip_sw_alert_handler_lpg_sleep_mode_alerts.3476271838
Short name	T538
Test name
Test status
Simulation time	3814162590 ps
CPU time	614.24 seconds
Started	Aug 14 06:14:02 PM PDT 24
Finished	Aug 14 06:24:17 PM PDT 24
Peak memory	649308 kb
Host	smart-69584fbc-09c1-4b7e-8b94-0d44f3ccd825
User	root
Command	/workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrlstate_regs +avoid_ferr_ips_append=otp_ctrlu_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3476271838 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.chip_ sw_alert_handler_lpg_sleep_mode_alerts.3476271838
Directory	/workspace/25.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location	/workspace/coverage/default/25.chip_sw_all_escalation_resets.2115038786
Short name	T549
Test name
Test status
Simulation time	4781822104 ps
CPU time	632.61 seconds
Started	Aug 14 06:11:03 PM PDT 24
Finished	Aug 14 06:21:36 PM PDT 24
Peak memory	650720 kb
Host	smart-50621e5a-50b2-42d6-a1e2-3147d3eb7d47
User	root
Command	/workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 2115038786 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.chip_sw_all_escalation_resets.2115038786
Directory	/workspace/25.chip_sw_all_escalation_resets/latest

Test location	/workspace/coverage/default/28.chip_sw_alert_handler_lpg_sleep_mode_alerts.269797760
Short name	T498
Test name
Test status
Simulation time	3878929064 ps
CPU time	446.44 seconds
Started	Aug 14 06:12:04 PM PDT 24
Finished	Aug 14 06:19:30 PM PDT 24
Peak memory	649972 kb
Host	smart-20c32eb4-08c6-40ab-9048-3eea7f05f441
User	root
Command	/workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrlstate_regs +avoid_ferr_ips_append=otp_ctrlu_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=269797760 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all _escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.chip_s w_alert_handler_lpg_sleep_mode_alerts.269797760
Directory	/workspace/28.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location	/workspace/coverage/default/29.chip_sw_alert_handler_lpg_sleep_mode_alerts.3439195794
Short name	T239
Test name
Test status
Simulation time	4139039224 ps
CPU time	441.53 seconds
Started	Aug 14 06:11:38 PM PDT 24
Finished	Aug 14 06:18:59 PM PDT 24
Peak memory	649480 kb
Host	smart-ff5731eb-3f52-4adb-882f-ef45be07f0f2
User	root
Command	/workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrlstate_regs +avoid_ferr_ips_append=otp_ctrlu_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3439195794 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.chip_ sw_alert_handler_lpg_sleep_mode_alerts.3439195794
Directory	/workspace/29.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location	/workspace/coverage/default/29.chip_sw_all_escalation_resets.1899269918
Short name	T511
Test name
Test status
Simulation time	4550763656 ps
CPU time	517.62 seconds
Started	Aug 14 06:13:00 PM PDT 24
Finished	Aug 14 06:21:38 PM PDT 24
Peak memory	650828 kb
Host	smart-daf80a5c-3777-4a56-94b5-4ac7ee150e6c
User	root
Command	/workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 1899269918 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.chip_sw_all_escalation_resets.1899269918
Directory	/workspace/29.chip_sw_all_escalation_resets/latest

Test location	/workspace/coverage/default/3.chip_sw_aon_timer_sleep_wdog_sleep_pause.2578331079
Short name	T1032
Test name
Test status
Simulation time	6973883780 ps
CPU time	512.02 seconds
Started	Aug 14 06:09:04 PM PDT 24
Finished	Aug 14 06:17:36 PM PDT 24
Peak memory	611124 kb
Host	smart-88fb9ede-defa-4ec4-8618-aa6b97a9f29e
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=aon_timer_sleep_wdog_sleep_pause_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=2578331079 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.chip_sw_aon_timer_sleep_wdog_sleep_pause.2578331079
Directory	/workspace/3.chip_sw_aon_timer_sleep_wdog_sleep_pause/latest

Test location	/workspace/coverage/default/3.chip_sw_csrng_edn_concurrency.2967883229
Short name	T610
Test name
Test status
Simulation time	21922515670 ps
CPU time	5274.59 seconds
Started	Aug 14 06:08:51 PM PDT 24
Finished	Aug 14 07:36:46 PM PDT 24
Peak memory	610868 kb
Host	smart-699f6c9a-d718-4b1e-a414-57d29e875f2d
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=140_000_000 +rng_srate_value_min=15 +rng_srate_value_max=20 +accelerate_cold_power_up_time=3 +accelerate_r egulators_power_up_time=2 +sw_build_device=sim_dv +sw_images=csrng_edn_concurrency_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2967883229 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd b -cm_log /dev/null -cm_name 3.chip_sw_csrng_edn_concurrency.2967883229
Directory	/workspace/3.chip_sw_csrng_edn_concurrency/latest

Test location	/workspace/coverage/default/3.chip_sw_data_integrity_escalation.647915258
Short name	T258
Test name
Test status
Simulation time	5595564160 ps
CPU time	618.68 seconds
Started	Aug 14 06:09:35 PM PDT 24
Finished	Aug 14 06:19:54 PM PDT 24
Peak memory	611936 kb
Host	smart-c511eed0-2169-45d1-945c-aac10a82b785
User	root
Command	/workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=data_integrity_escalation_reset_test:1:new_rules,test_ro m:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=647915258 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_data_integrity_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.chip_sw_data_integrity_escalation.647915258
Directory	/workspace/3.chip_sw_data_integrity_escalation/latest

Test location	/workspace/coverage/default/3.chip_sw_lc_ctrl_transition.3404080601
Short name	T706
Test name
Test status
Simulation time	6112042691 ps
CPU time	557.87 seconds
Started	Aug 14 06:11:33 PM PDT 24
Finished	Aug 14 06:20:52 PM PDT 24
Peak memory	622084 kb
Host	smart-6354859f-3142-4b07-8430-4b849cb3e935
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=lc_ctrl_transition_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3404080601 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_transition_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau lt.vdb -cm_log /dev/null -cm_name 3.chip_sw_lc_ctrl_transition.3404080601
Directory	/workspace/3.chip_sw_lc_ctrl_transition/latest

Test location	/workspace/coverage/default/3.chip_sw_sensor_ctrl_alert.3398822976
Short name	T146
Test name
Test status
Simulation time	6951373780 ps
CPU time	1063.99 seconds
Started	Aug 14 06:08:30 PM PDT 24
Finished	Aug 14 06:26:15 PM PDT 24
Peak memory	611176 kb
Host	smart-c1f0ccbd-422d-440d-9b24-85a92f1e506a
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=40_000_000 +sw_build_device=sim_dv +sw_images=sensor_ctrl_alert_test:1:new_rules,test_rom:0 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33988229 76 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac e/coverage/default.vdb -cm_log /dev/null -cm_name 3.chip_sw_sensor_ctrl_alert.3398822976
Directory	/workspace/3.chip_sw_sensor_ctrl_alert/latest

Test location	/workspace/coverage/default/3.chip_sw_uart_rand_baudrate.1466048274
Short name	T347
Test name
Test status
Simulation time	3874416340 ps
CPU time	533.62 seconds
Started	Aug 14 06:07:02 PM PDT 24
Finished	Aug 14 06:15:56 PM PDT 24
Peak memory	620180 kb
Host	smart-b598a796-f847-499a-9455-599827e27bbf
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random _seed=1466048274 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.chip_sw_uart_rand_baudrate.1466048274
Directory	/workspace/3.chip_sw_uart_rand_baudrate/latest

Test location	/workspace/coverage/default/3.chip_sw_uart_tx_rx.3202699615
Short name	T326
Test name
Test status
Simulation time	4611501774 ps
CPU time	539.26 seconds
Started	Aug 14 06:10:35 PM PDT 24
Finished	Aug 14 06:19:35 PM PDT 24
Peak memory	624612 kb
Host	smart-1a2bd0cd-0ba7-4372-97cb-453fcdc6f27b
User	root
Command	/workspace/default/simv +uart_idx=0 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3202699615 -a ssert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ce/coverage/default.vdb -cm_log /dev/null -cm_name 3.chip_sw_uart_tx_rx.3202699615
Directory	/workspace/3.chip_sw_uart_tx_rx/latest

Test location	/workspace/coverage/default/3.chip_sw_uart_tx_rx_alt_clk_freq.871099847
Short name	T821
Test name
Test status
Simulation time	7842724082 ps
CPU time	1319.04 seconds
Started	Aug 14 06:08:43 PM PDT 24
Finished	Aug 14 06:30:43 PM PDT 24
Peak memory	619436 kb
Host	smart-df86c652-0dab-4b40-9b4b-64522be16e18
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=80_000_000 +chip_clock_source=ChipClockSourceExternal96Mhz +calibrate_usb_clk=1 +sw_build_device=sim_dv +s w_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=871099847 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_ba udrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.chip_sw_uart_tx_rx_ alt_clk_freq.871099847
Directory	/workspace/3.chip_sw_uart_tx_rx_alt_clk_freq/latest

Test location	/workspace/coverage/default/3.chip_sw_uart_tx_rx_alt_clk_freq_low_speed.2156560717
Short name	T838
Test name
Test status
Simulation time	4425249365 ps
CPU time	473.53 seconds
Started	Aug 14 06:07:49 PM PDT 24
Finished	Aug 14 06:15:43 PM PDT 24
Peak memory	625068 kb
Host	smart-fcb44887-807e-4899-9377-2e085f4cb8f7
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +chip_clock_source=ChipClockSourceExternal48Mhz +sw_build_device=sim_dv +s w_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2156560717 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_b audrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.chip_sw_uart_tx_rx _alt_clk_freq_low_speed.2156560717
Directory	/workspace/3.chip_sw_uart_tx_rx_alt_clk_freq_low_speed/latest

Test location	/workspace/coverage/default/3.chip_sw_uart_tx_rx_idx1.3187960783
Short name	T345
Test name
Test status
Simulation time	4448577266 ps
CPU time	574.75 seconds
Started	Aug 14 06:07:14 PM PDT 24
Finished	Aug 14 06:16:50 PM PDT 24
Peak memory	624932 kb
Host	smart-54020d5b-552b-469f-b9fb-0b28e53a3836
User	root
Command	/workspace/default/simv +uart_idx=1 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3187960783 -a ssert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ce/coverage/default.vdb -cm_log /dev/null -cm_name 3.chip_sw_uart_tx_rx_idx1.3187960783
Directory	/workspace/3.chip_sw_uart_tx_rx_idx1/latest

Test location	/workspace/coverage/default/3.chip_sw_uart_tx_rx_idx2.2429584227
Short name	T360
Test name
Test status
Simulation time	4243547990 ps
CPU time	568.67 seconds
Started	Aug 14 06:08:46 PM PDT 24
Finished	Aug 14 06:18:15 PM PDT 24
Peak memory	620524 kb
Host	smart-91aca250-13fb-4d9d-a473-d2f97dbdbdd9
User	root
Command	/workspace/default/simv +uart_idx=2 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2429584227 -a ssert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ce/coverage/default.vdb -cm_log /dev/null -cm_name 3.chip_sw_uart_tx_rx_idx2.2429584227
Directory	/workspace/3.chip_sw_uart_tx_rx_idx2/latest

Test location	/workspace/coverage/default/3.chip_sw_uart_tx_rx_idx3.3525509453
Short name	T911
Test name
Test status
Simulation time	3781330710 ps
CPU time	677.82 seconds
Started	Aug 14 06:10:47 PM PDT 24
Finished	Aug 14 06:22:05 PM PDT 24
Peak memory	620536 kb
Host	smart-a4687dc5-d034-4b2d-a25f-305bd309f56b
User	root
Command	/workspace/default/simv +uart_idx=3 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3525509453 -a ssert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ce/coverage/default.vdb -cm_log /dev/null -cm_name 3.chip_sw_uart_tx_rx_idx3.3525509453
Directory	/workspace/3.chip_sw_uart_tx_rx_idx3/latest

Test location	/workspace/coverage/default/3.chip_tap_straps_dev.2265259003
Short name	T674
Test name
Test status
Simulation time	11465461317 ps
CPU time	1119.07 seconds
Started	Aug 14 06:08:31 PM PDT 24
Finished	Aug 14 06:27:10 PM PDT 24
Peak memory	625668 kb
Host	smart-c22c6b97-7a76-4dfc-ae65-50f9050f81be
User	root
Command	/workspace/default/simv +use_otp_image=OtpTypeLcStDev +create_jtag_riscv_map=1 +sw_build_device=sim_dv +sw_images=example_test_from_rom:0:test_in_rom: new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=2265259003 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_tap_straps_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.chip_tap_straps_dev.2265259003
Directory	/workspace/3.chip_tap_straps_dev/latest

Test location	/workspace/coverage/default/3.chip_tap_straps_prod.3251704198
Short name	T612
Test name
Test status
Simulation time	2947424672 ps
CPU time	161.64 seconds
Started	Aug 14 06:07:24 PM PDT 24
Finished	Aug 14 06:10:05 PM PDT 24
Peak memory	625120 kb
Host	smart-afbcd52e-fb35-46e2-9e32-fc25c8b9189b
User	root
Command	/workspace/default/simv +use_otp_image=OtpTypeLcStProd +create_jtag_riscv_map=1 +sw_build_device=sim_dv +sw_images=example_test_from_rom:0:test_in_rom :new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3251704198 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_tap_straps_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.chip_tap_straps_prod.3251704198
Directory	/workspace/3.chip_tap_straps_prod/latest

Test location	/workspace/coverage/default/3.chip_tap_straps_rma.1519312073
Short name	T95
Test name
Test status
Simulation time	4044264381 ps
CPU time	252.59 seconds
Started	Aug 14 06:07:05 PM PDT 24
Finished	Aug 14 06:11:18 PM PDT 24
Peak memory	625656 kb
Host	smart-adf1f443-8b95-45e8-8d5a-3159b2dce146
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +sw_build_device=sim_dv +sw_images=example_test_from_rom:0:test_in_rom:new_rules +cdc_instrumentation _enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1519312073 -as sert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_tap_straps_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/c overage/default.vdb -cm_log /dev/null -cm_name 3.chip_tap_straps_rma.1519312073
Directory	/workspace/3.chip_tap_straps_rma/latest

Test location	/workspace/coverage/default/3.chip_tap_straps_testunlock0.1083174402
Short name	T975
Test name
Test status
Simulation time	9435610453 ps
CPU time	847.32 seconds
Started	Aug 14 06:08:26 PM PDT 24
Finished	Aug 14 06:22:33 PM PDT 24
Peak memory	633888 kb
Host	smart-7159beee-12cf-4576-aa1d-751202feb58f
User	root
Command	/workspace/default/simv +use_otp_image=OtpTypeLcStTestUnlocked0 +create_jtag_riscv_map=1 +sw_build_device=sim_dv +sw_images=example_test_from_rom:0:te st_in_rom:new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1083174402 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_tap_straps_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.chip_tap_straps_testunlock0.1083174402
Directory	/workspace/3.chip_tap_straps_testunlock0/latest

Test location	/workspace/coverage/default/30.chip_sw_alert_handler_lpg_sleep_mode_alerts.3977709996
Short name	T515
Test name
Test status
Simulation time	3408776886 ps
CPU time	414.88 seconds
Started	Aug 14 06:14:45 PM PDT 24
Finished	Aug 14 06:21:40 PM PDT 24
Peak memory	649852 kb
Host	smart-dc94fb23-15f7-49c1-8565-618334b2ecfb
User	root
Command	/workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrlstate_regs +avoid_ferr_ips_append=otp_ctrlu_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3977709996 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.chip_ sw_alert_handler_lpg_sleep_mode_alerts.3977709996
Directory	/workspace/30.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location	/workspace/coverage/default/30.chip_sw_all_escalation_resets.1197669483
Short name	T527
Test name
Test status
Simulation time	4771115090 ps
CPU time	551.29 seconds
Started	Aug 14 06:14:56 PM PDT 24
Finished	Aug 14 06:24:08 PM PDT 24
Peak memory	650728 kb
Host	smart-02abab9b-4c08-4974-b8fb-839c43550806
User	root
Command	/workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 1197669483 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.chip_sw_all_escalation_resets.1197669483
Directory	/workspace/30.chip_sw_all_escalation_resets/latest

Test location	/workspace/coverage/default/31.chip_sw_alert_handler_lpg_sleep_mode_alerts.900706138
Short name	T507
Test name
Test status
Simulation time	3869796474 ps
CPU time	387.74 seconds
Started	Aug 14 06:13:39 PM PDT 24
Finished	Aug 14 06:20:07 PM PDT 24
Peak memory	649516 kb
Host	smart-312946e8-c3b3-4a73-ae0a-65e5bd2532bf
User	root
Command	/workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrlstate_regs +avoid_ferr_ips_append=otp_ctrlu_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=900706138 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all _escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.chip_s w_alert_handler_lpg_sleep_mode_alerts.900706138
Directory	/workspace/31.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location	/workspace/coverage/default/31.chip_sw_all_escalation_resets.2346612989
Short name	T531
Test name
Test status
Simulation time	5039034660 ps
CPU time	583.62 seconds
Started	Aug 14 06:12:24 PM PDT 24
Finished	Aug 14 06:22:08 PM PDT 24
Peak memory	650524 kb
Host	smart-9a209b4f-1ea8-4d96-89a7-6ab697e8bca3
User	root
Command	/workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 2346612989 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.chip_sw_all_escalation_resets.2346612989
Directory	/workspace/31.chip_sw_all_escalation_resets/latest

Test location	/workspace/coverage/default/33.chip_sw_alert_handler_lpg_sleep_mode_alerts.3284120009
Short name	T105
Test name
Test status
Simulation time	3869773428 ps
CPU time	355.66 seconds
Started	Aug 14 06:11:23 PM PDT 24
Finished	Aug 14 06:17:19 PM PDT 24
Peak memory	650064 kb
Host	smart-3a047fa5-a253-464f-9580-4d2bb83d4249
User	root
Command	/workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrlstate_regs +avoid_ferr_ips_append=otp_ctrlu_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3284120009 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.chip_ sw_alert_handler_lpg_sleep_mode_alerts.3284120009
Directory	/workspace/33.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location	/workspace/coverage/default/33.chip_sw_all_escalation_resets.363776983
Short name	T284
Test name
Test status
Simulation time	5668733552 ps
CPU time	624.81 seconds
Started	Aug 14 06:14:38 PM PDT 24
Finished	Aug 14 06:25:03 PM PDT 24
Peak memory	651184 kb
Host	smart-eaba836e-0e61-4de2-8b4d-7c9a3d7dbe3c
User	root
Command	/workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 363776983 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.chip_sw_all_escalation_resets.363776983
Directory	/workspace/33.chip_sw_all_escalation_resets/latest

Test location	/workspace/coverage/default/34.chip_sw_alert_handler_lpg_sleep_mode_alerts.4271050060
Short name	T447
Test name
Test status
Simulation time	3821965970 ps
CPU time	402.24 seconds
Started	Aug 14 06:12:58 PM PDT 24
Finished	Aug 14 06:19:41 PM PDT 24
Peak memory	649572 kb
Host	smart-372712e5-4cdc-440d-a6b7-91da041eeb57
User	root
Command	/workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrlstate_regs +avoid_ferr_ips_append=otp_ctrlu_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4271050060 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.chip_ sw_alert_handler_lpg_sleep_mode_alerts.4271050060
Directory	/workspace/34.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location	/workspace/coverage/default/34.chip_sw_all_escalation_resets.1100196119
Short name	T543
Test name
Test status
Simulation time	5400733448 ps
CPU time	641.21 seconds
Started	Aug 14 06:11:14 PM PDT 24
Finished	Aug 14 06:21:56 PM PDT 24
Peak memory	650704 kb
Host	smart-4e5114b7-1074-4071-9f2f-8872e3be3d4a
User	root
Command	/workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 1100196119 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.chip_sw_all_escalation_resets.1100196119
Directory	/workspace/34.chip_sw_all_escalation_resets/latest

Test location	/workspace/coverage/default/36.chip_sw_all_escalation_resets.4088093558
Short name	T109
Test name
Test status
Simulation time	6300653320 ps
CPU time	621.71 seconds
Started	Aug 14 06:14:12 PM PDT 24
Finished	Aug 14 06:24:34 PM PDT 24
Peak memory	650448 kb
Host	smart-1d7bfabd-4d3d-4b4b-b13c-68e4fc1eb9a6
User	root
Command	/workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 4088093558 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.chip_sw_all_escalation_resets.4088093558
Directory	/workspace/36.chip_sw_all_escalation_resets/latest

Test location	/workspace/coverage/default/37.chip_sw_alert_handler_lpg_sleep_mode_alerts.2001034895
Short name	T546
Test name
Test status
Simulation time	3691798552 ps
CPU time	382.04 seconds
Started	Aug 14 06:12:18 PM PDT 24
Finished	Aug 14 06:18:40 PM PDT 24
Peak memory	649296 kb
Host	smart-6829998b-f547-4a19-aafe-71d0e81673dd
User	root
Command	/workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrlstate_regs +avoid_ferr_ips_append=otp_ctrlu_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2001034895 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.chip_ sw_alert_handler_lpg_sleep_mode_alerts.2001034895
Directory	/workspace/37.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location	/workspace/coverage/default/4.chip_sw_alert_handler_lpg_sleep_mode_alerts.1402839465
Short name	T487
Test name
Test status
Simulation time	3545042300 ps
CPU time	386.67 seconds
Started	Aug 14 06:09:43 PM PDT 24
Finished	Aug 14 06:16:10 PM PDT 24
Peak memory	649360 kb
Host	smart-82166489-5156-4948-868b-27dbcefd59db
User	root
Command	/workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrlstate_regs +avoid_ferr_ips_append=otp_ctrlu_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1402839465 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.chip_s w_alert_handler_lpg_sleep_mode_alerts.1402839465
Directory	/workspace/4.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location	/workspace/coverage/default/4.chip_sw_all_escalation_resets.3558241492
Short name	T484
Test name
Test status
Simulation time	6200983142 ps
CPU time	686.91 seconds
Started	Aug 14 06:09:18 PM PDT 24
Finished	Aug 14 06:20:45 PM PDT 24
Peak memory	650868 kb
Host	smart-f6d18b59-cc1f-442d-a9a9-68b1e4003b08
User	root
Command	/workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 3558241492 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.chip_sw_all_escalation_resets.3558241492
Directory	/workspace/4.chip_sw_all_escalation_resets/latest

Test location	/workspace/coverage/default/4.chip_sw_aon_timer_sleep_wdog_sleep_pause.2336942868
Short name	T772
Test name
Test status
Simulation time	7974742844 ps
CPU time	467.55 seconds
Started	Aug 14 06:09:35 PM PDT 24
Finished	Aug 14 06:17:22 PM PDT 24
Peak memory	611232 kb
Host	smart-5fa27e4b-874b-4504-a32c-1f4741063b76
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=aon_timer_sleep_wdog_sleep_pause_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=2336942868 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.chip_sw_aon_timer_sleep_wdog_sleep_pause.2336942868
Directory	/workspace/4.chip_sw_aon_timer_sleep_wdog_sleep_pause/latest

Test location	/workspace/coverage/default/4.chip_sw_csrng_edn_concurrency.2471784740
Short name	T624
Test name
Test status
Simulation time	17569391550 ps
CPU time	4224.4 seconds
Started	Aug 14 06:09:57 PM PDT 24
Finished	Aug 14 07:20:22 PM PDT 24
Peak memory	611080 kb
Host	smart-8f105aea-c100-405c-9b5c-7c192c39dc8a
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=140_000_000 +rng_srate_value_min=15 +rng_srate_value_max=20 +accelerate_cold_power_up_time=3 +accelerate_r egulators_power_up_time=2 +sw_build_device=sim_dv +sw_images=csrng_edn_concurrency_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2471784740 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd b -cm_log /dev/null -cm_name 4.chip_sw_csrng_edn_concurrency.2471784740
Directory	/workspace/4.chip_sw_csrng_edn_concurrency/latest

Test location	/workspace/coverage/default/4.chip_sw_lc_ctrl_transition.1917944712
Short name	T899
Test name
Test status
Simulation time	6646878227 ps
CPU time	481.08 seconds
Started	Aug 14 06:08:26 PM PDT 24
Finished	Aug 14 06:16:28 PM PDT 24
Peak memory	622032 kb
Host	smart-8f21440b-5027-4d39-bd40-d6a1445e923e
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=lc_ctrl_transition_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1917944712 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_transition_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau lt.vdb -cm_log /dev/null -cm_name 4.chip_sw_lc_ctrl_transition.1917944712
Directory	/workspace/4.chip_sw_lc_ctrl_transition/latest

Test location	/workspace/coverage/default/4.chip_sw_sensor_ctrl_alert.165106286
Short name	T393
Test name
Test status
Simulation time	6812773408 ps
CPU time	944.96 seconds
Started	Aug 14 06:08:28 PM PDT 24
Finished	Aug 14 06:24:13 PM PDT 24
Peak memory	610932 kb
Host	smart-113d7924-14b1-43ab-bec0-e239432d8819
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=40_000_000 +sw_build_device=sim_dv +sw_images=sensor_ctrl_alert_test:1:new_rules,test_rom:0 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16510628 6 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace /coverage/default.vdb -cm_log /dev/null -cm_name 4.chip_sw_sensor_ctrl_alert.165106286
Directory	/workspace/4.chip_sw_sensor_ctrl_alert/latest

Test location	/workspace/coverage/default/4.chip_sw_uart_rand_baudrate.4137423627
Short name	T866
Test name
Test status
Simulation time	8930637432 ps
CPU time	1268.8 seconds
Started	Aug 14 06:08:27 PM PDT 24
Finished	Aug 14 06:29:37 PM PDT 24
Peak memory	620132 kb
Host	smart-2ef005d0-a251-4d04-8d84-e88e8d0d51dd
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random _seed=4137423627 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.chip_sw_uart_rand_baudrate.4137423627
Directory	/workspace/4.chip_sw_uart_rand_baudrate/latest

Test location	/workspace/coverage/default/4.chip_sw_uart_tx_rx.498344390
Short name	T369
Test name
Test status
Simulation time	4283806672 ps
CPU time	598.92 seconds
Started	Aug 14 06:11:21 PM PDT 24
Finished	Aug 14 06:21:20 PM PDT 24
Peak memory	620480 kb
Host	smart-b9873aa1-5183-45f3-9a78-d07ec8ae004d
User	root
Command	/workspace/default/simv +uart_idx=0 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=498344390 -as sert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac e/coverage/default.vdb -cm_log /dev/null -cm_name 4.chip_sw_uart_tx_rx.498344390
Directory	/workspace/4.chip_sw_uart_tx_rx/latest

Test location	/workspace/coverage/default/4.chip_sw_uart_tx_rx_alt_clk_freq_low_speed.4228799748
Short name	T622
Test name
Test status
Simulation time	4585173988 ps
CPU time	329.68 seconds
Started	Aug 14 06:09:17 PM PDT 24
Finished	Aug 14 06:14:47 PM PDT 24
Peak memory	625036 kb
Host	smart-41c92ed0-1e83-46dc-87d8-ed54dc566560
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +chip_clock_source=ChipClockSourceExternal48Mhz +sw_build_device=sim_dv +s w_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4228799748 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_b audrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.chip_sw_uart_tx_rx _alt_clk_freq_low_speed.4228799748
Directory	/workspace/4.chip_sw_uart_tx_rx_alt_clk_freq_low_speed/latest

Test location	/workspace/coverage/default/4.chip_sw_uart_tx_rx_idx1.2507397770
Short name	T630
Test name
Test status
Simulation time	3806875208 ps
CPU time	732.05 seconds
Started	Aug 14 06:09:07 PM PDT 24
Finished	Aug 14 06:21:19 PM PDT 24
Peak memory	624344 kb
Host	smart-8343cf98-0ff3-44c1-af9c-a54773a8eddb
User	root
Command	/workspace/default/simv +uart_idx=1 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2507397770 -a ssert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ce/coverage/default.vdb -cm_log /dev/null -cm_name 4.chip_sw_uart_tx_rx_idx1.2507397770
Directory	/workspace/4.chip_sw_uart_tx_rx_idx1/latest

Test location	/workspace/coverage/default/4.chip_sw_uart_tx_rx_idx2.1040405681
Short name	T915
Test name
Test status
Simulation time	4135270334 ps
CPU time	629.34 seconds
Started	Aug 14 06:08:36 PM PDT 24
Finished	Aug 14 06:19:06 PM PDT 24
Peak memory	620388 kb
Host	smart-673dd18e-a9ac-4b25-a36b-b9b5d8ba7ab2
User	root
Command	/workspace/default/simv +uart_idx=2 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1040405681 -a ssert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ce/coverage/default.vdb -cm_log /dev/null -cm_name 4.chip_sw_uart_tx_rx_idx2.1040405681
Directory	/workspace/4.chip_sw_uart_tx_rx_idx2/latest

Test location	/workspace/coverage/default/4.chip_sw_uart_tx_rx_idx3.3103859702
Short name	T979
Test name
Test status
Simulation time	4553233976 ps
CPU time	571.27 seconds
Started	Aug 14 06:08:54 PM PDT 24
Finished	Aug 14 06:18:25 PM PDT 24
Peak memory	620884 kb
Host	smart-bcc925eb-8c9e-49dd-a762-ecff59a3718d
User	root
Command	/workspace/default/simv +uart_idx=3 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3103859702 -a ssert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ce/coverage/default.vdb -cm_log /dev/null -cm_name 4.chip_sw_uart_tx_rx_idx3.3103859702
Directory	/workspace/4.chip_sw_uart_tx_rx_idx3/latest

Test location	/workspace/coverage/default/4.chip_tap_straps_dev.3415083277
Short name	T570
Test name
Test status
Simulation time	3635920701 ps
CPU time	204.76 seconds
Started	Aug 14 06:09:19 PM PDT 24
Finished	Aug 14 06:12:44 PM PDT 24
Peak memory	625232 kb
Host	smart-82b2be70-e094-4e8f-8320-43f32763602d
User	root
Command	/workspace/default/simv +use_otp_image=OtpTypeLcStDev +create_jtag_riscv_map=1 +sw_build_device=sim_dv +sw_images=example_test_from_rom:0:test_in_rom: new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=3415083277 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_tap_straps_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.chip_tap_straps_dev.3415083277
Directory	/workspace/4.chip_tap_straps_dev/latest

Test location	/workspace/coverage/default/4.chip_tap_straps_prod.3032700754
Short name	T613
Test name
Test status
Simulation time	3111278201 ps
CPU time	150.46 seconds
Started	Aug 14 06:07:57 PM PDT 24
Finished	Aug 14 06:10:28 PM PDT 24
Peak memory	624816 kb
Host	smart-ad7366ee-d45b-45c2-a250-6a3f1cd8b5b8
User	root
Command	/workspace/default/simv +use_otp_image=OtpTypeLcStProd +create_jtag_riscv_map=1 +sw_build_device=sim_dv +sw_images=example_test_from_rom:0:test_in_rom :new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3032700754 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_tap_straps_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.chip_tap_straps_prod.3032700754
Directory	/workspace/4.chip_tap_straps_prod/latest

Test location	/workspace/coverage/default/4.chip_tap_straps_rma.3377952489
Short name	T695
Test name
Test status
Simulation time	4163934477 ps
CPU time	344.26 seconds
Started	Aug 14 06:10:55 PM PDT 24
Finished	Aug 14 06:16:39 PM PDT 24
Peak memory	625648 kb
Host	smart-a7bec167-ad77-4713-9940-74f361fef49b
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +sw_build_device=sim_dv +sw_images=example_test_from_rom:0:test_in_rom:new_rules +cdc_instrumentation _enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3377952489 -as sert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_tap_straps_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/c overage/default.vdb -cm_log /dev/null -cm_name 4.chip_tap_straps_rma.3377952489
Directory	/workspace/4.chip_tap_straps_rma/latest

Test location	/workspace/coverage/default/4.chip_tap_straps_testunlock0.1244846789
Short name	T636
Test name
Test status
Simulation time	3597541808 ps
CPU time	216.86 seconds
Started	Aug 14 06:07:57 PM PDT 24
Finished	Aug 14 06:11:34 PM PDT 24
Peak memory	625304 kb
Host	smart-9ea61153-210c-40ea-b1b6-c97a01c6860c
User	root
Command	/workspace/default/simv +use_otp_image=OtpTypeLcStTestUnlocked0 +create_jtag_riscv_map=1 +sw_build_device=sim_dv +sw_images=example_test_from_rom:0:te st_in_rom:new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1244846789 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_tap_straps_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.chip_tap_straps_testunlock0.1244846789
Directory	/workspace/4.chip_tap_straps_testunlock0/latest

Test location	/workspace/coverage/default/41.chip_sw_all_escalation_resets.296563995
Short name	T208
Test name
Test status
Simulation time	5363741440 ps
CPU time	536.05 seconds
Started	Aug 14 06:14:57 PM PDT 24
Finished	Aug 14 06:23:54 PM PDT 24
Peak memory	620624 kb
Host	smart-afb8f4eb-707f-45de-90dc-968efbebef65
User	root
Command	/workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 296563995 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.chip_sw_all_escalation_resets.296563995
Directory	/workspace/41.chip_sw_all_escalation_resets/latest

Test location	/workspace/coverage/default/43.chip_sw_alert_handler_lpg_sleep_mode_alerts.3235198481
Short name	T462
Test name
Test status
Simulation time	3103918598 ps
CPU time	444.07 seconds
Started	Aug 14 06:15:09 PM PDT 24
Finished	Aug 14 06:22:34 PM PDT 24
Peak memory	649604 kb
Host	smart-a2ec0cea-9ded-4207-9dc8-929fdc5c7255
User	root
Command	/workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrlstate_regs +avoid_ferr_ips_append=otp_ctrlu_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3235198481 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.chip_ sw_alert_handler_lpg_sleep_mode_alerts.3235198481
Directory	/workspace/43.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location	/workspace/coverage/default/44.chip_sw_all_escalation_resets.3103735355
Short name	T172
Test name
Test status
Simulation time	4727161684 ps
CPU time	657.32 seconds
Started	Aug 14 06:12:57 PM PDT 24
Finished	Aug 14 06:23:55 PM PDT 24
Peak memory	650872 kb
Host	smart-6aa3307d-b323-407e-addd-7e4bce6a55a6
User	root
Command	/workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 3103735355 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.chip_sw_all_escalation_resets.3103735355
Directory	/workspace/44.chip_sw_all_escalation_resets/latest

Test location	/workspace/coverage/default/45.chip_sw_alert_handler_lpg_sleep_mode_alerts.3727148893
Short name	T520
Test name
Test status
Simulation time	3067765546 ps
CPU time	503.18 seconds
Started	Aug 14 06:13:36 PM PDT 24
Finished	Aug 14 06:21:59 PM PDT 24
Peak memory	649660 kb
Host	smart-a4e1315f-276a-4950-ad15-9497aecaf787
User	root
Command	/workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrlstate_regs +avoid_ferr_ips_append=otp_ctrlu_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3727148893 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.chip_ sw_alert_handler_lpg_sleep_mode_alerts.3727148893
Directory	/workspace/45.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location	/workspace/coverage/default/45.chip_sw_all_escalation_resets.574374072
Short name	T277
Test name
Test status
Simulation time	6003448724 ps
CPU time	754.58 seconds
Started	Aug 14 06:14:53 PM PDT 24
Finished	Aug 14 06:27:28 PM PDT 24
Peak memory	612468 kb
Host	smart-d5d92e73-7eed-4ea6-bf21-bdf81cc6391d
User	root
Command	/workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 574374072 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.chip_sw_all_escalation_resets.574374072
Directory	/workspace/45.chip_sw_all_escalation_resets/latest

Test location	/workspace/coverage/default/46.chip_sw_alert_handler_lpg_sleep_mode_alerts.2000308426
Short name	T483
Test name
Test status
Simulation time	4379109598 ps
CPU time	437.2 seconds
Started	Aug 14 06:15:16 PM PDT 24
Finished	Aug 14 06:22:34 PM PDT 24
Peak memory	650212 kb
Host	smart-8da810d9-5582-425d-ac62-c40ffe0e4562
User	root
Command	/workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrlstate_regs +avoid_ferr_ips_append=otp_ctrlu_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2000308426 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.chip_ sw_alert_handler_lpg_sleep_mode_alerts.2000308426
Directory	/workspace/46.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location	/workspace/coverage/default/48.chip_sw_alert_handler_lpg_sleep_mode_alerts.598648483
Short name	T378
Test name
Test status
Simulation time	4055108482 ps
CPU time	529.97 seconds
Started	Aug 14 06:13:43 PM PDT 24
Finished	Aug 14 06:22:33 PM PDT 24
Peak memory	649764 kb
Host	smart-8e30c669-0e8c-42d7-a572-c1b4f620b55b
User	root
Command	/workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrlstate_regs +avoid_ferr_ips_append=otp_ctrlu_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=598648483 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all _escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.chip_s w_alert_handler_lpg_sleep_mode_alerts.598648483
Directory	/workspace/48.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location	/workspace/coverage/default/48.chip_sw_all_escalation_resets.2654425894
Short name	T552
Test name
Test status
Simulation time	6148417544 ps
CPU time	671.72 seconds
Started	Aug 14 06:13:04 PM PDT 24
Finished	Aug 14 06:24:16 PM PDT 24
Peak memory	650828 kb
Host	smart-ad8df8c1-fd53-4979-9c93-dfde60ff9e99
User	root
Command	/workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 2654425894 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.chip_sw_all_escalation_resets.2654425894
Directory	/workspace/48.chip_sw_all_escalation_resets/latest

Test location	/workspace/coverage/default/5.chip_sw_alert_handler_lpg_sleep_mode_alerts.535824307
Short name	T939
Test name
Test status
Simulation time	3788434840 ps
CPU time	403.53 seconds
Started	Aug 14 06:10:25 PM PDT 24
Finished	Aug 14 06:17:09 PM PDT 24
Peak memory	649324 kb
Host	smart-2ed43996-c149-4da2-ad53-5a79c8f2350c
User	root
Command	/workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrlstate_regs +avoid_ferr_ips_append=otp_ctrlu_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=535824307 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all _escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.chip_sw _alert_handler_lpg_sleep_mode_alerts.535824307
Directory	/workspace/5.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location	/workspace/coverage/default/5.chip_sw_all_escalation_resets.1404013968
Short name	T465
Test name
Test status
Simulation time	4828117272 ps
CPU time	571.92 seconds
Started	Aug 14 06:08:37 PM PDT 24
Finished	Aug 14 06:18:10 PM PDT 24
Peak memory	620580 kb
Host	smart-ea136d94-a22b-4ee4-b18e-7e0a760c4c2d
User	root
Command	/workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 1404013968 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.chip_sw_all_escalation_resets.1404013968
Directory	/workspace/5.chip_sw_all_escalation_resets/latest

Test location	/workspace/coverage/default/5.chip_sw_csrng_edn_concurrency.2895359716
Short name	T276
Test name
Test status
Simulation time	29482292880 ps
CPU time	6107.6 seconds
Started	Aug 14 06:08:56 PM PDT 24
Finished	Aug 14 07:50:44 PM PDT 24
Peak memory	611072 kb
Host	smart-9f9789f5-4e68-410b-b569-32f7778c958b
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=140_000_000 +rng_srate_value_min=15 +rng_srate_value_max=20 +accelerate_cold_power_up_time=3 +accelerate_r egulators_power_up_time=2 +sw_build_device=sim_dv +sw_images=csrng_edn_concurrency_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2895359716 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd b -cm_log /dev/null -cm_name 5.chip_sw_csrng_edn_concurrency.2895359716
Directory	/workspace/5.chip_sw_csrng_edn_concurrency/latest

Test location	/workspace/coverage/default/5.chip_sw_data_integrity_escalation.2789073931
Short name	T291
Test name
Test status
Simulation time	5676438128 ps
CPU time	960.36 seconds
Started	Aug 14 06:08:45 PM PDT 24
Finished	Aug 14 06:24:46 PM PDT 24
Peak memory	611712 kb
Host	smart-abefa012-66f8-4b75-832a-29175ee34c8e
User	root
Command	/workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=data_integrity_escalation_reset_test:1:new_rules,test_ro m:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=2789073931 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_data_integrity_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.chip_sw_data_integrity_escalation.2789073931
Directory	/workspace/5.chip_sw_data_integrity_escalation/latest

Test location	/workspace/coverage/default/5.chip_sw_lc_ctrl_transition.2123048283
Short name	T604
Test name
Test status
Simulation time	6247234308 ps
CPU time	436.15 seconds
Started	Aug 14 06:09:42 PM PDT 24
Finished	Aug 14 06:16:58 PM PDT 24
Peak memory	622172 kb
Host	smart-340ddf0c-6d1c-4e4a-a89b-d0f0115dbb5e
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=lc_ctrl_transition_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2123048283 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_transition_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau lt.vdb -cm_log /dev/null -cm_name 5.chip_sw_lc_ctrl_transition.2123048283
Directory	/workspace/5.chip_sw_lc_ctrl_transition/latest

Test location	/workspace/coverage/default/5.chip_sw_uart_rand_baudrate.611633247
Short name	T313
Test name
Test status
Simulation time	8261253760 ps
CPU time	1678.41 seconds
Started	Aug 14 06:12:15 PM PDT 24
Finished	Aug 14 06:40:13 PM PDT 24
Peak memory	620152 kb
Host	smart-9cf13048-96ad-4029-8e0f-0c1565fb27b6
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random _seed=611633247 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.chip_sw_uart_rand_baudrate.611633247
Directory	/workspace/5.chip_sw_uart_rand_baudrate/latest

Test location	/workspace/coverage/default/50.chip_sw_all_escalation_resets.3428284935
Short name	T481
Test name
Test status
Simulation time	6023664696 ps
CPU time	697.08 seconds
Started	Aug 14 06:13:23 PM PDT 24
Finished	Aug 14 06:25:00 PM PDT 24
Peak memory	651100 kb
Host	smart-140cafbd-89ed-4dda-a223-89588ea1c6e6
User	root
Command	/workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 3428284935 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 50.chip_sw_all_escalation_resets.3428284935
Directory	/workspace/50.chip_sw_all_escalation_resets/latest

Test location	/workspace/coverage/default/51.chip_sw_alert_handler_lpg_sleep_mode_alerts.1922525703
Short name	T510
Test name
Test status
Simulation time	3852919808 ps
CPU time	380.16 seconds
Started	Aug 14 06:15:09 PM PDT 24
Finished	Aug 14 06:21:30 PM PDT 24
Peak memory	649536 kb
Host	smart-7049153d-815c-4e03-9eb1-9488dc287aaa
User	root
Command	/workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrlstate_regs +avoid_ferr_ips_append=otp_ctrlu_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1922525703 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 51.chip_ sw_alert_handler_lpg_sleep_mode_alerts.1922525703
Directory	/workspace/51.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location	/workspace/coverage/default/51.chip_sw_all_escalation_resets.4140768112
Short name	T384
Test name
Test status
Simulation time	4803179640 ps
CPU time	638.35 seconds
Started	Aug 14 06:13:17 PM PDT 24
Finished	Aug 14 06:23:56 PM PDT 24
Peak memory	650736 kb
Host	smart-705b91e4-3db9-443a-9b22-238795700816
User	root
Command	/workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 4140768112 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 51.chip_sw_all_escalation_resets.4140768112
Directory	/workspace/51.chip_sw_all_escalation_resets/latest

Test location	/workspace/coverage/default/52.chip_sw_alert_handler_lpg_sleep_mode_alerts.1016930030
Short name	T518
Test name
Test status
Simulation time	4482152108 ps
CPU time	439 seconds
Started	Aug 14 06:15:27 PM PDT 24
Finished	Aug 14 06:22:47 PM PDT 24
Peak memory	649964 kb
Host	smart-4733b19f-ebae-4c81-a519-203c3a413d9a
User	root
Command	/workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrlstate_regs +avoid_ferr_ips_append=otp_ctrlu_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1016930030 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 52.chip_ sw_alert_handler_lpg_sleep_mode_alerts.1016930030
Directory	/workspace/52.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location	/workspace/coverage/default/52.chip_sw_all_escalation_resets.3652588330
Short name	T944
Test name
Test status
Simulation time	5675970984 ps
CPU time	556.59 seconds
Started	Aug 14 06:12:59 PM PDT 24
Finished	Aug 14 06:22:15 PM PDT 24
Peak memory	650848 kb
Host	smart-fd1d782e-f78a-4594-bdb9-b4ffb6d6a958
User	root
Command	/workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 3652588330 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 52.chip_sw_all_escalation_resets.3652588330
Directory	/workspace/52.chip_sw_all_escalation_resets/latest

Test location	/workspace/coverage/default/53.chip_sw_alert_handler_lpg_sleep_mode_alerts.4112563149
Short name	T310
Test name
Test status
Simulation time	4032397550 ps
CPU time	445.99 seconds
Started	Aug 14 06:15:20 PM PDT 24
Finished	Aug 14 06:22:47 PM PDT 24
Peak memory	649284 kb
Host	smart-26c59d48-53a1-44cb-833b-0b5559838cf3
User	root
Command	/workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrlstate_regs +avoid_ferr_ips_append=otp_ctrlu_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4112563149 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 53.chip_ sw_alert_handler_lpg_sleep_mode_alerts.4112563149
Directory	/workspace/53.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location	/workspace/coverage/default/54.chip_sw_alert_handler_lpg_sleep_mode_alerts.438382265
Short name	T376
Test name
Test status
Simulation time	3423491712 ps
CPU time	359.24 seconds
Started	Aug 14 06:16:57 PM PDT 24
Finished	Aug 14 06:22:57 PM PDT 24
Peak memory	649584 kb
Host	smart-ab6fdfd7-ec34-4154-bded-3c3a7f224fbb
User	root
Command	/workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrlstate_regs +avoid_ferr_ips_append=otp_ctrlu_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=438382265 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all _escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 54.chip_s w_alert_handler_lpg_sleep_mode_alerts.438382265
Directory	/workspace/54.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location	/workspace/coverage/default/54.chip_sw_all_escalation_resets.323423138
Short name	T502
Test name
Test status
Simulation time	5554889336 ps
CPU time	391.72 seconds
Started	Aug 14 06:14:52 PM PDT 24
Finished	Aug 14 06:21:24 PM PDT 24
Peak memory	650788 kb
Host	smart-8c94c045-6c92-4af7-afff-60b7f52e6cc8
User	root
Command	/workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 323423138 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 54.chip_sw_all_escalation_resets.323423138
Directory	/workspace/54.chip_sw_all_escalation_resets/latest

Test location	/workspace/coverage/default/56.chip_sw_all_escalation_resets.875673311
Short name	T875
Test name
Test status
Simulation time	6056374652 ps
CPU time	672.42 seconds
Started	Aug 14 06:14:03 PM PDT 24
Finished	Aug 14 06:25:15 PM PDT 24
Peak memory	651084 kb
Host	smart-c7452dea-cfd2-4421-97d1-586b4d7164fc
User	root
Command	/workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 875673311 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 56.chip_sw_all_escalation_resets.875673311
Directory	/workspace/56.chip_sw_all_escalation_resets/latest

Test location	/workspace/coverage/default/57.chip_sw_alert_handler_lpg_sleep_mode_alerts.3604132182
Short name	T451
Test name
Test status
Simulation time	3516740380 ps
CPU time	326.52 seconds
Started	Aug 14 06:14:29 PM PDT 24
Finished	Aug 14 06:19:55 PM PDT 24
Peak memory	649632 kb
Host	smart-fd5585c3-f70e-4c36-99e4-244ea9afd748
User	root
Command	/workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrlstate_regs +avoid_ferr_ips_append=otp_ctrlu_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3604132182 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 57.chip_ sw_alert_handler_lpg_sleep_mode_alerts.3604132182
Directory	/workspace/57.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location	/workspace/coverage/default/57.chip_sw_all_escalation_resets.4236114838
Short name	T407
Test name
Test status
Simulation time	4889759386 ps
CPU time	643.77 seconds
Started	Aug 14 06:15:40 PM PDT 24
Finished	Aug 14 06:26:24 PM PDT 24
Peak memory	650820 kb
Host	smart-0b416287-16a8-4582-b1a0-820cbf73c761
User	root
Command	/workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 4236114838 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 57.chip_sw_all_escalation_resets.4236114838
Directory	/workspace/57.chip_sw_all_escalation_resets/latest

Test location	/workspace/coverage/default/58.chip_sw_all_escalation_resets.366074047
Short name	T497
Test name
Test status
Simulation time	5504295584 ps
CPU time	476.49 seconds
Started	Aug 14 06:13:35 PM PDT 24
Finished	Aug 14 06:21:32 PM PDT 24
Peak memory	649448 kb
Host	smart-1c79c7bc-19d8-48bf-a73b-1dd53ccb28cc
User	root
Command	/workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 366074047 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 58.chip_sw_all_escalation_resets.366074047
Directory	/workspace/58.chip_sw_all_escalation_resets/latest

Test location	/workspace/coverage/default/59.chip_sw_alert_handler_lpg_sleep_mode_alerts.2291205819
Short name	T496
Test name
Test status
Simulation time	3483660614 ps
CPU time	422.75 seconds
Started	Aug 14 06:14:11 PM PDT 24
Finished	Aug 14 06:21:14 PM PDT 24
Peak memory	649920 kb
Host	smart-10d31c02-a8ef-407d-b424-30abf5538c61
User	root
Command	/workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrlstate_regs +avoid_ferr_ips_append=otp_ctrlu_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2291205819 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 59.chip_ sw_alert_handler_lpg_sleep_mode_alerts.2291205819
Directory	/workspace/59.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location	/workspace/coverage/default/6.chip_sw_all_escalation_resets.3683692598
Short name	T169
Test name
Test status
Simulation time	4757379840 ps
CPU time	579.33 seconds
Started	Aug 14 06:09:59 PM PDT 24
Finished	Aug 14 06:19:39 PM PDT 24
Peak memory	651036 kb
Host	smart-fc03ab85-e8d9-4ef8-b796-e9ce5ec34efe
User	root
Command	/workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 3683692598 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.chip_sw_all_escalation_resets.3683692598
Directory	/workspace/6.chip_sw_all_escalation_resets/latest

Test location	/workspace/coverage/default/6.chip_sw_csrng_edn_concurrency.1210065176
Short name	T845
Test name
Test status
Simulation time	31069848000 ps
CPU time	5927.57 seconds
Started	Aug 14 06:10:44 PM PDT 24
Finished	Aug 14 07:49:33 PM PDT 24
Peak memory	611088 kb
Host	smart-cca5bfb3-6bee-4c63-b4ab-163523590713
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=140_000_000 +rng_srate_value_min=15 +rng_srate_value_max=20 +accelerate_cold_power_up_time=3 +accelerate_r egulators_power_up_time=2 +sw_build_device=sim_dv +sw_images=csrng_edn_concurrency_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1210065176 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd b -cm_log /dev/null -cm_name 6.chip_sw_csrng_edn_concurrency.1210065176
Directory	/workspace/6.chip_sw_csrng_edn_concurrency/latest

Test location	/workspace/coverage/default/6.chip_sw_lc_ctrl_transition.2334729274
Short name	T689
Test name
Test status
Simulation time	7808113597 ps
CPU time	536.21 seconds
Started	Aug 14 06:08:50 PM PDT 24
Finished	Aug 14 06:17:47 PM PDT 24
Peak memory	621816 kb
Host	smart-fdc10ebe-be95-4082-b6f4-f39066ec70e1
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=lc_ctrl_transition_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2334729274 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_transition_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau lt.vdb -cm_log /dev/null -cm_name 6.chip_sw_lc_ctrl_transition.2334729274
Directory	/workspace/6.chip_sw_lc_ctrl_transition/latest

Test location	/workspace/coverage/default/6.chip_sw_uart_rand_baudrate.1169959161
Short name	T647
Test name
Test status
Simulation time	4079224408 ps
CPU time	519.14 seconds
Started	Aug 14 06:11:26 PM PDT 24
Finished	Aug 14 06:20:05 PM PDT 24
Peak memory	620164 kb
Host	smart-a4b757b0-c452-4a75-9eeb-5a3cd2b0f622
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random _seed=1169959161 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.chip_sw_uart_rand_baudrate.1169959161
Directory	/workspace/6.chip_sw_uart_rand_baudrate/latest

Test location	/workspace/coverage/default/60.chip_sw_alert_handler_lpg_sleep_mode_alerts.1196967227
Short name	T958
Test name
Test status
Simulation time	4053519618 ps
CPU time	396.91 seconds
Started	Aug 14 06:15:30 PM PDT 24
Finished	Aug 14 06:22:08 PM PDT 24
Peak memory	649312 kb
Host	smart-226db201-0c0f-4440-ba28-6eb4c096c48c
User	root
Command	/workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrlstate_regs +avoid_ferr_ips_append=otp_ctrlu_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1196967227 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 60.chip_ sw_alert_handler_lpg_sleep_mode_alerts.1196967227
Directory	/workspace/60.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location	/workspace/coverage/default/60.chip_sw_all_escalation_resets.753399729
Short name	T500
Test name
Test status
Simulation time	5481822660 ps
CPU time	745.47 seconds
Started	Aug 14 06:16:27 PM PDT 24
Finished	Aug 14 06:28:53 PM PDT 24
Peak memory	651096 kb
Host	smart-7fe63d7b-3220-4504-96d7-04f8c8feb36b
User	root
Command	/workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 753399729 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 60.chip_sw_all_escalation_resets.753399729
Directory	/workspace/60.chip_sw_all_escalation_resets/latest

Test location	/workspace/coverage/default/61.chip_sw_all_escalation_resets.3577065611
Short name	T813
Test name
Test status
Simulation time	5510780840 ps
CPU time	652.29 seconds
Started	Aug 14 06:14:34 PM PDT 24
Finished	Aug 14 06:25:26 PM PDT 24
Peak memory	620364 kb
Host	smart-dfdcd145-62b8-4bf5-8e4a-6834f259bfe2
User	root
Command	/workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 3577065611 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 61.chip_sw_all_escalation_resets.3577065611
Directory	/workspace/61.chip_sw_all_escalation_resets/latest

Test location	/workspace/coverage/default/62.chip_sw_alert_handler_lpg_sleep_mode_alerts.3333428335
Short name	T419
Test name
Test status
Simulation time	4278697848 ps
CPU time	372.33 seconds
Started	Aug 14 06:16:16 PM PDT 24
Finished	Aug 14 06:22:29 PM PDT 24
Peak memory	649632 kb
Host	smart-1efb6113-0fbd-4b17-9d78-42fbece55780
User	root
Command	/workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrlstate_regs +avoid_ferr_ips_append=otp_ctrlu_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3333428335 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 62.chip_ sw_alert_handler_lpg_sleep_mode_alerts.3333428335
Directory	/workspace/62.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location	/workspace/coverage/default/62.chip_sw_all_escalation_resets.712094319
Short name	T455
Test name
Test status
Simulation time	5426202350 ps
CPU time	746.51 seconds
Started	Aug 14 06:14:36 PM PDT 24
Finished	Aug 14 06:27:03 PM PDT 24
Peak memory	650832 kb
Host	smart-da06cf65-466f-421c-b3e1-87670ea0a27b
User	root
Command	/workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 712094319 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 62.chip_sw_all_escalation_resets.712094319
Directory	/workspace/62.chip_sw_all_escalation_resets/latest

Test location	/workspace/coverage/default/63.chip_sw_alert_handler_lpg_sleep_mode_alerts.675937332
Short name	T542
Test name
Test status
Simulation time	3709342876 ps
CPU time	397.42 seconds
Started	Aug 14 06:19:22 PM PDT 24
Finished	Aug 14 06:25:59 PM PDT 24
Peak memory	649252 kb
Host	smart-17ff9178-9bfe-4fac-80b3-d929522ceef7
User	root
Command	/workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrlstate_regs +avoid_ferr_ips_append=otp_ctrlu_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=675937332 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all _escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 63.chip_s w_alert_handler_lpg_sleep_mode_alerts.675937332
Directory	/workspace/63.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location	/workspace/coverage/default/64.chip_sw_all_escalation_resets.3462861824
Short name	T492
Test name
Test status
Simulation time	5242741334 ps
CPU time	585.84 seconds
Started	Aug 14 06:14:00 PM PDT 24
Finished	Aug 14 06:23:46 PM PDT 24
Peak memory	650456 kb
Host	smart-7e9e1560-a1d3-4caa-a989-3769a7ee5e46
User	root
Command	/workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 3462861824 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 64.chip_sw_all_escalation_resets.3462861824
Directory	/workspace/64.chip_sw_all_escalation_resets/latest

Test location	/workspace/coverage/default/65.chip_sw_alert_handler_lpg_sleep_mode_alerts.2957475474
Short name	T721
Test name
Test status
Simulation time	4348672490 ps
CPU time	437.76 seconds
Started	Aug 14 06:14:01 PM PDT 24
Finished	Aug 14 06:21:19 PM PDT 24
Peak memory	649844 kb
Host	smart-fa1bf74e-8532-4073-a834-c94ecb90961d
User	root
Command	/workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrlstate_regs +avoid_ferr_ips_append=otp_ctrlu_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2957475474 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 65.chip_ sw_alert_handler_lpg_sleep_mode_alerts.2957475474
Directory	/workspace/65.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location	/workspace/coverage/default/66.chip_sw_alert_handler_lpg_sleep_mode_alerts.2688858483
Short name	T541
Test name
Test status
Simulation time	3720394826 ps
CPU time	396.36 seconds
Started	Aug 14 06:15:04 PM PDT 24
Finished	Aug 14 06:21:40 PM PDT 24
Peak memory	649640 kb
Host	smart-256bb14b-adbd-4f9c-b585-f130724af683
User	root
Command	/workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrlstate_regs +avoid_ferr_ips_append=otp_ctrlu_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2688858483 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 66.chip_ sw_alert_handler_lpg_sleep_mode_alerts.2688858483
Directory	/workspace/66.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location	/workspace/coverage/default/66.chip_sw_all_escalation_resets.1306223613
Short name	T709
Test name
Test status
Simulation time	5295546584 ps
CPU time	687.16 seconds
Started	Aug 14 06:16:07 PM PDT 24
Finished	Aug 14 06:27:35 PM PDT 24
Peak memory	620376 kb
Host	smart-55ec15fd-469b-4622-844c-f111438cf1a2
User	root
Command	/workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 1306223613 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 66.chip_sw_all_escalation_resets.1306223613
Directory	/workspace/66.chip_sw_all_escalation_resets/latest

Test location	/workspace/coverage/default/68.chip_sw_alert_handler_lpg_sleep_mode_alerts.861073642
Short name	T974
Test name
Test status
Simulation time	4214848496 ps
CPU time	402.62 seconds
Started	Aug 14 06:16:00 PM PDT 24
Finished	Aug 14 06:22:43 PM PDT 24
Peak memory	619676 kb
Host	smart-cb34abcd-9fee-4a6a-846e-98ca32db1e42
User	root
Command	/workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrlstate_regs +avoid_ferr_ips_append=otp_ctrlu_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=861073642 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all _escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 68.chip_s w_alert_handler_lpg_sleep_mode_alerts.861073642
Directory	/workspace/68.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location	/workspace/coverage/default/69.chip_sw_alert_handler_lpg_sleep_mode_alerts.1471092548
Short name	T228
Test name
Test status
Simulation time	4298114250 ps
CPU time	318.66 seconds
Started	Aug 14 06:16:00 PM PDT 24
Finished	Aug 14 06:21:18 PM PDT 24
Peak memory	649960 kb
Host	smart-c7a91fff-4e0d-4f91-80e0-3d335e1c15ce
User	root
Command	/workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrlstate_regs +avoid_ferr_ips_append=otp_ctrlu_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1471092548 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 69.chip_ sw_alert_handler_lpg_sleep_mode_alerts.1471092548
Directory	/workspace/69.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location	/workspace/coverage/default/69.chip_sw_all_escalation_resets.1759827617
Short name	T485
Test name
Test status
Simulation time	6011163070 ps
CPU time	649.65 seconds
Started	Aug 14 06:15:15 PM PDT 24
Finished	Aug 14 06:26:05 PM PDT 24
Peak memory	650948 kb
Host	smart-33d7cd55-ccad-459a-bcef-7f57b900316d
User	root
Command	/workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 1759827617 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 69.chip_sw_all_escalation_resets.1759827617
Directory	/workspace/69.chip_sw_all_escalation_resets/latest

Test location	/workspace/coverage/default/7.chip_sw_alert_handler_lpg_sleep_mode_alerts.3713580390
Short name	T463
Test name
Test status
Simulation time	3961168996 ps
CPU time	363.22 seconds
Started	Aug 14 06:10:58 PM PDT 24
Finished	Aug 14 06:17:01 PM PDT 24
Peak memory	649216 kb
Host	smart-5e73d426-75ba-4101-b792-a2d3c8c6ada7
User	root
Command	/workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrlstate_regs +avoid_ferr_ips_append=otp_ctrlu_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3713580390 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.chip_s w_alert_handler_lpg_sleep_mode_alerts.3713580390
Directory	/workspace/7.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location	/workspace/coverage/default/7.chip_sw_all_escalation_resets.2524357340
Short name	T545
Test name
Test status
Simulation time	6127122368 ps
CPU time	512.68 seconds
Started	Aug 14 06:10:59 PM PDT 24
Finished	Aug 14 06:19:32 PM PDT 24
Peak memory	650716 kb
Host	smart-760a8bc5-0f6c-4c69-b7d3-5b032733198e
User	root
Command	/workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 2524357340 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.chip_sw_all_escalation_resets.2524357340
Directory	/workspace/7.chip_sw_all_escalation_resets/latest

Test location	/workspace/coverage/default/7.chip_sw_csrng_edn_concurrency.3756218928
Short name	T704
Test name
Test status
Simulation time	13886884340 ps
CPU time	2637.75 seconds
Started	Aug 14 06:11:37 PM PDT 24
Finished	Aug 14 06:55:36 PM PDT 24
Peak memory	611188 kb
Host	smart-c359c3b1-46c6-4994-b62f-87f185cf4a25
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=140_000_000 +rng_srate_value_min=15 +rng_srate_value_max=20 +accelerate_cold_power_up_time=3 +accelerate_r egulators_power_up_time=2 +sw_build_device=sim_dv +sw_images=csrng_edn_concurrency_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3756218928 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd b -cm_log /dev/null -cm_name 7.chip_sw_csrng_edn_concurrency.3756218928
Directory	/workspace/7.chip_sw_csrng_edn_concurrency/latest

Test location	/workspace/coverage/default/7.chip_sw_lc_ctrl_transition.3120586832
Short name	T825
Test name
Test status
Simulation time	7607080388 ps
CPU time	690.35 seconds
Started	Aug 14 06:09:22 PM PDT 24
Finished	Aug 14 06:20:53 PM PDT 24
Peak memory	622112 kb
Host	smart-5db70378-0b96-446e-8665-25b36be7ff84
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=lc_ctrl_transition_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3120586832 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_transition_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau lt.vdb -cm_log /dev/null -cm_name 7.chip_sw_lc_ctrl_transition.3120586832
Directory	/workspace/7.chip_sw_lc_ctrl_transition/latest

Test location	/workspace/coverage/default/7.chip_sw_uart_rand_baudrate.3485283114
Short name	T794
Test name
Test status
Simulation time	8423751730 ps
CPU time	1370.17 seconds
Started	Aug 14 06:08:53 PM PDT 24
Finished	Aug 14 06:31:44 PM PDT 24
Peak memory	620236 kb
Host	smart-78a7fed3-eb77-4a15-ac1a-64d32042d1f2
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random _seed=3485283114 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.chip_sw_uart_rand_baudrate.3485283114
Directory	/workspace/7.chip_sw_uart_rand_baudrate/latest

Test location	/workspace/coverage/default/70.chip_sw_alert_handler_lpg_sleep_mode_alerts.10753886
Short name	T535
Test name
Test status
Simulation time	3509385970 ps
CPU time	403.2 seconds
Started	Aug 14 06:15:52 PM PDT 24
Finished	Aug 14 06:22:36 PM PDT 24
Peak memory	649588 kb
Host	smart-8d781471-8746-4d07-ac06-51dc9a40f9e7
User	root
Command	/workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrlstate_regs +avoid_ferr_ips_append=otp_ctrlu_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10753886 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_ escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 70.chip_sw _alert_handler_lpg_sleep_mode_alerts.10753886
Directory	/workspace/70.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location	/workspace/coverage/default/70.chip_sw_all_escalation_resets.2044648279
Short name	T1027
Test name
Test status
Simulation time	4768753196 ps
CPU time	476.65 seconds
Started	Aug 14 06:16:03 PM PDT 24
Finished	Aug 14 06:24:00 PM PDT 24
Peak memory	650748 kb
Host	smart-88344ade-65ee-414d-94f1-edbb70271bf8
User	root
Command	/workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 2044648279 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 70.chip_sw_all_escalation_resets.2044648279
Directory	/workspace/70.chip_sw_all_escalation_resets/latest

Test location	/workspace/coverage/default/71.chip_sw_all_escalation_resets.4091512340
Short name	T20
Test name
Test status
Simulation time	5080631236 ps
CPU time	595.07 seconds
Started	Aug 14 06:15:20 PM PDT 24
Finished	Aug 14 06:25:16 PM PDT 24
Peak memory	650780 kb
Host	smart-e97053c0-4cf5-455c-8038-51f555517d1c
User	root
Command	/workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 4091512340 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 71.chip_sw_all_escalation_resets.4091512340
Directory	/workspace/71.chip_sw_all_escalation_resets/latest

Test location	/workspace/coverage/default/72.chip_sw_alert_handler_lpg_sleep_mode_alerts.1853405742
Short name	T789
Test name
Test status
Simulation time	4168745248 ps
CPU time	466.26 seconds
Started	Aug 14 06:15:07 PM PDT 24
Finished	Aug 14 06:22:53 PM PDT 24
Peak memory	649612 kb
Host	smart-fcf28bcd-b95a-4a3f-b0f2-7752a06597a1
User	root
Command	/workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrlstate_regs +avoid_ferr_ips_append=otp_ctrlu_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1853405742 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 72.chip_ sw_alert_handler_lpg_sleep_mode_alerts.1853405742
Directory	/workspace/72.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location	/workspace/coverage/default/72.chip_sw_all_escalation_resets.56025891
Short name	T281
Test name
Test status
Simulation time	5191757716 ps
CPU time	498.09 seconds
Started	Aug 14 06:15:33 PM PDT 24
Finished	Aug 14 06:23:51 PM PDT 24
Peak memory	651016 kb
Host	smart-36d36fda-d0ad-413d-949f-cb78204440da
User	root
Command	/workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 56025891 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 72.chip_sw_all_escalation_resets.56025891
Directory	/workspace/72.chip_sw_all_escalation_resets/latest

Test location	/workspace/coverage/default/73.chip_sw_alert_handler_lpg_sleep_mode_alerts.3667595384
Short name	T240
Test name
Test status
Simulation time	3509973194 ps
CPU time	455.49 seconds
Started	Aug 14 06:15:17 PM PDT 24
Finished	Aug 14 06:22:53 PM PDT 24
Peak memory	649620 kb
Host	smart-84f083f5-e233-4f4b-b213-91602cef97f0
User	root
Command	/workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrlstate_regs +avoid_ferr_ips_append=otp_ctrlu_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3667595384 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 73.chip_ sw_alert_handler_lpg_sleep_mode_alerts.3667595384
Directory	/workspace/73.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location	/workspace/coverage/default/73.chip_sw_all_escalation_resets.3007751556
Short name	T802
Test name
Test status
Simulation time	6070411694 ps
CPU time	638.91 seconds
Started	Aug 14 06:15:34 PM PDT 24
Finished	Aug 14 06:26:14 PM PDT 24
Peak memory	620608 kb
Host	smart-df23e3b9-5b3e-42d4-b897-eb20d3a15966
User	root
Command	/workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 3007751556 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 73.chip_sw_all_escalation_resets.3007751556
Directory	/workspace/73.chip_sw_all_escalation_resets/latest

Test location	/workspace/coverage/default/74.chip_sw_alert_handler_lpg_sleep_mode_alerts.1911397241
Short name	T394
Test name
Test status
Simulation time	3545238786 ps
CPU time	296.36 seconds
Started	Aug 14 06:18:31 PM PDT 24
Finished	Aug 14 06:23:27 PM PDT 24
Peak memory	649264 kb
Host	smart-ccd6f770-1408-4024-bd76-ea1c2cff3fcd
User	root
Command	/workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrlstate_regs +avoid_ferr_ips_append=otp_ctrlu_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1911397241 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 74.chip_ sw_alert_handler_lpg_sleep_mode_alerts.1911397241
Directory	/workspace/74.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location	/workspace/coverage/default/74.chip_sw_all_escalation_resets.1636503224
Short name	T460
Test name
Test status
Simulation time	5594886736 ps
CPU time	600.67 seconds
Started	Aug 14 06:14:45 PM PDT 24
Finished	Aug 14 06:24:46 PM PDT 24
Peak memory	650844 kb
Host	smart-b8bceed9-fb1e-44d5-8ee3-66e7f8faf9a5
User	root
Command	/workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 1636503224 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 74.chip_sw_all_escalation_resets.1636503224
Directory	/workspace/74.chip_sw_all_escalation_resets/latest

Test location	/workspace/coverage/default/75.chip_sw_alert_handler_lpg_sleep_mode_alerts.3646736323
Short name	T491
Test name
Test status
Simulation time	4515451048 ps
CPU time	463.14 seconds
Started	Aug 14 06:14:54 PM PDT 24
Finished	Aug 14 06:22:38 PM PDT 24
Peak memory	649840 kb
Host	smart-2098c668-6abd-487b-87e3-7e56871c932d
User	root
Command	/workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrlstate_regs +avoid_ferr_ips_append=otp_ctrlu_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3646736323 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 75.chip_ sw_alert_handler_lpg_sleep_mode_alerts.3646736323
Directory	/workspace/75.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location	/workspace/coverage/default/76.chip_sw_alert_handler_lpg_sleep_mode_alerts.4008265284
Short name	T467
Test name
Test status
Simulation time	3090533486 ps
CPU time	335.53 seconds
Started	Aug 14 06:14:41 PM PDT 24
Finished	Aug 14 06:20:17 PM PDT 24
Peak memory	619616 kb
Host	smart-80254f8f-49f7-411a-95b6-621b6a149cd7
User	root
Command	/workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrlstate_regs +avoid_ferr_ips_append=otp_ctrlu_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4008265284 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 76.chip_ sw_alert_handler_lpg_sleep_mode_alerts.4008265284
Directory	/workspace/76.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location	/workspace/coverage/default/76.chip_sw_all_escalation_resets.255652197
Short name	T1011
Test name
Test status
Simulation time	6480723646 ps
CPU time	619.4 seconds
Started	Aug 14 06:17:49 PM PDT 24
Finished	Aug 14 06:28:09 PM PDT 24
Peak memory	650416 kb
Host	smart-e3c85fcf-aff7-4046-988d-ebd32510503b
User	root
Command	/workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 255652197 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 76.chip_sw_all_escalation_resets.255652197
Directory	/workspace/76.chip_sw_all_escalation_resets/latest

Test location	/workspace/coverage/default/77.chip_sw_alert_handler_lpg_sleep_mode_alerts.383294113
Short name	T469
Test name
Test status
Simulation time	3938460040 ps
CPU time	377.99 seconds
Started	Aug 14 06:15:14 PM PDT 24
Finished	Aug 14 06:21:32 PM PDT 24
Peak memory	649572 kb
Host	smart-47364486-2795-4092-9e41-4a56000bbd53
User	root
Command	/workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrlstate_regs +avoid_ferr_ips_append=otp_ctrlu_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=383294113 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all _escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 77.chip_s w_alert_handler_lpg_sleep_mode_alerts.383294113
Directory	/workspace/77.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location	/workspace/coverage/default/77.chip_sw_all_escalation_resets.1335500865
Short name	T185
Test name
Test status
Simulation time	4439718198 ps
CPU time	510.57 seconds
Started	Aug 14 06:18:34 PM PDT 24
Finished	Aug 14 06:27:05 PM PDT 24
Peak memory	650812 kb
Host	smart-793417b1-53f2-4ab1-8a71-48c7939d177a
User	root
Command	/workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 1335500865 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 77.chip_sw_all_escalation_resets.1335500865
Directory	/workspace/77.chip_sw_all_escalation_resets/latest

Test location	/workspace/coverage/default/78.chip_sw_alert_handler_lpg_sleep_mode_alerts.3878752818
Short name	T554
Test name
Test status
Simulation time	3790910216 ps
CPU time	391.01 seconds
Started	Aug 14 06:14:48 PM PDT 24
Finished	Aug 14 06:21:19 PM PDT 24
Peak memory	649668 kb
Host	smart-149a9c65-6647-418a-b614-312a95245957
User	root
Command	/workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrlstate_regs +avoid_ferr_ips_append=otp_ctrlu_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3878752818 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 78.chip_ sw_alert_handler_lpg_sleep_mode_alerts.3878752818
Directory	/workspace/78.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location	/workspace/coverage/default/78.chip_sw_all_escalation_resets.708999776
Short name	T454
Test name
Test status
Simulation time	5412699752 ps
CPU time	557.74 seconds
Started	Aug 14 06:17:46 PM PDT 24
Finished	Aug 14 06:27:04 PM PDT 24
Peak memory	650904 kb
Host	smart-a7850166-290a-46fb-888b-c3048be7e5ce
User	root
Command	/workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 708999776 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 78.chip_sw_all_escalation_resets.708999776
Directory	/workspace/78.chip_sw_all_escalation_resets/latest

Test location	/workspace/coverage/default/79.chip_sw_alert_handler_lpg_sleep_mode_alerts.404598224
Short name	T534
Test name
Test status
Simulation time	3371499120 ps
CPU time	310.79 seconds
Started	Aug 14 06:16:26 PM PDT 24
Finished	Aug 14 06:21:37 PM PDT 24
Peak memory	649920 kb
Host	smart-1beeb370-4f09-4db8-8411-6917a6377565
User	root
Command	/workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrlstate_regs +avoid_ferr_ips_append=otp_ctrlu_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=404598224 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all _escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 79.chip_s w_alert_handler_lpg_sleep_mode_alerts.404598224
Directory	/workspace/79.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location	/workspace/coverage/default/79.chip_sw_all_escalation_resets.4132861100
Short name	T489
Test name
Test status
Simulation time	5850405876 ps
CPU time	548.93 seconds
Started	Aug 14 06:15:40 PM PDT 24
Finished	Aug 14 06:24:49 PM PDT 24
Peak memory	650900 kb
Host	smart-2b69f87b-83b1-4306-a061-19c5d054b40f
User	root
Command	/workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 4132861100 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 79.chip_sw_all_escalation_resets.4132861100
Directory	/workspace/79.chip_sw_all_escalation_resets/latest

Test location	/workspace/coverage/default/8.chip_sw_csrng_edn_concurrency.410553481
Short name	T402
Test name
Test status
Simulation time	21348139304 ps
CPU time	5314.72 seconds
Started	Aug 14 06:10:43 PM PDT 24
Finished	Aug 14 07:39:18 PM PDT 24
Peak memory	611184 kb
Host	smart-a5d742c4-b6ad-4470-b939-0f1cb3d30e8a
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=140_000_000 +rng_srate_value_min=15 +rng_srate_value_max=20 +accelerate_cold_power_up_time=3 +accelerate_r egulators_power_up_time=2 +sw_build_device=sim_dv +sw_images=csrng_edn_concurrency_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=410553481 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.chip_sw_csrng_edn_concurrency.410553481
Directory	/workspace/8.chip_sw_csrng_edn_concurrency/latest

Test location	/workspace/coverage/default/8.chip_sw_lc_ctrl_transition.353253860
Short name	T670
Test name
Test status
Simulation time	6110444412 ps
CPU time	390.41 seconds
Started	Aug 14 06:10:55 PM PDT 24
Finished	Aug 14 06:17:26 PM PDT 24
Peak memory	622048 kb
Host	smart-d454947b-a15d-4c90-9e44-8cd7f781ecef
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=lc_ctrl_transition_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=353253860 -assert nopostproc +UVM_TEST NAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_transition_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul t.vdb -cm_log /dev/null -cm_name 8.chip_sw_lc_ctrl_transition.353253860
Directory	/workspace/8.chip_sw_lc_ctrl_transition/latest

Test location	/workspace/coverage/default/8.chip_sw_uart_rand_baudrate.3433986326
Short name	T829
Test name
Test status
Simulation time	8373805148 ps
CPU time	1222.39 seconds
Started	Aug 14 06:10:58 PM PDT 24
Finished	Aug 14 06:31:22 PM PDT 24
Peak memory	619508 kb
Host	smart-83843bba-888e-4024-b9d4-8321c23594ac
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random _seed=3433986326 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.chip_sw_uart_rand_baudrate.3433986326
Directory	/workspace/8.chip_sw_uart_rand_baudrate/latest

Test location	/workspace/coverage/default/80.chip_sw_alert_handler_lpg_sleep_mode_alerts.2778040084
Short name	T540
Test name
Test status
Simulation time	3856050576 ps
CPU time	416.21 seconds
Started	Aug 14 06:17:56 PM PDT 24
Finished	Aug 14 06:24:52 PM PDT 24
Peak memory	649520 kb
Host	smart-ef89873e-8e31-4370-a7d4-4a47566e0c3f
User	root
Command	/workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrlstate_regs +avoid_ferr_ips_append=otp_ctrlu_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2778040084 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 80.chip_ sw_alert_handler_lpg_sleep_mode_alerts.2778040084
Directory	/workspace/80.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location	/workspace/coverage/default/80.chip_sw_all_escalation_resets.1310006139
Short name	T529
Test name
Test status
Simulation time	4984455694 ps
CPU time	532.87 seconds
Started	Aug 14 06:14:54 PM PDT 24
Finished	Aug 14 06:23:47 PM PDT 24
Peak memory	650716 kb
Host	smart-73eb56a5-b703-45bd-9939-ccc8a434c444
User	root
Command	/workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 1310006139 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 80.chip_sw_all_escalation_resets.1310006139
Directory	/workspace/80.chip_sw_all_escalation_resets/latest

Test location	/workspace/coverage/default/81.chip_sw_alert_handler_lpg_sleep_mode_alerts.3109594465
Short name	T525
Test name
Test status
Simulation time	3673421234 ps
CPU time	389.9 seconds
Started	Aug 14 06:17:07 PM PDT 24
Finished	Aug 14 06:23:38 PM PDT 24
Peak memory	649632 kb
Host	smart-ff34dfea-5fac-449d-a501-75183862ed0c
User	root
Command	/workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrlstate_regs +avoid_ferr_ips_append=otp_ctrlu_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3109594465 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 81.chip_ sw_alert_handler_lpg_sleep_mode_alerts.3109594465
Directory	/workspace/81.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location	/workspace/coverage/default/81.chip_sw_all_escalation_resets.2324097482
Short name	T321
Test name
Test status
Simulation time	5369826322 ps
CPU time	552.27 seconds
Started	Aug 14 06:18:16 PM PDT 24
Finished	Aug 14 06:27:29 PM PDT 24
Peak memory	611720 kb
Host	smart-f9505dab-0eee-4520-892e-af0b8f874369
User	root
Command	/workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 2324097482 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 81.chip_sw_all_escalation_resets.2324097482
Directory	/workspace/81.chip_sw_all_escalation_resets/latest

Test location	/workspace/coverage/default/82.chip_sw_alert_handler_lpg_sleep_mode_alerts.1313290563
Short name	T115
Test name
Test status
Simulation time	3437890268 ps
CPU time	401.62 seconds
Started	Aug 14 06:15:36 PM PDT 24
Finished	Aug 14 06:22:18 PM PDT 24
Peak memory	649548 kb
Host	smart-62fd687c-58f6-45d0-b311-91c455c49be4
User	root
Command	/workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrlstate_regs +avoid_ferr_ips_append=otp_ctrlu_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1313290563 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 82.chip_ sw_alert_handler_lpg_sleep_mode_alerts.1313290563
Directory	/workspace/82.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location	/workspace/coverage/default/83.chip_sw_alert_handler_lpg_sleep_mode_alerts.1915516385
Short name	T458
Test name
Test status
Simulation time	4075443552 ps
CPU time	347.08 seconds
Started	Aug 14 06:16:21 PM PDT 24
Finished	Aug 14 06:22:08 PM PDT 24
Peak memory	649476 kb
Host	smart-bfdb0495-56ce-49ed-99e5-ef8e67afe92e
User	root
Command	/workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrlstate_regs +avoid_ferr_ips_append=otp_ctrlu_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1915516385 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 83.chip_ sw_alert_handler_lpg_sleep_mode_alerts.1915516385
Directory	/workspace/83.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location	/workspace/coverage/default/83.chip_sw_all_escalation_resets.883757344
Short name	T474
Test name
Test status
Simulation time	5769788296 ps
CPU time	589.36 seconds
Started	Aug 14 06:16:48 PM PDT 24
Finished	Aug 14 06:26:37 PM PDT 24
Peak memory	650692 kb
Host	smart-cdcea01a-4769-4f0a-b24b-67939d51f974
User	root
Command	/workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 883757344 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 83.chip_sw_all_escalation_resets.883757344
Directory	/workspace/83.chip_sw_all_escalation_resets/latest

Test location	/workspace/coverage/default/84.chip_sw_alert_handler_lpg_sleep_mode_alerts.1196812461
Short name	T555
Test name
Test status
Simulation time	4170472598 ps
CPU time	403.32 seconds
Started	Aug 14 06:17:30 PM PDT 24
Finished	Aug 14 06:24:13 PM PDT 24
Peak memory	649664 kb
Host	smart-6244a7d0-3763-4140-b1bc-544149ba57ea
User	root
Command	/workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrlstate_regs +avoid_ferr_ips_append=otp_ctrlu_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1196812461 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 84.chip_ sw_alert_handler_lpg_sleep_mode_alerts.1196812461
Directory	/workspace/84.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location	/workspace/coverage/default/84.chip_sw_all_escalation_resets.661986299
Short name	T760
Test name
Test status
Simulation time	5830927056 ps
CPU time	611.52 seconds
Started	Aug 14 06:16:22 PM PDT 24
Finished	Aug 14 06:26:33 PM PDT 24
Peak memory	620404 kb
Host	smart-84401ac7-7b11-4fac-8be9-a5dc36de3bcb
User	root
Command	/workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 661986299 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 84.chip_sw_all_escalation_resets.661986299
Directory	/workspace/84.chip_sw_all_escalation_resets/latest

Test location	/workspace/coverage/default/85.chip_sw_alert_handler_lpg_sleep_mode_alerts.2849770567
Short name	T512
Test name
Test status
Simulation time	3742846000 ps
CPU time	270.98 seconds
Started	Aug 14 06:17:14 PM PDT 24
Finished	Aug 14 06:21:46 PM PDT 24
Peak memory	647712 kb
Host	smart-71a77dbc-dcd1-491b-89c0-53f5ea2a48f2
User	root
Command	/workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrlstate_regs +avoid_ferr_ips_append=otp_ctrlu_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2849770567 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 85.chip_ sw_alert_handler_lpg_sleep_mode_alerts.2849770567
Directory	/workspace/85.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location	/workspace/coverage/default/85.chip_sw_all_escalation_resets.3647461817
Short name	T207
Test name
Test status
Simulation time	4951891698 ps
CPU time	487.74 seconds
Started	Aug 14 06:15:22 PM PDT 24
Finished	Aug 14 06:23:30 PM PDT 24
Peak memory	620652 kb
Host	smart-37657812-818c-454b-8216-457de5c3ee83
User	root
Command	/workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 3647461817 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 85.chip_sw_all_escalation_resets.3647461817
Directory	/workspace/85.chip_sw_all_escalation_resets/latest

Test location	/workspace/coverage/default/86.chip_sw_alert_handler_lpg_sleep_mode_alerts.1758629285
Short name	T523
Test name
Test status
Simulation time	3613544204 ps
CPU time	442.37 seconds
Started	Aug 14 06:16:46 PM PDT 24
Finished	Aug 14 06:24:08 PM PDT 24
Peak memory	649576 kb
Host	smart-2888676b-70a0-4d9c-8b2b-a39bc3bae680
User	root
Command	/workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrlstate_regs +avoid_ferr_ips_append=otp_ctrlu_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1758629285 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 86.chip_ sw_alert_handler_lpg_sleep_mode_alerts.1758629285
Directory	/workspace/86.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location	/workspace/coverage/default/87.chip_sw_alert_handler_lpg_sleep_mode_alerts.821094762
Short name	T548
Test name
Test status
Simulation time	3532907072 ps
CPU time	344.75 seconds
Started	Aug 14 06:21:11 PM PDT 24
Finished	Aug 14 06:26:56 PM PDT 24
Peak memory	649224 kb
Host	smart-08918b2f-b229-4264-9010-0ffc60f04196
User	root
Command	/workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrlstate_regs +avoid_ferr_ips_append=otp_ctrlu_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=821094762 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all _escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 87.chip_s w_alert_handler_lpg_sleep_mode_alerts.821094762
Directory	/workspace/87.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location	/workspace/coverage/default/87.chip_sw_all_escalation_resets.4199145912
Short name	T472
Test name
Test status
Simulation time	5248439896 ps
CPU time	590.4 seconds
Started	Aug 14 06:16:09 PM PDT 24
Finished	Aug 14 06:26:00 PM PDT 24
Peak memory	650516 kb
Host	smart-e7b07800-275a-4117-b662-a1dbc6cb3f1e
User	root
Command	/workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 4199145912 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 87.chip_sw_all_escalation_resets.4199145912
Directory	/workspace/87.chip_sw_all_escalation_resets/latest

Test location	/workspace/coverage/default/88.chip_sw_alert_handler_lpg_sleep_mode_alerts.2618606315
Short name	T536
Test name
Test status
Simulation time	3392159800 ps
CPU time	362.31 seconds
Started	Aug 14 06:17:08 PM PDT 24
Finished	Aug 14 06:23:11 PM PDT 24
Peak memory	649536 kb
Host	smart-ca34b80f-b9af-4f89-8f16-1b6376834e33
User	root
Command	/workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrlstate_regs +avoid_ferr_ips_append=otp_ctrlu_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2618606315 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 88.chip_ sw_alert_handler_lpg_sleep_mode_alerts.2618606315
Directory	/workspace/88.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location	/workspace/coverage/default/88.chip_sw_all_escalation_resets.2195189802
Short name	T373
Test name
Test status
Simulation time	4282243160 ps
CPU time	603.38 seconds
Started	Aug 14 06:16:19 PM PDT 24
Finished	Aug 14 06:26:23 PM PDT 24
Peak memory	650232 kb
Host	smart-5b878c50-e4eb-4b01-8254-6182ae87cfe1
User	root
Command	/workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 2195189802 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 88.chip_sw_all_escalation_resets.2195189802
Directory	/workspace/88.chip_sw_all_escalation_resets/latest

Test location	/workspace/coverage/default/89.chip_sw_alert_handler_lpg_sleep_mode_alerts.545796706
Short name	T412
Test name
Test status
Simulation time	4366267422 ps
CPU time	430.16 seconds
Started	Aug 14 06:19:10 PM PDT 24
Finished	Aug 14 06:26:21 PM PDT 24
Peak memory	649520 kb
Host	smart-9cd93904-66f4-4d47-9e36-0828ce00af94
User	root
Command	/workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrlstate_regs +avoid_ferr_ips_append=otp_ctrlu_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=545796706 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all _escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 89.chip_s w_alert_handler_lpg_sleep_mode_alerts.545796706
Directory	/workspace/89.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location	/workspace/coverage/default/9.chip_sw_alert_handler_lpg_sleep_mode_alerts.446715004
Short name	T495
Test name
Test status
Simulation time	3522135716 ps
CPU time	360.96 seconds
Started	Aug 14 06:09:36 PM PDT 24
Finished	Aug 14 06:15:37 PM PDT 24
Peak memory	649484 kb
Host	smart-618ca53b-28fa-4e0a-8355-4227f486a77e
User	root
Command	/workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrlstate_regs +avoid_ferr_ips_append=otp_ctrlu_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=446715004 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all _escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.chip_sw _alert_handler_lpg_sleep_mode_alerts.446715004
Directory	/workspace/9.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location	/workspace/coverage/default/9.chip_sw_csrng_edn_concurrency.549163075
Short name	T832
Test name
Test status
Simulation time	35017355312 ps
CPU time	6827.61 seconds
Started	Aug 14 06:11:35 PM PDT 24
Finished	Aug 14 08:05:23 PM PDT 24
Peak memory	611124 kb
Host	smart-87cdc7a7-628f-446b-9770-5ff516785de0
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=140_000_000 +rng_srate_value_min=15 +rng_srate_value_max=20 +accelerate_cold_power_up_time=3 +accelerate_r egulators_power_up_time=2 +sw_build_device=sim_dv +sw_images=csrng_edn_concurrency_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=549163075 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.chip_sw_csrng_edn_concurrency.549163075
Directory	/workspace/9.chip_sw_csrng_edn_concurrency/latest

Test location	/workspace/coverage/default/9.chip_sw_uart_rand_baudrate.1882803527
Short name	T325
Test name
Test status
Simulation time	5042034808 ps
CPU time	557.16 seconds
Started	Aug 14 06:12:12 PM PDT 24
Finished	Aug 14 06:21:30 PM PDT 24
Peak memory	620172 kb
Host	smart-add8b01e-c296-410b-9e42-99c63feb5920
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random _seed=1882803527 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.chip_sw_uart_rand_baudrate.1882803527
Directory	/workspace/9.chip_sw_uart_rand_baudrate/latest

Test location	/workspace/coverage/default/91.chip_sw_all_escalation_resets.2376324183
Short name	T494
Test name
Test status
Simulation time	5114085928 ps
CPU time	547.3 seconds
Started	Aug 14 06:16:39 PM PDT 24
Finished	Aug 14 06:25:47 PM PDT 24
Peak memory	650996 kb
Host	smart-80d501fa-2109-4cbc-a97c-e8c2fe5230a0
User	root
Command	/workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 2376324183 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 91.chip_sw_all_escalation_resets.2376324183
Directory	/workspace/91.chip_sw_all_escalation_resets/latest

Test location	/workspace/coverage/default/92.chip_sw_all_escalation_resets.3742065466
Short name	T503
Test name
Test status
Simulation time	4545266216 ps
CPU time	514.73 seconds
Started	Aug 14 06:17:52 PM PDT 24
Finished	Aug 14 06:26:27 PM PDT 24
Peak memory	650808 kb
Host	smart-c2bbfa5d-f7d4-401c-90a2-1de82a9fad1c
User	root
Command	/workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 3742065466 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 92.chip_sw_all_escalation_resets.3742065466
Directory	/workspace/92.chip_sw_all_escalation_resets/latest

Test location	/workspace/coverage/default/93.chip_sw_all_escalation_resets.325797301
Short name	T456
Test name
Test status
Simulation time	4383531242 ps
CPU time	485.64 seconds
Started	Aug 14 06:16:57 PM PDT 24
Finished	Aug 14 06:25:03 PM PDT 24
Peak memory	650704 kb
Host	smart-f23f98d9-0a8c-46a4-8b72-ca3b34ccfb8a
User	root
Command	/workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 325797301 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 93.chip_sw_all_escalation_resets.325797301
Directory	/workspace/93.chip_sw_all_escalation_resets/latest

Test location	/workspace/coverage/default/94.chip_sw_all_escalation_resets.2362478035
Short name	T516
Test name
Test status
Simulation time	5534454136 ps
CPU time	511.56 seconds
Started	Aug 14 06:18:36 PM PDT 24
Finished	Aug 14 06:27:08 PM PDT 24
Peak memory	651096 kb
Host	smart-209a6cd5-7822-4071-bbd6-59d1a877d809
User	root
Command	/workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 2362478035 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 94.chip_sw_all_escalation_resets.2362478035
Directory	/workspace/94.chip_sw_all_escalation_resets/latest

Test location	/workspace/coverage/default/95.chip_sw_all_escalation_resets.1472255928
Short name	T379
Test name
Test status
Simulation time	4366010512 ps
CPU time	497.21 seconds
Started	Aug 14 06:16:36 PM PDT 24
Finished	Aug 14 06:24:53 PM PDT 24
Peak memory	651052 kb
Host	smart-c9923c81-5cc0-4e6e-b96b-b31373b0b65e
User	root
Command	/workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 1472255928 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 95.chip_sw_all_escalation_resets.1472255928
Directory	/workspace/95.chip_sw_all_escalation_resets/latest

Test location	/workspace/coverage/default/96.chip_sw_all_escalation_resets.2382975340
Short name	T806
Test name
Test status
Simulation time	4076981720 ps
CPU time	410.65 seconds
Started	Aug 14 06:17:42 PM PDT 24
Finished	Aug 14 06:24:33 PM PDT 24
Peak memory	650560 kb
Host	smart-cf143ddc-63bc-4709-bb88-7ccb5216eb7a
User	root
Command	/workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 2382975340 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 96.chip_sw_all_escalation_resets.2382975340
Directory	/workspace/96.chip_sw_all_escalation_resets/latest

Test location	/workspace/coverage/default/97.chip_sw_all_escalation_resets.2320383271
Short name	T657
Test name
Test status
Simulation time	5672759540 ps
CPU time	633.46 seconds
Started	Aug 14 06:18:49 PM PDT 24
Finished	Aug 14 06:29:22 PM PDT 24
Peak memory	650604 kb
Host	smart-38303872-d946-4075-94fa-3f03f3e03a39
User	root
Command	/workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 2320383271 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 97.chip_sw_all_escalation_resets.2320383271
Directory	/workspace/97.chip_sw_all_escalation_resets/latest

Test location	/workspace/coverage/default/98.chip_sw_all_escalation_resets.4150311657
Short name	T505
Test name
Test status
Simulation time	5530267916 ps
CPU time	560.15 seconds
Started	Aug 14 06:16:42 PM PDT 24
Finished	Aug 14 06:26:02 PM PDT 24
Peak memory	650860 kb
Host	smart-650bc2b5-f1d0-49fb-a0f5-24f279c4514c
User	root
Command	/workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 4150311657 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 98.chip_sw_all_escalation_resets.4150311657
Directory	/workspace/98.chip_sw_all_escalation_resets/latest

Test location	/workspace/coverage/default/99.chip_sw_all_escalation_resets.4131529830
Short name	T328
Test name
Test status
Simulation time	6213114300 ps
CPU time	471.51 seconds
Started	Aug 14 06:17:36 PM PDT 24
Finished	Aug 14 06:25:28 PM PDT 24
Peak memory	650556 kb
Host	smart-65800245-9aaf-40c2-a818-43ec8baa3645
User	root
Command	/workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 4131529830 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 99.chip_sw_all_escalation_resets.4131529830
Directory	/workspace/99.chip_sw_all_escalation_resets/latest

Test location	/workspace/coverage/pad_ctrl_test_mode/0.chip_padctrl_attributes.670755234
Short name	T247
Test name
Test status
Simulation time	4669197960 ps
CPU time	195.9 seconds
Started	Aug 14 05:39:05 PM PDT 24
Finished	Aug 14 05:42:21 PM PDT 24
Peak memory	641500 kb
Host	smart-4b5d7c52-eff0-4301-8496-de8af2d5f3d0
User	root
Command	/workspace/pad_ctrl_test_mode/simv +use_otp_image=OtpTypeLcStProd +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=670755234 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TES T_SEQ=chip_padctrl_attributes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/pad_ctrl_test_mode.vdb -cm_log /dev/n ull -cm_name 0.chip_padctrl_attributes.670755234
Directory	/workspace/0.chip_padctrl_attributes/latest

Test location	/workspace/coverage/pad_ctrl_test_mode/1.chip_padctrl_attributes.784049982
Short name	T246
Test name
Test status
Simulation time	5571636176 ps
CPU time	207.58 seconds
Started	Aug 14 05:39:01 PM PDT 24
Finished	Aug 14 05:42:29 PM PDT 24
Peak memory	649680 kb
Host	smart-bec7046c-9405-4423-9107-4233d3208147
User	root
Command	/workspace/pad_ctrl_test_mode/simv +use_otp_image=OtpTypeLcStProd +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=784049982 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TES T_SEQ=chip_padctrl_attributes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/pad_ctrl_test_mode.vdb -cm_log /dev/n ull -cm_name 1.chip_padctrl_attributes.784049982
Directory	/workspace/1.chip_padctrl_attributes/latest

Test location	/workspace/coverage/pad_ctrl_test_mode/2.chip_padctrl_attributes.1706073002
Short name	T251
Test name
Test status
Simulation time	4525177000 ps
CPU time	285.66 seconds
Started	Aug 14 05:39:08 PM PDT 24
Finished	Aug 14 05:43:54 PM PDT 24
Peak memory	641388 kb
Host	smart-53ae48ce-24f7-41b1-abdd-a133c8f54368
User	root
Command	/workspace/pad_ctrl_test_mode/simv +use_otp_image=OtpTypeLcStProd +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1706073002 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TE ST_SEQ=chip_padctrl_attributes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/pad_ctrl_test_mode.vdb -cm_log /dev/ null -cm_name 2.chip_padctrl_attributes.1706073002
Directory	/workspace/2.chip_padctrl_attributes/latest

Test location	/workspace/coverage/pad_ctrl_test_mode/3.chip_padctrl_attributes.507312334
Short name	T250
Test name
Test status
Simulation time	4038861100 ps
CPU time	234.5 seconds
Started	Aug 14 05:39:01 PM PDT 24
Finished	Aug 14 05:42:55 PM PDT 24
Peak memory	641492 kb
Host	smart-5493163e-bfb7-4cb9-b829-edb1d12b8afb
User	root
Command	/workspace/pad_ctrl_test_mode/simv +use_otp_image=OtpTypeLcStProd +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=507312334 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TES T_SEQ=chip_padctrl_attributes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/pad_ctrl_test_mode.vdb -cm_log /dev/n ull -cm_name 3.chip_padctrl_attributes.507312334
Directory	/workspace/3.chip_padctrl_attributes/latest

Test location	/workspace/coverage/pad_ctrl_test_mode/4.chip_padctrl_attributes.1494586566
Short name	T50
Test name
Test status
Simulation time	4974650693 ps
CPU time	306.85 seconds
Started	Aug 14 05:39:03 PM PDT 24
Finished	Aug 14 05:44:10 PM PDT 24
Peak memory	650288 kb
Host	smart-df2f8343-5ff7-4d30-9e3a-02b270713930
User	root
Command	/workspace/pad_ctrl_test_mode/simv +use_otp_image=OtpTypeLcStProd +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1494586566 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TE ST_SEQ=chip_padctrl_attributes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/pad_ctrl_test_mode.vdb -cm_log /dev/ null -cm_name 4.chip_padctrl_attributes.1494586566
Directory	/workspace/4.chip_padctrl_attributes/latest

Test location	/workspace/coverage/pad_ctrl_test_mode/6.chip_padctrl_attributes.1131544435
Short name	T249
Test name
Test status
Simulation time	3673742772 ps
CPU time	215.25 seconds
Started	Aug 14 05:39:01 PM PDT 24
Finished	Aug 14 05:42:37 PM PDT 24
Peak memory	641760 kb
Host	smart-b3a3de72-ad17-4557-8d3f-b0cb72844fd5
User	root
Command	/workspace/pad_ctrl_test_mode/simv +use_otp_image=OtpTypeLcStProd +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1131544435 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TE ST_SEQ=chip_padctrl_attributes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/pad_ctrl_test_mode.vdb -cm_log /dev/ null -cm_name 6.chip_padctrl_attributes.1131544435
Directory	/workspace/6.chip_padctrl_attributes/latest

Test location	/workspace/coverage/pad_ctrl_test_mode/8.chip_padctrl_attributes.3526503971
Short name	T248
Test name
Test status
Simulation time	4823373940 ps
CPU time	322.81 seconds
Started	Aug 14 05:39:03 PM PDT 24
Finished	Aug 14 05:44:26 PM PDT 24
Peak memory	649668 kb
Host	smart-4c7c129f-482f-46f4-a810-2d6b9bdd6557
User	root
Command	/workspace/pad_ctrl_test_mode/simv +use_otp_image=OtpTypeLcStProd +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3526503971 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TE ST_SEQ=chip_padctrl_attributes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/pad_ctrl_test_mode.vdb -cm_log /dev/ null -cm_name 8.chip_padctrl_attributes.3526503971
Directory	/workspace/8.chip_padctrl_attributes/latest

Test location	/workspace/coverage/pad_ctrl_test_mode/9.chip_padctrl_attributes.41387924
Short name	T165
Test name
Test status
Simulation time	5361615294 ps
CPU time	286.09 seconds
Started	Aug 14 05:39:05 PM PDT 24
Finished	Aug 14 05:43:51 PM PDT 24
Peak memory	657852 kb
Host	smart-b925a156-2c92-48e6-9b1f-c5c184f5e6c9
User	root
Command	/workspace/pad_ctrl_test_mode/simv +use_otp_image=OtpTypeLcStProd +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41387924 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST _SEQ=chip_padctrl_attributes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/pad_ctrl_test_mode.vdb -cm_log /dev/nu ll -cm_name 9.chip_padctrl_attributes.41387924
Directory	/workspace/9.chip_padctrl_attributes/latest