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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
85.60 88.40 77.09 90.05 89.40 83.77 84.87


Total test records in report: 1034
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T850 /workspace/coverage/default/2.chip_sw_csrng_smoketest.2724008846 Aug 14 06:07:22 PM PDT 24 Aug 14 06:12:16 PM PDT 24 3095751800 ps
T851 /workspace/coverage/default/2.chip_sw_lc_walkthrough_testunlocks.405492032 Aug 14 06:00:51 PM PDT 24 Aug 14 06:29:58 PM PDT 24 22640086069 ps
T852 /workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_fast_dev.3202893259 Aug 14 05:49:29 PM PDT 24 Aug 14 05:57:05 PM PDT 24 3913536156 ps
T853 /workspace/coverage/default/0.chip_sw_sram_ctrl_scrambled_access.898352096 Aug 14 05:50:40 PM PDT 24 Aug 14 05:59:56 PM PDT 24 4853998312 ps
T447 /workspace/coverage/default/34.chip_sw_alert_handler_lpg_sleep_mode_alerts.4271050060 Aug 14 06:12:58 PM PDT 24 Aug 14 06:19:41 PM PDT 24 3821965970 ps
T854 /workspace/coverage/default/13.chip_sw_lc_ctrl_transition.3852137876 Aug 14 06:11:54 PM PDT 24 Aug 14 06:21:33 PM PDT 24 6379373293 ps
T855 /workspace/coverage/default/1.chip_sw_sram_ctrl_smoketest.1347915626 Aug 14 05:55:18 PM PDT 24 Aug 14 05:59:16 PM PDT 24 2974758390 ps
T856 /workspace/coverage/default/1.rom_e2e_shutdown_exception_c.3453957903 Aug 14 05:58:52 PM PDT 24 Aug 14 07:01:14 PM PDT 24 14511266209 ps
T382 /workspace/coverage/default/0.chip_sw_plic_sw_irq.1675049966 Aug 14 05:52:17 PM PDT 24 Aug 14 05:57:13 PM PDT 24 2202385600 ps
T190 /workspace/coverage/default/2.chip_jtag_mem_access.4155263942 Aug 14 05:57:52 PM PDT 24 Aug 14 06:20:49 PM PDT 24 13694480440 ps
T857 /workspace/coverage/default/2.chip_sw_otbn_ecdsa_op_irq_jitter_en.825954272 Aug 14 06:02:28 PM PDT 24 Aug 14 06:51:28 PM PDT 24 18839855542 ps
T450 /workspace/coverage/default/1.chip_sw_alert_handler_lpg_sleep_mode_alerts.1981430239 Aug 14 05:51:22 PM PDT 24 Aug 14 05:57:38 PM PDT 24 4321385400 ps
T550 /workspace/coverage/default/2.chip_sw_alert_handler_lpg_sleep_mode_alerts.4171697155 Aug 14 06:02:39 PM PDT 24 Aug 14 06:10:12 PM PDT 24 3046854304 ps
T195 /workspace/coverage/default/0.chip_sw_sram_ctrl_execution_main.1575215601 Aug 14 05:48:54 PM PDT 24 Aug 14 06:01:19 PM PDT 24 6878816837 ps
T858 /workspace/coverage/default/0.rom_e2e_sigverify_always_a_nothing_b_bad_prod_end.322193222 Aug 14 05:55:39 PM PDT 24 Aug 14 06:54:15 PM PDT 24 13611721637 ps
T859 /workspace/coverage/default/1.chip_sw_clkmgr_jitter_reduced_freq.2282733949 Aug 14 05:53:01 PM PDT 24 Aug 14 05:56:56 PM PDT 24 2648411434 ps
T196 /workspace/coverage/default/1.chip_sw_sram_ctrl_execution_main.3842032522 Aug 14 05:51:26 PM PDT 24 Aug 14 06:11:25 PM PDT 24 8880396001 ps
T383 /workspace/coverage/default/1.chip_sw_power_sleep_load.2095668869 Aug 14 05:57:14 PM PDT 24 Aug 14 06:03:13 PM PDT 24 4205083760 ps
T53 /workspace/coverage/default/0.chip_sw_spi_host_tx_rx.2742146 Aug 14 05:46:57 PM PDT 24 Aug 14 05:51:45 PM PDT 24 2778016736 ps
T860 /workspace/coverage/default/1.chip_sw_flash_ctrl_access_jitter_en_reduced_freq.1102193936 Aug 14 05:53:59 PM PDT 24 Aug 14 06:13:50 PM PDT 24 7439843430 ps
T861 /workspace/coverage/default/1.chip_sw_otp_ctrl_lc_signals_test_unlocked0.1970597838 Aug 14 05:50:22 PM PDT 24 Aug 14 06:02:21 PM PDT 24 4525934664 ps
T862 /workspace/coverage/default/0.rom_e2e_keymgr_init_rom_ext_invalid_meas.1061490038 Aug 14 05:58:35 PM PDT 24 Aug 14 06:50:37 PM PDT 24 14658817700 ps
T354 /workspace/coverage/default/0.chip_sw_rstmgr_alert_info.2330959948 Aug 14 05:52:37 PM PDT 24 Aug 14 06:19:13 PM PDT 24 8970667738 ps
T502 /workspace/coverage/default/54.chip_sw_all_escalation_resets.323423138 Aug 14 06:14:52 PM PDT 24 Aug 14 06:21:24 PM PDT 24 5554889336 ps
T863 /workspace/coverage/default/0.chip_sw_usbdev_config_host.2965113243 Aug 14 05:49:36 PM PDT 24 Aug 14 06:23:44 PM PDT 24 7680589128 ps
T864 /workspace/coverage/default/2.chip_sw_uart_rand_baudrate.4173428860 Aug 14 05:57:39 PM PDT 24 Aug 14 06:21:37 PM PDT 24 8400653988 ps
T865 /workspace/coverage/default/2.chip_sw_hmac_enc_idle.2393943685 Aug 14 06:03:32 PM PDT 24 Aug 14 06:09:06 PM PDT 24 3149962178 ps
T151 /workspace/coverage/default/1.chip_sw_ast_clk_rst_inputs.1423093163 Aug 14 05:54:34 PM PDT 24 Aug 14 06:42:55 PM PDT 24 20628233871 ps
T866 /workspace/coverage/default/4.chip_sw_uart_rand_baudrate.4137423627 Aug 14 06:08:27 PM PDT 24 Aug 14 06:29:37 PM PDT 24 8930637432 ps
T867 /workspace/coverage/default/0.chip_sw_hmac_oneshot.762242814 Aug 14 05:51:37 PM PDT 24 Aug 14 05:58:53 PM PDT 24 3241854508 ps
T868 /workspace/coverage/default/2.chip_sw_flash_ctrl_access.2975280405 Aug 14 06:00:47 PM PDT 24 Aug 14 06:18:44 PM PDT 24 5037701912 ps
T30 /workspace/coverage/default/2.chip_sw_sleep_pin_mio_dio_val.1137840202 Aug 14 05:55:55 PM PDT 24 Aug 14 05:59:54 PM PDT 24 2587758014 ps
T284 /workspace/coverage/default/33.chip_sw_all_escalation_resets.363776983 Aug 14 06:14:38 PM PDT 24 Aug 14 06:25:03 PM PDT 24 5668733552 ps
T869 /workspace/coverage/default/0.chip_sw_uart_tx_rx_idx1.4165572197 Aug 14 05:47:33 PM PDT 24 Aug 14 06:00:29 PM PDT 24 4921265696 ps
T870 /workspace/coverage/default/0.chip_sw_hmac_enc_jitter_en_reduced_freq.3693791304 Aug 14 05:52:16 PM PDT 24 Aug 14 05:57:39 PM PDT 24 3853058528 ps
T492 /workspace/coverage/default/64.chip_sw_all_escalation_resets.3462861824 Aug 14 06:14:00 PM PDT 24 Aug 14 06:23:46 PM PDT 24 5242741334 ps
T871 /workspace/coverage/default/0.chip_sw_otp_ctrl_ecc_error_vendor_test.636380354 Aug 14 05:47:02 PM PDT 24 Aug 14 05:51:09 PM PDT 24 3235618798 ps
T158 /workspace/coverage/default/0.chip_sw_spi_device_pass_through_collision.194454043 Aug 14 05:49:34 PM PDT 24 Aug 14 06:01:55 PM PDT 24 5285688700 ps
T159 /workspace/coverage/default/2.chip_sw_spi_device_pass_through_collision.1515059698 Aug 14 05:59:50 PM PDT 24 Aug 14 06:08:35 PM PDT 24 5317262474 ps
T872 /workspace/coverage/default/1.chip_sw_clkmgr_smoketest.1663056862 Aug 14 05:55:55 PM PDT 24 Aug 14 05:59:56 PM PDT 24 2524573894 ps
T873 /workspace/coverage/default/0.chip_sw_aon_timer_sleep_wdog_sleep_pause.2102956524 Aug 14 05:48:05 PM PDT 24 Aug 14 05:54:26 PM PDT 24 7610573920 ps
T874 /workspace/coverage/default/2.chip_sw_sram_ctrl_scrambled_access_jitter_en.753575252 Aug 14 06:03:30 PM PDT 24 Aug 14 06:14:10 PM PDT 24 5541601660 ps
T875 /workspace/coverage/default/56.chip_sw_all_escalation_resets.875673311 Aug 14 06:14:03 PM PDT 24 Aug 14 06:25:15 PM PDT 24 6056374652 ps
T876 /workspace/coverage/default/22.chip_sw_alert_handler_lpg_sleep_mode_alerts.2238890551 Aug 14 06:13:09 PM PDT 24 Aug 14 06:19:03 PM PDT 24 3950805810 ps
T877 /workspace/coverage/default/0.chip_sw_edn_entropy_reqs_jitter.1423306418 Aug 14 05:51:39 PM PDT 24 Aug 14 06:11:47 PM PDT 24 6764993412 ps
T878 /workspace/coverage/default/1.chip_sw_alert_handler_escalation.89964312 Aug 14 05:55:33 PM PDT 24 Aug 14 06:04:17 PM PDT 24 4403166224 ps
T879 /workspace/coverage/default/1.chip_sw_rstmgr_sw_rst.3497970786 Aug 14 05:48:26 PM PDT 24 Aug 14 05:51:47 PM PDT 24 2757754312 ps
T880 /workspace/coverage/default/1.chip_sw_uart_tx_rx_alt_clk_freq_low_speed.679452224 Aug 14 05:54:17 PM PDT 24 Aug 14 06:13:35 PM PDT 24 8777437725 ps
T881 /workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_slow_dev.1094173170 Aug 14 05:54:06 PM PDT 24 Aug 14 06:03:52 PM PDT 24 4833744320 ps
T491 /workspace/coverage/default/75.chip_sw_alert_handler_lpg_sleep_mode_alerts.3646736323 Aug 14 06:14:54 PM PDT 24 Aug 14 06:22:38 PM PDT 24 4515451048 ps
T882 /workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_bad_dev.951064512 Aug 14 05:58:13 PM PDT 24 Aug 14 07:33:04 PM PDT 24 22872253856 ps
T883 /workspace/coverage/default/1.chip_sw_flash_ctrl_clock_freqs.804194549 Aug 14 05:55:28 PM PDT 24 Aug 14 06:18:06 PM PDT 24 6448009041 ps
T884 /workspace/coverage/default/1.chip_sw_otbn_randomness.1973538530 Aug 14 05:50:52 PM PDT 24 Aug 14 06:09:40 PM PDT 24 6056083576 ps
T885 /workspace/coverage/default/0.chip_sw_otp_ctrl_lc_signals_dev.1131071579 Aug 14 05:52:25 PM PDT 24 Aug 14 06:14:24 PM PDT 24 8485555300 ps
T98 /workspace/coverage/default/0.chip_sw_usbdev_aon_pullup.3556338891 Aug 14 05:46:51 PM PDT 24 Aug 14 05:55:47 PM PDT 24 3997202260 ps
T886 /workspace/coverage/default/2.chip_sw_clkmgr_reset_frequency.1514848694 Aug 14 06:05:51 PM PDT 24 Aug 14 06:13:43 PM PDT 24 3132895368 ps
T887 /workspace/coverage/default/14.chip_sw_uart_rand_baudrate.1734302930 Aug 14 06:10:57 PM PDT 24 Aug 14 06:33:59 PM PDT 24 7474685830 ps
T888 /workspace/coverage/default/2.chip_sw_uart_tx_rx_alt_clk_freq_low_speed.3889957345 Aug 14 05:58:46 PM PDT 24 Aug 14 06:08:36 PM PDT 24 4642367982 ps
T889 /workspace/coverage/default/0.chip_sw_pwrmgr_random_sleep_power_glitch_reset.2413844638 Aug 14 05:48:48 PM PDT 24 Aug 14 06:39:42 PM PDT 24 39499568418 ps
T890 /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_good_test_unlocked0.769343367 Aug 14 05:58:28 PM PDT 24 Aug 14 06:55:00 PM PDT 24 11285567982 ps
T891 /workspace/coverage/default/2.chip_sw_pwrmgr_usb_clk_disabled_when_active.299217343 Aug 14 06:00:47 PM PDT 24 Aug 14 06:07:12 PM PDT 24 4163534326 ps
T409 /workspace/coverage/default/0.chip_sw_pwrmgr_deep_sleep_all_wake_ups.141241280 Aug 14 05:51:37 PM PDT 24 Aug 14 06:19:41 PM PDT 24 22295598306 ps
T81 /workspace/coverage/default/0.chip_sw_spi_device_pinmux_sleep_retention.275008573 Aug 14 05:47:56 PM PDT 24 Aug 14 05:54:38 PM PDT 24 4093338338 ps
T892 /workspace/coverage/default/0.chip_sw_alert_handler_ping_ok.2780322656 Aug 14 05:47:44 PM PDT 24 Aug 14 06:08:32 PM PDT 24 7264949394 ps
T893 /workspace/coverage/default/2.chip_sw_i2c_host_tx_rx_idx1.705480966 Aug 14 05:59:06 PM PDT 24 Aug 14 06:11:08 PM PDT 24 4644118820 ps
T533 /workspace/coverage/default/15.chip_sw_alert_handler_lpg_sleep_mode_alerts.1008606446 Aug 14 06:10:19 PM PDT 24 Aug 14 06:17:56 PM PDT 24 3972561652 ps
T894 /workspace/coverage/default/2.chip_sw_sysrst_ctrl_in_irq.325561092 Aug 14 06:01:18 PM PDT 24 Aug 14 06:13:48 PM PDT 24 4732238143 ps
T895 /workspace/coverage/default/2.chip_sw_sysrst_ctrl_ec_rst_l.2614301713 Aug 14 06:02:15 PM PDT 24 Aug 14 07:15:06 PM PDT 24 19978471641 ps
T896 /workspace/coverage/default/0.chip_sw_keymgr_sideload_kmac.1099139874 Aug 14 05:49:51 PM PDT 24 Aug 14 06:18:03 PM PDT 24 7699041036 ps
T897 /workspace/coverage/default/2.chip_sw_alert_handler_ping_ok.1759511302 Aug 14 06:03:50 PM PDT 24 Aug 14 06:24:22 PM PDT 24 7637888472 ps
T898 /workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_bad_prod_end.285438408 Aug 14 05:55:06 PM PDT 24 Aug 14 07:33:26 PM PDT 24 24196042887 ps
T899 /workspace/coverage/default/4.chip_sw_lc_ctrl_transition.1917944712 Aug 14 06:08:26 PM PDT 24 Aug 14 06:16:28 PM PDT 24 6646878227 ps
T900 /workspace/coverage/default/1.chip_sw_lc_ctrl_transition.2235019686 Aug 14 05:49:39 PM PDT 24 Aug 14 06:05:08 PM PDT 24 11768029432 ps
T901 /workspace/coverage/default/0.chip_sw_aes_entropy.1641961324 Aug 14 05:51:18 PM PDT 24 Aug 14 05:56:45 PM PDT 24 2947316352 ps
T521 /workspace/coverage/default/3.chip_sw_alert_handler_lpg_sleep_mode_alerts.49105368 Aug 14 06:08:57 PM PDT 24 Aug 14 06:15:15 PM PDT 24 3846907890 ps
T902 /workspace/coverage/default/1.chip_sw_alert_handler_reverse_ping_in_deep_sleep.3842652171 Aug 14 05:51:02 PM PDT 24 Aug 14 09:15:04 PM PDT 24 255649805900 ps
T903 /workspace/coverage/default/0.chip_sw_rom_ctrl_integrity_check.3623465937 Aug 14 05:50:13 PM PDT 24 Aug 14 05:58:41 PM PDT 24 9087142212 ps
T904 /workspace/coverage/default/0.chip_sw_lc_ctrl_otp_hw_cfg0.934520610 Aug 14 05:48:33 PM PDT 24 Aug 14 05:53:47 PM PDT 24 3538917240 ps
T905 /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0.1661988020 Aug 14 05:57:43 PM PDT 24 Aug 14 06:48:58 PM PDT 24 11227034120 ps
T906 /workspace/coverage/default/1.chip_sw_otbn_ecdsa_op_irq.3712513311 Aug 14 05:51:37 PM PDT 24 Aug 14 06:51:56 PM PDT 24 17578632936 ps
T907 /workspace/coverage/default/0.chip_sw_clkmgr_off_otbn_trans.3632750672 Aug 14 05:52:46 PM PDT 24 Aug 14 06:04:40 PM PDT 24 4689820270 ps
T908 /workspace/coverage/default/1.chip_sw_uart_rand_baudrate.1280219704 Aug 14 05:49:13 PM PDT 24 Aug 14 06:01:35 PM PDT 24 4495966234 ps
T527 /workspace/coverage/default/30.chip_sw_all_escalation_resets.1197669483 Aug 14 06:14:56 PM PDT 24 Aug 14 06:24:08 PM PDT 24 4771115090 ps
T909 /workspace/coverage/default/2.chip_sw_kmac_smoketest.1424697573 Aug 14 06:10:45 PM PDT 24 Aug 14 06:16:53 PM PDT 24 3318733856 ps
T910 /workspace/coverage/default/2.chip_sw_lc_ctrl_otp_hw_cfg0.1665000305 Aug 14 05:59:14 PM PDT 24 Aug 14 06:05:25 PM PDT 24 3455643200 ps
T204 /workspace/coverage/default/2.chip_sw_otp_ctrl_vendor_test_csr_access.2727091871 Aug 14 06:00:11 PM PDT 24 Aug 14 06:04:45 PM PDT 24 2647693396 ps
T455 /workspace/coverage/default/62.chip_sw_all_escalation_resets.712094319 Aug 14 06:14:36 PM PDT 24 Aug 14 06:27:03 PM PDT 24 5426202350 ps
T911 /workspace/coverage/default/3.chip_sw_uart_tx_rx_idx3.3525509453 Aug 14 06:10:47 PM PDT 24 Aug 14 06:22:05 PM PDT 24 3781330710 ps
T434 /workspace/coverage/default/0.chip_sw_rv_dm_access_after_escalation_reset.989269666 Aug 14 05:51:45 PM PDT 24 Aug 14 06:01:42 PM PDT 24 4863309151 ps
T912 /workspace/coverage/default/0.chip_sw_gpio_smoketest.2782777014 Aug 14 05:55:15 PM PDT 24 Aug 14 06:00:37 PM PDT 24 3034652423 ps
T913 /workspace/coverage/default/1.chip_sw_example_rom.3663383188 Aug 14 05:52:55 PM PDT 24 Aug 14 05:54:59 PM PDT 24 2419880968 ps
T914 /workspace/coverage/default/1.chip_sw_clkmgr_off_kmac_trans.2568403517 Aug 14 05:55:28 PM PDT 24 Aug 14 06:02:14 PM PDT 24 3619510100 ps
T915 /workspace/coverage/default/4.chip_sw_uart_tx_rx_idx2.1040405681 Aug 14 06:08:36 PM PDT 24 Aug 14 06:19:06 PM PDT 24 4135270334 ps
T916 /workspace/coverage/default/0.chip_sw_kmac_smoketest.3601612900 Aug 14 05:49:02 PM PDT 24 Aug 14 05:53:44 PM PDT 24 2695824218 ps
T364 /workspace/coverage/default/1.chip_sw_pwrmgr_lowpower_cancel.3644681515 Aug 14 05:51:58 PM PDT 24 Aug 14 05:59:23 PM PDT 24 3917750016 ps
T917 /workspace/coverage/default/0.chip_sw_otbn_smoketest.1373602486 Aug 14 05:54:11 PM PDT 24 Aug 14 06:20:21 PM PDT 24 6218853064 ps
T918 /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_good_dev.1495369111 Aug 14 05:52:36 PM PDT 24 Aug 14 06:53:49 PM PDT 24 15833409208 ps
T919 /workspace/coverage/default/2.rom_e2e_shutdown_output.3207959012 Aug 14 06:11:39 PM PDT 24 Aug 14 07:11:00 PM PDT 24 23307533907 ps
T920 /workspace/coverage/default/0.chip_sw_lc_ctrl_raw_to_scrap.2998505917 Aug 14 05:47:30 PM PDT 24 Aug 14 05:50:06 PM PDT 24 3040491826 ps
T921 /workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_slow_rma.2359424595 Aug 14 05:52:11 PM PDT 24 Aug 14 06:02:21 PM PDT 24 5169545960 ps
T922 /workspace/coverage/default/0.chip_sw_aon_timer_irq.3806139653 Aug 14 05:47:22 PM PDT 24 Aug 14 05:54:50 PM PDT 24 3993351600 ps
T160 /workspace/coverage/default/2.chip_plic_all_irqs_10.1929498433 Aug 14 06:05:24 PM PDT 24 Aug 14 06:13:34 PM PDT 24 3617045842 ps
T923 /workspace/coverage/default/0.chip_sw_otbn_randomness.476327122 Aug 14 05:51:48 PM PDT 24 Aug 14 06:08:58 PM PDT 24 6313778048 ps
T152 /workspace/coverage/default/0.chip_sw_ast_clk_rst_inputs.2824144296 Aug 14 05:48:16 PM PDT 24 Aug 14 06:52:40 PM PDT 24 25989495262 ps
T924 /workspace/coverage/default/0.chip_sw_otp_ctrl_smoketest.4028148860 Aug 14 05:54:57 PM PDT 24 Aug 14 05:58:51 PM PDT 24 2795872332 ps
T925 /workspace/coverage/default/0.chip_sw_rv_timer_irq.3972068454 Aug 14 05:49:06 PM PDT 24 Aug 14 05:55:00 PM PDT 24 3273635312 ps
T523 /workspace/coverage/default/86.chip_sw_alert_handler_lpg_sleep_mode_alerts.1758629285 Aug 14 06:16:46 PM PDT 24 Aug 14 06:24:08 PM PDT 24 3613544204 ps
T147 /workspace/coverage/default/2.chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup.4199516827 Aug 14 06:04:06 PM PDT 24 Aug 14 06:12:52 PM PDT 24 5504464906 ps
T926 /workspace/coverage/default/2.chip_sw_lc_walkthrough_dev.54077757 Aug 14 06:00:20 PM PDT 24 Aug 14 07:28:36 PM PDT 24 45976979635 ps
T542 /workspace/coverage/default/63.chip_sw_alert_handler_lpg_sleep_mode_alerts.675937332 Aug 14 06:19:22 PM PDT 24 Aug 14 06:25:59 PM PDT 24 3709342876 ps
T927 /workspace/coverage/default/2.rom_e2e_smoke.1407146013 Aug 14 06:14:45 PM PDT 24 Aug 14 07:05:49 PM PDT 24 14510883386 ps
T928 /workspace/coverage/default/2.chip_sw_uart_smoketest.2736377752 Aug 14 06:07:22 PM PDT 24 Aug 14 06:10:54 PM PDT 24 2656426158 ps
T929 /workspace/coverage/default/0.chip_sw_sleep_sram_ret_contents_no_scramble.2062671508 Aug 14 05:49:09 PM PDT 24 Aug 14 06:05:42 PM PDT 24 9632212088 ps
T930 /workspace/coverage/default/0.chip_sw_usbdev_stream.3323794249 Aug 14 05:47:58 PM PDT 24 Aug 14 06:58:05 PM PDT 24 19146102382 ps
T931 /workspace/coverage/default/2.chip_sw_otbn_smoketest.3542603150 Aug 14 06:08:20 PM PDT 24 Aug 14 06:26:27 PM PDT 24 6464075210 ps
T932 /workspace/coverage/default/2.chip_sw_uart_tx_rx.819885283 Aug 14 05:56:55 PM PDT 24 Aug 14 06:09:07 PM PDT 24 4161300360 ps
T933 /workspace/coverage/default/2.chip_sw_clkmgr_jitter_frequency.872058532 Aug 14 06:05:53 PM PDT 24 Aug 14 06:14:03 PM PDT 24 3550677500 ps
T934 /workspace/coverage/default/0.chip_sw_kmac_mode_cshake.119801184 Aug 14 05:47:19 PM PDT 24 Aug 14 05:50:05 PM PDT 24 3384689118 ps
T935 /workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0.492467840 Aug 14 06:04:08 PM PDT 24 Aug 14 06:16:31 PM PDT 24 4442272540 ps
T372 /workspace/coverage/default/1.chip_sw_pattgen_ios.3365307363 Aug 14 05:52:02 PM PDT 24 Aug 14 05:55:45 PM PDT 24 2657805252 ps
T936 /workspace/coverage/default/2.chip_sw_flash_init_reduced_freq.2949388467 Aug 14 06:05:53 PM PDT 24 Aug 14 06:47:47 PM PDT 24 27309054899 ps
T937 /workspace/coverage/default/0.chip_sw_example_flash.817116318 Aug 14 05:47:02 PM PDT 24 Aug 14 05:51:52 PM PDT 24 2556825164 ps
T938 /workspace/coverage/default/0.chip_sw_flash_ctrl_ops_jitter_en_reduced_freq.257270447 Aug 14 05:51:46 PM PDT 24 Aug 14 06:04:25 PM PDT 24 4611491808 ps
T48 /workspace/coverage/default/0.chip_sw_gpio.1118647925 Aug 14 05:46:57 PM PDT 24 Aug 14 05:54:27 PM PDT 24 3633598297 ps
T939 /workspace/coverage/default/5.chip_sw_alert_handler_lpg_sleep_mode_alerts.535824307 Aug 14 06:10:25 PM PDT 24 Aug 14 06:17:09 PM PDT 24 3788434840 ps
T940 /workspace/coverage/default/0.chip_sw_pwrmgr_wdog_reset.1781887503 Aug 14 05:50:45 PM PDT 24 Aug 14 06:01:14 PM PDT 24 4984277750 ps
T941 /workspace/coverage/default/0.chip_sw_uart_smoketest.1817925010 Aug 14 05:52:18 PM PDT 24 Aug 14 05:57:01 PM PDT 24 3372433236 ps
T942 /workspace/coverage/default/0.chip_sw_lc_walkthrough_dev.2879549669 Aug 14 05:47:26 PM PDT 24 Aug 14 07:21:05 PM PDT 24 48981709908 ps
T392 /workspace/coverage/default/2.chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up.2538232362 Aug 14 06:03:55 PM PDT 24 Aug 14 06:10:50 PM PDT 24 6550889320 ps
T943 /workspace/coverage/default/0.chip_sw_kmac_entropy.1348261882 Aug 14 05:50:33 PM PDT 24 Aug 14 05:56:16 PM PDT 24 3256428338 ps
T944 /workspace/coverage/default/52.chip_sw_all_escalation_resets.3652588330 Aug 14 06:12:59 PM PDT 24 Aug 14 06:22:15 PM PDT 24 5675970984 ps
T552 /workspace/coverage/default/48.chip_sw_all_escalation_resets.2654425894 Aug 14 06:13:04 PM PDT 24 Aug 14 06:24:16 PM PDT 24 6148417544 ps
T445 /workspace/coverage/default/26.chip_sw_all_escalation_resets.2448680340 Aug 14 06:12:35 PM PDT 24 Aug 14 06:25:38 PM PDT 24 5753462372 ps
T945 /workspace/coverage/default/2.chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz.3271668458 Aug 14 06:00:15 PM PDT 24 Aug 14 06:02:20 PM PDT 24 2610675393 ps
T946 /workspace/coverage/default/2.chip_sw_hmac_enc_jitter_en_reduced_freq.1232999406 Aug 14 06:06:21 PM PDT 24 Aug 14 06:10:38 PM PDT 24 2609873474 ps
T947 /workspace/coverage/default/1.chip_sw_pwrmgr_deep_sleep_por_reset.3971983509 Aug 14 05:53:58 PM PDT 24 Aug 14 06:08:21 PM PDT 24 7576988358 ps
T948 /workspace/coverage/default/2.chip_sw_rstmgr_sw_rst.3899334366 Aug 14 06:00:40 PM PDT 24 Aug 14 06:05:36 PM PDT 24 3159629952 ps
T949 /workspace/coverage/default/0.chip_sw_pwrmgr_sysrst_ctrl_reset.3140059963 Aug 14 05:50:23 PM PDT 24 Aug 14 06:06:21 PM PDT 24 7731209212 ps
T161 /workspace/coverage/default/1.chip_plic_all_irqs_10.2416229857 Aug 14 05:53:40 PM PDT 24 Aug 14 06:03:57 PM PDT 24 3866273440 ps
T950 /workspace/coverage/default/0.chip_sw_lc_walkthrough_rma.2145703450 Aug 14 05:48:31 PM PDT 24 Aug 14 07:12:49 PM PDT 24 47055787186 ps
T951 /workspace/coverage/default/1.chip_sw_lc_ctrl_rand_to_scrap.215964421 Aug 14 05:54:29 PM PDT 24 Aug 14 05:56:46 PM PDT 24 2418637326 ps
T952 /workspace/coverage/default/1.chip_sw_hmac_enc_jitter_en_reduced_freq.1913352854 Aug 14 05:52:27 PM PDT 24 Aug 14 05:55:43 PM PDT 24 3160863641 ps
T953 /workspace/coverage/default/2.chip_sw_inject_scramble_seed.3878279337 Aug 14 05:57:12 PM PDT 24 Aug 14 09:15:49 PM PDT 24 64710991223 ps
T954 /workspace/coverage/default/1.chip_sw_pwrmgr_sysrst_ctrl_reset.1395772951 Aug 14 05:49:55 PM PDT 24 Aug 14 06:09:44 PM PDT 24 7736484120 ps
T516 /workspace/coverage/default/94.chip_sw_all_escalation_resets.2362478035 Aug 14 06:18:36 PM PDT 24 Aug 14 06:27:08 PM PDT 24 5534454136 ps
T444 /workspace/coverage/default/19.chip_sw_alert_handler_lpg_sleep_mode_alerts.2870813608 Aug 14 06:11:56 PM PDT 24 Aug 14 06:22:08 PM PDT 24 4364159728 ps
T309 /workspace/coverage/default/0.chip_sw_rv_core_ibex_address_translation.38789760 Aug 14 05:52:15 PM PDT 24 Aug 14 05:57:27 PM PDT 24 3539062698 ps
T955 /workspace/coverage/default/0.chip_sw_sysrst_ctrl_in_irq.2974211295 Aug 14 05:51:22 PM PDT 24 Aug 14 06:01:18 PM PDT 24 5164848978 ps
T956 /workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0.3524758816 Aug 14 05:47:25 PM PDT 24 Aug 14 05:57:27 PM PDT 24 3978964728 ps
T957 /workspace/coverage/default/0.chip_sw_kmac_mode_kmac_jitter_en_reduced_freq.2487322091 Aug 14 05:53:11 PM PDT 24 Aug 14 05:58:49 PM PDT 24 3529780709 ps
T958 /workspace/coverage/default/60.chip_sw_alert_handler_lpg_sleep_mode_alerts.1196967227 Aug 14 06:15:30 PM PDT 24 Aug 14 06:22:08 PM PDT 24 4053519618 ps
T959 /workspace/coverage/default/2.chip_sw_uart_tx_rx_idx2.1680419242 Aug 14 05:59:13 PM PDT 24 Aug 14 06:12:21 PM PDT 24 4115252694 ps
T960 /workspace/coverage/default/2.chip_sw_example_concurrency.1053477995 Aug 14 05:57:09 PM PDT 24 Aug 14 06:01:33 PM PDT 24 3176496560 ps
T961 /workspace/coverage/default/2.chip_sw_edn_entropy_reqs_jitter.2922234599 Aug 14 06:05:45 PM PDT 24 Aug 14 06:26:03 PM PDT 24 8010141264 ps
T962 /workspace/coverage/default/2.chip_sw_sysrst_ctrl_inputs.794436298 Aug 14 06:01:25 PM PDT 24 Aug 14 06:06:10 PM PDT 24 3078174109 ps
T963 /workspace/coverage/default/0.chip_sw_lc_ctrl_volatile_raw_unlock.177636348 Aug 14 05:49:26 PM PDT 24 Aug 14 05:51:55 PM PDT 24 2037934250 ps
T108 /workspace/coverage/default/0.chip_sw_alert_handler_lpg_sleep_mode_alerts.697883980 Aug 14 05:51:51 PM PDT 24 Aug 14 05:58:22 PM PDT 24 3890205648 ps
T964 /workspace/coverage/default/1.chip_sw_edn_auto_mode.1089498756 Aug 14 05:49:58 PM PDT 24 Aug 14 06:07:51 PM PDT 24 4145514640 ps
T965 /workspace/coverage/default/2.chip_sw_aes_idle.2991549210 Aug 14 06:02:24 PM PDT 24 Aug 14 06:08:27 PM PDT 24 3269599048 ps
T966 /workspace/coverage/default/2.chip_sw_keymgr_key_derivation_jitter_en_reduced_freq.1583898278 Aug 14 06:06:19 PM PDT 24 Aug 14 06:28:55 PM PDT 24 9293240808 ps
T967 /workspace/coverage/default/0.chip_sw_entropy_src_smoketest.1375199814 Aug 14 05:55:17 PM PDT 24 Aug 14 06:06:22 PM PDT 24 3681773880 ps
T968 /workspace/coverage/default/14.chip_sw_lc_ctrl_transition.2585573117 Aug 14 06:09:29 PM PDT 24 Aug 14 06:17:49 PM PDT 24 6613668312 ps
T969 /workspace/coverage/default/1.chip_sw_pwrmgr_random_sleep_power_glitch_reset.103355688 Aug 14 05:50:19 PM PDT 24 Aug 14 06:44:09 PM PDT 24 43880686236 ps
T970 /workspace/coverage/default/1.chip_sw_otp_ctrl_lc_signals_prod.2306312186 Aug 14 05:52:20 PM PDT 24 Aug 14 06:19:26 PM PDT 24 8827760814 ps
T546 /workspace/coverage/default/37.chip_sw_alert_handler_lpg_sleep_mode_alerts.2001034895 Aug 14 06:12:18 PM PDT 24 Aug 14 06:18:40 PM PDT 24 3691798552 ps
T971 /workspace/coverage/default/1.chip_sw_rstmgr_smoketest.3182290659 Aug 14 05:54:19 PM PDT 24 Aug 14 05:57:09 PM PDT 24 2794261306 ps
T972 /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_bad_b_good_prod_end.482111310 Aug 14 05:56:52 PM PDT 24 Aug 14 07:33:09 PM PDT 24 23520724314 ps
T973 /workspace/coverage/default/0.chip_sw_otbn_ecdsa_op_irq.302520154 Aug 14 05:50:14 PM PDT 24 Aug 14 06:51:13 PM PDT 24 17779718600 ps
T974 /workspace/coverage/default/68.chip_sw_alert_handler_lpg_sleep_mode_alerts.861073642 Aug 14 06:16:00 PM PDT 24 Aug 14 06:22:43 PM PDT 24 4214848496 ps
T476 /workspace/coverage/default/2.chip_sw_alert_handler_lpg_sleep_mode_pings.3668341477 Aug 14 06:02:04 PM PDT 24 Aug 14 06:24:21 PM PDT 24 11619422500 ps
T975 /workspace/coverage/default/3.chip_tap_straps_testunlock0.1083174402 Aug 14 06:08:26 PM PDT 24 Aug 14 06:22:33 PM PDT 24 9435610453 ps
T976 /workspace/coverage/default/0.rom_e2e_smoke.1421288190 Aug 14 05:52:41 PM PDT 24 Aug 14 06:48:37 PM PDT 24 14764502648 ps
T977 /workspace/coverage/default/2.chip_sw_sram_ctrl_smoketest.2530374983 Aug 14 06:07:06 PM PDT 24 Aug 14 06:11:13 PM PDT 24 2923396856 ps
T76 /workspace/coverage/default/2.chip_sw_alert_test.1645554855 Aug 14 06:03:05 PM PDT 24 Aug 14 06:08:58 PM PDT 24 3130431026 ps
T978 /workspace/coverage/default/0.chip_sw_rv_timer_smoketest.1232080088 Aug 14 05:49:01 PM PDT 24 Aug 14 05:52:28 PM PDT 24 2923975432 ps
T979 /workspace/coverage/default/4.chip_sw_uart_tx_rx_idx3.3103859702 Aug 14 06:08:54 PM PDT 24 Aug 14 06:18:25 PM PDT 24 4553233976 ps
T79 /workspace/coverage/default/0.chip_sw_sleep_pin_retention.429939694 Aug 14 05:48:38 PM PDT 24 Aug 14 05:53:32 PM PDT 24 3135395516 ps
T980 /workspace/coverage/default/3.chip_sw_all_escalation_resets.1407285796 Aug 14 06:10:43 PM PDT 24 Aug 14 06:21:51 PM PDT 24 4465912100 ps
T235 /workspace/coverage/default/2.chip_plic_all_irqs_0.2944717956 Aug 14 06:07:05 PM PDT 24 Aug 14 06:25:13 PM PDT 24 5583120440 ps
T981 /workspace/coverage/default/13.chip_sw_uart_rand_baudrate.1724338929 Aug 14 06:10:39 PM PDT 24 Aug 14 06:51:01 PM PDT 24 12655780684 ps
T982 /workspace/coverage/default/0.chip_sw_flash_init_reduced_freq.1173704223 Aug 14 05:48:16 PM PDT 24 Aug 14 06:27:50 PM PDT 24 20165379843 ps
T983 /workspace/coverage/default/0.chip_sw_alert_handler_escalation.1781380768 Aug 14 05:49:22 PM PDT 24 Aug 14 05:56:30 PM PDT 24 5664499834 ps
T984 /workspace/coverage/default/0.chip_sw_clkmgr_off_kmac_trans.1407769253 Aug 14 05:48:35 PM PDT 24 Aug 14 05:57:57 PM PDT 24 5549991428 ps
T985 /workspace/coverage/default/0.rom_e2e_asm_init_dev.2966699942 Aug 14 05:55:35 PM PDT 24 Aug 14 06:53:09 PM PDT 24 15148177442 ps
T543 /workspace/coverage/default/34.chip_sw_all_escalation_resets.1100196119 Aug 14 06:11:14 PM PDT 24 Aug 14 06:21:56 PM PDT 24 5400733448 ps
T356 /workspace/coverage/default/0.chip_sw_entropy_src_csrng.2206941932 Aug 14 05:47:23 PM PDT 24 Aug 14 06:20:14 PM PDT 24 7325500244 ps
T986 /workspace/coverage/default/0.chip_sw_uart_rand_baudrate.2705701331 Aug 14 05:50:14 PM PDT 24 Aug 14 06:33:22 PM PDT 24 12956566642 ps
T150 /workspace/coverage/default/1.chip_sw_sensor_ctrl_alert.222439706 Aug 14 05:51:40 PM PDT 24 Aug 14 06:05:38 PM PDT 24 8274758256 ps
T987 /workspace/coverage/default/1.chip_sw_example_concurrency.581397730 Aug 14 05:54:06 PM PDT 24 Aug 14 05:59:09 PM PDT 24 2920504672 ps
T988 /workspace/coverage/default/0.chip_sw_uart_tx_rx.2492479492 Aug 14 05:46:35 PM PDT 24 Aug 14 05:58:27 PM PDT 24 5096692744 ps
T989 /workspace/coverage/default/0.chip_sw_rv_plic_smoketest.3773010433 Aug 14 05:51:11 PM PDT 24 Aug 14 05:57:15 PM PDT 24 2875357320 ps
T990 /workspace/coverage/default/2.chip_sw_aon_timer_irq.2250092850 Aug 14 06:02:21 PM PDT 24 Aug 14 06:08:13 PM PDT 24 3667633992 ps
T991 /workspace/coverage/default/0.chip_sw_pwrmgr_all_reset_reqs.2538806786 Aug 14 05:49:11 PM PDT 24 Aug 14 06:17:33 PM PDT 24 12392093476 ps
T17 /workspace/coverage/default/1.chip_jtag_csr_rw.1581544171 Aug 14 05:42:59 PM PDT 24 Aug 14 06:04:58 PM PDT 24 11910022560 ps
T493 /workspace/coverage/default/1.chip_sw_all_escalation_resets.3341942489 Aug 14 05:56:05 PM PDT 24 Aug 14 06:08:17 PM PDT 24 5837048112 ps
T319 /workspace/coverage/default/0.rom_e2e_jtag_debug_test_unlocked0.3082388561 Aug 14 05:52:43 PM PDT 24 Aug 14 06:25:59 PM PDT 24 10651394463 ps
T394 /workspace/coverage/default/74.chip_sw_alert_handler_lpg_sleep_mode_alerts.1911397241 Aug 14 06:18:31 PM PDT 24 Aug 14 06:23:27 PM PDT 24 3545238786 ps
T992 /workspace/coverage/default/1.chip_sw_aes_masking_off.1911974217 Aug 14 05:53:28 PM PDT 24 Aug 14 05:58:28 PM PDT 24 2961789903 ps
T993 /workspace/coverage/default/2.chip_sw_csrng_lc_hw_debug_en_test.2470563069 Aug 14 06:03:22 PM PDT 24 Aug 14 06:15:35 PM PDT 24 5976347652 ps
T994 /workspace/coverage/default/0.chip_sw_otp_ctrl_dai_lock.4247762464 Aug 14 05:49:14 PM PDT 24 Aug 14 07:20:26 PM PDT 24 27941474400 ps
T410 /workspace/coverage/default/1.chip_sw_pwrmgr_deep_sleep_all_wake_ups.1950508654 Aug 14 05:59:11 PM PDT 24 Aug 14 06:30:18 PM PDT 24 26631273892 ps
T517 /workspace/coverage/default/16.chip_sw_all_escalation_resets.2399394796 Aug 14 06:12:09 PM PDT 24 Aug 14 06:25:15 PM PDT 24 5502643368 ps
T995 /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_bad_prod_end.457665714 Aug 14 05:52:57 PM PDT 24 Aug 14 06:49:17 PM PDT 24 15459884122 ps
T432 /workspace/coverage/default/1.chip_sw_rv_core_ibex_nmi_irq.2436918818 Aug 14 05:50:57 PM PDT 24 Aug 14 06:05:59 PM PDT 24 4584574736 ps
T199 /workspace/coverage/default/2.chip_sw_pwrmgr_random_sleep_all_wake_ups.3764479108 Aug 14 06:06:05 PM PDT 24 Aug 14 06:33:13 PM PDT 24 24521931196 ps
T333 /workspace/coverage/default/0.chip_sw_keymgr_sideload_aes.197235630 Aug 14 05:49:23 PM PDT 24 Aug 14 06:23:31 PM PDT 24 8745219208 ps
T996 /workspace/coverage/default/0.chip_sw_pwrmgr_deep_sleep_por_reset.2985225693 Aug 14 05:48:24 PM PDT 24 Aug 14 06:04:26 PM PDT 24 7305180798 ps
T997 /workspace/coverage/default/1.chip_sw_power_idle_load.2348362624 Aug 14 05:53:04 PM PDT 24 Aug 14 06:03:24 PM PDT 24 4646159448 ps
T998 /workspace/coverage/default/1.chip_sw_rv_core_ibex_lockstep_glitch.2800685560 Aug 14 05:56:41 PM PDT 24 Aug 14 06:01:17 PM PDT 24 2728042748 ps
T999 /workspace/coverage/default/2.chip_sw_edn_sw_mode.2831718181 Aug 14 06:03:43 PM PDT 24 Aug 14 06:37:39 PM PDT 24 9973820292 ps
T457 /workspace/coverage/default/38.chip_sw_alert_handler_lpg_sleep_mode_alerts.1912127956 Aug 14 06:11:17 PM PDT 24 Aug 14 06:16:53 PM PDT 24 4538016088 ps
T1000 /workspace/coverage/default/2.chip_sw_entropy_src_ast_rng_req.3942461255 Aug 14 06:03:24 PM PDT 24 Aug 14 06:06:42 PM PDT 24 2251611310 ps
T60 /workspace/coverage/default/2.chip_sw_spi_device_tpm.2002876322 Aug 14 05:59:54 PM PDT 24 Aug 14 06:06:08 PM PDT 24 3296675645 ps
T1001 /workspace/coverage/default/1.chip_sw_flash_ctrl_mem_protection.574470026 Aug 14 05:53:20 PM PDT 24 Aug 14 06:15:08 PM PDT 24 5520300742 ps
T1002 /workspace/coverage/default/1.chip_sw_pwrmgr_all_reset_reqs.2250437278 Aug 14 05:53:45 PM PDT 24 Aug 14 06:15:59 PM PDT 24 11530754395 ps
T1003 /workspace/coverage/default/2.rom_e2e_keymgr_init_rom_ext_meas.586172961 Aug 14 06:11:28 PM PDT 24 Aug 14 07:19:04 PM PDT 24 15737198600 ps
T1004 /workspace/coverage/default/0.rom_e2e_asm_init_rma.2175227750 Aug 14 05:58:22 PM PDT 24 Aug 14 06:56:47 PM PDT 24 15195708872 ps
T538 /workspace/coverage/default/25.chip_sw_alert_handler_lpg_sleep_mode_alerts.3476271838 Aug 14 06:14:02 PM PDT 24 Aug 14 06:24:17 PM PDT 24 3814162590 ps
T1005 /workspace/coverage/default/0.rom_keymgr_functest.2078191108 Aug 14 05:52:24 PM PDT 24 Aug 14 06:01:01 PM PDT 24 3697254630 ps
T361 /workspace/coverage/default/1.chip_sw_i2c_device_tx_rx.1606632428 Aug 14 05:57:09 PM PDT 24 Aug 14 06:06:27 PM PDT 24 3924629352 ps
T1006 /workspace/coverage/default/2.chip_sw_sleep_sram_ret_contents_no_scramble.2059838066 Aug 14 06:07:21 PM PDT 24 Aug 14 06:19:11 PM PDT 24 8118526600 ps
T1007 /workspace/coverage/default/10.chip_sw_all_escalation_resets.3376795541 Aug 14 06:09:40 PM PDT 24 Aug 14 06:19:29 PM PDT 24 4651255018 ps
T1008 /workspace/coverage/default/1.chip_sw_aes_entropy.3303485186 Aug 14 05:51:31 PM PDT 24 Aug 14 05:56:38 PM PDT 24 2550716860 ps
T54 /workspace/coverage/default/2.chip_sw_spi_host_tx_rx.4212819594 Aug 14 05:58:07 PM PDT 24 Aug 14 06:03:04 PM PDT 24 3169936338 ps
T1009 /workspace/coverage/default/1.chip_sw_uart_tx_rx_idx1.2989231560 Aug 14 05:53:44 PM PDT 24 Aug 14 06:04:35 PM PDT 24 4207143800 ps
T1010 /workspace/coverage/default/1.chip_sw_pwrmgr_wdog_reset.1837492992 Aug 14 05:54:19 PM PDT 24 Aug 14 06:03:46 PM PDT 24 3983685376 ps
T1011 /workspace/coverage/default/76.chip_sw_all_escalation_resets.255652197 Aug 14 06:17:49 PM PDT 24 Aug 14 06:28:09 PM PDT 24 6480723646 ps
T1012 /workspace/coverage/default/2.chip_sw_kmac_idle.4152116885 Aug 14 06:04:56 PM PDT 24 Aug 14 06:10:05 PM PDT 24 3027358400 ps
T1013 /workspace/coverage/default/0.chip_sw_kmac_mode_kmac.34413071 Aug 14 05:48:47 PM PDT 24 Aug 14 05:54:49 PM PDT 24 3124353038 ps
T1014 /workspace/coverage/default/1.chip_sw_flash_rma_unlocked.3444304045 Aug 14 05:49:39 PM PDT 24 Aug 14 07:12:20 PM PDT 24 43107286800 ps
T292 /workspace/coverage/default/0.chip_sw_data_integrity_escalation.1585329629 Aug 14 05:50:22 PM PDT 24 Aug 14 06:06:20 PM PDT 24 4722568880 ps
T1015 /workspace/coverage/default/0.chip_sw_edn_auto_mode.3974603802 Aug 14 05:52:53 PM PDT 24 Aug 14 06:31:39 PM PDT 24 7007074600 ps
T1016 /workspace/coverage/default/0.chip_sw_csrng_kat_test.3096793488 Aug 14 05:49:42 PM PDT 24 Aug 14 05:55:07 PM PDT 24 3151566776 ps
T524 /workspace/coverage/default/50.chip_sw_alert_handler_lpg_sleep_mode_alerts.986594536 Aug 14 06:14:57 PM PDT 24 Aug 14 06:21:50 PM PDT 24 3831919420 ps
T1017 /workspace/coverage/default/1.chip_sw_otp_ctrl_lc_signals_rma.2057814697 Aug 14 05:48:57 PM PDT 24 Aug 14 06:10:13 PM PDT 24 9062574872 ps
T452 /workspace/coverage/default/0.chip_sw_all_escalation_resets.2603524313 Aug 14 05:48:30 PM PDT 24 Aug 14 06:01:20 PM PDT 24 5426593120 ps
T534 /workspace/coverage/default/79.chip_sw_alert_handler_lpg_sleep_mode_alerts.404598224 Aug 14 06:16:26 PM PDT 24 Aug 14 06:21:37 PM PDT 24 3371499120 ps
T223 /workspace/coverage/default/2.chip_sw_flash_rma_unlocked.2197864360 Aug 14 05:57:46 PM PDT 24 Aug 14 07:16:17 PM PDT 24 43930190785 ps
T393 /workspace/coverage/default/4.chip_sw_sensor_ctrl_alert.165106286 Aug 14 06:08:28 PM PDT 24 Aug 14 06:24:13 PM PDT 24 6812773408 ps
T1018 /workspace/coverage/default/2.chip_sw_pwrmgr_random_sleep_all_reset_reqs.3986876188 Aug 14 06:00:18 PM PDT 24 Aug 14 06:33:04 PM PDT 24 21307337060 ps
T1019 /workspace/coverage/default/2.chip_sw_clkmgr_jitter.3835819115 Aug 14 06:05:42 PM PDT 24 Aug 14 06:08:31 PM PDT 24 3337969327 ps
T84 /workspace/coverage/default/2.chip_sw_sleep_pin_wake.2715153387 Aug 14 05:56:34 PM PDT 24 Aug 14 06:00:41 PM PDT 24 2510013756 ps
T380 /workspace/coverage/default/86.chip_sw_all_escalation_resets.3203048834 Aug 14 06:17:11 PM PDT 24 Aug 14 06:28:31 PM PDT 24 4940655480 ps
T424 /workspace/coverage/default/2.chip_sw_sysrst_ctrl_reset.210398001 Aug 14 06:01:42 PM PDT 24 Aug 14 06:29:06 PM PDT 24 24136083054 ps
T425 /workspace/coverage/default/0.chip_sw_flash_crash_alert.1353028233 Aug 14 05:52:34 PM PDT 24 Aug 14 06:02:51 PM PDT 24 5096789360 ps
T426 /workspace/coverage/default/1.chip_sw_edn_sw_mode.1209140554 Aug 14 05:55:36 PM PDT 24 Aug 14 06:35:32 PM PDT 24 9982971736 ps
T427 /workspace/coverage/default/0.chip_sw_lc_ctrl_test_locked0_to_scrap.2690022368 Aug 14 05:49:12 PM PDT 24 Aug 14 05:51:57 PM PDT 24 3836704399 ps
T428 /workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_lc.371467360 Aug 14 06:04:59 PM PDT 24 Aug 14 06:20:57 PM PDT 24 12004568013 ps
T429 /workspace/coverage/default/2.chip_sw_flash_ctrl_lc_rw_en.2753031489 Aug 14 05:59:28 PM PDT 24 Aug 14 06:12:01 PM PDT 24 6303320492 ps
T318 /workspace/coverage/default/0.chip_sw_rv_dm_ndm_reset_req_when_cpu_halted.2828273423 Aug 14 05:49:47 PM PDT 24 Aug 14 05:57:34 PM PDT 24 4123661362 ps
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