Unified Coverage Report :: Module :: i2c

Module : i2c

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
84.66			84.66

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_i2c_0.1/rtl/i2c.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.top_earlgrey.u_i2c0	84.48			84.48
tb.dut.top_earlgrey.u_i2c1	84.57			84.57
tb.dut.top_earlgrey.u_i2c2	84.57			84.57

---

Module Instance : tb.dut.top_earlgrey.u_i2c0

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
84.48			84.48

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
84.48			84.48

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
93.16	92.47		87.00			100.00	top_earlgrey

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.top_earlgrey.u_i2c1

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
84.57			84.57

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
84.57			84.57

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
93.16	92.47		87.00			100.00	top_earlgrey

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.top_earlgrey.u_i2c2

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
84.57			84.57

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
84.57			84.57

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
93.16	92.47		87.00			100.00	top_earlgrey

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Toggle Coverage for Module : i2c

	Total	Covered	Percent
Totals	54	40	74.07
Total Bits	352	298	84.66
Total Bits 0->1	176	149	84.66
Total Bits 1->0	176	149	84.66

Ports	54	40	74.07
Port Bits	352	298	84.66
Port Bits 0->1	176	149	84.66
Port Bits 1->0	176	149	84.66

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T4,T5,T6	Yes	T1,T2,T3	INPUT
ram_cfg_i.rf_cfg.cfg[3:0]	No	No		No		INPUT
ram_cfg_i.rf_cfg.cfg_en	No	No		No		INPUT
ram_cfg_i.rf_cfg.test	No	No		No		INPUT
ram_cfg_i.ram_cfg.cfg[3:0]	No	No		No		INPUT
ram_cfg_i.ram_cfg.cfg_en	No	No		No		INPUT
ram_cfg_i.ram_cfg.test	No	No		No		INPUT
tl_i.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.data_intg[6:0]	Yes	Yes	T218,T219,T27	Yes	T218,T219,T27	INPUT
tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.instr_type[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.instr_type[2:1]	No	No		No		INPUT
tl_i.a_user.instr_type[3]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_data[31:0]	Yes	Yes	T218,T219,T27	Yes	T218,T219,T27	INPUT
tl_i.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[1:0]	No	No		No		INPUT
tl_i.a_address[6:2]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[15:7]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[17:16]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[18]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[19]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[29:20]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[30]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[31]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_source[5:0]	Yes	Yes	*T15,*T9,*T14	Yes	T15,T9,T14	INPUT
tl_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_size[1:0]	Yes	Yes	T44,T45,T46	Yes	T44,T45,T46	INPUT
tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_opcode[0]	Yes	Yes	*T14,*T89,*T90	Yes	T14,T89,T90	INPUT
tl_i.a_opcode[1]	No	No		No		INPUT
tl_i.a_opcode[2]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_valid	Yes	Yes	T218,T219,T27	Yes	T218,T219,T27	INPUT
tl_o.a_ready	Yes	Yes	T218,T219,T27	Yes	T218,T219,T27	OUTPUT
tl_o.d_error	No	No		No		OUTPUT
tl_o.d_user.data_intg[6:0]	Yes	Yes	T218,T219,T27	Yes	T218,T219,T27	OUTPUT
tl_o.d_user.rsp_intg[1:0]	Yes	Yes	T218,T219,T27	Yes	T218,T219,T27	OUTPUT
tl_o.d_user.rsp_intg[3:2]	No	No		No		OUTPUT
tl_o.d_user.rsp_intg[5:4]	Yes	Yes	T140,*T190,T141	Yes	T218,T219,T27	OUTPUT
tl_o.d_user.rsp_intg[6]	No	No		No		OUTPUT
tl_o.d_data[31:0]	Yes	Yes	T218,T219,T27	Yes	T218,T219,T27	OUTPUT
tl_o.d_sink	No	No		No		OUTPUT
tl_o.d_source[1:0]	Yes	Yes	*T90,*T218,*T219	Yes	T90,T218,T219	OUTPUT
tl_o.d_source[5:2]	No	No		No		OUTPUT
tl_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_size[0]	No	No		No		OUTPUT
tl_o.d_size[1]	Yes	Yes	T140,T190,T141	Yes	T218,T219,T27	OUTPUT
tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_opcode[0]	Yes	Yes	*T218,*T219,*T27	Yes	T218,T219,T27	OUTPUT
tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_valid	Yes	Yes	T218,T219,T27	Yes	T218,T219,T27	OUTPUT
alert_rx_i[0].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T18,T142,T220	Yes	T18,T142,T220	INPUT
alert_rx_i[0].ping_n	Yes	Yes	T18,T142,T221	Yes	T18,T142,T221	INPUT
alert_rx_i[0].ping_p	Yes	Yes	T18,T142,T221	Yes	T18,T142,T221	INPUT
alert_tx_o[0].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T18,T142,T220	Yes	T18,T142,T220	OUTPUT
cio_scl_i	Yes	Yes	T218,T219,T27	Yes	T218,T219,T27	INPUT
cio_scl_o	Unreachable	Unreachable		Unreachable		OUTPUT
cio_scl_en_o	Yes	Yes	T219,T27,T28	Yes	T219,T27,T28	OUTPUT
cio_sda_i	Yes	Yes	T218,T219,T27	Yes	T218,T219,T27	INPUT
cio_sda_o	Unreachable	Unreachable		Unreachable		OUTPUT
cio_sda_en_o	Yes	Yes	T218,T219,T27	Yes	T218,T219,T27	OUTPUT
intr_fmt_threshold_o	Yes	Yes	T219,T222,T223	Yes	T219,T222,T223	OUTPUT
intr_rx_threshold_o	Yes	Yes	T219,T222,T223	Yes	T219,T222,T223	OUTPUT
intr_acq_threshold_o	Yes	Yes	T215,T216,T217	Yes	T215,T216,T217	OUTPUT
intr_rx_overflow_o	Yes	Yes	T215,T216,T217	Yes	T215,T216,T217	OUTPUT
intr_controller_halt_o	Yes	Yes	T215,T216,T217	Yes	T215,T216,T217	OUTPUT
intr_scl_interference_o	Yes	Yes	T215,T216,T217	Yes	T215,T216,T217	OUTPUT
intr_sda_interference_o	Yes	Yes	T215,T216,T217	Yes	T215,T216,T217	OUTPUT
intr_stretch_timeout_o	Yes	Yes	T215,T216,T217	Yes	T215,T216,T217	OUTPUT
intr_sda_unstable_o	Yes	Yes	T215,T216,T217	Yes	T215,T216,T217	OUTPUT
intr_cmd_complete_o	Yes	Yes	T218,T219,T222	Yes	T218,T219,T222	OUTPUT
intr_tx_stretch_o	Yes	Yes	T215,T216,T217	Yes	T215,T216,T217	OUTPUT
intr_tx_threshold_o	Yes	Yes	T90,T215,T216	Yes	T90,T215,T216	OUTPUT
intr_acq_stretch_o	Yes	Yes	T215,T216,T217	Yes	T215,T216,T217	OUTPUT
intr_unexp_stop_o	Yes	Yes	T215,T216,T217	Yes	T215,T216,T217	OUTPUT
intr_host_timeout_o	Yes	Yes	T215,T216,T217	Yes	T215,T216,T217	OUTPUT

*Tests covering at least one bit in the range

Toggle Coverage for Instance : tb.dut.top_earlgrey.u_i2c0

	Total	Covered	Percent
Totals	54	40	74.07
Total Bits	348	294	84.48
Total Bits 0->1	174	147	84.48
Total Bits 1->0	174	147	84.48

Ports	54	40	74.07
Port Bits	348	294	84.48
Port Bits 0->1	174	147	84.48
Port Bits 1->0	174	147	84.48

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T4,T5,T6	Yes	T1,T2,T3	INPUT
ram_cfg_i.rf_cfg.cfg[3:0]	No	No		No		INPUT
ram_cfg_i.rf_cfg.cfg_en	No	No		No		INPUT
ram_cfg_i.rf_cfg.test	No	No		No		INPUT
ram_cfg_i.ram_cfg.cfg[3:0]	No	No		No		INPUT
ram_cfg_i.ram_cfg.cfg_en	No	No		No		INPUT
ram_cfg_i.ram_cfg.test	No	No		No		INPUT
tl_i.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.data_intg[6:0]	Yes	Yes	T218,T27,T140	Yes	T218,T27,T140	INPUT
tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.instr_type[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.instr_type[2:1]	No	No		No		INPUT
tl_i.a_user.instr_type[3]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_data[31:0]	Yes	Yes	T218,T27,T140	Yes	T218,T27,T140	INPUT
tl_i.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[1:0]	No	No		No		INPUT
tl_i.a_address[6:2]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[18:7]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[19]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[29:20]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[30]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[31]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_source[5:0]	Yes	Yes	*T15,*T9,*T14	Yes	T15,T9,T14	INPUT
tl_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_size[1:0]	Yes	Yes	T44,T45,T46	Yes	T44,T45,T46	INPUT
tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_opcode[0]	Yes	Yes	*T14,*T89,*T90	Yes	T14,T89,T90	INPUT
tl_i.a_opcode[1]	No	No		No		INPUT
tl_i.a_opcode[2]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_valid	Yes	Yes	T218,T27,T140	Yes	T218,T27,T140	INPUT
tl_o.a_ready	Yes	Yes	T218,T27,T140	Yes	T218,T27,T140	OUTPUT
tl_o.d_error	No	No		No		OUTPUT
tl_o.d_user.data_intg[6:0]	Yes	Yes	T218,T27,T28	Yes	T218,T27,T28	OUTPUT
tl_o.d_user.rsp_intg[1:0]	Yes	Yes	T218,T27,T140	Yes	T218,T27,T140	OUTPUT
tl_o.d_user.rsp_intg[3:2]	No	No		No		OUTPUT
tl_o.d_user.rsp_intg[5:4]	Yes	Yes	T140,*T190,T141	Yes	T218,T27,T140	OUTPUT
tl_o.d_user.rsp_intg[6]	No	No		No		OUTPUT
tl_o.d_data[31:0]	Yes	Yes	T218,T27,T140	Yes	T218,T27,T140	OUTPUT
tl_o.d_sink	No	No		No		OUTPUT
tl_o.d_source[1:0]	Yes	Yes	*T90,*T218,*T27	Yes	T90,T218,T27	OUTPUT
tl_o.d_source[5:2]	No	No		No		OUTPUT
tl_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_size[0]	No	No		No		OUTPUT
tl_o.d_size[1]	Yes	Yes	T140,T190,T141	Yes	T218,T27,T140	OUTPUT
tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_opcode[0]	Yes	Yes	*T218,*T27,*T140	Yes	T218,T27,T140	OUTPUT
tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_valid	Yes	Yes	T218,T27,T140	Yes	T218,T27,T140	OUTPUT
alert_rx_i[0].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T18,T142,T190	Yes	T18,T142,T190	INPUT
alert_rx_i[0].ping_n	Yes	Yes	T18,T142,T221	Yes	T18,T142,T221	INPUT
alert_rx_i[0].ping_p	Yes	Yes	T18,T142,T221	Yes	T18,T142,T221	INPUT
alert_tx_o[0].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T18,T142,T190	Yes	T18,T142,T190	OUTPUT
cio_scl_i	Yes	Yes	T218,T27,T28	Yes	T218,T27,T28	INPUT
cio_scl_o	Unreachable	Unreachable		Unreachable		OUTPUT
cio_scl_en_o	Yes	Yes	T27,T28,T57	Yes	T27,T28,T57	OUTPUT
cio_sda_i	Yes	Yes	T218,T27,T28	Yes	T218,T27,T28	INPUT
cio_sda_o	Unreachable	Unreachable		Unreachable		OUTPUT
cio_sda_en_o	Yes	Yes	T218,T27,T28	Yes	T218,T27,T28	OUTPUT
intr_fmt_threshold_o	Yes	Yes	T90,T224,T215	Yes	T90,T224,T215	OUTPUT
intr_rx_threshold_o	Yes	Yes	T224,T215,T225	Yes	T224,T215,T225	OUTPUT
intr_acq_threshold_o	Yes	Yes	T215,T216,T217	Yes	T215,T216,T217	OUTPUT
intr_rx_overflow_o	Yes	Yes	T215,T216,T217	Yes	T215,T216,T217	OUTPUT
intr_controller_halt_o	Yes	Yes	T215,T216,T217	Yes	T215,T216,T217	OUTPUT
intr_scl_interference_o	Yes	Yes	T215,T216,T217	Yes	T215,T216,T217	OUTPUT
intr_sda_interference_o	Yes	Yes	T215,T216,T217	Yes	T215,T216,T217	OUTPUT
intr_stretch_timeout_o	Yes	Yes	T215,T216,T217	Yes	T215,T216,T217	OUTPUT
intr_sda_unstable_o	Yes	Yes	T215,T216,T217	Yes	T215,T216,T217	OUTPUT
intr_cmd_complete_o	Yes	Yes	T218,T224,T215	Yes	T218,T224,T215	OUTPUT
intr_tx_stretch_o	Yes	Yes	T215,T216,T217	Yes	T215,T216,T217	OUTPUT
intr_tx_threshold_o	Yes	Yes	T215,T216,T217	Yes	T215,T216,T217	OUTPUT
intr_acq_stretch_o	Yes	Yes	T215,T216,T217	Yes	T215,T216,T217	OUTPUT
intr_unexp_stop_o	Yes	Yes	T215,T216,T217	Yes	T215,T216,T217	OUTPUT
intr_host_timeout_o	Yes	Yes	T215,T216,T217	Yes	T215,T216,T217	OUTPUT

*Tests covering at least one bit in the range

Toggle Coverage for Instance : tb.dut.top_earlgrey.u_i2c1

	Total	Covered	Percent
Totals	54	40	74.07
Total Bits	350	296	84.57
Total Bits 0->1	175	148	84.57
Total Bits 1->0	175	148	84.57

Ports	54	40	74.07
Port Bits	350	296	84.57
Port Bits 0->1	175	148	84.57
Port Bits 1->0	175	148	84.57

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T4,T5,T6	Yes	T1,T2,T3	INPUT
ram_cfg_i.rf_cfg.cfg[3:0]	No	No		No		INPUT
ram_cfg_i.rf_cfg.cfg_en	No	No		No		INPUT
ram_cfg_i.rf_cfg.test	No	No		No		INPUT
ram_cfg_i.ram_cfg.cfg[3:0]	No	No		No		INPUT
ram_cfg_i.ram_cfg.cfg_en	No	No		No		INPUT
ram_cfg_i.ram_cfg.test	No	No		No		INPUT
tl_i.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.data_intg[6:0]	Yes	Yes	T27,T140,T28	Yes	T27,T140,T28	INPUT
tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.instr_type[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.instr_type[2:1]	No	No		No		INPUT
tl_i.a_user.instr_type[3]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_data[31:0]	Yes	Yes	T27,T140,T28	Yes	T27,T140,T28	INPUT
tl_i.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[1:0]	No	No		No		INPUT
tl_i.a_address[6:2]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[15:7]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[16]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[18:17]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[19]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[29:20]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[30]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[31]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_source[5:0]	Yes	Yes	*T15,*T9,*T14	Yes	T15,T9,T14	INPUT
tl_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_size[1:0]	Yes	Yes	T44,T45,T46	Yes	T44,T45,T46	INPUT
tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_opcode[0]	Yes	Yes	*T14,*T89,*T90	Yes	T14,T89,T90	INPUT
tl_i.a_opcode[1]	No	No		No		INPUT
tl_i.a_opcode[2]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_valid	Yes	Yes	T27,T140,T28	Yes	T27,T140,T28	INPUT
tl_o.a_ready	Yes	Yes	T27,T140,T28	Yes	T27,T140,T28	OUTPUT
tl_o.d_error	No	No		No		OUTPUT
tl_o.d_user.data_intg[6:0]	Yes	Yes	T27,T28,T57	Yes	T27,T28,T57	OUTPUT
tl_o.d_user.rsp_intg[1:0]	Yes	Yes	T27,T140,T28	Yes	T27,T140,T28	OUTPUT
tl_o.d_user.rsp_intg[3:2]	No	No		No		OUTPUT
tl_o.d_user.rsp_intg[5:4]	Yes	Yes	T140,*T190,T141	Yes	T27,T140,T28	OUTPUT
tl_o.d_user.rsp_intg[6]	No	No		No		OUTPUT
tl_o.d_data[31:0]	Yes	Yes	T27,T140,T28	Yes	T27,T140,T28	OUTPUT
tl_o.d_sink	No	No		No		OUTPUT
tl_o.d_source[1:0]	Yes	Yes	*T90,*T27,*T140	Yes	T90,T27,T140	OUTPUT
tl_o.d_source[5:2]	No	No		No		OUTPUT
tl_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_size[0]	No	No		No		OUTPUT
tl_o.d_size[1]	Yes	Yes	T140,T190,T141	Yes	T27,T140,T28	OUTPUT
tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_opcode[0]	Yes	Yes	*T27,*T140,*T28	Yes	T27,T140,T28	OUTPUT
tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_valid	Yes	Yes	T27,T140,T28	Yes	T27,T140,T28	OUTPUT
alert_rx_i[0].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T18,T142,T226	Yes	T18,T142,T226	INPUT
alert_rx_i[0].ping_n	Yes	Yes	T18,T142,T221	Yes	T18,T142,T221	INPUT
alert_rx_i[0].ping_p	Yes	Yes	T18,T142,T221	Yes	T18,T142,T221	INPUT
alert_tx_o[0].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T18,T142,T226	Yes	T18,T142,T226	OUTPUT
cio_scl_i	Yes	Yes	T27,T28,T57	Yes	T27,T28,T57	INPUT
cio_scl_o	Unreachable	Unreachable		Unreachable		OUTPUT
cio_scl_en_o	Yes	Yes	T27,T28,T57	Yes	T27,T28,T57	OUTPUT
cio_sda_i	Yes	Yes	T27,T28,T57	Yes	T27,T28,T57	INPUT
cio_sda_o	Unreachable	Unreachable		Unreachable		OUTPUT
cio_sda_en_o	Yes	Yes	T27,T28,T57	Yes	T27,T28,T57	OUTPUT
intr_fmt_threshold_o	Yes	Yes	T227,T90,T215	Yes	T227,T90,T215	OUTPUT
intr_rx_threshold_o	Yes	Yes	T227,T215,T228	Yes	T227,T215,T228	OUTPUT
intr_acq_threshold_o	Yes	Yes	T215,T216,T217	Yes	T215,T216,T217	OUTPUT
intr_rx_overflow_o	Yes	Yes	T215,T216,T217	Yes	T215,T216,T217	OUTPUT
intr_controller_halt_o	Yes	Yes	T215,T216,T217	Yes	T215,T216,T217	OUTPUT
intr_scl_interference_o	Yes	Yes	T215,T216,T217	Yes	T215,T216,T217	OUTPUT
intr_sda_interference_o	Yes	Yes	T215,T216,T217	Yes	T215,T216,T217	OUTPUT
intr_stretch_timeout_o	Yes	Yes	T215,T216,T217	Yes	T215,T216,T217	OUTPUT
intr_sda_unstable_o	Yes	Yes	T215,T216,T217	Yes	T215,T216,T217	OUTPUT
intr_cmd_complete_o	Yes	Yes	T227,T215,T228	Yes	T227,T215,T228	OUTPUT
intr_tx_stretch_o	Yes	Yes	T215,T216,T217	Yes	T215,T216,T217	OUTPUT
intr_tx_threshold_o	Yes	Yes	T215,T216,T217	Yes	T215,T216,T217	OUTPUT
intr_acq_stretch_o	Yes	Yes	T215,T216,T217	Yes	T215,T216,T217	OUTPUT
intr_unexp_stop_o	Yes	Yes	T215,T216,T217	Yes	T215,T216,T217	OUTPUT
intr_host_timeout_o	Yes	Yes	T215,T216,T217	Yes	T215,T216,T217	OUTPUT

*Tests covering at least one bit in the range

Toggle Coverage for Instance : tb.dut.top_earlgrey.u_i2c2

	Total	Covered	Percent
Totals	54	40	74.07
Total Bits	350	296	84.57
Total Bits 0->1	175	148	84.57
Total Bits 1->0	175	148	84.57

Ports	54	40	74.07
Port Bits	350	296	84.57
Port Bits 0->1	175	148	84.57
Port Bits 1->0	175	148	84.57

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T4,T5,T6	Yes	T1,T2,T3	INPUT
ram_cfg_i.rf_cfg.cfg[3:0]	No	No		No		INPUT
ram_cfg_i.rf_cfg.cfg_en	No	No		No		INPUT
ram_cfg_i.rf_cfg.test	No	No		No		INPUT
ram_cfg_i.ram_cfg.cfg[3:0]	No	No		No		INPUT
ram_cfg_i.ram_cfg.cfg_en	No	No		No		INPUT
ram_cfg_i.ram_cfg.test	No	No		No		INPUT
tl_i.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.data_intg[6:0]	Yes	Yes	T219,T27,T140	Yes	T219,T27,T140	INPUT
tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.instr_type[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.instr_type[2:1]	No	No		No		INPUT
tl_i.a_user.instr_type[3]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_data[31:0]	Yes	Yes	T219,T27,T140	Yes	T219,T27,T140	INPUT
tl_i.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[1:0]	No	No		No		INPUT
tl_i.a_address[6:2]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[16:7]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[17]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[18]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[19]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[29:20]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[30]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[31]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_source[5:0]	Yes	Yes	*T15,*T9,*T14	Yes	T15,T9,T14	INPUT
tl_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_size[1:0]	Yes	Yes	T44,T45,T46	Yes	T44,T45,T46	INPUT
tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_opcode[0]	Yes	Yes	*T14,*T89,*T90	Yes	T14,T89,T90	INPUT
tl_i.a_opcode[1]	No	No		No		INPUT
tl_i.a_opcode[2]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_valid	Yes	Yes	T219,T27,T140	Yes	T219,T27,T140	INPUT
tl_o.a_ready	Yes	Yes	T219,T27,T140	Yes	T219,T27,T140	OUTPUT
tl_o.d_error	No	No		No		OUTPUT
tl_o.d_user.data_intg[6:0]	Yes	Yes	T219,T27,T28	Yes	T219,T27,T28	OUTPUT
tl_o.d_user.rsp_intg[1:0]	Yes	Yes	T219,T27,T140	Yes	T219,T27,T140	OUTPUT
tl_o.d_user.rsp_intg[3:2]	No	No		No		OUTPUT
tl_o.d_user.rsp_intg[5:4]	Yes	Yes	T140,*T190,T141	Yes	T219,T27,T140	OUTPUT
tl_o.d_user.rsp_intg[6]	No	No		No		OUTPUT
tl_o.d_data[31:0]	Yes	Yes	T219,T27,T140	Yes	T219,T27,T140	OUTPUT
tl_o.d_sink	No	No		No		OUTPUT
tl_o.d_source[1:0]	Yes	Yes	*T90,*T219,*T27	Yes	T90,T219,T27	OUTPUT
tl_o.d_source[5:2]	No	No		No		OUTPUT
tl_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_size[0]	No	No		No		OUTPUT
tl_o.d_size[1]	Yes	Yes	T140,T190,T141	Yes	T219,T27,T140	OUTPUT
tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_opcode[0]	Yes	Yes	*T219,*T27,*T140	Yes	T219,T27,T140	OUTPUT
tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_valid	Yes	Yes	T219,T27,T140	Yes	T219,T27,T140	OUTPUT
alert_rx_i[0].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T18,T142,T220	Yes	T18,T142,T220	INPUT
alert_rx_i[0].ping_n	Yes	Yes	T18,T142,T20	Yes	T18,T142,T20	INPUT
alert_rx_i[0].ping_p	Yes	Yes	T18,T142,T20	Yes	T18,T142,T20	INPUT
alert_tx_o[0].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T18,T142,T220	Yes	T18,T142,T220	OUTPUT
cio_scl_i	Yes	Yes	T219,T27,T28	Yes	T219,T27,T28	INPUT
cio_scl_o	Unreachable	Unreachable		Unreachable		OUTPUT
cio_scl_en_o	Yes	Yes	T219,T27,T28	Yes	T219,T27,T28	OUTPUT
cio_sda_i	Yes	Yes	T219,T27,T28	Yes	T219,T27,T28	INPUT
cio_sda_o	Unreachable	Unreachable		Unreachable		OUTPUT
cio_sda_en_o	Yes	Yes	T219,T27,T28	Yes	T219,T27,T28	OUTPUT
intr_fmt_threshold_o	Yes	Yes	T219,T222,T223	Yes	T219,T222,T223	OUTPUT
intr_rx_threshold_o	Yes	Yes	T219,T222,T223	Yes	T219,T222,T223	OUTPUT
intr_acq_threshold_o	Yes	Yes	T215,T216,T217	Yes	T215,T216,T217	OUTPUT
intr_rx_overflow_o	Yes	Yes	T215,T216,T217	Yes	T215,T216,T217	OUTPUT
intr_controller_halt_o	Yes	Yes	T215,T216,T217	Yes	T215,T216,T217	OUTPUT
intr_scl_interference_o	Yes	Yes	T215,T216,T217	Yes	T215,T216,T217	OUTPUT
intr_sda_interference_o	Yes	Yes	T215,T216,T217	Yes	T215,T216,T217	OUTPUT
intr_stretch_timeout_o	Yes	Yes	T215,T216,T217	Yes	T215,T216,T217	OUTPUT
intr_sda_unstable_o	Yes	Yes	T215,T216,T217	Yes	T215,T216,T217	OUTPUT
intr_cmd_complete_o	Yes	Yes	T219,T222,T223	Yes	T219,T222,T223	OUTPUT
intr_tx_stretch_o	Yes	Yes	T215,T216,T217	Yes	T215,T216,T217	OUTPUT
intr_tx_threshold_o	Yes	Yes	T90,T215,T216	Yes	T90,T215,T216	OUTPUT
intr_acq_stretch_o	Yes	Yes	T215,T216,T217	Yes	T215,T216,T217	OUTPUT
intr_unexp_stop_o	Yes	Yes	T215,T216,T217	Yes	T215,T216,T217	OUTPUT
intr_host_timeout_o	Yes	Yes	T215,T216,T217	Yes	T215,T216,T217	OUTPUT

*Tests covering at least one bit in the range