Unified Coverage Report :: Module :: uart

Module : uart

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.26			90.26

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_uart_0.1/rtl/uart.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.top_earlgrey.u_uart1	89.54			89.54
tb.dut.top_earlgrey.u_uart2	89.54			89.54
tb.dut.top_earlgrey.u_uart3	89.61			89.61
tb.dut.top_earlgrey.u_uart0	90.13			90.13

---

Module Instance : tb.dut.top_earlgrey.u_uart1

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
89.54			89.54

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
89.54			89.54

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
93.16	92.47		87.00			100.00	top_earlgrey

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.top_earlgrey.u_uart2

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
89.54			89.54

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
89.54			89.54

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
93.16	92.47		87.00			100.00	top_earlgrey

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.top_earlgrey.u_uart3

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
89.61			89.61

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
89.61			89.61

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
93.16	92.47		87.00			100.00	top_earlgrey

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.top_earlgrey.u_uart0

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.13			90.13

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.13			90.13

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
93.16	92.47		87.00			100.00	top_earlgrey

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Toggle Coverage for Module : uart

	Total	Covered	Percent
Totals	40	32	80.00
Total Bits	308	278	90.26
Total Bits 0->1	154	139	90.26
Total Bits 1->0	154	139	90.26

Ports	40	32	80.00
Port Bits	308	278	90.26
Port Bits 0->1	154	139	90.26
Port Bits 1->0	154	139	90.26

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T4,T5,T6	Yes	T1,T2,T3	INPUT
tl_i.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.data_intg[6:0]	Yes	Yes	T3,T59,T5	Yes	T3,T59,T5	INPUT
tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.instr_type[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.instr_type[2:1]	No	No		No		INPUT
tl_i.a_user.instr_type[3]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_data[31:0]	Yes	Yes	T3,T59,T5	Yes	T3,T59,T5	INPUT
tl_i.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[1:0]	No	No		No		INPUT
tl_i.a_address[5:2]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[15:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[17:16]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[29:18]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[30]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[31]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_source[5:0]	Yes	Yes	*T15,*T9,*T14	Yes	T15,T9,T14	INPUT
tl_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_size[1:0]	Yes	Yes	T44,T45,T46	Yes	T44,T45,T46	INPUT
tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_opcode[0]	Yes	Yes	*T14,*T89,*T90	Yes	T14,T89,T90	INPUT
tl_i.a_opcode[1]	No	No		No		INPUT
tl_i.a_opcode[2]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_valid	Yes	Yes	T3,T59,T5	Yes	T3,T59,T5	INPUT
tl_o.a_ready	Yes	Yes	T3,T59,T5	Yes	T3,T59,T5	OUTPUT
tl_o.d_error	No	No		No		OUTPUT
tl_o.d_user.data_intg[6:0]	Yes	Yes	T3,T59,T5	Yes	T3,T59,T5	OUTPUT
tl_o.d_user.rsp_intg[1:0]	Yes	Yes	T3,T59,T5	Yes	T3,T59,T5	OUTPUT
tl_o.d_user.rsp_intg[3:2]	No	No		No		OUTPUT
tl_o.d_user.rsp_intg[5:4]	Yes	Yes	T5,T7,T58	Yes	T3,T59,T5	OUTPUT
tl_o.d_user.rsp_intg[6]	No	No		No		OUTPUT
tl_o.d_data[31:0]	Yes	Yes	T3,T59,T5	Yes	T3,T59,T5	OUTPUT
tl_o.d_sink	No	No		No		OUTPUT
tl_o.d_source[1:0]	Yes	Yes	T15,*T17,*T3	Yes	T15,T17,T3	OUTPUT
tl_o.d_source[5:2]	No	No		No		OUTPUT
tl_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_size[0]	No	No		No		OUTPUT
tl_o.d_size[1]	Yes	Yes	T5,T7,T58	Yes	T3,T59,T5	OUTPUT
tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_opcode[0]	Yes	Yes	*T3,*T59,*T5	Yes	T3,T59,T5	OUTPUT
tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_valid	Yes	Yes	T3,T59,T5	Yes	T3,T59,T5	OUTPUT
alert_rx_i[0].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T104,T302,T18	Yes	T104,T302,T18	INPUT
alert_rx_i[0].ping_n	Yes	Yes	T18,T343,T20	Yes	T18,T20,T21	INPUT
alert_rx_i[0].ping_p	Yes	Yes	T18,T20,T21	Yes	T18,T343,T20	INPUT
alert_tx_o[0].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T104,T302,T18	Yes	T104,T302,T18	OUTPUT
cio_rx_i	Yes	Yes	T3,T4,T5	Yes	T1,T2,T3	INPUT
cio_tx_o	Yes	Yes	T3,T59,T5	Yes	T3,T59,T5	OUTPUT
cio_tx_en_o	Unreachable	Unreachable		Unreachable		OUTPUT
intr_tx_watermark_o	Yes	Yes	T3,T93,T311	Yes	T3,T93,T311	OUTPUT
intr_tx_empty_o	Yes	Yes	T3,T93,T311	Yes	T3,T93,T311	OUTPUT
intr_rx_watermark_o	Yes	Yes	T3,T93,T311	Yes	T3,T93,T311	OUTPUT
intr_tx_done_o	Yes	Yes	T3,T93,T311	Yes	T3,T93,T311	OUTPUT
intr_rx_overflow_o	Yes	Yes	T3,T93,T311	Yes	T3,T93,T311	OUTPUT
intr_rx_frame_err_o	Yes	Yes	T180,T181,T182	Yes	T180,T181,T182	OUTPUT
intr_rx_break_err_o	Yes	Yes	T180,T181,T182	Yes	T180,T181,T182	OUTPUT
intr_rx_timeout_o	Yes	Yes	T180,T181,T182	Yes	T180,T181,T182	OUTPUT
intr_rx_parity_err_o	Yes	Yes	T180,T181,T182	Yes	T180,T181,T182	OUTPUT

*Tests covering at least one bit in the range

Toggle Coverage for Instance : tb.dut.top_earlgrey.u_uart1

	Total	Covered	Percent
Totals	40	32	80.00
Total Bits	306	274	89.54
Total Bits 0->1	153	137	89.54
Total Bits 1->0	153	137	89.54

Ports	40	32	80.00
Port Bits	306	274	89.54
Port Bits 0->1	153	137	89.54
Port Bits 1->0	153	137	89.54

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T4,T5,T6	Yes	T1,T2,T3	INPUT
tl_i.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.data_intg[6:0]	Yes	Yes	T3,T93,T311	Yes	T3,T93,T311	INPUT
tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.instr_type[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.instr_type[2:1]	No	No		No		INPUT
tl_i.a_user.instr_type[3]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_data[31:0]	Yes	Yes	T3,T93,T311	Yes	T3,T93,T311	INPUT
tl_i.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[1:0]	No	No		No		INPUT
tl_i.a_address[5:2]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[15:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[16]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[29:17]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[30]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[31]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_source[5:0]	Yes	Yes	*T15,*T9,*T14	Yes	T15,T9,T14	INPUT
tl_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_size[1:0]	Yes	Yes	T44,T45,T46	Yes	T44,T45,T46	INPUT
tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_opcode[0]	Yes	Yes	*T14,*T89,*T90	Yes	T14,T89,T90	INPUT
tl_i.a_opcode[1]	No	No		No		INPUT
tl_i.a_opcode[2]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_valid	Yes	Yes	T3,T93,T311	Yes	T3,T93,T311	INPUT
tl_o.a_ready	Yes	Yes	T3,T93,T311	Yes	T3,T93,T311	OUTPUT
tl_o.d_error	No	No		No		OUTPUT
tl_o.d_user.data_intg[6:0]	Yes	Yes	T3,T93,T311	Yes	T3,T93,T311	OUTPUT
tl_o.d_user.rsp_intg[1:0]	Yes	Yes	T3,T93,T311	Yes	T3,T93,T311	OUTPUT
tl_o.d_user.rsp_intg[3:2]	No	No		No		OUTPUT
tl_o.d_user.rsp_intg[5:4]	Yes	Yes	*T190,*T335,*T336	Yes	T3,T93,T311	OUTPUT
tl_o.d_user.rsp_intg[6]	No	No		No		OUTPUT
tl_o.d_data[31:0]	Yes	Yes	T3,T93,T311	Yes	T3,T93,T311	OUTPUT
tl_o.d_sink	No	No		No		OUTPUT
tl_o.d_source[0]	No	No		No		OUTPUT
tl_o.d_source[1]	Yes	Yes	*T3,*T93,*T311	Yes	T3,T93,T311	OUTPUT
tl_o.d_source[5:2]	No	No		No		OUTPUT
tl_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_size[0]	No	No		No		OUTPUT
tl_o.d_size[1]	Yes	Yes	T190,T335,T336	Yes	T3,T93,T311	OUTPUT
tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_opcode[0]	Yes	Yes	*T3,*T93,*T311	Yes	T3,T93,T311	OUTPUT
tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_valid	Yes	Yes	T3,T93,T311	Yes	T3,T93,T311	OUTPUT
alert_rx_i[0].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T104,T302,T18	Yes	T104,T302,T18	INPUT
alert_rx_i[0].ping_n	Yes	Yes	T18,T20,T21	Yes	T18,T20,T21	INPUT
alert_rx_i[0].ping_p	Yes	Yes	T18,T20,T21	Yes	T18,T20,T21	INPUT
alert_tx_o[0].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T104,T302,T18	Yes	T104,T302,T18	OUTPUT
cio_rx_i	Yes	Yes	T3,T93,T311	Yes	T3,T93,T311	INPUT
cio_tx_o	Yes	Yes	T3,T93,T311	Yes	T3,T93,T311	OUTPUT
cio_tx_en_o	Unreachable	Unreachable		Unreachable		OUTPUT
intr_tx_watermark_o	Yes	Yes	T3,T93,T311	Yes	T3,T93,T311	OUTPUT
intr_tx_empty_o	Yes	Yes	T3,T93,T311	Yes	T3,T93,T311	OUTPUT
intr_rx_watermark_o	Yes	Yes	T3,T93,T311	Yes	T3,T93,T311	OUTPUT
intr_tx_done_o	Yes	Yes	T3,T93,T311	Yes	T3,T93,T311	OUTPUT
intr_rx_overflow_o	Yes	Yes	T3,T93,T311	Yes	T3,T93,T311	OUTPUT
intr_rx_frame_err_o	Yes	Yes	T180,T181,T182	Yes	T180,T181,T182	OUTPUT
intr_rx_break_err_o	Yes	Yes	T180,T181,T182	Yes	T180,T181,T182	OUTPUT
intr_rx_timeout_o	Yes	Yes	T180,T181,T182	Yes	T180,T181,T182	OUTPUT
intr_rx_parity_err_o	Yes	Yes	T180,T181,T182	Yes	T180,T181,T182	OUTPUT

*Tests covering at least one bit in the range

Toggle Coverage for Instance : tb.dut.top_earlgrey.u_uart2

	Total	Covered	Percent
Totals	40	32	80.00
Total Bits	306	274	89.54
Total Bits 0->1	153	137	89.54
Total Bits 1->0	153	137	89.54

Ports	40	32	80.00
Port Bits	306	274	89.54
Port Bits 0->1	153	137	89.54
Port Bits 1->0	153	137	89.54

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T4,T5,T6	Yes	T1,T2,T3	INPUT
tl_i.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.data_intg[6:0]	Yes	Yes	T135,T27,T28	Yes	T135,T27,T28	INPUT
tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.instr_type[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.instr_type[2:1]	No	No		No		INPUT
tl_i.a_user.instr_type[3]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_data[31:0]	Yes	Yes	T135,T27,T28	Yes	T135,T27,T28	INPUT
tl_i.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[1:0]	No	No		No		INPUT
tl_i.a_address[5:2]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[16:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[17]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[29:18]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[30]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[31]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_source[5:0]	Yes	Yes	*T15,*T9,*T14	Yes	T15,T9,T14	INPUT
tl_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_size[1:0]	Yes	Yes	T44,T45,T46	Yes	T44,T45,T46	INPUT
tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_opcode[0]	Yes	Yes	*T14,*T89,*T90	Yes	T14,T89,T90	INPUT
tl_i.a_opcode[1]	No	No		No		INPUT
tl_i.a_opcode[2]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_valid	Yes	Yes	T135,T27,T28	Yes	T135,T27,T28	INPUT
tl_o.a_ready	Yes	Yes	T135,T27,T28	Yes	T135,T27,T28	OUTPUT
tl_o.d_error	No	No		No		OUTPUT
tl_o.d_user.data_intg[6:0]	Yes	Yes	T135,T27,T28	Yes	T135,T27,T28	OUTPUT
tl_o.d_user.rsp_intg[1:0]	Yes	Yes	T135,T27,T28	Yes	T135,T27,T28	OUTPUT
tl_o.d_user.rsp_intg[3:2]	No	No		No		OUTPUT
tl_o.d_user.rsp_intg[5:4]	Yes	Yes	*T190,*T335,*T336	Yes	T135,T27,T28	OUTPUT
tl_o.d_user.rsp_intg[6]	No	No		No		OUTPUT
tl_o.d_data[31:0]	Yes	Yes	T135,T27,T28	Yes	T135,T27,T28	OUTPUT
tl_o.d_sink	No	No		No		OUTPUT
tl_o.d_source[0]	No	No		No		OUTPUT
tl_o.d_source[1]	Yes	Yes	*T135,*T27,*T28	Yes	T135,T27,T28	OUTPUT
tl_o.d_source[5:2]	No	No		No		OUTPUT
tl_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_size[0]	No	No		No		OUTPUT
tl_o.d_size[1]	Yes	Yes	T190,T335,T336	Yes	T135,T27,T28	OUTPUT
tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_opcode[0]	Yes	Yes	*T135,*T27,*T28	Yes	T135,T27,T28	OUTPUT
tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_valid	Yes	Yes	T135,T27,T28	Yes	T135,T27,T28	OUTPUT
alert_rx_i[0].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T18,T344,T345	Yes	T18,T344,T345	INPUT
alert_rx_i[0].ping_n	Yes	Yes	T18,T20,T21	Yes	T18,T20,T21	INPUT
alert_rx_i[0].ping_p	Yes	Yes	T18,T20,T21	Yes	T18,T20,T21	INPUT
alert_tx_o[0].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T18,T344,T345	Yes	T18,T344,T345	OUTPUT
cio_rx_i	Yes	Yes	T135,T346,T245	Yes	T135,T346,T245	INPUT
cio_tx_o	Yes	Yes	T135,T346,T245	Yes	T135,T346,T245	OUTPUT
cio_tx_en_o	Unreachable	Unreachable		Unreachable		OUTPUT
intr_tx_watermark_o	Yes	Yes	T135,T180,T346	Yes	T135,T180,T346	OUTPUT
intr_tx_empty_o	Yes	Yes	T135,T180,T346	Yes	T135,T180,T346	OUTPUT
intr_rx_watermark_o	Yes	Yes	T135,T180,T346	Yes	T135,T180,T346	OUTPUT
intr_tx_done_o	Yes	Yes	T135,T180,T346	Yes	T135,T180,T346	OUTPUT
intr_rx_overflow_o	Yes	Yes	T135,T180,T346	Yes	T135,T180,T346	OUTPUT
intr_rx_frame_err_o	Yes	Yes	T180,T181,T182	Yes	T180,T181,T182	OUTPUT
intr_rx_break_err_o	Yes	Yes	T180,T181,T182	Yes	T180,T181,T182	OUTPUT
intr_rx_timeout_o	Yes	Yes	T180,T181,T182	Yes	T180,T181,T182	OUTPUT
intr_rx_parity_err_o	Yes	Yes	T180,T181,T182	Yes	T180,T181,T182	OUTPUT

*Tests covering at least one bit in the range

Toggle Coverage for Instance : tb.dut.top_earlgrey.u_uart3

	Total	Covered	Percent
Totals	40	32	80.00
Total Bits	308	276	89.61
Total Bits 0->1	154	138	89.61
Total Bits 1->0	154	138	89.61

Ports	40	32	80.00
Port Bits	308	276	89.61
Port Bits 0->1	154	138	89.61
Port Bits 1->0	154	138	89.61

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T4,T5,T6	Yes	T1,T2,T3	INPUT
tl_i.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.data_intg[6:0]	Yes	Yes	T30,T31,T27	Yes	T30,T31,T27	INPUT
tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.instr_type[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.instr_type[2:1]	No	No		No		INPUT
tl_i.a_user.instr_type[3]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_data[31:0]	Yes	Yes	T30,T31,T27	Yes	T30,T31,T27	INPUT
tl_i.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[1:0]	No	No		No		INPUT
tl_i.a_address[5:2]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[15:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[17:16]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[29:18]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[30]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[31]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_source[5:0]	Yes	Yes	*T15,*T9,*T14	Yes	T15,T9,T14	INPUT
tl_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_size[1:0]	Yes	Yes	T44,T45,T46	Yes	T44,T45,T46	INPUT
tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_opcode[0]	Yes	Yes	*T14,*T89,*T90	Yes	T14,T89,T90	INPUT
tl_i.a_opcode[1]	No	No		No		INPUT
tl_i.a_opcode[2]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_valid	Yes	Yes	T30,T31,T27	Yes	T30,T31,T27	INPUT
tl_o.a_ready	Yes	Yes	T30,T31,T27	Yes	T30,T31,T27	OUTPUT
tl_o.d_error	No	No		No		OUTPUT
tl_o.d_user.data_intg[6:0]	Yes	Yes	T30,T31,T27	Yes	T30,T31,T27	OUTPUT
tl_o.d_user.rsp_intg[1:0]	Yes	Yes	T30,T31,T27	Yes	T30,T31,T27	OUTPUT
tl_o.d_user.rsp_intg[3:2]	No	No		No		OUTPUT
tl_o.d_user.rsp_intg[5:4]	Yes	Yes	*T190,*T335,*T336	Yes	T30,T31,T27	OUTPUT
tl_o.d_user.rsp_intg[6]	No	No		No		OUTPUT
tl_o.d_data[31:0]	Yes	Yes	T30,T31,T27	Yes	T30,T31,T27	OUTPUT
tl_o.d_sink	No	No		No		OUTPUT
tl_o.d_source[0]	No	No		No		OUTPUT
tl_o.d_source[1]	Yes	Yes	*T30,*T31,*T27	Yes	T30,T31,T27	OUTPUT
tl_o.d_source[5:2]	No	No		No		OUTPUT
tl_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_size[0]	No	No		No		OUTPUT
tl_o.d_size[1]	Yes	Yes	T190,T335,T336	Yes	T30,T31,T27	OUTPUT
tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_opcode[0]	Yes	Yes	*T30,*T31,*T27	Yes	T30,T31,T27	OUTPUT
tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_valid	Yes	Yes	T30,T31,T27	Yes	T30,T31,T27	OUTPUT
alert_rx_i[0].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T18,T347,T190	Yes	T18,T347,T190	INPUT
alert_rx_i[0].ping_n	Yes	Yes	T18,T343,T20	Yes	T18,T20,T21	INPUT
alert_rx_i[0].ping_p	Yes	Yes	T18,T20,T21	Yes	T18,T343,T20	INPUT
alert_tx_o[0].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T18,T347,T190	Yes	T18,T347,T190	OUTPUT
cio_rx_i	Yes	Yes	T30,T31,T348	Yes	T30,T31,T348	INPUT
cio_tx_o	Yes	Yes	T30,T31,T348	Yes	T30,T31,T348	OUTPUT
cio_tx_en_o	Unreachable	Unreachable		Unreachable		OUTPUT
intr_tx_watermark_o	Yes	Yes	T30,T31,T348	Yes	T30,T31,T348	OUTPUT
intr_tx_empty_o	Yes	Yes	T30,T31,T348	Yes	T30,T31,T348	OUTPUT
intr_rx_watermark_o	Yes	Yes	T30,T31,T348	Yes	T30,T31,T348	OUTPUT
intr_tx_done_o	Yes	Yes	T30,T31,T348	Yes	T30,T31,T348	OUTPUT
intr_rx_overflow_o	Yes	Yes	T30,T31,T348	Yes	T30,T31,T348	OUTPUT
intr_rx_frame_err_o	Yes	Yes	T180,T181,T182	Yes	T180,T181,T182	OUTPUT
intr_rx_break_err_o	Yes	Yes	T180,T181,T182	Yes	T180,T181,T182	OUTPUT
intr_rx_timeout_o	Yes	Yes	T180,T181,T182	Yes	T180,T181,T182	OUTPUT
intr_rx_parity_err_o	Yes	Yes	T180,T181,T182	Yes	T180,T181,T182	OUTPUT

*Tests covering at least one bit in the range

Toggle Coverage for Instance : tb.dut.top_earlgrey.u_uart0

	Total	Covered	Percent
Totals	40	32	80.00
Total Bits	304	274	90.13
Total Bits 0->1	152	137	90.13
Total Bits 1->0	152	137	90.13

Ports	40	32	80.00
Port Bits	304	274	90.13
Port Bits 0->1	152	137	90.13
Port Bits 1->0	152	137	90.13

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T4,T5,T6	Yes	T1,T2,T3	INPUT
tl_i.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.data_intg[6:0]	Yes	Yes	T59,T5,T7	Yes	T59,T5,T7	INPUT
tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.instr_type[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.instr_type[2:1]	No	No		No		INPUT
tl_i.a_user.instr_type[3]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_data[31:0]	Yes	Yes	T59,T5,T7	Yes	T59,T5,T7	INPUT
tl_i.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[1:0]	No	No		No		INPUT
tl_i.a_address[5:2]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[29:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[30]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[31]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_source[5:0]	Yes	Yes	*T15,*T9,*T14	Yes	T15,T9,T14	INPUT
tl_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_size[1:0]	Yes	Yes	T44,T45,T46	Yes	T44,T45,T46	INPUT
tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_opcode[0]	Yes	Yes	*T14,*T89,*T90	Yes	T14,T89,T90	INPUT
tl_i.a_opcode[1]	No	No		No		INPUT
tl_i.a_opcode[2]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_valid	Yes	Yes	T59,T5,T7	Yes	T59,T5,T7	INPUT
tl_o.a_ready	Yes	Yes	T59,T5,T7	Yes	T59,T5,T7	OUTPUT
tl_o.d_error	No	No		No		OUTPUT
tl_o.d_user.data_intg[6:0]	Yes	Yes	T59,T5,T7	Yes	T59,T5,T7	OUTPUT
tl_o.d_user.rsp_intg[1:0]	Yes	Yes	T59,T5,T7	Yes	T59,T5,T7	OUTPUT
tl_o.d_user.rsp_intg[3:2]	No	No		No		OUTPUT
tl_o.d_user.rsp_intg[5:4]	Yes	Yes	T5,T7,T58	Yes	T59,T5,T7	OUTPUT
tl_o.d_user.rsp_intg[6]	No	No		No		OUTPUT
tl_o.d_data[31:0]	Yes	Yes	T59,T5,T7	Yes	T59,T5,T7	OUTPUT
tl_o.d_sink	No	No		No		OUTPUT
tl_o.d_source[1:0]	Yes	Yes	T15,*T17,*T59	Yes	T15,T17,T59	OUTPUT
tl_o.d_source[5:2]	No	No		No		OUTPUT
tl_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_size[0]	No	No		No		OUTPUT
tl_o.d_size[1]	Yes	Yes	T5,T7,T58	Yes	T59,T5,T7	OUTPUT
tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_opcode[0]	Yes	Yes	*T59,*T5,*T7	Yes	T59,T5,T7	OUTPUT
tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_valid	Yes	Yes	T59,T5,T7	Yes	T59,T5,T7	OUTPUT
alert_rx_i[0].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T18,T190,T20	Yes	T18,T190,T20	INPUT
alert_rx_i[0].ping_n	Yes	Yes	T18,T20,T21	Yes	T18,T20,T21	INPUT
alert_rx_i[0].ping_p	Yes	Yes	T18,T20,T21	Yes	T18,T20,T21	INPUT
alert_tx_o[0].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T18,T190,T20	Yes	T18,T190,T20	OUTPUT
cio_rx_i	Yes	Yes	T4,T5,T6	Yes	T1,T2,T3	INPUT
cio_tx_o	Yes	Yes	T59,T5,T7	Yes	T59,T5,T7	OUTPUT
cio_tx_en_o	Unreachable	Unreachable		Unreachable		OUTPUT
intr_tx_watermark_o	Yes	Yes	T153,T295,T117	Yes	T153,T295,T117	OUTPUT
intr_tx_empty_o	Yes	Yes	T295,T117,T313	Yes	T295,T117,T313	OUTPUT
intr_rx_watermark_o	Yes	Yes	T295,T117,T313	Yes	T295,T117,T313	OUTPUT
intr_tx_done_o	Yes	Yes	T295,T117,T313	Yes	T295,T117,T313	OUTPUT
intr_rx_overflow_o	Yes	Yes	T295,T117,T313	Yes	T295,T117,T313	OUTPUT
intr_rx_frame_err_o	Yes	Yes	T180,T181,T182	Yes	T180,T181,T182	OUTPUT
intr_rx_break_err_o	Yes	Yes	T180,T181,T182	Yes	T180,T181,T182	OUTPUT
intr_rx_timeout_o	Yes	Yes	T180,T181,T182	Yes	T180,T181,T182	OUTPUT
intr_rx_parity_err_o	Yes	Yes	T180,T181,T182	Yes	T180,T181,T182	OUTPUT

*Tests covering at least one bit in the range