Module Definition
dashboard | hierarchy | modlist | groups | tests | asserts

Module : xbar_main
SCORELINECONDTOGGLEFSMBRANCHASSERT
81.08 81.08

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_top_earlgrey_xbar_main_0.1/rtl/autogen/xbar_main.sv

Module self-instances :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
tb.dut.top_earlgrey.u_xbar_main 81.08 81.08


Module Instance : tb.dut.top_earlgrey.u_xbar_main

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
81.08 81.08


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
81.08 81.08


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
93.16 92.47 87.00 100.00 top_earlgrey


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children

Since this is the module's only instance, the coverage report is the same as for the module.
Toggle Coverage for Module : xbar_main
TotalCoveredPercent
Totals 550 301 54.73
Total Bits 6824 5533 81.08
Total Bits 0->1 3412 2767 81.10
Total Bits 1->0 3412 2766 81.07

Ports 550 301 54.73
Port Bits 6824 5533 81.08
Port Bits 0->1 3412 2767 81.10
Port Bits 1->0 3412 2766 81.07

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_main_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
clk_fixed_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
clk_usb_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
clk_spi_host0_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
clk_spi_host1_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_main_ni Yes Yes T4,T5,T6 Yes T1,T2,T3 INPUT
rst_fixed_ni Yes Yes T4,T5,T6 Yes T1,T2,T3 INPUT
rst_usb_ni Yes Yes T4,T5,T6 Yes T1,T2,T3 INPUT
rst_spi_host0_ni Yes Yes T4,T5,T6 Yes T1,T2,T3 INPUT
rst_spi_host1_ni Yes Yes T4,T5,T6 Yes T1,T2,T3 INPUT
tl_rv_core_ibex__corei_i.d_ready No No No INPUT
tl_rv_core_ibex__corei_i.a_user.data_intg[6:0] No No No INPUT
tl_rv_core_ibex__corei_i.a_user.cmd_intg[6:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_rv_core_ibex__corei_i.a_user.instr_type[3:0] No No No INPUT
tl_rv_core_ibex__corei_i.a_user.rsvd[4:0] Unreachable Unreachable Unreachable INPUT
tl_rv_core_ibex__corei_i.a_data[31:0] No No No INPUT
tl_rv_core_ibex__corei_i.a_mask[3:0] No No No INPUT
tl_rv_core_ibex__corei_i.a_address[31:0] Unreachable Unreachable Unreachable INPUT
tl_rv_core_ibex__corei_i.a_source[2:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_rv_core_ibex__corei_i.a_source[5:3] No No No INPUT
tl_rv_core_ibex__corei_i.a_source[7:6] Unreachable Unreachable Unreachable INPUT
tl_rv_core_ibex__corei_i.a_size[1:0] No No No INPUT
tl_rv_core_ibex__corei_i.a_param[2:0] Unreachable Unreachable Unreachable INPUT
tl_rv_core_ibex__corei_i.a_opcode[2:0] No No No INPUT
tl_rv_core_ibex__corei_i.a_valid Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_rv_core_ibex__corei_o.a_ready Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_rv_core_ibex__corei_o.d_error Yes Yes T4,T58,T15 Yes T4,T58,T15 OUTPUT
tl_rv_core_ibex__corei_o.d_user.data_intg[6:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_rv_core_ibex__corei_o.d_user.rsp_intg[5:0] Yes Yes *T4,*T58,*T15 Yes T4,T58,T15 OUTPUT
tl_rv_core_ibex__corei_o.d_user.rsp_intg[6] No No No OUTPUT
tl_rv_core_ibex__corei_o.d_data[31:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_rv_core_ibex__corei_o.d_sink No No No OUTPUT
tl_rv_core_ibex__corei_o.d_source[2:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_rv_core_ibex__corei_o.d_source[5:3] No No No OUTPUT
tl_rv_core_ibex__corei_o.d_source[7:6] Unreachable Unreachable Unreachable OUTPUT
tl_rv_core_ibex__corei_o.d_size[0] No No No OUTPUT
tl_rv_core_ibex__corei_o.d_size[1] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_rv_core_ibex__corei_o.d_param[2:0] Unreachable Unreachable Unreachable OUTPUT
tl_rv_core_ibex__corei_o.d_opcode[0] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 OUTPUT
tl_rv_core_ibex__corei_o.d_opcode[2:1] Unreachable Unreachable Unreachable OUTPUT
tl_rv_core_ibex__corei_o.d_valid Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_rv_core_ibex__cored_i.d_ready Yes Yes T14,T89,T90 Yes T14,T89,T90 INPUT
tl_rv_core_ibex__cored_i.a_user.data_intg[6:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_rv_core_ibex__cored_i.a_user.cmd_intg[6:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_rv_core_ibex__cored_i.a_user.instr_type[3:0] Yes Yes T14,T44,T46 Yes T14,T44,T46 INPUT
tl_rv_core_ibex__cored_i.a_user.rsvd[4:0] Unreachable Unreachable Unreachable INPUT
tl_rv_core_ibex__cored_i.a_data[31:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_rv_core_ibex__cored_i.a_mask[3:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_rv_core_ibex__cored_i.a_address[31:0] Unreachable Unreachable Unreachable INPUT
tl_rv_core_ibex__cored_i.a_source[5:0] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 INPUT
tl_rv_core_ibex__cored_i.a_source[7:6] Unreachable Unreachable Unreachable INPUT
tl_rv_core_ibex__cored_i.a_size[1:0] Yes Yes T14,T44,T45 Yes T14,T44,T45 INPUT
tl_rv_core_ibex__cored_i.a_param[2:0] Unreachable Unreachable Unreachable INPUT
tl_rv_core_ibex__cored_i.a_opcode[0] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 INPUT
tl_rv_core_ibex__cored_i.a_opcode[1] No No No INPUT
tl_rv_core_ibex__cored_i.a_opcode[2] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_rv_core_ibex__cored_i.a_valid Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_rv_core_ibex__cored_o.a_ready Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_rv_core_ibex__cored_o.d_error Yes Yes T4,T77,T58 Yes T4,T77,T58 OUTPUT
tl_rv_core_ibex__cored_o.d_user.data_intg[6:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_rv_core_ibex__cored_o.d_user.rsp_intg[5:0] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 OUTPUT
tl_rv_core_ibex__cored_o.d_user.rsp_intg[6] No No No OUTPUT
tl_rv_core_ibex__cored_o.d_data[31:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_rv_core_ibex__cored_o.d_sink No No No OUTPUT
tl_rv_core_ibex__cored_o.d_source[5:0] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 OUTPUT
tl_rv_core_ibex__cored_o.d_source[7:6] Unreachable Unreachable Unreachable OUTPUT
tl_rv_core_ibex__cored_o.d_size[1:0] Yes Yes T44,T45,T46 Yes T44,T45,T46 OUTPUT
tl_rv_core_ibex__cored_o.d_param[2:0] Unreachable Unreachable Unreachable OUTPUT
tl_rv_core_ibex__cored_o.d_opcode[0] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 OUTPUT
tl_rv_core_ibex__cored_o.d_opcode[2:1] Unreachable Unreachable Unreachable OUTPUT
tl_rv_core_ibex__cored_o.d_valid Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_rv_dm__sba_i.d_ready Yes Yes T4,T6,T7 Yes T1,T2,T3 INPUT
tl_rv_dm__sba_i.a_user.data_intg[6:0] Yes Yes T15,T9,T14 Yes T15,T9,T14 INPUT
tl_rv_dm__sba_i.a_user.cmd_intg[6:0] Yes Yes T4,T6,T7 Yes T1,T2,T3 INPUT
tl_rv_dm__sba_i.a_user.instr_type[0] Yes Yes *T4,*T6,*T7 Yes T1,T2,T3 INPUT
tl_rv_dm__sba_i.a_user.instr_type[2:1] No No No INPUT
tl_rv_dm__sba_i.a_user.instr_type[3] Yes Yes T4,T6,T7 Yes T1,T2,T3 INPUT
tl_rv_dm__sba_i.a_user.rsvd[4:0] Unreachable Unreachable Unreachable INPUT
tl_rv_dm__sba_i.a_data[31:0] Yes Yes T15,T9,T14 Yes T15,T9,T14 INPUT
tl_rv_dm__sba_i.a_mask[3:0] Yes Yes T4,T6,T7 Yes T1,T2,T3 INPUT
tl_rv_dm__sba_i.a_address[31:0] Unreachable Unreachable Unreachable INPUT
tl_rv_dm__sba_i.a_source[5:0] No No No INPUT
tl_rv_dm__sba_i.a_source[7:6] Unreachable Unreachable Unreachable INPUT
tl_rv_dm__sba_i.a_size[0] No No No INPUT
tl_rv_dm__sba_i.a_size[1] Yes Yes T4,T6,T7 Yes T1,T2,T3 INPUT
tl_rv_dm__sba_i.a_param[2:0] Unreachable Unreachable Unreachable INPUT
tl_rv_dm__sba_i.a_opcode[1:0] No No No INPUT
tl_rv_dm__sba_i.a_opcode[2] Yes Yes T4,T6,T7 Yes T1,T2,T3 INPUT
tl_rv_dm__sba_i.a_valid Yes Yes T15,T9,T14 Yes T15,T9,T14 INPUT
tl_rv_dm__sba_o.a_ready Yes Yes T4,T5,T6 Yes T1,T2,T3 OUTPUT
tl_rv_dm__sba_o.d_error No No No OUTPUT
tl_rv_dm__sba_o.d_user.data_intg[6:0] Yes Yes T15,T9,T14 Yes T15,T9,T14 OUTPUT
tl_rv_dm__sba_o.d_user.rsp_intg[1:0] Yes Yes T15,T14,T17 Yes T15,T14,T17 OUTPUT
tl_rv_dm__sba_o.d_user.rsp_intg[2] No No No OUTPUT
tl_rv_dm__sba_o.d_user.rsp_intg[5:3] Yes Yes T15,*T9,T14 Yes T15,T9,T14 OUTPUT
tl_rv_dm__sba_o.d_user.rsp_intg[6] No No No OUTPUT
tl_rv_dm__sba_o.d_data[31:0] Yes Yes T15,T9,T14 Yes T15,T9,T14 OUTPUT
tl_rv_dm__sba_o.d_sink No No No OUTPUT
tl_rv_dm__sba_o.d_source[5:0] No No No OUTPUT
tl_rv_dm__sba_o.d_source[7:6] Unreachable Unreachable Unreachable OUTPUT
tl_rv_dm__sba_o.d_size[0] No No No OUTPUT
tl_rv_dm__sba_o.d_size[1] Yes Yes T15,T9,T14 Yes T15,T9,T14 OUTPUT
tl_rv_dm__sba_o.d_param[2:0] Unreachable Unreachable Unreachable OUTPUT
tl_rv_dm__sba_o.d_opcode[0] Yes Yes *T15,*T9,*T14 Yes T15,T9,T14 OUTPUT
tl_rv_dm__sba_o.d_opcode[2:1] Unreachable Unreachable Unreachable OUTPUT
tl_rv_dm__sba_o.d_valid Yes Yes T15,T9,T14 Yes T15,T9,T14 OUTPUT
tl_rv_dm__regs_o.d_ready Yes Yes T4,T5,T6 Yes T1,T2,T3 OUTPUT
tl_rv_dm__regs_o.a_user.data_intg[6:0] No No No OUTPUT
tl_rv_dm__regs_o.a_user.cmd_intg[6:0] No No No OUTPUT
tl_rv_dm__regs_o.a_user.instr_type[3:0] No No No OUTPUT
tl_rv_dm__regs_o.a_user.rsvd[4:0] Unreachable Unreachable Unreachable OUTPUT
tl_rv_dm__regs_o.a_data[31:0] No No No OUTPUT
tl_rv_dm__regs_o.a_mask[3:0] No No No OUTPUT
tl_rv_dm__regs_o.a_address[31:0] Unreachable Unreachable Unreachable OUTPUT
tl_rv_dm__regs_o.a_source[5:0] No No No OUTPUT
tl_rv_dm__regs_o.a_source[7:6] Unreachable Unreachable Unreachable OUTPUT
tl_rv_dm__regs_o.a_size[1:0] No No No OUTPUT
tl_rv_dm__regs_o.a_param[2:0] Unreachable Unreachable Unreachable OUTPUT
tl_rv_dm__regs_o.a_opcode[2:0] No No No OUTPUT
tl_rv_dm__regs_o.a_valid No No No OUTPUT
tl_rv_dm__regs_i.a_ready No No No INPUT
tl_rv_dm__regs_i.d_error No No No INPUT
tl_rv_dm__regs_i.d_user.data_intg[6:0] No No No INPUT
tl_rv_dm__regs_i.d_user.rsp_intg[6:0] No No No INPUT
tl_rv_dm__regs_i.d_data[31:0] No No No INPUT
tl_rv_dm__regs_i.d_sink No No No INPUT
tl_rv_dm__regs_i.d_source[5:0] No No No INPUT
tl_rv_dm__regs_i.d_source[7:6] Unreachable Unreachable Unreachable INPUT
tl_rv_dm__regs_i.d_size[1:0] No No No INPUT
tl_rv_dm__regs_i.d_param[2:0] Unreachable Unreachable Unreachable INPUT
tl_rv_dm__regs_i.d_opcode[0] No No No INPUT
tl_rv_dm__regs_i.d_opcode[2:1] Unreachable Unreachable Unreachable INPUT
tl_rv_dm__regs_i.d_valid No No No INPUT
tl_rv_dm__mem_o.d_ready Yes Yes T4,T5,T6 Yes T1,T2,T3 OUTPUT
tl_rv_dm__mem_o.a_user.data_intg[6:0] Yes Yes T15,T9,T16 Yes T15,T9,T16 OUTPUT
tl_rv_dm__mem_o.a_user.cmd_intg[6:0] Yes Yes T15,T9,T16 Yes T15,T9,T16 OUTPUT
tl_rv_dm__mem_o.a_user.instr_type[3:0] Yes Yes T15,T9,T16 Yes T15,T9,T16 OUTPUT
tl_rv_dm__mem_o.a_user.rsvd[4:0] Unreachable Unreachable Unreachable OUTPUT
tl_rv_dm__mem_o.a_data[31:0] Yes Yes T15,T9,T16 Yes T15,T9,T16 OUTPUT
tl_rv_dm__mem_o.a_mask[3:0] Yes Yes T15,T9,T16 Yes T15,T9,T16 OUTPUT
tl_rv_dm__mem_o.a_address[31:0] Unreachable Unreachable Unreachable OUTPUT
tl_rv_dm__mem_o.a_source[4:0] Yes Yes *T15,*T9,*T16 Yes T15,T9,T16 OUTPUT
tl_rv_dm__mem_o.a_source[5] No No No OUTPUT
tl_rv_dm__mem_o.a_source[7:6] Unreachable Unreachable Unreachable OUTPUT
tl_rv_dm__mem_o.a_size[0] No No No OUTPUT
tl_rv_dm__mem_o.a_size[1] Yes Yes T15,T9,T16 Yes T15,T9,T16 OUTPUT
tl_rv_dm__mem_o.a_param[2:0] Unreachable Unreachable Unreachable OUTPUT
tl_rv_dm__mem_o.a_opcode[1:0] No No No OUTPUT
tl_rv_dm__mem_o.a_opcode[2] Yes Yes T15,T9,T16 Yes T15,T9,T16 OUTPUT
tl_rv_dm__mem_o.a_valid Yes Yes T15,T9,T16 Yes T15,T9,T16 OUTPUT
tl_rv_dm__mem_i.a_ready Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_rv_dm__mem_i.d_error Yes Yes T1,T2,T3 Yes T4,T6,T7 INPUT
tl_rv_dm__mem_i.d_user.data_intg[6:0] Yes Yes T15,T9,T16 Yes T15,T9,T16 INPUT
tl_rv_dm__mem_i.d_user.rsp_intg[2:0] Yes Yes *T15,*T9,*T16 Yes T15,T9,T16 INPUT
tl_rv_dm__mem_i.d_user.rsp_intg[3] No No No INPUT
tl_rv_dm__mem_i.d_user.rsp_intg[5:4] Yes Yes *T9,*T14,*T11 Yes T15,T9,T16 INPUT
tl_rv_dm__mem_i.d_user.rsp_intg[6] No No No INPUT
tl_rv_dm__mem_i.d_data[31:0] Yes Yes T1,T2,T3 Yes T4,T6,T7 INPUT
tl_rv_dm__mem_i.d_sink No No No INPUT
tl_rv_dm__mem_i.d_source[4:0] Yes Yes *T15,*T9,*T16 Yes T15,T9,T16 INPUT
tl_rv_dm__mem_i.d_source[5] No No No INPUT
tl_rv_dm__mem_i.d_source[7:6] Unreachable Unreachable Unreachable INPUT
tl_rv_dm__mem_i.d_size[0] No No No INPUT
tl_rv_dm__mem_i.d_size[1] Yes Yes T9,T14,T11 Yes T15,T9,T16 INPUT
tl_rv_dm__mem_i.d_param[2:0] Unreachable Unreachable Unreachable INPUT
tl_rv_dm__mem_i.d_opcode[0] Yes Yes *T1,*T2,*T3 Yes T4,T6,T7 INPUT
tl_rv_dm__mem_i.d_opcode[2:1] Unreachable Unreachable Unreachable INPUT
tl_rv_dm__mem_i.d_valid Yes Yes T15,T9,T16 Yes T15,T9,T16 INPUT
tl_rom_ctrl__rom_o.d_ready Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_rom_ctrl__rom_o.a_user.data_intg[6:0] Yes Yes T59,T5,T7 Yes T59,T5,T7 OUTPUT
tl_rom_ctrl__rom_o.a_user.cmd_intg[6:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_rom_ctrl__rom_o.a_user.instr_type[3:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_rom_ctrl__rom_o.a_user.rsvd[4:0] Unreachable Unreachable Unreachable OUTPUT
tl_rom_ctrl__rom_o.a_data[31:0] Yes Yes T59,T5,T7 Yes T59,T5,T7 OUTPUT
tl_rom_ctrl__rom_o.a_mask[3:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_rom_ctrl__rom_o.a_address[31:0] Unreachable Unreachable Unreachable OUTPUT
tl_rom_ctrl__rom_o.a_source[4:0] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 OUTPUT
tl_rom_ctrl__rom_o.a_source[5] No No No OUTPUT
tl_rom_ctrl__rom_o.a_source[7:6] Unreachable Unreachable Unreachable OUTPUT
tl_rom_ctrl__rom_o.a_size[0] No No No OUTPUT
tl_rom_ctrl__rom_o.a_size[1] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_rom_ctrl__rom_o.a_param[2:0] Unreachable Unreachable Unreachable OUTPUT
tl_rom_ctrl__rom_o.a_opcode[1:0] No No No OUTPUT
tl_rom_ctrl__rom_o.a_opcode[2] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_rom_ctrl__rom_o.a_valid Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_rom_ctrl__rom_i.a_ready Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_rom_ctrl__rom_i.d_error No No No INPUT
tl_rom_ctrl__rom_i.d_user.data_intg[6:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_rom_ctrl__rom_i.d_user.rsp_intg[1:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_rom_ctrl__rom_i.d_user.rsp_intg[3:2] No No No INPUT
tl_rom_ctrl__rom_i.d_user.rsp_intg[4] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 INPUT
tl_rom_ctrl__rom_i.d_user.rsp_intg[6:5] No No No INPUT
tl_rom_ctrl__rom_i.d_data[31:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_rom_ctrl__rom_i.d_sink No No No INPUT
tl_rom_ctrl__rom_i.d_source[4:0] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 INPUT
tl_rom_ctrl__rom_i.d_source[5] No No No INPUT
tl_rom_ctrl__rom_i.d_source[7:6] Unreachable Unreachable Unreachable INPUT
tl_rom_ctrl__rom_i.d_size[0] No No No INPUT
tl_rom_ctrl__rom_i.d_size[1] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_rom_ctrl__rom_i.d_param[2:0] Unreachable Unreachable Unreachable INPUT
tl_rom_ctrl__rom_i.d_opcode[0] No No No INPUT
tl_rom_ctrl__rom_i.d_opcode[2:1] Unreachable Unreachable Unreachable INPUT
tl_rom_ctrl__rom_i.d_valid Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_rom_ctrl__regs_o.d_ready Yes Yes T4,T5,T6 Yes T1,T2,T3 OUTPUT
tl_rom_ctrl__regs_o.a_user.data_intg[1:0] Yes Yes T64,T65,T66 Yes T64,T65,T66 OUTPUT
tl_rom_ctrl__regs_o.a_user.data_intg[2] No No No OUTPUT
tl_rom_ctrl__regs_o.a_user.data_intg[5:3] Yes Yes *T147,*T148,*T149 Yes T147,T148,T149 OUTPUT
tl_rom_ctrl__regs_o.a_user.data_intg[6] No No No OUTPUT
tl_rom_ctrl__regs_o.a_user.cmd_intg[6:0] Yes Yes T147,T148,T64 Yes T147,T148,T64 OUTPUT
tl_rom_ctrl__regs_o.a_user.instr_type[0] Yes Yes *T147,*T148,*T64 Yes T147,T148,T64 OUTPUT
tl_rom_ctrl__regs_o.a_user.instr_type[2:1] No No No OUTPUT
tl_rom_ctrl__regs_o.a_user.instr_type[3] Yes Yes T147,T148,T64 Yes T147,T148,T64 OUTPUT
tl_rom_ctrl__regs_o.a_user.rsvd[4:0] Unreachable Unreachable Unreachable OUTPUT
tl_rom_ctrl__regs_o.a_data[0] Yes Yes *T64,*T65,*T66 Yes T64,T65,T66 OUTPUT
tl_rom_ctrl__regs_o.a_data[31:1] No No No OUTPUT
tl_rom_ctrl__regs_o.a_mask[3:0] Yes Yes T147,T148,T64 Yes T147,T148,T64 OUTPUT
tl_rom_ctrl__regs_o.a_address[31:0] Unreachable Unreachable Unreachable OUTPUT
tl_rom_ctrl__regs_o.a_source[0] No No No OUTPUT
tl_rom_ctrl__regs_o.a_source[1] Yes Yes *T147,*T148,*T64 Yes T147,T148,T64 OUTPUT
tl_rom_ctrl__regs_o.a_source[5:2] No No No OUTPUT
tl_rom_ctrl__regs_o.a_source[7:6] Unreachable Unreachable Unreachable OUTPUT
tl_rom_ctrl__regs_o.a_size[0] No No No OUTPUT
tl_rom_ctrl__regs_o.a_size[1] Yes Yes T147,T148,T64 Yes T147,T148,T64 OUTPUT
tl_rom_ctrl__regs_o.a_param[2:0] Unreachable Unreachable Unreachable OUTPUT
tl_rom_ctrl__regs_o.a_opcode[1:0] No No No OUTPUT
tl_rom_ctrl__regs_o.a_opcode[2] Yes Yes T147,T148,T149 Yes T147,T148,T149 OUTPUT
tl_rom_ctrl__regs_o.a_valid Yes Yes T147,T148,T64 Yes T147,T148,T64 OUTPUT
tl_rom_ctrl__regs_i.a_ready Yes Yes T147,T148,T64 Yes T147,T148,T64 INPUT
tl_rom_ctrl__regs_i.d_error No No No INPUT
tl_rom_ctrl__regs_i.d_user.data_intg[6:0] Yes Yes T147,T149,T150 Yes T147,T149,T150 INPUT
tl_rom_ctrl__regs_i.d_user.rsp_intg[0] No No Yes T64,T65,T66 INPUT
tl_rom_ctrl__regs_i.d_user.rsp_intg[1] No Yes *T64,*T65,*T66 No INPUT
tl_rom_ctrl__regs_i.d_user.rsp_intg[3:2] No No No INPUT
tl_rom_ctrl__regs_i.d_user.rsp_intg[5:4] Yes Yes T148,T149,T151 Yes T147,T148,T64 INPUT
tl_rom_ctrl__regs_i.d_user.rsp_intg[6] No No No INPUT
tl_rom_ctrl__regs_i.d_data[31:0] Yes Yes T147,T149,T150 Yes T147,T64,T65 INPUT
tl_rom_ctrl__regs_i.d_sink No No No INPUT
tl_rom_ctrl__regs_i.d_source[0] No No No INPUT
tl_rom_ctrl__regs_i.d_source[1] Yes Yes *T147,*T148,*T149 Yes T147,T148,T64 INPUT
tl_rom_ctrl__regs_i.d_source[5:2] No No No INPUT
tl_rom_ctrl__regs_i.d_source[7:6] Unreachable Unreachable Unreachable INPUT
tl_rom_ctrl__regs_i.d_size[0] No No No INPUT
tl_rom_ctrl__regs_i.d_size[1] Yes Yes T148,T149,T151 Yes T147,T148,T64 INPUT
tl_rom_ctrl__regs_i.d_param[2:0] Unreachable Unreachable Unreachable INPUT
tl_rom_ctrl__regs_i.d_opcode[0] Yes Yes *T148,*T149,*T151 Yes T147,T148,T149 INPUT
tl_rom_ctrl__regs_i.d_opcode[2:1] Unreachable Unreachable Unreachable INPUT
tl_rom_ctrl__regs_i.d_valid Yes Yes T147,T148,T64 Yes T147,T148,T64 INPUT
tl_peri_o.d_ready Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_peri_o.a_user.data_intg[6:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_peri_o.a_user.cmd_intg[6:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_peri_o.a_user.instr_type[0] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 OUTPUT
tl_peri_o.a_user.instr_type[2:1] No No No OUTPUT
tl_peri_o.a_user.instr_type[3] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_peri_o.a_user.rsvd[4:0] Unreachable Unreachable Unreachable OUTPUT
tl_peri_o.a_data[31:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_peri_o.a_mask[3:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_peri_o.a_address[31:0] Unreachable Unreachable Unreachable OUTPUT
tl_peri_o.a_source[5:0] Yes Yes *T15,*T9,*T14 Yes T15,T9,T14 OUTPUT
tl_peri_o.a_source[7:6] Unreachable Unreachable Unreachable OUTPUT
tl_peri_o.a_size[1:0] Yes Yes T44,T45,T46 Yes T44,T45,T46 OUTPUT
tl_peri_o.a_param[2:0] Unreachable Unreachable Unreachable OUTPUT
tl_peri_o.a_opcode[0] Yes Yes *T14,*T89,*T90 Yes T14,T89,T90 OUTPUT
tl_peri_o.a_opcode[1] No No No OUTPUT
tl_peri_o.a_opcode[2] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_peri_o.a_valid Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_peri_i.a_ready Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_peri_i.d_error Yes Yes T4,T78,T152 Yes T4,T78,T152 INPUT
tl_peri_i.d_user.data_intg[6:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_peri_i.d_user.rsp_intg[5:0] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 INPUT
tl_peri_i.d_user.rsp_intg[6] No No No INPUT
tl_peri_i.d_data[31:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_peri_i.d_sink No No No INPUT
tl_peri_i.d_source[5:0] Yes Yes *T15,*T9,*T14 Yes T15,T9,T14 INPUT
tl_peri_i.d_source[7:6] Unreachable Unreachable Unreachable INPUT
tl_peri_i.d_size[1:0] Yes Yes T44,T45,T46 Yes T44,T45,T46 INPUT
tl_peri_i.d_param[2:0] Unreachable Unreachable Unreachable INPUT
tl_peri_i.d_opcode[0] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 INPUT
tl_peri_i.d_opcode[2:1] Unreachable Unreachable Unreachable INPUT
tl_peri_i.d_valid Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_spi_host0_o.d_ready Yes Yes T153,T139,T26 Yes T153,T139,T26 OUTPUT
tl_spi_host0_o.a_user.data_intg[6:0] Yes Yes T139,T26,T27 Yes T139,T26,T27 OUTPUT
tl_spi_host0_o.a_user.cmd_intg[0] Yes Yes *T153,*T139,*T26 Yes T153,T139,T26 OUTPUT
tl_spi_host0_o.a_user.cmd_intg[1] No No No OUTPUT
tl_spi_host0_o.a_user.cmd_intg[6:2] Yes Yes T153,T139,T26 Yes T153,T139,T26 OUTPUT
tl_spi_host0_o.a_user.instr_type[0] Yes Yes *T153,*T139,*T26 Yes T153,T139,T26 OUTPUT
tl_spi_host0_o.a_user.instr_type[2:1] No No No OUTPUT
tl_spi_host0_o.a_user.instr_type[3] Yes Yes T153,T139,T26 Yes T153,T139,T26 OUTPUT
tl_spi_host0_o.a_user.rsvd[4:0] Unreachable Unreachable Unreachable OUTPUT
tl_spi_host0_o.a_data[31:0] Yes Yes T139,T26,T27 Yes T139,T26,T27 OUTPUT
tl_spi_host0_o.a_mask[3:0] Yes Yes T153,T139,T26 Yes T153,T139,T26 OUTPUT
tl_spi_host0_o.a_address[31:0] Unreachable Unreachable Unreachable OUTPUT
tl_spi_host0_o.a_source[1:0] Yes Yes *T14,*T153,*T139 Yes T14,T153,T139 OUTPUT
tl_spi_host0_o.a_source[5:2] No No No OUTPUT
tl_spi_host0_o.a_source[7:6] Unreachable Unreachable Unreachable OUTPUT
tl_spi_host0_o.a_size[0] No No No OUTPUT
tl_spi_host0_o.a_size[1] Yes Yes T153,T139,T26 Yes T153,T139,T26 OUTPUT
tl_spi_host0_o.a_param[2:0] Unreachable Unreachable Unreachable OUTPUT
tl_spi_host0_o.a_opcode[0] Yes Yes *T56,*T143,*T144 Yes T56,T143,T144 OUTPUT
tl_spi_host0_o.a_opcode[1] No No No OUTPUT
tl_spi_host0_o.a_opcode[2] Yes Yes T153,T139,T26 Yes T153,T139,T26 OUTPUT
tl_spi_host0_o.a_valid Yes Yes T153,T139,T26 Yes T153,T139,T26 OUTPUT
tl_spi_host0_i.a_ready Yes Yes T153,T139,T26 Yes T153,T139,T26 INPUT
tl_spi_host0_i.d_error No No No INPUT
tl_spi_host0_i.d_user.data_intg[6:0] Yes Yes T139,T26,T27 Yes T139,T26,T27 INPUT
tl_spi_host0_i.d_user.rsp_intg[1:0] Yes Yes T153,T139,T26 Yes T153,T139,T26 INPUT
tl_spi_host0_i.d_user.rsp_intg[3:2] No No No INPUT
tl_spi_host0_i.d_user.rsp_intg[5:4] Yes Yes T153,T140,T14 Yes T153,T139,T26 INPUT
tl_spi_host0_i.d_user.rsp_intg[6] No No No INPUT
tl_spi_host0_i.d_data[31:0] Yes Yes T139,T26,T27 Yes T139,T26,T27 INPUT
tl_spi_host0_i.d_sink No No No INPUT
tl_spi_host0_i.d_source[1:0] Yes Yes *T14,*T153,*T26 Yes T14,T153,T139 INPUT
tl_spi_host0_i.d_source[5:2] No No No INPUT
tl_spi_host0_i.d_source[7:6] Unreachable Unreachable Unreachable INPUT
tl_spi_host0_i.d_size[0] No No No INPUT
tl_spi_host0_i.d_size[1] Yes Yes T153,T140,T14 Yes T153,T139,T26 INPUT
tl_spi_host0_i.d_param[2:0] Unreachable Unreachable Unreachable INPUT
tl_spi_host0_i.d_opcode[0] Yes Yes *T153,*T139,*T26 Yes T153,T139,T26 INPUT
tl_spi_host0_i.d_opcode[2:1] Unreachable Unreachable Unreachable INPUT
tl_spi_host0_i.d_valid Yes Yes T153,T139,T26 Yes T153,T139,T26 INPUT
tl_spi_host1_o.d_ready Yes Yes T153,T139,T27 Yes T153,T139,T27 OUTPUT
tl_spi_host1_o.a_user.data_intg[6:0] Yes Yes T139,T27,T140 Yes T139,T27,T140 OUTPUT
tl_spi_host1_o.a_user.cmd_intg[6:0] Yes Yes T153,T139,T27 Yes T153,T139,T27 OUTPUT
tl_spi_host1_o.a_user.instr_type[0] Yes Yes *T153,*T139,*T27 Yes T153,T139,T27 OUTPUT
tl_spi_host1_o.a_user.instr_type[2:1] No No No OUTPUT
tl_spi_host1_o.a_user.instr_type[3] Yes Yes T153,T139,T27 Yes T153,T139,T27 OUTPUT
tl_spi_host1_o.a_user.rsvd[4:0] Unreachable Unreachable Unreachable OUTPUT
tl_spi_host1_o.a_data[31:0] Yes Yes T139,T27,T140 Yes T139,T27,T140 OUTPUT
tl_spi_host1_o.a_mask[3:0] Yes Yes T153,T139,T27 Yes T153,T139,T27 OUTPUT
tl_spi_host1_o.a_address[31:0] Unreachable Unreachable Unreachable OUTPUT
tl_spi_host1_o.a_source[1:0] Yes Yes *T14,*T153,*T139 Yes T14,T153,T139 OUTPUT
tl_spi_host1_o.a_source[5:2] No No No OUTPUT
tl_spi_host1_o.a_source[7:6] Unreachable Unreachable Unreachable OUTPUT
tl_spi_host1_o.a_size[0] No No No OUTPUT
tl_spi_host1_o.a_size[1] Yes Yes T153,T139,T27 Yes T153,T139,T27 OUTPUT
tl_spi_host1_o.a_param[2:0] Unreachable Unreachable Unreachable OUTPUT
tl_spi_host1_o.a_opcode[1:0] No No No OUTPUT
tl_spi_host1_o.a_opcode[2] Yes Yes T153,T139,T27 Yes T153,T139,T27 OUTPUT
tl_spi_host1_o.a_valid Yes Yes T153,T139,T27 Yes T153,T139,T27 OUTPUT
tl_spi_host1_i.a_ready Yes Yes T153,T139,T27 Yes T153,T139,T27 INPUT
tl_spi_host1_i.d_error No No No INPUT
tl_spi_host1_i.d_user.data_intg[6:0] Yes Yes T139,T27,T140 Yes T139,T27,T140 INPUT
tl_spi_host1_i.d_user.rsp_intg[1:0] Yes Yes T153,T139,T27 Yes T153,T139,T27 INPUT
tl_spi_host1_i.d_user.rsp_intg[3:2] No No No INPUT
tl_spi_host1_i.d_user.rsp_intg[5:4] Yes Yes T153,T27,T140 Yes T153,T139,T27 INPUT
tl_spi_host1_i.d_user.rsp_intg[6] No No No INPUT
tl_spi_host1_i.d_data[31:0] Yes Yes T139,T27,T140 Yes T139,T27,T140 INPUT
tl_spi_host1_i.d_sink No No No INPUT
tl_spi_host1_i.d_source[1:0] Yes Yes *T14,*T153,*T139 Yes T14,T153,T139 INPUT
tl_spi_host1_i.d_source[5:2] No No No INPUT
tl_spi_host1_i.d_source[7:6] Unreachable Unreachable Unreachable INPUT
tl_spi_host1_i.d_size[0] No No No INPUT
tl_spi_host1_i.d_size[1] Yes Yes T153,T27,T140 Yes T153,T139,T27 INPUT
tl_spi_host1_i.d_param[2:0] Unreachable Unreachable Unreachable INPUT
tl_spi_host1_i.d_opcode[0] Yes Yes *T153,*T139,*T27 Yes T153,T139,T27 INPUT
tl_spi_host1_i.d_opcode[2:1] Unreachable Unreachable Unreachable INPUT
tl_spi_host1_i.d_valid Yes Yes T153,T139,T27 Yes T153,T139,T27 INPUT
tl_usbdev_o.d_ready Yes Yes T32,T153,T92 Yes T32,T153,T92 OUTPUT
tl_usbdev_o.a_user.data_intg[6:0] Yes Yes T32,T153,T86 Yes T32,T153,T86 OUTPUT
tl_usbdev_o.a_user.cmd_intg[6:0] Yes Yes T32,T153,T92 Yes T32,T153,T92 OUTPUT
tl_usbdev_o.a_user.instr_type[0] Yes Yes *T32,*T153,*T92 Yes T32,T153,T92 OUTPUT
tl_usbdev_o.a_user.instr_type[2:1] No No No OUTPUT
tl_usbdev_o.a_user.instr_type[3] Yes Yes T32,T153,T92 Yes T32,T153,T92 OUTPUT
tl_usbdev_o.a_user.rsvd[4:0] Unreachable Unreachable Unreachable OUTPUT
tl_usbdev_o.a_data[31:0] Yes Yes T32,T86,T140 Yes T32,T86,T140 OUTPUT
tl_usbdev_o.a_mask[3:0] Yes Yes T32,T153,T92 Yes T32,T153,T92 OUTPUT
tl_usbdev_o.a_address[31:0] Unreachable Unreachable Unreachable OUTPUT
tl_usbdev_o.a_source[0] No No No OUTPUT
tl_usbdev_o.a_source[1] Yes Yes *T32,*T153,*T86 Yes T32,T153,T86 OUTPUT
tl_usbdev_o.a_source[5:2] No No No OUTPUT
tl_usbdev_o.a_source[7:6] Unreachable Unreachable Unreachable OUTPUT
tl_usbdev_o.a_size[0] No No No OUTPUT
tl_usbdev_o.a_size[1] Yes Yes T32,T153,T92 Yes T32,T153,T92 OUTPUT
tl_usbdev_o.a_param[2:0] Unreachable Unreachable Unreachable OUTPUT
tl_usbdev_o.a_opcode[1:0] No No No OUTPUT
tl_usbdev_o.a_opcode[2] Yes Yes T32,T153,T92 Yes T32,T153,T92 OUTPUT
tl_usbdev_o.a_valid Yes Yes T32,T153,T92 Yes T32,T153,T92 OUTPUT
tl_usbdev_i.a_ready Yes Yes T32,T153,T92 Yes T32,T153,T92 INPUT
tl_usbdev_i.d_error No No No INPUT
tl_usbdev_i.d_user.data_intg[6:0] Yes Yes T32,T153,T140 Yes T32,T153,T92 INPUT
tl_usbdev_i.d_user.rsp_intg[1:0] Yes Yes T32,T153,*T92 Yes T32,T153,T86 INPUT
tl_usbdev_i.d_user.rsp_intg[3:2] No No No INPUT
tl_usbdev_i.d_user.rsp_intg[5:4] Yes Yes T153,T140,T33 Yes T32,T153,T92 INPUT
tl_usbdev_i.d_user.rsp_intg[6] No No No INPUT
tl_usbdev_i.d_data[31:0] Yes Yes T32,T153,T92 Yes T32,T153,T140 INPUT
tl_usbdev_i.d_sink No No No INPUT
tl_usbdev_i.d_source[0] No No No INPUT
tl_usbdev_i.d_source[1] Yes Yes *T32,*T153,*T140 Yes T32,T153,T86 INPUT
tl_usbdev_i.d_source[5:2] No No No INPUT
tl_usbdev_i.d_source[7:6] Unreachable Unreachable Unreachable INPUT
tl_usbdev_i.d_size[0] No No No INPUT
tl_usbdev_i.d_size[1] Yes Yes T153,T140,T33 Yes T32,T153,T92 INPUT
tl_usbdev_i.d_param[2:0] Unreachable Unreachable Unreachable INPUT
tl_usbdev_i.d_opcode[0] Yes Yes *T32,*T153,*T86 Yes T32,T153,T140 INPUT
tl_usbdev_i.d_opcode[2:1] Unreachable Unreachable Unreachable INPUT
tl_usbdev_i.d_valid Yes Yes T32,T153,T92 Yes T32,T153,T92 INPUT
tl_flash_ctrl__core_o.d_ready Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_flash_ctrl__core_o.a_user.data_intg[6:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_flash_ctrl__core_o.a_user.cmd_intg[6:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_flash_ctrl__core_o.a_user.instr_type[0] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 OUTPUT
tl_flash_ctrl__core_o.a_user.instr_type[2:1] No No No OUTPUT
tl_flash_ctrl__core_o.a_user.instr_type[3] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_flash_ctrl__core_o.a_user.rsvd[4:0] Unreachable Unreachable Unreachable OUTPUT
tl_flash_ctrl__core_o.a_data[31:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_flash_ctrl__core_o.a_mask[3:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_flash_ctrl__core_o.a_address[31:0] Unreachable Unreachable Unreachable OUTPUT
tl_flash_ctrl__core_o.a_source[1:0] Yes Yes *T90,*T1,*T2 Yes T90,T1,T2 OUTPUT
tl_flash_ctrl__core_o.a_source[5:2] No No No OUTPUT
tl_flash_ctrl__core_o.a_source[7:6] Unreachable Unreachable Unreachable OUTPUT
tl_flash_ctrl__core_o.a_size[0] No No No OUTPUT
tl_flash_ctrl__core_o.a_size[1] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_flash_ctrl__core_o.a_param[2:0] Unreachable Unreachable Unreachable OUTPUT
tl_flash_ctrl__core_o.a_opcode[1:0] No No No OUTPUT
tl_flash_ctrl__core_o.a_opcode[2] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_flash_ctrl__core_o.a_valid Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_flash_ctrl__core_i.a_ready Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_flash_ctrl__core_i.d_error Yes Yes T1,T2,T3 Yes T4,T5,T6 INPUT
tl_flash_ctrl__core_i.d_user.data_intg[6:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_flash_ctrl__core_i.d_user.rsp_intg[2:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_flash_ctrl__core_i.d_user.rsp_intg[3] No No No INPUT
tl_flash_ctrl__core_i.d_user.rsp_intg[5:4] Yes Yes T59,T4,T5 Yes T1,T2,T3 INPUT
tl_flash_ctrl__core_i.d_user.rsp_intg[6] No No No INPUT
tl_flash_ctrl__core_i.d_data[31:0] Yes Yes T1,T2,T3 Yes T59,T4,T5 INPUT
tl_flash_ctrl__core_i.d_sink No No No INPUT
tl_flash_ctrl__core_i.d_source[1:0] Yes Yes *T90,*T1,*T2 Yes T90,T1,T2 INPUT
tl_flash_ctrl__core_i.d_source[5:2] No No No INPUT
tl_flash_ctrl__core_i.d_source[7:6] Unreachable Unreachable Unreachable INPUT
tl_flash_ctrl__core_i.d_size[0] No No No INPUT
tl_flash_ctrl__core_i.d_size[1] Yes Yes T59,T4,T5 Yes T1,T2,T3 INPUT
tl_flash_ctrl__core_i.d_param[2:0] Unreachable Unreachable Unreachable INPUT
tl_flash_ctrl__core_i.d_opcode[0] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 INPUT
tl_flash_ctrl__core_i.d_opcode[2:1] Unreachable Unreachable Unreachable INPUT
tl_flash_ctrl__core_i.d_valid Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_flash_ctrl__prim_o.d_ready Yes Yes T4,T5,T6 Yes T1,T2,T3 OUTPUT
tl_flash_ctrl__prim_o.a_user.data_intg[6:0] Yes Yes T90 Yes T90 OUTPUT
tl_flash_ctrl__prim_o.a_user.cmd_intg[6:0] Yes Yes T90 Yes T90 OUTPUT
tl_flash_ctrl__prim_o.a_user.instr_type[0] Yes Yes *T90 Yes T90 OUTPUT
tl_flash_ctrl__prim_o.a_user.instr_type[2:1] No No No OUTPUT
tl_flash_ctrl__prim_o.a_user.instr_type[3] Yes Yes T90 Yes T90 OUTPUT
tl_flash_ctrl__prim_o.a_user.rsvd[4:0] Unreachable Unreachable Unreachable OUTPUT
tl_flash_ctrl__prim_o.a_data[31:0] Yes Yes T90 Yes T90 OUTPUT
tl_flash_ctrl__prim_o.a_mask[3:0] Yes Yes T90 Yes T90 OUTPUT
tl_flash_ctrl__prim_o.a_address[31:0] Unreachable Unreachable Unreachable OUTPUT
tl_flash_ctrl__prim_o.a_source[0] Yes Yes *T90 Yes T90 OUTPUT
tl_flash_ctrl__prim_o.a_source[5:1] No No No OUTPUT
tl_flash_ctrl__prim_o.a_source[7:6] Unreachable Unreachable Unreachable OUTPUT
tl_flash_ctrl__prim_o.a_size[0] No No No OUTPUT
tl_flash_ctrl__prim_o.a_size[1] Yes Yes T90 Yes T90 OUTPUT
tl_flash_ctrl__prim_o.a_param[2:0] Unreachable Unreachable Unreachable OUTPUT
tl_flash_ctrl__prim_o.a_opcode[1:0] No No No OUTPUT
tl_flash_ctrl__prim_o.a_opcode[2] Yes Yes T90 Yes T90 OUTPUT
tl_flash_ctrl__prim_o.a_valid Yes Yes T90 Yes T90 OUTPUT
tl_flash_ctrl__prim_i.a_ready Yes Yes T90 Yes T90 INPUT
tl_flash_ctrl__prim_i.d_error No No No INPUT
tl_flash_ctrl__prim_i.d_user.data_intg[6:0] Yes Yes T90 Yes T90 INPUT
tl_flash_ctrl__prim_i.d_user.rsp_intg[1:0] Yes Yes T90 Yes T90 INPUT
tl_flash_ctrl__prim_i.d_user.rsp_intg[3:2] No No No INPUT
tl_flash_ctrl__prim_i.d_user.rsp_intg[5:4] Yes Yes T90 Yes T90 INPUT
tl_flash_ctrl__prim_i.d_user.rsp_intg[6] No No No INPUT
tl_flash_ctrl__prim_i.d_data[31:0] Yes Yes T90 Yes T90 INPUT
tl_flash_ctrl__prim_i.d_sink No No No INPUT
tl_flash_ctrl__prim_i.d_source[0] Yes Yes *T90 Yes T90 INPUT
tl_flash_ctrl__prim_i.d_source[5:1] No No No INPUT
tl_flash_ctrl__prim_i.d_source[7:6] Unreachable Unreachable Unreachable INPUT
tl_flash_ctrl__prim_i.d_size[0] No No No INPUT
tl_flash_ctrl__prim_i.d_size[1] Yes Yes T90 Yes T90 INPUT
tl_flash_ctrl__prim_i.d_param[2:0] Unreachable Unreachable Unreachable INPUT
tl_flash_ctrl__prim_i.d_opcode[0] Yes Yes *T90 Yes T90 INPUT
tl_flash_ctrl__prim_i.d_opcode[2:1] Unreachable Unreachable Unreachable INPUT
tl_flash_ctrl__prim_i.d_valid Yes Yes T90 Yes T90 INPUT
tl_flash_ctrl__mem_o.d_ready Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_flash_ctrl__mem_o.a_user.data_intg[6:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_flash_ctrl__mem_o.a_user.cmd_intg[6:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_flash_ctrl__mem_o.a_user.instr_type[3:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_flash_ctrl__mem_o.a_user.rsvd[4:0] Unreachable Unreachable Unreachable OUTPUT
tl_flash_ctrl__mem_o.a_data[31:0] Yes Yes T1,T3,T59 Yes T1,T3,T59 OUTPUT
tl_flash_ctrl__mem_o.a_mask[3:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_flash_ctrl__mem_o.a_address[31:0] Unreachable Unreachable Unreachable OUTPUT
tl_flash_ctrl__mem_o.a_source[0] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 OUTPUT
tl_flash_ctrl__mem_o.a_source[1] No No No OUTPUT
tl_flash_ctrl__mem_o.a_source[4:2] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_flash_ctrl__mem_o.a_source[5] No No No OUTPUT
tl_flash_ctrl__mem_o.a_source[7:6] Unreachable Unreachable Unreachable OUTPUT
tl_flash_ctrl__mem_o.a_size[0] No No No OUTPUT
tl_flash_ctrl__mem_o.a_size[1] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_flash_ctrl__mem_o.a_param[2:0] Unreachable Unreachable Unreachable OUTPUT
tl_flash_ctrl__mem_o.a_opcode[1:0] No No No OUTPUT
tl_flash_ctrl__mem_o.a_opcode[2] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_flash_ctrl__mem_o.a_valid Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_flash_ctrl__mem_i.a_ready Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_flash_ctrl__mem_i.d_error Yes Yes T1,T2,T3 Yes T4,T5,T6 INPUT
tl_flash_ctrl__mem_i.d_user.data_intg[6:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_flash_ctrl__mem_i.d_user.rsp_intg[2:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_flash_ctrl__mem_i.d_user.rsp_intg[3] No No No INPUT
tl_flash_ctrl__mem_i.d_user.rsp_intg[4] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 INPUT
tl_flash_ctrl__mem_i.d_user.rsp_intg[6:5] No No No INPUT
tl_flash_ctrl__mem_i.d_data[31:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_flash_ctrl__mem_i.d_sink No No No INPUT
tl_flash_ctrl__mem_i.d_source[0] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 INPUT
tl_flash_ctrl__mem_i.d_source[1] No No No INPUT
tl_flash_ctrl__mem_i.d_source[4:2] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_flash_ctrl__mem_i.d_source[5] No No No INPUT
tl_flash_ctrl__mem_i.d_source[7:6] Unreachable Unreachable Unreachable INPUT
tl_flash_ctrl__mem_i.d_size[0] No No No INPUT
tl_flash_ctrl__mem_i.d_size[1] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_flash_ctrl__mem_i.d_param[2:0] Unreachable Unreachable Unreachable INPUT
tl_flash_ctrl__mem_i.d_opcode[0] No No No INPUT
tl_flash_ctrl__mem_i.d_opcode[2:1] Unreachable Unreachable Unreachable INPUT
tl_flash_ctrl__mem_i.d_valid Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_hmac_o.d_ready Yes Yes T59,T4,T5 Yes T1,T2,T3 OUTPUT
tl_hmac_o.a_user.data_intg[6:0] Yes Yes T59,T5,T7 Yes T59,T5,T7 OUTPUT
tl_hmac_o.a_user.cmd_intg[6:0] Yes Yes T59,T5,T7 Yes T59,T5,T7 OUTPUT
tl_hmac_o.a_user.instr_type[0] Yes Yes *T59,*T5,*T7 Yes T59,T5,T7 OUTPUT
tl_hmac_o.a_user.instr_type[2:1] No No No OUTPUT
tl_hmac_o.a_user.instr_type[3] Yes Yes T59,T5,T7 Yes T59,T5,T7 OUTPUT
tl_hmac_o.a_user.rsvd[4:0] Unreachable Unreachable Unreachable OUTPUT
tl_hmac_o.a_data[31:0] Yes Yes T59,T5,T7 Yes T59,T5,T7 OUTPUT
tl_hmac_o.a_mask[3:0] Yes Yes T59,T5,T7 Yes T59,T5,T7 OUTPUT
tl_hmac_o.a_address[31:0] Unreachable Unreachable Unreachable OUTPUT
tl_hmac_o.a_source[1:0] Yes Yes *T90,*T59,*T5 Yes T90,T59,T5 OUTPUT
tl_hmac_o.a_source[5:2] No No No OUTPUT
tl_hmac_o.a_source[7:6] Unreachable Unreachable Unreachable OUTPUT
tl_hmac_o.a_size[0] No No No OUTPUT
tl_hmac_o.a_size[1] Yes Yes T59,T5,T7 Yes T59,T5,T7 OUTPUT
tl_hmac_o.a_param[2:0] Unreachable Unreachable Unreachable OUTPUT
tl_hmac_o.a_opcode[0] Yes Yes *T109,*T154,*T155 Yes T109,T154,T155 OUTPUT
tl_hmac_o.a_opcode[1] No No No OUTPUT
tl_hmac_o.a_opcode[2] Yes Yes T59,T5,T7 Yes T59,T5,T7 OUTPUT
tl_hmac_o.a_valid Yes Yes T59,T5,T7 Yes T59,T5,T7 OUTPUT
tl_hmac_i.a_ready Yes Yes T59,T5,T7 Yes T59,T5,T7 INPUT
tl_hmac_i.d_error No No No INPUT
tl_hmac_i.d_user.data_intg[6:0] Yes Yes T59,T5,T7 Yes T59,T5,T7 INPUT
tl_hmac_i.d_user.rsp_intg[1:0] Yes Yes T59,T5,T7 Yes T59,T5,T7 INPUT
tl_hmac_i.d_user.rsp_intg[3:2] No No No INPUT
tl_hmac_i.d_user.rsp_intg[5:4] Yes Yes T59,T5,T7 Yes T59,T5,T7 INPUT
tl_hmac_i.d_user.rsp_intg[6] No No No INPUT
tl_hmac_i.d_data[31:0] Yes Yes T59,T5,T7 Yes T59,T5,T7 INPUT
tl_hmac_i.d_sink No No No INPUT
tl_hmac_i.d_source[1:0] Yes Yes *T90,*T59,*T5 Yes T90,T59,T5 INPUT
tl_hmac_i.d_source[5:2] No No No INPUT
tl_hmac_i.d_source[7:6] Unreachable Unreachable Unreachable INPUT
tl_hmac_i.d_size[0] No No No INPUT
tl_hmac_i.d_size[1] Yes Yes T59,T5,T7 Yes T59,T5,T7 INPUT
tl_hmac_i.d_param[2:0] Unreachable Unreachable Unreachable INPUT
tl_hmac_i.d_opcode[0] Yes Yes *T59,*T5,*T7 Yes T59,T5,T7 INPUT
tl_hmac_i.d_opcode[2:1] Unreachable Unreachable Unreachable INPUT
tl_hmac_i.d_valid Yes Yes T59,T5,T7 Yes T59,T5,T7 INPUT
tl_kmac_o.d_ready Yes Yes T2,T4,T5 Yes T1,T2,T3 OUTPUT
tl_kmac_o.a_user.data_intg[6:0] Yes Yes T2,T47,T156 Yes T2,T47,T156 OUTPUT
tl_kmac_o.a_user.cmd_intg[6:0] Yes Yes T2,T47,T156 Yes T2,T47,T156 OUTPUT
tl_kmac_o.a_user.instr_type[0] Yes Yes *T2,*T47,*T156 Yes T2,T47,T156 OUTPUT
tl_kmac_o.a_user.instr_type[2:1] No No No OUTPUT
tl_kmac_o.a_user.instr_type[3] Yes Yes T2,T47,T156 Yes T2,T47,T156 OUTPUT
tl_kmac_o.a_user.rsvd[4:0] Unreachable Unreachable Unreachable OUTPUT
tl_kmac_o.a_data[31:0] Yes Yes T2,T47,T156 Yes T2,T47,T156 OUTPUT
tl_kmac_o.a_mask[3:0] Yes Yes T2,T47,T156 Yes T2,T47,T156 OUTPUT
tl_kmac_o.a_address[31:0] Unreachable Unreachable Unreachable OUTPUT
tl_kmac_o.a_source[1:0] Yes Yes *T90,*T63,*T2 Yes T90,T63,T2 OUTPUT
tl_kmac_o.a_source[5:2] No No No OUTPUT
tl_kmac_o.a_source[7:6] Unreachable Unreachable Unreachable OUTPUT
tl_kmac_o.a_size[0] No No No OUTPUT
tl_kmac_o.a_size[1] Yes Yes T2,T47,T156 Yes T2,T47,T156 OUTPUT
tl_kmac_o.a_param[2:0] Unreachable Unreachable Unreachable OUTPUT
tl_kmac_o.a_opcode[0] Yes Yes *T2,*T156,*T157 Yes T2,T156,T157 OUTPUT
tl_kmac_o.a_opcode[1] No No No OUTPUT
tl_kmac_o.a_opcode[2] Yes Yes T2,T47,T156 Yes T2,T47,T156 OUTPUT
tl_kmac_o.a_valid Yes Yes T2,T47,T156 Yes T2,T47,T156 OUTPUT
tl_kmac_i.a_ready Yes Yes T2,T47,T156 Yes T2,T47,T156 INPUT
tl_kmac_i.d_error No No No INPUT
tl_kmac_i.d_user.data_intg[6:0] Yes Yes T2,T47,T156 Yes T2,T47,T156 INPUT
tl_kmac_i.d_user.rsp_intg[1:0] Yes Yes T2,T47,T156 Yes T2,T47,T156 INPUT
tl_kmac_i.d_user.rsp_intg[3:2] No No No INPUT
tl_kmac_i.d_user.rsp_intg[5:4] Yes Yes T2,T156,T157 Yes T2,T47,T156 INPUT
tl_kmac_i.d_user.rsp_intg[6] No No No INPUT
tl_kmac_i.d_data[31:0] Yes Yes T2,T47,T156 Yes T2,T156,T139 INPUT
tl_kmac_i.d_sink No No No INPUT
tl_kmac_i.d_source[1:0] Yes Yes *T90,*T63,*T2 Yes T90,T63,T2 INPUT
tl_kmac_i.d_source[5:2] No No No INPUT
tl_kmac_i.d_source[7:6] Unreachable Unreachable Unreachable INPUT
tl_kmac_i.d_size[0] No No No INPUT
tl_kmac_i.d_size[1] Yes Yes T2,T156,T157 Yes T2,T47,T156 INPUT
tl_kmac_i.d_param[2:0] Unreachable Unreachable Unreachable INPUT
tl_kmac_i.d_opcode[0] Yes Yes *T2,*T47,*T156 Yes T2,T156,T139 INPUT
tl_kmac_i.d_opcode[2:1] Unreachable Unreachable Unreachable INPUT
tl_kmac_i.d_valid Yes Yes T2,T47,T156 Yes T2,T47,T156 INPUT
tl_aes_o.d_ready Yes Yes T4,T5,T6 Yes T1,T2,T3 OUTPUT
tl_aes_o.a_user.data_intg[6:0] Yes Yes T158,T115,T159 Yes T158,T115,T159 OUTPUT
tl_aes_o.a_user.cmd_intg[0] Yes Yes *T158,*T115,*T159 Yes T158,T115,T159 OUTPUT
tl_aes_o.a_user.cmd_intg[1] No No No OUTPUT
tl_aes_o.a_user.cmd_intg[6:2] Yes Yes T158,T115,T159 Yes T158,T115,T159 OUTPUT
tl_aes_o.a_user.instr_type[0] Yes Yes *T158,*T115,*T159 Yes T158,T115,T159 OUTPUT
tl_aes_o.a_user.instr_type[2:1] No No No OUTPUT
tl_aes_o.a_user.instr_type[3] Yes Yes T158,T115,T159 Yes T158,T115,T159 OUTPUT
tl_aes_o.a_user.rsvd[4:0] Unreachable Unreachable Unreachable OUTPUT
tl_aes_o.a_data[31:0] Yes Yes T158,T115,T159 Yes T158,T115,T159 OUTPUT
tl_aes_o.a_mask[3:0] Yes Yes T158,T115,T159 Yes T158,T115,T159 OUTPUT
tl_aes_o.a_address[31:0] Unreachable Unreachable Unreachable OUTPUT
tl_aes_o.a_source[1:0] Yes Yes *T90,*T158,*T115 Yes T90,T158,T115 OUTPUT
tl_aes_o.a_source[5:2] No No No OUTPUT
tl_aes_o.a_source[7:6] Unreachable Unreachable Unreachable OUTPUT
tl_aes_o.a_size[0] No No No OUTPUT
tl_aes_o.a_size[1] Yes Yes T158,T115,T159 Yes T158,T115,T159 OUTPUT
tl_aes_o.a_param[2:0] Unreachable Unreachable Unreachable OUTPUT
tl_aes_o.a_opcode[1:0] No No No OUTPUT
tl_aes_o.a_opcode[2] Yes Yes T158,T115,T159 Yes T158,T115,T159 OUTPUT
tl_aes_o.a_valid Yes Yes T158,T115,T159 Yes T158,T115,T159 OUTPUT
tl_aes_i.a_ready Yes Yes T158,T115,T159 Yes T158,T115,T159 INPUT
tl_aes_i.d_error No No No INPUT
tl_aes_i.d_user.data_intg[6:0] Yes Yes T158,T115,T159 Yes T158,T115,T159 INPUT
tl_aes_i.d_user.rsp_intg[1:0] Yes Yes T158,T115,T159 Yes T158,T115,T159 INPUT
tl_aes_i.d_user.rsp_intg[3:2] No No No INPUT
tl_aes_i.d_user.rsp_intg[5:4] Yes Yes T160,*T161,*T90 Yes T158,T115,T159 INPUT
tl_aes_i.d_user.rsp_intg[6] No No No INPUT
tl_aes_i.d_data[31:0] Yes Yes T158,T159,T162 Yes T158,T115,T159 INPUT
tl_aes_i.d_sink No No No INPUT
tl_aes_i.d_source[1:0] Yes Yes *T90,*T158,*T115 Yes T90,T158,T115 INPUT
tl_aes_i.d_source[5:2] No No No INPUT
tl_aes_i.d_source[7:6] Unreachable Unreachable Unreachable INPUT
tl_aes_i.d_size[0] No No No INPUT
tl_aes_i.d_size[1] Yes Yes T160,T161,T90 Yes T158,T115,T159 INPUT
tl_aes_i.d_param[2:0] Unreachable Unreachable Unreachable INPUT
tl_aes_i.d_opcode[0] Yes Yes *T158,*T115,*T159 Yes T158,T115,T159 INPUT
tl_aes_i.d_opcode[2:1] Unreachable Unreachable Unreachable INPUT
tl_aes_i.d_valid Yes Yes T158,T115,T159 Yes T158,T115,T159 INPUT
tl_entropy_src_o.d_ready Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_entropy_src_o.a_user.data_intg[6:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_entropy_src_o.a_user.cmd_intg[6:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_entropy_src_o.a_user.instr_type[0] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 OUTPUT
tl_entropy_src_o.a_user.instr_type[2:1] No No No OUTPUT
tl_entropy_src_o.a_user.instr_type[3] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_entropy_src_o.a_user.rsvd[4:0] Unreachable Unreachable Unreachable OUTPUT
tl_entropy_src_o.a_data[31:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_entropy_src_o.a_mask[3:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_entropy_src_o.a_address[31:0] Unreachable Unreachable Unreachable OUTPUT
tl_entropy_src_o.a_source[1:0] Yes Yes *T90,*T1,*T2 Yes T90,T1,T2 OUTPUT
tl_entropy_src_o.a_source[5:2] No No No OUTPUT
tl_entropy_src_o.a_source[7:6] Unreachable Unreachable Unreachable OUTPUT
tl_entropy_src_o.a_size[0] No No No OUTPUT
tl_entropy_src_o.a_size[1] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_entropy_src_o.a_param[2:0] Unreachable Unreachable Unreachable OUTPUT
tl_entropy_src_o.a_opcode[1:0] No No No OUTPUT
tl_entropy_src_o.a_opcode[2] Yes Yes T59,T22,T47 Yes T59,T22,T47 OUTPUT
tl_entropy_src_o.a_valid Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_entropy_src_i.a_ready Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_entropy_src_i.d_error No No No INPUT
tl_entropy_src_i.d_user.data_intg[6:0] Yes Yes T22,T47,T123 Yes T22,T47,T123 INPUT
tl_entropy_src_i.d_user.rsp_intg[1:0] Yes Yes T59,T22,T4 Yes T1,T2,T3 INPUT
tl_entropy_src_i.d_user.rsp_intg[3:2] No No No INPUT
tl_entropy_src_i.d_user.rsp_intg[5:4] Yes Yes *T4,*T5,*T6 Yes T1,T2,T3 INPUT
tl_entropy_src_i.d_user.rsp_intg[6] No No No INPUT
tl_entropy_src_i.d_data[31:0] Yes Yes T59,T22,T4 Yes T1,T2,T3 INPUT
tl_entropy_src_i.d_sink No No No INPUT
tl_entropy_src_i.d_source[1:0] Yes Yes *T90,*T59,*T22 Yes T90,T1,T2 INPUT
tl_entropy_src_i.d_source[5:2] No No No INPUT
tl_entropy_src_i.d_source[7:6] Unreachable Unreachable Unreachable INPUT
tl_entropy_src_i.d_size[0] No No No INPUT
tl_entropy_src_i.d_size[1] Yes Yes T4,T5,T6 Yes T1,T2,T3 INPUT
tl_entropy_src_i.d_param[2:0] Unreachable Unreachable Unreachable INPUT
tl_entropy_src_i.d_opcode[0] Yes Yes *T22,*T47,*T58 Yes T59,T22,T47 INPUT
tl_entropy_src_i.d_opcode[2:1] Unreachable Unreachable Unreachable INPUT
tl_entropy_src_i.d_valid Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_csrng_o.d_ready Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_csrng_o.a_user.data_intg[6:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_csrng_o.a_user.cmd_intg[6:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_csrng_o.a_user.instr_type[0] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 OUTPUT
tl_csrng_o.a_user.instr_type[2:1] No No No OUTPUT
tl_csrng_o.a_user.instr_type[3] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_csrng_o.a_user.rsvd[4:0] Unreachable Unreachable Unreachable OUTPUT
tl_csrng_o.a_data[31:0] Yes Yes T22,T47,T163 Yes T22,T47,T163 OUTPUT
tl_csrng_o.a_mask[3:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_csrng_o.a_address[31:0] Unreachable Unreachable Unreachable OUTPUT
tl_csrng_o.a_source[1:0] Yes Yes *T90,*T22,*T47 Yes T90,T22,T47 OUTPUT
tl_csrng_o.a_source[5:2] No No No OUTPUT
tl_csrng_o.a_source[7:6] Unreachable Unreachable Unreachable OUTPUT
tl_csrng_o.a_size[0] No No No OUTPUT
tl_csrng_o.a_size[1] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_csrng_o.a_param[2:0] Unreachable Unreachable Unreachable OUTPUT
tl_csrng_o.a_opcode[1:0] No No No OUTPUT
tl_csrng_o.a_opcode[2] Yes Yes T22,T47,T163 Yes T22,T47,T163 OUTPUT
tl_csrng_o.a_valid Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_csrng_i.a_ready Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_csrng_i.d_error No No No INPUT
tl_csrng_i.d_user.data_intg[6:0] Yes Yes T22,T47,T163 Yes T22,T47,T163 INPUT
tl_csrng_i.d_user.rsp_intg[1:0] Yes Yes T22,T4,T5 Yes T1,T2,T3 INPUT
tl_csrng_i.d_user.rsp_intg[3:2] No No No INPUT
tl_csrng_i.d_user.rsp_intg[5:4] Yes Yes *T4,*T5,*T6 Yes T1,T2,T3 INPUT
tl_csrng_i.d_user.rsp_intg[6] No No No INPUT
tl_csrng_i.d_data[31:0] Yes Yes T22,T4,T5 Yes T1,T2,T3 INPUT
tl_csrng_i.d_sink No No No INPUT
tl_csrng_i.d_source[1:0] Yes Yes *T90,*T22,*T47 Yes T90,T22,T47 INPUT
tl_csrng_i.d_source[5:2] No No No INPUT
tl_csrng_i.d_source[7:6] Unreachable Unreachable Unreachable INPUT
tl_csrng_i.d_size[0] No No No INPUT
tl_csrng_i.d_size[1] Yes Yes T4,T5,T6 Yes T1,T2,T3 INPUT
tl_csrng_i.d_param[2:0] Unreachable Unreachable Unreachable INPUT
tl_csrng_i.d_opcode[0] Yes Yes *T22,*T47,*T163 Yes T22,T47,T163 INPUT
tl_csrng_i.d_opcode[2:1] Unreachable Unreachable Unreachable INPUT
tl_csrng_i.d_valid Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_edn0_o.d_ready Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_edn0_o.a_user.data_intg[6:0] Yes Yes T22,T47,T123 Yes T22,T47,T123 OUTPUT
tl_edn0_o.a_user.cmd_intg[0] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 OUTPUT
tl_edn0_o.a_user.cmd_intg[1] No No No OUTPUT
tl_edn0_o.a_user.cmd_intg[6:2] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_edn0_o.a_user.instr_type[0] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 OUTPUT
tl_edn0_o.a_user.instr_type[2:1] No No No OUTPUT
tl_edn0_o.a_user.instr_type[3] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_edn0_o.a_user.rsvd[4:0] Unreachable Unreachable Unreachable OUTPUT
tl_edn0_o.a_data[31:0] Yes Yes T22,T47,T123 Yes T22,T47,T123 OUTPUT
tl_edn0_o.a_mask[3:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_edn0_o.a_address[31:0] Unreachable Unreachable Unreachable OUTPUT
tl_edn0_o.a_source[1:0] Yes Yes *T90,*T1,*T2 Yes T90,T1,T2 OUTPUT
tl_edn0_o.a_source[5:2] No No No OUTPUT
tl_edn0_o.a_source[7:6] Unreachable Unreachable Unreachable OUTPUT
tl_edn0_o.a_size[0] No No No OUTPUT
tl_edn0_o.a_size[1] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_edn0_o.a_param[2:0] Unreachable Unreachable Unreachable OUTPUT
tl_edn0_o.a_opcode[1:0] No No No OUTPUT
tl_edn0_o.a_opcode[2] Yes Yes T22,T47,T123 Yes T22,T47,T123 OUTPUT
tl_edn0_o.a_valid Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_edn0_i.a_ready Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_edn0_i.d_error No No No INPUT
tl_edn0_i.d_user.data_intg[6:0] Yes Yes T22,T47,T123 Yes T22,T47,T123 INPUT
tl_edn0_i.d_user.rsp_intg[1:0] Yes Yes T22,T4,T5 Yes T1,T2,T3 INPUT
tl_edn0_i.d_user.rsp_intg[3:2] No No No INPUT
tl_edn0_i.d_user.rsp_intg[5:4] Yes Yes *T4,*T5,*T6 Yes T1,T2,T3 INPUT
tl_edn0_i.d_user.rsp_intg[6] No No No INPUT
tl_edn0_i.d_data[31:0] Yes Yes T22,T4,T5 Yes T1,T2,T3 INPUT
tl_edn0_i.d_sink No No No INPUT
tl_edn0_i.d_source[1:0] Yes Yes *T90,*T22,*T4 Yes T90,T1,T2 INPUT
tl_edn0_i.d_source[5:2] No No No INPUT
tl_edn0_i.d_source[7:6] Unreachable Unreachable Unreachable INPUT
tl_edn0_i.d_size[0] No No No INPUT
tl_edn0_i.d_size[1] Yes Yes T4,T5,T6 Yes T1,T2,T3 INPUT
tl_edn0_i.d_param[2:0] Unreachable Unreachable Unreachable INPUT
tl_edn0_i.d_opcode[0] Yes Yes *T22,*T47,*T123 Yes T22,T47,T123 INPUT
tl_edn0_i.d_opcode[2:1] Unreachable Unreachable Unreachable INPUT
tl_edn0_i.d_valid Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_edn1_o.d_ready Yes Yes T22,T4,T5 Yes T1,T2,T3 OUTPUT
tl_edn1_o.a_user.data_intg[6:0] Yes Yes T22,T47,T123 Yes T22,T47,T123 OUTPUT
tl_edn1_o.a_user.cmd_intg[0] Yes Yes *T22,*T47,*T123 Yes T22,T47,T123 OUTPUT
tl_edn1_o.a_user.cmd_intg[1] No No No OUTPUT
tl_edn1_o.a_user.cmd_intg[6:2] Yes Yes T22,T47,T123 Yes T22,T47,T123 OUTPUT
tl_edn1_o.a_user.instr_type[0] Yes Yes *T22,*T47,*T123 Yes T22,T47,T123 OUTPUT
tl_edn1_o.a_user.instr_type[2:1] No No No OUTPUT
tl_edn1_o.a_user.instr_type[3] Yes Yes T22,T47,T123 Yes T22,T47,T123 OUTPUT
tl_edn1_o.a_user.rsvd[4:0] Unreachable Unreachable Unreachable OUTPUT
tl_edn1_o.a_data[31:0] Yes Yes T22,T47,T123 Yes T22,T47,T123 OUTPUT
tl_edn1_o.a_mask[3:0] Yes Yes T22,T47,T123 Yes T22,T47,T123 OUTPUT
tl_edn1_o.a_address[31:0] Unreachable Unreachable Unreachable OUTPUT
tl_edn1_o.a_source[1:0] Yes Yes *T90,*T22,*T47 Yes T90,T22,T47 OUTPUT
tl_edn1_o.a_source[5:2] No No No OUTPUT
tl_edn1_o.a_source[7:6] Unreachable Unreachable Unreachable OUTPUT
tl_edn1_o.a_size[0] No No No OUTPUT
tl_edn1_o.a_size[1] Yes Yes T22,T47,T123 Yes T22,T47,T123 OUTPUT
tl_edn1_o.a_param[2:0] Unreachable Unreachable Unreachable OUTPUT
tl_edn1_o.a_opcode[1:0] No No No OUTPUT
tl_edn1_o.a_opcode[2] Yes Yes T22,T47,T123 Yes T22,T47,T123 OUTPUT
tl_edn1_o.a_valid Yes Yes T22,T47,T123 Yes T22,T47,T123 OUTPUT
tl_edn1_i.a_ready Yes Yes T22,T47,T123 Yes T22,T47,T123 INPUT
tl_edn1_i.d_error No No No INPUT
tl_edn1_i.d_user.data_intg[6:0] Yes Yes T22,T47,T123 Yes T22,T47,T123 INPUT
tl_edn1_i.d_user.rsp_intg[1:0] Yes Yes T22,T47,T123 Yes T22,T47,T123 INPUT
tl_edn1_i.d_user.rsp_intg[3:2] No No No INPUT
tl_edn1_i.d_user.rsp_intg[5:4] Yes Yes *T119,*T120,*T164 Yes T22,T47,T123 INPUT
tl_edn1_i.d_user.rsp_intg[6] No No No INPUT
tl_edn1_i.d_data[31:0] Yes Yes T22,T47,T123 Yes T22,T47,T123 INPUT
tl_edn1_i.d_sink No No No INPUT
tl_edn1_i.d_source[1:0] Yes Yes *T90,*T22,*T47 Yes T90,T22,T47 INPUT
tl_edn1_i.d_source[5:2] No No No INPUT
tl_edn1_i.d_source[7:6] Unreachable Unreachable Unreachable INPUT
tl_edn1_i.d_size[0] No No No INPUT
tl_edn1_i.d_size[1] Yes Yes T119,T120,T164 Yes T22,T47,T123 INPUT
tl_edn1_i.d_param[2:0] Unreachable Unreachable Unreachable INPUT
tl_edn1_i.d_opcode[0] Yes Yes *T22,*T47,*T123 Yes T22,T47,T123 INPUT
tl_edn1_i.d_opcode[2:1] Unreachable Unreachable Unreachable INPUT
tl_edn1_i.d_valid Yes Yes T22,T47,T123 Yes T22,T47,T123 INPUT
tl_rv_plic_o.d_ready Yes Yes T1,T3,T22 Yes T1,T2,T3 OUTPUT
tl_rv_plic_o.a_user.data_intg[6:0] Yes Yes T1,T3,T22 Yes T1,T3,T22 OUTPUT
tl_rv_plic_o.a_user.cmd_intg[6:0] Yes Yes T1,T3,T22 Yes T1,T3,T22 OUTPUT
tl_rv_plic_o.a_user.instr_type[0] Yes Yes *T1,*T3,*T22 Yes T1,T3,T22 OUTPUT
tl_rv_plic_o.a_user.instr_type[2:1] No No No OUTPUT
tl_rv_plic_o.a_user.instr_type[3] Yes Yes T1,T3,T22 Yes T1,T3,T22 OUTPUT
tl_rv_plic_o.a_user.rsvd[4:0] Unreachable Unreachable Unreachable OUTPUT
tl_rv_plic_o.a_data[31:0] Yes Yes T1,T3,T22 Yes T1,T3,T22 OUTPUT
tl_rv_plic_o.a_mask[3:0] Yes Yes T1,T3,T22 Yes T1,T3,T22 OUTPUT
tl_rv_plic_o.a_address[31:0] Unreachable Unreachable Unreachable OUTPUT
tl_rv_plic_o.a_source[1:0] Yes Yes *T14,*T1,*T3 Yes T14,T1,T3 OUTPUT
tl_rv_plic_o.a_source[5:2] No No No OUTPUT
tl_rv_plic_o.a_source[7:6] Unreachable Unreachable Unreachable OUTPUT
tl_rv_plic_o.a_size[0] No No No OUTPUT
tl_rv_plic_o.a_size[1] Yes Yes T1,T3,T22 Yes T1,T3,T22 OUTPUT
tl_rv_plic_o.a_param[2:0] Unreachable Unreachable Unreachable OUTPUT
tl_rv_plic_o.a_opcode[1:0] No No No OUTPUT
tl_rv_plic_o.a_opcode[2] Yes Yes T1,T3,T22 Yes T1,T3,T22 OUTPUT
tl_rv_plic_o.a_valid Yes Yes T1,T3,T22 Yes T1,T3,T22 OUTPUT
tl_rv_plic_i.a_ready Yes Yes T1,T3,T22 Yes T1,T3,T22 INPUT
tl_rv_plic_i.d_error No No No INPUT
tl_rv_plic_i.d_user.data_intg[6:0] Yes Yes T1,T3,T22 Yes T1,T3,T22 INPUT
tl_rv_plic_i.d_user.rsp_intg[1:0] Yes Yes T1,T3,T22 Yes T1,T3,T22 INPUT
tl_rv_plic_i.d_user.rsp_intg[3:2] No No No INPUT
tl_rv_plic_i.d_user.rsp_intg[5:4] Yes Yes T4,T77,T78 Yes T1,T3,T22 INPUT
tl_rv_plic_i.d_user.rsp_intg[6] No No No INPUT
tl_rv_plic_i.d_data[31:0] Yes Yes T1,T3,T22 Yes T1,T3,T22 INPUT
tl_rv_plic_i.d_sink No No No INPUT
tl_rv_plic_i.d_source[1:0] Yes Yes *T14,*T1,*T3 Yes T14,T1,T3 INPUT
tl_rv_plic_i.d_source[5:2] No No No INPUT
tl_rv_plic_i.d_source[7:6] Unreachable Unreachable Unreachable INPUT
tl_rv_plic_i.d_size[0] No No No INPUT
tl_rv_plic_i.d_size[1] Yes Yes T4,T77,T78 Yes T1,T3,T22 INPUT
tl_rv_plic_i.d_param[2:0] Unreachable Unreachable Unreachable INPUT
tl_rv_plic_i.d_opcode[0] Yes Yes *T1,*T3,*T22 Yes T1,T3,T22 INPUT
tl_rv_plic_i.d_opcode[2:1] Unreachable Unreachable Unreachable INPUT
tl_rv_plic_i.d_valid Yes Yes T1,T3,T22 Yes T1,T3,T22 INPUT
tl_otbn_o.d_ready Yes Yes T59,T22,T4 Yes T1,T2,T3 OUTPUT
tl_otbn_o.a_user.data_intg[6:0] Yes Yes T59,T22,T5 Yes T59,T22,T5 OUTPUT
tl_otbn_o.a_user.cmd_intg[6:0] Yes Yes T59,T22,T5 Yes T59,T22,T5 OUTPUT
tl_otbn_o.a_user.instr_type[0] Yes Yes *T59,*T22,*T5 Yes T59,T22,T5 OUTPUT
tl_otbn_o.a_user.instr_type[2:1] No No No OUTPUT
tl_otbn_o.a_user.instr_type[3] Yes Yes T59,T22,T5 Yes T59,T22,T5 OUTPUT
tl_otbn_o.a_user.rsvd[4:0] Unreachable Unreachable Unreachable OUTPUT
tl_otbn_o.a_data[31:0] Yes Yes T59,T22,T5 Yes T59,T22,T5 OUTPUT
tl_otbn_o.a_mask[3:0] Yes Yes T59,T22,T5 Yes T59,T22,T5 OUTPUT
tl_otbn_o.a_address[31:0] Unreachable Unreachable Unreachable OUTPUT
tl_otbn_o.a_source[1:0] Yes Yes *T89,*T165,*T63 Yes T89,T165,T63 OUTPUT
tl_otbn_o.a_source[5:2] No No No OUTPUT
tl_otbn_o.a_source[7:6] Unreachable Unreachable Unreachable OUTPUT
tl_otbn_o.a_size[0] No No No OUTPUT
tl_otbn_o.a_size[1] Yes Yes T59,T22,T5 Yes T59,T22,T5 OUTPUT
tl_otbn_o.a_param[2:0] Unreachable Unreachable Unreachable OUTPUT
tl_otbn_o.a_opcode[1:0] No No No OUTPUT
tl_otbn_o.a_opcode[2] Yes Yes T59,T22,T5 Yes T59,T22,T5 OUTPUT
tl_otbn_o.a_valid Yes Yes T59,T22,T5 Yes T59,T22,T5 OUTPUT
tl_otbn_i.a_ready Yes Yes T59,T22,T5 Yes T59,T22,T5 INPUT
tl_otbn_i.d_error No No No INPUT
tl_otbn_i.d_user.data_intg[6:0] Yes Yes T59,T22,T5 Yes T59,T22,T5 INPUT
tl_otbn_i.d_user.rsp_intg[1:0] Yes Yes T59,T22,T5 Yes T59,T22,T5 INPUT
tl_otbn_i.d_user.rsp_intg[3:2] No No No INPUT
tl_otbn_i.d_user.rsp_intg[5:4] Yes Yes T59,T22,T5 Yes T59,T22,T5 INPUT
tl_otbn_i.d_user.rsp_intg[6] No No No INPUT
tl_otbn_i.d_data[31:0] Yes Yes T59,T22,T5 Yes T59,T22,T5 INPUT
tl_otbn_i.d_sink No No No INPUT
tl_otbn_i.d_source[1:0] Yes Yes *T89,*T165,*T63 Yes T89,T165,T63 INPUT
tl_otbn_i.d_source[5:2] No No No INPUT
tl_otbn_i.d_source[7:6] Unreachable Unreachable Unreachable INPUT
tl_otbn_i.d_size[0] No No No INPUT
tl_otbn_i.d_size[1] Yes Yes T59,T22,T5 Yes T59,T22,T5 INPUT
tl_otbn_i.d_param[2:0] Unreachable Unreachable Unreachable INPUT
tl_otbn_i.d_opcode[0] Yes Yes *T59,*T22,*T5 Yes T59,T22,T5 INPUT
tl_otbn_i.d_opcode[2:1] Unreachable Unreachable Unreachable INPUT
tl_otbn_i.d_valid Yes Yes T59,T22,T5 Yes T59,T22,T5 INPUT
tl_keymgr_o.d_ready Yes Yes T59,T4,T5 Yes T1,T2,T3 OUTPUT
tl_keymgr_o.a_user.data_intg[6:0] Yes Yes T59,T47,T166 Yes T59,T47,T166 OUTPUT
tl_keymgr_o.a_user.cmd_intg[0] Yes Yes *T59,*T47,*T166 Yes T59,T47,T166 OUTPUT
tl_keymgr_o.a_user.cmd_intg[1] No No No OUTPUT
tl_keymgr_o.a_user.cmd_intg[6:2] Yes Yes T59,T47,T166 Yes T59,T47,T166 OUTPUT
tl_keymgr_o.a_user.instr_type[0] Yes Yes *T59,*T47,*T166 Yes T59,T47,T166 OUTPUT
tl_keymgr_o.a_user.instr_type[2:1] No No No OUTPUT
tl_keymgr_o.a_user.instr_type[3] Yes Yes T59,T47,T166 Yes T59,T47,T166 OUTPUT
tl_keymgr_o.a_user.rsvd[4:0] Unreachable Unreachable Unreachable OUTPUT
tl_keymgr_o.a_data[31:0] Yes Yes T47,T166,T167 Yes T47,T166,T167 OUTPUT
tl_keymgr_o.a_mask[3:0] Yes Yes T59,T47,T166 Yes T59,T47,T166 OUTPUT
tl_keymgr_o.a_address[31:0] Unreachable Unreachable Unreachable OUTPUT
tl_keymgr_o.a_source[1:0] Yes Yes *T90,*T59,*T47 Yes T90,T59,T47 OUTPUT
tl_keymgr_o.a_source[5:2] No No No OUTPUT
tl_keymgr_o.a_source[7:6] Unreachable Unreachable Unreachable OUTPUT
tl_keymgr_o.a_size[0] No No No OUTPUT
tl_keymgr_o.a_size[1] Yes Yes T59,T47,T166 Yes T59,T47,T166 OUTPUT
tl_keymgr_o.a_param[2:0] Unreachable Unreachable Unreachable OUTPUT
tl_keymgr_o.a_opcode[1:0] No No No OUTPUT
tl_keymgr_o.a_opcode[2] Yes Yes T59,T47,T166 Yes T59,T47,T166 OUTPUT
tl_keymgr_o.a_valid Yes Yes T59,T47,T166 Yes T59,T47,T166 OUTPUT
tl_keymgr_i.a_ready Yes Yes T59,T47,T166 Yes T59,T47,T166 INPUT
tl_keymgr_i.d_error No No No INPUT
tl_keymgr_i.d_user.data_intg[6:0] Yes Yes T47,T115,T139 Yes T47,T115,T139 INPUT
tl_keymgr_i.d_user.rsp_intg[1:0] Yes Yes T59,T47,T166 Yes T59,T47,T166 INPUT
tl_keymgr_i.d_user.rsp_intg[3:2] No No No INPUT
tl_keymgr_i.d_user.rsp_intg[5:4] Yes Yes T58,T168,*T169 Yes T59,T47,T166 INPUT
tl_keymgr_i.d_user.rsp_intg[6] No No No INPUT
tl_keymgr_i.d_data[31:0] Yes Yes T59,T47,T166 Yes T59,T47,T166 INPUT
tl_keymgr_i.d_sink No No No INPUT
tl_keymgr_i.d_source[1:0] Yes Yes *T90,*T59,*T47 Yes T90,T59,T47 INPUT
tl_keymgr_i.d_source[5:2] No No No INPUT
tl_keymgr_i.d_source[7:6] Unreachable Unreachable Unreachable INPUT
tl_keymgr_i.d_size[0] No No No INPUT
tl_keymgr_i.d_size[1] Yes Yes T58,T168,T169 Yes T59,T47,T166 INPUT
tl_keymgr_i.d_param[2:0] Unreachable Unreachable Unreachable INPUT
tl_keymgr_i.d_opcode[0] Yes Yes *T59,*T47,*T166 Yes T59,T47,T166 INPUT
tl_keymgr_i.d_opcode[2:1] Unreachable Unreachable Unreachable INPUT
tl_keymgr_i.d_valid Yes Yes T59,T47,T166 Yes T59,T47,T166 INPUT
tl_rv_core_ibex__cfg_o.d_ready Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_rv_core_ibex__cfg_o.a_user.data_intg[6:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_rv_core_ibex__cfg_o.a_user.cmd_intg[0] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 OUTPUT
tl_rv_core_ibex__cfg_o.a_user.cmd_intg[1] No No No OUTPUT
tl_rv_core_ibex__cfg_o.a_user.cmd_intg[6:2] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_rv_core_ibex__cfg_o.a_user.instr_type[0] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 OUTPUT
tl_rv_core_ibex__cfg_o.a_user.instr_type[2:1] No No No OUTPUT
tl_rv_core_ibex__cfg_o.a_user.instr_type[3] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_rv_core_ibex__cfg_o.a_user.rsvd[4:0] Unreachable Unreachable Unreachable OUTPUT
tl_rv_core_ibex__cfg_o.a_data[31:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_rv_core_ibex__cfg_o.a_mask[3:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_rv_core_ibex__cfg_o.a_address[31:0] Unreachable Unreachable Unreachable OUTPUT
tl_rv_core_ibex__cfg_o.a_source[1:0] Yes Yes *T15,*T170,*T1 Yes T15,T170,T1 OUTPUT
tl_rv_core_ibex__cfg_o.a_source[5:2] No No No OUTPUT
tl_rv_core_ibex__cfg_o.a_source[7:6] Unreachable Unreachable Unreachable OUTPUT
tl_rv_core_ibex__cfg_o.a_size[0] No No No OUTPUT
tl_rv_core_ibex__cfg_o.a_size[1] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_rv_core_ibex__cfg_o.a_param[2:0] Unreachable Unreachable Unreachable OUTPUT
tl_rv_core_ibex__cfg_o.a_opcode[1:0] No No No OUTPUT
tl_rv_core_ibex__cfg_o.a_opcode[2] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_rv_core_ibex__cfg_o.a_valid Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_rv_core_ibex__cfg_i.a_ready Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_rv_core_ibex__cfg_i.d_error No No No INPUT
tl_rv_core_ibex__cfg_i.d_user.data_intg[6:0] Yes Yes T1,T59,T22 Yes T1,T59,T22 INPUT
tl_rv_core_ibex__cfg_i.d_user.rsp_intg[1:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_rv_core_ibex__cfg_i.d_user.rsp_intg[3:2] No No No INPUT
tl_rv_core_ibex__cfg_i.d_user.rsp_intg[5:4] Yes Yes T4,T5,T6 Yes T1,T2,T3 INPUT
tl_rv_core_ibex__cfg_i.d_user.rsp_intg[6] No No No INPUT
tl_rv_core_ibex__cfg_i.d_data[31:0] Yes Yes T1,T59,T22 Yes T1,T59,T22 INPUT
tl_rv_core_ibex__cfg_i.d_sink No No No INPUT
tl_rv_core_ibex__cfg_i.d_source[0] No No Yes T15,T170 INPUT
tl_rv_core_ibex__cfg_i.d_source[1] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 INPUT
tl_rv_core_ibex__cfg_i.d_source[5:2] No No No INPUT
tl_rv_core_ibex__cfg_i.d_source[7:6] Unreachable Unreachable Unreachable INPUT
tl_rv_core_ibex__cfg_i.d_size[0] No No No INPUT
tl_rv_core_ibex__cfg_i.d_size[1] Yes Yes T4,T5,T6 Yes T1,T2,T3 INPUT
tl_rv_core_ibex__cfg_i.d_param[2:0] Unreachable Unreachable Unreachable INPUT
tl_rv_core_ibex__cfg_i.d_opcode[0] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 INPUT
tl_rv_core_ibex__cfg_i.d_opcode[2:1] Unreachable Unreachable Unreachable INPUT
tl_rv_core_ibex__cfg_i.d_valid Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_sram_ctrl_main__regs_o.d_ready Yes Yes T59,T4,T5 Yes T1,T2,T3 OUTPUT
tl_sram_ctrl_main__regs_o.a_user.data_intg[6:0] Yes Yes T59,T5,T7 Yes T59,T5,T7 OUTPUT
tl_sram_ctrl_main__regs_o.a_user.cmd_intg[0] Yes Yes *T59,*T5,*T7 Yes T59,T5,T7 OUTPUT
tl_sram_ctrl_main__regs_o.a_user.cmd_intg[1] No No No OUTPUT
tl_sram_ctrl_main__regs_o.a_user.cmd_intg[6:2] Yes Yes T171,T172,T116 Yes T171,T172,T116 OUTPUT
tl_sram_ctrl_main__regs_o.a_user.instr_type[0] Yes Yes *T59,*T5,*T7 Yes T59,T5,T7 OUTPUT
tl_sram_ctrl_main__regs_o.a_user.instr_type[2:1] No No No OUTPUT
tl_sram_ctrl_main__regs_o.a_user.instr_type[3] Yes Yes T59,T5,T7 Yes T59,T5,T7 OUTPUT
tl_sram_ctrl_main__regs_o.a_user.rsvd[4:0] Unreachable Unreachable Unreachable OUTPUT
tl_sram_ctrl_main__regs_o.a_data[31:0] Yes Yes T59,T5,T7 Yes T59,T5,T7 OUTPUT
tl_sram_ctrl_main__regs_o.a_mask[3:0] Yes Yes T59,T5,T7 Yes T59,T5,T7 OUTPUT
tl_sram_ctrl_main__regs_o.a_address[31:0] Unreachable Unreachable Unreachable OUTPUT
tl_sram_ctrl_main__regs_o.a_source[1:0] Yes Yes *T14,*T173,*T59 Yes T14,T173,T59 OUTPUT
tl_sram_ctrl_main__regs_o.a_source[5:2] No No No OUTPUT
tl_sram_ctrl_main__regs_o.a_source[7:6] Unreachable Unreachable Unreachable OUTPUT
tl_sram_ctrl_main__regs_o.a_size[0] No No No OUTPUT
tl_sram_ctrl_main__regs_o.a_size[1] Yes Yes T59,T5,T7 Yes T59,T5,T7 OUTPUT
tl_sram_ctrl_main__regs_o.a_param[2:0] Unreachable Unreachable Unreachable OUTPUT
tl_sram_ctrl_main__regs_o.a_opcode[1:0] No No No OUTPUT
tl_sram_ctrl_main__regs_o.a_opcode[2] Yes Yes T171,T172,T116 Yes T171,T172,T116 OUTPUT
tl_sram_ctrl_main__regs_o.a_valid Yes Yes T59,T5,T7 Yes T59,T5,T7 OUTPUT
tl_sram_ctrl_main__regs_i.a_ready Yes Yes T59,T5,T7 Yes T59,T5,T7 INPUT
tl_sram_ctrl_main__regs_i.d_error No No No INPUT
tl_sram_ctrl_main__regs_i.d_user.data_intg[5:0] Yes Yes *T172,*T14,*T174 Yes T172,T14,T174 INPUT
tl_sram_ctrl_main__regs_i.d_user.data_intg[6] No No No INPUT
tl_sram_ctrl_main__regs_i.d_user.rsp_intg[1:0] Yes Yes T5,T7,T58 Yes T59,T5,T7 INPUT
tl_sram_ctrl_main__regs_i.d_user.rsp_intg[3:2] No No No INPUT
tl_sram_ctrl_main__regs_i.d_user.rsp_intg[5:4] Yes Yes *T5,*T7,*T58 Yes T59,T5,T7 INPUT
tl_sram_ctrl_main__regs_i.d_user.rsp_intg[6] No No No INPUT
tl_sram_ctrl_main__regs_i.d_data[31:0] Yes Yes T5,T7,T58 Yes T59,T5,T7 INPUT
tl_sram_ctrl_main__regs_i.d_sink No No No INPUT
tl_sram_ctrl_main__regs_i.d_source[1:0] Yes Yes *T14,*T5,*T7 Yes T14,T173,T59 INPUT
tl_sram_ctrl_main__regs_i.d_source[5:2] No No No INPUT
tl_sram_ctrl_main__regs_i.d_source[7:6] Unreachable Unreachable Unreachable INPUT
tl_sram_ctrl_main__regs_i.d_size[0] No No No INPUT
tl_sram_ctrl_main__regs_i.d_size[1] Yes Yes T5,T7,T58 Yes T59,T5,T7 INPUT
tl_sram_ctrl_main__regs_i.d_param[2:0] Unreachable Unreachable Unreachable INPUT
tl_sram_ctrl_main__regs_i.d_opcode[0] Yes Yes *T171,*T172,*T116 Yes T171,T172,T116 INPUT
tl_sram_ctrl_main__regs_i.d_opcode[2:1] Unreachable Unreachable Unreachable INPUT
tl_sram_ctrl_main__regs_i.d_valid Yes Yes T59,T5,T7 Yes T59,T5,T7 INPUT
tl_sram_ctrl_main__ram_o.d_ready Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_sram_ctrl_main__ram_o.a_user.data_intg[6:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_sram_ctrl_main__ram_o.a_user.cmd_intg[6:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_sram_ctrl_main__ram_o.a_user.instr_type[3:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_sram_ctrl_main__ram_o.a_user.rsvd[4:0] Unreachable Unreachable Unreachable OUTPUT
tl_sram_ctrl_main__ram_o.a_data[31:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_sram_ctrl_main__ram_o.a_mask[3:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_sram_ctrl_main__ram_o.a_address[31:0] Unreachable Unreachable Unreachable OUTPUT
tl_sram_ctrl_main__ram_o.a_source[4:0] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 OUTPUT
tl_sram_ctrl_main__ram_o.a_source[5] No No No OUTPUT
tl_sram_ctrl_main__ram_o.a_source[7:6] Unreachable Unreachable Unreachable OUTPUT
tl_sram_ctrl_main__ram_o.a_size[0] No No No OUTPUT
tl_sram_ctrl_main__ram_o.a_size[1] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_sram_ctrl_main__ram_o.a_param[2:0] Unreachable Unreachable Unreachable OUTPUT
tl_sram_ctrl_main__ram_o.a_opcode[0] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 OUTPUT
tl_sram_ctrl_main__ram_o.a_opcode[1] No No No OUTPUT
tl_sram_ctrl_main__ram_o.a_opcode[2] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_sram_ctrl_main__ram_o.a_valid Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_sram_ctrl_main__ram_i.a_ready Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_sram_ctrl_main__ram_i.d_error Yes Yes T1,T2,T3 Yes T4,T5,T6 INPUT
tl_sram_ctrl_main__ram_i.d_user.data_intg[6:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_sram_ctrl_main__ram_i.d_user.rsp_intg[2:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_sram_ctrl_main__ram_i.d_user.rsp_intg[3] No No No INPUT
tl_sram_ctrl_main__ram_i.d_user.rsp_intg[5:4] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_sram_ctrl_main__ram_i.d_user.rsp_intg[6] No No No INPUT
tl_sram_ctrl_main__ram_i.d_data[31:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_sram_ctrl_main__ram_i.d_sink No No No INPUT
tl_sram_ctrl_main__ram_i.d_source[4:0] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 INPUT
tl_sram_ctrl_main__ram_i.d_source[5] No No No INPUT
tl_sram_ctrl_main__ram_i.d_source[7:6] Unreachable Unreachable Unreachable INPUT
tl_sram_ctrl_main__ram_i.d_size[0] No No No INPUT
tl_sram_ctrl_main__ram_i.d_size[1] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_sram_ctrl_main__ram_i.d_param[2:0] Unreachable Unreachable Unreachable INPUT
tl_sram_ctrl_main__ram_i.d_opcode[0] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 INPUT
tl_sram_ctrl_main__ram_i.d_opcode[2:1] Unreachable Unreachable Unreachable INPUT
tl_sram_ctrl_main__ram_i.d_valid Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
scanmode_i[3:0] Unreachable Unreachable Unreachable INPUT

*Tests covering at least one bit in the range
0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%