Group : tl_agent_pkg::max_outstanding_cg::SHAPE{max_outstanding=3}
dashboard | hierarchy | modlist | groups | tests | asserts

Group : tl_agent_pkg::max_outstanding_cg::SHAPE{max_outstanding=3}
SCOREINSTANCESWEIGHTGOALAT LEASTPER INSTANCEAUTO BIN MAXPRINT MISSING
100.00 100.00 1 100 1 1 64 64


Source File(s) :
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:
NAMESCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_chip_reg_block.cov::m_max_outstanding_cg 100.00 1 100 1 64 64




Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_chip_reg_block.cov::m_max_outstanding_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_chip_reg_block.cov::m_max_outstanding_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 3 0 3 100.00


Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_chip_reg_block.cov::m_max_outstanding_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_num_of_outstanding 3 0 3 100.00 100 1 1 0


Summary for Variable cp_num_of_outstanding

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_num_of_outstanding

Bins
NAME   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
values[1] 38656685 1 T1 352 T2 5223 T3 3993
values[2] 1101084 1 T428 1396 T429 1574 T169 1445
values[3] 38488 1 T169 41 T421 34 T571 2