Unified Coverage Report :: Group :: tl_agent_pkg::max_outstanding_cg::SHAPE{max_outstanding=64}

Group : tl_agent_pkg::max_outstanding_cg::SHAPE{max_outstanding=64}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

3 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_max_outstanding_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_max_outstanding_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_max_outstanding_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_max_outstanding_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_max_outstanding_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	64	0	64	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_max_outstanding_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_of_outstanding	64	0	64	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_max_outstanding_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_max_outstanding_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	64	0	64	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_max_outstanding_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_of_outstanding	64	0	64	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_max_outstanding_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_max_outstanding_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	64	0	64	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_max_outstanding_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_of_outstanding	64	0	64	100.00	100	1	1	0

Summary for Variable cp_num_of_outstanding

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	64	0	64	100.00

User Defined Bins for cp_num_of_outstanding

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[1]	3618702	1			T98	121		T99	98		T100	1249
values[2]	716374	1			T98	66		T99	45		T100	346
values[3]	92869	1			T99	2		T100	13		T161	16
values[4]	50651	1			T161	2		T457	26		T448	40
values[5]	34374	1			T457	31		T448	40		T841	96
values[6]	26430	1			T457	22		T448	56		T841	71
values[7]	21386	1			T457	19		T448	27		T841	52
values[8]	18543	1			T457	34		T448	14		T841	37
values[9]	16267	1			T457	37		T448	12		T841	22
values[10]	15131	1			T457	19		T448	7		T841	35
values[11]	14469	1			T457	29		T448	9		T841	17
values[12]	13631	1			T457	23		T448	5		T841	11
values[13]	13189	1			T457	25		T448	3		T841	6
values[14]	12810	1			T457	34		T448	2		T841	6
values[15]	12385	1			T457	31		T448	4		T841	12
values[16]	11892	1			T457	29		T448	4		T841	15
values[17]	11171	1			T457	16		T448	3		T841	28
values[18]	11095	1			T457	13		T448	4		T841	29
values[19]	10949	1			T457	11		T448	8		T841	16
values[20]	10380	1			T457	3		T448	10		T841	5
values[21]	9751	1			T457	5		T448	11		T841	10
values[22]	9311	1			T457	10		T448	7		T841	4
values[23]	9331	1			T457	12		T448	5		T841	4
values[24]	8812	1			T457	18		T448	6		T841	7
values[25]	8502	1			T457	22		T448	6		T841	4
values[26]	8165	1			T457	19		T448	6		T841	8
values[27]	8076	1			T457	23		T448	6		T841	4
values[28]	7722	1			T457	24		T448	3		T841	8
values[29]	7360	1			T457	17		T448	8		T841	4
values[30]	6807	1			T457	13		T448	5		T841	2
values[31]	6178	1			T457	2		T448	5		T841	5
values[32]	5753	1			T457	4		T448	5		T841	3
values[33]	5247	1			T457	1		T448	3		T841	6
values[34]	4877	1			T457	2		T448	3		T841	4
values[35]	4437	1			T457	3		T448	3		T841	5
values[36]	4182	1			T457	1		T448	4		T841	9
values[37]	3999	1			T457	3		T448	6		T841	8
values[38]	3854	1			T457	2		T448	14		T841	9
values[39]	3560	1			T448	7		T841	4		T562	14
values[40]	3544	1			T448	11		T841	3		T562	18
values[41]	3380	1			T448	5		T841	3		T562	16
values[42]	3260	1			T448	7		T841	7		T562	13
values[43]	3193	1			T448	7		T841	4		T562	12
values[44]	3152	1			T448	7		T841	2		T562	21
values[45]	3134	1			T448	17		T841	2		T562	26
values[46]	3052	1			T448	11		T841	4		T562	22
values[47]	3046	1			T448	3		T841	10		T562	20
values[48]	2928	1			T448	3		T841	4		T562	18
values[49]	2878	1			T448	7		T841	4		T562	18
values[50]	2787	1			T448	3		T841	5		T562	14
values[51]	2795	1			T448	5		T841	2		T562	18
values[52]	2704	1			T448	3		T841	3		T562	19
values[53]	2608	1			T448	8		T841	4		T562	21
values[54]	2583	1			T448	7		T841	7		T562	20
values[55]	2607	1			T448	8		T841	16		T562	22
values[56]	2534	1			T448	6		T841	4		T562	24
values[57]	2398	1			T448	5		T841	10		T562	9
values[58]	2372	1			T448	2		T841	12		T562	13
values[59]	2394	1			T448	2		T841	9		T562	14
values[60]	2406	1			T448	3		T841	12		T562	21
values[61]	2693	1			T448	5		T841	6		T562	25
values[62]	3972	1			T448	7		T841	9		T562	54
values[63]	10698	1			T448	3		T841	47		T562	123
values[64]	236920	1			T448	14		T841	54		T562	296

Summary for Variable cp_num_of_outstanding

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	64	0	64	100.00

User Defined Bins for cp_num_of_outstanding

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[1]	4633802	1			T98	83		T99	91		T100	1222
values[2]	793537	1			T98	22		T99	30		T100	304
values[3]	77509	1			T98	1		T99	2		T100	56
values[4]	14076	1			T100	2		T161	2		T457	1
values[5]	5315	1			T161	1		T477	1		T448	22
values[6]	3129	1			T477	1		T448	24		T559	1
values[7]	2411	1			T448	24		T841	16		T562	8
values[8]	1899	1			T448	21		T841	12		T562	11
values[9]	1637	1			T448	16		T841	4		T562	15
values[10]	1546	1			T448	19		T841	3		T562	21
values[11]	1388	1			T448	15		T841	4		T562	12
values[12]	1361	1			T448	13		T841	4		T562	8
values[13]	1314	1			T448	4		T841	8		T562	4
values[14]	1262	1			T448	13		T841	12		T562	13
values[15]	1117	1			T448	15		T841	4		T562	7
values[16]	944	1			T448	6		T841	5		T562	3
values[17]	918	1			T448	11		T841	1		T562	3
values[18]	927	1			T448	19		T841	1		T562	1
values[19]	900	1			T448	21		T841	1		T562	1
values[20]	792	1			T448	9		T841	4		T562	1
values[21]	802	1			T448	19		T841	3		T562	3
values[22]	814	1			T448	24		T841	3		T562	1
values[23]	732	1			T448	9		T841	3		T562	2
values[24]	710	1			T448	9		T841	7		T562	3
values[25]	687	1			T448	7		T841	5		T562	1
values[26]	609	1			T448	14		T562	2		T653	7
values[27]	642	1			T448	10		T562	2		T653	10
values[28]	605	1			T448	19		T562	1		T653	9
values[29]	604	1			T448	14		T562	1		T653	2
values[30]	587	1			T448	8		T562	2		T653	7
values[31]	632	1			T448	31		T562	2		T653	12
values[32]	587	1			T448	28		T562	1		T653	15
values[33]	522	1			T448	21		T562	1		T653	5
values[34]	484	1			T448	4		T562	1		T653	1
values[35]	504	1			T448	1		T562	3		T653	1
values[36]	438	1			T562	2		T653	1		T594	2
values[37]	445	1			T562	2		T653	2		T594	3
values[38]	458	1			T562	2		T653	1		T594	1
values[39]	410	1			T562	4		T594	1		T596	3
values[40]	415	1			T562	7		T594	1		T596	1
values[41]	416	1			T562	5		T594	1		T596	1
values[42]	384	1			T562	1		T594	6		T596	1
values[43]	429	1			T562	1		T594	6		T596	1
values[44]	395	1			T562	1		T594	2		T596	2
values[45]	399	1			T562	4		T594	2		T596	1
values[46]	395	1			T562	2		T594	1		T596	1
values[47]	403	1			T562	2		T594	6		T596	1
values[48]	451	1			T562	8		T594	6		T596	1
values[49]	388	1			T562	3		T594	3		T596	2
values[50]	364	1			T562	3		T594	4		T596	2
values[51]	369	1			T562	2		T596	6		T497	4
values[52]	344	1			T562	2		T596	2		T497	4
values[53]	374	1			T562	2		T596	1		T497	4
values[54]	363	1			T562	3		T596	1		T497	4
values[55]	373	1			T562	10		T596	1		T497	3
values[56]	359	1			T562	7		T596	1		T497	3
values[57]	360	1			T562	3		T596	1		T497	4
values[58]	363	1			T562	2		T596	1		T497	4
values[59]	346	1			T562	1		T596	1		T497	4
values[60]	326	1			T562	2		T596	1		T497	5
values[61]	368	1			T562	1		T596	1		T497	4
values[62]	641	1			T562	3		T596	2		T497	4
values[63]	2348	1			T562	29		T596	9		T497	6
values[64]	26747	1			T562	74		T596	102		T497	249

Summary for Variable cp_num_of_outstanding

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	64	0	64	100.00

User Defined Bins for cp_num_of_outstanding

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[1]	527371	1			T98	1		T99	2		T100	15
values[2]	2685198	1			T98	116		T99	65		T100	519
values[3]	1073537	1			T98	79		T99	44		T100	1004
values[4]	127993	1			T99	1		T100	39		T161	33
values[5]	64875	1			T161	4		T457	26		T477	1
values[6]	43220	1			T457	25		T448	65		T841	124
values[7]	32235	1			T457	19		T448	44		T841	106
values[8]	26434	1			T457	25		T448	35		T841	103
values[9]	22763	1			T457	42		T448	33		T841	60
values[10]	20008	1			T457	25		T448	36		T841	46
values[11]	17963	1			T457	19		T448	26		T841	35
values[12]	16724	1			T457	27		T448	20		T841	28
values[13]	15984	1			T457	20		T448	17		T841	31
values[14]	15202	1			T457	35		T448	3		T841	39
values[15]	14291	1			T457	16		T448	6		T841	38
values[16]	13988	1			T457	14		T448	9		T841	29
values[17]	13587	1			T457	26		T448	9		T841	19
values[18]	12914	1			T457	43		T448	10		T841	11
values[19]	12638	1			T457	21		T448	10		T841	20
values[20]	11948	1			T457	28		T448	7		T841	13
values[21]	11558	1			T457	26		T448	9		T841	14
values[22]	11087	1			T457	21		T448	12		T841	8
values[23]	10564	1			T457	28		T448	11		T841	5
values[24]	10178	1			T457	18		T448	8		T841	7
values[25]	9682	1			T457	10		T448	3		T841	2
values[26]	9277	1			T457	11		T448	5		T841	1
values[27]	8818	1			T457	12		T448	10		T841	3
values[28]	8262	1			T457	5		T448	6		T841	4
values[29]	7818	1			T457	8		T448	15		T841	1
values[30]	7458	1			T457	5		T448	12		T841	1
values[31]	6754	1			T457	8		T448	11		T841	1
values[32]	6365	1			T457	11		T448	8		T841	1
values[33]	5700	1			T457	14		T448	12		T841	3
values[34]	5261	1			T457	1		T448	6		T841	6
values[35]	4916	1			T457	2		T448	13		T841	3
values[36]	4517	1			T457	5		T448	17		T841	3
values[37]	4327	1			T457	8		T448	9		T841	4
values[38]	4143	1			T448	17		T841	1		T562	7
values[39]	3998	1			T448	22		T841	5		T562	6
values[40]	3783	1			T448	17		T841	1		T562	6
values[41]	3554	1			T448	8		T841	4		T562	13
values[42]	3585	1			T448	10		T841	5		T562	17
values[43]	3381	1			T448	4		T841	6		T562	16
values[44]	3315	1			T448	8		T841	4		T562	15
values[45]	3262	1			T448	7		T841	2		T562	15
values[46]	3185	1			T448	7		T841	9		T562	12
values[47]	3184	1			T448	11		T841	4		T562	15
values[48]	3161	1			T448	6		T841	3		T562	12
values[49]	3115	1			T448	6		T841	1		T562	15
values[50]	3114	1			T448	5		T841	1		T562	19
values[51]	3147	1			T448	17		T841	2		T562	15
values[52]	3096	1			T448	17		T841	1		T562	8
values[53]	2988	1			T448	13		T841	1		T562	10
values[54]	2902	1			T448	4		T841	1		T562	10
values[55]	2883	1			T448	4		T841	1		T562	7
values[56]	2796	1			T448	6		T841	1		T562	5
values[57]	2761	1			T448	11		T841	7		T562	7
values[58]	2674	1			T448	18		T841	1		T562	9
values[59]	2714	1			T448	8		T841	1		T562	8
values[60]	2602	1			T448	3		T841	1		T562	14
values[61]	2749	1			T448	2		T841	2		T562	8
values[62]	3537	1			T841	3		T562	17		T653	22
values[63]	8710	1			T841	25		T562	62		T653	68
values[64]	229429	1			T841	45		T562	203		T653	261