Unified Coverage Report :: Group :: tl_agent_pkg::max_outstanding_cg::SHAPE{max_outstanding=64}

Group : tl_agent_pkg::max_outstanding_cg::SHAPE{max_outstanding=64}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

3 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_max_outstanding_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_max_outstanding_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_max_outstanding_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_max_outstanding_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_max_outstanding_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	64	0	64	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_max_outstanding_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_of_outstanding	64	0	64	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_max_outstanding_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_max_outstanding_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	64	0	64	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_max_outstanding_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_of_outstanding	64	0	64	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_max_outstanding_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_max_outstanding_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	64	0	64	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_max_outstanding_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_of_outstanding	64	0	64	100.00	100	1	1	0

Summary for Variable cp_num_of_outstanding

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	64	0	64	100.00

User Defined Bins for cp_num_of_outstanding

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[1]	3638477	1			T94	71		T95	83		T96	691
values[2]	740830	1			T94	30		T95	46		T96	169
values[3]	116292	1			T96	2		T248	1		T278	3
values[4]	65613	1			T278	2		T451	3		T450	328
values[5]	43078	1			T450	210		T446	90		T543	226
values[6]	31235	1			T450	116		T446	63		T543	135
values[7]	24648	1			T450	67		T446	65		T543	105
values[8]	20316	1			T450	45		T446	40		T543	83
values[9]	17739	1			T450	45		T446	35		T543	90
values[10]	16326	1			T450	60		T446	18		T543	60
values[11]	14945	1			T450	46		T446	17		T543	65
values[12]	13598	1			T450	55		T446	10		T543	69
values[13]	12880	1			T450	49		T446	13		T543	43
values[14]	12350	1			T450	14		T446	7		T543	41
values[15]	11883	1			T450	14		T446	5		T543	43
values[16]	11123	1			T450	15		T446	6		T543	46
values[17]	9944	1			T450	9		T446	7		T543	45
values[18]	9713	1			T450	13		T446	12		T543	41
values[19]	9451	1			T450	22		T446	7		T543	40
values[20]	9362	1			T450	19		T446	22		T543	40
values[21]	9055	1			T450	19		T446	20		T543	19
values[22]	8584	1			T450	19		T446	15		T543	24
values[23]	8304	1			T450	19		T446	12		T543	35
values[24]	8021	1			T450	9		T446	6		T543	30
values[25]	7882	1			T450	13		T446	9		T543	32
values[26]	7702	1			T450	11		T446	12		T543	36
values[27]	7053	1			T450	6		T446	7		T543	27
values[28]	6532	1			T450	7		T446	11		T543	22
values[29]	6450	1			T450	6		T446	11		T543	23
values[30]	5868	1			T450	11		T446	8		T543	19
values[31]	5328	1			T450	9		T446	11		T543	14
values[32]	5108	1			T450	5		T446	4		T543	16
values[33]	4856	1			T450	5		T446	3		T543	25
values[34]	4492	1			T450	8		T446	7		T543	14
values[35]	4086	1			T450	7		T446	6		T543	24
values[36]	3875	1			T450	10		T446	9		T543	32
values[37]	3804	1			T450	3		T446	8		T543	32
values[38]	3561	1			T450	5		T446	14		T543	21
values[39]	3264	1			T450	8		T446	9		T543	15
values[40]	3199	1			T450	11		T446	10		T543	15
values[41]	3213	1			T450	11		T446	13		T543	14
values[42]	3106	1			T450	8		T446	5		T543	22
values[43]	3042	1			T450	12		T446	6		T543	17
values[44]	2886	1			T450	7		T446	8		T543	18
values[45]	2948	1			T450	8		T446	8		T543	15
values[46]	2770	1			T450	8		T446	11		T543	12
values[47]	2665	1			T450	13		T446	12		T543	11
values[48]	2618	1			T450	9		T446	13		T543	18
values[49]	2706	1			T450	7		T446	13		T543	18
values[50]	2621	1			T450	7		T446	9		T543	15
values[51]	2556	1			T450	11		T446	5		T543	15
values[52]	2476	1			T450	8		T446	6		T543	14
values[53]	2325	1			T450	16		T446	4		T543	14
values[54]	2393	1			T450	11		T446	3		T543	16
values[55]	2266	1			T450	9		T446	4		T543	18
values[56]	2325	1			T450	16		T446	5		T543	24
values[57]	2274	1			T450	10		T446	5		T543	18
values[58]	2338	1			T450	7		T446	10		T543	17
values[59]	2253	1			T450	4		T446	12		T543	21
values[60]	2259	1			T450	5		T446	8		T543	18
values[61]	2420	1			T450	4		T446	6		T543	21
values[62]	3937	1			T450	21		T446	8		T543	44
values[63]	11856	1			T450	78		T446	11		T543	167
values[64]	151084	1			T450	188		T446	59		T543	419

Summary for Variable cp_num_of_outstanding

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	64	0	64	100.00

User Defined Bins for cp_num_of_outstanding

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[1]	4629033	1			T94	151		T95	143		T96	758
values[2]	778340	1			T94	39		T95	55		T96	187
values[3]	78460	1			T94	1		T95	2		T96	3
values[4]	12618	1			T451	2		T450	10		T544	2
values[5]	4938	1			T451	1		T447	1		T446	1
values[6]	3363	1			T543	8		T841	1		T600	6
values[7]	2832	1			T543	5		T600	3		T612	5
values[8]	2457	1			T543	15		T600	4		T612	1
values[9]	2203	1			T543	15		T600	13		T612	1
values[10]	2054	1			T543	14		T600	29		T641	1
values[11]	1757	1			T543	6		T600	20		T641	3
values[12]	1574	1			T543	5		T600	26		T641	4
values[13]	1442	1			T543	4		T600	21		T641	14
values[14]	1352	1			T543	6		T600	24		T641	20
values[15]	1270	1			T543	7		T600	15		T641	11
values[16]	1257	1			T543	7		T600	12		T641	7
values[17]	1245	1			T543	5		T600	17		T641	8
values[18]	1185	1			T543	4		T600	33		T641	7
values[19]	1072	1			T543	2		T600	23		T641	7
values[20]	991	1			T543	5		T600	13		T641	12
values[21]	898	1			T543	7		T600	3		T641	1
values[22]	845	1			T543	16		T600	1		T641	2
values[23]	819	1			T543	17		T600	4		T641	7
values[24]	865	1			T543	14		T600	5		T641	4
values[25]	744	1			T543	6		T600	2		T641	2
values[26]	775	1			T543	9		T600	3		T641	2
values[27]	801	1			T543	3		T600	8		T641	1
values[28]	664	1			T543	3		T600	3		T641	3
values[29]	658	1			T543	2		T600	1		T641	7
values[30]	603	1			T543	2		T600	1		T641	6
values[31]	591	1			T543	3		T600	2		T641	1
values[32]	557	1			T543	3		T600	1		T783	2
values[33]	545	1			T543	3		T600	5		T783	2
values[34]	486	1			T543	10		T600	6		T783	5
values[35]	532	1			T543	6		T600	13		T783	4
values[36]	517	1			T543	4		T600	7		T783	8
values[37]	517	1			T543	2		T600	12		T783	6
values[38]	538	1			T543	2		T600	7		T783	8
values[39]	500	1			T543	2		T600	8		T783	6
values[40]	519	1			T543	2		T600	4		T783	5
values[41]	475	1			T543	2		T600	4		T783	10
values[42]	510	1			T543	5		T600	12		T783	8
values[43]	499	1			T543	5		T600	10		T783	9
values[44]	507	1			T543	6		T600	9		T783	8
values[45]	473	1			T543	11		T783	3		T455	2
values[46]	489	1			T543	9		T783	3		T455	3
values[47]	436	1			T543	12		T783	5		T455	2
values[48]	464	1			T543	7		T783	4		T455	3
values[49]	458	1			T543	10		T783	9		T455	2
values[50]	456	1			T543	8		T783	8		T455	5
values[51]	460	1			T543	4		T783	6		T455	2
values[52]	394	1			T543	8		T783	3		T455	4
values[53]	418	1			T543	6		T783	6		T455	2
values[54]	428	1			T543	3		T783	3		T455	4
values[55]	409	1			T543	4		T783	3		T455	4
values[56]	432	1			T543	3		T783	6		T455	3
values[57]	411	1			T543	2		T783	5		T455	3
values[58]	387	1			T543	9		T783	8		T455	2
values[59]	376	1			T543	7		T783	4		T455	4
values[60]	416	1			T543	5		T783	2		T455	10
values[61]	485	1			T543	3		T783	5		T455	12
values[62]	789	1			T543	6		T783	10		T455	13
values[63]	3193	1			T543	26		T783	26		T455	49
values[64]	21849	1			T543	137		T783	54		T455	155

Summary for Variable cp_num_of_outstanding

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	64	0	64	100.00

User Defined Bins for cp_num_of_outstanding

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[1]	540206	1			T94	1		T95	1		T96	6
values[2]	2578797	1			T94	132		T95	91		T96	625
values[3]	1152642	1			T94	63		T95	50		T96	186
values[4]	168739	1			T278	3		T279	1		T280	1
values[5]	92578	1			T450	398		T447	2		T446	164
values[6]	59978	1			T450	210		T446	136		T543	289
values[7]	42394	1			T450	99		T446	92		T543	168
values[8]	32331	1			T450	65		T446	40		T543	136
values[9]	26430	1			T450	56		T446	20		T543	124
values[10]	22331	1			T450	54		T446	10		T543	69
values[11]	20144	1			T450	42		T446	16		T543	65
values[12]	18225	1			T450	44		T446	9		T543	88
values[13]	16869	1			T450	40		T446	8		T543	68
values[14]	15304	1			T450	34		T446	11		T543	74
values[15]	14717	1			T450	27		T446	23		T543	66
values[16]	13719	1			T450	24		T446	19		T543	52
values[17]	13224	1			T450	30		T446	11		T543	44
values[18]	12699	1			T450	22		T446	11		T543	48
values[19]	12334	1			T450	13		T446	19		T543	45
values[20]	11423	1			T450	9		T446	10		T543	38
values[21]	10972	1			T450	5		T446	13		T543	55
values[22]	10828	1			T450	13		T446	5		T543	38
values[23]	10115	1			T450	7		T446	8		T543	34
values[24]	9780	1			T450	14		T446	7		T543	32
values[25]	9355	1			T450	12		T446	8		T543	17
values[26]	8765	1			T450	10		T446	7		T543	20
values[27]	8194	1			T450	7		T446	6		T543	25
values[28]	7531	1			T450	7		T446	7		T543	26
values[29]	7289	1			T450	5		T446	11		T543	33
values[30]	6755	1			T450	8		T446	12		T543	30
values[31]	6011	1			T450	20		T446	16		T543	27
values[32]	5776	1			T450	17		T446	17		T543	26
values[33]	5593	1			T450	9		T446	10		T543	22
values[34]	5205	1			T450	13		T446	10		T543	31
values[35]	4767	1			T450	10		T446	13		T543	37
values[36]	4350	1			T450	11		T446	7		T543	41
values[37]	4236	1			T450	9		T446	6		T543	35
values[38]	4002	1			T450	11		T446	22		T543	39
values[39]	3832	1			T450	8		T446	16		T543	34
values[40]	3643	1			T450	4		T446	9		T543	26
values[41]	3474	1			T450	12		T446	7		T543	25
values[42]	3312	1			T450	6		T446	14		T543	32
values[43]	3390	1			T450	3		T446	22		T543	29
values[44]	3325	1			T450	4		T446	8		T543	38
values[45]	3218	1			T450	7		T446	2		T543	38
values[46]	3021	1			T450	7		T446	3		T543	22
values[47]	2975	1			T450	7		T446	9		T543	19
values[48]	2954	1			T450	6		T446	6		T543	28
values[49]	2989	1			T450	8		T446	6		T543	29
values[50]	3034	1			T450	12		T446	17		T543	23
values[51]	2911	1			T450	15		T446	7		T543	27
values[52]	2898	1			T450	15		T446	3		T543	14
values[53]	2806	1			T450	13		T446	11		T543	16
values[54]	2774	1			T450	9		T446	10		T543	16
values[55]	2683	1			T450	6		T446	10		T543	22
values[56]	2666	1			T450	11		T446	4		T543	29
values[57]	2583	1			T450	6		T446	9		T543	18
values[58]	2556	1			T450	4		T446	3		T543	20
values[59]	2540	1			T450	4		T446	5		T543	22
values[60]	2524	1			T450	10		T446	5		T543	15
values[61]	2656	1			T450	5		T446	5		T543	16
values[62]	3701	1			T450	12		T446	7		T543	41
values[63]	10203	1			T450	62		T446	6		T543	135
values[64]	145008	1			T450	120		T446	102		T543	237