Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=32}
dashboard | hierarchy | modlist | groups | tests | asserts

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=32}
SCOREINSTANCESWEIGHTGOALAT LEASTPER INSTANCEAUTO BIN MAXPRINT MISSING
100.00 100.00 1 100 1 1 64 64


Source File(s) :
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

4 Instances:
NAMESCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_chip_reg_block.cov::m_tl_a_chan_cov_cg 100.00 1 100 1 64 64
tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg 100.00 1 100 1 64 64
tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg 100.00 1 100 1 64 64
tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg 100.00 1 100 1 64 64



Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_chip_reg_block.cov::m_tl_a_chan_cov_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64



Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_chip_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY   EXPECTED   UNCOVERED   COVERED   PERCENT   
Variables 38 0 38 100.00
Crosses 3 0 3 100.00


Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_chip_reg_block.cov::m_tl_a_chan_cov_cg
VARIABLE   EXPECTED   UNCOVERED   COVERED   PERCENT   GOAL   WEIGHT   AT LEAST   AUTO BIN MAX   COMMENT   
cp_mask 1 0 1 100.00 100 1 1 0
cp_opcode 3 0 3 100.00 100 1 1 0
cp_size 1 0 1 100.00 100 1 1 0
cp_source 33 0 33 100.00 100 1 1 0


Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_chip_reg_block.cov::m_tl_a_chan_cov_cg
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
tl_a_chan_cov_cg_cc 3 0 3 100.00 100 1 1 0


Group Instance : tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64



Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

CATEGORY   EXPECTED   UNCOVERED   COVERED   PERCENT   
Variables 38 0 38 100.00
Crosses 3 0 3 100.00


Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg
VARIABLE   EXPECTED   UNCOVERED   COVERED   PERCENT   GOAL   WEIGHT   AT LEAST   AUTO BIN MAX   COMMENT   
cp_mask 1 0 1 100.00 100 1 1 0
cp_opcode 3 0 3 100.00 100 1 1 0
cp_size 1 0 1 100.00 100 1 1 0
cp_source 33 0 33 100.00 100 1 1 0


Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
tl_a_chan_cov_cg_cc 3 0 3 100.00 100 1 1 0


Group Instance : tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64



Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

CATEGORY   EXPECTED   UNCOVERED   COVERED   PERCENT   
Variables 38 0 38 100.00
Crosses 3 0 3 100.00


Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg
VARIABLE   EXPECTED   UNCOVERED   COVERED   PERCENT   GOAL   WEIGHT   AT LEAST   AUTO BIN MAX   COMMENT   
cp_mask 1 0 1 100.00 100 1 1 0
cp_opcode 3 0 3 100.00 100 1 1 0
cp_size 1 0 1 100.00 100 1 1 0
cp_source 33 0 33 100.00 100 1 1 0


Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
tl_a_chan_cov_cg_cc 3 0 3 100.00 100 1 1 0


Group Instance : tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64



Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

CATEGORY   EXPECTED   UNCOVERED   COVERED   PERCENT   
Variables 38 0 38 100.00
Crosses 3 0 3 100.00


Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg
VARIABLE   EXPECTED   UNCOVERED   COVERED   PERCENT   GOAL   WEIGHT   AT LEAST   AUTO BIN MAX   COMMENT   
cp_mask 1 0 1 100.00 100 1 1 0
cp_opcode 3 0 3 100.00 100 1 1 0
cp_size 1 0 1 100.00 100 1 1 0
cp_source 33 0 33 100.00 100 1 1 0


Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
tl_a_chan_cov_cg_cc 3 0 3 100.00 100 1 1 0


Summary for Variable cp_mask

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for cp_mask

Excluded/Illegal bins
NAMECOUNTSTATUS
others 1894656 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_enables 37746997 1 T1 349 T2 4965 T3 3832


Summary for Variable cp_opcode

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_opcode

Bins
NAME   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
values[0x4] 27480792 1 T1 175 T2 1762 T3 1057
values[0x0] 10653491 1 T1 174 T2 3203 T3 2775
values[0x1] 1507370 1 T1 3 T2 258 T3 161


Summary for Variable cp_size

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for cp_size

Excluded/Illegal bins
NAMECOUNTSTATUS
others 569563 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
biggest_size 39072090 1 T1 352 T2 5223 T3 3993


Summary for Variable cp_source

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 33 0 33 100.00


User Defined Bins for cp_source

Bins
NAME   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
valid_sources[0x00] 18717146 1 T1 176 T2 2612 T3 1997
valid_sources[0x01] 18715829 1 T1 176 T2 2611 T3 1996
valid_sources[0x02] 35629 1 T230 1 T428 13 T900 11
valid_sources[0x03] 34777 1 T230 2 T428 12 T900 7
valid_sources[0x04] 36190 1 T101 2 T428 10 T900 5
valid_sources[0x05] 35674 1 T101 2 T428 9 T900 6
valid_sources[0x06] 35438 1 T428 13 T900 13 T429 5
valid_sources[0x07] 35456 1 T101 2 T428 18 T900 10
valid_sources[0x08] 35741 1 T428 7 T900 13 T169 72
valid_sources[0x09] 35830 1 T428 12 T900 14 T429 5
valid_sources[0x0a] 35588 1 T101 1 T428 8 T900 9
valid_sources[0x0b] 35335 1 T101 1 T428 20 T900 11
valid_sources[0x0c] 35989 1 T428 10 T900 8 T429 36
valid_sources[0x0d] 36390 1 T428 12 T900 11 T429 12
valid_sources[0x0e] 35039 1 T101 2 T230 1 T428 11
valid_sources[0x0f] 35206 1 T230 3 T428 9 T900 11
valid_sources[0x10] 35707 1 T428 19 T900 6 T169 87
valid_sources[0x11] 34559 1 T428 7 T900 4 T429 1
valid_sources[0x12] 35522 1 T101 1 T428 7 T900 15
valid_sources[0x13] 35683 1 T428 9 T900 18 T429 10
valid_sources[0x14] 35514 1 T428 11 T900 13 T429 8
valid_sources[0x15] 34678 1 T101 2 T428 15 T900 19
valid_sources[0x16] 35257 1 T101 1 T230 4 T428 6
valid_sources[0x17] 36583 1 T230 3 T428 11 T900 3
valid_sources[0x18] 35201 1 T101 1 T428 9 T900 16
valid_sources[0x19] 35043 1 T428 3 T900 12 T429 19
valid_sources[0x1a] 36047 1 T101 2 T428 10 T900 11
valid_sources[0x1b] 36095 1 T45 39 T101 2 T230 1
valid_sources[0x1c] 35899 1 T101 1 T428 6 T900 13
valid_sources[0x1d] 36105 1 T101 1 T428 14 T900 9
valid_sources[0x1e] 35609 1 T101 1 T428 12 T900 19
valid_sources[0x1f] 42964 1 T230 4 T428 9 T900 26
valid_sources[0x20] 35299 1 T230 1 T428 11 T900 10


Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 3 0 3 100.00


Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins
cp_opcode   cp_mask   cp_size   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
values[0x4] all_enables biggest_size 26866589 1 T1 175 T2 1762 T3 1057
values[0x0] all_enables biggest_size 10599350 1 T1 174 T2 3203 T3 2775
values[0x1] all_enables biggest_size 281058 1 T30 23 T45 21 T101 20


Summary for Variable cp_mask

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for cp_mask

Excluded/Illegal bins
NAMECOUNTSTATUS
others 2789079 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_enables 439790 1 T98 29 T99 27 T100 245


Summary for Variable cp_opcode

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_opcode

Bins
NAME   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
values[0x4] 1093501 1 T98 67 T99 42 T100 542
values[0x0] 1041993 1 T98 56 T99 54 T100 543
values[0x1] 1093375 1 T98 64 T99 49 T100 523


Summary for Variable cp_size

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for cp_size

Excluded/Illegal bins
NAMECOUNTSTATUS
others 2160822 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
biggest_size 1068047 1 T98 74 T99 60 T100 537


Summary for Variable cp_source

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 33 0 33 100.00


User Defined Bins for cp_source

Bins
NAME   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
valid_sources[0x00] 50910 1 T98 3 T100 3 T161 1
valid_sources[0x01] 50613 1 T98 1 T99 13 T100 21
valid_sources[0x02] 50460 1 T98 1 T99 13 T100 18
valid_sources[0x03] 49734 1 T98 3 T99 2 T100 45
valid_sources[0x04] 49682 1 T98 6 T99 5 T100 55
valid_sources[0x05] 50163 1 T98 3 T99 2 T100 36
valid_sources[0x06] 50755 1 T98 3 T100 20 T161 3
valid_sources[0x07] 50325 1 T98 3 T99 2 T100 19
valid_sources[0x08] 49968 1 T98 1 T100 39 T161 3
valid_sources[0x09] 50172 1 T98 4 T99 2 T100 25
valid_sources[0x0a] 51072 1 T98 2 T99 3 T100 27
valid_sources[0x0b] 49639 1 T98 1 T99 5 T100 28
valid_sources[0x0c] 49936 1 T98 3 T99 7 T100 24
valid_sources[0x0d] 50085 1 T98 2 T100 21 T161 1
valid_sources[0x0e] 50353 1 T99 5 T100 33 T161 2
valid_sources[0x0f] 51438 1 T98 3 T100 46 T161 1
valid_sources[0x10] 50791 1 T100 43 T185 26 T457 96
valid_sources[0x11] 49850 1 T99 1 T100 9 T185 36
valid_sources[0x12] 49947 1 T98 2 T99 2 T100 23
valid_sources[0x13] 50114 1 T98 4 T99 8 T100 17
valid_sources[0x14] 49670 1 T98 6 T99 1 T100 8
valid_sources[0x15] 51864 1 T98 2 T99 2 T100 27
valid_sources[0x16] 51102 1 T98 3 T100 16 T161 7
valid_sources[0x17] 49945 1 T98 6 T100 30 T161 1
valid_sources[0x18] 49113 1 T98 4 T99 1 T100 28
valid_sources[0x19] 49934 1 T99 2 T100 23 T161 5
valid_sources[0x1a] 50314 1 T99 1 T100 28 T161 2
valid_sources[0x1b] 50354 1 T98 4 T100 33 T161 1
valid_sources[0x1c] 50920 1 T98 8 T100 21 T161 1
valid_sources[0x1d] 50128 1 T98 5 T99 3 T100 13
valid_sources[0x1e] 50773 1 T98 4 T100 24 T185 9
valid_sources[0x1f] 50870 1 T98 2 T99 4 T100 39
valid_sources[0x20] 50583 1 T98 7 T100 39 T185 20


Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 3 0 3 100.00


Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins
cp_opcode   cp_mask   cp_size   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
values[0x4] all_enables biggest_size 46165 1 T98 4 T99 2 T100 20
values[0x0] all_enables biggest_size 347532 1 T98 22 T99 22 T100 203
values[0x1] all_enables biggest_size 46093 1 T98 3 T99 3 T100 22


Summary for Variable cp_mask

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for cp_mask

Excluded/Illegal bins
NAMECOUNTSTATUS
others 2977816 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_enables 484290 1 T98 10 T99 20 T100 225


Summary for Variable cp_opcode

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_opcode

Bins
NAME   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
values[0x4] 1183822 1 T98 46 T99 42 T100 517
values[0x0] 1093218 1 T98 26 T99 33 T100 558
values[0x1] 1185066 1 T98 34 T99 48 T100 509


Summary for Variable cp_size

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for cp_size

Excluded/Illegal bins
NAMECOUNTSTATUS
others 2287019 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
biggest_size 1175087 1 T98 37 T99 42 T100 518


Summary for Variable cp_source

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 33 0 33 100.00


User Defined Bins for cp_source

Bins
NAME   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
valid_sources[0x00] 54085 1 T99 3 T100 23 T185 30
valid_sources[0x01] 54092 1 T100 16 T161 4 T185 25
valid_sources[0x02] 54351 1 T98 4 T99 3 T100 15
valid_sources[0x03] 54820 1 T100 40 T185 25 T457 44
valid_sources[0x04] 53992 1 T100 17 T161 10 T185 43
valid_sources[0x05] 53459 1 T99 3 T100 20 T185 32
valid_sources[0x06] 54329 1 T99 1 T100 28 T185 35
valid_sources[0x07] 53977 1 T98 2 T99 4 T100 24
valid_sources[0x08] 53976 1 T99 1 T100 24 T185 41
valid_sources[0x09] 53321 1 T100 24 T185 20 T457 23
valid_sources[0x0a] 53974 1 T98 2 T99 1 T100 18
valid_sources[0x0b] 53729 1 T99 5 T100 27 T161 2
valid_sources[0x0c] 53898 1 T99 2 T100 36 T185 33
valid_sources[0x0d] 53004 1 T99 2 T100 10 T161 3
valid_sources[0x0e] 53308 1 T99 12 T100 18 T161 2
valid_sources[0x0f] 54337 1 T99 4 T100 24 T185 44
valid_sources[0x10] 53677 1 T99 2 T100 15 T185 29
valid_sources[0x11] 54185 1 T100 20 T161 3 T185 30
valid_sources[0x12] 53525 1 T98 9 T99 2 T100 26
valid_sources[0x13] 54128 1 T98 1 T99 2 T100 18
valid_sources[0x14] 52670 1 T99 4 T100 26 T161 10
valid_sources[0x15] 54832 1 T98 4 T100 32 T185 35
valid_sources[0x16] 54782 1 T98 6 T99 2 T100 25
valid_sources[0x17] 54182 1 T100 17 T185 13 T281 2
valid_sources[0x18] 53309 1 T99 3 T100 14 T185 31
valid_sources[0x19] 54223 1 T100 28 T161 5 T185 30
valid_sources[0x1a] 54175 1 T99 3 T100 10 T185 30
valid_sources[0x1b] 54539 1 T100 56 T185 35 T457 30
valid_sources[0x1c] 54308 1 T100 30 T185 32 T457 24
valid_sources[0x1d] 53992 1 T99 1 T100 25 T185 44
valid_sources[0x1e] 55280 1 T99 7 T100 34 T185 42
valid_sources[0x1f] 54021 1 T99 2 T100 23 T161 6
valid_sources[0x20] 54475 1 T100 30 T185 24 T457 19


Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 3 0 3 100.00


Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins
cp_opcode   cp_mask   cp_size   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
values[0x4] all_enables biggest_size 50797 1 T98 1 T99 1 T100 17
values[0x0] all_enables biggest_size 382810 1 T98 7 T99 13 T100 181
values[0x1] all_enables biggest_size 50683 1 T98 2 T99 6 T100 27


Summary for Variable cp_mask

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for cp_mask

Excluded/Illegal bins
NAMECOUNTSTATUS
others 2810517 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_enables 444539 1 T98 23 T99 11 T100 221


Summary for Variable cp_opcode

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_opcode

Bins
NAME   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
values[0x4] 1101601 1 T98 63 T99 33 T100 519
values[0x0] 1050335 1 T98 56 T99 42 T100 520
values[0x1] 1103120 1 T98 77 T99 37 T100 538


Summary for Variable cp_size

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for cp_size

Excluded/Illegal bins
NAMECOUNTSTATUS
others 2177290 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
biggest_size 1077766 1 T98 67 T99 36 T100 528


Summary for Variable cp_source

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 33 0 33 100.00


User Defined Bins for cp_source

Bins
NAME   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
valid_sources[0x00] 50069 1 T99 1 T100 29 T161 1
valid_sources[0x01] 50978 1 T99 2 T100 19 T185 37
valid_sources[0x02] 50680 1 T99 1 T100 13 T161 5
valid_sources[0x03] 50428 1 T99 2 T100 13 T161 4
valid_sources[0x04] 51435 1 T98 6 T99 8 T100 38
valid_sources[0x05] 49635 1 T98 2 T99 1 T100 16
valid_sources[0x06] 51142 1 T99 3 T100 39 T185 31
valid_sources[0x07] 49943 1 T98 4 T99 5 T100 20
valid_sources[0x08] 50119 1 T99 3 T100 15 T161 1
valid_sources[0x09] 50191 1 T99 2 T100 40 T161 2
valid_sources[0x0a] 51167 1 T98 5 T100 20 T161 3
valid_sources[0x0b] 50231 1 T98 1 T99 1 T100 28
valid_sources[0x0c] 51857 1 T98 15 T100 22 T185 51
valid_sources[0x0d] 50500 1 T98 31 T99 3 T100 40
valid_sources[0x0e] 51136 1 T99 2 T100 15 T161 4
valid_sources[0x0f] 51233 1 T99 2 T100 37 T185 46
valid_sources[0x10] 50955 1 T98 5 T100 14 T161 5
valid_sources[0x11] 50300 1 T100 25 T161 4 T185 25
valid_sources[0x12] 51008 1 T99 1 T100 19 T161 3
valid_sources[0x13] 51268 1 T99 1 T100 25 T161 2
valid_sources[0x14] 50163 1 T100 33 T161 1 T185 28
valid_sources[0x15] 51666 1 T100 26 T161 4 T185 35
valid_sources[0x16] 51503 1 T98 3 T99 1 T100 22
valid_sources[0x17] 51130 1 T99 1 T100 31 T161 3
valid_sources[0x18] 50539 1 T98 3 T99 4 T100 16
valid_sources[0x19] 50649 1 T98 10 T99 2 T100 31
valid_sources[0x1a] 51437 1 T98 6 T99 2 T100 30
valid_sources[0x1b] 51148 1 T99 4 T100 9 T161 1
valid_sources[0x1c] 51210 1 T98 3 T99 1 T100 5
valid_sources[0x1d] 51537 1 T100 8 T161 2 T185 28
valid_sources[0x1e] 51474 1 T98 2 T100 33 T161 2
valid_sources[0x1f] 50820 1 T98 4 T100 20 T161 4
valid_sources[0x20] 51360 1 T98 4 T99 1 T100 18


Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 3 0 3 100.00


Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins
cp_opcode   cp_mask   cp_size   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
values[0x4] all_enables biggest_size 46395 1 T98 2 T99 1 T100 19
values[0x0] all_enables biggest_size 351147 1 T98 18 T99 9 T100 182
values[0x1] all_enables biggest_size 46997 1 T98 3 T99 1 T100 20