Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=32}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=32}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

4 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_chip_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_chip_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_chip_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_chip_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	33	0	33	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_chip_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	33	0	33	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	33	0	33	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	33	0	33	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1702517	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

36163611

1

T1

350

T2

4133

T3

6630

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	25792694	1			T1	175		T2	1167		T3	2639
values[0x0]	10680814	1			T1	175		T2	2966		T3	3991
values[0x1]	1392620	1			T1	3		T2	139		T3	268

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	492262	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

37373866

1

T1

353

T2

4272

T3

6898

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	33	0	33	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	17972965	1			T1	177		T2	2136		T3	3449
valid_sources[0x01]	17970734	1			T1	176		T2	2136		T3	3449
valid_sources[0x02]	31188	1			T237	1		T890	4		T178	88
valid_sources[0x03]	30038	1			T97	1		T178	78		T401	22
valid_sources[0x04]	30368	1			T35	2		T178	75		T401	33
valid_sources[0x05]	31254	1			T181	1		T891	3		T178	74
valid_sources[0x06]	30961	1			T97	1		T237	1		T178	78
valid_sources[0x07]	31236	1			T35	2		T178	86		T401	31
valid_sources[0x08]	30609	1			T178	71		T401	30		T402	15
valid_sources[0x09]	30361	1			T181	1		T891	6		T178	99
valid_sources[0x0a]	30666	1			T891	3		T890	63		T178	72
valid_sources[0x0b]	30772	1			T891	4		T178	71		T401	35
valid_sources[0x0c]	31248	1			T97	3		T181	3		T891	2
valid_sources[0x0d]	30108	1			T181	2		T178	80		T401	30
valid_sources[0x0e]	31380	1			T237	4		T178	62		T401	35
valid_sources[0x0f]	30076	1			T97	3		T181	1		T891	5
valid_sources[0x10]	31591	1			T97	1		T178	62		T401	36
valid_sources[0x11]	31070	1			T178	73		T401	30		T402	18
valid_sources[0x12]	31442	1			T181	6		T178	62		T401	29
valid_sources[0x13]	30872	1			T891	5		T178	70		T401	34
valid_sources[0x14]	30882	1			T181	2		T178	94		T401	37
valid_sources[0x15]	30879	1			T181	4		T237	7		T891	1
valid_sources[0x16]	31091	1			T178	74		T401	34		T402	25
valid_sources[0x17]	31680	1			T35	1		T97	6		T891	2
valid_sources[0x18]	31258	1			T35	4		T891	2		T178	73
valid_sources[0x19]	31381	1			T891	1		T178	83		T401	32
valid_sources[0x1a]	30136	1			T98	6		T891	1		T178	71
valid_sources[0x1b]	31391	1			T891	4		T178	81		T401	38
valid_sources[0x1c]	31048	1			T891	7		T178	75		T401	34
valid_sources[0x1d]	31473	1			T97	1		T181	8		T237	1
valid_sources[0x1e]	30759	1			T35	1		T237	1		T891	14
valid_sources[0x1f]	30286	1			T181	2		T237	1		T891	7
valid_sources[0x20]	30574	1			T97	2		T98	3		T178	75

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

25284392

1

T1

175

T2

1167

T3

2639

values[0x0]

all_enables

biggest_size

10624187

1

T1

175

T2

2966

T3

3991

values[0x1]

all_enables

biggest_size

255032

1

T35

14

T97

16

T98

17

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2667003	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

421957

1

T94

15

T95

17

T96

122

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	1047070	1			T94	42		T95	43		T96	265
values[0x0]	995001	1			T94	29		T95	51		T96	278
values[0x1]	1046889	1			T94	30		T95	35		T96	319

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2063927	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

1025033

1

T94

38

T95

38

T96

273

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	33	0	33	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	48228	1			T96	3		T99	5		T248	14
valid_sources[0x01]	47472	1			T96	15		T99	25		T248	13
valid_sources[0x02]	48741	1			T95	20		T96	15		T99	37
valid_sources[0x03]	47665	1			T96	21		T99	7		T248	32
valid_sources[0x04]	49493	1			T96	12		T99	33		T248	26
valid_sources[0x05]	48145	1			T95	3		T96	26		T99	29
valid_sources[0x06]	49342	1			T96	15		T99	9		T248	16
valid_sources[0x07]	49029	1			T95	5		T96	14		T99	14
valid_sources[0x08]	48615	1			T96	15		T99	5		T248	16
valid_sources[0x09]	47437	1			T95	9		T96	22		T99	5
valid_sources[0x0a]	46972	1			T95	9		T96	8		T99	7
valid_sources[0x0b]	49055	1			T94	4		T96	25		T99	38
valid_sources[0x0c]	48315	1			T96	15		T99	35		T248	28
valid_sources[0x0d]	48951	1			T96	12		T99	9		T248	16
valid_sources[0x0e]	48731	1			T96	7		T99	3		T248	23
valid_sources[0x0f]	47567	1			T96	15		T99	11		T248	21
valid_sources[0x10]	48927	1			T94	5		T96	6		T99	28
valid_sources[0x11]	48651	1			T96	10		T99	9		T248	16
valid_sources[0x12]	48345	1			T94	4		T96	6		T99	71
valid_sources[0x13]	48547	1			T94	9		T95	6		T96	11
valid_sources[0x14]	48061	1			T94	13		T96	12		T99	11
valid_sources[0x15]	47732	1			T96	10		T99	13		T248	23
valid_sources[0x16]	48417	1			T96	18		T99	30		T248	13
valid_sources[0x17]	47333	1			T94	7		T96	5		T99	17
valid_sources[0x18]	48889	1			T95	1		T96	23		T99	50
valid_sources[0x19]	48600	1			T95	3		T96	13		T99	14
valid_sources[0x1a]	49058	1			T96	10		T99	14		T248	25
valid_sources[0x1b]	49795	1			T95	1		T96	14		T99	11
valid_sources[0x1c]	47213	1			T94	20		T96	11		T99	6
valid_sources[0x1d]	48528	1			T96	10		T248	17		T445	77
valid_sources[0x1e]	48765	1			T96	15		T99	22		T248	22
valid_sources[0x1f]	48286	1			T95	1		T96	16		T99	15
valid_sources[0x20]	48499	1			T96	18		T99	1		T248	11

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

44460

1

T94

2

T96

10

T99

21

values[0x0]

all_enables

biggest_size

332879

1

T94

12

T95

15

T96

97

values[0x1]

all_enables

biggest_size

44618

1

T94

1

T95

2

T96

15

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2844529	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

463151

1

T94

28

T95

28

T96

130

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	1134214	1			T94	63		T95	63		T96	311
values[0x0]	1040149	1			T94	56		T95	62		T96	318
values[0x1]	1133317	1			T94	72		T95	75		T96	319

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2181611	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

1126069

1

T94

67

T95

73

T96

334

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	33	0	33	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	51376	1			T94	2		T96	13		T99	13
valid_sources[0x01]	50252	1			T96	17		T248	14		T278	2
valid_sources[0x02]	51162	1			T94	10		T95	2		T96	15
valid_sources[0x03]	51428	1			T94	5		T96	22		T99	5
valid_sources[0x04]	51686	1			T96	19		T248	10		T278	1
valid_sources[0x05]	51050	1			T94	5		T96	17		T99	10
valid_sources[0x06]	52151	1			T94	1		T95	21		T96	13
valid_sources[0x07]	51505	1			T95	1		T96	19		T99	42
valid_sources[0x08]	52173	1			T94	1		T96	14		T99	22
valid_sources[0x09]	50913	1			T94	2		T96	8		T99	6
valid_sources[0x0a]	50586	1			T94	4		T95	1		T96	17
valid_sources[0x0b]	51014	1			T94	7		T96	16		T99	5
valid_sources[0x0c]	51883	1			T94	2		T96	10		T99	15
valid_sources[0x0d]	52788	1			T94	1		T95	3		T96	16
valid_sources[0x0e]	52494	1			T95	29		T96	15		T248	25
valid_sources[0x0f]	53244	1			T94	1		T96	10		T99	2
valid_sources[0x10]	51184	1			T94	14		T95	8		T96	17
valid_sources[0x11]	51360	1			T94	2		T95	2		T96	13
valid_sources[0x12]	52578	1			T94	2		T96	14		T248	16
valid_sources[0x13]	50600	1			T95	8		T96	16		T248	19
valid_sources[0x14]	52582	1			T94	11		T96	20		T99	42
valid_sources[0x15]	51244	1			T94	1		T96	19		T99	42
valid_sources[0x16]	51363	1			T94	3		T95	10		T96	14
valid_sources[0x17]	52013	1			T95	2		T96	20		T99	13
valid_sources[0x18]	51356	1			T94	3		T96	12		T99	1
valid_sources[0x19]	51950	1			T94	2		T95	11		T96	17
valid_sources[0x1a]	52803	1			T95	1		T96	14		T99	36
valid_sources[0x1b]	52283	1			T94	7		T96	14		T99	6
valid_sources[0x1c]	51327	1			T96	15		T99	7		T248	27
valid_sources[0x1d]	51703	1			T96	17		T99	3		T248	22
valid_sources[0x1e]	52457	1			T94	1		T96	13		T248	15
valid_sources[0x1f]	51908	1			T94	2		T96	7		T248	12
valid_sources[0x20]	52052	1			T95	5		T96	13		T99	16

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

49071

1

T94

5

T95

2

T96

9

values[0x0]

all_enables

biggest_size

365079

1

T94

20

T95

25

T96

100

values[0x1]

all_enables

biggest_size

49001

1

T94

3

T95

1

T96

21

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2690103	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

426425

1

T94

24

T95

20

T96

112

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	1057064	1			T94	62		T95	50		T96	275
values[0x0]	1003412	1			T94	70		T95	48		T96	255
values[0x1]	1056052	1			T94	64		T95	44		T96	287

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2083088	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

1033440

1

T94

60

T95

42

T96

278

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	33	0	33	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	48498	1			T94	2		T95	6		T96	7
valid_sources[0x01]	47978	1			T94	4		T96	15		T99	10
valid_sources[0x02]	48059	1			T94	1		T96	20		T99	18
valid_sources[0x03]	48821	1			T94	6		T95	14		T96	17
valid_sources[0x04]	48943	1			T94	4		T95	17		T96	17
valid_sources[0x05]	48635	1			T94	3		T95	1		T96	18
valid_sources[0x06]	49013	1			T94	2		T95	3		T96	16
valid_sources[0x07]	48853	1			T94	5		T96	15		T99	24
valid_sources[0x08]	48329	1			T94	1		T96	16		T99	9
valid_sources[0x09]	47975	1			T94	2		T96	13		T99	18
valid_sources[0x0a]	48100	1			T94	4		T96	8		T99	21
valid_sources[0x0b]	48935	1			T94	1		T95	16		T96	11
valid_sources[0x0c]	48283	1			T96	10		T99	20		T248	49
valid_sources[0x0d]	48963	1			T94	2		T96	9		T99	16
valid_sources[0x0e]	48960	1			T94	1		T95	1		T96	15
valid_sources[0x0f]	49108	1			T94	2		T96	14		T99	16
valid_sources[0x10]	49764	1			T94	2		T96	9		T99	12
valid_sources[0x11]	48065	1			T94	4		T95	1		T96	19
valid_sources[0x12]	50043	1			T94	1		T95	12		T96	14
valid_sources[0x13]	47964	1			T94	2		T95	1		T96	13
valid_sources[0x14]	49459	1			T94	2		T96	17		T99	15
valid_sources[0x15]	48586	1			T94	5		T96	15		T99	14
valid_sources[0x16]	48883	1			T94	1		T95	2		T96	12
valid_sources[0x17]	48239	1			T94	2		T96	3		T99	14
valid_sources[0x18]	49518	1			T94	6		T95	2		T96	7
valid_sources[0x19]	48837	1			T94	1		T96	12		T99	6
valid_sources[0x1a]	48437	1			T94	1		T96	12		T99	10
valid_sources[0x1b]	49453	1			T94	2		T96	14		T99	13
valid_sources[0x1c]	48619	1			T95	2		T96	12		T99	15
valid_sources[0x1d]	48687	1			T94	2		T96	16		T99	25
valid_sources[0x1e]	49198	1			T94	3		T95	2		T96	10
valid_sources[0x1f]	48857	1			T94	6		T96	10		T99	14
valid_sources[0x20]	48875	1			T94	5		T95	1		T96	7

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

45122

1

T94

4

T95

3

T96

11

values[0x0]

all_enables

biggest_size

336133

1

T94

17

T95

17

T96

90

values[0x1]

all_enables

biggest_size

45170

1

T94

3

T96

11

T99

15