Module Definition
dashboard | hierarchy | modlist | groups | tests | asserts



Module Instance : tb.dut.top_earlgrey.u_rv_plic.gen_alert_tx[0].u_prim_alert_sender

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
75.00 75.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
75.00 75.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
89.26 99.65 66.67 100.00 100.00 80.00 u_rv_plic


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.gen_alert_senders[1].u_alert_sender

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
75.00 75.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
75.00 75.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
90.27 94.12 89.29 99.75 100.00 68.18 u_rv_core_ibex


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.gen_alert_senders[3].u_alert_sender

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
87.50 87.50


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
87.50 87.50


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
90.27 94.12 89.29 99.75 100.00 68.18 u_rv_core_ibex


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.gen_alert_tx[0].u_prim_alert_sender

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
89.17 98.93 80.88 98.84 75.19 92.00 u_pinmux_aon


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.gen_alert_senders[0].u_alert_sender

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
90.27 94.12 89.29 99.75 100.00 68.18 u_rv_core_ibex


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.gen_alert_senders[2].u_alert_sender

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
90.27 94.12 89.29 99.75 100.00 68.18 u_rv_core_ibex


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children

Toggle Coverage for Module : prim_alert_sender
TotalCoveredPercent
Totals 12 12 100.00
Total Bits 24 24 100.00
Total Bits 0->1 12 12 100.00
Total Bits 1->0 12 12 100.00

Ports 12 12 100.00
Port Bits 24 24 100.00
Port Bits 0->1 12 12 100.00
Port Bits 1->0 12 12 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T45,T39,T29 Yes T1,T2,T3 INPUT
alert_test_i Yes Yes T80,T279,T199 Yes T80,T279,T199 INPUT
alert_req_i Yes Yes T87,T248,T224 Yes T87,T248,T224 INPUT
alert_ack_o Yes Yes T87,T248,T224 Yes T87,T248,T224 OUTPUT
alert_state_o Yes Yes T87,T248,T156 Yes T87,T248,T224 OUTPUT
alert_rx_i.ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_rx_i.ack_p Yes Yes T87,T248,T80 Yes T87,T248,T80 INPUT
alert_rx_i.ping_n Yes Yes T104,T105,T106 Yes T104,T105,T106 INPUT
alert_rx_i.ping_p Yes Yes T104,T105,T106 Yes T104,T105,T106 INPUT
alert_tx_o.alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_tx_o.alert_p Yes Yes T87,T248,T80 Yes T87,T248,T80 OUTPUT

Toggle Coverage for Instance : tb.dut.top_earlgrey.u_rv_plic.gen_alert_tx[0].u_prim_alert_sender
TotalCoveredPercent
Totals 12 9 75.00
Total Bits 24 18 75.00
Total Bits 0->1 12 9 75.00
Total Bits 1->0 12 9 75.00

Ports 12 9 75.00
Port Bits 24 18 75.00
Port Bits 0->1 12 9 75.00
Port Bits 1->0 12 9 75.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T45,T39,T29 Yes T1,T2,T3 INPUT
alert_test_i Yes Yes T80,T81,T82 Yes T80,T81,T82 INPUT
alert_req_i No No No INPUT
alert_ack_o No No No OUTPUT
alert_state_o No No No OUTPUT
alert_rx_i.ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_rx_i.ack_p Yes Yes T80,T104,T105 Yes T80,T104,T105 INPUT
alert_rx_i.ping_n Yes Yes T104,T105,T106 Yes T104,T105,T106 INPUT
alert_rx_i.ping_p Yes Yes T104,T105,T106 Yes T104,T105,T106 INPUT
alert_tx_o.alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_tx_o.alert_p Yes Yes T80,T104,T105 Yes T80,T104,T105 OUTPUT

Toggle Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.gen_alert_senders[1].u_alert_sender
TotalCoveredPercent
Totals 12 9 75.00
Total Bits 24 18 75.00
Total Bits 0->1 12 9 75.00
Total Bits 1->0 12 9 75.00

Ports 12 9 75.00
Port Bits 24 18 75.00
Port Bits 0->1 12 9 75.00
Port Bits 1->0 12 9 75.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T45,T39,T29 Yes T1,T2,T3 INPUT
alert_test_i Yes Yes T80,T279,T199 Yes T80,T279,T199 INPUT
alert_req_i No No No INPUT
alert_ack_o No No No OUTPUT
alert_state_o No No No OUTPUT
alert_rx_i.ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_rx_i.ack_p Yes Yes T80,T104,T279 Yes T80,T104,T279 INPUT
alert_rx_i.ping_n Yes Yes T104,T105,T106 Yes T104,T105,T106 INPUT
alert_rx_i.ping_p Yes Yes T104,T105,T106 Yes T104,T105,T106 INPUT
alert_tx_o.alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_tx_o.alert_p Yes Yes T80,T104,T279 Yes T80,T104,T279 OUTPUT

Toggle Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.gen_alert_senders[3].u_alert_sender
TotalCoveredPercent
Totals 12 10 83.33
Total Bits 24 21 87.50
Total Bits 0->1 12 11 91.67
Total Bits 1->0 12 10 83.33

Ports 12 10 83.33
Port Bits 24 21 87.50
Port Bits 0->1 12 11 91.67
Port Bits 1->0 12 10 83.33

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T45,T39,T29 Yes T1,T2,T3 INPUT
alert_test_i Yes Yes T80,T81,T82 Yes T80,T81,T82 INPUT
alert_req_i Yes Yes T407 Yes T407 INPUT
alert_ack_o No No No OUTPUT
alert_state_o No No Yes T407 OUTPUT
alert_rx_i.ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_rx_i.ack_p Yes Yes T80,T104,T105 Yes T80,T104,T105 INPUT
alert_rx_i.ping_n Yes Yes T104,T105,T106 Yes T104,T105,T313 INPUT
alert_rx_i.ping_p Yes Yes T104,T105,T313 Yes T104,T105,T106 INPUT
alert_tx_o.alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_tx_o.alert_p Yes Yes T80,T104,T105 Yes T80,T104,T105 OUTPUT

Toggle Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.gen_alert_tx[0].u_prim_alert_sender
TotalCoveredPercent
Totals 12 12 100.00
Total Bits 24 24 100.00
Total Bits 0->1 12 12 100.00
Total Bits 1->0 12 12 100.00

Ports 12 12 100.00
Port Bits 24 24 100.00
Port Bits 0->1 12 12 100.00
Port Bits 1->0 12 12 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T45,T39,T29 Yes T1,T2,T3 INPUT
alert_test_i Yes Yes T80,T81,T82 Yes T80,T81,T82 INPUT
alert_req_i Yes Yes T109,T110,T111 Yes T108,T109,T110 INPUT
alert_ack_o Yes Yes T108,T109,T110 Yes T108,T109,T110 OUTPUT
alert_state_o Yes Yes T109,T110,T111 Yes T108,T109,T110 OUTPUT
alert_rx_i.ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_rx_i.ack_p Yes Yes T80,T104,T105 Yes T80,T104,T105 INPUT
alert_rx_i.ping_n Yes Yes T104,T105,T106 Yes T104,T105,T106 INPUT
alert_rx_i.ping_p Yes Yes T104,T105,T106 Yes T104,T105,T106 INPUT
alert_tx_o.alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_tx_o.alert_p Yes Yes T80,T104,T105 Yes T80,T104,T105 OUTPUT

Toggle Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.gen_alert_senders[0].u_alert_sender
TotalCoveredPercent
Totals 12 12 100.00
Total Bits 24 24 100.00
Total Bits 0->1 12 12 100.00
Total Bits 1->0 12 12 100.00

Ports 12 12 100.00
Port Bits 24 24 100.00
Port Bits 0->1 12 12 100.00
Port Bits 1->0 12 12 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T45,T39,T29 Yes T1,T2,T3 INPUT
alert_test_i Yes Yes T80,T81,T82 Yes T80,T81,T82 INPUT
alert_req_i Yes Yes T303 Yes T303 INPUT
alert_ack_o Yes Yes T303 Yes T303 OUTPUT
alert_state_o Yes Yes T303 Yes T303 OUTPUT
alert_rx_i.ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_rx_i.ack_p Yes Yes T80,T104,T105 Yes T80,T104,T105 INPUT
alert_rx_i.ping_n Yes Yes T104,T105,T106 Yes T104,T105,T106 INPUT
alert_rx_i.ping_p Yes Yes T104,T105,T106 Yes T104,T105,T106 INPUT
alert_tx_o.alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_tx_o.alert_p Yes Yes T80,T104,T105 Yes T80,T104,T105 OUTPUT

Toggle Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.gen_alert_senders[2].u_alert_sender
TotalCoveredPercent
Totals 12 12 100.00
Total Bits 24 24 100.00
Total Bits 0->1 12 12 100.00
Total Bits 1->0 12 12 100.00

Ports 12 12 100.00
Port Bits 24 24 100.00
Port Bits 0->1 12 12 100.00
Port Bits 1->0 12 12 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T45,T39,T29 Yes T1,T2,T3 INPUT
alert_test_i Yes Yes T80,T81,T82 Yes T80,T81,T82 INPUT
alert_req_i Yes Yes T87,T248,T224 Yes T87,T248,T224 INPUT
alert_ack_o Yes Yes T87,T248,T224 Yes T87,T248,T224 OUTPUT
alert_state_o Yes Yes T87,T248,T156 Yes T87,T248,T224 OUTPUT
alert_rx_i.ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_rx_i.ack_p Yes Yes T87,T248,T80 Yes T87,T248,T80 INPUT
alert_rx_i.ping_n Yes Yes T104,T105,T106 Yes T104,T105,T106 INPUT
alert_rx_i.ping_p Yes Yes T104,T105,T106 Yes T104,T105,T106 INPUT
alert_tx_o.alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_tx_o.alert_p Yes Yes T87,T248,T80 Yes T87,T248,T80 OUTPUT

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%