dashboard | hierarchy | modlist | groups | tests | asserts

Module Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_prio63

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.80 99.94 99.75 99.52 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
wr_en_data_arb 100.00 100.00 100.00 100.00


Module Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_prio64

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.80 99.94 99.75 99.52 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
wr_en_data_arb 100.00 100.00 100.00 100.00


Module Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_prio65

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.80 99.94 99.75 99.52 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
wr_en_data_arb 100.00 100.00 100.00 100.00


Module Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_prio66

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.80 99.94 99.75 99.52 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
wr_en_data_arb 100.00 100.00 100.00 100.00


Module Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_prio67

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.80 99.94 99.75 99.52 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
wr_en_data_arb 100.00 100.00 100.00 100.00


Module Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_prio68

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.80 99.94 99.75 99.52 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
wr_en_data_arb 100.00 100.00 100.00 100.00


Module Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_prio69

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.80 99.94 99.75 99.52 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
wr_en_data_arb 100.00 100.00 100.00 100.00


Module Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_prio70

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.80 99.94 99.75 99.52 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
wr_en_data_arb 100.00 100.00 100.00 100.00


Module Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_prio71

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.80 99.94 99.75 99.52 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
wr_en_data_arb 100.00 100.00 100.00 100.00


Module Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_prio72

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.80 99.94 99.75 99.52 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
wr_en_data_arb 100.00 100.00 100.00 100.00


Module Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_prio73

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.80 99.94 99.75 99.52 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
wr_en_data_arb 100.00 100.00 100.00 100.00


Module Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_prio74

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.80 99.94 99.75 99.52 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
wr_en_data_arb 100.00 100.00 100.00 100.00


Module Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_prio75

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.80 99.94 99.75 99.52 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
wr_en_data_arb 100.00 100.00 100.00 100.00


Module Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_prio76

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.80 99.94 99.75 99.52 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
wr_en_data_arb 100.00 100.00 100.00 100.00


Module Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_prio77

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.80 99.94 99.75 99.52 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
wr_en_data_arb 100.00 100.00 100.00 100.00


Module Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_prio78

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.80 99.94 99.75 99.52 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
wr_en_data_arb 100.00 100.00 100.00 100.00


Module Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_prio79

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.80 99.94 99.75 99.52 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
wr_en_data_arb 100.00 100.00 100.00 100.00


Module Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_prio80

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.80 99.94 99.75 99.52 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
wr_en_data_arb 100.00 100.00 100.00 100.00


Module Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_prio81

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.80 99.94 99.75 99.52 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
wr_en_data_arb 100.00 100.00 100.00 100.00


Module Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_prio82

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.80 99.94 99.75 99.52 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
wr_en_data_arb 100.00 100.00 100.00 100.00


Module Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_prio83

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.80 99.94 99.75 99.52 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
wr_en_data_arb 100.00 100.00 100.00 100.00


Module Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_prio84

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.80 99.94 99.75 99.52 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
wr_en_data_arb 100.00 100.00 100.00 100.00


Module Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_prio85

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.80 99.94 99.75 99.52 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
wr_en_data_arb 100.00 100.00 100.00 100.00


Module Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_prio86

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.80 99.94 99.75 99.52 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
wr_en_data_arb 100.00 100.00 100.00 100.00


Module Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_prio87

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.80 99.94 99.75 99.52 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
wr_en_data_arb 100.00 100.00 100.00 100.00


Module Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_prio88

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.80 99.94 99.75 99.52 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
wr_en_data_arb 100.00 100.00 100.00 100.00


Module Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_prio89

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.80 99.94 99.75 99.52 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
wr_en_data_arb 100.00 100.00 100.00 100.00


Module Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_prio90

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.80 99.94 99.75 99.52 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
wr_en_data_arb 100.00 100.00 100.00 100.00


Module Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_prio91

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.80 99.94 99.75 99.52 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
wr_en_data_arb 100.00 100.00 100.00 100.00


Module Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_prio92

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.80 99.94 99.75 99.52 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
wr_en_data_arb 100.00 100.00 100.00 100.00


Module Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_prio93

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.80 99.94 99.75 99.52 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
wr_en_data_arb 100.00 100.00 100.00 100.00


Module Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_prio94

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.80 99.94 99.75 99.52 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
wr_en_data_arb 100.00 100.00 100.00 100.00

Go back
Module Instances:
tb.dut.top_earlgrey.u_rv_plic.u_reg.u_prio63
tb.dut.top_earlgrey.u_rv_plic.u_reg.u_prio64
tb.dut.top_earlgrey.u_rv_plic.u_reg.u_prio65
tb.dut.top_earlgrey.u_rv_plic.u_reg.u_prio66
tb.dut.top_earlgrey.u_rv_plic.u_reg.u_prio67
tb.dut.top_earlgrey.u_rv_plic.u_reg.u_prio68
tb.dut.top_earlgrey.u_rv_plic.u_reg.u_prio69
tb.dut.top_earlgrey.u_rv_plic.u_reg.u_prio70
tb.dut.top_earlgrey.u_rv_plic.u_reg.u_prio71
tb.dut.top_earlgrey.u_rv_plic.u_reg.u_prio72
tb.dut.top_earlgrey.u_rv_plic.u_reg.u_prio73
tb.dut.top_earlgrey.u_rv_plic.u_reg.u_prio74
tb.dut.top_earlgrey.u_rv_plic.u_reg.u_prio75
tb.dut.top_earlgrey.u_rv_plic.u_reg.u_prio76
tb.dut.top_earlgrey.u_rv_plic.u_reg.u_prio77
tb.dut.top_earlgrey.u_rv_plic.u_reg.u_prio78
tb.dut.top_earlgrey.u_rv_plic.u_reg.u_prio79
tb.dut.top_earlgrey.u_rv_plic.u_reg.u_prio80
tb.dut.top_earlgrey.u_rv_plic.u_reg.u_prio81
tb.dut.top_earlgrey.u_rv_plic.u_reg.u_prio82
tb.dut.top_earlgrey.u_rv_plic.u_reg.u_prio83
tb.dut.top_earlgrey.u_rv_plic.u_reg.u_prio84
tb.dut.top_earlgrey.u_rv_plic.u_reg.u_prio85
tb.dut.top_earlgrey.u_rv_plic.u_reg.u_prio86
tb.dut.top_earlgrey.u_rv_plic.u_reg.u_prio87
tb.dut.top_earlgrey.u_rv_plic.u_reg.u_prio88
tb.dut.top_earlgrey.u_rv_plic.u_reg.u_prio89
tb.dut.top_earlgrey.u_rv_plic.u_reg.u_prio90
tb.dut.top_earlgrey.u_rv_plic.u_reg.u_prio91
tb.dut.top_earlgrey.u_rv_plic.u_reg.u_prio92
tb.dut.top_earlgrey.u_rv_plic.u_reg.u_prio93
tb.dut.top_earlgrey.u_rv_plic.u_reg.u_prio94
Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_prio63
Line No.TotalCoveredPercent
TOTAL77100.00
ALWAYS5644100.00
CONT_ASSIGN6411100.00
CONT_ASSIGN6511100.00
CONT_ASSIGN7211100.00


55                        always_ff @(posedge clk_i or negedge rst_ni) begin
56         1/1              if (!rst_ni) begin
           Tests:       T1 T2 T3 
57         1/1                q <= RESVAL;
           Tests:       T1 T2 T3 
58         1/1              end else if (wr_en) begin
           Tests:       T1 T2 T3 
59         1/1                q <= wr_data;
           Tests:       T27 T249 T131 
60                          end
                        MISSING_ELSE
61                        end
62                      
63                        // feed back out for consolidation
64         1/1            assign ds = wr_en ? wr_data : qs;
           Tests:       T27 T249 T131 
65         1/1            assign qe = wr_en;
           Tests:       T27 T249 T131 
66                      
67                        if (SwAccess == SwAccessRC) begin : gen_rc
68                          // In case of a SW RC colliding with a HW write, SW gets the value written by HW
69                          // but the register is cleared to 0. See #5416 for a discussion.
70                          assign qs = de && we ? d : q;
71                        end else begin : gen_no_rc
72         1/1              assign qs = q;
           Tests:       T27 T249 T131 
Cond Coverage for Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_prio63
TotalCoveredPercent
Conditions22100.00
Logical22100.00
Non-Logical00
Event00

 LINE       64
 EXPRESSION (wr_en ? wr_data : qs)
             --1--
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT27,T249,T131
Branch Coverage for Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_prio63
Line No.TotalCoveredPercent
Branches 5 5 100.00
TERNARY 64 2 2 100.00
IF 56 3 3 100.00 



64           assign ds = wr_en ? wr_data : qs;
                               -1-  
                               ==>  
                               ==>

Branches:
-1-StatusTests
1 Covered T27,T249,T131
0 Covered T1,T2,T3 



56             if (!rst_ni) begin
               -1-  
57               q <= RESVAL;
                 ==>
58             end else if (wr_en) begin
                        -2-  
59               q <= wr_data;
                 ==>
60             end
               MISSING_ELSE
               ==>

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T27,T249,T131
0 0 Covered T1,T2,T3

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_prio64
Line No.TotalCoveredPercent
TOTAL77100.00
ALWAYS5644100.00
CONT_ASSIGN6411100.00
CONT_ASSIGN6511100.00
CONT_ASSIGN7211100.00


55                        always_ff @(posedge clk_i or negedge rst_ni) begin
56         1/1              if (!rst_ni) begin
           Tests:       T1 T2 T3 
57         1/1                q <= RESVAL;
           Tests:       T1 T2 T3 
58         1/1              end else if (wr_en) begin
           Tests:       T1 T2 T3 
59         1/1                q <= wr_data;
           Tests:       T27 T249 T131 
60                          end
                        MISSING_ELSE
61                        end
62                      
63                        // feed back out for consolidation
64         1/1            assign ds = wr_en ? wr_data : qs;
           Tests:       T27 T249 T131 
65         1/1            assign qe = wr_en;
           Tests:       T27 T249 T131 
66                      
67                        if (SwAccess == SwAccessRC) begin : gen_rc
68                          // In case of a SW RC colliding with a HW write, SW gets the value written by HW
69                          // but the register is cleared to 0. See #5416 for a discussion.
70                          assign qs = de && we ? d : q;
71                        end else begin : gen_no_rc
72         1/1              assign qs = q;
           Tests:       T27 T249 T131 
Cond Coverage for Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_prio64
TotalCoveredPercent
Conditions22100.00
Logical22100.00
Non-Logical00
Event00

 LINE       64
 EXPRESSION (wr_en ? wr_data : qs)
             --1--
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT27,T249,T131
Branch Coverage for Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_prio64
Line No.TotalCoveredPercent
Branches 5 5 100.00
TERNARY 64 2 2 100.00
IF 56 3 3 100.00 



64           assign ds = wr_en ? wr_data : qs;
                               -1-  
                               ==>  
                               ==>

Branches:
-1-StatusTests
1 Covered T27,T249,T131
0 Covered T1,T2,T3 



56             if (!rst_ni) begin
               -1-  
57               q <= RESVAL;
                 ==>
58             end else if (wr_en) begin
                        -2-  
59               q <= wr_data;
                 ==>
60             end
               MISSING_ELSE
               ==>

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T27,T249,T131
0 0 Covered T1,T2,T3

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_prio65
Line No.TotalCoveredPercent
TOTAL77100.00
ALWAYS5644100.00
CONT_ASSIGN6411100.00
CONT_ASSIGN6511100.00
CONT_ASSIGN7211100.00


55                        always_ff @(posedge clk_i or negedge rst_ni) begin
56         1/1              if (!rst_ni) begin
           Tests:       T1 T2 T3 
57         1/1                q <= RESVAL;
           Tests:       T1 T2 T3 
58         1/1              end else if (wr_en) begin
           Tests:       T1 T2 T3 
59         1/1                q <= wr_data;
           Tests:       T27 T249 T131 
60                          end
                        MISSING_ELSE
61                        end
62                      
63                        // feed back out for consolidation
64         1/1            assign ds = wr_en ? wr_data : qs;
           Tests:       T27 T249 T131 
65         1/1            assign qe = wr_en;
           Tests:       T27 T249 T131 
66                      
67                        if (SwAccess == SwAccessRC) begin : gen_rc
68                          // In case of a SW RC colliding with a HW write, SW gets the value written by HW
69                          // but the register is cleared to 0. See #5416 for a discussion.
70                          assign qs = de && we ? d : q;
71                        end else begin : gen_no_rc
72         1/1              assign qs = q;
           Tests:       T27 T249 T131 
Cond Coverage for Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_prio65
TotalCoveredPercent
Conditions22100.00
Logical22100.00
Non-Logical00
Event00

 LINE       64
 EXPRESSION (wr_en ? wr_data : qs)
             --1--
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT27,T249,T131
Branch Coverage for Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_prio65
Line No.TotalCoveredPercent
Branches 5 5 100.00
TERNARY 64 2 2 100.00
IF 56 3 3 100.00 



64           assign ds = wr_en ? wr_data : qs;
                               -1-  
                               ==>  
                               ==>

Branches:
-1-StatusTests
1 Covered T27,T249,T131
0 Covered T1,T2,T3 



56             if (!rst_ni) begin
               -1-  
57               q <= RESVAL;
                 ==>
58             end else if (wr_en) begin
                        -2-  
59               q <= wr_data;
                 ==>
60             end
               MISSING_ELSE
               ==>

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T27,T249,T131
0 0 Covered T1,T2,T3

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_prio66
Line No.TotalCoveredPercent
TOTAL77100.00
ALWAYS5644100.00
CONT_ASSIGN6411100.00
CONT_ASSIGN6511100.00
CONT_ASSIGN7211100.00


55                        always_ff @(posedge clk_i or negedge rst_ni) begin
56         1/1              if (!rst_ni) begin
           Tests:       T1 T2 T3 
57         1/1                q <= RESVAL;
           Tests:       T1 T2 T3 
58         1/1              end else if (wr_en) begin
           Tests:       T1 T2 T3 
59         1/1                q <= wr_data;
           Tests:       T27 T249 T131 
60                          end
                        MISSING_ELSE
61                        end
62                      
63                        // feed back out for consolidation
64         1/1            assign ds = wr_en ? wr_data : qs;
           Tests:       T27 T249 T131 
65         1/1            assign qe = wr_en;
           Tests:       T27 T249 T131 
66                      
67                        if (SwAccess == SwAccessRC) begin : gen_rc
68                          // In case of a SW RC colliding with a HW write, SW gets the value written by HW
69                          // but the register is cleared to 0. See #5416 for a discussion.
70                          assign qs = de && we ? d : q;
71                        end else begin : gen_no_rc
72         1/1              assign qs = q;
           Tests:       T27 T249 T131 
Cond Coverage for Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_prio66
TotalCoveredPercent
Conditions22100.00
Logical22100.00
Non-Logical00
Event00

 LINE       64
 EXPRESSION (wr_en ? wr_data : qs)
             --1--
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT27,T249,T131
Branch Coverage for Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_prio66
Line No.TotalCoveredPercent
Branches 5 5 100.00
TERNARY 64 2 2 100.00
IF 56 3 3 100.00 



64           assign ds = wr_en ? wr_data : qs;
                               -1-  
                               ==>  
                               ==>

Branches:
-1-StatusTests
1 Covered T27,T249,T131
0 Covered T1,T2,T3 



56             if (!rst_ni) begin
               -1-  
57               q <= RESVAL;
                 ==>
58             end else if (wr_en) begin
                        -2-  
59               q <= wr_data;
                 ==>
60             end
               MISSING_ELSE
               ==>

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T27,T249,T131
0 0 Covered T1,T2,T3

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_prio67
Line No.TotalCoveredPercent
TOTAL77100.00
ALWAYS5644100.00
CONT_ASSIGN6411100.00
CONT_ASSIGN6511100.00
CONT_ASSIGN7211100.00


55                        always_ff @(posedge clk_i or negedge rst_ni) begin
56         1/1              if (!rst_ni) begin
           Tests:       T1 T2 T3 
57         1/1                q <= RESVAL;
           Tests:       T1 T2 T3 
58         1/1              end else if (wr_en) begin
           Tests:       T1 T2 T3 
59         1/1                q <= wr_data;
           Tests:       T27 T249 T131 
60                          end
                        MISSING_ELSE
61                        end
62                      
63                        // feed back out for consolidation
64         1/1            assign ds = wr_en ? wr_data : qs;
           Tests:       T27 T249 T131 
65         1/1            assign qe = wr_en;
           Tests:       T27 T249 T131 
66                      
67                        if (SwAccess == SwAccessRC) begin : gen_rc
68                          // In case of a SW RC colliding with a HW write, SW gets the value written by HW
69                          // but the register is cleared to 0. See #5416 for a discussion.
70                          assign qs = de && we ? d : q;
71                        end else begin : gen_no_rc
72         1/1              assign qs = q;
           Tests:       T27 T249 T131 
Cond Coverage for Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_prio67
TotalCoveredPercent
Conditions22100.00
Logical22100.00
Non-Logical00
Event00

 LINE       64
 EXPRESSION (wr_en ? wr_data : qs)
             --1--
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT27,T249,T131
Branch Coverage for Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_prio67
Line No.TotalCoveredPercent
Branches 5 5 100.00
TERNARY 64 2 2 100.00
IF 56 3 3 100.00 



64           assign ds = wr_en ? wr_data : qs;
                               -1-  
                               ==>  
                               ==>

Branches:
-1-StatusTests
1 Covered T27,T249,T131
0 Covered T1,T2,T3 



56             if (!rst_ni) begin
               -1-  
57               q <= RESVAL;
                 ==>
58             end else if (wr_en) begin
                        -2-  
59               q <= wr_data;
                 ==>
60             end
               MISSING_ELSE
               ==>

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T27,T249,T131
0 0 Covered T1,T2,T3

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_prio68
Line No.TotalCoveredPercent
TOTAL77100.00
ALWAYS5644100.00
CONT_ASSIGN6411100.00
CONT_ASSIGN6511100.00
CONT_ASSIGN7211100.00


55                        always_ff @(posedge clk_i or negedge rst_ni) begin
56         1/1              if (!rst_ni) begin
           Tests:       T1 T2 T3 
57         1/1                q <= RESVAL;
           Tests:       T1 T2 T3 
58         1/1              end else if (wr_en) begin
           Tests:       T1 T2 T3 
59         1/1                q <= wr_data;
           Tests:       T27 T249 T131 
60                          end
                        MISSING_ELSE
61                        end
62                      
63                        // feed back out for consolidation
64         1/1            assign ds = wr_en ? wr_data : qs;
           Tests:       T27 T249 T131 
65         1/1            assign qe = wr_en;
           Tests:       T27 T249 T131 
66                      
67                        if (SwAccess == SwAccessRC) begin : gen_rc
68                          // In case of a SW RC colliding with a HW write, SW gets the value written by HW
69                          // but the register is cleared to 0. See #5416 for a discussion.
70                          assign qs = de && we ? d : q;
71                        end else begin : gen_no_rc
72         1/1              assign qs = q;
           Tests:       T27 T249 T131 
Cond Coverage for Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_prio68
TotalCoveredPercent
Conditions22100.00
Logical22100.00
Non-Logical00
Event00

 LINE       64
 EXPRESSION (wr_en ? wr_data : qs)
             --1--
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT27,T249,T131
Branch Coverage for Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_prio68
Line No.TotalCoveredPercent
Branches 5 5 100.00
TERNARY 64 2 2 100.00
IF 56 3 3 100.00 



64           assign ds = wr_en ? wr_data : qs;
                               -1-  
                               ==>  
                               ==>

Branches:
-1-StatusTests
1 Covered T27,T249,T131
0 Covered T1,T2,T3 



56             if (!rst_ni) begin
               -1-  
57               q <= RESVAL;
                 ==>
58             end else if (wr_en) begin
                        -2-  
59               q <= wr_data;
                 ==>
60             end
               MISSING_ELSE
               ==>

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T27,T249,T131
0 0 Covered T1,T2,T3

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_prio69
Line No.TotalCoveredPercent
TOTAL77100.00
ALWAYS5644100.00
CONT_ASSIGN6411100.00
CONT_ASSIGN6511100.00
CONT_ASSIGN7211100.00


55                        always_ff @(posedge clk_i or negedge rst_ni) begin
56         1/1              if (!rst_ni) begin
           Tests:       T1 T2 T3 
57         1/1                q <= RESVAL;
           Tests:       T1 T2 T3 
58         1/1              end else if (wr_en) begin
           Tests:       T1 T2 T3 
59         1/1                q <= wr_data;
           Tests:       T12 T27 T10 
60                          end
                        MISSING_ELSE
61                        end
62                      
63                        // feed back out for consolidation
64         1/1            assign ds = wr_en ? wr_data : qs;
           Tests:       T12 T27 T10 
65         1/1            assign qe = wr_en;
           Tests:       T12 T27 T10 
66                      
67                        if (SwAccess == SwAccessRC) begin : gen_rc
68                          // In case of a SW RC colliding with a HW write, SW gets the value written by HW
69                          // but the register is cleared to 0. See #5416 for a discussion.
70                          assign qs = de && we ? d : q;
71                        end else begin : gen_no_rc
72         1/1              assign qs = q;
           Tests:       T12 T27 T10 
Cond Coverage for Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_prio69
TotalCoveredPercent
Conditions22100.00
Logical22100.00
Non-Logical00
Event00

 LINE       64
 EXPRESSION (wr_en ? wr_data : qs)
             --1--
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT12,T27,T10
Branch Coverage for Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_prio69
Line No.TotalCoveredPercent
Branches 5 5 100.00
TERNARY 64 2 2 100.00
IF 56 3 3 100.00 



64           assign ds = wr_en ? wr_data : qs;
                               -1-  
                               ==>  
                               ==>

Branches:
-1-StatusTests
1 Covered T12,T27,T10
0 Covered T1,T2,T3 



56             if (!rst_ni) begin
               -1-  
57               q <= RESVAL;
                 ==>
58             end else if (wr_en) begin
                        -2-  
59               q <= wr_data;
                 ==>
60             end
               MISSING_ELSE
               ==>

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T12,T27,T10
0 0 Covered T1,T2,T3

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_prio70
Line No.TotalCoveredPercent
TOTAL77100.00
ALWAYS5644100.00
CONT_ASSIGN6411100.00
CONT_ASSIGN6511100.00
CONT_ASSIGN7211100.00


55                        always_ff @(posedge clk_i or negedge rst_ni) begin
56         1/1              if (!rst_ni) begin
           Tests:       T1 T2 T3 
57         1/1                q <= RESVAL;
           Tests:       T1 T2 T3 
58         1/1              end else if (wr_en) begin
           Tests:       T1 T2 T3 
59         1/1                q <= wr_data;
           Tests:       T12 T249 T131 
60                          end
                        MISSING_ELSE
61                        end
62                      
63                        // feed back out for consolidation
64         1/1            assign ds = wr_en ? wr_data : qs;
           Tests:       T12 T249 T131 
65         1/1            assign qe = wr_en;
           Tests:       T12 T249 T131 
66                      
67                        if (SwAccess == SwAccessRC) begin : gen_rc
68                          // In case of a SW RC colliding with a HW write, SW gets the value written by HW
69                          // but the register is cleared to 0. See #5416 for a discussion.
70                          assign qs = de && we ? d : q;
71                        end else begin : gen_no_rc
72         1/1              assign qs = q;
           Tests:       T12 T249 T131 
Cond Coverage for Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_prio70
TotalCoveredPercent
Conditions22100.00
Logical22100.00
Non-Logical00
Event00

 LINE       64
 EXPRESSION (wr_en ? wr_data : qs)
             --1--
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT12,T249,T131
Branch Coverage for Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_prio70
Line No.TotalCoveredPercent
Branches 5 5 100.00
TERNARY 64 2 2 100.00
IF 56 3 3 100.00 



64           assign ds = wr_en ? wr_data : qs;
                               -1-  
                               ==>  
                               ==>

Branches:
-1-StatusTests
1 Covered T12,T249,T131
0 Covered T1,T2,T3 



56             if (!rst_ni) begin
               -1-  
57               q <= RESVAL;
                 ==>
58             end else if (wr_en) begin
                        -2-  
59               q <= wr_data;
                 ==>
60             end
               MISSING_ELSE
               ==>

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T12,T249,T131
0 0 Covered T1,T2,T3

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_prio71
Line No.TotalCoveredPercent
TOTAL77100.00
ALWAYS5644100.00
CONT_ASSIGN6411100.00
CONT_ASSIGN6511100.00
CONT_ASSIGN7211100.00


55                        always_ff @(posedge clk_i or negedge rst_ni) begin
56         1/1              if (!rst_ni) begin
           Tests:       T1 T2 T3 
57         1/1                q <= RESVAL;
           Tests:       T1 T2 T3 
58         1/1              end else if (wr_en) begin
           Tests:       T1 T2 T3 
59         1/1                q <= wr_data;
           Tests:       T12 T249 T131 
60                          end
                        MISSING_ELSE
61                        end
62                      
63                        // feed back out for consolidation
64         1/1            assign ds = wr_en ? wr_data : qs;
           Tests:       T12 T249 T131 
65         1/1            assign qe = wr_en;
           Tests:       T12 T249 T131 
66                      
67                        if (SwAccess == SwAccessRC) begin : gen_rc
68                          // In case of a SW RC colliding with a HW write, SW gets the value written by HW
69                          // but the register is cleared to 0. See #5416 for a discussion.
70                          assign qs = de && we ? d : q;
71                        end else begin : gen_no_rc
72         1/1              assign qs = q;
           Tests:       T12 T249 T131 
Cond Coverage for Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_prio71
TotalCoveredPercent
Conditions22100.00
Logical22100.00
Non-Logical00
Event00

 LINE       64
 EXPRESSION (wr_en ? wr_data : qs)
             --1--
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT12,T249,T131
Branch Coverage for Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_prio71
Line No.TotalCoveredPercent
Branches 5 5 100.00
TERNARY 64 2 2 100.00
IF 56 3 3 100.00 



64           assign ds = wr_en ? wr_data : qs;
                               -1-  
                               ==>  
                               ==>

Branches:
-1-StatusTests
1 Covered T12,T249,T131
0 Covered T1,T2,T3 



56             if (!rst_ni) begin
               -1-  
57               q <= RESVAL;
                 ==>
58             end else if (wr_en) begin
                        -2-  
59               q <= wr_data;
                 ==>
60             end
               MISSING_ELSE
               ==>

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T12,T249,T131
0 0 Covered T1,T2,T3

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_prio72
Line No.TotalCoveredPercent
TOTAL77100.00
ALWAYS5644100.00
CONT_ASSIGN6411100.00
CONT_ASSIGN6511100.00
CONT_ASSIGN7211100.00


55                        always_ff @(posedge clk_i or negedge rst_ni) begin
56         1/1              if (!rst_ni) begin
           Tests:       T1 T2 T3 
57         1/1                q <= RESVAL;
           Tests:       T1 T2 T3 
58         1/1              end else if (wr_en) begin
           Tests:       T1 T2 T3 
59         1/1                q <= wr_data;
           Tests:       T12 T10 T11 
60                          end
                        MISSING_ELSE
61                        end
62                      
63                        // feed back out for consolidation
64         1/1            assign ds = wr_en ? wr_data : qs;
           Tests:       T12 T10 T11 
65         1/1            assign qe = wr_en;
           Tests:       T12 T10 T11 
66                      
67                        if (SwAccess == SwAccessRC) begin : gen_rc
68                          // In case of a SW RC colliding with a HW write, SW gets the value written by HW
69                          // but the register is cleared to 0. See #5416 for a discussion.
70                          assign qs = de && we ? d : q;
71                        end else begin : gen_no_rc
72         1/1              assign qs = q;
           Tests:       T12 T10 T11 
Cond Coverage for Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_prio72
TotalCoveredPercent
Conditions22100.00
Logical22100.00
Non-Logical00
Event00

 LINE       64
 EXPRESSION (wr_en ? wr_data : qs)
             --1--
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT12,T10,T11
Branch Coverage for Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_prio72
Line No.TotalCoveredPercent
Branches 5 5 100.00
TERNARY 64 2 2 100.00
IF 56 3 3 100.00 



64           assign ds = wr_en ? wr_data : qs;
                               -1-  
                               ==>  
                               ==>

Branches:
-1-StatusTests
1 Covered T12,T10,T11
0 Covered T1,T2,T3 



56             if (!rst_ni) begin
               -1-  
57               q <= RESVAL;
                 ==>
58             end else if (wr_en) begin
                        -2-  
59               q <= wr_data;
                 ==>
60             end
               MISSING_ELSE
               ==>

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T12,T10,T11
0 0 Covered T1,T2,T3

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_prio73
Line No.TotalCoveredPercent
TOTAL77100.00
ALWAYS5644100.00
CONT_ASSIGN6411100.00
CONT_ASSIGN6511100.00
CONT_ASSIGN7211100.00


55                        always_ff @(posedge clk_i or negedge rst_ni) begin
56         1/1              if (!rst_ni) begin
           Tests:       T1 T2 T3 
57         1/1                q <= RESVAL;
           Tests:       T1 T2 T3 
58         1/1              end else if (wr_en) begin
           Tests:       T1 T2 T3 
59         1/1                q <= wr_data;
           Tests:       T12 T10 T11 
60                          end
                        MISSING_ELSE
61                        end
62                      
63                        // feed back out for consolidation
64         1/1            assign ds = wr_en ? wr_data : qs;
           Tests:       T12 T10 T11 
65         1/1            assign qe = wr_en;
           Tests:       T12 T10 T11 
66                      
67                        if (SwAccess == SwAccessRC) begin : gen_rc
68                          // In case of a SW RC colliding with a HW write, SW gets the value written by HW
69                          // but the register is cleared to 0. See #5416 for a discussion.
70                          assign qs = de && we ? d : q;
71                        end else begin : gen_no_rc
72         1/1              assign qs = q;
           Tests:       T12 T10 T11 
Cond Coverage for Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_prio73
TotalCoveredPercent
Conditions22100.00
Logical22100.00
Non-Logical00
Event00

 LINE       64
 EXPRESSION (wr_en ? wr_data : qs)
             --1--
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT12,T10,T11
Branch Coverage for Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_prio73
Line No.TotalCoveredPercent
Branches 5 5 100.00
TERNARY 64 2 2 100.00
IF 56 3 3 100.00 



64           assign ds = wr_en ? wr_data : qs;
                               -1-  
                               ==>  
                               ==>

Branches:
-1-StatusTests
1 Covered T12,T10,T11
0 Covered T1,T2,T3 



56             if (!rst_ni) begin
               -1-  
57               q <= RESVAL;
                 ==>
58             end else if (wr_en) begin
                        -2-  
59               q <= wr_data;
                 ==>
60             end
               MISSING_ELSE
               ==>

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T12,T10,T11
0 0 Covered T1,T2,T3

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_prio74
Line No.TotalCoveredPercent
TOTAL77100.00
ALWAYS5644100.00
CONT_ASSIGN6411100.00
CONT_ASSIGN6511100.00
CONT_ASSIGN7211100.00


55                        always_ff @(posedge clk_i or negedge rst_ni) begin
56         1/1              if (!rst_ni) begin
           Tests:       T1 T2 T3 
57         1/1                q <= RESVAL;
           Tests:       T1 T2 T3 
58         1/1              end else if (wr_en) begin
           Tests:       T1 T2 T3 
59         1/1                q <= wr_data;
           Tests:       T12 T249 T131 
60                          end
                        MISSING_ELSE
61                        end
62                      
63                        // feed back out for consolidation
64         1/1            assign ds = wr_en ? wr_data : qs;
           Tests:       T12 T249 T131 
65         1/1            assign qe = wr_en;
           Tests:       T12 T249 T131 
66                      
67                        if (SwAccess == SwAccessRC) begin : gen_rc
68                          // In case of a SW RC colliding with a HW write, SW gets the value written by HW
69                          // but the register is cleared to 0. See #5416 for a discussion.
70                          assign qs = de && we ? d : q;
71                        end else begin : gen_no_rc
72         1/1              assign qs = q;
           Tests:       T12 T249 T131 
Cond Coverage for Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_prio74
TotalCoveredPercent
Conditions22100.00
Logical22100.00
Non-Logical00
Event00

 LINE       64
 EXPRESSION (wr_en ? wr_data : qs)
             --1--
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT12,T249,T131
Branch Coverage for Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_prio74
Line No.TotalCoveredPercent
Branches 5 5 100.00
TERNARY 64 2 2 100.00
IF 56 3 3 100.00 



64           assign ds = wr_en ? wr_data : qs;
                               -1-  
                               ==>  
                               ==>

Branches:
-1-StatusTests
1 Covered T12,T249,T131
0 Covered T1,T2,T3 



56             if (!rst_ni) begin
               -1-  
57               q <= RESVAL;
                 ==>
58             end else if (wr_en) begin
                        -2-  
59               q <= wr_data;
                 ==>
60             end
               MISSING_ELSE
               ==>

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T12,T249,T131
0 0 Covered T1,T2,T3

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_prio75
Line No.TotalCoveredPercent
TOTAL77100.00
ALWAYS5644100.00
CONT_ASSIGN6411100.00
CONT_ASSIGN6511100.00
CONT_ASSIGN7211100.00


55                        always_ff @(posedge clk_i or negedge rst_ni) begin
56         1/1              if (!rst_ni) begin
           Tests:       T1 T2 T3 
57         1/1                q <= RESVAL;
           Tests:       T1 T2 T3 
58         1/1              end else if (wr_en) begin
           Tests:       T1 T2 T3 
59         1/1                q <= wr_data;
           Tests:       T249 T131 T252 
60                          end
                        MISSING_ELSE
61                        end
62                      
63                        // feed back out for consolidation
64         1/1            assign ds = wr_en ? wr_data : qs;
           Tests:       T249 T131 T252 
65         1/1            assign qe = wr_en;
           Tests:       T249 T131 T252 
66                      
67                        if (SwAccess == SwAccessRC) begin : gen_rc
68                          // In case of a SW RC colliding with a HW write, SW gets the value written by HW
69                          // but the register is cleared to 0. See #5416 for a discussion.
70                          assign qs = de && we ? d : q;
71                        end else begin : gen_no_rc
72         1/1              assign qs = q;
           Tests:       T249 T131 T252 
Cond Coverage for Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_prio75
TotalCoveredPercent
Conditions22100.00
Logical22100.00
Non-Logical00
Event00

 LINE       64
 EXPRESSION (wr_en ? wr_data : qs)
             --1--
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT249,T131,T252
Branch Coverage for Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_prio75
Line No.TotalCoveredPercent
Branches 5 5 100.00
TERNARY 64 2 2 100.00
IF 56 3 3 100.00 



64           assign ds = wr_en ? wr_data : qs;
                               -1-  
                               ==>  
                               ==>

Branches:
-1-StatusTests
1 Covered T249,T131,T252
0 Covered T1,T2,T3 



56             if (!rst_ni) begin
               -1-  
57               q <= RESVAL;
                 ==>
58             end else if (wr_en) begin
                        -2-  
59               q <= wr_data;
                 ==>
60             end
               MISSING_ELSE
               ==>

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T249,T131,T252
0 0 Covered T1,T2,T3

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_prio76
Line No.TotalCoveredPercent
TOTAL77100.00
ALWAYS5644100.00
CONT_ASSIGN6411100.00
CONT_ASSIGN6511100.00
CONT_ASSIGN7211100.00


55                        always_ff @(posedge clk_i or negedge rst_ni) begin
56         1/1              if (!rst_ni) begin
           Tests:       T1 T2 T3 
57         1/1                q <= RESVAL;
           Tests:       T1 T2 T3 
58         1/1              end else if (wr_en) begin
           Tests:       T1 T2 T3 
59         1/1                q <= wr_data;
           Tests:       T249 T131 T252 
60                          end
                        MISSING_ELSE
61                        end
62                      
63                        // feed back out for consolidation
64         1/1            assign ds = wr_en ? wr_data : qs;
           Tests:       T249 T131 T252 
65         1/1            assign qe = wr_en;
           Tests:       T249 T131 T252 
66                      
67                        if (SwAccess == SwAccessRC) begin : gen_rc
68                          // In case of a SW RC colliding with a HW write, SW gets the value written by HW
69                          // but the register is cleared to 0. See #5416 for a discussion.
70                          assign qs = de && we ? d : q;
71                        end else begin : gen_no_rc
72         1/1              assign qs = q;
           Tests:       T249 T131 T252 
Cond Coverage for Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_prio76
TotalCoveredPercent
Conditions22100.00
Logical22100.00
Non-Logical00
Event00

 LINE       64
 EXPRESSION (wr_en ? wr_data : qs)
             --1--
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT249,T131,T252
Branch Coverage for Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_prio76
Line No.TotalCoveredPercent
Branches 5 5 100.00
TERNARY 64 2 2 100.00
IF 56 3 3 100.00 



64           assign ds = wr_en ? wr_data : qs;
                               -1-  
                               ==>  
                               ==>

Branches:
-1-StatusTests
1 Covered T249,T131,T252
0 Covered T1,T2,T3 



56             if (!rst_ni) begin
               -1-  
57               q <= RESVAL;
                 ==>
58             end else if (wr_en) begin
                        -2-  
59               q <= wr_data;
                 ==>
60             end
               MISSING_ELSE
               ==>

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T249,T131,T252
0 0 Covered T1,T2,T3

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_prio77
Line No.TotalCoveredPercent
TOTAL77100.00
ALWAYS5644100.00
CONT_ASSIGN6411100.00
CONT_ASSIGN6511100.00
CONT_ASSIGN7211100.00


55                        always_ff @(posedge clk_i or negedge rst_ni) begin
56         1/1              if (!rst_ni) begin
           Tests:       T1 T2 T3 
57         1/1                q <= RESVAL;
           Tests:       T1 T2 T3 
58         1/1              end else if (wr_en) begin
           Tests:       T1 T2 T3 
59         1/1                q <= wr_data;
           Tests:       T62 T249 T131 
60                          end
                        MISSING_ELSE
61                        end
62                      
63                        // feed back out for consolidation
64         1/1            assign ds = wr_en ? wr_data : qs;
           Tests:       T62 T249 T131 
65         1/1            assign qe = wr_en;
           Tests:       T62 T249 T131 
66                      
67                        if (SwAccess == SwAccessRC) begin : gen_rc
68                          // In case of a SW RC colliding with a HW write, SW gets the value written by HW
69                          // but the register is cleared to 0. See #5416 for a discussion.
70                          assign qs = de && we ? d : q;
71                        end else begin : gen_no_rc
72         1/1              assign qs = q;
           Tests:       T62 T249 T131 
Cond Coverage for Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_prio77
TotalCoveredPercent
Conditions22100.00
Logical22100.00
Non-Logical00
Event00

 LINE       64
 EXPRESSION (wr_en ? wr_data : qs)
             --1--
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT62,T249,T131
Branch Coverage for Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_prio77
Line No.TotalCoveredPercent
Branches 5 5 100.00
TERNARY 64 2 2 100.00
IF 56 3 3 100.00 



64           assign ds = wr_en ? wr_data : qs;
                               -1-  
                               ==>  
                               ==>

Branches:
-1-StatusTests
1 Covered T62,T249,T131
0 Covered T1,T2,T3 



56             if (!rst_ni) begin
               -1-  
57               q <= RESVAL;
                 ==>
58             end else if (wr_en) begin
                        -2-  
59               q <= wr_data;
                 ==>
60             end
               MISSING_ELSE
               ==>

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T62,T249,T131
0 0 Covered T1,T2,T3

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_prio78
Line No.TotalCoveredPercent
TOTAL77100.00
ALWAYS5644100.00
CONT_ASSIGN6411100.00
CONT_ASSIGN6511100.00
CONT_ASSIGN7211100.00


55                        always_ff @(posedge clk_i or negedge rst_ni) begin
56         1/1              if (!rst_ni) begin
           Tests:       T1 T2 T3 
57         1/1                q <= RESVAL;
           Tests:       T1 T2 T3 
58         1/1              end else if (wr_en) begin
           Tests:       T1 T2 T3 
59         1/1                q <= wr_data;
           Tests:       T62 T249 T131 
60                          end
                        MISSING_ELSE
61                        end
62                      
63                        // feed back out for consolidation
64         1/1            assign ds = wr_en ? wr_data : qs;
           Tests:       T62 T249 T131 
65         1/1            assign qe = wr_en;
           Tests:       T62 T249 T131 
66                      
67                        if (SwAccess == SwAccessRC) begin : gen_rc
68                          // In case of a SW RC colliding with a HW write, SW gets the value written by HW
69                          // but the register is cleared to 0. See #5416 for a discussion.
70                          assign qs = de && we ? d : q;
71                        end else begin : gen_no_rc
72         1/1              assign qs = q;
           Tests:       T62 T249 T131 
Cond Coverage for Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_prio78
TotalCoveredPercent
Conditions22100.00
Logical22100.00
Non-Logical00
Event00

 LINE       64
 EXPRESSION (wr_en ? wr_data : qs)
             --1--
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT62,T249,T131
Branch Coverage for Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_prio78
Line No.TotalCoveredPercent
Branches 5 5 100.00
TERNARY 64 2 2 100.00
IF 56 3 3 100.00 



64           assign ds = wr_en ? wr_data : qs;
                               -1-  
                               ==>  
                               ==>

Branches:
-1-StatusTests
1 Covered T62,T249,T131
0 Covered T1,T2,T3 



56             if (!rst_ni) begin
               -1-  
57               q <= RESVAL;
                 ==>
58             end else if (wr_en) begin
                        -2-  
59               q <= wr_data;
                 ==>
60             end
               MISSING_ELSE
               ==>

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T62,T249,T131
0 0 Covered T1,T2,T3

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_prio79
Line No.TotalCoveredPercent
TOTAL77100.00
ALWAYS5644100.00
CONT_ASSIGN6411100.00
CONT_ASSIGN6511100.00
CONT_ASSIGN7211100.00


55                        always_ff @(posedge clk_i or negedge rst_ni) begin
56         1/1              if (!rst_ni) begin
           Tests:       T1 T2 T3 
57         1/1                q <= RESVAL;
           Tests:       T1 T2 T3 
58         1/1              end else if (wr_en) begin
           Tests:       T1 T2 T3 
59         1/1                q <= wr_data;
           Tests:       T249 T131 T252 
60                          end
                        MISSING_ELSE
61                        end
62                      
63                        // feed back out for consolidation
64         1/1            assign ds = wr_en ? wr_data : qs;
           Tests:       T249 T131 T252 
65         1/1            assign qe = wr_en;
           Tests:       T249 T131 T252 
66                      
67                        if (SwAccess == SwAccessRC) begin : gen_rc
68                          // In case of a SW RC colliding with a HW write, SW gets the value written by HW
69                          // but the register is cleared to 0. See #5416 for a discussion.
70                          assign qs = de && we ? d : q;
71                        end else begin : gen_no_rc
72         1/1              assign qs = q;
           Tests:       T249 T131 T252 
Cond Coverage for Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_prio79
TotalCoveredPercent
Conditions22100.00
Logical22100.00
Non-Logical00
Event00

 LINE       64
 EXPRESSION (wr_en ? wr_data : qs)
             --1--
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT249,T131,T252
Branch Coverage for Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_prio79
Line No.TotalCoveredPercent
Branches 5 5 100.00
TERNARY 64 2 2 100.00
IF 56 3 3 100.00 



64           assign ds = wr_en ? wr_data : qs;
                               -1-  
                               ==>  
                               ==>

Branches:
-1-StatusTests
1 Covered T249,T131,T252
0 Covered T1,T2,T3 



56             if (!rst_ni) begin
               -1-  
57               q <= RESVAL;
                 ==>
58             end else if (wr_en) begin
                        -2-  
59               q <= wr_data;
                 ==>
60             end
               MISSING_ELSE
               ==>

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T249,T131,T252
0 0 Covered T1,T2,T3

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_prio80
Line No.TotalCoveredPercent
TOTAL77100.00
ALWAYS5644100.00
CONT_ASSIGN6411100.00
CONT_ASSIGN6511100.00
CONT_ASSIGN7211100.00


55                        always_ff @(posedge clk_i or negedge rst_ni) begin
56         1/1              if (!rst_ni) begin
           Tests:       T1 T2 T3 
57         1/1                q <= RESVAL;
           Tests:       T1 T2 T3 
58         1/1              end else if (wr_en) begin
           Tests:       T1 T2 T3 
59         1/1                q <= wr_data;
           Tests:       T62 T249 T131 
60                          end
                        MISSING_ELSE
61                        end
62                      
63                        // feed back out for consolidation
64         1/1            assign ds = wr_en ? wr_data : qs;
           Tests:       T62 T249 T131 
65         1/1            assign qe = wr_en;
           Tests:       T62 T249 T131 
66                      
67                        if (SwAccess == SwAccessRC) begin : gen_rc
68                          // In case of a SW RC colliding with a HW write, SW gets the value written by HW
69                          // but the register is cleared to 0. See #5416 for a discussion.
70                          assign qs = de && we ? d : q;
71                        end else begin : gen_no_rc
72         1/1              assign qs = q;
           Tests:       T62 T249 T131 
Cond Coverage for Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_prio80
TotalCoveredPercent
Conditions22100.00
Logical22100.00
Non-Logical00
Event00

 LINE       64
 EXPRESSION (wr_en ? wr_data : qs)
             --1--
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT62,T249,T131
Branch Coverage for Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_prio80
Line No.TotalCoveredPercent
Branches 5 5 100.00
TERNARY 64 2 2 100.00
IF 56 3 3 100.00 



64           assign ds = wr_en ? wr_data : qs;
                               -1-  
                               ==>  
                               ==>

Branches:
-1-StatusTests
1 Covered T62,T249,T131
0 Covered T1,T2,T3 



56             if (!rst_ni) begin
               -1-  
57               q <= RESVAL;
                 ==>
58             end else if (wr_en) begin
                        -2-  
59               q <= wr_data;
                 ==>
60             end
               MISSING_ELSE
               ==>

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T62,T249,T131
0 0 Covered T1,T2,T3

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_prio81
Line No.TotalCoveredPercent
TOTAL77100.00
ALWAYS5644100.00
CONT_ASSIGN6411100.00
CONT_ASSIGN6511100.00
CONT_ASSIGN7211100.00


55                        always_ff @(posedge clk_i or negedge rst_ni) begin
56         1/1              if (!rst_ni) begin
           Tests:       T1 T2 T3 
57         1/1                q <= RESVAL;
           Tests:       T1 T2 T3 
58         1/1              end else if (wr_en) begin
           Tests:       T1 T2 T3 
59         1/1                q <= wr_data;
           Tests:       T62 T249 T131 
60                          end
                        MISSING_ELSE
61                        end
62                      
63                        // feed back out for consolidation
64         1/1            assign ds = wr_en ? wr_data : qs;
           Tests:       T62 T249 T131 
65         1/1            assign qe = wr_en;
           Tests:       T62 T249 T131 
66                      
67                        if (SwAccess == SwAccessRC) begin : gen_rc
68                          // In case of a SW RC colliding with a HW write, SW gets the value written by HW
69                          // but the register is cleared to 0. See #5416 for a discussion.
70                          assign qs = de && we ? d : q;
71                        end else begin : gen_no_rc
72         1/1              assign qs = q;
           Tests:       T62 T249 T131 
Cond Coverage for Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_prio81
TotalCoveredPercent
Conditions22100.00
Logical22100.00
Non-Logical00
Event00

 LINE       64
 EXPRESSION (wr_en ? wr_data : qs)
             --1--
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT62,T249,T131
Branch Coverage for Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_prio81
Line No.TotalCoveredPercent
Branches 5 5 100.00
TERNARY 64 2 2 100.00
IF 56 3 3 100.00 



64           assign ds = wr_en ? wr_data : qs;
                               -1-  
                               ==>  
                               ==>

Branches:
-1-StatusTests
1 Covered T62,T249,T131
0 Covered T1,T2,T3 



56             if (!rst_ni) begin
               -1-  
57               q <= RESVAL;
                 ==>
58             end else if (wr_en) begin
                        -2-  
59               q <= wr_data;
                 ==>
60             end
               MISSING_ELSE
               ==>

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T62,T249,T131
0 0 Covered T1,T2,T3

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_prio82
Line No.TotalCoveredPercent
TOTAL77100.00
ALWAYS5644100.00
CONT_ASSIGN6411100.00
CONT_ASSIGN6511100.00
CONT_ASSIGN7211100.00


55                        always_ff @(posedge clk_i or negedge rst_ni) begin
56         1/1              if (!rst_ni) begin
           Tests:       T1 T2 T3 
57         1/1                q <= RESVAL;
           Tests:       T1 T2 T3 
58         1/1              end else if (wr_en) begin
           Tests:       T1 T2 T3 
59         1/1                q <= wr_data;
           Tests:       T62 T249 T131 
60                          end
                        MISSING_ELSE
61                        end
62                      
63                        // feed back out for consolidation
64         1/1            assign ds = wr_en ? wr_data : qs;
           Tests:       T62 T249 T131 
65         1/1            assign qe = wr_en;
           Tests:       T62 T249 T131 
66                      
67                        if (SwAccess == SwAccessRC) begin : gen_rc
68                          // In case of a SW RC colliding with a HW write, SW gets the value written by HW
69                          // but the register is cleared to 0. See #5416 for a discussion.
70                          assign qs = de && we ? d : q;
71                        end else begin : gen_no_rc
72         1/1              assign qs = q;
           Tests:       T62 T249 T131 
Cond Coverage for Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_prio82
TotalCoveredPercent
Conditions22100.00
Logical22100.00
Non-Logical00
Event00

 LINE       64
 EXPRESSION (wr_en ? wr_data : qs)
             --1--
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT62,T249,T131
Branch Coverage for Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_prio82
Line No.TotalCoveredPercent
Branches 5 5 100.00
TERNARY 64 2 2 100.00
IF 56 3 3 100.00 



64           assign ds = wr_en ? wr_data : qs;
                               -1-  
                               ==>  
                               ==>

Branches:
-1-StatusTests
1 Covered T62,T249,T131
0 Covered T1,T2,T3 



56             if (!rst_ni) begin
               -1-  
57               q <= RESVAL;
                 ==>
58             end else if (wr_en) begin
                        -2-  
59               q <= wr_data;
                 ==>
60             end
               MISSING_ELSE
               ==>

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T62,T249,T131
0 0 Covered T1,T2,T3

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_prio83
Line No.TotalCoveredPercent
TOTAL77100.00
ALWAYS5644100.00
CONT_ASSIGN6411100.00
CONT_ASSIGN6511100.00
CONT_ASSIGN7211100.00


55                        always_ff @(posedge clk_i or negedge rst_ni) begin
56         1/1              if (!rst_ni) begin
           Tests:       T1 T2 T3 
57         1/1                q <= RESVAL;
           Tests:       T1 T2 T3 
58         1/1              end else if (wr_en) begin
           Tests:       T1 T2 T3 
59         1/1                q <= wr_data;
           Tests:       T62 T249 T131 
60                          end
                        MISSING_ELSE
61                        end
62                      
63                        // feed back out for consolidation
64         1/1            assign ds = wr_en ? wr_data : qs;
           Tests:       T62 T249 T131 
65         1/1            assign qe = wr_en;
           Tests:       T62 T249 T131 
66                      
67                        if (SwAccess == SwAccessRC) begin : gen_rc
68                          // In case of a SW RC colliding with a HW write, SW gets the value written by HW
69                          // but the register is cleared to 0. See #5416 for a discussion.
70                          assign qs = de && we ? d : q;
71                        end else begin : gen_no_rc
72         1/1              assign qs = q;
           Tests:       T62 T249 T131 
Cond Coverage for Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_prio83
TotalCoveredPercent
Conditions22100.00
Logical22100.00
Non-Logical00
Event00

 LINE       64
 EXPRESSION (wr_en ? wr_data : qs)
             --1--
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT62,T249,T131
Branch Coverage for Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_prio83
Line No.TotalCoveredPercent
Branches 5 5 100.00
TERNARY 64 2 2 100.00
IF 56 3 3 100.00 



64           assign ds = wr_en ? wr_data : qs;
                               -1-  
                               ==>  
                               ==>

Branches:
-1-StatusTests
1 Covered T62,T249,T131
0 Covered T1,T2,T3 



56             if (!rst_ni) begin
               -1-  
57               q <= RESVAL;
                 ==>
58             end else if (wr_en) begin
                        -2-  
59               q <= wr_data;
                 ==>
60             end
               MISSING_ELSE
               ==>

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T62,T249,T131
0 0 Covered T1,T2,T3

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_prio84
Line No.TotalCoveredPercent
TOTAL77100.00
ALWAYS5644100.00
CONT_ASSIGN6411100.00
CONT_ASSIGN6511100.00
CONT_ASSIGN7211100.00


55                        always_ff @(posedge clk_i or negedge rst_ni) begin
56         1/1              if (!rst_ni) begin
           Tests:       T1 T2 T3 
57         1/1                q <= RESVAL;
           Tests:       T1 T2 T3 
58         1/1              end else if (wr_en) begin
           Tests:       T1 T2 T3 
59         1/1                q <= wr_data;
           Tests:       T62 T249 T131 
60                          end
                        MISSING_ELSE
61                        end
62                      
63                        // feed back out for consolidation
64         1/1            assign ds = wr_en ? wr_data : qs;
           Tests:       T62 T249 T131 
65         1/1            assign qe = wr_en;
           Tests:       T62 T249 T131 
66                      
67                        if (SwAccess == SwAccessRC) begin : gen_rc
68                          // In case of a SW RC colliding with a HW write, SW gets the value written by HW
69                          // but the register is cleared to 0. See #5416 for a discussion.
70                          assign qs = de && we ? d : q;
71                        end else begin : gen_no_rc
72         1/1              assign qs = q;
           Tests:       T62 T249 T131 
Cond Coverage for Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_prio84
TotalCoveredPercent
Conditions22100.00
Logical22100.00
Non-Logical00
Event00

 LINE       64
 EXPRESSION (wr_en ? wr_data : qs)
             --1--
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT62,T249,T131
Branch Coverage for Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_prio84
Line No.TotalCoveredPercent
Branches 5 5 100.00
TERNARY 64 2 2 100.00
IF 56 3 3 100.00 



64           assign ds = wr_en ? wr_data : qs;
                               -1-  
                               ==>  
                               ==>

Branches:
-1-StatusTests
1 Covered T62,T249,T131
0 Covered T1,T2,T3 



56             if (!rst_ni) begin
               -1-  
57               q <= RESVAL;
                 ==>
58             end else if (wr_en) begin
                        -2-  
59               q <= wr_data;
                 ==>
60             end
               MISSING_ELSE
               ==>

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T62,T249,T131
0 0 Covered T1,T2,T3

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_prio85
Line No.TotalCoveredPercent
TOTAL77100.00
ALWAYS5644100.00
CONT_ASSIGN6411100.00
CONT_ASSIGN6511100.00
CONT_ASSIGN7211100.00


55                        always_ff @(posedge clk_i or negedge rst_ni) begin
56         1/1              if (!rst_ni) begin
           Tests:       T1 T2 T3 
57         1/1                q <= RESVAL;
           Tests:       T1 T2 T3 
58         1/1              end else if (wr_en) begin
           Tests:       T1 T2 T3 
59         1/1                q <= wr_data;
           Tests:       T249 T131 T252 
60                          end
                        MISSING_ELSE
61                        end
62                      
63                        // feed back out for consolidation
64         1/1            assign ds = wr_en ? wr_data : qs;
           Tests:       T249 T131 T252 
65         1/1            assign qe = wr_en;
           Tests:       T249 T131 T252 
66                      
67                        if (SwAccess == SwAccessRC) begin : gen_rc
68                          // In case of a SW RC colliding with a HW write, SW gets the value written by HW
69                          // but the register is cleared to 0. See #5416 for a discussion.
70                          assign qs = de && we ? d : q;
71                        end else begin : gen_no_rc
72         1/1              assign qs = q;
           Tests:       T249 T131 T252 
Cond Coverage for Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_prio85
TotalCoveredPercent
Conditions22100.00
Logical22100.00
Non-Logical00
Event00

 LINE       64
 EXPRESSION (wr_en ? wr_data : qs)
             --1--
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT249,T131,T252
Branch Coverage for Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_prio85
Line No.TotalCoveredPercent
Branches 5 5 100.00
TERNARY 64 2 2 100.00
IF 56 3 3 100.00 



64           assign ds = wr_en ? wr_data : qs;
                               -1-  
                               ==>  
                               ==>

Branches:
-1-StatusTests
1 Covered T249,T131,T252
0 Covered T1,T2,T3 



56             if (!rst_ni) begin
               -1-  
57               q <= RESVAL;
                 ==>
58             end else if (wr_en) begin
                        -2-  
59               q <= wr_data;
                 ==>
60             end
               MISSING_ELSE
               ==>

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T249,T131,T252
0 0 Covered T1,T2,T3

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_prio86
Line No.TotalCoveredPercent
TOTAL77100.00
ALWAYS5644100.00
CONT_ASSIGN6411100.00
CONT_ASSIGN6511100.00
CONT_ASSIGN7211100.00


55                        always_ff @(posedge clk_i or negedge rst_ni) begin
56         1/1              if (!rst_ni) begin
           Tests:       T1 T2 T3 
57         1/1                q <= RESVAL;
           Tests:       T1 T2 T3 
58         1/1              end else if (wr_en) begin
           Tests:       T1 T2 T3 
59         1/1                q <= wr_data;
           Tests:       T62 T249 T131 
60                          end
                        MISSING_ELSE
61                        end
62                      
63                        // feed back out for consolidation
64         1/1            assign ds = wr_en ? wr_data : qs;
           Tests:       T62 T249 T131 
65         1/1            assign qe = wr_en;
           Tests:       T62 T249 T131 
66                      
67                        if (SwAccess == SwAccessRC) begin : gen_rc
68                          // In case of a SW RC colliding with a HW write, SW gets the value written by HW
69                          // but the register is cleared to 0. See #5416 for a discussion.
70                          assign qs = de && we ? d : q;
71                        end else begin : gen_no_rc
72         1/1              assign qs = q;
           Tests:       T62 T249 T131 
Cond Coverage for Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_prio86
TotalCoveredPercent
Conditions22100.00
Logical22100.00
Non-Logical00
Event00

 LINE       64
 EXPRESSION (wr_en ? wr_data : qs)
             --1--
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT62,T249,T131
Branch Coverage for Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_prio86
Line No.TotalCoveredPercent
Branches 5 5 100.00
TERNARY 64 2 2 100.00
IF 56 3 3 100.00 



64           assign ds = wr_en ? wr_data : qs;
                               -1-  
                               ==>  
                               ==>

Branches:
-1-StatusTests
1 Covered T62,T249,T131
0 Covered T1,T2,T3 



56             if (!rst_ni) begin
               -1-  
57               q <= RESVAL;
                 ==>
58             end else if (wr_en) begin
                        -2-  
59               q <= wr_data;
                 ==>
60             end
               MISSING_ELSE
               ==>

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T62,T249,T131
0 0 Covered T1,T2,T3

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_prio87
Line No.TotalCoveredPercent
TOTAL77100.00
ALWAYS5644100.00
CONT_ASSIGN6411100.00
CONT_ASSIGN6511100.00
CONT_ASSIGN7211100.00


55                        always_ff @(posedge clk_i or negedge rst_ni) begin
56         1/1              if (!rst_ni) begin
           Tests:       T1 T2 T3 
57         1/1                q <= RESVAL;
           Tests:       T1 T2 T3 
58         1/1              end else if (wr_en) begin
           Tests:       T1 T2 T3 
59         1/1                q <= wr_data;
           Tests:       T249 T131 T252 
60                          end
                        MISSING_ELSE
61                        end
62                      
63                        // feed back out for consolidation
64         1/1            assign ds = wr_en ? wr_data : qs;
           Tests:       T249 T131 T252 
65         1/1            assign qe = wr_en;
           Tests:       T249 T131 T252 
66                      
67                        if (SwAccess == SwAccessRC) begin : gen_rc
68                          // In case of a SW RC colliding with a HW write, SW gets the value written by HW
69                          // but the register is cleared to 0. See #5416 for a discussion.
70                          assign qs = de && we ? d : q;
71                        end else begin : gen_no_rc
72         1/1              assign qs = q;
           Tests:       T249 T131 T252 
Cond Coverage for Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_prio87
TotalCoveredPercent
Conditions22100.00
Logical22100.00
Non-Logical00
Event00

 LINE       64
 EXPRESSION (wr_en ? wr_data : qs)
             --1--
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT249,T131,T252
Branch Coverage for Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_prio87
Line No.TotalCoveredPercent
Branches 5 5 100.00
TERNARY 64 2 2 100.00
IF 56 3 3 100.00 



64           assign ds = wr_en ? wr_data : qs;
                               -1-  
                               ==>  
                               ==>

Branches:
-1-StatusTests
1 Covered T249,T131,T252
0 Covered T1,T2,T3 



56             if (!rst_ni) begin
               -1-  
57               q <= RESVAL;
                 ==>
58             end else if (wr_en) begin
                        -2-  
59               q <= wr_data;
                 ==>
60             end
               MISSING_ELSE
               ==>

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T249,T131,T252
0 0 Covered T1,T2,T3

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_prio88
Line No.TotalCoveredPercent
TOTAL77100.00
ALWAYS5644100.00
CONT_ASSIGN6411100.00
CONT_ASSIGN6511100.00
CONT_ASSIGN7211100.00


55                        always_ff @(posedge clk_i or negedge rst_ni) begin
56         1/1              if (!rst_ni) begin
           Tests:       T1 T2 T3 
57         1/1                q <= RESVAL;
           Tests:       T1 T2 T3 
58         1/1              end else if (wr_en) begin
           Tests:       T1 T2 T3 
59         1/1                q <= wr_data;
           Tests:       T249 T131 T252 
60                          end
                        MISSING_ELSE
61                        end
62                      
63                        // feed back out for consolidation
64         1/1            assign ds = wr_en ? wr_data : qs;
           Tests:       T249 T131 T252 
65         1/1            assign qe = wr_en;
           Tests:       T249 T131 T252 
66                      
67                        if (SwAccess == SwAccessRC) begin : gen_rc
68                          // In case of a SW RC colliding with a HW write, SW gets the value written by HW
69                          // but the register is cleared to 0. See #5416 for a discussion.
70                          assign qs = de && we ? d : q;
71                        end else begin : gen_no_rc
72         1/1              assign qs = q;
           Tests:       T249 T131 T252 
Cond Coverage for Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_prio88
TotalCoveredPercent
Conditions22100.00
Logical22100.00
Non-Logical00
Event00

 LINE       64
 EXPRESSION (wr_en ? wr_data : qs)
             --1--
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT249,T131,T252
Branch Coverage for Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_prio88
Line No.TotalCoveredPercent
Branches 5 5 100.00
TERNARY 64 2 2 100.00
IF 56 3 3 100.00 



64           assign ds = wr_en ? wr_data : qs;
                               -1-  
                               ==>  
                               ==>

Branches:
-1-StatusTests
1 Covered T249,T131,T252
0 Covered T1,T2,T3 



56             if (!rst_ni) begin
               -1-  
57               q <= RESVAL;
                 ==>
58             end else if (wr_en) begin
                        -2-  
59               q <= wr_data;
                 ==>
60             end
               MISSING_ELSE
               ==>

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T249,T131,T252
0 0 Covered T1,T2,T3

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_prio89
Line No.TotalCoveredPercent
TOTAL77100.00
ALWAYS5644100.00
CONT_ASSIGN6411100.00
CONT_ASSIGN6511100.00
CONT_ASSIGN7211100.00


55                        always_ff @(posedge clk_i or negedge rst_ni) begin
56         1/1              if (!rst_ni) begin
           Tests:       T1 T2 T3 
57         1/1                q <= RESVAL;
           Tests:       T1 T2 T3 
58         1/1              end else if (wr_en) begin
           Tests:       T1 T2 T3 
59         1/1                q <= wr_data;
           Tests:       T249 T131 T252 
60                          end
                        MISSING_ELSE
61                        end
62                      
63                        // feed back out for consolidation
64         1/1            assign ds = wr_en ? wr_data : qs;
           Tests:       T249 T131 T252 
65         1/1            assign qe = wr_en;
           Tests:       T249 T131 T252 
66                      
67                        if (SwAccess == SwAccessRC) begin : gen_rc
68                          // In case of a SW RC colliding with a HW write, SW gets the value written by HW
69                          // but the register is cleared to 0. See #5416 for a discussion.
70                          assign qs = de && we ? d : q;
71                        end else begin : gen_no_rc
72         1/1              assign qs = q;
           Tests:       T249 T131 T252 
Cond Coverage for Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_prio89
TotalCoveredPercent
Conditions22100.00
Logical22100.00
Non-Logical00
Event00

 LINE       64
 EXPRESSION (wr_en ? wr_data : qs)
             --1--
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT249,T131,T252
Branch Coverage for Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_prio89
Line No.TotalCoveredPercent
Branches 5 5 100.00
TERNARY 64 2 2 100.00
IF 56 3 3 100.00 



64           assign ds = wr_en ? wr_data : qs;
                               -1-  
                               ==>  
                               ==>

Branches:
-1-StatusTests
1 Covered T249,T131,T252
0 Covered T1,T2,T3 



56             if (!rst_ni) begin
               -1-  
57               q <= RESVAL;
                 ==>
58             end else if (wr_en) begin
                        -2-  
59               q <= wr_data;
                 ==>
60             end
               MISSING_ELSE
               ==>

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T249,T131,T252
0 0 Covered T1,T2,T3

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_prio90
Line No.TotalCoveredPercent
TOTAL77100.00
ALWAYS5644100.00
CONT_ASSIGN6411100.00
CONT_ASSIGN6511100.00
CONT_ASSIGN7211100.00


55                        always_ff @(posedge clk_i or negedge rst_ni) begin
56         1/1              if (!rst_ni) begin
           Tests:       T1 T2 T3 
57         1/1                q <= RESVAL;
           Tests:       T1 T2 T3 
58         1/1              end else if (wr_en) begin
           Tests:       T1 T2 T3 
59         1/1                q <= wr_data;
           Tests:       T249 T131 T252 
60                          end
                        MISSING_ELSE
61                        end
62                      
63                        // feed back out for consolidation
64         1/1            assign ds = wr_en ? wr_data : qs;
           Tests:       T249 T131 T252 
65         1/1            assign qe = wr_en;
           Tests:       T249 T131 T252 
66                      
67                        if (SwAccess == SwAccessRC) begin : gen_rc
68                          // In case of a SW RC colliding with a HW write, SW gets the value written by HW
69                          // but the register is cleared to 0. See #5416 for a discussion.
70                          assign qs = de && we ? d : q;
71                        end else begin : gen_no_rc
72         1/1              assign qs = q;
           Tests:       T249 T131 T252 
Cond Coverage for Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_prio90
TotalCoveredPercent
Conditions22100.00
Logical22100.00
Non-Logical00
Event00

 LINE       64
 EXPRESSION (wr_en ? wr_data : qs)
             --1--
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT249,T131,T252
Branch Coverage for Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_prio90
Line No.TotalCoveredPercent
Branches 5 5 100.00
TERNARY 64 2 2 100.00
IF 56 3 3 100.00 



64           assign ds = wr_en ? wr_data : qs;
                               -1-  
                               ==>  
                               ==>

Branches:
-1-StatusTests
1 Covered T249,T131,T252
0 Covered T1,T2,T3 



56             if (!rst_ni) begin
               -1-  
57               q <= RESVAL;
                 ==>
58             end else if (wr_en) begin
                        -2-  
59               q <= wr_data;
                 ==>
60             end
               MISSING_ELSE
               ==>

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T249,T131,T252
0 0 Covered T1,T2,T3

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_prio91
Line No.TotalCoveredPercent
TOTAL77100.00
ALWAYS5644100.00
CONT_ASSIGN6411100.00
CONT_ASSIGN6511100.00
CONT_ASSIGN7211100.00


55                        always_ff @(posedge clk_i or negedge rst_ni) begin
56         1/1              if (!rst_ni) begin
           Tests:       T1 T2 T3 
57         1/1                q <= RESVAL;
           Tests:       T1 T2 T3 
58         1/1              end else if (wr_en) begin
           Tests:       T1 T2 T3 
59         1/1                q <= wr_data;
           Tests:       T249 T131 T252 
60                          end
                        MISSING_ELSE
61                        end
62                      
63                        // feed back out for consolidation
64         1/1            assign ds = wr_en ? wr_data : qs;
           Tests:       T249 T131 T252 
65         1/1            assign qe = wr_en;
           Tests:       T249 T131 T252 
66                      
67                        if (SwAccess == SwAccessRC) begin : gen_rc
68                          // In case of a SW RC colliding with a HW write, SW gets the value written by HW
69                          // but the register is cleared to 0. See #5416 for a discussion.
70                          assign qs = de && we ? d : q;
71                        end else begin : gen_no_rc
72         1/1              assign qs = q;
           Tests:       T249 T131 T252 
Cond Coverage for Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_prio91
TotalCoveredPercent
Conditions22100.00
Logical22100.00
Non-Logical00
Event00

 LINE       64
 EXPRESSION (wr_en ? wr_data : qs)
             --1--
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT249,T131,T252
Branch Coverage for Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_prio91
Line No.TotalCoveredPercent
Branches 5 5 100.00
TERNARY 64 2 2 100.00
IF 56 3 3 100.00 



64           assign ds = wr_en ? wr_data : qs;
                               -1-  
                               ==>  
                               ==>

Branches:
-1-StatusTests
1 Covered T249,T131,T252
0 Covered T1,T2,T3 



56             if (!rst_ni) begin
               -1-  
57               q <= RESVAL;
                 ==>
58             end else if (wr_en) begin
                        -2-  
59               q <= wr_data;
                 ==>
60             end
               MISSING_ELSE
               ==>

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T249,T131,T252
0 0 Covered T1,T2,T3

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_prio92
Line No.TotalCoveredPercent
TOTAL77100.00
ALWAYS5644100.00
CONT_ASSIGN6411100.00
CONT_ASSIGN6511100.00
CONT_ASSIGN7211100.00


55                        always_ff @(posedge clk_i or negedge rst_ni) begin
56         1/1              if (!rst_ni) begin
           Tests:       T1 T2 T3 
57         1/1                q <= RESVAL;
           Tests:       T1 T2 T3 
58         1/1              end else if (wr_en) begin
           Tests:       T1 T2 T3 
59         1/1                q <= wr_data;
           Tests:       T65 T249 T131 
60                          end
                        MISSING_ELSE
61                        end
62                      
63                        // feed back out for consolidation
64         1/1            assign ds = wr_en ? wr_data : qs;
           Tests:       T65 T249 T131 
65         1/1            assign qe = wr_en;
           Tests:       T65 T249 T131 
66                      
67                        if (SwAccess == SwAccessRC) begin : gen_rc
68                          // In case of a SW RC colliding with a HW write, SW gets the value written by HW
69                          // but the register is cleared to 0. See #5416 for a discussion.
70                          assign qs = de && we ? d : q;
71                        end else begin : gen_no_rc
72         1/1              assign qs = q;
           Tests:       T65 T249 T131 
Cond Coverage for Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_prio92
TotalCoveredPercent
Conditions22100.00
Logical22100.00
Non-Logical00
Event00

 LINE       64
 EXPRESSION (wr_en ? wr_data : qs)
             --1--
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT65,T249,T131
Branch Coverage for Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_prio92
Line No.TotalCoveredPercent
Branches 5 5 100.00
TERNARY 64 2 2 100.00
IF 56 3 3 100.00 



64           assign ds = wr_en ? wr_data : qs;
                               -1-  
                               ==>  
                               ==>

Branches:
-1-StatusTests
1 Covered T65,T249,T131
0 Covered T1,T2,T3 



56             if (!rst_ni) begin
               -1-  
57               q <= RESVAL;
                 ==>
58             end else if (wr_en) begin
                        -2-  
59               q <= wr_data;
                 ==>
60             end
               MISSING_ELSE
               ==>

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T65,T249,T131
0 0 Covered T1,T2,T3

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_prio93
Line No.TotalCoveredPercent
TOTAL77100.00
ALWAYS5644100.00
CONT_ASSIGN6411100.00
CONT_ASSIGN6511100.00
CONT_ASSIGN7211100.00


55                        always_ff @(posedge clk_i or negedge rst_ni) begin
56         1/1              if (!rst_ni) begin
           Tests:       T1 T2 T3 
57         1/1                q <= RESVAL;
           Tests:       T1 T2 T3 
58         1/1              end else if (wr_en) begin
           Tests:       T1 T2 T3 
59         1/1                q <= wr_data;
           Tests:       T65 T249 T131 
60                          end
                        MISSING_ELSE
61                        end
62                      
63                        // feed back out for consolidation
64         1/1            assign ds = wr_en ? wr_data : qs;
           Tests:       T65 T249 T131 
65         1/1            assign qe = wr_en;
           Tests:       T65 T249 T131 
66                      
67                        if (SwAccess == SwAccessRC) begin : gen_rc
68                          // In case of a SW RC colliding with a HW write, SW gets the value written by HW
69                          // but the register is cleared to 0. See #5416 for a discussion.
70                          assign qs = de && we ? d : q;
71                        end else begin : gen_no_rc
72         1/1              assign qs = q;
           Tests:       T65 T249 T131 
Cond Coverage for Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_prio93
TotalCoveredPercent
Conditions22100.00
Logical22100.00
Non-Logical00
Event00

 LINE       64
 EXPRESSION (wr_en ? wr_data : qs)
             --1--
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT65,T249,T131
Branch Coverage for Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_prio93
Line No.TotalCoveredPercent
Branches 5 5 100.00
TERNARY 64 2 2 100.00
IF 56 3 3 100.00 



64           assign ds = wr_en ? wr_data : qs;
                               -1-  
                               ==>  
                               ==>

Branches:
-1-StatusTests
1 Covered T65,T249,T131
0 Covered T1,T2,T3 



56             if (!rst_ni) begin
               -1-  
57               q <= RESVAL;
                 ==>
58             end else if (wr_en) begin
                        -2-  
59               q <= wr_data;
                 ==>
60             end
               MISSING_ELSE
               ==>

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T65,T249,T131
0 0 Covered T1,T2,T3

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_prio94
Line No.TotalCoveredPercent
TOTAL77100.00
ALWAYS5644100.00
CONT_ASSIGN6411100.00
CONT_ASSIGN6511100.00
CONT_ASSIGN7211100.00


55                        always_ff @(posedge clk_i or negedge rst_ni) begin
56         1/1              if (!rst_ni) begin
           Tests:       T1 T2 T3 
57         1/1                q <= RESVAL;
           Tests:       T1 T2 T3 
58         1/1              end else if (wr_en) begin
           Tests:       T1 T2 T3 
59         1/1                q <= wr_data;
           Tests:       T249 T131 T252 
60                          end
                        MISSING_ELSE
61                        end
62                      
63                        // feed back out for consolidation
64         1/1            assign ds = wr_en ? wr_data : qs;
           Tests:       T249 T131 T252 
65         1/1            assign qe = wr_en;
           Tests:       T249 T131 T252 
66                      
67                        if (SwAccess == SwAccessRC) begin : gen_rc
68                          // In case of a SW RC colliding with a HW write, SW gets the value written by HW
69                          // but the register is cleared to 0. See #5416 for a discussion.
70                          assign qs = de && we ? d : q;
71                        end else begin : gen_no_rc
72         1/1              assign qs = q;
           Tests:       T249 T131 T252 
Cond Coverage for Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_prio94
TotalCoveredPercent
Conditions22100.00
Logical22100.00
Non-Logical00
Event00

 LINE       64
 EXPRESSION (wr_en ? wr_data : qs)
             --1--
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT249,T131,T252
Branch Coverage for Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_prio94
Line No.TotalCoveredPercent
Branches 5 5 100.00
TERNARY 64 2 2 100.00
IF 56 3 3 100.00 



64           assign ds = wr_en ? wr_data : qs;
                               -1-  
                               ==>  
                               ==>

Branches:
-1-StatusTests
1 Covered T249,T131,T252
0 Covered T1,T2,T3 



56             if (!rst_ni) begin
               -1-  
57               q <= RESVAL;
                 ==>
58             end else if (wr_en) begin
                        -2-  
59               q <= wr_data;
                 ==>
60             end
               MISSING_ELSE
               ==>

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T249,T131,T252
0 0 Covered T1,T2,T3

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%