Unified Coverage Report :: Module Instance :: tb.dut.u_padring.u_prim_mubi4_dec.gen_bits[0].u_prim_buf.gen_generic.u_impl_generic

Module Instance : tb.dut.u_prim_usb_diff_rx.gen_generic.u_impl_generic.obs_buf.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							obs_buf

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_prim_usb_diff_rx.gen_generic.u_impl_generic.obs_buf.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	15	1	1	100.00
CONT_ASSIGN	16	1	1	100.00

14                        logic [Width-1:0] inv;
15         1/1            assign inv = ~in_i;
           Tests:       T4 T7 T16 
16         1/1            assign out_o = ~inv;
           Tests:       T4 T7 T16