Unified Coverage Report :: Module Instance :: tb.dut.top_earlgrey.u_rv_dm.u_tlul_lc_gate_sba.u_err_en_sync.gen_buffs[1].gen_bits[2].u_prim_buf.u_secure_anchor_buf.gen_generic.u_impl_generic

Module Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_prim_reg_we_check.u_prim_buf.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_prim_buf

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_prim_reg_we_check.u_prim_buf.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	15	1	1	100.00
CONT_ASSIGN	16	1	1	100.00

14                        logic [Width-1:0] inv;
15         1/1            assign inv = ~in_i;
           Tests:       T2 T3 T5 
16         1/1            assign out_o = ~inv;
           Tests:       T2 T3 T5