Line Coverage for Module :
prim_pulse_sync
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 7 | 7 | 100.00 |
| ALWAYS | 31 | 3 | 3 | 100.00 |
| CONT_ASSIGN | 49 | 0 | 0 | |
| CONT_ASSIGN | 52 | 0 | 0 | |
| ALWAYS | 55 | 0 | 0 | |
| ALWAYS | 89 | 3 | 3 | 100.00 |
| CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
30 always_ff @(posedge clk_src_i or negedge rst_src_ni) begin
31 1/1 if (!rst_src_ni) begin
Tests: T1 T2 T3
32 1/1 src_level <= 1'b0;
Tests: T1 T2 T3
33 end else begin
34 1/1 src_level <= src_level ^ src_pulse_i;
Tests: T1 T2 T3
35 end
36 end
37
38
39 // source active must come far enough such that the destination domain has time
40 // to create a valid pulse.
41 `ifdef INC_ASSERT
42 //VCS coverage off
43 // pragma coverage off
44
45 // source active flag tracks whether there is an ongoing "toggle" event.
46 // Until this toggle event is accepted by the destination domain (negative edge of
47 // of the pulse output), the source side cannot toggle again.
48 logic effective_rst_n;
49 unreachable assign effective_rst_n = rst_src_ni && dst_pulse_o;
50
51 logic src_active_flag_d, src_active_flag_q;
52 unreachable assign src_active_flag_d = src_pulse_i || src_active_flag_q;
53
54 always_ff @(posedge clk_src_i or negedge effective_rst_n) begin
55 unreachable if (!effective_rst_n) begin
56 unreachable src_active_flag_q <= '0;
57 end else begin
58 unreachable src_active_flag_q <= src_active_flag_d;
59 end
60 end
61
62 //VCS coverage on
63 // pragma coverage on
64
65 `ASSERT(SrcPulseCheck_M, src_pulse_i |-> !src_active_flag_q, clk_src_i, !rst_src_ni)
66 `endif
67
68 //////////////////////////////////////////////////////////
69 // synchronize level signal to destination clock domain //
70 //////////////////////////////////////////////////////////
71 logic dst_level;
72
73 prim_flop_2sync #(.Width(1)) prim_flop_2sync (
74 // source clock domain
75 .d_i (src_level),
76 // destination clock domain
77 .clk_i (clk_dst_i),
78 .rst_ni (rst_dst_ni),
79 .q_o (dst_level)
80 );
81
82 ////////////////////////////////////////
83 // convert level signal back to pulse //
84 ////////////////////////////////////////
85 logic dst_level_q;
86
87 // delay dst_level by 1 cycle
88 always_ff @(posedge clk_dst_i or negedge rst_dst_ni) begin
89 1/1 if (!rst_dst_ni) begin
Tests: T1 T2 T3
90 1/1 dst_level_q <= 1'b0;
Tests: T1 T2 T3
91 end else begin
92 1/1 dst_level_q <= dst_level;
Tests: T1 T2 T3
93 end
94 end
95
96 // edge detection
97 1/1 assign dst_pulse_o = dst_level_q ^ dst_level;
Tests: T5 T23 T26
Cond Coverage for Module :
prim_pulse_sync
| Total | Covered | Percent |
|---|
| Conditions | 8 | 8 | 100.00 |
| Logical | 8 | 8 | 100.00 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 34
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T1,T2,T3 |
| 0 | 1 | Covered | T5,T23,T26 |
| 1 | 0 | Covered | T5,T23,T26 |
| 1 | 1 | Covered | T5,T23,T26 |
LINE 97
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T1,T2,T3 |
| 0 | 1 | Covered | T5,T23,T26 |
| 1 | 0 | Covered | T5,T23,T26 |
| 1 | 1 | Covered | T5,T23,T26 |
Branch Coverage for Module :
prim_pulse_sync
| Line No. | Total | Covered | Percent |
| Branches |
|
4 |
4 |
100.00 |
| IF |
31 |
2 |
2 |
100.00 |
| IF |
89 |
2 |
2 |
100.00 |
31 if (!rst_src_ni) begin
-1-
32 src_level <= 1'b0;
==>
33 end else begin
34 src_level <= src_level ^ src_pulse_i;
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T3 |
| 0 |
Covered |
T1,T2,T3 |
89 if (!rst_dst_ni) begin
-1-
90 dst_level_q <= 1'b0;
==>
91 end else begin
92 dst_level_q <= dst_level;
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T3 |
| 0 |
Covered |
T1,T2,T3 |
Assert Coverage for Module :
prim_pulse_sync
Assertion Details
DstPulseCheck_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
2147483647 |
11033 |
0 |
0 |
| T5 |
32109 |
7 |
0 |
0 |
| T6 |
30012 |
0 |
0 |
0 |
| T11 |
62864 |
0 |
0 |
0 |
| T23 |
42392 |
0 |
0 |
0 |
| T25 |
42752 |
0 |
0 |
0 |
| T26 |
0 |
2 |
0 |
0 |
| T30 |
24077 |
0 |
0 |
0 |
| T34 |
17832 |
0 |
0 |
0 |
| T68 |
54830 |
0 |
0 |
0 |
| T71 |
0 |
2 |
0 |
0 |
| T72 |
0 |
2 |
0 |
0 |
| T73 |
0 |
4 |
0 |
0 |
| T74 |
0 |
2 |
0 |
0 |
| T77 |
0 |
7 |
0 |
0 |
| T78 |
0 |
6 |
0 |
0 |
| T79 |
0 |
7 |
0 |
0 |
| T104 |
25569 |
0 |
0 |
0 |
| T105 |
17834 |
0 |
0 |
0 |
| T120 |
0 |
2 |
0 |
0 |
| T121 |
44406 |
0 |
0 |
0 |
| T124 |
0 |
4 |
0 |
0 |
| T182 |
94666 |
3 |
0 |
0 |
| T183 |
106242 |
3 |
0 |
0 |
| T396 |
121606 |
3 |
0 |
0 |
| T404 |
161558 |
2 |
0 |
0 |
| T405 |
246434 |
2 |
0 |
0 |
| T417 |
248798 |
6 |
0 |
0 |
| T418 |
103802 |
1 |
0 |
0 |
| T419 |
0 |
2 |
0 |
0 |
| T420 |
94770 |
1 |
0 |
0 |
| T421 |
142820 |
1 |
0 |
0 |
| T422 |
211580 |
0 |
0 |
0 |
SrcPulseCheck_M
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
2147483647 |
11048 |
0 |
0 |
| T5 |
62541 |
7 |
0 |
0 |
| T6 |
58497 |
0 |
0 |
0 |
| T11 |
62864 |
0 |
0 |
0 |
| T23 |
42392 |
0 |
0 |
0 |
| T25 |
42752 |
0 |
0 |
0 |
| T26 |
0 |
3 |
0 |
0 |
| T30 |
46987 |
0 |
0 |
0 |
| T34 |
356 |
0 |
0 |
0 |
| T68 |
107521 |
0 |
0 |
0 |
| T71 |
0 |
3 |
0 |
0 |
| T72 |
0 |
2 |
0 |
0 |
| T73 |
0 |
4 |
0 |
0 |
| T74 |
0 |
2 |
0 |
0 |
| T77 |
0 |
2 |
0 |
0 |
| T78 |
0 |
7 |
0 |
0 |
| T79 |
0 |
4 |
0 |
0 |
| T104 |
49992 |
0 |
0 |
0 |
| T105 |
34453 |
0 |
0 |
0 |
| T120 |
0 |
2 |
0 |
0 |
| T121 |
44406 |
0 |
0 |
0 |
| T124 |
0 |
4 |
0 |
0 |
| T182 |
94666 |
3 |
0 |
0 |
| T183 |
106242 |
3 |
0 |
0 |
| T396 |
121606 |
3 |
0 |
0 |
| T404 |
161558 |
2 |
0 |
0 |
| T405 |
246434 |
2 |
0 |
0 |
| T417 |
248798 |
6 |
0 |
0 |
| T418 |
103802 |
1 |
0 |
0 |
| T419 |
0 |
2 |
0 |
0 |
| T420 |
94770 |
1 |
0 |
0 |
| T421 |
142820 |
1 |
0 |
0 |
| T422 |
211580 |
0 |
0 |
0 |