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Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_sleep_regwen_5.wr_en_data_arb

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 u_mio_pad_sleep_regwen_5


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_sleep_regwen_6.wr_en_data_arb

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 u_mio_pad_sleep_regwen_6


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_sleep_regwen_7.wr_en_data_arb

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 u_mio_pad_sleep_regwen_7


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_sleep_regwen_8.wr_en_data_arb

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 u_mio_pad_sleep_regwen_8


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_sleep_regwen_9.wr_en_data_arb

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 u_mio_pad_sleep_regwen_9


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_sleep_regwen_10.wr_en_data_arb

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 u_mio_pad_sleep_regwen_10


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_sleep_regwen_11.wr_en_data_arb

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 u_mio_pad_sleep_regwen_11


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_sleep_regwen_12.wr_en_data_arb

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 u_mio_pad_sleep_regwen_12


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_sleep_regwen_13.wr_en_data_arb

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 u_mio_pad_sleep_regwen_13


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_sleep_regwen_14.wr_en_data_arb

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 u_mio_pad_sleep_regwen_14


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_sleep_regwen_15.wr_en_data_arb

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 u_mio_pad_sleep_regwen_15


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_sleep_regwen_16.wr_en_data_arb

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 u_mio_pad_sleep_regwen_16


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_sleep_regwen_17.wr_en_data_arb

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 u_mio_pad_sleep_regwen_17


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children

Go back
Module Instances:
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_sleep_regwen_5.wr_en_data_arb
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_sleep_regwen_6.wr_en_data_arb
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_sleep_regwen_7.wr_en_data_arb
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_sleep_regwen_8.wr_en_data_arb
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_sleep_regwen_9.wr_en_data_arb
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_sleep_regwen_10.wr_en_data_arb
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_sleep_regwen_11.wr_en_data_arb
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_sleep_regwen_12.wr_en_data_arb
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_sleep_regwen_13.wr_en_data_arb
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_sleep_regwen_14.wr_en_data_arb
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_sleep_regwen_15.wr_en_data_arb
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_sleep_regwen_16.wr_en_data_arb
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_sleep_regwen_17.wr_en_data_arb
Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_sleep_regwen_5.wr_en_data_arb
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN11311100.00
CONT_ASSIGN13511100.00

112 end else if (SwAccess == SwAccessW0C) begin : gen_w0c 113 1/1 assign wr_en = we | de; Tests: T71 T96 T97  114 if (Mubi) begin : gen_mubi 115 if (DW == 4) begin : gen_mubi4 116 assign wr_data = prim_mubi_pkg::mubi4_and_hi(prim_mubi_pkg::mubi4_t'(de ? d : q), 117 (we ? prim_mubi_pkg::mubi4_t'(wd) : 118 prim_mubi_pkg::MuBi4True)); 119 end else if (DW == 8) begin : gen_mubi8 120 assign wr_data = prim_mubi_pkg::mubi8_and_hi(prim_mubi_pkg::mubi8_t'(de ? d : q), 121 (we ? prim_mubi_pkg::mubi8_t'(wd) : 122 prim_mubi_pkg::MuBi8True)); 123 end else if (DW == 12) begin : gen_mubi12 124 assign wr_data = prim_mubi_pkg::mubi12_and_hi(prim_mubi_pkg::mubi12_t'(de ? d : q), 125 (we ? prim_mubi_pkg::mubi12_t'(wd) : 126 prim_mubi_pkg::MuBi12True)); 127 end else if (DW == 16) begin : gen_mubi16 128 assign wr_data = prim_mubi_pkg::mubi16_and_hi(prim_mubi_pkg::mubi16_t'(de ? d : q), 129 (we ? prim_mubi_pkg::mubi16_t'(wd) : 130 prim_mubi_pkg::MuBi16True)); 131 end else begin : gen_invalid_mubi 132 $error("%m: Invalid width for MuBi"); 133 end 134 end else begin : gen_non_mubi 135 1/1 assign wr_data = (de ? d : q) & (we ? wd : '1); Tests: T1 T2 T3 

Cond Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_sleep_regwen_5.wr_en_data_arb
TotalCoveredPercent
Conditions88100.00
Logical88100.00
Non-Logical00
Event00

 LINE       113
 EXPRESSION (we | de)
             -1   -2
-1--2-StatusTests
00CoveredT1,T2,T3
01Unreachable
10CoveredT71,T177,T432

 LINE       135
 EXPRESSION ((de ? d : q) & (we ? wd : '1))
             ------1-----   -------2------
-1--2-StatusTests
01CoveredT180,T427,T184
10CoveredT432,T180,T427
11CoveredT1,T2,T3

 LINE       135
 SUB-EXPRESSION (de ? d : q)
                 -1
-1-StatusTests
0CoveredT1,T2,T3
1Unreachable

 LINE       135
 SUB-EXPRESSION (we ? wd : '1)
                 -1
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT71,T177,T432
Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_sleep_regwen_6.wr_en_data_arb
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN11311100.00
CONT_ASSIGN13511100.00

112 end else if (SwAccess == SwAccessW0C) begin : gen_w0c 113 1/1 assign wr_en = we | de; Tests: T71 T96 T97  114 if (Mubi) begin : gen_mubi 115 if (DW == 4) begin : gen_mubi4 116 assign wr_data = prim_mubi_pkg::mubi4_and_hi(prim_mubi_pkg::mubi4_t'(de ? d : q), 117 (we ? prim_mubi_pkg::mubi4_t'(wd) : 118 prim_mubi_pkg::MuBi4True)); 119 end else if (DW == 8) begin : gen_mubi8 120 assign wr_data = prim_mubi_pkg::mubi8_and_hi(prim_mubi_pkg::mubi8_t'(de ? d : q), 121 (we ? prim_mubi_pkg::mubi8_t'(wd) : 122 prim_mubi_pkg::MuBi8True)); 123 end else if (DW == 12) begin : gen_mubi12 124 assign wr_data = prim_mubi_pkg::mubi12_and_hi(prim_mubi_pkg::mubi12_t'(de ? d : q), 125 (we ? prim_mubi_pkg::mubi12_t'(wd) : 126 prim_mubi_pkg::MuBi12True)); 127 end else if (DW == 16) begin : gen_mubi16 128 assign wr_data = prim_mubi_pkg::mubi16_and_hi(prim_mubi_pkg::mubi16_t'(de ? d : q), 129 (we ? prim_mubi_pkg::mubi16_t'(wd) : 130 prim_mubi_pkg::MuBi16True)); 131 end else begin : gen_invalid_mubi 132 $error("%m: Invalid width for MuBi"); 133 end 134 end else begin : gen_non_mubi 135 1/1 assign wr_data = (de ? d : q) & (we ? wd : '1); Tests: T1 T2 T3 

Cond Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_sleep_regwen_6.wr_en_data_arb
TotalCoveredPercent
Conditions88100.00
Logical88100.00
Non-Logical00
Event00

 LINE       113
 EXPRESSION (we | de)
             -1   -2
-1--2-StatusTests
00CoveredT1,T2,T3
01Unreachable
10CoveredT71,T177,T432

 LINE       135
 EXPRESSION ((de ? d : q) & (we ? wd : '1))
             ------1-----   -------2------
-1--2-StatusTests
01CoveredT71,T401,T426
10CoveredT71,T432,T401
11CoveredT1,T2,T3

 LINE       135
 SUB-EXPRESSION (de ? d : q)
                 -1
-1-StatusTests
0CoveredT1,T2,T3
1Unreachable

 LINE       135
 SUB-EXPRESSION (we ? wd : '1)
                 -1
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT71,T177,T432
Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_sleep_regwen_7.wr_en_data_arb
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN11311100.00
CONT_ASSIGN13511100.00

112 end else if (SwAccess == SwAccessW0C) begin : gen_w0c 113 1/1 assign wr_en = we | de; Tests: T71 T96 T97  114 if (Mubi) begin : gen_mubi 115 if (DW == 4) begin : gen_mubi4 116 assign wr_data = prim_mubi_pkg::mubi4_and_hi(prim_mubi_pkg::mubi4_t'(de ? d : q), 117 (we ? prim_mubi_pkg::mubi4_t'(wd) : 118 prim_mubi_pkg::MuBi4True)); 119 end else if (DW == 8) begin : gen_mubi8 120 assign wr_data = prim_mubi_pkg::mubi8_and_hi(prim_mubi_pkg::mubi8_t'(de ? d : q), 121 (we ? prim_mubi_pkg::mubi8_t'(wd) : 122 prim_mubi_pkg::MuBi8True)); 123 end else if (DW == 12) begin : gen_mubi12 124 assign wr_data = prim_mubi_pkg::mubi12_and_hi(prim_mubi_pkg::mubi12_t'(de ? d : q), 125 (we ? prim_mubi_pkg::mubi12_t'(wd) : 126 prim_mubi_pkg::MuBi12True)); 127 end else if (DW == 16) begin : gen_mubi16 128 assign wr_data = prim_mubi_pkg::mubi16_and_hi(prim_mubi_pkg::mubi16_t'(de ? d : q), 129 (we ? prim_mubi_pkg::mubi16_t'(wd) : 130 prim_mubi_pkg::MuBi16True)); 131 end else begin : gen_invalid_mubi 132 $error("%m: Invalid width for MuBi"); 133 end 134 end else begin : gen_non_mubi 135 1/1 assign wr_data = (de ? d : q) & (we ? wd : '1); Tests: T1 T2 T3 

Cond Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_sleep_regwen_7.wr_en_data_arb
TotalCoveredPercent
Conditions88100.00
Logical88100.00
Non-Logical00
Event00

 LINE       113
 EXPRESSION (we | de)
             -1   -2
-1--2-StatusTests
00CoveredT1,T2,T3
01Unreachable
10CoveredT71,T103,T177

 LINE       135
 EXPRESSION ((de ? d : q) & (we ? wd : '1))
             ------1-----   -------2------
-1--2-StatusTests
01CoveredT71,T177,T401
10CoveredT71,T103,T177
11CoveredT1,T2,T3

 LINE       135
 SUB-EXPRESSION (de ? d : q)
                 -1
-1-StatusTests
0CoveredT1,T2,T3
1Unreachable

 LINE       135
 SUB-EXPRESSION (we ? wd : '1)
                 -1
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT71,T103,T177
Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_sleep_regwen_8.wr_en_data_arb
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN11311100.00
CONT_ASSIGN13511100.00

112 end else if (SwAccess == SwAccessW0C) begin : gen_w0c 113 1/1 assign wr_en = we | de; Tests: T71 T96 T97  114 if (Mubi) begin : gen_mubi 115 if (DW == 4) begin : gen_mubi4 116 assign wr_data = prim_mubi_pkg::mubi4_and_hi(prim_mubi_pkg::mubi4_t'(de ? d : q), 117 (we ? prim_mubi_pkg::mubi4_t'(wd) : 118 prim_mubi_pkg::MuBi4True)); 119 end else if (DW == 8) begin : gen_mubi8 120 assign wr_data = prim_mubi_pkg::mubi8_and_hi(prim_mubi_pkg::mubi8_t'(de ? d : q), 121 (we ? prim_mubi_pkg::mubi8_t'(wd) : 122 prim_mubi_pkg::MuBi8True)); 123 end else if (DW == 12) begin : gen_mubi12 124 assign wr_data = prim_mubi_pkg::mubi12_and_hi(prim_mubi_pkg::mubi12_t'(de ? d : q), 125 (we ? prim_mubi_pkg::mubi12_t'(wd) : 126 prim_mubi_pkg::MuBi12True)); 127 end else if (DW == 16) begin : gen_mubi16 128 assign wr_data = prim_mubi_pkg::mubi16_and_hi(prim_mubi_pkg::mubi16_t'(de ? d : q), 129 (we ? prim_mubi_pkg::mubi16_t'(wd) : 130 prim_mubi_pkg::MuBi16True)); 131 end else begin : gen_invalid_mubi 132 $error("%m: Invalid width for MuBi"); 133 end 134 end else begin : gen_non_mubi 135 1/1 assign wr_data = (de ? d : q) & (we ? wd : '1); Tests: T1 T2 T3 

Cond Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_sleep_regwen_8.wr_en_data_arb
TotalCoveredPercent
Conditions88100.00
Logical88100.00
Non-Logical00
Event00

 LINE       113
 EXPRESSION (we | de)
             -1   -2
-1--2-StatusTests
00CoveredT1,T2,T3
01Unreachable
10CoveredT71,T177,T432

 LINE       135
 EXPRESSION ((de ? d : q) & (we ? wd : '1))
             ------1-----   -------2------
-1--2-StatusTests
01CoveredT179,T180,T427
10CoveredT179,T180,T427
11CoveredT1,T2,T3

 LINE       135
 SUB-EXPRESSION (de ? d : q)
                 -1
-1-StatusTests
0CoveredT1,T2,T3
1Unreachable

 LINE       135
 SUB-EXPRESSION (we ? wd : '1)
                 -1
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT71,T177,T432
Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_sleep_regwen_9.wr_en_data_arb
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN11311100.00
CONT_ASSIGN13511100.00

112 end else if (SwAccess == SwAccessW0C) begin : gen_w0c 113 1/1 assign wr_en = we | de; Tests: T96 T97 T98  114 if (Mubi) begin : gen_mubi 115 if (DW == 4) begin : gen_mubi4 116 assign wr_data = prim_mubi_pkg::mubi4_and_hi(prim_mubi_pkg::mubi4_t'(de ? d : q), 117 (we ? prim_mubi_pkg::mubi4_t'(wd) : 118 prim_mubi_pkg::MuBi4True)); 119 end else if (DW == 8) begin : gen_mubi8 120 assign wr_data = prim_mubi_pkg::mubi8_and_hi(prim_mubi_pkg::mubi8_t'(de ? d : q), 121 (we ? prim_mubi_pkg::mubi8_t'(wd) : 122 prim_mubi_pkg::MuBi8True)); 123 end else if (DW == 12) begin : gen_mubi12 124 assign wr_data = prim_mubi_pkg::mubi12_and_hi(prim_mubi_pkg::mubi12_t'(de ? d : q), 125 (we ? prim_mubi_pkg::mubi12_t'(wd) : 126 prim_mubi_pkg::MuBi12True)); 127 end else if (DW == 16) begin : gen_mubi16 128 assign wr_data = prim_mubi_pkg::mubi16_and_hi(prim_mubi_pkg::mubi16_t'(de ? d : q), 129 (we ? prim_mubi_pkg::mubi16_t'(wd) : 130 prim_mubi_pkg::MuBi16True)); 131 end else begin : gen_invalid_mubi 132 $error("%m: Invalid width for MuBi"); 133 end 134 end else begin : gen_non_mubi 135 1/1 assign wr_data = (de ? d : q) & (we ? wd : '1); Tests: T1 T2 T3 

Cond Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_sleep_regwen_9.wr_en_data_arb
TotalCoveredPercent
Conditions88100.00
Logical88100.00
Non-Logical00
Event00

 LINE       113
 EXPRESSION (we | de)
             -1   -2
-1--2-StatusTests
00CoveredT1,T2,T3
01Unreachable
10CoveredT177,T179,T188

 LINE       135
 EXPRESSION ((de ? d : q) & (we ? wd : '1))
             ------1-----   -------2------
-1--2-StatusTests
01CoveredT177,T179,T188
10CoveredT177,T179,T188
11CoveredT1,T2,T3

 LINE       135
 SUB-EXPRESSION (de ? d : q)
                 -1
-1-StatusTests
0CoveredT1,T2,T3
1Unreachable

 LINE       135
 SUB-EXPRESSION (we ? wd : '1)
                 -1
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT177,T179,T188
Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_sleep_regwen_10.wr_en_data_arb
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN11311100.00
CONT_ASSIGN13511100.00

112 end else if (SwAccess == SwAccessW0C) begin : gen_w0c 113 1/1 assign wr_en = we | de; Tests: T96 T97 T98  114 if (Mubi) begin : gen_mubi 115 if (DW == 4) begin : gen_mubi4 116 assign wr_data = prim_mubi_pkg::mubi4_and_hi(prim_mubi_pkg::mubi4_t'(de ? d : q), 117 (we ? prim_mubi_pkg::mubi4_t'(wd) : 118 prim_mubi_pkg::MuBi4True)); 119 end else if (DW == 8) begin : gen_mubi8 120 assign wr_data = prim_mubi_pkg::mubi8_and_hi(prim_mubi_pkg::mubi8_t'(de ? d : q), 121 (we ? prim_mubi_pkg::mubi8_t'(wd) : 122 prim_mubi_pkg::MuBi8True)); 123 end else if (DW == 12) begin : gen_mubi12 124 assign wr_data = prim_mubi_pkg::mubi12_and_hi(prim_mubi_pkg::mubi12_t'(de ? d : q), 125 (we ? prim_mubi_pkg::mubi12_t'(wd) : 126 prim_mubi_pkg::MuBi12True)); 127 end else if (DW == 16) begin : gen_mubi16 128 assign wr_data = prim_mubi_pkg::mubi16_and_hi(prim_mubi_pkg::mubi16_t'(de ? d : q), 129 (we ? prim_mubi_pkg::mubi16_t'(wd) : 130 prim_mubi_pkg::MuBi16True)); 131 end else begin : gen_invalid_mubi 132 $error("%m: Invalid width for MuBi"); 133 end 134 end else begin : gen_non_mubi 135 1/1 assign wr_data = (de ? d : q) & (we ? wd : '1); Tests: T1 T2 T3 

Cond Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_sleep_regwen_10.wr_en_data_arb
TotalCoveredPercent
Conditions88100.00
Logical88100.00
Non-Logical00
Event00

 LINE       113
 EXPRESSION (we | de)
             -1   -2
-1--2-StatusTests
00CoveredT1,T2,T3
01Unreachable
10CoveredT177,T179,T447

 LINE       135
 EXPRESSION ((de ? d : q) & (we ? wd : '1))
             ------1-----   -------2------
-1--2-StatusTests
01CoveredT179,T188,T401
10CoveredT179,T447,T188
11CoveredT1,T2,T3

 LINE       135
 SUB-EXPRESSION (de ? d : q)
                 -1
-1-StatusTests
0CoveredT1,T2,T3
1Unreachable

 LINE       135
 SUB-EXPRESSION (we ? wd : '1)
                 -1
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT177,T179,T447
Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_sleep_regwen_11.wr_en_data_arb
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN11311100.00
CONT_ASSIGN13511100.00

112 end else if (SwAccess == SwAccessW0C) begin : gen_w0c 113 1/1 assign wr_en = we | de; Tests: T96 T97 T98  114 if (Mubi) begin : gen_mubi 115 if (DW == 4) begin : gen_mubi4 116 assign wr_data = prim_mubi_pkg::mubi4_and_hi(prim_mubi_pkg::mubi4_t'(de ? d : q), 117 (we ? prim_mubi_pkg::mubi4_t'(wd) : 118 prim_mubi_pkg::MuBi4True)); 119 end else if (DW == 8) begin : gen_mubi8 120 assign wr_data = prim_mubi_pkg::mubi8_and_hi(prim_mubi_pkg::mubi8_t'(de ? d : q), 121 (we ? prim_mubi_pkg::mubi8_t'(wd) : 122 prim_mubi_pkg::MuBi8True)); 123 end else if (DW == 12) begin : gen_mubi12 124 assign wr_data = prim_mubi_pkg::mubi12_and_hi(prim_mubi_pkg::mubi12_t'(de ? d : q), 125 (we ? prim_mubi_pkg::mubi12_t'(wd) : 126 prim_mubi_pkg::MuBi12True)); 127 end else if (DW == 16) begin : gen_mubi16 128 assign wr_data = prim_mubi_pkg::mubi16_and_hi(prim_mubi_pkg::mubi16_t'(de ? d : q), 129 (we ? prim_mubi_pkg::mubi16_t'(wd) : 130 prim_mubi_pkg::MuBi16True)); 131 end else begin : gen_invalid_mubi 132 $error("%m: Invalid width for MuBi"); 133 end 134 end else begin : gen_non_mubi 135 1/1 assign wr_data = (de ? d : q) & (we ? wd : '1); Tests: T1 T2 T3 

Cond Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_sleep_regwen_11.wr_en_data_arb
TotalCoveredPercent
Conditions88100.00
Logical88100.00
Non-Logical00
Event00

 LINE       113
 EXPRESSION (we | de)
             -1   -2
-1--2-StatusTests
00CoveredT1,T2,T3
01Unreachable
10CoveredT177,T179,T188

 LINE       135
 EXPRESSION ((de ? d : q) & (we ? wd : '1))
             ------1-----   -------2------
-1--2-StatusTests
01CoveredT179,T180,T189
10CoveredT179,T180,T189
11CoveredT1,T2,T3

 LINE       135
 SUB-EXPRESSION (de ? d : q)
                 -1
-1-StatusTests
0CoveredT1,T2,T3
1Unreachable

 LINE       135
 SUB-EXPRESSION (we ? wd : '1)
                 -1
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT177,T179,T188
Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_sleep_regwen_12.wr_en_data_arb
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN11311100.00
CONT_ASSIGN13511100.00

112 end else if (SwAccess == SwAccessW0C) begin : gen_w0c 113 1/1 assign wr_en = we | de; Tests: T96 T97 T98  114 if (Mubi) begin : gen_mubi 115 if (DW == 4) begin : gen_mubi4 116 assign wr_data = prim_mubi_pkg::mubi4_and_hi(prim_mubi_pkg::mubi4_t'(de ? d : q), 117 (we ? prim_mubi_pkg::mubi4_t'(wd) : 118 prim_mubi_pkg::MuBi4True)); 119 end else if (DW == 8) begin : gen_mubi8 120 assign wr_data = prim_mubi_pkg::mubi8_and_hi(prim_mubi_pkg::mubi8_t'(de ? d : q), 121 (we ? prim_mubi_pkg::mubi8_t'(wd) : 122 prim_mubi_pkg::MuBi8True)); 123 end else if (DW == 12) begin : gen_mubi12 124 assign wr_data = prim_mubi_pkg::mubi12_and_hi(prim_mubi_pkg::mubi12_t'(de ? d : q), 125 (we ? prim_mubi_pkg::mubi12_t'(wd) : 126 prim_mubi_pkg::MuBi12True)); 127 end else if (DW == 16) begin : gen_mubi16 128 assign wr_data = prim_mubi_pkg::mubi16_and_hi(prim_mubi_pkg::mubi16_t'(de ? d : q), 129 (we ? prim_mubi_pkg::mubi16_t'(wd) : 130 prim_mubi_pkg::MuBi16True)); 131 end else begin : gen_invalid_mubi 132 $error("%m: Invalid width for MuBi"); 133 end 134 end else begin : gen_non_mubi 135 1/1 assign wr_data = (de ? d : q) & (we ? wd : '1); Tests: T1 T2 T3 

Cond Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_sleep_regwen_12.wr_en_data_arb
TotalCoveredPercent
Conditions88100.00
Logical88100.00
Non-Logical00
Event00

 LINE       113
 EXPRESSION (we | de)
             -1   -2
-1--2-StatusTests
00CoveredT1,T2,T3
01Unreachable
10CoveredT542,T177,T179

 LINE       135
 EXPRESSION ((de ? d : q) & (we ? wd : '1))
             ------1-----   -------2------
-1--2-StatusTests
01CoveredT180,T189,T184
10CoveredT542,T472,T180
11CoveredT1,T2,T3

 LINE       135
 SUB-EXPRESSION (de ? d : q)
                 -1
-1-StatusTests
0CoveredT1,T2,T3
1Unreachable

 LINE       135
 SUB-EXPRESSION (we ? wd : '1)
                 -1
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT542,T177,T179
Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_sleep_regwen_13.wr_en_data_arb
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN11311100.00
CONT_ASSIGN13511100.00

112 end else if (SwAccess == SwAccessW0C) begin : gen_w0c 113 1/1 assign wr_en = we | de; Tests: T96 T97 T98  114 if (Mubi) begin : gen_mubi 115 if (DW == 4) begin : gen_mubi4 116 assign wr_data = prim_mubi_pkg::mubi4_and_hi(prim_mubi_pkg::mubi4_t'(de ? d : q), 117 (we ? prim_mubi_pkg::mubi4_t'(wd) : 118 prim_mubi_pkg::MuBi4True)); 119 end else if (DW == 8) begin : gen_mubi8 120 assign wr_data = prim_mubi_pkg::mubi8_and_hi(prim_mubi_pkg::mubi8_t'(de ? d : q), 121 (we ? prim_mubi_pkg::mubi8_t'(wd) : 122 prim_mubi_pkg::MuBi8True)); 123 end else if (DW == 12) begin : gen_mubi12 124 assign wr_data = prim_mubi_pkg::mubi12_and_hi(prim_mubi_pkg::mubi12_t'(de ? d : q), 125 (we ? prim_mubi_pkg::mubi12_t'(wd) : 126 prim_mubi_pkg::MuBi12True)); 127 end else if (DW == 16) begin : gen_mubi16 128 assign wr_data = prim_mubi_pkg::mubi16_and_hi(prim_mubi_pkg::mubi16_t'(de ? d : q), 129 (we ? prim_mubi_pkg::mubi16_t'(wd) : 130 prim_mubi_pkg::MuBi16True)); 131 end else begin : gen_invalid_mubi 132 $error("%m: Invalid width for MuBi"); 133 end 134 end else begin : gen_non_mubi 135 1/1 assign wr_data = (de ? d : q) & (we ? wd : '1); Tests: T1 T2 T3 

Cond Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_sleep_regwen_13.wr_en_data_arb
TotalCoveredPercent
Conditions88100.00
Logical88100.00
Non-Logical00
Event00

 LINE       113
 EXPRESSION (we | de)
             -1   -2
-1--2-StatusTests
00CoveredT1,T2,T3
01Unreachable
10CoveredT177,T179,T188

 LINE       135
 EXPRESSION ((de ? d : q) & (we ? wd : '1))
             ------1-----   -------2------
-1--2-StatusTests
01CoveredT177,T179,T188
10CoveredT177,T179,T188
11CoveredT1,T2,T3

 LINE       135
 SUB-EXPRESSION (de ? d : q)
                 -1
-1-StatusTests
0CoveredT1,T2,T3
1Unreachable

 LINE       135
 SUB-EXPRESSION (we ? wd : '1)
                 -1
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT177,T179,T188
Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_sleep_regwen_14.wr_en_data_arb
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN11311100.00
CONT_ASSIGN13511100.00

112 end else if (SwAccess == SwAccessW0C) begin : gen_w0c 113 1/1 assign wr_en = we | de; Tests: T96 T97 T98  114 if (Mubi) begin : gen_mubi 115 if (DW == 4) begin : gen_mubi4 116 assign wr_data = prim_mubi_pkg::mubi4_and_hi(prim_mubi_pkg::mubi4_t'(de ? d : q), 117 (we ? prim_mubi_pkg::mubi4_t'(wd) : 118 prim_mubi_pkg::MuBi4True)); 119 end else if (DW == 8) begin : gen_mubi8 120 assign wr_data = prim_mubi_pkg::mubi8_and_hi(prim_mubi_pkg::mubi8_t'(de ? d : q), 121 (we ? prim_mubi_pkg::mubi8_t'(wd) : 122 prim_mubi_pkg::MuBi8True)); 123 end else if (DW == 12) begin : gen_mubi12 124 assign wr_data = prim_mubi_pkg::mubi12_and_hi(prim_mubi_pkg::mubi12_t'(de ? d : q), 125 (we ? prim_mubi_pkg::mubi12_t'(wd) : 126 prim_mubi_pkg::MuBi12True)); 127 end else if (DW == 16) begin : gen_mubi16 128 assign wr_data = prim_mubi_pkg::mubi16_and_hi(prim_mubi_pkg::mubi16_t'(de ? d : q), 129 (we ? prim_mubi_pkg::mubi16_t'(wd) : 130 prim_mubi_pkg::MuBi16True)); 131 end else begin : gen_invalid_mubi 132 $error("%m: Invalid width for MuBi"); 133 end 134 end else begin : gen_non_mubi 135 1/1 assign wr_data = (de ? d : q) & (we ? wd : '1); Tests: T1 T2 T3 

Cond Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_sleep_regwen_14.wr_en_data_arb
TotalCoveredPercent
Conditions88100.00
Logical88100.00
Non-Logical00
Event00

 LINE       113
 EXPRESSION (we | de)
             -1   -2
-1--2-StatusTests
00CoveredT1,T2,T3
01Unreachable
10CoveredT177,T432,T579

 LINE       135
 EXPRESSION ((de ? d : q) & (we ? wd : '1))
             ------1-----   -------2------
-1--2-StatusTests
01CoveredT179,T189,T426
10CoveredT179,T189,T426
11CoveredT1,T2,T3

 LINE       135
 SUB-EXPRESSION (de ? d : q)
                 -1
-1-StatusTests
0CoveredT1,T2,T3
1Unreachable

 LINE       135
 SUB-EXPRESSION (we ? wd : '1)
                 -1
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT177,T432,T579
Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_sleep_regwen_15.wr_en_data_arb
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN11311100.00
CONT_ASSIGN13511100.00

112 end else if (SwAccess == SwAccessW0C) begin : gen_w0c 113 1/1 assign wr_en = we | de; Tests: T96 T97 T98  114 if (Mubi) begin : gen_mubi 115 if (DW == 4) begin : gen_mubi4 116 assign wr_data = prim_mubi_pkg::mubi4_and_hi(prim_mubi_pkg::mubi4_t'(de ? d : q), 117 (we ? prim_mubi_pkg::mubi4_t'(wd) : 118 prim_mubi_pkg::MuBi4True)); 119 end else if (DW == 8) begin : gen_mubi8 120 assign wr_data = prim_mubi_pkg::mubi8_and_hi(prim_mubi_pkg::mubi8_t'(de ? d : q), 121 (we ? prim_mubi_pkg::mubi8_t'(wd) : 122 prim_mubi_pkg::MuBi8True)); 123 end else if (DW == 12) begin : gen_mubi12 124 assign wr_data = prim_mubi_pkg::mubi12_and_hi(prim_mubi_pkg::mubi12_t'(de ? d : q), 125 (we ? prim_mubi_pkg::mubi12_t'(wd) : 126 prim_mubi_pkg::MuBi12True)); 127 end else if (DW == 16) begin : gen_mubi16 128 assign wr_data = prim_mubi_pkg::mubi16_and_hi(prim_mubi_pkg::mubi16_t'(de ? d : q), 129 (we ? prim_mubi_pkg::mubi16_t'(wd) : 130 prim_mubi_pkg::MuBi16True)); 131 end else begin : gen_invalid_mubi 132 $error("%m: Invalid width for MuBi"); 133 end 134 end else begin : gen_non_mubi 135 1/1 assign wr_data = (de ? d : q) & (we ? wd : '1); Tests: T1 T2 T3 

Cond Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_sleep_regwen_15.wr_en_data_arb
TotalCoveredPercent
Conditions88100.00
Logical88100.00
Non-Logical00
Event00

 LINE       113
 EXPRESSION (we | de)
             -1   -2
-1--2-StatusTests
00CoveredT1,T2,T3
01Unreachable
10CoveredT177,T179,T188

 LINE       135
 EXPRESSION ((de ? d : q) & (we ? wd : '1))
             ------1-----   -------2------
-1--2-StatusTests
01CoveredT177,T188,T427
10CoveredT177,T188,T427
11CoveredT1,T2,T3

 LINE       135
 SUB-EXPRESSION (de ? d : q)
                 -1
-1-StatusTests
0CoveredT1,T2,T3
1Unreachable

 LINE       135
 SUB-EXPRESSION (we ? wd : '1)
                 -1
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT177,T179,T188
Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_sleep_regwen_16.wr_en_data_arb
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN11311100.00
CONT_ASSIGN13511100.00

112 end else if (SwAccess == SwAccessW0C) begin : gen_w0c 113 1/1 assign wr_en = we | de; Tests: T96 T97 T98  114 if (Mubi) begin : gen_mubi 115 if (DW == 4) begin : gen_mubi4 116 assign wr_data = prim_mubi_pkg::mubi4_and_hi(prim_mubi_pkg::mubi4_t'(de ? d : q), 117 (we ? prim_mubi_pkg::mubi4_t'(wd) : 118 prim_mubi_pkg::MuBi4True)); 119 end else if (DW == 8) begin : gen_mubi8 120 assign wr_data = prim_mubi_pkg::mubi8_and_hi(prim_mubi_pkg::mubi8_t'(de ? d : q), 121 (we ? prim_mubi_pkg::mubi8_t'(wd) : 122 prim_mubi_pkg::MuBi8True)); 123 end else if (DW == 12) begin : gen_mubi12 124 assign wr_data = prim_mubi_pkg::mubi12_and_hi(prim_mubi_pkg::mubi12_t'(de ? d : q), 125 (we ? prim_mubi_pkg::mubi12_t'(wd) : 126 prim_mubi_pkg::MuBi12True)); 127 end else if (DW == 16) begin : gen_mubi16 128 assign wr_data = prim_mubi_pkg::mubi16_and_hi(prim_mubi_pkg::mubi16_t'(de ? d : q), 129 (we ? prim_mubi_pkg::mubi16_t'(wd) : 130 prim_mubi_pkg::MuBi16True)); 131 end else begin : gen_invalid_mubi 132 $error("%m: Invalid width for MuBi"); 133 end 134 end else begin : gen_non_mubi 135 1/1 assign wr_data = (de ? d : q) & (we ? wd : '1); Tests: T1 T2 T3 

Cond Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_sleep_regwen_16.wr_en_data_arb
TotalCoveredPercent
Conditions88100.00
Logical88100.00
Non-Logical00
Event00

 LINE       113
 EXPRESSION (we | de)
             -1   -2
-1--2-StatusTests
00CoveredT1,T2,T3
01Unreachable
10CoveredT177,T541,T179

 LINE       135
 EXPRESSION ((de ? d : q) & (we ? wd : '1))
             ------1-----   -------2------
-1--2-StatusTests
01CoveredT177,T401,T180
10CoveredT177,T541,T401
11CoveredT1,T2,T3

 LINE       135
 SUB-EXPRESSION (de ? d : q)
                 -1
-1-StatusTests
0CoveredT1,T2,T3
1Unreachable

 LINE       135
 SUB-EXPRESSION (we ? wd : '1)
                 -1
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT177,T541,T179
Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_sleep_regwen_17.wr_en_data_arb
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN11311100.00
CONT_ASSIGN13511100.00

112 end else if (SwAccess == SwAccessW0C) begin : gen_w0c 113 1/1 assign wr_en = we | de; Tests: T96 T97 T98  114 if (Mubi) begin : gen_mubi 115 if (DW == 4) begin : gen_mubi4 116 assign wr_data = prim_mubi_pkg::mubi4_and_hi(prim_mubi_pkg::mubi4_t'(de ? d : q), 117 (we ? prim_mubi_pkg::mubi4_t'(wd) : 118 prim_mubi_pkg::MuBi4True)); 119 end else if (DW == 8) begin : gen_mubi8 120 assign wr_data = prim_mubi_pkg::mubi8_and_hi(prim_mubi_pkg::mubi8_t'(de ? d : q), 121 (we ? prim_mubi_pkg::mubi8_t'(wd) : 122 prim_mubi_pkg::MuBi8True)); 123 end else if (DW == 12) begin : gen_mubi12 124 assign wr_data = prim_mubi_pkg::mubi12_and_hi(prim_mubi_pkg::mubi12_t'(de ? d : q), 125 (we ? prim_mubi_pkg::mubi12_t'(wd) : 126 prim_mubi_pkg::MuBi12True)); 127 end else if (DW == 16) begin : gen_mubi16 128 assign wr_data = prim_mubi_pkg::mubi16_and_hi(prim_mubi_pkg::mubi16_t'(de ? d : q), 129 (we ? prim_mubi_pkg::mubi16_t'(wd) : 130 prim_mubi_pkg::MuBi16True)); 131 end else begin : gen_invalid_mubi 132 $error("%m: Invalid width for MuBi"); 133 end 134 end else begin : gen_non_mubi 135 1/1 assign wr_data = (de ? d : q) & (we ? wd : '1); Tests: T1 T2 T3 

Cond Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_sleep_regwen_17.wr_en_data_arb
TotalCoveredPercent
Conditions88100.00
Logical88100.00
Non-Logical00
Event00

 LINE       113
 EXPRESSION (we | de)
             -1   -2
-1--2-StatusTests
00CoveredT1,T2,T3
01Unreachable
10CoveredT177,T432,T179

 LINE       135
 EXPRESSION ((de ? d : q) & (we ? wd : '1))
             ------1-----   -------2------
-1--2-StatusTests
01CoveredT177,T179,T401
10CoveredT177,T179,T401
11CoveredT1,T2,T3

 LINE       135
 SUB-EXPRESSION (de ? d : q)
                 -1
-1-StatusTests
0CoveredT1,T2,T3
1Unreachable

 LINE       135
 SUB-EXPRESSION (we ? wd : '1)
                 -1
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT177,T432,T179
0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%