Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_7.wr_en_data_arb
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 2 | 2 | 100.00 |
| CONT_ASSIGN | 33 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 34 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 39 | 0 | 0 | |
32 if (SwAccess inside {SwAccessRW, SwAccessWO}) begin : gen_w
33 1/1 assign wr_en = we | de;
Tests: T177 T179 T188
34 1/1 assign wr_data = (we == 1'b1) ? wd : d; // SW higher priority
Tests: T177 T179 T188
35 // Unused q - Prevent lint errors.
36 logic [DW-1:0] unused_q;
37 //VCS coverage off
38 // pragma coverage off
39 unreachable assign unused_q = q;
Cond Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_7.wr_en_data_arb
| Total | Covered | Percent |
|---|
| Conditions | 6 | 6 | 100.00 |
| Logical | 6 | 6 | 100.00 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 33
EXPRESSION (we | de)
-1 -2
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T1,T2,T3 |
| 0 | 1 | Unreachable | |
| 1 | 0 | Covered | T177,T179,T188 |
LINE 34
EXPRESSION ((we == 1'b1) ? wd : d)
------1-----
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T177,T179,T188 |
LINE 34
SUB-EXPRESSION (we == 1'b1)
------1-----
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T177,T179,T188 |
Branch Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_7.wr_en_data_arb
| Line No. | Total | Covered | Percent |
| Branches |
|
2 |
2 |
100.00 |
| TERNARY |
34 |
2 |
2 |
100.00 |
34 assign wr_data = (we == 1'b1) ? wd : d; // SW higher priority
-1-
==>
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T177,T179,T188 |
| 0 |
Covered |
T1,T2,T3 |
Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_padsel_0.wr_en_data_arb
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 2 | 2 | 100.00 |
| CONT_ASSIGN | 33 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 34 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 39 | 0 | 0 | |
32 if (SwAccess inside {SwAccessRW, SwAccessWO}) begin : gen_w
33 1/1 assign wr_en = we | de;
Tests: T6 T25 T76
34 1/1 assign wr_data = (we == 1'b1) ? wd : d; // SW higher priority
Tests: T1 T2 T3
35 // Unused q - Prevent lint errors.
36 logic [DW-1:0] unused_q;
37 //VCS coverage off
38 // pragma coverage off
39 unreachable assign unused_q = q;
Cond Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_padsel_0.wr_en_data_arb
| Total | Covered | Percent |
|---|
| Conditions | 6 | 6 | 100.00 |
| Logical | 6 | 6 | 100.00 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 33
EXPRESSION (we | de)
-1 -2
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T1,T2,T3 |
| 0 | 1 | Unreachable | |
| 1 | 0 | Covered | T6,T25,T76 |
LINE 34
EXPRESSION ((we == 1'b1) ? wd : d)
------1-----
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T6,T25,T76 |
LINE 34
SUB-EXPRESSION (we == 1'b1)
------1-----
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T6,T25,T76 |
Branch Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_padsel_0.wr_en_data_arb
| Line No. | Total | Covered | Percent |
| Branches |
|
2 |
2 |
100.00 |
| TERNARY |
34 |
2 |
2 |
100.00 |
34 assign wr_data = (we == 1'b1) ? wd : d; // SW higher priority
-1-
==>
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T6,T25,T76 |
| 0 |
Covered |
T1,T2,T3 |
Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_padsel_1.wr_en_data_arb
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 2 | 2 | 100.00 |
| CONT_ASSIGN | 33 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 34 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 39 | 0 | 0 | |
32 if (SwAccess inside {SwAccessRW, SwAccessWO}) begin : gen_w
33 1/1 assign wr_en = we | de;
Tests: T96 T97 T98
34 1/1 assign wr_data = (we == 1'b1) ? wd : d; // SW higher priority
Tests: T1 T2 T3
35 // Unused q - Prevent lint errors.
36 logic [DW-1:0] unused_q;
37 //VCS coverage off
38 // pragma coverage off
39 unreachable assign unused_q = q;
Cond Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_padsel_1.wr_en_data_arb
| Total | Covered | Percent |
|---|
| Conditions | 6 | 6 | 100.00 |
| Logical | 6 | 6 | 100.00 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 33
EXPRESSION (we | de)
-1 -2
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T1,T2,T3 |
| 0 | 1 | Unreachable | |
| 1 | 0 | Covered | T188,T401,T180 |
LINE 34
EXPRESSION ((we == 1'b1) ? wd : d)
------1-----
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T188,T401,T180 |
LINE 34
SUB-EXPRESSION (we == 1'b1)
------1-----
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T188,T401,T180 |
Branch Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_padsel_1.wr_en_data_arb
| Line No. | Total | Covered | Percent |
| Branches |
|
2 |
2 |
100.00 |
| TERNARY |
34 |
2 |
2 |
100.00 |
34 assign wr_data = (we == 1'b1) ? wd : d; // SW higher priority
-1-
==>
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T188,T401,T180 |
| 0 |
Covered |
T1,T2,T3 |
Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_padsel_2.wr_en_data_arb
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 2 | 2 | 100.00 |
| CONT_ASSIGN | 33 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 34 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 39 | 0 | 0 | |
32 if (SwAccess inside {SwAccessRW, SwAccessWO}) begin : gen_w
33 1/1 assign wr_en = we | de;
Tests: T96 T97 T98
34 1/1 assign wr_data = (we == 1'b1) ? wd : d; // SW higher priority
Tests: T1 T2 T3
35 // Unused q - Prevent lint errors.
36 logic [DW-1:0] unused_q;
37 //VCS coverage off
38 // pragma coverage off
39 unreachable assign unused_q = q;
Cond Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_padsel_2.wr_en_data_arb
| Total | Covered | Percent |
|---|
| Conditions | 6 | 6 | 100.00 |
| Logical | 6 | 6 | 100.00 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 33
EXPRESSION (we | de)
-1 -2
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T1,T2,T3 |
| 0 | 1 | Unreachable | |
| 1 | 0 | Covered | T439,T445,T401 |
LINE 34
EXPRESSION ((we == 1'b1) ? wd : d)
------1-----
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T439,T445,T401 |
LINE 34
SUB-EXPRESSION (we == 1'b1)
------1-----
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T439,T445,T401 |
Branch Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_padsel_2.wr_en_data_arb
| Line No. | Total | Covered | Percent |
| Branches |
|
2 |
2 |
100.00 |
| TERNARY |
34 |
2 |
2 |
100.00 |
34 assign wr_data = (we == 1'b1) ? wd : d; // SW higher priority
-1-
==>
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T439,T445,T401 |
| 0 |
Covered |
T1,T2,T3 |
Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_padsel_3.wr_en_data_arb
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 2 | 2 | 100.00 |
| CONT_ASSIGN | 33 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 34 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 39 | 0 | 0 | |
32 if (SwAccess inside {SwAccessRW, SwAccessWO}) begin : gen_w
33 1/1 assign wr_en = we | de;
Tests: T23 T96 T97
34 1/1 assign wr_data = (we == 1'b1) ? wd : d; // SW higher priority
Tests: T1 T2 T3
35 // Unused q - Prevent lint errors.
36 logic [DW-1:0] unused_q;
37 //VCS coverage off
38 // pragma coverage off
39 unreachable assign unused_q = q;
Cond Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_padsel_3.wr_en_data_arb
| Total | Covered | Percent |
|---|
| Conditions | 6 | 6 | 100.00 |
| Logical | 6 | 6 | 100.00 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 33
EXPRESSION (we | de)
-1 -2
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T1,T2,T3 |
| 0 | 1 | Unreachable | |
| 1 | 0 | Covered | T23,T177,T179 |
LINE 34
EXPRESSION ((we == 1'b1) ? wd : d)
------1-----
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T23,T177,T179 |
LINE 34
SUB-EXPRESSION (we == 1'b1)
------1-----
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T23,T177,T179 |
Branch Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_padsel_3.wr_en_data_arb
| Line No. | Total | Covered | Percent |
| Branches |
|
2 |
2 |
100.00 |
| TERNARY |
34 |
2 |
2 |
100.00 |
34 assign wr_data = (we == 1'b1) ? wd : d; // SW higher priority
-1-
==>
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T23,T177,T179 |
| 0 |
Covered |
T1,T2,T3 |
Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_padsel_4.wr_en_data_arb
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 2 | 2 | 100.00 |
| CONT_ASSIGN | 33 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 34 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 39 | 0 | 0 | |
32 if (SwAccess inside {SwAccessRW, SwAccessWO}) begin : gen_w
33 1/1 assign wr_en = we | de;
Tests: T96 T97 T98
34 1/1 assign wr_data = (we == 1'b1) ? wd : d; // SW higher priority
Tests: T1 T2 T3
35 // Unused q - Prevent lint errors.
36 logic [DW-1:0] unused_q;
37 //VCS coverage off
38 // pragma coverage off
39 unreachable assign unused_q = q;
Cond Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_padsel_4.wr_en_data_arb
| Total | Covered | Percent |
|---|
| Conditions | 6 | 6 | 100.00 |
| Logical | 6 | 6 | 100.00 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 33
EXPRESSION (we | de)
-1 -2
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T1,T2,T3 |
| 0 | 1 | Unreachable | |
| 1 | 0 | Covered | T177,T541,T179 |
LINE 34
EXPRESSION ((we == 1'b1) ? wd : d)
------1-----
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T177,T541,T179 |
LINE 34
SUB-EXPRESSION (we == 1'b1)
------1-----
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T177,T541,T179 |
Branch Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_padsel_4.wr_en_data_arb
| Line No. | Total | Covered | Percent |
| Branches |
|
2 |
2 |
100.00 |
| TERNARY |
34 |
2 |
2 |
100.00 |
34 assign wr_data = (we == 1'b1) ? wd : d; // SW higher priority
-1-
==>
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T177,T541,T179 |
| 0 |
Covered |
T1,T2,T3 |
Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_padsel_5.wr_en_data_arb
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 2 | 2 | 100.00 |
| CONT_ASSIGN | 33 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 34 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 39 | 0 | 0 | |
32 if (SwAccess inside {SwAccessRW, SwAccessWO}) begin : gen_w
33 1/1 assign wr_en = we | de;
Tests: T77 T78 T79
34 1/1 assign wr_data = (we == 1'b1) ? wd : d; // SW higher priority
Tests: T1 T2 T3
35 // Unused q - Prevent lint errors.
36 logic [DW-1:0] unused_q;
37 //VCS coverage off
38 // pragma coverage off
39 unreachable assign unused_q = q;
Cond Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_padsel_5.wr_en_data_arb
| Total | Covered | Percent |
|---|
| Conditions | 6 | 6 | 100.00 |
| Logical | 6 | 6 | 100.00 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 33
EXPRESSION (we | de)
-1 -2
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T1,T2,T3 |
| 0 | 1 | Unreachable | |
| 1 | 0 | Covered | T77,T78,T79 |
LINE 34
EXPRESSION ((we == 1'b1) ? wd : d)
------1-----
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T77,T78,T79 |
LINE 34
SUB-EXPRESSION (we == 1'b1)
------1-----
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T77,T78,T79 |
Branch Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_padsel_5.wr_en_data_arb
| Line No. | Total | Covered | Percent |
| Branches |
|
2 |
2 |
100.00 |
| TERNARY |
34 |
2 |
2 |
100.00 |
34 assign wr_data = (we == 1'b1) ? wd : d; // SW higher priority
-1-
==>
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T77,T78,T79 |
| 0 |
Covered |
T1,T2,T3 |
Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_padsel_6.wr_en_data_arb
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 2 | 2 | 100.00 |
| CONT_ASSIGN | 33 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 34 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 39 | 0 | 0 | |
32 if (SwAccess inside {SwAccessRW, SwAccessWO}) begin : gen_w
33 1/1 assign wr_en = we | de;
Tests: T96 T97 T98
34 1/1 assign wr_data = (we == 1'b1) ? wd : d; // SW higher priority
Tests: T1 T2 T3
35 // Unused q - Prevent lint errors.
36 logic [DW-1:0] unused_q;
37 //VCS coverage off
38 // pragma coverage off
39 unreachable assign unused_q = q;
Cond Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_padsel_6.wr_en_data_arb
| Total | Covered | Percent |
|---|
| Conditions | 6 | 6 | 100.00 |
| Logical | 6 | 6 | 100.00 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 33
EXPRESSION (we | de)
-1 -2
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T1,T2,T3 |
| 0 | 1 | Unreachable | |
| 1 | 0 | Covered | T177,T179,T188 |
LINE 34
EXPRESSION ((we == 1'b1) ? wd : d)
------1-----
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T177,T179,T188 |
LINE 34
SUB-EXPRESSION (we == 1'b1)
------1-----
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T177,T179,T188 |
Branch Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_padsel_6.wr_en_data_arb
| Line No. | Total | Covered | Percent |
| Branches |
|
2 |
2 |
100.00 |
| TERNARY |
34 |
2 |
2 |
100.00 |
34 assign wr_data = (we == 1'b1) ? wd : d; // SW higher priority
-1-
==>
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T177,T179,T188 |
| 0 |
Covered |
T1,T2,T3 |
Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_padsel_7.wr_en_data_arb
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 2 | 2 | 100.00 |
| CONT_ASSIGN | 33 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 34 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 39 | 0 | 0 | |
32 if (SwAccess inside {SwAccessRW, SwAccessWO}) begin : gen_w
33 1/1 assign wr_en = we | de;
Tests: T4 T24 T96
34 1/1 assign wr_data = (we == 1'b1) ? wd : d; // SW higher priority
Tests: T1 T2 T3
35 // Unused q - Prevent lint errors.
36 logic [DW-1:0] unused_q;
37 //VCS coverage off
38 // pragma coverage off
39 unreachable assign unused_q = q;
Cond Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_padsel_7.wr_en_data_arb
| Total | Covered | Percent |
|---|
| Conditions | 6 | 6 | 100.00 |
| Logical | 6 | 6 | 100.00 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 33
EXPRESSION (we | de)
-1 -2
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T1,T2,T3 |
| 0 | 1 | Unreachable | |
| 1 | 0 | Covered | T4,T24,T177 |
LINE 34
EXPRESSION ((we == 1'b1) ? wd : d)
------1-----
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T4,T24,T177 |
LINE 34
SUB-EXPRESSION (we == 1'b1)
------1-----
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T4,T24,T177 |
Branch Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_padsel_7.wr_en_data_arb
| Line No. | Total | Covered | Percent |
| Branches |
|
2 |
2 |
100.00 |
| TERNARY |
34 |
2 |
2 |
100.00 |
34 assign wr_data = (we == 1'b1) ? wd : d; // SW higher priority
-1-
==>
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T4,T24,T177 |
| 0 |
Covered |
T1,T2,T3 |
Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_cause_cause_0.wr_en_data_arb
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 2 | 2 | 100.00 |
| CONT_ASSIGN | 113 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 135 | 1 | 1 | 100.00 |
112 end else if (SwAccess == SwAccessW0C) begin : gen_w0c
113 1/1 assign wr_en = we | de;
Tests: T6 T25 T77
114 if (Mubi) begin : gen_mubi
115 if (DW == 4) begin : gen_mubi4
116 assign wr_data = prim_mubi_pkg::mubi4_and_hi(prim_mubi_pkg::mubi4_t'(de ? d : q),
117 (we ? prim_mubi_pkg::mubi4_t'(wd) :
118 prim_mubi_pkg::MuBi4True));
119 end else if (DW == 8) begin : gen_mubi8
120 assign wr_data = prim_mubi_pkg::mubi8_and_hi(prim_mubi_pkg::mubi8_t'(de ? d : q),
121 (we ? prim_mubi_pkg::mubi8_t'(wd) :
122 prim_mubi_pkg::MuBi8True));
123 end else if (DW == 12) begin : gen_mubi12
124 assign wr_data = prim_mubi_pkg::mubi12_and_hi(prim_mubi_pkg::mubi12_t'(de ? d : q),
125 (we ? prim_mubi_pkg::mubi12_t'(wd) :
126 prim_mubi_pkg::MuBi12True));
127 end else if (DW == 16) begin : gen_mubi16
128 assign wr_data = prim_mubi_pkg::mubi16_and_hi(prim_mubi_pkg::mubi16_t'(de ? d : q),
129 (we ? prim_mubi_pkg::mubi16_t'(wd) :
130 prim_mubi_pkg::MuBi16True));
131 end else begin : gen_invalid_mubi
132 $error("%m: Invalid width for MuBi");
133 end
134 end else begin : gen_non_mubi
135 1/1 assign wr_data = (de ? d : q) & (we ? wd : '1);
Tests: T6 T25 T77
Cond Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_cause_cause_0.wr_en_data_arb
| Total | Covered | Percent |
|---|
| Conditions | 10 | 10 | 100.00 |
| Logical | 10 | 10 | 100.00 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 113
EXPRESSION (we | de)
-1 -2
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T1,T2,T3 |
| 0 | 1 | Covered | T6,T25,T76 |
| 1 | 0 | Covered | T6,T25,T77 |
LINE 135
EXPRESSION ((de ? d : q) & (we ? wd : '1))
------1----- -------2------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T6,T25,T76 |
| 1 | 1 | Covered | T6,T25,T76 |
LINE 135
SUB-EXPRESSION (de ? d : q)
-1
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T6,T25,T76 |
LINE 135
SUB-EXPRESSION (we ? wd : '1)
-1
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T6,T25,T77 |
Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_cause_cause_1.wr_en_data_arb
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 2 | 2 | 100.00 |
| CONT_ASSIGN | 113 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 135 | 1 | 1 | 100.00 |
112 end else if (SwAccess == SwAccessW0C) begin : gen_w0c
113 1/1 assign wr_en = we | de;
Tests: T6 T25 T77
114 if (Mubi) begin : gen_mubi
115 if (DW == 4) begin : gen_mubi4
116 assign wr_data = prim_mubi_pkg::mubi4_and_hi(prim_mubi_pkg::mubi4_t'(de ? d : q),
117 (we ? prim_mubi_pkg::mubi4_t'(wd) :
118 prim_mubi_pkg::MuBi4True));
119 end else if (DW == 8) begin : gen_mubi8
120 assign wr_data = prim_mubi_pkg::mubi8_and_hi(prim_mubi_pkg::mubi8_t'(de ? d : q),
121 (we ? prim_mubi_pkg::mubi8_t'(wd) :
122 prim_mubi_pkg::MuBi8True));
123 end else if (DW == 12) begin : gen_mubi12
124 assign wr_data = prim_mubi_pkg::mubi12_and_hi(prim_mubi_pkg::mubi12_t'(de ? d : q),
125 (we ? prim_mubi_pkg::mubi12_t'(wd) :
126 prim_mubi_pkg::MuBi12True));
127 end else if (DW == 16) begin : gen_mubi16
128 assign wr_data = prim_mubi_pkg::mubi16_and_hi(prim_mubi_pkg::mubi16_t'(de ? d : q),
129 (we ? prim_mubi_pkg::mubi16_t'(wd) :
130 prim_mubi_pkg::MuBi16True));
131 end else begin : gen_invalid_mubi
132 $error("%m: Invalid width for MuBi");
133 end
134 end else begin : gen_non_mubi
135 1/1 assign wr_data = (de ? d : q) & (we ? wd : '1);
Tests: T6 T25 T77
Cond Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_cause_cause_1.wr_en_data_arb
| Total | Covered | Percent |
|---|
| Conditions | 10 | 6 | 60.00 |
| Logical | 10 | 6 | 60.00 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 113
EXPRESSION (we | de)
-1 -2
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T1,T2,T3 |
| 0 | 1 | Not Covered | |
| 1 | 0 | Covered | T6,T25,T77 |
LINE 135
EXPRESSION ((de ? d : q) & (we ? wd : '1))
------1----- -------2------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Not Covered | |
| 1 | 1 | Not Covered | |
LINE 135
SUB-EXPRESSION (de ? d : q)
-1
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Not Covered | |
LINE 135
SUB-EXPRESSION (we ? wd : '1)
-1
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T6,T25,T77 |
Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_cause_cause_2.wr_en_data_arb
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 2 | 2 | 100.00 |
| CONT_ASSIGN | 113 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 135 | 1 | 1 | 100.00 |
112 end else if (SwAccess == SwAccessW0C) begin : gen_w0c
113 1/1 assign wr_en = we | de;
Tests: T6 T25 T77
114 if (Mubi) begin : gen_mubi
115 if (DW == 4) begin : gen_mubi4
116 assign wr_data = prim_mubi_pkg::mubi4_and_hi(prim_mubi_pkg::mubi4_t'(de ? d : q),
117 (we ? prim_mubi_pkg::mubi4_t'(wd) :
118 prim_mubi_pkg::MuBi4True));
119 end else if (DW == 8) begin : gen_mubi8
120 assign wr_data = prim_mubi_pkg::mubi8_and_hi(prim_mubi_pkg::mubi8_t'(de ? d : q),
121 (we ? prim_mubi_pkg::mubi8_t'(wd) :
122 prim_mubi_pkg::MuBi8True));
123 end else if (DW == 12) begin : gen_mubi12
124 assign wr_data = prim_mubi_pkg::mubi12_and_hi(prim_mubi_pkg::mubi12_t'(de ? d : q),
125 (we ? prim_mubi_pkg::mubi12_t'(wd) :
126 prim_mubi_pkg::MuBi12True));
127 end else if (DW == 16) begin : gen_mubi16
128 assign wr_data = prim_mubi_pkg::mubi16_and_hi(prim_mubi_pkg::mubi16_t'(de ? d : q),
129 (we ? prim_mubi_pkg::mubi16_t'(wd) :
130 prim_mubi_pkg::MuBi16True));
131 end else begin : gen_invalid_mubi
132 $error("%m: Invalid width for MuBi");
133 end
134 end else begin : gen_non_mubi
135 1/1 assign wr_data = (de ? d : q) & (we ? wd : '1);
Tests: T6 T25 T77
Cond Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_cause_cause_2.wr_en_data_arb
| Total | Covered | Percent |
|---|
| Conditions | 10 | 6 | 60.00 |
| Logical | 10 | 6 | 60.00 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 113
EXPRESSION (we | de)
-1 -2
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T1,T2,T3 |
| 0 | 1 | Not Covered | |
| 1 | 0 | Covered | T6,T25,T77 |
LINE 135
EXPRESSION ((de ? d : q) & (we ? wd : '1))
------1----- -------2------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Not Covered | |
| 1 | 1 | Not Covered | |
LINE 135
SUB-EXPRESSION (de ? d : q)
-1
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Not Covered | |
LINE 135
SUB-EXPRESSION (we ? wd : '1)
-1
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T6,T25,T77 |
Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_cause_cause_3.wr_en_data_arb
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 2 | 2 | 100.00 |
| CONT_ASSIGN | 113 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 135 | 1 | 1 | 100.00 |
112 end else if (SwAccess == SwAccessW0C) begin : gen_w0c
113 1/1 assign wr_en = we | de;
Tests: T6 T25 T77
114 if (Mubi) begin : gen_mubi
115 if (DW == 4) begin : gen_mubi4
116 assign wr_data = prim_mubi_pkg::mubi4_and_hi(prim_mubi_pkg::mubi4_t'(de ? d : q),
117 (we ? prim_mubi_pkg::mubi4_t'(wd) :
118 prim_mubi_pkg::MuBi4True));
119 end else if (DW == 8) begin : gen_mubi8
120 assign wr_data = prim_mubi_pkg::mubi8_and_hi(prim_mubi_pkg::mubi8_t'(de ? d : q),
121 (we ? prim_mubi_pkg::mubi8_t'(wd) :
122 prim_mubi_pkg::MuBi8True));
123 end else if (DW == 12) begin : gen_mubi12
124 assign wr_data = prim_mubi_pkg::mubi12_and_hi(prim_mubi_pkg::mubi12_t'(de ? d : q),
125 (we ? prim_mubi_pkg::mubi12_t'(wd) :
126 prim_mubi_pkg::MuBi12True));
127 end else if (DW == 16) begin : gen_mubi16
128 assign wr_data = prim_mubi_pkg::mubi16_and_hi(prim_mubi_pkg::mubi16_t'(de ? d : q),
129 (we ? prim_mubi_pkg::mubi16_t'(wd) :
130 prim_mubi_pkg::MuBi16True));
131 end else begin : gen_invalid_mubi
132 $error("%m: Invalid width for MuBi");
133 end
134 end else begin : gen_non_mubi
135 1/1 assign wr_data = (de ? d : q) & (we ? wd : '1);
Tests: T6 T25 T77
Cond Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_cause_cause_3.wr_en_data_arb
| Total | Covered | Percent |
|---|
| Conditions | 10 | 9 | 90.00 |
| Logical | 10 | 9 | 90.00 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 113
EXPRESSION (we | de)
-1 -2
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T1,T2,T3 |
| 0 | 1 | Covered | T23 |
| 1 | 0 | Covered | T6,T25,T77 |
LINE 135
EXPRESSION ((de ? d : q) & (we ? wd : '1))
------1----- -------2------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Not Covered | |
| 1 | 1 | Covered | T23 |
LINE 135
SUB-EXPRESSION (de ? d : q)
-1
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T23 |
LINE 135
SUB-EXPRESSION (we ? wd : '1)
-1
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T6,T25,T77 |