Unified Coverage Report :: Module Instance :: tb.dut.top_earlgrey.u_aon_timer_aon.u_reg.u_wdog_bark_thold.wr_en_data

Module Instance : tb.dut.top_earlgrey.u_sensor_ctrl_aon.u_reg.u_intr_state_io_status_change.wr_en_data_arb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00		u_intr_state_io_status_change

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_sensor_ctrl_aon.u_reg.u_intr_state_init_status_change.wr_en_data_arb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00		u_intr_state_init_status_change

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_sensor_ctrl_aon.u_reg.u_intr_enable_io_status_change.wr_en_data_arb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00		u_intr_enable_io_status_change

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_sensor_ctrl_aon.u_reg.u_intr_enable_init_status_change.wr_en_data_arb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00		u_intr_enable_init_status_change

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_sensor_ctrl_aon.u_reg.u_cfg_regwen.wr_en_data_arb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
87.50	100.00	75.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
87.50	100.00	75.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.24	85.71	100.00			100.00		u_cfg_regwen

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_sensor_ctrl_aon.u_reg.u_alert_trig_val_0.wr_en_data_arb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00		u_alert_trig_val_0

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_sensor_ctrl_aon.u_reg.u_alert_trig_val_1.wr_en_data_arb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00		u_alert_trig_val_1

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Go back
Module Instances:
tb.dut.top_earlgrey.u_sensor_ctrl_aon.u_reg.u_intr_state_io_status_change.wr_en_data_arb
tb.dut.top_earlgrey.u_sensor_ctrl_aon.u_reg.u_intr_state_init_status_change.wr_en_data_arb
tb.dut.top_earlgrey.u_sensor_ctrl_aon.u_reg.u_intr_enable_io_status_change.wr_en_data_arb
tb.dut.top_earlgrey.u_sensor_ctrl_aon.u_reg.u_intr_enable_init_status_change.wr_en_data_arb
tb.dut.top_earlgrey.u_sensor_ctrl_aon.u_reg.u_cfg_regwen.wr_en_data_arb
tb.dut.top_earlgrey.u_sensor_ctrl_aon.u_reg.u_alert_trig_val_0.wr_en_data_arb
tb.dut.top_earlgrey.u_sensor_ctrl_aon.u_reg.u_alert_trig_val_1.wr_en_data_arb

Line Coverage for Instance : tb.dut.top_earlgrey.u_sensor_ctrl_aon.u_reg.u_intr_state_io_status_change.wr_en_data_arb

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	88	1	1	100.00
CONT_ASSIGN	110	1	1	100.00



87                          // If both try to set/clr at the same bit pos, SW wins.
88         1/1              assign wr_en   = we | de;
           Tests:       T1 T2 T3 
89                          if (Mubi) begin : gen_mubi
90                            if (DW == 4) begin : gen_mubi4
91                              assign wr_data = prim_mubi_pkg::mubi4_and_hi(prim_mubi_pkg::mubi4_t'(de ? d : q),
92                                                                           (we ? prim_mubi_pkg::mubi4_t'(~wd) :
93                                                                                 prim_mubi_pkg::MuBi4True));
94                            end else if (DW == 8) begin : gen_mubi8
95                              assign wr_data = prim_mubi_pkg::mubi8_and_hi(prim_mubi_pkg::mubi8_t'(de ? d : q),
96                                                                           (we ? prim_mubi_pkg::mubi8_t'(~wd) :
97                                                                                 prim_mubi_pkg::MuBi8True));
98                            end else if (DW == 12) begin : gen_mubi12
99                              assign wr_data = prim_mubi_pkg::mubi12_and_hi(prim_mubi_pkg::mubi12_t'(de ? d : q),
100                                                                           (we ? prim_mubi_pkg::mubi12_t'(~wd) :
101                                                                                 prim_mubi_pkg::MuBi12True));
102                           end else if (DW == 16) begin : gen_mubi16
103                             assign wr_data = prim_mubi_pkg::mubi16_and_hi(prim_mubi_pkg::mubi16_t'(de ? d : q),
104                                                                           (we ? prim_mubi_pkg::mubi16_t'(~wd) :
105                                                                                 prim_mubi_pkg::MuBi16True));
106                           end else begin : gen_invalid_mubi
107                             $error("%m: Invalid width for MuBi");
108                           end
109                         end else begin : gen_non_mubi
110        1/1                assign wr_data = (de ? d : q) & (we ? ~wd : '1);
           Tests:       T1 T2 T3

Cond Coverage for Instance : tb.dut.top_earlgrey.u_sensor_ctrl_aon.u_reg.u_intr_state_io_status_change.wr_en_data_arb

	Total	Covered	Percent
Conditions	10	10	100.00
Logical	10	10	100.00
Non-Logical	0	0
Event	0	0

 LINE       88
 EXPRESSION (we | de)
             -1   -2

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T179,T127,T339

 LINE       110
 EXPRESSION ((de ? d : q) & (we ? ((~wd)) : '1))
             ------1-----   ---------2---------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T179,T127,T339
1	1	Covered	T1,T2,T3

 LINE       110
 SUB-EXPRESSION (de ? d : q)
                 -1

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       110
 SUB-EXPRESSION (we ? ((~wd)) : '1)
                 -1

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T179,T127,T339

Line Coverage for Instance : tb.dut.top_earlgrey.u_sensor_ctrl_aon.u_reg.u_intr_state_init_status_change.wr_en_data_arb

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	88	1	1	100.00
CONT_ASSIGN	110	1	1	100.00



87                          // If both try to set/clr at the same bit pos, SW wins.
88         1/1              assign wr_en   = we | de;
           Tests:       T1 T2 T3 
89                          if (Mubi) begin : gen_mubi
90                            if (DW == 4) begin : gen_mubi4
91                              assign wr_data = prim_mubi_pkg::mubi4_and_hi(prim_mubi_pkg::mubi4_t'(de ? d : q),
92                                                                           (we ? prim_mubi_pkg::mubi4_t'(~wd) :
93                                                                                 prim_mubi_pkg::MuBi4True));
94                            end else if (DW == 8) begin : gen_mubi8
95                              assign wr_data = prim_mubi_pkg::mubi8_and_hi(prim_mubi_pkg::mubi8_t'(de ? d : q),
96                                                                           (we ? prim_mubi_pkg::mubi8_t'(~wd) :
97                                                                                 prim_mubi_pkg::MuBi8True));
98                            end else if (DW == 12) begin : gen_mubi12
99                              assign wr_data = prim_mubi_pkg::mubi12_and_hi(prim_mubi_pkg::mubi12_t'(de ? d : q),
100                                                                           (we ? prim_mubi_pkg::mubi12_t'(~wd) :
101                                                                                 prim_mubi_pkg::MuBi12True));
102                           end else if (DW == 16) begin : gen_mubi16
103                             assign wr_data = prim_mubi_pkg::mubi16_and_hi(prim_mubi_pkg::mubi16_t'(de ? d : q),
104                                                                           (we ? prim_mubi_pkg::mubi16_t'(~wd) :
105                                                                                 prim_mubi_pkg::MuBi16True));
106                           end else begin : gen_invalid_mubi
107                             $error("%m: Invalid width for MuBi");
108                           end
109                         end else begin : gen_non_mubi
110        1/1                assign wr_data = (de ? d : q) & (we ? ~wd : '1);
           Tests:       T1 T2 T3

Cond Coverage for Instance : tb.dut.top_earlgrey.u_sensor_ctrl_aon.u_reg.u_intr_state_init_status_change.wr_en_data_arb

	Total	Covered	Percent
Conditions	10	10	100.00
Logical	10	10	100.00
Non-Logical	0	0
Event	0	0

 LINE       88
 EXPRESSION (we | de)
             -1   -2

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T179,T127,T339

 LINE       110
 EXPRESSION ((de ? d : q) & (we ? ((~wd)) : '1))
             ------1-----   ---------2---------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T179,T127,T339
1	1	Covered	T1,T2,T3

 LINE       110
 SUB-EXPRESSION (de ? d : q)
                 -1

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       110
 SUB-EXPRESSION (we ? ((~wd)) : '1)
                 -1

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T179,T127,T339

Line Coverage for Instance : tb.dut.top_earlgrey.u_sensor_ctrl_aon.u_reg.u_intr_enable_io_status_change.wr_en_data_arb

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	33	1	1	100.00
CONT_ASSIGN	34	1	1	100.00
CONT_ASSIGN	39	0	0



32                        if (SwAccess inside {SwAccessRW, SwAccessWO}) begin : gen_w
33         1/1              assign wr_en   = we | de;
           Tests:       T179 T127 T339 
34         1/1              assign wr_data = (we == 1'b1) ? wd : d; // SW higher priority
           Tests:       T1 T2 T3 
35                          // Unused q - Prevent lint errors.
36                          logic [DW-1:0] unused_q;
37                          //VCS coverage off
38                          // pragma coverage off
39         unreachable      assign unused_q = q;

Cond Coverage for Instance : tb.dut.top_earlgrey.u_sensor_ctrl_aon.u_reg.u_intr_enable_io_status_change.wr_en_data_arb

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       33
 EXPRESSION (we | de)
             -1   -2

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Covered	T179,T127,T339

 LINE       34
 EXPRESSION ((we == 1'b1) ? wd : d)
             ------1-----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T179,T127,T339

 LINE       34
 SUB-EXPRESSION (we == 1'b1)
                ------1-----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T179,T127,T339

Branch Coverage for Instance : tb.dut.top_earlgrey.u_sensor_ctrl_aon.u_reg.u_intr_enable_io_status_change.wr_en_data_arb

	Line No.	Total	Covered	Percent
Branches		2	2	100.00
TERNARY	34	2	2	100.00



34             assign wr_data = (we == 1'b1) ? wd : d; // SW higher priority
                                             -1-  
                                             ==>  
                                             ==>

Branches:

-1-	Status	Tests
1	Covered	T179,T127,T339
0	Covered	T1,T2,T3

Line Coverage for Instance : tb.dut.top_earlgrey.u_sensor_ctrl_aon.u_reg.u_intr_enable_init_status_change.wr_en_data_arb

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	33	1	1	100.00
CONT_ASSIGN	34	1	1	100.00
CONT_ASSIGN	39	0	0



32                        if (SwAccess inside {SwAccessRW, SwAccessWO}) begin : gen_w
33         1/1              assign wr_en   = we | de;
           Tests:       T179 T127 T339 
34         1/1              assign wr_data = (we == 1'b1) ? wd : d; // SW higher priority
           Tests:       T1 T2 T3 
35                          // Unused q - Prevent lint errors.
36                          logic [DW-1:0] unused_q;
37                          //VCS coverage off
38                          // pragma coverage off
39         unreachable      assign unused_q = q;

Cond Coverage for Instance : tb.dut.top_earlgrey.u_sensor_ctrl_aon.u_reg.u_intr_enable_init_status_change.wr_en_data_arb

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       33
 EXPRESSION (we | de)
             -1   -2

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Covered	T179,T127,T339

 LINE       34
 EXPRESSION ((we == 1'b1) ? wd : d)
             ------1-----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T179,T127,T339

 LINE       34
 SUB-EXPRESSION (we == 1'b1)
                ------1-----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T179,T127,T339

Branch Coverage for Instance : tb.dut.top_earlgrey.u_sensor_ctrl_aon.u_reg.u_intr_enable_init_status_change.wr_en_data_arb

	Line No.	Total	Covered	Percent
Branches		2	2	100.00
TERNARY	34	2	2	100.00



34             assign wr_data = (we == 1'b1) ? wd : d; // SW higher priority
                                             -1-  
                                             ==>  
                                             ==>

Branches:

-1-	Status	Tests
1	Covered	T179,T127,T339
0	Covered	T1,T2,T3

Line Coverage for Instance : tb.dut.top_earlgrey.u_sensor_ctrl_aon.u_reg.u_cfg_regwen.wr_en_data_arb

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	113	1	1	100.00
CONT_ASSIGN	135	1	1	100.00



112                       end else if (SwAccess == SwAccessW0C) begin : gen_w0c
113        1/1              assign wr_en   = we | de;
           Tests:       T98 
114                         if (Mubi) begin : gen_mubi
115                           if (DW == 4) begin : gen_mubi4
116                             assign wr_data = prim_mubi_pkg::mubi4_and_hi(prim_mubi_pkg::mubi4_t'(de ? d : q),
117                                                                          (we ? prim_mubi_pkg::mubi4_t'(wd) :
118                                                                                prim_mubi_pkg::MuBi4True));
119                           end else if (DW == 8) begin : gen_mubi8
120                             assign wr_data = prim_mubi_pkg::mubi8_and_hi(prim_mubi_pkg::mubi8_t'(de ? d : q),
121                                                                          (we ? prim_mubi_pkg::mubi8_t'(wd) :
122                                                                                prim_mubi_pkg::MuBi8True));
123                           end else if (DW == 12) begin : gen_mubi12
124                             assign wr_data = prim_mubi_pkg::mubi12_and_hi(prim_mubi_pkg::mubi12_t'(de ? d : q),
125                                                                           (we ? prim_mubi_pkg::mubi12_t'(wd) :
126                                                                                 prim_mubi_pkg::MuBi12True));
127                           end else if (DW == 16) begin : gen_mubi16
128                             assign wr_data = prim_mubi_pkg::mubi16_and_hi(prim_mubi_pkg::mubi16_t'(de ? d : q),
129                                                                           (we ? prim_mubi_pkg::mubi16_t'(wd) :
130                                                                                 prim_mubi_pkg::MuBi16True));
131                           end else begin : gen_invalid_mubi
132                             $error("%m: Invalid width for MuBi");
133                           end
134                         end else begin : gen_non_mubi
135        1/1                assign wr_data = (de ? d : q) & (we ? wd : '1);
           Tests:       T1 T2 T3

Cond Coverage for Instance : tb.dut.top_earlgrey.u_sensor_ctrl_aon.u_reg.u_cfg_regwen.wr_en_data_arb

	Total	Covered	Percent
Conditions	8	6	75.00
Logical	8	6	75.00
Non-Logical	0	0
Event	0	0

 LINE       113
 EXPRESSION (we | de)
             -1   -2

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Covered	T98

 LINE       135
 EXPRESSION ((de ? d : q) & (we ? wd : '1))
             ------1-----   -------2------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Covered	T1,T2,T3

 LINE       135
 SUB-EXPRESSION (de ? d : q)
                 -1

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Unreachable

 LINE       135
 SUB-EXPRESSION (we ? wd : '1)
                 -1

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T98

Line Coverage for Instance : tb.dut.top_earlgrey.u_sensor_ctrl_aon.u_reg.u_alert_trig_val_0.wr_en_data_arb

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	33	1	1	100.00
CONT_ASSIGN	34	1	1	100.00
CONT_ASSIGN	39	0	0



32                        if (SwAccess inside {SwAccessRW, SwAccessWO}) begin : gen_w
33         1/1              assign wr_en   = we | de;
           Tests:       T164 T143 T165 
34         1/1              assign wr_data = (we == 1'b1) ? wd : d; // SW higher priority
           Tests:       T1 T2 T3 
35                          // Unused q - Prevent lint errors.
36                          logic [DW-1:0] unused_q;
37                          //VCS coverage off
38                          // pragma coverage off
39         unreachable      assign unused_q = q;

Cond Coverage for Instance : tb.dut.top_earlgrey.u_sensor_ctrl_aon.u_reg.u_alert_trig_val_0.wr_en_data_arb

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       33
 EXPRESSION (we | de)
             -1   -2

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Covered	T164,T143,T165

 LINE       34
 EXPRESSION ((we == 1'b1) ? wd : d)
             ------1-----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T164,T143,T165

 LINE       34
 SUB-EXPRESSION (we == 1'b1)
                ------1-----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T164,T143,T165

Branch Coverage for Instance : tb.dut.top_earlgrey.u_sensor_ctrl_aon.u_reg.u_alert_trig_val_0.wr_en_data_arb

	Line No.	Total	Covered	Percent
Branches		2	2	100.00
TERNARY	34	2	2	100.00



34             assign wr_data = (we == 1'b1) ? wd : d; // SW higher priority
                                             -1-  
                                             ==>  
                                             ==>

Branches:

-1-	Status	Tests
1	Covered	T164,T143,T165
0	Covered	T1,T2,T3

Line Coverage for Instance : tb.dut.top_earlgrey.u_sensor_ctrl_aon.u_reg.u_alert_trig_val_1.wr_en_data_arb

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	33	1	1	100.00
CONT_ASSIGN	34	1	1	100.00
CONT_ASSIGN	39	0	0



32                        if (SwAccess inside {SwAccessRW, SwAccessWO}) begin : gen_w
33         1/1              assign wr_en   = we | de;
           Tests:       T164 T143 T165 
34         1/1              assign wr_data = (we == 1'b1) ? wd : d; // SW higher priority
           Tests:       T1 T2 T3 
35                          // Unused q - Prevent lint errors.
36                          logic [DW-1:0] unused_q;
37                          //VCS coverage off
38                          // pragma coverage off
39         unreachable      assign unused_q = q;

Cond Coverage for Instance : tb.dut.top_earlgrey.u_sensor_ctrl_aon.u_reg.u_alert_trig_val_1.wr_en_data_arb

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       33
 EXPRESSION (we | de)
             -1   -2

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Covered	T164,T143,T165

 LINE       34
 EXPRESSION ((we == 1'b1) ? wd : d)
             ------1-----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T164,T143,T165

 LINE       34
 SUB-EXPRESSION (we == 1'b1)
                ------1-----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T164,T143,T165

Branch Coverage for Instance : tb.dut.top_earlgrey.u_sensor_ctrl_aon.u_reg.u_alert_trig_val_1.wr_en_data_arb

	Line No.	Total	Covered	Percent
Branches		2	2	100.00
TERNARY	34	2	2	100.00



34             assign wr_data = (we == 1'b1) ? wd : d; // SW higher priority
                                             -1-  
                                             ==>  
                                             ==>

Branches:

-1-	Status	Tests
1	Covered	T164,T143,T165
0	Covered	T1,T2,T3