Unified Coverage Report :: Module Instance :: tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_46_schmitt_en_46

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_46_schmitt_en_46

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
60.00	60.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
60.00	60.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.25	99.77	97.22			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_46_od_en_46

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
60.00	60.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
60.00	60.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.25	99.77	97.22			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_46_input_disable_46

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.25	99.77	97.22			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_46_slew_rate_46

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
60.00	60.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
60.00	60.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.25	99.77	97.22			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_46_drive_strength_46

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.25	99.77	97.22			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_dio_pad_attr_0_invert_0

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.25	99.77	97.22			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_dio_pad_attr_0_virtual_od_en_0

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.25	99.77	97.22			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_dio_pad_attr_0_pull_en_0

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.25	99.77	97.22			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_dio_pad_attr_0_pull_select_0

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.25	99.77	97.22			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_dio_pad_attr_0_keeper_en_0

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
60.00	60.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
60.00	60.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.25	99.77	97.22			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_dio_pad_attr_0_schmitt_en_0

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
60.00	60.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
60.00	60.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.25	99.77	97.22			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_dio_pad_attr_0_od_en_0

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
60.00	60.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
60.00	60.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.25	99.77	97.22			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_dio_pad_attr_0_input_disable_0

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.25	99.77	97.22			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_dio_pad_attr_0_slew_rate_0

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
60.00	60.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
60.00	60.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.25	99.77	97.22			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_dio_pad_attr_0_drive_strength_0

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.25	99.77	97.22			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_dio_pad_attr_1_invert_1

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.25	99.77	97.22			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_dio_pad_attr_1_virtual_od_en_1

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.25	99.77	97.22			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_dio_pad_attr_1_pull_en_1

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.25	99.77	97.22			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_dio_pad_attr_1_pull_select_1

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.25	99.77	97.22			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_dio_pad_attr_1_keeper_en_1

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
60.00	60.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
60.00	60.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.25	99.77	97.22			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_dio_pad_attr_1_schmitt_en_1

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
60.00	60.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
60.00	60.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.25	99.77	97.22			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_dio_pad_attr_1_od_en_1

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
60.00	60.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
60.00	60.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.25	99.77	97.22			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_dio_pad_attr_1_input_disable_1

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.25	99.77	97.22			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_dio_pad_attr_1_slew_rate_1

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
60.00	60.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
60.00	60.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.25	99.77	97.22			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_dio_pad_attr_1_drive_strength_1

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.25	99.77	97.22			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_dio_pad_attr_2_invert_2

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.25	99.77	97.22			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_dio_pad_attr_2_virtual_od_en_2

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.25	99.77	97.22			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_dio_pad_attr_2_pull_en_2

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.25	99.77	97.22			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_dio_pad_attr_2_pull_select_2

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.25	99.77	97.22			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_dio_pad_attr_2_keeper_en_2

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
60.00	60.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
60.00	60.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.25	99.77	97.22			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_dio_pad_attr_2_schmitt_en_2

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
60.00	60.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
60.00	60.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.25	99.77	97.22			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_dio_pad_attr_2_od_en_2

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
60.00	60.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
60.00	60.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.25	99.77	97.22			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_dio_pad_attr_2_input_disable_2

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.25	99.77	97.22			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_dio_pad_attr_2_slew_rate_2

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
60.00	60.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
60.00	60.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.25	99.77	97.22			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_dio_pad_attr_2_drive_strength_2

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.25	99.77	97.22			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_dio_pad_attr_3_invert_3

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.25	99.77	97.22			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_dio_pad_attr_3_virtual_od_en_3

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.25	99.77	97.22			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_dio_pad_attr_3_pull_en_3

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.25	99.77	97.22			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_dio_pad_attr_3_pull_select_3

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.25	99.77	97.22			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_dio_pad_attr_3_keeper_en_3

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
60.00	60.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
60.00	60.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.25	99.77	97.22			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_dio_pad_attr_3_schmitt_en_3

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
60.00	60.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
60.00	60.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.25	99.77	97.22			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_dio_pad_attr_3_od_en_3

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
60.00	60.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
60.00	60.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.25	99.77	97.22			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_dio_pad_attr_3_input_disable_3

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.25	99.77	97.22			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_dio_pad_attr_3_slew_rate_3

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
60.00	60.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
60.00	60.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.25	99.77	97.22			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_dio_pad_attr_3_drive_strength_3

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.25	99.77	97.22			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_dio_pad_attr_4_invert_4

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.25	99.77	97.22			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_dio_pad_attr_4_virtual_od_en_4

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.25	99.77	97.22			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_dio_pad_attr_4_pull_en_4

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.25	99.77	97.22			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_dio_pad_attr_4_pull_select_4

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.25	99.77	97.22			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_dio_pad_attr_4_keeper_en_4

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
60.00	60.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
60.00	60.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.25	99.77	97.22			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_dio_pad_attr_4_schmitt_en_4

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
60.00	60.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
60.00	60.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.25	99.77	97.22			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_dio_pad_attr_4_od_en_4

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
60.00	60.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
60.00	60.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.25	99.77	97.22			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_dio_pad_attr_4_input_disable_4

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.25	99.77	97.22			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_dio_pad_attr_4_slew_rate_4

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
60.00	60.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
60.00	60.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.25	99.77	97.22			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_dio_pad_attr_4_drive_strength_4

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.25	99.77	97.22			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_dio_pad_attr_5_invert_5

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.25	99.77	97.22			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_dio_pad_attr_5_virtual_od_en_5

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.25	99.77	97.22			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_dio_pad_attr_5_pull_en_5

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.25	99.77	97.22			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_dio_pad_attr_5_pull_select_5

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.25	99.77	97.22			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_dio_pad_attr_5_keeper_en_5

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
60.00	60.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
60.00	60.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.25	99.77	97.22			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_dio_pad_attr_5_schmitt_en_5

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
60.00	60.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
60.00	60.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.25	99.77	97.22			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_dio_pad_attr_5_od_en_5

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
60.00	60.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
60.00	60.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.25	99.77	97.22			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_dio_pad_attr_5_input_disable_5

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.25	99.77	97.22			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_dio_pad_attr_5_slew_rate_5

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
60.00	60.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
60.00	60.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.25	99.77	97.22			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_dio_pad_attr_5_drive_strength_5

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.25	99.77	97.22			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_dio_pad_attr_6_invert_6

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.25	99.77	97.22			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_dio_pad_attr_6_virtual_od_en_6

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.25	99.77	97.22			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_dio_pad_attr_6_pull_en_6

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.25	99.77	97.22			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_dio_pad_attr_6_pull_select_6

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.25	99.77	97.22			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_dio_pad_attr_6_keeper_en_6

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
60.00	60.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
60.00	60.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.25	99.77	97.22			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_dio_pad_attr_6_schmitt_en_6

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
60.00	60.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
60.00	60.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.25	99.77	97.22			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_dio_pad_attr_6_od_en_6

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
60.00	60.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
60.00	60.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.25	99.77	97.22			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_dio_pad_attr_6_input_disable_6

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.25	99.77	97.22			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_dio_pad_attr_6_slew_rate_6

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
60.00	60.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
60.00	60.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.25	99.77	97.22			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_dio_pad_attr_6_drive_strength_6

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.25	99.77	97.22			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_dio_pad_attr_7_invert_7

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.25	99.77	97.22			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_dio_pad_attr_7_virtual_od_en_7

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.25	99.77	97.22			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_dio_pad_attr_7_pull_en_7

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.25	99.77	97.22			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_dio_pad_attr_7_pull_select_7

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.25	99.77	97.22			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_dio_pad_attr_7_keeper_en_7

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
60.00	60.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
60.00	60.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.25	99.77	97.22			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_dio_pad_attr_7_schmitt_en_7

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
60.00	60.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
60.00	60.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.25	99.77	97.22			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_dio_pad_attr_7_od_en_7

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
60.00	60.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
60.00	60.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.25	99.77	97.22			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_dio_pad_attr_7_input_disable_7

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.25	99.77	97.22			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_dio_pad_attr_7_slew_rate_7

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
60.00	60.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
60.00	60.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.25	99.77	97.22			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_dio_pad_attr_7_drive_strength_7

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.25	99.77	97.22			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_dio_pad_attr_8_invert_8

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.25	99.77	97.22			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_dio_pad_attr_8_virtual_od_en_8

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.25	99.77	97.22			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_dio_pad_attr_8_pull_en_8

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.25	99.77	97.22			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_dio_pad_attr_8_pull_select_8

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.25	99.77	97.22			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_dio_pad_attr_8_keeper_en_8

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
60.00	60.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
60.00	60.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.25	99.77	97.22			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_dio_pad_attr_8_schmitt_en_8

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
60.00	60.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
60.00	60.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.25	99.77	97.22			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_dio_pad_attr_8_od_en_8

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
60.00	60.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
60.00	60.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.25	99.77	97.22			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_dio_pad_attr_8_input_disable_8

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.25	99.77	97.22			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_dio_pad_attr_8_slew_rate_8

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
60.00	60.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
60.00	60.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.25	99.77	97.22			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_dio_pad_attr_8_drive_strength_8

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.25	99.77	97.22			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_dio_pad_attr_9_invert_9

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.25	99.77	97.22			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_dio_pad_attr_9_virtual_od_en_9

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.25	99.77	97.22			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_dio_pad_attr_9_pull_en_9

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.25	99.77	97.22			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_dio_pad_attr_9_pull_select_9

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.25	99.77	97.22			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_dio_pad_attr_9_keeper_en_9

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
60.00	60.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
60.00	60.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.25	99.77	97.22			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_dio_pad_attr_9_schmitt_en_9

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
60.00	60.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
60.00	60.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.25	99.77	97.22			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_dio_pad_attr_9_od_en_9

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
60.00	60.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
60.00	60.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.25	99.77	97.22			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_dio_pad_attr_9_input_disable_9

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.25	99.77	97.22			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_dio_pad_attr_9_slew_rate_9

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
60.00	60.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
60.00	60.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.25	99.77	97.22			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_dio_pad_attr_9_drive_strength_9

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.25	99.77	97.22			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_dio_pad_attr_10_invert_10

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.25	99.77	97.22			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_dio_pad_attr_10_virtual_od_en_10

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.25	99.77	97.22			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_dio_pad_attr_10_pull_en_10

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.25	99.77	97.22			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_dio_pad_attr_10_pull_select_10

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.25	99.77	97.22			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_dio_pad_attr_10_keeper_en_10

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
60.00	60.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
60.00	60.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.25	99.77	97.22			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_dio_pad_attr_10_schmitt_en_10

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
60.00	60.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
60.00	60.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.25	99.77	97.22			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_dio_pad_attr_10_od_en_10

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
60.00	60.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
60.00	60.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.25	99.77	97.22			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_dio_pad_attr_10_input_disable_10

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.25	99.77	97.22			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_dio_pad_attr_10_slew_rate_10

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
60.00	60.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
60.00	60.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.25	99.77	97.22			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_dio_pad_attr_10_drive_strength_10

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.25	99.77	97.22			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_dio_pad_attr_11_invert_11

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.25	99.77	97.22			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_dio_pad_attr_11_virtual_od_en_11

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.25	99.77	97.22			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_dio_pad_attr_11_pull_en_11

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.25	99.77	97.22			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_dio_pad_attr_11_pull_select_11

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.25	99.77	97.22			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_dio_pad_attr_11_keeper_en_11

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
60.00	60.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
60.00	60.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.25	99.77	97.22			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_dio_pad_attr_11_schmitt_en_11

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
60.00	60.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
60.00	60.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.25	99.77	97.22			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_dio_pad_attr_11_od_en_11

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
60.00	60.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
60.00	60.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.25	99.77	97.22			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_dio_pad_attr_11_input_disable_11

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.25	99.77	97.22			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_dio_pad_attr_11_slew_rate_11

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
60.00	60.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
60.00	60.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.25	99.77	97.22			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_dio_pad_attr_11_drive_strength_11

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.25	99.77	97.22			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_dio_pad_attr_12_invert_12

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.25	99.77	97.22			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_dio_pad_attr_12_virtual_od_en_12

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
60.00	60.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
60.00	60.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.25	99.77	97.22			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_dio_pad_attr_12_pull_en_12

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.25	99.77	97.22			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_dio_pad_attr_12_pull_select_12

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.25	99.77	97.22			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_dio_pad_attr_12_keeper_en_12

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
60.00	60.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
60.00	60.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.25	99.77	97.22			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_dio_pad_attr_12_schmitt_en_12

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
60.00	60.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
60.00	60.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.25	99.77	97.22			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_dio_pad_attr_12_od_en_12

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
60.00	60.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
60.00	60.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.25	99.77	97.22			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_dio_pad_attr_12_input_disable_12

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.25	99.77	97.22			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_dio_pad_attr_12_slew_rate_12

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
60.00	60.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
60.00	60.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.25	99.77	97.22			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_dio_pad_attr_12_drive_strength_12

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
60.00	60.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
60.00	60.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.25	99.77	97.22			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_dio_pad_attr_13_invert_13

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.25	99.77	97.22			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_dio_pad_attr_13_virtual_od_en_13

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
60.00	60.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
60.00	60.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.25	99.77	97.22			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_dio_pad_attr_13_pull_en_13

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.25	99.77	97.22			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_dio_pad_attr_13_pull_select_13

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.25	99.77	97.22			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_dio_pad_attr_13_keeper_en_13

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
60.00	60.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
60.00	60.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.25	99.77	97.22			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_dio_pad_attr_13_schmitt_en_13

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
60.00	60.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
60.00	60.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.25	99.77	97.22			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_dio_pad_attr_13_od_en_13

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
60.00	60.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
60.00	60.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.25	99.77	97.22			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_dio_pad_attr_13_input_disable_13

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.25	99.77	97.22			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_dio_pad_attr_13_slew_rate_13

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
60.00	60.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
60.00	60.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.25	99.77	97.22			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_dio_pad_attr_13_drive_strength_13

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
60.00	60.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
60.00	60.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.25	99.77	97.22			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_dio_pad_attr_14_invert_14

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.25	99.77	97.22			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_dio_pad_attr_14_virtual_od_en_14

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.25	99.77	97.22			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_dio_pad_attr_14_pull_en_14

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.25	99.77	97.22			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_dio_pad_attr_14_pull_select_14

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.25	99.77	97.22			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_dio_pad_attr_14_keeper_en_14

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
60.00	60.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
60.00	60.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.25	99.77	97.22			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_dio_pad_attr_14_schmitt_en_14

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
60.00	60.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
60.00	60.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.25	99.77	97.22			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_dio_pad_attr_14_od_en_14

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
60.00	60.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
60.00	60.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.25	99.77	97.22			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_dio_pad_attr_14_input_disable_14

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.25	99.77	97.22			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_dio_pad_attr_14_slew_rate_14

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
60.00	60.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
60.00	60.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.25	99.77	97.22			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_dio_pad_attr_14_drive_strength_14

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.25	99.77	97.22			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_dio_pad_attr_15_invert_15

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.25	99.77	97.22			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_dio_pad_attr_15_virtual_od_en_15

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.25	99.77	97.22			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_dio_pad_attr_15_pull_en_15

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.25	99.77	97.22			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_dio_pad_attr_15_pull_select_15

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.25	99.77	97.22			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_dio_pad_attr_15_keeper_en_15

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
60.00	60.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
60.00	60.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.25	99.77	97.22			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_dio_pad_attr_15_schmitt_en_15

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
60.00	60.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
60.00	60.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.25	99.77	97.22			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_dio_pad_attr_15_od_en_15

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
60.00	60.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
60.00	60.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.25	99.77	97.22			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_dio_pad_attr_15_input_disable_15

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.25	99.77	97.22			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_dio_pad_attr_15_slew_rate_15

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
60.00	60.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
60.00	60.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.25	99.77	97.22			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_dio_pad_attr_15_drive_strength_15

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.25	99.77	97.22			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_sensor_ctrl_aon.u_reg.u_intr_test_io_status_change

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
92.41	100.00	69.65			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_sensor_ctrl_aon.u_reg.u_intr_test_init_status_change

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
92.41	100.00	69.65			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_sensor_ctrl_aon.u_reg.u_alert_test_recov_alert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
92.41	100.00	69.65			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_sensor_ctrl_aon.u_reg.u_alert_test_fatal_alert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
92.41	100.00	69.65			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_sensor_ctrl_aon.u_reg.u_manual_pad_attr_0_pull_en_0

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
80.00	80.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
80.00	80.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
92.41	100.00	69.65			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_sensor_ctrl_aon.u_reg.u_manual_pad_attr_0_pull_select_0

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
80.00	80.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
80.00	80.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
92.41	100.00	69.65			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_sensor_ctrl_aon.u_reg.u_manual_pad_attr_0_input_disable_0

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
80.00	80.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
80.00	80.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
92.41	100.00	69.65			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_sensor_ctrl_aon.u_reg.u_manual_pad_attr_1_pull_en_1

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
80.00	80.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
80.00	80.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
92.41	100.00	69.65			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_sensor_ctrl_aon.u_reg.u_manual_pad_attr_1_pull_select_1

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
80.00	80.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
80.00	80.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
92.41	100.00	69.65			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_sensor_ctrl_aon.u_reg.u_manual_pad_attr_1_input_disable_1

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
80.00	80.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
80.00	80.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
92.41	100.00	69.65			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_sensor_ctrl_aon.u_reg.u_manual_pad_attr_2_pull_en_2

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
80.00	80.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
80.00	80.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
92.41	100.00	69.65			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_sensor_ctrl_aon.u_reg.u_manual_pad_attr_2_pull_select_2

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
80.00	80.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
80.00	80.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
92.41	100.00	69.65			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_sensor_ctrl_aon.u_reg.u_manual_pad_attr_2_input_disable_2

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
80.00	80.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
80.00	80.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
92.41	100.00	69.65			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_sensor_ctrl_aon.u_reg.u_manual_pad_attr_3_pull_en_3

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
80.00	80.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
80.00	80.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
92.41	100.00	69.65			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_sensor_ctrl_aon.u_reg.u_manual_pad_attr_3_pull_select_3

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
80.00	80.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
80.00	80.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
92.41	100.00	69.65			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_sensor_ctrl_aon.u_reg.u_manual_pad_attr_3_input_disable_3

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
80.00	80.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
80.00	80.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
92.41	100.00	69.65			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_cc0

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.80	99.94	99.75			99.52	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_alert_test

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.80	99.94	99.75			99.52	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_46_schmitt_en_46

	Line No.	Total	Covered	Percent
TOTAL		5	3	60.00
CONT_ASSIGN	26	1	0	0.00
CONT_ASSIGN	27	1	0	0.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	30	1	1	100.00

25                        // between qs and ds
26         0/1     ==>    assign ds = d;
27         0/1     ==>    assign qs = d;
28         1/1            assign q = wd;
           Tests:       T1 T2 T3 
29         1/1            assign qe = we;
           Tests:       T96 T97 T98 
30         1/1            assign qre = re;
           Tests:       T96 T97 T98 

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_46_od_en_46

	Line No.	Total	Covered	Percent
TOTAL		5	3	60.00
CONT_ASSIGN	26	1	0	0.00
CONT_ASSIGN	27	1	0	0.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	30	1	1	100.00

25                        // between qs and ds
26         0/1     ==>    assign ds = d;
27         0/1     ==>    assign qs = d;
28         1/1            assign q = wd;
           Tests:       T1 T2 T3 
29         1/1            assign qe = we;
           Tests:       T96 T97 T98 
30         1/1            assign qre = re;
           Tests:       T96 T97 T98 

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_46_input_disable_46

	Line No.	Total	Covered	Percent
TOTAL		5	5	100.00
CONT_ASSIGN	26	1	1	100.00
CONT_ASSIGN	27	1	1	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	30	1	1	100.00

25                        // between qs and ds
26         1/1            assign ds = d;
           Tests:       T20 T21 T22 
27         1/1            assign qs = d;
           Tests:       T20 T21 T22 
28         1/1            assign q = wd;
           Tests:       T1 T2 T3 
29         1/1            assign qe = we;
           Tests:       T96 T97 T98 
30         1/1            assign qre = re;
           Tests:       T96 T97 T98 

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_46_slew_rate_46

	Line No.	Total	Covered	Percent
TOTAL		5	3	60.00
CONT_ASSIGN	26	1	0	0.00
CONT_ASSIGN	27	1	0	0.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	30	1	1	100.00

25                        // between qs and ds
26         0/1     ==>    assign ds = d;
27         0/1     ==>    assign qs = d;
28         1/1            assign q = wd;
           Tests:       T1 T2 T3 
29         1/1            assign qe = we;
           Tests:       T96 T97 T98 
30         1/1            assign qre = re;
           Tests:       T96 T97 T98 

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_mio_pad_attr_46_drive_strength_46

	Line No.	Total	Covered	Percent
TOTAL		5	5	100.00
CONT_ASSIGN	26	1	1	100.00
CONT_ASSIGN	27	1	1	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	30	1	1	100.00

25                        // between qs and ds
26         1/1            assign ds = d;
           Tests:       T20 T21 T22 
27         1/1            assign qs = d;
           Tests:       T20 T21 T22 
28         1/1            assign q = wd;
           Tests:       T1 T2 T3 
29         1/1            assign qe = we;
           Tests:       T96 T97 T98 
30         1/1            assign qre = re;
           Tests:       T96 T97 T98 

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_dio_pad_attr_0_invert_0

	Line No.	Total	Covered	Percent
TOTAL		5	5	100.00
CONT_ASSIGN	26	1	1	100.00
CONT_ASSIGN	27	1	1	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	30	1	1	100.00

25                        // between qs and ds
26         1/1            assign ds = d;
           Tests:       T20 T21 T22 
27         1/1            assign qs = d;
           Tests:       T20 T21 T22 
28         1/1            assign q = wd;
           Tests:       T1 T2 T3 
29         1/1            assign qe = we;
           Tests:       T1 T2 T3 
30         1/1            assign qre = re;
           Tests:       T1 T2 T3 

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_dio_pad_attr_0_virtual_od_en_0

	Line No.	Total	Covered	Percent
TOTAL		5	5	100.00
CONT_ASSIGN	26	1	1	100.00
CONT_ASSIGN	27	1	1	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	30	1	1	100.00

25                        // between qs and ds
26         1/1            assign ds = d;
           Tests:       T20 T21 T22 
27         1/1            assign qs = d;
           Tests:       T20 T21 T22 
28         1/1            assign q = wd;
           Tests:       T1 T2 T3 
29         1/1            assign qe = we;
           Tests:       T1 T2 T3 
30         1/1            assign qre = re;
           Tests:       T1 T2 T3 

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_dio_pad_attr_0_pull_en_0

	Line No.	Total	Covered	Percent
TOTAL		5	5	100.00
CONT_ASSIGN	26	1	1	100.00
CONT_ASSIGN	27	1	1	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	30	1	1	100.00

25                        // between qs and ds
26         1/1            assign ds = d;
           Tests:       T20 T21 T22 
27         1/1            assign qs = d;
           Tests:       T20 T21 T22 
28         1/1            assign q = wd;
           Tests:       T1 T2 T3 
29         1/1            assign qe = we;
           Tests:       T1 T2 T3 
30         1/1            assign qre = re;
           Tests:       T1 T2 T3 

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_dio_pad_attr_0_pull_select_0

	Line No.	Total	Covered	Percent
TOTAL		5	5	100.00
CONT_ASSIGN	26	1	1	100.00
CONT_ASSIGN	27	1	1	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	30	1	1	100.00

25                        // between qs and ds
26         1/1            assign ds = d;
           Tests:       T20 T21 T22 
27         1/1            assign qs = d;
           Tests:       T20 T21 T22 
28         1/1            assign q = wd;
           Tests:       T1 T2 T3 
29         1/1            assign qe = we;
           Tests:       T1 T2 T3 
30         1/1            assign qre = re;
           Tests:       T1 T2 T3 

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_dio_pad_attr_0_keeper_en_0

	Line No.	Total	Covered	Percent
TOTAL		5	3	60.00
CONT_ASSIGN	26	1	0	0.00
CONT_ASSIGN	27	1	0	0.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	30	1	1	100.00

25                        // between qs and ds
26         0/1     ==>    assign ds = d;
27         0/1     ==>    assign qs = d;
28         1/1            assign q = wd;
           Tests:       T1 T2 T3 
29         1/1            assign qe = we;
           Tests:       T1 T2 T3 
30         1/1            assign qre = re;
           Tests:       T1 T2 T3 

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_dio_pad_attr_0_schmitt_en_0

	Line No.	Total	Covered	Percent
TOTAL		5	3	60.00
CONT_ASSIGN	26	1	0	0.00
CONT_ASSIGN	27	1	0	0.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	30	1	1	100.00

25                        // between qs and ds
26         0/1     ==>    assign ds = d;
27         0/1     ==>    assign qs = d;
28         1/1            assign q = wd;
           Tests:       T1 T2 T3 
29         1/1            assign qe = we;
           Tests:       T1 T2 T3 
30         1/1            assign qre = re;
           Tests:       T1 T2 T3 

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_dio_pad_attr_0_od_en_0

	Line No.	Total	Covered	Percent
TOTAL		5	3	60.00
CONT_ASSIGN	26	1	0	0.00
CONT_ASSIGN	27	1	0	0.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	30	1	1	100.00

25                        // between qs and ds
26         0/1     ==>    assign ds = d;
27         0/1     ==>    assign qs = d;
28         1/1            assign q = wd;
           Tests:       T1 T2 T3 
29         1/1            assign qe = we;
           Tests:       T1 T2 T3 
30         1/1            assign qre = re;
           Tests:       T1 T2 T3 

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_dio_pad_attr_0_input_disable_0

	Line No.	Total	Covered	Percent
TOTAL		5	5	100.00
CONT_ASSIGN	26	1	1	100.00
CONT_ASSIGN	27	1	1	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	30	1	1	100.00

25                        // between qs and ds
26         1/1            assign ds = d;
           Tests:       T20 T21 T22 
27         1/1            assign qs = d;
           Tests:       T20 T21 T22 
28         1/1            assign q = wd;
           Tests:       T1 T2 T3 
29         1/1            assign qe = we;
           Tests:       T1 T2 T3 
30         1/1            assign qre = re;
           Tests:       T1 T2 T3 

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_dio_pad_attr_0_slew_rate_0

	Line No.	Total	Covered	Percent
TOTAL		5	3	60.00
CONT_ASSIGN	26	1	0	0.00
CONT_ASSIGN	27	1	0	0.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	30	1	1	100.00

25                        // between qs and ds
26         0/1     ==>    assign ds = d;
27         0/1     ==>    assign qs = d;
28         1/1            assign q = wd;
           Tests:       T1 T2 T3 
29         1/1            assign qe = we;
           Tests:       T1 T2 T3 
30         1/1            assign qre = re;
           Tests:       T1 T2 T3 

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_dio_pad_attr_0_drive_strength_0

	Line No.	Total	Covered	Percent
TOTAL		5	5	100.00
CONT_ASSIGN	26	1	1	100.00
CONT_ASSIGN	27	1	1	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	30	1	1	100.00

25                        // between qs and ds
26         1/1            assign ds = d;
           Tests:       T1 T2 T3 
27         1/1            assign qs = d;
           Tests:       T1 T2 T3 
28         1/1            assign q = wd;
           Tests:       T1 T2 T3 
29         1/1            assign qe = we;
           Tests:       T1 T2 T3 
30         1/1            assign qre = re;
           Tests:       T1 T2 T3 

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_dio_pad_attr_1_invert_1

	Line No.	Total	Covered	Percent
TOTAL		5	5	100.00
CONT_ASSIGN	26	1	1	100.00
CONT_ASSIGN	27	1	1	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	30	1	1	100.00

25                        // between qs and ds
26         1/1            assign ds = d;
           Tests:       T20 T21 T22 
27         1/1            assign qs = d;
           Tests:       T20 T21 T22 
28         1/1            assign q = wd;
           Tests:       T1 T2 T3 
29         1/1            assign qe = we;
           Tests:       T1 T2 T3 
30         1/1            assign qre = re;
           Tests:       T1 T2 T3 

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_dio_pad_attr_1_virtual_od_en_1

	Line No.	Total	Covered	Percent
TOTAL		5	5	100.00
CONT_ASSIGN	26	1	1	100.00
CONT_ASSIGN	27	1	1	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	30	1	1	100.00

25                        // between qs and ds
26         1/1            assign ds = d;
           Tests:       T20 T21 T22 
27         1/1            assign qs = d;
           Tests:       T20 T21 T22 
28         1/1            assign q = wd;
           Tests:       T1 T2 T3 
29         1/1            assign qe = we;
           Tests:       T1 T2 T3 
30         1/1            assign qre = re;
           Tests:       T1 T2 T3 

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_dio_pad_attr_1_pull_en_1

	Line No.	Total	Covered	Percent
TOTAL		5	5	100.00
CONT_ASSIGN	26	1	1	100.00
CONT_ASSIGN	27	1	1	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	30	1	1	100.00

25                        // between qs and ds
26         1/1            assign ds = d;
           Tests:       T20 T21 T22 
27         1/1            assign qs = d;
           Tests:       T20 T21 T22 
28         1/1            assign q = wd;
           Tests:       T1 T2 T3 
29         1/1            assign qe = we;
           Tests:       T1 T2 T3 
30         1/1            assign qre = re;
           Tests:       T1 T2 T3 

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_dio_pad_attr_1_pull_select_1

	Line No.	Total	Covered	Percent
TOTAL		5	5	100.00
CONT_ASSIGN	26	1	1	100.00
CONT_ASSIGN	27	1	1	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	30	1	1	100.00

25                        // between qs and ds
26         1/1            assign ds = d;
           Tests:       T20 T21 T22 
27         1/1            assign qs = d;
           Tests:       T20 T21 T22 
28         1/1            assign q = wd;
           Tests:       T1 T2 T3 
29         1/1            assign qe = we;
           Tests:       T1 T2 T3 
30         1/1            assign qre = re;
           Tests:       T1 T2 T3 

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_dio_pad_attr_1_keeper_en_1

	Line No.	Total	Covered	Percent
TOTAL		5	3	60.00
CONT_ASSIGN	26	1	0	0.00
CONT_ASSIGN	27	1	0	0.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	30	1	1	100.00

25                        // between qs and ds
26         0/1     ==>    assign ds = d;
27         0/1     ==>    assign qs = d;
28         1/1            assign q = wd;
           Tests:       T1 T2 T3 
29         1/1            assign qe = we;
           Tests:       T1 T2 T3 
30         1/1            assign qre = re;
           Tests:       T1 T2 T3 

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_dio_pad_attr_1_schmitt_en_1

	Line No.	Total	Covered	Percent
TOTAL		5	3	60.00
CONT_ASSIGN	26	1	0	0.00
CONT_ASSIGN	27	1	0	0.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	30	1	1	100.00

25                        // between qs and ds
26         0/1     ==>    assign ds = d;
27         0/1     ==>    assign qs = d;
28         1/1            assign q = wd;
           Tests:       T1 T2 T3 
29         1/1            assign qe = we;
           Tests:       T1 T2 T3 
30         1/1            assign qre = re;
           Tests:       T1 T2 T3 

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_dio_pad_attr_1_od_en_1

	Line No.	Total	Covered	Percent
TOTAL		5	3	60.00
CONT_ASSIGN	26	1	0	0.00
CONT_ASSIGN	27	1	0	0.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	30	1	1	100.00

25                        // between qs and ds
26         0/1     ==>    assign ds = d;
27         0/1     ==>    assign qs = d;
28         1/1            assign q = wd;
           Tests:       T1 T2 T3 
29         1/1            assign qe = we;
           Tests:       T1 T2 T3 
30         1/1            assign qre = re;
           Tests:       T1 T2 T3 

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_dio_pad_attr_1_input_disable_1

	Line No.	Total	Covered	Percent
TOTAL		5	5	100.00
CONT_ASSIGN	26	1	1	100.00
CONT_ASSIGN	27	1	1	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	30	1	1	100.00

25                        // between qs and ds
26         1/1            assign ds = d;
           Tests:       T20 T21 T22 
27         1/1            assign qs = d;
           Tests:       T20 T21 T22 
28         1/1            assign q = wd;
           Tests:       T1 T2 T3 
29         1/1            assign qe = we;
           Tests:       T1 T2 T3 
30         1/1            assign qre = re;
           Tests:       T1 T2 T3 

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_dio_pad_attr_1_slew_rate_1

	Line No.	Total	Covered	Percent
TOTAL		5	3	60.00
CONT_ASSIGN	26	1	0	0.00
CONT_ASSIGN	27	1	0	0.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	30	1	1	100.00

25                        // between qs and ds
26         0/1     ==>    assign ds = d;
27         0/1     ==>    assign qs = d;
28         1/1            assign q = wd;
           Tests:       T1 T2 T3 
29         1/1            assign qe = we;
           Tests:       T1 T2 T3 
30         1/1            assign qre = re;
           Tests:       T1 T2 T3 

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_dio_pad_attr_1_drive_strength_1

	Line No.	Total	Covered	Percent
TOTAL		5	5	100.00
CONT_ASSIGN	26	1	1	100.00
CONT_ASSIGN	27	1	1	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	30	1	1	100.00

25                        // between qs and ds
26         1/1            assign ds = d;
           Tests:       T1 T2 T3 
27         1/1            assign qs = d;
           Tests:       T1 T2 T3 
28         1/1            assign q = wd;
           Tests:       T1 T2 T3 
29         1/1            assign qe = we;
           Tests:       T1 T2 T3 
30         1/1            assign qre = re;
           Tests:       T1 T2 T3 

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_dio_pad_attr_2_invert_2

	Line No.	Total	Covered	Percent
TOTAL		5	5	100.00
CONT_ASSIGN	26	1	1	100.00
CONT_ASSIGN	27	1	1	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	30	1	1	100.00

25                        // between qs and ds
26         1/1            assign ds = d;
           Tests:       T20 T21 T22 
27         1/1            assign qs = d;
           Tests:       T20 T21 T22 
28         1/1            assign q = wd;
           Tests:       T1 T2 T3 
29         1/1            assign qe = we;
           Tests:       T9 T10 T11 
30         1/1            assign qre = re;
           Tests:       T9 T10 T11 

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_dio_pad_attr_2_virtual_od_en_2

	Line No.	Total	Covered	Percent
TOTAL		5	5	100.00
CONT_ASSIGN	26	1	1	100.00
CONT_ASSIGN	27	1	1	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	30	1	1	100.00

25                        // between qs and ds
26         1/1            assign ds = d;
           Tests:       T20 T21 T22 
27         1/1            assign qs = d;
           Tests:       T20 T21 T22 
28         1/1            assign q = wd;
           Tests:       T1 T2 T3 
29         1/1            assign qe = we;
           Tests:       T9 T10 T11 
30         1/1            assign qre = re;
           Tests:       T9 T10 T11 

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_dio_pad_attr_2_pull_en_2

	Line No.	Total	Covered	Percent
TOTAL		5	5	100.00
CONT_ASSIGN	26	1	1	100.00
CONT_ASSIGN	27	1	1	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	30	1	1	100.00

25                        // between qs and ds
26         1/1            assign ds = d;
           Tests:       T9 T10 T11 
27         1/1            assign qs = d;
           Tests:       T9 T10 T11 
28         1/1            assign q = wd;
           Tests:       T1 T2 T3 
29         1/1            assign qe = we;
           Tests:       T9 T10 T11 
30         1/1            assign qre = re;
           Tests:       T9 T10 T11 

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_dio_pad_attr_2_pull_select_2

	Line No.	Total	Covered	Percent
TOTAL		5	5	100.00
CONT_ASSIGN	26	1	1	100.00
CONT_ASSIGN	27	1	1	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	30	1	1	100.00

25                        // between qs and ds
26         1/1            assign ds = d;
           Tests:       T9 T10 T11 
27         1/1            assign qs = d;
           Tests:       T9 T10 T11 
28         1/1            assign q = wd;
           Tests:       T1 T2 T3 
29         1/1            assign qe = we;
           Tests:       T9 T10 T11 
30         1/1            assign qre = re;
           Tests:       T9 T10 T11 

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_dio_pad_attr_2_keeper_en_2

	Line No.	Total	Covered	Percent
TOTAL		5	3	60.00
CONT_ASSIGN	26	1	0	0.00
CONT_ASSIGN	27	1	0	0.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	30	1	1	100.00

25                        // between qs and ds
26         0/1     ==>    assign ds = d;
27         0/1     ==>    assign qs = d;
28         1/1            assign q = wd;
           Tests:       T1 T2 T3 
29         1/1            assign qe = we;
           Tests:       T9 T10 T11 
30         1/1            assign qre = re;
           Tests:       T9 T10 T11 

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_dio_pad_attr_2_schmitt_en_2

	Line No.	Total	Covered	Percent
TOTAL		5	3	60.00
CONT_ASSIGN	26	1	0	0.00
CONT_ASSIGN	27	1	0	0.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	30	1	1	100.00

25                        // between qs and ds
26         0/1     ==>    assign ds = d;
27         0/1     ==>    assign qs = d;
28         1/1            assign q = wd;
           Tests:       T1 T2 T3 
29         1/1            assign qe = we;
           Tests:       T9 T10 T11 
30         1/1            assign qre = re;
           Tests:       T9 T10 T11 

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_dio_pad_attr_2_od_en_2

	Line No.	Total	Covered	Percent
TOTAL		5	3	60.00
CONT_ASSIGN	26	1	0	0.00
CONT_ASSIGN	27	1	0	0.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	30	1	1	100.00

25                        // between qs and ds
26         0/1     ==>    assign ds = d;
27         0/1     ==>    assign qs = d;
28         1/1            assign q = wd;
           Tests:       T1 T2 T3 
29         1/1            assign qe = we;
           Tests:       T9 T10 T11 
30         1/1            assign qre = re;
           Tests:       T9 T10 T11 

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_dio_pad_attr_2_input_disable_2

	Line No.	Total	Covered	Percent
TOTAL		5	5	100.00
CONT_ASSIGN	26	1	1	100.00
CONT_ASSIGN	27	1	1	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	30	1	1	100.00

25                        // between qs and ds
26         1/1            assign ds = d;
           Tests:       T20 T21 T22 
27         1/1            assign qs = d;
           Tests:       T20 T21 T22 
28         1/1            assign q = wd;
           Tests:       T1 T2 T3 
29         1/1            assign qe = we;
           Tests:       T9 T10 T11 
30         1/1            assign qre = re;
           Tests:       T9 T10 T11 

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_dio_pad_attr_2_slew_rate_2

	Line No.	Total	Covered	Percent
TOTAL		5	3	60.00
CONT_ASSIGN	26	1	0	0.00
CONT_ASSIGN	27	1	0	0.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	30	1	1	100.00

25                        // between qs and ds
26         0/1     ==>    assign ds = d;
27         0/1     ==>    assign qs = d;
28         1/1            assign q = wd;
           Tests:       T1 T2 T3 
29         1/1            assign qe = we;
           Tests:       T9 T10 T11 
30         1/1            assign qre = re;
           Tests:       T9 T10 T11 

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_dio_pad_attr_2_drive_strength_2

	Line No.	Total	Covered	Percent
TOTAL		5	5	100.00
CONT_ASSIGN	26	1	1	100.00
CONT_ASSIGN	27	1	1	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	30	1	1	100.00

25                        // between qs and ds
26         1/1            assign ds = d;
           Tests:       T20 T21 T22 
27         1/1            assign qs = d;
           Tests:       T20 T21 T22 
28         1/1            assign q = wd;
           Tests:       T1 T2 T3 
29         1/1            assign qe = we;
           Tests:       T9 T10 T11 
30         1/1            assign qre = re;
           Tests:       T9 T10 T11 

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_dio_pad_attr_3_invert_3

	Line No.	Total	Covered	Percent
TOTAL		5	5	100.00
CONT_ASSIGN	26	1	1	100.00
CONT_ASSIGN	27	1	1	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	30	1	1	100.00

25                        // between qs and ds
26         1/1            assign ds = d;
           Tests:       T20 T21 T22 
27         1/1            assign qs = d;
           Tests:       T20 T21 T22 
28         1/1            assign q = wd;
           Tests:       T1 T2 T3 
29         1/1            assign qe = we;
           Tests:       T9 T10 T11 
30         1/1            assign qre = re;
           Tests:       T9 T10 T11 

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_dio_pad_attr_3_virtual_od_en_3

	Line No.	Total	Covered	Percent
TOTAL		5	5	100.00
CONT_ASSIGN	26	1	1	100.00
CONT_ASSIGN	27	1	1	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	30	1	1	100.00

25                        // between qs and ds
26         1/1            assign ds = d;
           Tests:       T20 T21 T22 
27         1/1            assign qs = d;
           Tests:       T20 T21 T22 
28         1/1            assign q = wd;
           Tests:       T1 T2 T3 
29         1/1            assign qe = we;
           Tests:       T9 T10 T11 
30         1/1            assign qre = re;
           Tests:       T9 T10 T11 

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_dio_pad_attr_3_pull_en_3

	Line No.	Total	Covered	Percent
TOTAL		5	5	100.00
CONT_ASSIGN	26	1	1	100.00
CONT_ASSIGN	27	1	1	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	30	1	1	100.00

25                        // between qs and ds
26         1/1            assign ds = d;
           Tests:       T9 T10 T11 
27         1/1            assign qs = d;
           Tests:       T9 T10 T11 
28         1/1            assign q = wd;
           Tests:       T1 T2 T3 
29         1/1            assign qe = we;
           Tests:       T9 T10 T11 
30         1/1            assign qre = re;
           Tests:       T9 T10 T11 

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_dio_pad_attr_3_pull_select_3

	Line No.	Total	Covered	Percent
TOTAL		5	5	100.00
CONT_ASSIGN	26	1	1	100.00
CONT_ASSIGN	27	1	1	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	30	1	1	100.00

25                        // between qs and ds
26         1/1            assign ds = d;
           Tests:       T9 T10 T11 
27         1/1            assign qs = d;
           Tests:       T9 T10 T11 
28         1/1            assign q = wd;
           Tests:       T1 T2 T3 
29         1/1            assign qe = we;
           Tests:       T9 T10 T11 
30         1/1            assign qre = re;
           Tests:       T9 T10 T11 

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_dio_pad_attr_3_keeper_en_3

	Line No.	Total	Covered	Percent
TOTAL		5	3	60.00
CONT_ASSIGN	26	1	0	0.00
CONT_ASSIGN	27	1	0	0.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	30	1	1	100.00

25                        // between qs and ds
26         0/1     ==>    assign ds = d;
27         0/1     ==>    assign qs = d;
28         1/1            assign q = wd;
           Tests:       T1 T2 T3 
29         1/1            assign qe = we;
           Tests:       T9 T10 T11 
30         1/1            assign qre = re;
           Tests:       T9 T10 T11 

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_dio_pad_attr_3_schmitt_en_3

	Line No.	Total	Covered	Percent
TOTAL		5	3	60.00
CONT_ASSIGN	26	1	0	0.00
CONT_ASSIGN	27	1	0	0.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	30	1	1	100.00

25                        // between qs and ds
26         0/1     ==>    assign ds = d;
27         0/1     ==>    assign qs = d;
28         1/1            assign q = wd;
           Tests:       T1 T2 T3 
29         1/1            assign qe = we;
           Tests:       T9 T10 T11 
30         1/1            assign qre = re;
           Tests:       T9 T10 T11 

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_dio_pad_attr_3_od_en_3

	Line No.	Total	Covered	Percent
TOTAL		5	3	60.00
CONT_ASSIGN	26	1	0	0.00
CONT_ASSIGN	27	1	0	0.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	30	1	1	100.00

25                        // between qs and ds
26         0/1     ==>    assign ds = d;
27         0/1     ==>    assign qs = d;
28         1/1            assign q = wd;
           Tests:       T1 T2 T3 
29         1/1            assign qe = we;
           Tests:       T9 T10 T11 
30         1/1            assign qre = re;
           Tests:       T9 T10 T11 

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_dio_pad_attr_3_input_disable_3

	Line No.	Total	Covered	Percent
TOTAL		5	5	100.00
CONT_ASSIGN	26	1	1	100.00
CONT_ASSIGN	27	1	1	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	30	1	1	100.00

25                        // between qs and ds
26         1/1            assign ds = d;
           Tests:       T20 T21 T22 
27         1/1            assign qs = d;
           Tests:       T20 T21 T22 
28         1/1            assign q = wd;
           Tests:       T1 T2 T3 
29         1/1            assign qe = we;
           Tests:       T9 T10 T11 
30         1/1            assign qre = re;
           Tests:       T9 T10 T11 

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_dio_pad_attr_3_slew_rate_3

	Line No.	Total	Covered	Percent
TOTAL		5	3	60.00
CONT_ASSIGN	26	1	0	0.00
CONT_ASSIGN	27	1	0	0.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	30	1	1	100.00

25                        // between qs and ds
26         0/1     ==>    assign ds = d;
27         0/1     ==>    assign qs = d;
28         1/1            assign q = wd;
           Tests:       T1 T2 T3 
29         1/1            assign qe = we;
           Tests:       T9 T10 T11 
30         1/1            assign qre = re;
           Tests:       T9 T10 T11 

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_dio_pad_attr_3_drive_strength_3

	Line No.	Total	Covered	Percent
TOTAL		5	5	100.00
CONT_ASSIGN	26	1	1	100.00
CONT_ASSIGN	27	1	1	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	30	1	1	100.00

25                        // between qs and ds
26         1/1            assign ds = d;
           Tests:       T20 T21 T22 
27         1/1            assign qs = d;
           Tests:       T20 T21 T22 
28         1/1            assign q = wd;
           Tests:       T1 T2 T3 
29         1/1            assign qe = we;
           Tests:       T9 T10 T11 
30         1/1            assign qre = re;
           Tests:       T9 T10 T11 

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_dio_pad_attr_4_invert_4

	Line No.	Total	Covered	Percent
TOTAL		5	5	100.00
CONT_ASSIGN	26	1	1	100.00
CONT_ASSIGN	27	1	1	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	30	1	1	100.00

25                        // between qs and ds
26         1/1            assign ds = d;
           Tests:       T20 T21 T22 
27         1/1            assign qs = d;
           Tests:       T20 T21 T22 
28         1/1            assign q = wd;
           Tests:       T1 T2 T3 
29         1/1            assign qe = we;
           Tests:       T9 T10 T11 
30         1/1            assign qre = re;
           Tests:       T9 T10 T11 

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_dio_pad_attr_4_virtual_od_en_4

	Line No.	Total	Covered	Percent
TOTAL		5	5	100.00
CONT_ASSIGN	26	1	1	100.00
CONT_ASSIGN	27	1	1	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	30	1	1	100.00

25                        // between qs and ds
26         1/1            assign ds = d;
           Tests:       T20 T21 T22 
27         1/1            assign qs = d;
           Tests:       T20 T21 T22 
28         1/1            assign q = wd;
           Tests:       T1 T2 T3 
29         1/1            assign qe = we;
           Tests:       T9 T10 T11 
30         1/1            assign qre = re;
           Tests:       T9 T10 T11 

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_dio_pad_attr_4_pull_en_4

	Line No.	Total	Covered	Percent
TOTAL		5	5	100.00
CONT_ASSIGN	26	1	1	100.00
CONT_ASSIGN	27	1	1	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	30	1	1	100.00

25                        // between qs and ds
26         1/1            assign ds = d;
           Tests:       T9 T10 T11 
27         1/1            assign qs = d;
           Tests:       T9 T10 T11 
28         1/1            assign q = wd;
           Tests:       T1 T2 T3 
29         1/1            assign qe = we;
           Tests:       T9 T10 T11 
30         1/1            assign qre = re;
           Tests:       T9 T10 T11 

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_dio_pad_attr_4_pull_select_4

	Line No.	Total	Covered	Percent
TOTAL		5	5	100.00
CONT_ASSIGN	26	1	1	100.00
CONT_ASSIGN	27	1	1	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	30	1	1	100.00

25                        // between qs and ds
26         1/1            assign ds = d;
           Tests:       T9 T10 T11 
27         1/1            assign qs = d;
           Tests:       T9 T10 T11 
28         1/1            assign q = wd;
           Tests:       T1 T2 T3 
29         1/1            assign qe = we;
           Tests:       T9 T10 T11 
30         1/1            assign qre = re;
           Tests:       T9 T10 T11 

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_dio_pad_attr_4_keeper_en_4

	Line No.	Total	Covered	Percent
TOTAL		5	3	60.00
CONT_ASSIGN	26	1	0	0.00
CONT_ASSIGN	27	1	0	0.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	30	1	1	100.00

25                        // between qs and ds
26         0/1     ==>    assign ds = d;
27         0/1     ==>    assign qs = d;
28         1/1            assign q = wd;
           Tests:       T1 T2 T3 
29         1/1            assign qe = we;
           Tests:       T9 T10 T11 
30         1/1            assign qre = re;
           Tests:       T9 T10 T11 

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_dio_pad_attr_4_schmitt_en_4

	Line No.	Total	Covered	Percent
TOTAL		5	3	60.00
CONT_ASSIGN	26	1	0	0.00
CONT_ASSIGN	27	1	0	0.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	30	1	1	100.00

25                        // between qs and ds
26         0/1     ==>    assign ds = d;
27         0/1     ==>    assign qs = d;
28         1/1            assign q = wd;
           Tests:       T1 T2 T3 
29         1/1            assign qe = we;
           Tests:       T9 T10 T11 
30         1/1            assign qre = re;
           Tests:       T9 T10 T11 

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_dio_pad_attr_4_od_en_4

	Line No.	Total	Covered	Percent
TOTAL		5	3	60.00
CONT_ASSIGN	26	1	0	0.00
CONT_ASSIGN	27	1	0	0.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	30	1	1	100.00

25                        // between qs and ds
26         0/1     ==>    assign ds = d;
27         0/1     ==>    assign qs = d;
28         1/1            assign q = wd;
           Tests:       T1 T2 T3 
29         1/1            assign qe = we;
           Tests:       T9 T10 T11 
30         1/1            assign qre = re;
           Tests:       T9 T10 T11 

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_dio_pad_attr_4_input_disable_4

	Line No.	Total	Covered	Percent
TOTAL		5	5	100.00
CONT_ASSIGN	26	1	1	100.00
CONT_ASSIGN	27	1	1	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	30	1	1	100.00

25                        // between qs and ds
26         1/1            assign ds = d;
           Tests:       T20 T21 T22 
27         1/1            assign qs = d;
           Tests:       T20 T21 T22 
28         1/1            assign q = wd;
           Tests:       T1 T2 T3 
29         1/1            assign qe = we;
           Tests:       T9 T10 T11 
30         1/1            assign qre = re;
           Tests:       T9 T10 T11 

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_dio_pad_attr_4_slew_rate_4

	Line No.	Total	Covered	Percent
TOTAL		5	3	60.00
CONT_ASSIGN	26	1	0	0.00
CONT_ASSIGN	27	1	0	0.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	30	1	1	100.00

25                        // between qs and ds
26         0/1     ==>    assign ds = d;
27         0/1     ==>    assign qs = d;
28         1/1            assign q = wd;
           Tests:       T1 T2 T3 
29         1/1            assign qe = we;
           Tests:       T9 T10 T11 
30         1/1            assign qre = re;
           Tests:       T9 T10 T11 

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_dio_pad_attr_4_drive_strength_4

	Line No.	Total	Covered	Percent
TOTAL		5	5	100.00
CONT_ASSIGN	26	1	1	100.00
CONT_ASSIGN	27	1	1	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	30	1	1	100.00

25                        // between qs and ds
26         1/1            assign ds = d;
           Tests:       T20 T21 T22 
27         1/1            assign qs = d;
           Tests:       T20 T21 T22 
28         1/1            assign q = wd;
           Tests:       T1 T2 T3 
29         1/1            assign qe = we;
           Tests:       T9 T10 T11 
30         1/1            assign qre = re;
           Tests:       T9 T10 T11 

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_dio_pad_attr_5_invert_5

	Line No.	Total	Covered	Percent
TOTAL		5	5	100.00
CONT_ASSIGN	26	1	1	100.00
CONT_ASSIGN	27	1	1	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	30	1	1	100.00

25                        // between qs and ds
26         1/1            assign ds = d;
           Tests:       T20 T21 T22 
27         1/1            assign qs = d;
           Tests:       T20 T21 T22 
28         1/1            assign q = wd;
           Tests:       T1 T2 T3 
29         1/1            assign qe = we;
           Tests:       T9 T10 T11 
30         1/1            assign qre = re;
           Tests:       T9 T10 T11 

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_dio_pad_attr_5_virtual_od_en_5

	Line No.	Total	Covered	Percent
TOTAL		5	5	100.00
CONT_ASSIGN	26	1	1	100.00
CONT_ASSIGN	27	1	1	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	30	1	1	100.00

25                        // between qs and ds
26         1/1            assign ds = d;
           Tests:       T20 T21 T22 
27         1/1            assign qs = d;
           Tests:       T20 T21 T22 
28         1/1            assign q = wd;
           Tests:       T1 T2 T3 
29         1/1            assign qe = we;
           Tests:       T9 T10 T11 
30         1/1            assign qre = re;
           Tests:       T9 T10 T11 

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_dio_pad_attr_5_pull_en_5

	Line No.	Total	Covered	Percent
TOTAL		5	5	100.00
CONT_ASSIGN	26	1	1	100.00
CONT_ASSIGN	27	1	1	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	30	1	1	100.00

25                        // between qs and ds
26         1/1            assign ds = d;
           Tests:       T9 T10 T11 
27         1/1            assign qs = d;
           Tests:       T9 T10 T11 
28         1/1            assign q = wd;
           Tests:       T1 T2 T3 
29         1/1            assign qe = we;
           Tests:       T9 T10 T11 
30         1/1            assign qre = re;
           Tests:       T9 T10 T11 

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_dio_pad_attr_5_pull_select_5

	Line No.	Total	Covered	Percent
TOTAL		5	5	100.00
CONT_ASSIGN	26	1	1	100.00
CONT_ASSIGN	27	1	1	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	30	1	1	100.00

25                        // between qs and ds
26         1/1            assign ds = d;
           Tests:       T9 T10 T11 
27         1/1            assign qs = d;
           Tests:       T9 T10 T11 
28         1/1            assign q = wd;
           Tests:       T1 T2 T3 
29         1/1            assign qe = we;
           Tests:       T9 T10 T11 
30         1/1            assign qre = re;
           Tests:       T9 T10 T11 

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_dio_pad_attr_5_keeper_en_5

	Line No.	Total	Covered	Percent
TOTAL		5	3	60.00
CONT_ASSIGN	26	1	0	0.00
CONT_ASSIGN	27	1	0	0.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	30	1	1	100.00

25                        // between qs and ds
26         0/1     ==>    assign ds = d;
27         0/1     ==>    assign qs = d;
28         1/1            assign q = wd;
           Tests:       T1 T2 T3 
29         1/1            assign qe = we;
           Tests:       T9 T10 T11 
30         1/1            assign qre = re;
           Tests:       T9 T10 T11 

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_dio_pad_attr_5_schmitt_en_5

	Line No.	Total	Covered	Percent
TOTAL		5	3	60.00
CONT_ASSIGN	26	1	0	0.00
CONT_ASSIGN	27	1	0	0.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	30	1	1	100.00

25                        // between qs and ds
26         0/1     ==>    assign ds = d;
27         0/1     ==>    assign qs = d;
28         1/1            assign q = wd;
           Tests:       T1 T2 T3 
29         1/1            assign qe = we;
           Tests:       T9 T10 T11 
30         1/1            assign qre = re;
           Tests:       T9 T10 T11 

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_dio_pad_attr_5_od_en_5

	Line No.	Total	Covered	Percent
TOTAL		5	3	60.00
CONT_ASSIGN	26	1	0	0.00
CONT_ASSIGN	27	1	0	0.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	30	1	1	100.00

25                        // between qs and ds
26         0/1     ==>    assign ds = d;
27         0/1     ==>    assign qs = d;
28         1/1            assign q = wd;
           Tests:       T1 T2 T3 
29         1/1            assign qe = we;
           Tests:       T9 T10 T11 
30         1/1            assign qre = re;
           Tests:       T9 T10 T11 

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_dio_pad_attr_5_input_disable_5

	Line No.	Total	Covered	Percent
TOTAL		5	5	100.00
CONT_ASSIGN	26	1	1	100.00
CONT_ASSIGN	27	1	1	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	30	1	1	100.00

25                        // between qs and ds
26         1/1            assign ds = d;
           Tests:       T20 T21 T22 
27         1/1            assign qs = d;
           Tests:       T20 T21 T22 
28         1/1            assign q = wd;
           Tests:       T1 T2 T3 
29         1/1            assign qe = we;
           Tests:       T9 T10 T11 
30         1/1            assign qre = re;
           Tests:       T9 T10 T11 

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_dio_pad_attr_5_slew_rate_5

	Line No.	Total	Covered	Percent
TOTAL		5	3	60.00
CONT_ASSIGN	26	1	0	0.00
CONT_ASSIGN	27	1	0	0.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	30	1	1	100.00

25                        // between qs and ds
26         0/1     ==>    assign ds = d;
27         0/1     ==>    assign qs = d;
28         1/1            assign q = wd;
           Tests:       T1 T2 T3 
29         1/1            assign qe = we;
           Tests:       T9 T10 T11 
30         1/1            assign qre = re;
           Tests:       T9 T10 T11 

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_dio_pad_attr_5_drive_strength_5

	Line No.	Total	Covered	Percent
TOTAL		5	5	100.00
CONT_ASSIGN	26	1	1	100.00
CONT_ASSIGN	27	1	1	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	30	1	1	100.00

25                        // between qs and ds
26         1/1            assign ds = d;
           Tests:       T20 T21 T22 
27         1/1            assign qs = d;
           Tests:       T20 T21 T22 
28         1/1            assign q = wd;
           Tests:       T1 T2 T3 
29         1/1            assign qe = we;
           Tests:       T9 T10 T11 
30         1/1            assign qre = re;
           Tests:       T9 T10 T11 

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_dio_pad_attr_6_invert_6

	Line No.	Total	Covered	Percent
TOTAL		5	5	100.00
CONT_ASSIGN	26	1	1	100.00
CONT_ASSIGN	27	1	1	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	30	1	1	100.00

25                        // between qs and ds
26         1/1            assign ds = d;
           Tests:       T20 T21 T22 
27         1/1            assign qs = d;
           Tests:       T20 T21 T22 
28         1/1            assign q = wd;
           Tests:       T1 T2 T3 
29         1/1            assign qe = we;
           Tests:       T96 T97 T98 
30         1/1            assign qre = re;
           Tests:       T96 T97 T98 

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_dio_pad_attr_6_virtual_od_en_6

	Line No.	Total	Covered	Percent
TOTAL		5	5	100.00
CONT_ASSIGN	26	1	1	100.00
CONT_ASSIGN	27	1	1	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	30	1	1	100.00

25                        // between qs and ds
26         1/1            assign ds = d;
           Tests:       T20 T21 T22 
27         1/1            assign qs = d;
           Tests:       T20 T21 T22 
28         1/1            assign q = wd;
           Tests:       T1 T2 T3 
29         1/1            assign qe = we;
           Tests:       T96 T97 T98 
30         1/1            assign qre = re;
           Tests:       T96 T97 T98 

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_dio_pad_attr_6_pull_en_6

	Line No.	Total	Covered	Percent
TOTAL		5	5	100.00
CONT_ASSIGN	26	1	1	100.00
CONT_ASSIGN	27	1	1	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	30	1	1	100.00

25                        // between qs and ds
26         1/1            assign ds = d;
           Tests:       T20 T22 T49 
27         1/1            assign qs = d;
           Tests:       T20 T22 T49 
28         1/1            assign q = wd;
           Tests:       T1 T2 T3 
29         1/1            assign qe = we;
           Tests:       T96 T97 T98 
30         1/1            assign qre = re;
           Tests:       T96 T97 T98 

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_dio_pad_attr_6_pull_select_6

	Line No.	Total	Covered	Percent
TOTAL		5	5	100.00
CONT_ASSIGN	26	1	1	100.00
CONT_ASSIGN	27	1	1	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	30	1	1	100.00

25                        // between qs and ds
26         1/1            assign ds = d;
           Tests:       T20 T21 T22 
27         1/1            assign qs = d;
           Tests:       T20 T21 T22 
28         1/1            assign q = wd;
           Tests:       T1 T2 T3 
29         1/1            assign qe = we;
           Tests:       T96 T97 T98 
30         1/1            assign qre = re;
           Tests:       T96 T97 T98 

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_dio_pad_attr_6_keeper_en_6

	Line No.	Total	Covered	Percent
TOTAL		5	3	60.00
CONT_ASSIGN	26	1	0	0.00
CONT_ASSIGN	27	1	0	0.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	30	1	1	100.00

25                        // between qs and ds
26         0/1     ==>    assign ds = d;
27         0/1     ==>    assign qs = d;
28         1/1            assign q = wd;
           Tests:       T1 T2 T3 
29         1/1            assign qe = we;
           Tests:       T96 T97 T98 
30         1/1            assign qre = re;
           Tests:       T96 T97 T98 

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_dio_pad_attr_6_schmitt_en_6

	Line No.	Total	Covered	Percent
TOTAL		5	3	60.00
CONT_ASSIGN	26	1	0	0.00
CONT_ASSIGN	27	1	0	0.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	30	1	1	100.00

25                        // between qs and ds
26         0/1     ==>    assign ds = d;
27         0/1     ==>    assign qs = d;
28         1/1            assign q = wd;
           Tests:       T1 T2 T3 
29         1/1            assign qe = we;
           Tests:       T96 T97 T98 
30         1/1            assign qre = re;
           Tests:       T96 T97 T98 

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_dio_pad_attr_6_od_en_6

	Line No.	Total	Covered	Percent
TOTAL		5	3	60.00
CONT_ASSIGN	26	1	0	0.00
CONT_ASSIGN	27	1	0	0.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	30	1	1	100.00

25                        // between qs and ds
26         0/1     ==>    assign ds = d;
27         0/1     ==>    assign qs = d;
28         1/1            assign q = wd;
           Tests:       T1 T2 T3 
29         1/1            assign qe = we;
           Tests:       T96 T97 T98 
30         1/1            assign qre = re;
           Tests:       T96 T97 T98 

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_dio_pad_attr_6_input_disable_6

	Line No.	Total	Covered	Percent
TOTAL		5	5	100.00
CONT_ASSIGN	26	1	1	100.00
CONT_ASSIGN	27	1	1	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	30	1	1	100.00

25                        // between qs and ds
26         1/1            assign ds = d;
           Tests:       T20 T21 T22 
27         1/1            assign qs = d;
           Tests:       T20 T21 T22 
28         1/1            assign q = wd;
           Tests:       T1 T2 T3 
29         1/1            assign qe = we;
           Tests:       T96 T97 T98 
30         1/1            assign qre = re;
           Tests:       T96 T97 T98 

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_dio_pad_attr_6_slew_rate_6

	Line No.	Total	Covered	Percent
TOTAL		5	3	60.00
CONT_ASSIGN	26	1	0	0.00
CONT_ASSIGN	27	1	0	0.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	30	1	1	100.00

25                        // between qs and ds
26         0/1     ==>    assign ds = d;
27         0/1     ==>    assign qs = d;
28         1/1            assign q = wd;
           Tests:       T1 T2 T3 
29         1/1            assign qe = we;
           Tests:       T96 T97 T98 
30         1/1            assign qre = re;
           Tests:       T96 T97 T98 

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_dio_pad_attr_6_drive_strength_6

	Line No.	Total	Covered	Percent
TOTAL		5	5	100.00
CONT_ASSIGN	26	1	1	100.00
CONT_ASSIGN	27	1	1	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	30	1	1	100.00

25                        // between qs and ds
26         1/1            assign ds = d;
           Tests:       T20 T21 T22 
27         1/1            assign qs = d;
           Tests:       T20 T21 T22 
28         1/1            assign q = wd;
           Tests:       T1 T2 T3 
29         1/1            assign qe = we;
           Tests:       T96 T97 T98 
30         1/1            assign qre = re;
           Tests:       T96 T97 T98 

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_dio_pad_attr_7_invert_7

	Line No.	Total	Covered	Percent
TOTAL		5	5	100.00
CONT_ASSIGN	26	1	1	100.00
CONT_ASSIGN	27	1	1	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	30	1	1	100.00

25                        // between qs and ds
26         1/1            assign ds = d;
           Tests:       T20 T21 T22 
27         1/1            assign qs = d;
           Tests:       T20 T21 T22 
28         1/1            assign q = wd;
           Tests:       T1 T2 T3 
29         1/1            assign qe = we;
           Tests:       T96 T97 T98 
30         1/1            assign qre = re;
           Tests:       T96 T97 T98 

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_dio_pad_attr_7_virtual_od_en_7

	Line No.	Total	Covered	Percent
TOTAL		5	5	100.00
CONT_ASSIGN	26	1	1	100.00
CONT_ASSIGN	27	1	1	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	30	1	1	100.00

25                        // between qs and ds
26         1/1            assign ds = d;
           Tests:       T20 T21 T22 
27         1/1            assign qs = d;
           Tests:       T20 T21 T22 
28         1/1            assign q = wd;
           Tests:       T1 T2 T3 
29         1/1            assign qe = we;
           Tests:       T96 T97 T98 
30         1/1            assign qre = re;
           Tests:       T96 T97 T98 

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_dio_pad_attr_7_pull_en_7

	Line No.	Total	Covered	Percent
TOTAL		5	5	100.00
CONT_ASSIGN	26	1	1	100.00
CONT_ASSIGN	27	1	1	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	30	1	1	100.00

25                        // between qs and ds
26         1/1            assign ds = d;
           Tests:       T20 T21 T22 
27         1/1            assign qs = d;
           Tests:       T20 T21 T22 
28         1/1            assign q = wd;
           Tests:       T1 T2 T3 
29         1/1            assign qe = we;
           Tests:       T96 T97 T98 
30         1/1            assign qre = re;
           Tests:       T96 T97 T98 

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_dio_pad_attr_7_pull_select_7

	Line No.	Total	Covered	Percent
TOTAL		5	5	100.00
CONT_ASSIGN	26	1	1	100.00
CONT_ASSIGN	27	1	1	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	30	1	1	100.00

25                        // between qs and ds
26         1/1            assign ds = d;
           Tests:       T20 T21 T22 
27         1/1            assign qs = d;
           Tests:       T20 T21 T22 
28         1/1            assign q = wd;
           Tests:       T1 T2 T3 
29         1/1            assign qe = we;
           Tests:       T96 T97 T98 
30         1/1            assign qre = re;
           Tests:       T96 T97 T98 

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_dio_pad_attr_7_keeper_en_7

	Line No.	Total	Covered	Percent
TOTAL		5	3	60.00
CONT_ASSIGN	26	1	0	0.00
CONT_ASSIGN	27	1	0	0.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	30	1	1	100.00

25                        // between qs and ds
26         0/1     ==>    assign ds = d;
27         0/1     ==>    assign qs = d;
28         1/1            assign q = wd;
           Tests:       T1 T2 T3 
29         1/1            assign qe = we;
           Tests:       T96 T97 T98 
30         1/1            assign qre = re;
           Tests:       T96 T97 T98 

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_dio_pad_attr_7_schmitt_en_7

	Line No.	Total	Covered	Percent
TOTAL		5	3	60.00
CONT_ASSIGN	26	1	0	0.00
CONT_ASSIGN	27	1	0	0.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	30	1	1	100.00

25                        // between qs and ds
26         0/1     ==>    assign ds = d;
27         0/1     ==>    assign qs = d;
28         1/1            assign q = wd;
           Tests:       T1 T2 T3 
29         1/1            assign qe = we;
           Tests:       T96 T97 T98 
30         1/1            assign qre = re;
           Tests:       T96 T97 T98 

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_dio_pad_attr_7_od_en_7

	Line No.	Total	Covered	Percent
TOTAL		5	3	60.00
CONT_ASSIGN	26	1	0	0.00
CONT_ASSIGN	27	1	0	0.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	30	1	1	100.00

25                        // between qs and ds
26         0/1     ==>    assign ds = d;
27         0/1     ==>    assign qs = d;
28         1/1            assign q = wd;
           Tests:       T1 T2 T3 
29         1/1            assign qe = we;
           Tests:       T96 T97 T98 
30         1/1            assign qre = re;
           Tests:       T96 T97 T98 

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_dio_pad_attr_7_input_disable_7

	Line No.	Total	Covered	Percent
TOTAL		5	5	100.00
CONT_ASSIGN	26	1	1	100.00
CONT_ASSIGN	27	1	1	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	30	1	1	100.00

25                        // between qs and ds
26         1/1            assign ds = d;
           Tests:       T20 T21 T22 
27         1/1            assign qs = d;
           Tests:       T20 T21 T22 
28         1/1            assign q = wd;
           Tests:       T1 T2 T3 
29         1/1            assign qe = we;
           Tests:       T96 T97 T98 
30         1/1            assign qre = re;
           Tests:       T96 T97 T98 

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_dio_pad_attr_7_slew_rate_7

	Line No.	Total	Covered	Percent
TOTAL		5	3	60.00
CONT_ASSIGN	26	1	0	0.00
CONT_ASSIGN	27	1	0	0.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	30	1	1	100.00

25                        // between qs and ds
26         0/1     ==>    assign ds = d;
27         0/1     ==>    assign qs = d;
28         1/1            assign q = wd;
           Tests:       T1 T2 T3 
29         1/1            assign qe = we;
           Tests:       T96 T97 T98 
30         1/1            assign qre = re;
           Tests:       T96 T97 T98 

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_dio_pad_attr_7_drive_strength_7

	Line No.	Total	Covered	Percent
TOTAL		5	5	100.00
CONT_ASSIGN	26	1	1	100.00
CONT_ASSIGN	27	1	1	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	30	1	1	100.00

25                        // between qs and ds
26         1/1            assign ds = d;
           Tests:       T20 T21 T22 
27         1/1            assign qs = d;
           Tests:       T20 T21 T22 
28         1/1            assign q = wd;
           Tests:       T1 T2 T3 
29         1/1            assign qe = we;
           Tests:       T96 T97 T98 
30         1/1            assign qre = re;
           Tests:       T96 T97 T98 

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_dio_pad_attr_8_invert_8

	Line No.	Total	Covered	Percent
TOTAL		5	5	100.00
CONT_ASSIGN	26	1	1	100.00
CONT_ASSIGN	27	1	1	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	30	1	1	100.00

25                        // between qs and ds
26         1/1            assign ds = d;
           Tests:       T20 T21 T22 
27         1/1            assign qs = d;
           Tests:       T20 T21 T22 
28         1/1            assign q = wd;
           Tests:       T1 T2 T3 
29         1/1            assign qe = we;
           Tests:       T96 T97 T98 
30         1/1            assign qre = re;
           Tests:       T96 T97 T98 

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_dio_pad_attr_8_virtual_od_en_8

	Line No.	Total	Covered	Percent
TOTAL		5	5	100.00
CONT_ASSIGN	26	1	1	100.00
CONT_ASSIGN	27	1	1	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	30	1	1	100.00

25                        // between qs and ds
26         1/1            assign ds = d;
           Tests:       T20 T21 T22 
27         1/1            assign qs = d;
           Tests:       T20 T21 T22 
28         1/1            assign q = wd;
           Tests:       T1 T2 T3 
29         1/1            assign qe = we;
           Tests:       T96 T97 T98 
30         1/1            assign qre = re;
           Tests:       T96 T97 T98 

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_dio_pad_attr_8_pull_en_8

	Line No.	Total	Covered	Percent
TOTAL		5	5	100.00
CONT_ASSIGN	26	1	1	100.00
CONT_ASSIGN	27	1	1	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	30	1	1	100.00

25                        // between qs and ds
26         1/1            assign ds = d;
           Tests:       T20 T21 T22 
27         1/1            assign qs = d;
           Tests:       T20 T21 T22 
28         1/1            assign q = wd;
           Tests:       T1 T2 T3 
29         1/1            assign qe = we;
           Tests:       T96 T97 T98 
30         1/1            assign qre = re;
           Tests:       T96 T97 T98 

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_dio_pad_attr_8_pull_select_8

	Line No.	Total	Covered	Percent
TOTAL		5	5	100.00
CONT_ASSIGN	26	1	1	100.00
CONT_ASSIGN	27	1	1	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	30	1	1	100.00

25                        // between qs and ds
26         1/1            assign ds = d;
           Tests:       T20 T21 T22 
27         1/1            assign qs = d;
           Tests:       T20 T21 T22 
28         1/1            assign q = wd;
           Tests:       T1 T2 T3 
29         1/1            assign qe = we;
           Tests:       T96 T97 T98 
30         1/1            assign qre = re;
           Tests:       T96 T97 T98 

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_dio_pad_attr_8_keeper_en_8

	Line No.	Total	Covered	Percent
TOTAL		5	3	60.00
CONT_ASSIGN	26	1	0	0.00
CONT_ASSIGN	27	1	0	0.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	30	1	1	100.00

25                        // between qs and ds
26         0/1     ==>    assign ds = d;
27         0/1     ==>    assign qs = d;
28         1/1            assign q = wd;
           Tests:       T1 T2 T3 
29         1/1            assign qe = we;
           Tests:       T96 T97 T98 
30         1/1            assign qre = re;
           Tests:       T96 T97 T98 

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_dio_pad_attr_8_schmitt_en_8

	Line No.	Total	Covered	Percent
TOTAL		5	3	60.00
CONT_ASSIGN	26	1	0	0.00
CONT_ASSIGN	27	1	0	0.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	30	1	1	100.00

25                        // between qs and ds
26         0/1     ==>    assign ds = d;
27         0/1     ==>    assign qs = d;
28         1/1            assign q = wd;
           Tests:       T1 T2 T3 
29         1/1            assign qe = we;
           Tests:       T96 T97 T98 
30         1/1            assign qre = re;
           Tests:       T96 T97 T98 

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_dio_pad_attr_8_od_en_8

	Line No.	Total	Covered	Percent
TOTAL		5	3	60.00
CONT_ASSIGN	26	1	0	0.00
CONT_ASSIGN	27	1	0	0.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	30	1	1	100.00

25                        // between qs and ds
26         0/1     ==>    assign ds = d;
27         0/1     ==>    assign qs = d;
28         1/1            assign q = wd;
           Tests:       T1 T2 T3 
29         1/1            assign qe = we;
           Tests:       T96 T97 T98 
30         1/1            assign qre = re;
           Tests:       T96 T97 T98 

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_dio_pad_attr_8_input_disable_8

	Line No.	Total	Covered	Percent
TOTAL		5	5	100.00
CONT_ASSIGN	26	1	1	100.00
CONT_ASSIGN	27	1	1	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	30	1	1	100.00

25                        // between qs and ds
26         1/1            assign ds = d;
           Tests:       T20 T21 T22 
27         1/1            assign qs = d;
           Tests:       T20 T21 T22 
28         1/1            assign q = wd;
           Tests:       T1 T2 T3 
29         1/1            assign qe = we;
           Tests:       T96 T97 T98 
30         1/1            assign qre = re;
           Tests:       T96 T97 T98 

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_dio_pad_attr_8_slew_rate_8

	Line No.	Total	Covered	Percent
TOTAL		5	3	60.00
CONT_ASSIGN	26	1	0	0.00
CONT_ASSIGN	27	1	0	0.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	30	1	1	100.00

25                        // between qs and ds
26         0/1     ==>    assign ds = d;
27         0/1     ==>    assign qs = d;
28         1/1            assign q = wd;
           Tests:       T1 T2 T3 
29         1/1            assign qe = we;
           Tests:       T96 T97 T98 
30         1/1            assign qre = re;
           Tests:       T96 T97 T98 

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_dio_pad_attr_8_drive_strength_8

	Line No.	Total	Covered	Percent
TOTAL		5	5	100.00
CONT_ASSIGN	26	1	1	100.00
CONT_ASSIGN	27	1	1	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	30	1	1	100.00

25                        // between qs and ds
26         1/1            assign ds = d;
           Tests:       T20 T21 T22 
27         1/1            assign qs = d;
           Tests:       T20 T21 T22 
28         1/1            assign q = wd;
           Tests:       T1 T2 T3 
29         1/1            assign qe = we;
           Tests:       T96 T97 T98 
30         1/1            assign qre = re;
           Tests:       T96 T97 T98 

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_dio_pad_attr_9_invert_9

	Line No.	Total	Covered	Percent
TOTAL		5	5	100.00
CONT_ASSIGN	26	1	1	100.00
CONT_ASSIGN	27	1	1	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	30	1	1	100.00

25                        // between qs and ds
26         1/1            assign ds = d;
           Tests:       T20 T21 T22 
27         1/1            assign qs = d;
           Tests:       T20 T21 T22 
28         1/1            assign q = wd;
           Tests:       T1 T2 T3 
29         1/1            assign qe = we;
           Tests:       T96 T97 T98 
30         1/1            assign qre = re;
           Tests:       T96 T97 T98 

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_dio_pad_attr_9_virtual_od_en_9

	Line No.	Total	Covered	Percent
TOTAL		5	5	100.00
CONT_ASSIGN	26	1	1	100.00
CONT_ASSIGN	27	1	1	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	30	1	1	100.00

25                        // between qs and ds
26         1/1            assign ds = d;
           Tests:       T20 T21 T22 
27         1/1            assign qs = d;
           Tests:       T20 T21 T22 
28         1/1            assign q = wd;
           Tests:       T1 T2 T3 
29         1/1            assign qe = we;
           Tests:       T96 T97 T98 
30         1/1            assign qre = re;
           Tests:       T96 T97 T98 

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_dio_pad_attr_9_pull_en_9

	Line No.	Total	Covered	Percent
TOTAL		5	5	100.00
CONT_ASSIGN	26	1	1	100.00
CONT_ASSIGN	27	1	1	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	30	1	1	100.00

25                        // between qs and ds
26         1/1            assign ds = d;
           Tests:       T20 T21 T22 
27         1/1            assign qs = d;
           Tests:       T20 T21 T22 
28         1/1            assign q = wd;
           Tests:       T1 T2 T3 
29         1/1            assign qe = we;
           Tests:       T96 T97 T98 
30         1/1            assign qre = re;
           Tests:       T96 T97 T98 

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_dio_pad_attr_9_pull_select_9

	Line No.	Total	Covered	Percent
TOTAL		5	5	100.00
CONT_ASSIGN	26	1	1	100.00
CONT_ASSIGN	27	1	1	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	30	1	1	100.00

25                        // between qs and ds
26         1/1            assign ds = d;
           Tests:       T20 T21 T49 
27         1/1            assign qs = d;
           Tests:       T20 T21 T49 
28         1/1            assign q = wd;
           Tests:       T1 T2 T3 
29         1/1            assign qe = we;
           Tests:       T96 T97 T98 
30         1/1            assign qre = re;
           Tests:       T96 T97 T98 

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_dio_pad_attr_9_keeper_en_9

	Line No.	Total	Covered	Percent
TOTAL		5	3	60.00
CONT_ASSIGN	26	1	0	0.00
CONT_ASSIGN	27	1	0	0.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	30	1	1	100.00

25                        // between qs and ds
26         0/1     ==>    assign ds = d;
27         0/1     ==>    assign qs = d;
28         1/1            assign q = wd;
           Tests:       T1 T2 T3 
29         1/1            assign qe = we;
           Tests:       T96 T97 T98 
30         1/1            assign qre = re;
           Tests:       T96 T97 T98 

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_dio_pad_attr_9_schmitt_en_9

	Line No.	Total	Covered	Percent
TOTAL		5	3	60.00
CONT_ASSIGN	26	1	0	0.00
CONT_ASSIGN	27	1	0	0.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	30	1	1	100.00

25                        // between qs and ds
26         0/1     ==>    assign ds = d;
27         0/1     ==>    assign qs = d;
28         1/1            assign q = wd;
           Tests:       T1 T2 T3 
29         1/1            assign qe = we;
           Tests:       T96 T97 T98 
30         1/1            assign qre = re;
           Tests:       T96 T97 T98 

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_dio_pad_attr_9_od_en_9

	Line No.	Total	Covered	Percent
TOTAL		5	3	60.00
CONT_ASSIGN	26	1	0	0.00
CONT_ASSIGN	27	1	0	0.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	30	1	1	100.00

25                        // between qs and ds
26         0/1     ==>    assign ds = d;
27         0/1     ==>    assign qs = d;
28         1/1            assign q = wd;
           Tests:       T1 T2 T3 
29         1/1            assign qe = we;
           Tests:       T96 T97 T98 
30         1/1            assign qre = re;
           Tests:       T96 T97 T98 

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_dio_pad_attr_9_input_disable_9

	Line No.	Total	Covered	Percent
TOTAL		5	5	100.00
CONT_ASSIGN	26	1	1	100.00
CONT_ASSIGN	27	1	1	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	30	1	1	100.00

25                        // between qs and ds
26         1/1            assign ds = d;
           Tests:       T20 T21 T22 
27         1/1            assign qs = d;
           Tests:       T20 T21 T22 
28         1/1            assign q = wd;
           Tests:       T1 T2 T3 
29         1/1            assign qe = we;
           Tests:       T96 T97 T98 
30         1/1            assign qre = re;
           Tests:       T96 T97 T98 

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_dio_pad_attr_9_slew_rate_9

	Line No.	Total	Covered	Percent
TOTAL		5	3	60.00
CONT_ASSIGN	26	1	0	0.00
CONT_ASSIGN	27	1	0	0.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	30	1	1	100.00

25                        // between qs and ds
26         0/1     ==>    assign ds = d;
27         0/1     ==>    assign qs = d;
28         1/1            assign q = wd;
           Tests:       T1 T2 T3 
29         1/1            assign qe = we;
           Tests:       T96 T97 T98 
30         1/1            assign qre = re;
           Tests:       T96 T97 T98 

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_dio_pad_attr_9_drive_strength_9

	Line No.	Total	Covered	Percent
TOTAL		5	5	100.00
CONT_ASSIGN	26	1	1	100.00
CONT_ASSIGN	27	1	1	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	30	1	1	100.00

25                        // between qs and ds
26         1/1            assign ds = d;
           Tests:       T20 T21 T22 
27         1/1            assign qs = d;
           Tests:       T20 T21 T22 
28         1/1            assign q = wd;
           Tests:       T1 T2 T3 
29         1/1            assign qe = we;
           Tests:       T96 T97 T98 
30         1/1            assign qre = re;
           Tests:       T96 T97 T98 

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_dio_pad_attr_10_invert_10

	Line No.	Total	Covered	Percent
TOTAL		5	5	100.00
CONT_ASSIGN	26	1	1	100.00
CONT_ASSIGN	27	1	1	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	30	1	1	100.00

25                        // between qs and ds
26         1/1            assign ds = d;
           Tests:       T20 T21 T22 
27         1/1            assign qs = d;
           Tests:       T20 T21 T22 
28         1/1            assign q = wd;
           Tests:       T1 T2 T3 
29         1/1            assign qe = we;
           Tests:       T15 T51 T52 
30         1/1            assign qre = re;
           Tests:       T15 T51 T52 

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_dio_pad_attr_10_virtual_od_en_10

	Line No.	Total	Covered	Percent
TOTAL		5	5	100.00
CONT_ASSIGN	26	1	1	100.00
CONT_ASSIGN	27	1	1	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	30	1	1	100.00

25                        // between qs and ds
26         1/1            assign ds = d;
           Tests:       T15 T51 T52 
27         1/1            assign qs = d;
           Tests:       T15 T51 T52 
28         1/1            assign q = wd;
           Tests:       T1 T2 T3 
29         1/1            assign qe = we;
           Tests:       T15 T51 T52 
30         1/1            assign qre = re;
           Tests:       T15 T51 T52 

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_dio_pad_attr_10_pull_en_10

	Line No.	Total	Covered	Percent
TOTAL		5	5	100.00
CONT_ASSIGN	26	1	1	100.00
CONT_ASSIGN	27	1	1	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	30	1	1	100.00

25                        // between qs and ds
26         1/1            assign ds = d;
           Tests:       T20 T21 T22 
27         1/1            assign qs = d;
           Tests:       T20 T21 T22 
28         1/1            assign q = wd;
           Tests:       T1 T2 T3 
29         1/1            assign qe = we;
           Tests:       T15 T51 T52 
30         1/1            assign qre = re;
           Tests:       T15 T51 T52 

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_dio_pad_attr_10_pull_select_10

	Line No.	Total	Covered	Percent
TOTAL		5	5	100.00
CONT_ASSIGN	26	1	1	100.00
CONT_ASSIGN	27	1	1	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	30	1	1	100.00

25                        // between qs and ds
26         1/1            assign ds = d;
           Tests:       T20 T21 T22 
27         1/1            assign qs = d;
           Tests:       T20 T21 T22 
28         1/1            assign q = wd;
           Tests:       T1 T2 T3 
29         1/1            assign qe = we;
           Tests:       T15 T51 T52 
30         1/1            assign qre = re;
           Tests:       T15 T51 T52 

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_dio_pad_attr_10_keeper_en_10

	Line No.	Total	Covered	Percent
TOTAL		5	3	60.00
CONT_ASSIGN	26	1	0	0.00
CONT_ASSIGN	27	1	0	0.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	30	1	1	100.00

25                        // between qs and ds
26         0/1     ==>    assign ds = d;
27         0/1     ==>    assign qs = d;
28         1/1            assign q = wd;
           Tests:       T1 T2 T3 
29         1/1            assign qe = we;
           Tests:       T15 T51 T52 
30         1/1            assign qre = re;
           Tests:       T15 T51 T52 

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_dio_pad_attr_10_schmitt_en_10

	Line No.	Total	Covered	Percent
TOTAL		5	3	60.00
CONT_ASSIGN	26	1	0	0.00
CONT_ASSIGN	27	1	0	0.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	30	1	1	100.00

25                        // between qs and ds
26         0/1     ==>    assign ds = d;
27         0/1     ==>    assign qs = d;
28         1/1            assign q = wd;
           Tests:       T1 T2 T3 
29         1/1            assign qe = we;
           Tests:       T15 T51 T52 
30         1/1            assign qre = re;
           Tests:       T15 T51 T52 

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_dio_pad_attr_10_od_en_10

	Line No.	Total	Covered	Percent
TOTAL		5	3	60.00
CONT_ASSIGN	26	1	0	0.00
CONT_ASSIGN	27	1	0	0.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	30	1	1	100.00

25                        // between qs and ds
26         0/1     ==>    assign ds = d;
27         0/1     ==>    assign qs = d;
28         1/1            assign q = wd;
           Tests:       T1 T2 T3 
29         1/1            assign qe = we;
           Tests:       T15 T51 T52 
30         1/1            assign qre = re;
           Tests:       T15 T51 T52 

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_dio_pad_attr_10_input_disable_10

	Line No.	Total	Covered	Percent
TOTAL		5	5	100.00
CONT_ASSIGN	26	1	1	100.00
CONT_ASSIGN	27	1	1	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	30	1	1	100.00

25                        // between qs and ds
26         1/1            assign ds = d;
           Tests:       T20 T21 T22 
27         1/1            assign qs = d;
           Tests:       T20 T21 T22 
28         1/1            assign q = wd;
           Tests:       T1 T2 T3 
29         1/1            assign qe = we;
           Tests:       T15 T51 T52 
30         1/1            assign qre = re;
           Tests:       T15 T51 T52 

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_dio_pad_attr_10_slew_rate_10

	Line No.	Total	Covered	Percent
TOTAL		5	3	60.00
CONT_ASSIGN	26	1	0	0.00
CONT_ASSIGN	27	1	0	0.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	30	1	1	100.00

25                        // between qs and ds
26         0/1     ==>    assign ds = d;
27         0/1     ==>    assign qs = d;
28         1/1            assign q = wd;
           Tests:       T1 T2 T3 
29         1/1            assign qe = we;
           Tests:       T15 T51 T52 
30         1/1            assign qre = re;
           Tests:       T15 T51 T52 

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_dio_pad_attr_10_drive_strength_10

	Line No.	Total	Covered	Percent
TOTAL		5	5	100.00
CONT_ASSIGN	26	1	1	100.00
CONT_ASSIGN	27	1	1	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	30	1	1	100.00

25                        // between qs and ds
26         1/1            assign ds = d;
           Tests:       T20 T21 T22 
27         1/1            assign qs = d;
           Tests:       T20 T21 T22 
28         1/1            assign q = wd;
           Tests:       T1 T2 T3 
29         1/1            assign qe = we;
           Tests:       T15 T51 T52 
30         1/1            assign qre = re;
           Tests:       T15 T51 T52 

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_dio_pad_attr_11_invert_11

	Line No.	Total	Covered	Percent
TOTAL		5	5	100.00
CONT_ASSIGN	26	1	1	100.00
CONT_ASSIGN	27	1	1	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	30	1	1	100.00

25                        // between qs and ds
26         1/1            assign ds = d;
           Tests:       T20 T21 T22 
27         1/1            assign qs = d;
           Tests:       T20 T21 T22 
28         1/1            assign q = wd;
           Tests:       T1 T2 T3 
29         1/1            assign qe = we;
           Tests:       T15 T51 T52 
30         1/1            assign qre = re;
           Tests:       T15 T51 T52 

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_dio_pad_attr_11_virtual_od_en_11

	Line No.	Total	Covered	Percent
TOTAL		5	5	100.00
CONT_ASSIGN	26	1	1	100.00
CONT_ASSIGN	27	1	1	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	30	1	1	100.00

25                        // between qs and ds
26         1/1            assign ds = d;
           Tests:       T15 T51 T52 
27         1/1            assign qs = d;
           Tests:       T15 T51 T52 
28         1/1            assign q = wd;
           Tests:       T1 T2 T3 
29         1/1            assign qe = we;
           Tests:       T15 T51 T52 
30         1/1            assign qre = re;
           Tests:       T15 T51 T52 

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_dio_pad_attr_11_pull_en_11

	Line No.	Total	Covered	Percent
TOTAL		5	5	100.00
CONT_ASSIGN	26	1	1	100.00
CONT_ASSIGN	27	1	1	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	30	1	1	100.00

25                        // between qs and ds
26         1/1            assign ds = d;
           Tests:       T20 T21 T22 
27         1/1            assign qs = d;
           Tests:       T20 T21 T22 
28         1/1            assign q = wd;
           Tests:       T1 T2 T3 
29         1/1            assign qe = we;
           Tests:       T15 T51 T52 
30         1/1            assign qre = re;
           Tests:       T15 T51 T52 

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_dio_pad_attr_11_pull_select_11

	Line No.	Total	Covered	Percent
TOTAL		5	5	100.00
CONT_ASSIGN	26	1	1	100.00
CONT_ASSIGN	27	1	1	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	30	1	1	100.00

25                        // between qs and ds
26         1/1            assign ds = d;
           Tests:       T20 T22 T49 
27         1/1            assign qs = d;
           Tests:       T20 T22 T49 
28         1/1            assign q = wd;
           Tests:       T1 T2 T3 
29         1/1            assign qe = we;
           Tests:       T15 T51 T52 
30         1/1            assign qre = re;
           Tests:       T15 T51 T52 

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_dio_pad_attr_11_keeper_en_11

	Line No.	Total	Covered	Percent
TOTAL		5	3	60.00
CONT_ASSIGN	26	1	0	0.00
CONT_ASSIGN	27	1	0	0.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	30	1	1	100.00

25                        // between qs and ds
26         0/1     ==>    assign ds = d;
27         0/1     ==>    assign qs = d;
28         1/1            assign q = wd;
           Tests:       T1 T2 T3 
29         1/1            assign qe = we;
           Tests:       T15 T51 T52 
30         1/1            assign qre = re;
           Tests:       T15 T51 T52 

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_dio_pad_attr_11_schmitt_en_11

	Line No.	Total	Covered	Percent
TOTAL		5	3	60.00
CONT_ASSIGN	26	1	0	0.00
CONT_ASSIGN	27	1	0	0.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	30	1	1	100.00

25                        // between qs and ds
26         0/1     ==>    assign ds = d;
27         0/1     ==>    assign qs = d;
28         1/1            assign q = wd;
           Tests:       T1 T2 T3 
29         1/1            assign qe = we;
           Tests:       T15 T51 T52 
30         1/1            assign qre = re;
           Tests:       T15 T51 T52 

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_dio_pad_attr_11_od_en_11

	Line No.	Total	Covered	Percent
TOTAL		5	3	60.00
CONT_ASSIGN	26	1	0	0.00
CONT_ASSIGN	27	1	0	0.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	30	1	1	100.00

25                        // between qs and ds
26         0/1     ==>    assign ds = d;
27         0/1     ==>    assign qs = d;
28         1/1            assign q = wd;
           Tests:       T1 T2 T3 
29         1/1            assign qe = we;
           Tests:       T15 T51 T52 
30         1/1            assign qre = re;
           Tests:       T15 T51 T52 

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_dio_pad_attr_11_input_disable_11

	Line No.	Total	Covered	Percent
TOTAL		5	5	100.00
CONT_ASSIGN	26	1	1	100.00
CONT_ASSIGN	27	1	1	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	30	1	1	100.00

25                        // between qs and ds
26         1/1            assign ds = d;
           Tests:       T20 T21 T22 
27         1/1            assign qs = d;
           Tests:       T20 T21 T22 
28         1/1            assign q = wd;
           Tests:       T1 T2 T3 
29         1/1            assign qe = we;
           Tests:       T15 T51 T52 
30         1/1            assign qre = re;
           Tests:       T15 T51 T52 

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_dio_pad_attr_11_slew_rate_11

	Line No.	Total	Covered	Percent
TOTAL		5	3	60.00
CONT_ASSIGN	26	1	0	0.00
CONT_ASSIGN	27	1	0	0.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	30	1	1	100.00

25                        // between qs and ds
26         0/1     ==>    assign ds = d;
27         0/1     ==>    assign qs = d;
28         1/1            assign q = wd;
           Tests:       T1 T2 T3 
29         1/1            assign qe = we;
           Tests:       T15 T51 T52 
30         1/1            assign qre = re;
           Tests:       T15 T51 T52 

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_dio_pad_attr_11_drive_strength_11

	Line No.	Total	Covered	Percent
TOTAL		5	5	100.00
CONT_ASSIGN	26	1	1	100.00
CONT_ASSIGN	27	1	1	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	30	1	1	100.00

25                        // between qs and ds
26         1/1            assign ds = d;
           Tests:       T20 T21 T22 
27         1/1            assign qs = d;
           Tests:       T20 T21 T22 
28         1/1            assign q = wd;
           Tests:       T1 T2 T3 
29         1/1            assign qe = we;
           Tests:       T15 T51 T52 
30         1/1            assign qre = re;
           Tests:       T15 T51 T52 

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_dio_pad_attr_12_invert_12

	Line No.	Total	Covered	Percent
TOTAL		5	5	100.00
CONT_ASSIGN	26	1	1	100.00
CONT_ASSIGN	27	1	1	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	30	1	1	100.00

25                        // between qs and ds
26         1/1            assign ds = d;
           Tests:       T20 T21 T22 
27         1/1            assign qs = d;
           Tests:       T20 T21 T22 
28         1/1            assign q = wd;
           Tests:       T1 T2 T3 
29         1/1            assign qe = we;
           Tests:       T96 T97 T98 
30         1/1            assign qre = re;
           Tests:       T96 T97 T98 

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_dio_pad_attr_12_virtual_od_en_12

	Line No.	Total	Covered	Percent
TOTAL		5	3	60.00
CONT_ASSIGN	26	1	0	0.00
CONT_ASSIGN	27	1	0	0.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	30	1	1	100.00

25                        // between qs and ds
26         0/1     ==>    assign ds = d;
27         0/1     ==>    assign qs = d;
28         1/1            assign q = wd;
           Tests:       T1 T2 T3 
29         1/1            assign qe = we;
           Tests:       T96 T97 T98 
30         1/1            assign qre = re;
           Tests:       T96 T97 T98 

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_dio_pad_attr_12_pull_en_12

	Line No.	Total	Covered	Percent
TOTAL		5	5	100.00
CONT_ASSIGN	26	1	1	100.00
CONT_ASSIGN	27	1	1	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	30	1	1	100.00

25                        // between qs and ds
26         1/1            assign ds = d;
           Tests:       T20 T21 T22 
27         1/1            assign qs = d;
           Tests:       T20 T21 T22 
28         1/1            assign q = wd;
           Tests:       T1 T2 T3 
29         1/1            assign qe = we;
           Tests:       T96 T97 T98 
30         1/1            assign qre = re;
           Tests:       T96 T97 T98 

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_dio_pad_attr_12_pull_select_12

	Line No.	Total	Covered	Percent
TOTAL		5	5	100.00
CONT_ASSIGN	26	1	1	100.00
CONT_ASSIGN	27	1	1	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	30	1	1	100.00

25                        // between qs and ds
26         1/1            assign ds = d;
           Tests:       T20 T21 T22 
27         1/1            assign qs = d;
           Tests:       T20 T21 T22 
28         1/1            assign q = wd;
           Tests:       T1 T2 T3 
29         1/1            assign qe = we;
           Tests:       T96 T97 T98 
30         1/1            assign qre = re;
           Tests:       T96 T97 T98 

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_dio_pad_attr_12_keeper_en_12

	Line No.	Total	Covered	Percent
TOTAL		5	3	60.00
CONT_ASSIGN	26	1	0	0.00
CONT_ASSIGN	27	1	0	0.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	30	1	1	100.00

25                        // between qs and ds
26         0/1     ==>    assign ds = d;
27         0/1     ==>    assign qs = d;
28         1/1            assign q = wd;
           Tests:       T1 T2 T3 
29         1/1            assign qe = we;
           Tests:       T96 T97 T98 
30         1/1            assign qre = re;
           Tests:       T96 T97 T98 

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_dio_pad_attr_12_schmitt_en_12

	Line No.	Total	Covered	Percent
TOTAL		5	3	60.00
CONT_ASSIGN	26	1	0	0.00
CONT_ASSIGN	27	1	0	0.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	30	1	1	100.00

25                        // between qs and ds
26         0/1     ==>    assign ds = d;
27         0/1     ==>    assign qs = d;
28         1/1            assign q = wd;
           Tests:       T1 T2 T3 
29         1/1            assign qe = we;
           Tests:       T96 T97 T98 
30         1/1            assign qre = re;
           Tests:       T96 T97 T98 

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_dio_pad_attr_12_od_en_12

	Line No.	Total	Covered	Percent
TOTAL		5	3	60.00
CONT_ASSIGN	26	1	0	0.00
CONT_ASSIGN	27	1	0	0.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	30	1	1	100.00

25                        // between qs and ds
26         0/1     ==>    assign ds = d;
27         0/1     ==>    assign qs = d;
28         1/1            assign q = wd;
           Tests:       T1 T2 T3 
29         1/1            assign qe = we;
           Tests:       T96 T97 T98 
30         1/1            assign qre = re;
           Tests:       T96 T97 T98 

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_dio_pad_attr_12_input_disable_12

	Line No.	Total	Covered	Percent
TOTAL		5	5	100.00
CONT_ASSIGN	26	1	1	100.00
CONT_ASSIGN	27	1	1	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	30	1	1	100.00

25                        // between qs and ds
26         1/1            assign ds = d;
           Tests:       T20 T21 T22 
27         1/1            assign qs = d;
           Tests:       T20 T21 T22 
28         1/1            assign q = wd;
           Tests:       T1 T2 T3 
29         1/1            assign qe = we;
           Tests:       T96 T97 T98 
30         1/1            assign qre = re;
           Tests:       T96 T97 T98 

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_dio_pad_attr_12_slew_rate_12

	Line No.	Total	Covered	Percent
TOTAL		5	3	60.00
CONT_ASSIGN	26	1	0	0.00
CONT_ASSIGN	27	1	0	0.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	30	1	1	100.00

25                        // between qs and ds
26         0/1     ==>    assign ds = d;
27         0/1     ==>    assign qs = d;
28         1/1            assign q = wd;
           Tests:       T1 T2 T3 
29         1/1            assign qe = we;
           Tests:       T96 T97 T98 
30         1/1            assign qre = re;
           Tests:       T96 T97 T98 

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_dio_pad_attr_12_drive_strength_12

	Line No.	Total	Covered	Percent
TOTAL		5	3	60.00
CONT_ASSIGN	26	1	0	0.00
CONT_ASSIGN	27	1	0	0.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	30	1	1	100.00

25                        // between qs and ds
26         0/1     ==>    assign ds = d;
27         0/1     ==>    assign qs = d;
28         1/1            assign q = wd;
           Tests:       T1 T2 T3 
29         1/1            assign qe = we;
           Tests:       T96 T97 T98 
30         1/1            assign qre = re;
           Tests:       T96 T97 T98 

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_dio_pad_attr_13_invert_13

	Line No.	Total	Covered	Percent
TOTAL		5	5	100.00
CONT_ASSIGN	26	1	1	100.00
CONT_ASSIGN	27	1	1	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	30	1	1	100.00

25                        // between qs and ds
26         1/1            assign ds = d;
           Tests:       T20 T21 T22 
27         1/1            assign qs = d;
           Tests:       T20 T21 T22 
28         1/1            assign q = wd;
           Tests:       T1 T2 T3 
29         1/1            assign qe = we;
           Tests:       T96 T97 T98 
30         1/1            assign qre = re;
           Tests:       T96 T97 T98 

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_dio_pad_attr_13_virtual_od_en_13

	Line No.	Total	Covered	Percent
TOTAL		5	3	60.00
CONT_ASSIGN	26	1	0	0.00
CONT_ASSIGN	27	1	0	0.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	30	1	1	100.00

25                        // between qs and ds
26         0/1     ==>    assign ds = d;
27         0/1     ==>    assign qs = d;
28         1/1            assign q = wd;
           Tests:       T1 T2 T3 
29         1/1            assign qe = we;
           Tests:       T96 T97 T98 
30         1/1            assign qre = re;
           Tests:       T96 T97 T98 

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_dio_pad_attr_13_pull_en_13

	Line No.	Total	Covered	Percent
TOTAL		5	5	100.00
CONT_ASSIGN	26	1	1	100.00
CONT_ASSIGN	27	1	1	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	30	1	1	100.00

25                        // between qs and ds
26         1/1            assign ds = d;
           Tests:       T20 T21 T22 
27         1/1            assign qs = d;
           Tests:       T20 T21 T22 
28         1/1            assign q = wd;
           Tests:       T1 T2 T3 
29         1/1            assign qe = we;
           Tests:       T96 T97 T98 
30         1/1            assign qre = re;
           Tests:       T96 T97 T98 

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_dio_pad_attr_13_pull_select_13

	Line No.	Total	Covered	Percent
TOTAL		5	5	100.00
CONT_ASSIGN	26	1	1	100.00
CONT_ASSIGN	27	1	1	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	30	1	1	100.00

25                        // between qs and ds
26         1/1            assign ds = d;
           Tests:       T20 T21 T22 
27         1/1            assign qs = d;
           Tests:       T20 T21 T22 
28         1/1            assign q = wd;
           Tests:       T1 T2 T3 
29         1/1            assign qe = we;
           Tests:       T96 T97 T98 
30         1/1            assign qre = re;
           Tests:       T96 T97 T98 

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_dio_pad_attr_13_keeper_en_13

	Line No.	Total	Covered	Percent
TOTAL		5	3	60.00
CONT_ASSIGN	26	1	0	0.00
CONT_ASSIGN	27	1	0	0.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	30	1	1	100.00

25                        // between qs and ds
26         0/1     ==>    assign ds = d;
27         0/1     ==>    assign qs = d;
28         1/1            assign q = wd;
           Tests:       T1 T2 T3 
29         1/1            assign qe = we;
           Tests:       T96 T97 T98 
30         1/1            assign qre = re;
           Tests:       T96 T97 T98 

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_dio_pad_attr_13_schmitt_en_13

	Line No.	Total	Covered	Percent
TOTAL		5	3	60.00
CONT_ASSIGN	26	1	0	0.00
CONT_ASSIGN	27	1	0	0.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	30	1	1	100.00

25                        // between qs and ds
26         0/1     ==>    assign ds = d;
27         0/1     ==>    assign qs = d;
28         1/1            assign q = wd;
           Tests:       T1 T2 T3 
29         1/1            assign qe = we;
           Tests:       T96 T97 T98 
30         1/1            assign qre = re;
           Tests:       T96 T97 T98 

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_dio_pad_attr_13_od_en_13

	Line No.	Total	Covered	Percent
TOTAL		5	3	60.00
CONT_ASSIGN	26	1	0	0.00
CONT_ASSIGN	27	1	0	0.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	30	1	1	100.00

25                        // between qs and ds
26         0/1     ==>    assign ds = d;
27         0/1     ==>    assign qs = d;
28         1/1            assign q = wd;
           Tests:       T1 T2 T3 
29         1/1            assign qe = we;
           Tests:       T96 T97 T98 
30         1/1            assign qre = re;
           Tests:       T96 T97 T98 

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_dio_pad_attr_13_input_disable_13

	Line No.	Total	Covered	Percent
TOTAL		5	5	100.00
CONT_ASSIGN	26	1	1	100.00
CONT_ASSIGN	27	1	1	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	30	1	1	100.00

25                        // between qs and ds
26         1/1            assign ds = d;
           Tests:       T20 T21 T22 
27         1/1            assign qs = d;
           Tests:       T20 T21 T22 
28         1/1            assign q = wd;
           Tests:       T1 T2 T3 
29         1/1            assign qe = we;
           Tests:       T96 T97 T98 
30         1/1            assign qre = re;
           Tests:       T96 T97 T98 

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_dio_pad_attr_13_slew_rate_13

	Line No.	Total	Covered	Percent
TOTAL		5	3	60.00
CONT_ASSIGN	26	1	0	0.00
CONT_ASSIGN	27	1	0	0.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	30	1	1	100.00

25                        // between qs and ds
26         0/1     ==>    assign ds = d;
27         0/1     ==>    assign qs = d;
28         1/1            assign q = wd;
           Tests:       T1 T2 T3 
29         1/1            assign qe = we;
           Tests:       T96 T97 T98 
30         1/1            assign qre = re;
           Tests:       T96 T97 T98 

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_dio_pad_attr_13_drive_strength_13

	Line No.	Total	Covered	Percent
TOTAL		5	3	60.00
CONT_ASSIGN	26	1	0	0.00
CONT_ASSIGN	27	1	0	0.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	30	1	1	100.00

25                        // between qs and ds
26         0/1     ==>    assign ds = d;
27         0/1     ==>    assign qs = d;
28         1/1            assign q = wd;
           Tests:       T1 T2 T3 
29         1/1            assign qe = we;
           Tests:       T96 T97 T98 
30         1/1            assign qre = re;
           Tests:       T96 T97 T98 

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_dio_pad_attr_14_invert_14

	Line No.	Total	Covered	Percent
TOTAL		5	5	100.00
CONT_ASSIGN	26	1	1	100.00
CONT_ASSIGN	27	1	1	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	30	1	1	100.00

25                        // between qs and ds
26         1/1            assign ds = d;
           Tests:       T20 T21 T22 
27         1/1            assign qs = d;
           Tests:       T20 T21 T22 
28         1/1            assign q = wd;
           Tests:       T1 T2 T3 
29         1/1            assign qe = we;
           Tests:       T9 T47 T48 
30         1/1            assign qre = re;
           Tests:       T9 T47 T48 

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_dio_pad_attr_14_virtual_od_en_14

	Line No.	Total	Covered	Percent
TOTAL		5	5	100.00
CONT_ASSIGN	26	1	1	100.00
CONT_ASSIGN	27	1	1	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	30	1	1	100.00

25                        // between qs and ds
26         1/1            assign ds = d;
           Tests:       T20 T21 T22 
27         1/1            assign qs = d;
           Tests:       T20 T21 T22 
28         1/1            assign q = wd;
           Tests:       T1 T2 T3 
29         1/1            assign qe = we;
           Tests:       T9 T47 T48 
30         1/1            assign qre = re;
           Tests:       T9 T47 T48 

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_dio_pad_attr_14_pull_en_14

	Line No.	Total	Covered	Percent
TOTAL		5	5	100.00
CONT_ASSIGN	26	1	1	100.00
CONT_ASSIGN	27	1	1	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	30	1	1	100.00

25                        // between qs and ds
26         1/1            assign ds = d;
           Tests:       T9 T47 T48 
27         1/1            assign qs = d;
           Tests:       T9 T47 T48 
28         1/1            assign q = wd;
           Tests:       T1 T2 T3 
29         1/1            assign qe = we;
           Tests:       T9 T47 T48 
30         1/1            assign qre = re;
           Tests:       T9 T47 T48 

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_dio_pad_attr_14_pull_select_14

	Line No.	Total	Covered	Percent
TOTAL		5	5	100.00
CONT_ASSIGN	26	1	1	100.00
CONT_ASSIGN	27	1	1	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	30	1	1	100.00

25                        // between qs and ds
26         1/1            assign ds = d;
           Tests:       T9 T47 T48 
27         1/1            assign qs = d;
           Tests:       T9 T47 T48 
28         1/1            assign q = wd;
           Tests:       T1 T2 T3 
29         1/1            assign qe = we;
           Tests:       T9 T47 T48 
30         1/1            assign qre = re;
           Tests:       T9 T47 T48 

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_dio_pad_attr_14_keeper_en_14

	Line No.	Total	Covered	Percent
TOTAL		5	3	60.00
CONT_ASSIGN	26	1	0	0.00
CONT_ASSIGN	27	1	0	0.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	30	1	1	100.00

25                        // between qs and ds
26         0/1     ==>    assign ds = d;
27         0/1     ==>    assign qs = d;
28         1/1            assign q = wd;
           Tests:       T1 T2 T3 
29         1/1            assign qe = we;
           Tests:       T9 T47 T48 
30         1/1            assign qre = re;
           Tests:       T9 T47 T48 

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_dio_pad_attr_14_schmitt_en_14

	Line No.	Total	Covered	Percent
TOTAL		5	3	60.00
CONT_ASSIGN	26	1	0	0.00
CONT_ASSIGN	27	1	0	0.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	30	1	1	100.00

25                        // between qs and ds
26         0/1     ==>    assign ds = d;
27         0/1     ==>    assign qs = d;
28         1/1            assign q = wd;
           Tests:       T1 T2 T3 
29         1/1            assign qe = we;
           Tests:       T9 T47 T48 
30         1/1            assign qre = re;
           Tests:       T9 T47 T48 

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_dio_pad_attr_14_od_en_14

	Line No.	Total	Covered	Percent
TOTAL		5	3	60.00
CONT_ASSIGN	26	1	0	0.00
CONT_ASSIGN	27	1	0	0.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	30	1	1	100.00

25                        // between qs and ds
26         0/1     ==>    assign ds = d;
27         0/1     ==>    assign qs = d;
28         1/1            assign q = wd;
           Tests:       T1 T2 T3 
29         1/1            assign qe = we;
           Tests:       T9 T47 T48 
30         1/1            assign qre = re;
           Tests:       T9 T47 T48 

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_dio_pad_attr_14_input_disable_14

	Line No.	Total	Covered	Percent
TOTAL		5	5	100.00
CONT_ASSIGN	26	1	1	100.00
CONT_ASSIGN	27	1	1	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	30	1	1	100.00

25                        // between qs and ds
26         1/1            assign ds = d;
           Tests:       T20 T21 T22 
27         1/1            assign qs = d;
           Tests:       T20 T21 T22 
28         1/1            assign q = wd;
           Tests:       T1 T2 T3 
29         1/1            assign qe = we;
           Tests:       T9 T47 T48 
30         1/1            assign qre = re;
           Tests:       T9 T47 T48 

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_dio_pad_attr_14_slew_rate_14

	Line No.	Total	Covered	Percent
TOTAL		5	3	60.00
CONT_ASSIGN	26	1	0	0.00
CONT_ASSIGN	27	1	0	0.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	30	1	1	100.00

25                        // between qs and ds
26         0/1     ==>    assign ds = d;
27         0/1     ==>    assign qs = d;
28         1/1            assign q = wd;
           Tests:       T1 T2 T3 
29         1/1            assign qe = we;
           Tests:       T9 T47 T48 
30         1/1            assign qre = re;
           Tests:       T9 T47 T48 

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_dio_pad_attr_14_drive_strength_14

	Line No.	Total	Covered	Percent
TOTAL		5	5	100.00
CONT_ASSIGN	26	1	1	100.00
CONT_ASSIGN	27	1	1	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	30	1	1	100.00

25                        // between qs and ds
26         1/1            assign ds = d;
           Tests:       T20 T21 T22 
27         1/1            assign qs = d;
           Tests:       T20 T21 T22 
28         1/1            assign q = wd;
           Tests:       T1 T2 T3 
29         1/1            assign qe = we;
           Tests:       T9 T47 T48 
30         1/1            assign qre = re;
           Tests:       T9 T47 T48 

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_dio_pad_attr_15_invert_15

	Line No.	Total	Covered	Percent
TOTAL		5	5	100.00
CONT_ASSIGN	26	1	1	100.00
CONT_ASSIGN	27	1	1	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	30	1	1	100.00

25                        // between qs and ds
26         1/1            assign ds = d;
           Tests:       T20 T21 T22 
27         1/1            assign qs = d;
           Tests:       T20 T21 T22 
28         1/1            assign q = wd;
           Tests:       T1 T2 T3 
29         1/1            assign qe = we;
           Tests:       T9 T47 T48 
30         1/1            assign qre = re;
           Tests:       T9 T47 T48 

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_dio_pad_attr_15_virtual_od_en_15

	Line No.	Total	Covered	Percent
TOTAL		5	5	100.00
CONT_ASSIGN	26	1	1	100.00
CONT_ASSIGN	27	1	1	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	30	1	1	100.00

25                        // between qs and ds
26         1/1            assign ds = d;
           Tests:       T20 T21 T22 
27         1/1            assign qs = d;
           Tests:       T20 T21 T22 
28         1/1            assign q = wd;
           Tests:       T1 T2 T3 
29         1/1            assign qe = we;
           Tests:       T9 T47 T48 
30         1/1            assign qre = re;
           Tests:       T9 T47 T48 

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_dio_pad_attr_15_pull_en_15

	Line No.	Total	Covered	Percent
TOTAL		5	5	100.00
CONT_ASSIGN	26	1	1	100.00
CONT_ASSIGN	27	1	1	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	30	1	1	100.00

25                        // between qs and ds
26         1/1            assign ds = d;
           Tests:       T9 T47 T48 
27         1/1            assign qs = d;
           Tests:       T9 T47 T48 
28         1/1            assign q = wd;
           Tests:       T1 T2 T3 
29         1/1            assign qe = we;
           Tests:       T9 T47 T48 
30         1/1            assign qre = re;
           Tests:       T9 T47 T48 

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_dio_pad_attr_15_pull_select_15

	Line No.	Total	Covered	Percent
TOTAL		5	5	100.00
CONT_ASSIGN	26	1	1	100.00
CONT_ASSIGN	27	1	1	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	30	1	1	100.00

25                        // between qs and ds
26         1/1            assign ds = d;
           Tests:       T9 T47 T48 
27         1/1            assign qs = d;
           Tests:       T9 T47 T48 
28         1/1            assign q = wd;
           Tests:       T1 T2 T3 
29         1/1            assign qe = we;
           Tests:       T9 T47 T48 
30         1/1            assign qre = re;
           Tests:       T9 T47 T48 

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_dio_pad_attr_15_keeper_en_15

	Line No.	Total	Covered	Percent
TOTAL		5	3	60.00
CONT_ASSIGN	26	1	0	0.00
CONT_ASSIGN	27	1	0	0.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	30	1	1	100.00

25                        // between qs and ds
26         0/1     ==>    assign ds = d;
27         0/1     ==>    assign qs = d;
28         1/1            assign q = wd;
           Tests:       T1 T2 T3 
29         1/1            assign qe = we;
           Tests:       T9 T47 T48 
30         1/1            assign qre = re;
           Tests:       T9 T47 T48 

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_dio_pad_attr_15_schmitt_en_15

	Line No.	Total	Covered	Percent
TOTAL		5	3	60.00
CONT_ASSIGN	26	1	0	0.00
CONT_ASSIGN	27	1	0	0.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	30	1	1	100.00

25                        // between qs and ds
26         0/1     ==>    assign ds = d;
27         0/1     ==>    assign qs = d;
28         1/1            assign q = wd;
           Tests:       T1 T2 T3 
29         1/1            assign qe = we;
           Tests:       T9 T47 T48 
30         1/1            assign qre = re;
           Tests:       T9 T47 T48 

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_dio_pad_attr_15_od_en_15

	Line No.	Total	Covered	Percent
TOTAL		5	3	60.00
CONT_ASSIGN	26	1	0	0.00
CONT_ASSIGN	27	1	0	0.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	30	1	1	100.00

25                        // between qs and ds
26         0/1     ==>    assign ds = d;
27         0/1     ==>    assign qs = d;
28         1/1            assign q = wd;
           Tests:       T1 T2 T3 
29         1/1            assign qe = we;
           Tests:       T9 T47 T48 
30         1/1            assign qre = re;
           Tests:       T9 T47 T48 

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_dio_pad_attr_15_input_disable_15

	Line No.	Total	Covered	Percent
TOTAL		5	5	100.00
CONT_ASSIGN	26	1	1	100.00
CONT_ASSIGN	27	1	1	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	30	1	1	100.00

25                        // between qs and ds
26         1/1            assign ds = d;
           Tests:       T20 T21 T49 
27         1/1            assign qs = d;
           Tests:       T20 T21 T49 
28         1/1            assign q = wd;
           Tests:       T1 T2 T3 
29         1/1            assign qe = we;
           Tests:       T9 T47 T48 
30         1/1            assign qre = re;
           Tests:       T9 T47 T48 

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_dio_pad_attr_15_slew_rate_15

	Line No.	Total	Covered	Percent
TOTAL		5	3	60.00
CONT_ASSIGN	26	1	0	0.00
CONT_ASSIGN	27	1	0	0.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	30	1	1	100.00

25                        // between qs and ds
26         0/1     ==>    assign ds = d;
27         0/1     ==>    assign qs = d;
28         1/1            assign q = wd;
           Tests:       T1 T2 T3 
29         1/1            assign qe = we;
           Tests:       T9 T47 T48 
30         1/1            assign qre = re;
           Tests:       T9 T47 T48 

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_dio_pad_attr_15_drive_strength_15

	Line No.	Total	Covered	Percent
TOTAL		5	5	100.00
CONT_ASSIGN	26	1	1	100.00
CONT_ASSIGN	27	1	1	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	30	1	1	100.00

25                        // between qs and ds
26         1/1            assign ds = d;
           Tests:       T20 T49 T50 
27         1/1            assign qs = d;
           Tests:       T20 T49 T50 
28         1/1            assign q = wd;
           Tests:       T1 T2 T3 
29         1/1            assign qe = we;
           Tests:       T9 T47 T48 
30         1/1            assign qre = re;
           Tests:       T9 T47 T48 

Line Coverage for Instance : tb.dut.top_earlgrey.u_sensor_ctrl_aon.u_reg.u_intr_test_io_status_change

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	26	0	0
CONT_ASSIGN	27	0	0
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	30	0	0

25                        // between qs and ds
26         unreachable    assign ds = d;
27         unreachable    assign qs = d;
28         1/1            assign q = wd;
           Tests:       T1 T2 T3 
29         1/1            assign qe = we;
           Tests:       T131 T196 T197 
30         unreachable    assign qre = re;

Line Coverage for Instance : tb.dut.top_earlgrey.u_sensor_ctrl_aon.u_reg.u_intr_test_init_status_change

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	26	0	0
CONT_ASSIGN	27	0	0
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	30	0	0

25                        // between qs and ds
26         unreachable    assign ds = d;
27         unreachable    assign qs = d;
28         1/1            assign q = wd;
           Tests:       T1 T2 T3 
29         1/1            assign qe = we;
           Tests:       T131 T196 T197 
30         unreachable    assign qre = re;

Line Coverage for Instance : tb.dut.top_earlgrey.u_sensor_ctrl_aon.u_reg.u_alert_test_recov_alert

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	26	0	0
CONT_ASSIGN	27	0	0
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	30	0	0

25                        // between qs and ds
26         unreachable    assign ds = d;
27         unreachable    assign qs = d;
28         1/1            assign q = wd;
           Tests:       T1 T2 T3 
29         1/1            assign qe = we;
           Tests:       T80 T81 T82 
30         unreachable    assign qre = re;

Line Coverage for Instance : tb.dut.top_earlgrey.u_sensor_ctrl_aon.u_reg.u_alert_test_fatal_alert

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	26	0	0
CONT_ASSIGN	27	0	0
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	30	0	0

25                        // between qs and ds
26         unreachable    assign ds = d;
27         unreachable    assign qs = d;
28         1/1            assign q = wd;
           Tests:       T1 T2 T3 
29         1/1            assign qe = we;
           Tests:       T80 T81 T82 
30         unreachable    assign qre = re;

Line Coverage for Instance : tb.dut.top_earlgrey.u_sensor_ctrl_aon.u_reg.u_manual_pad_attr_0_pull_en_0

	Line No.	Total	Covered	Percent
TOTAL		5	4	80.00
CONT_ASSIGN	26	1	1	100.00
CONT_ASSIGN	27	1	1	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	30	1	0	0.00

25                        // between qs and ds
26         1/1            assign ds = d;
           Tests:       T20 T21 T22 
27         1/1            assign qs = d;
           Tests:       T20 T21 T22 
28         1/1            assign q = wd;
           Tests:       T1 T2 T3 
29         1/1            assign qe = we;
           Tests:       T20 T21 T22 
30         0/1     ==>    assign qre = re;

Line Coverage for Instance : tb.dut.top_earlgrey.u_sensor_ctrl_aon.u_reg.u_manual_pad_attr_0_pull_select_0

	Line No.	Total	Covered	Percent
TOTAL		5	4	80.00
CONT_ASSIGN	26	1	1	100.00
CONT_ASSIGN	27	1	1	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	30	1	0	0.00

25                        // between qs and ds
26         1/1            assign ds = d;
           Tests:       T20 T21 T22 
27         1/1            assign qs = d;
           Tests:       T20 T21 T22 
28         1/1            assign q = wd;
           Tests:       T1 T2 T3 
29         1/1            assign qe = we;
           Tests:       T20 T21 T22 
30         0/1     ==>    assign qre = re;

Line Coverage for Instance : tb.dut.top_earlgrey.u_sensor_ctrl_aon.u_reg.u_manual_pad_attr_0_input_disable_0

	Line No.	Total	Covered	Percent
TOTAL		5	4	80.00
CONT_ASSIGN	26	1	1	100.00
CONT_ASSIGN	27	1	1	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	30	1	0	0.00

25                        // between qs and ds
26         1/1            assign ds = d;
           Tests:       T20 T21 T22 
27         1/1            assign qs = d;
           Tests:       T20 T21 T22 
28         1/1            assign q = wd;
           Tests:       T1 T2 T3 
29         1/1            assign qe = we;
           Tests:       T20 T21 T22 
30         0/1     ==>    assign qre = re;

Line Coverage for Instance : tb.dut.top_earlgrey.u_sensor_ctrl_aon.u_reg.u_manual_pad_attr_1_pull_en_1

	Line No.	Total	Covered	Percent
TOTAL		5	4	80.00
CONT_ASSIGN	26	1	1	100.00
CONT_ASSIGN	27	1	1	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	30	1	0	0.00

25                        // between qs and ds
26         1/1            assign ds = d;
           Tests:       T20 T21 T22 
27         1/1            assign qs = d;
           Tests:       T20 T21 T22 
28         1/1            assign q = wd;
           Tests:       T1 T2 T3 
29         1/1            assign qe = we;
           Tests:       T20 T21 T22 
30         0/1     ==>    assign qre = re;

Line Coverage for Instance : tb.dut.top_earlgrey.u_sensor_ctrl_aon.u_reg.u_manual_pad_attr_1_pull_select_1

	Line No.	Total	Covered	Percent
TOTAL		5	4	80.00
CONT_ASSIGN	26	1	1	100.00
CONT_ASSIGN	27	1	1	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	30	1	0	0.00

25                        // between qs and ds
26         1/1            assign ds = d;
           Tests:       T20 T21 T22 
27         1/1            assign qs = d;
           Tests:       T20 T21 T22 
28         1/1            assign q = wd;
           Tests:       T1 T2 T3 
29         1/1            assign qe = we;
           Tests:       T20 T21 T22 
30         0/1     ==>    assign qre = re;

Line Coverage for Instance : tb.dut.top_earlgrey.u_sensor_ctrl_aon.u_reg.u_manual_pad_attr_1_input_disable_1

	Line No.	Total	Covered	Percent
TOTAL		5	4	80.00
CONT_ASSIGN	26	1	1	100.00
CONT_ASSIGN	27	1	1	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	30	1	0	0.00

25                        // between qs and ds
26         1/1            assign ds = d;
           Tests:       T20 T21 T22 
27         1/1            assign qs = d;
           Tests:       T20 T21 T22 
28         1/1            assign q = wd;
           Tests:       T1 T2 T3 
29         1/1            assign qe = we;
           Tests:       T20 T21 T22 
30         0/1     ==>    assign qre = re;

Line Coverage for Instance : tb.dut.top_earlgrey.u_sensor_ctrl_aon.u_reg.u_manual_pad_attr_2_pull_en_2

	Line No.	Total	Covered	Percent
TOTAL		5	4	80.00
CONT_ASSIGN	26	1	1	100.00
CONT_ASSIGN	27	1	1	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	30	1	0	0.00

25                        // between qs and ds
26         1/1            assign ds = d;
           Tests:       T20 T21 T22 
27         1/1            assign qs = d;
           Tests:       T20 T21 T22 
28         1/1            assign q = wd;
           Tests:       T1 T2 T3 
29         1/1            assign qe = we;
           Tests:       T20 T21 T22 
30         0/1     ==>    assign qre = re;

Line Coverage for Instance : tb.dut.top_earlgrey.u_sensor_ctrl_aon.u_reg.u_manual_pad_attr_2_pull_select_2

	Line No.	Total	Covered	Percent
TOTAL		5	4	80.00
CONT_ASSIGN	26	1	1	100.00
CONT_ASSIGN	27	1	1	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	30	1	0	0.00

25                        // between qs and ds
26         1/1            assign ds = d;
           Tests:       T20 T21 T22 
27         1/1            assign qs = d;
           Tests:       T20 T21 T22 
28         1/1            assign q = wd;
           Tests:       T1 T2 T3 
29         1/1            assign qe = we;
           Tests:       T20 T21 T22 
30         0/1     ==>    assign qre = re;

Line Coverage for Instance : tb.dut.top_earlgrey.u_sensor_ctrl_aon.u_reg.u_manual_pad_attr_2_input_disable_2

	Line No.	Total	Covered	Percent
TOTAL		5	4	80.00
CONT_ASSIGN	26	1	1	100.00
CONT_ASSIGN	27	1	1	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	30	1	0	0.00

25                        // between qs and ds
26         1/1            assign ds = d;
           Tests:       T20 T21 T22 
27         1/1            assign qs = d;
           Tests:       T20 T21 T22 
28         1/1            assign q = wd;
           Tests:       T1 T2 T3 
29         1/1            assign qe = we;
           Tests:       T20 T21 T22 
30         0/1     ==>    assign qre = re;

Line Coverage for Instance : tb.dut.top_earlgrey.u_sensor_ctrl_aon.u_reg.u_manual_pad_attr_3_pull_en_3

	Line No.	Total	Covered	Percent
TOTAL		5	4	80.00
CONT_ASSIGN	26	1	1	100.00
CONT_ASSIGN	27	1	1	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	30	1	0	0.00

25                        // between qs and ds
26         1/1            assign ds = d;
           Tests:       T20 T21 T22 
27         1/1            assign qs = d;
           Tests:       T20 T21 T22 
28         1/1            assign q = wd;
           Tests:       T1 T2 T3 
29         1/1            assign qe = we;
           Tests:       T20 T21 T22 
30         0/1     ==>    assign qre = re;

Line Coverage for Instance : tb.dut.top_earlgrey.u_sensor_ctrl_aon.u_reg.u_manual_pad_attr_3_pull_select_3

	Line No.	Total	Covered	Percent
TOTAL		5	4	80.00
CONT_ASSIGN	26	1	1	100.00
CONT_ASSIGN	27	1	1	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	30	1	0	0.00

25                        // between qs and ds
26         1/1            assign ds = d;
           Tests:       T20 T21 T22 
27         1/1            assign qs = d;
           Tests:       T20 T21 T22 
28         1/1            assign q = wd;
           Tests:       T1 T2 T3 
29         1/1            assign qe = we;
           Tests:       T20 T21 T22 
30         0/1     ==>    assign qre = re;

Line Coverage for Instance : tb.dut.top_earlgrey.u_sensor_ctrl_aon.u_reg.u_manual_pad_attr_3_input_disable_3

	Line No.	Total	Covered	Percent
TOTAL		5	4	80.00
CONT_ASSIGN	26	1	1	100.00
CONT_ASSIGN	27	1	1	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	30	1	0	0.00

25                        // between qs and ds
26         1/1            assign ds = d;
           Tests:       T20 T21 T22 
27         1/1            assign qs = d;
           Tests:       T20 T21 T22 
28         1/1            assign q = wd;
           Tests:       T1 T2 T3 
29         1/1            assign qe = we;
           Tests:       T20 T21 T22 
30         0/1     ==>    assign qre = re;

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_cc0

	Line No.	Total	Covered	Percent
TOTAL		5	5	100.00
CONT_ASSIGN	26	1	1	100.00
CONT_ASSIGN	27	1	1	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	30	1	1	100.00

25                        // between qs and ds
26         1/1            assign ds = d;
           Tests:       T4 T5 T6 
27         1/1            assign qs = d;
           Tests:       T4 T5 T6 
28         1/1            assign q = wd;
           Tests:       T2 T4 T5 
29         1/1            assign qe = we;
           Tests:       T4 T5 T6 
30         1/1            assign qre = re;
           Tests:       T4 T5 T6 

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_plic.u_reg.u_alert_test

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	26	0	0
CONT_ASSIGN	27	0	0
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	30	0	0

25                        // between qs and ds
26         unreachable    assign ds = d;
27         unreachable    assign qs = d;
28         1/1            assign q = wd;
           Tests:       T4 T5 T6 
29         1/1            assign qe = we;
           Tests:       T80 T81 T82 
30         unreachable    assign qre = re;