Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_reg_if.u_err
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 26 | 26 | 100.00 |
| CONT_ASSIGN | 26 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 27 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 28 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 32 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 36 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 39 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 42 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 54 | 1 | 1 | 100.00 |
| ALWAYS | 57 | 17 | 17 | 100.00 |
| CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
25 logic op_full, op_partial, op_get;
26 1/1 assign op_full = (tl_i.a_opcode == PutFullData);
Tests: T1 T2 T3
27 1/1 assign op_partial = (tl_i.a_opcode == PutPartialData);
Tests: T1 T2 T3
28 1/1 assign op_get = (tl_i.a_opcode == Get);
Tests: T1 T2 T3
29
30 // An instruction type transaction cannot be write
31 logic instr_wr_err;
32 1/1 assign instr_wr_err = prim_mubi_pkg::mubi4_test_true_strict(tl_i.a_user.instr_type) &
Tests: T1 T2 T3
33 (op_full | op_partial);
34
35 logic instr_type_err;
36 1/1 assign instr_type_err = prim_mubi_pkg::mubi4_test_invalid(tl_i.a_user.instr_type);
Tests: T1 T2 T3
37
38 // Anything that doesn't fall into the permitted category, it raises an error
39 1/1 assign err_o = ~(opcode_allowed & a_config_allowed) | instr_wr_err | instr_type_err;
Tests: T1 T2 T3
40
41 // opcode check
42 1/1 assign opcode_allowed = (tl_i.a_opcode == PutFullData)
Tests: T1 T2 T3
43 | (tl_i.a_opcode == PutPartialData)
44 | (tl_i.a_opcode == Get);
45
46 // a channel configuration check
47 logic addr_sz_chk; // address and size alignment check
48 logic mask_chk; // inactive lane a_mask check
49 logic fulldata_chk; // PutFullData should have size match to mask
50
51 localparam bit [MW-1:0] MaskOne = 1;
52 logic [MW-1:0] mask;
53
54 1/1 assign mask = MaskOne << tl_i.a_address[SubAW-1:0];
Tests: T94 T95 T96
55
56 always_comb begin
57 1/1 addr_sz_chk = 1'b0;
Tests: T1 T2 T3
58 1/1 mask_chk = 1'b0;
Tests: T1 T2 T3
59 1/1 fulldata_chk = 1'b0; // Only valid when opcode is PutFullData
Tests: T1 T2 T3
60
61 1/1 if (tl_i.a_valid) begin
Tests: T1 T2 T3
62 1/1 unique case (tl_i.a_size)
Tests: T1 T2 T3
63 'h0: begin // 1 Byte
64 1/1 addr_sz_chk = 1'b1;
Tests: T95 T96 T99
65 1/1 mask_chk = ~|(tl_i.a_mask & ~mask);
Tests: T95 T96 T99
66 1/1 fulldata_chk = |(tl_i.a_mask & mask);
Tests: T95 T96 T99
67 end
68
69 'h1: begin // 2 Byte
70 1/1 addr_sz_chk = ~tl_i.a_address[0];
Tests: T95 T96 T99
71 // check inactive lanes if lower 2B, check a_mask[3:2], if uppwer 2B, a_mask[1:0]
72 1/1 mask_chk = (tl_i.a_address[1]) ? ~|(tl_i.a_mask & 4'b0011)
Tests: T95 T96 T99
73 : ~|(tl_i.a_mask & 4'b1100);
74 1/1 fulldata_chk = (tl_i.a_address[1]) ? &tl_i.a_mask[3:2] : &tl_i.a_mask[1:0] ;
Tests: T95 T96 T99
75 end
76
77 'h2: begin // 4 Byte
78 1/1 addr_sz_chk = ~|tl_i.a_address[SubAW-1:0];
Tests: T1 T2 T3
79 1/1 mask_chk = 1'b1;
Tests: T1 T2 T3
80 1/1 fulldata_chk = &tl_i.a_mask[3:0];
Tests: T1 T2 T3
81 end
82
83 default: begin // else
84 addr_sz_chk = 1'b0;
85 mask_chk = 1'b0;
86 fulldata_chk = 1'b0;
87 end
88 endcase
89 end else begin
90 1/1 addr_sz_chk = 1'b0;
Tests: T1 T2 T3
91 1/1 mask_chk = 1'b0;
Tests: T1 T2 T3
92 1/1 fulldata_chk = 1'b0;
Tests: T1 T2 T3
93 end
94 end
95
96 1/1 assign a_config_allowed = addr_sz_chk
Tests: T1 T2 T3
Cond Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_reg_if.u_err
| Total | Covered | Percent |
|---|
| Conditions | 35 | 35 | 100.00 |
| Logical | 35 | 35 | 100.00 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 26
EXPRESSION (tl_i.a_opcode == PutFullData)
---------------1--------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 27
EXPRESSION (tl_i.a_opcode == PutPartialData)
----------------1----------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T35,T97,T98 |
LINE 28
EXPRESSION (tl_i.a_opcode == Get)
-----------1----------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 39
EXPRESSION (( ~ (opcode_allowed & a_config_allowed) ) | instr_wr_err | instr_type_err)
--------------------1-------------------- ------2----- -------3------
| -1- | -2- | -3- | Status | Tests |
|---|
| 0 | 0 | 0 | Covered | T1,T2,T3 |
| 0 | 0 | 1 | Covered | T278,T548,T544 |
| 0 | 1 | 0 | Covered | T600,T637,T657 |
| 1 | 0 | 0 | Covered | T1,T2,T3 |
LINE 39
SUB-EXPRESSION (opcode_allowed & a_config_allowed)
-------1------ --------2-------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T544,T446,T658 |
| 1 | 0 | Covered | T1,T2,T3 |
| 1 | 1 | Covered | T1,T2,T3 |
LINE 42
EXPRESSION ((tl_i.a_opcode == PutFullData) | (tl_i.a_opcode == PutPartialData) | (tl_i.a_opcode == Get))
---------------1-------------- ----------------2---------------- -----------3----------
| -1- | -2- | -3- | Status | Tests |
|---|
| 0 | 0 | 0 | Covered | T278,T279,T443 |
| 0 | 0 | 1 | Covered | T1,T2,T3 |
| 0 | 1 | 0 | Covered | T35,T97,T98 |
| 1 | 0 | 0 | Covered | T1,T2,T3 |
LINE 42
SUB-EXPRESSION (tl_i.a_opcode == PutFullData)
---------------1--------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 42
SUB-EXPRESSION (tl_i.a_opcode == PutPartialData)
----------------1----------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T35,T97,T98 |
LINE 42
SUB-EXPRESSION (tl_i.a_opcode == Get)
-----------1----------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 72
EXPRESSION (tl_i.a_address[1] ? ((~|(tl_i.a_mask & 4'b0011))) : ((~|(tl_i.a_mask & 4'b1100))))
--------1--------
| -1- | Status | Tests |
|---|
| 0 | Covered | T96,T99,T248 |
| 1 | Covered | T95,T96,T99 |
LINE 74
EXPRESSION (tl_i.a_address[1] ? ((&tl_i.a_mask[3:2])) : ((&tl_i.a_mask[1:0])))
--------1--------
| -1- | Status | Tests |
|---|
| 0 | Covered | T96,T99,T248 |
| 1 | Covered | T95,T96,T99 |
LINE 96
EXPRESSION (addr_sz_chk & mask_chk & (op_get | op_partial | fulldata_chk))
-----1----- ----2--- ------------------3-----------------
| -1- | -2- | -3- | Status | Tests |
|---|
| 0 | 1 | 1 | Covered | T278,T279,T443 |
| 1 | 0 | 1 | Covered | T278,T279,T443 |
| 1 | 1 | 0 | Covered | T443,T548,T446 |
| 1 | 1 | 1 | Covered | T1,T2,T3 |
LINE 96
SUB-EXPRESSION (op_get | op_partial | fulldata_chk)
---1-- -----2---- ------3-----
| -1- | -2- | -3- | Status | Tests |
|---|
| 0 | 0 | 0 | Covered | T1,T2,T3 |
| 0 | 0 | 1 | Covered | T1,T2,T3 |
| 0 | 1 | 0 | Covered | T35,T97,T98 |
| 1 | 0 | 0 | Covered | T1,T2,T3 |
Branch Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_reg_if.u_err
| Line No. | Total | Covered | Percent |
| Branches |
|
8 |
8 |
100.00 |
| IF |
61 |
8 |
8 |
100.00 |
61 if (tl_i.a_valid) begin
-1-
62 unique case (tl_i.a_size)
-2-
63 'h0: begin // 1 Byte
64 addr_sz_chk = 1'b1;
==>
65 mask_chk = ~|(tl_i.a_mask & ~mask);
66 fulldata_chk = |(tl_i.a_mask & mask);
67 end
68
69 'h1: begin // 2 Byte
70 addr_sz_chk = ~tl_i.a_address[0];
71 // check inactive lanes if lower 2B, check a_mask[3:2], if uppwer 2B, a_mask[1:0]
72 mask_chk = (tl_i.a_address[1]) ? ~|(tl_i.a_mask & 4'b0011)
-3-
==>
==>
73 : ~|(tl_i.a_mask & 4'b1100);
74 fulldata_chk = (tl_i.a_address[1]) ? &tl_i.a_mask[3:2] : &tl_i.a_mask[1:0] ;
-4-
==>
==>
75 end
76
77 'h2: begin // 4 Byte
78 addr_sz_chk = ~|tl_i.a_address[SubAW-1:0];
==>
79 mask_chk = 1'b1;
80 fulldata_chk = &tl_i.a_mask[3:0];
81 end
82
83 default: begin // else
84 addr_sz_chk = 1'b0;
==>
85 mask_chk = 1'b0;
86 fulldata_chk = 1'b0;
87 end
88 endcase
89 end else begin
90 addr_sz_chk = 1'b0;
==>
Branches:
| -1- | -2- | -3- | -4- | Status | Tests |
| 1 |
'h0 |
- |
- |
Covered |
T95,T96,T99 |
| 1 |
'h1 |
1 |
- |
Covered |
T95,T96,T99 |
| 1 |
'h1 |
0 |
- |
Covered |
T96,T99,T248 |
| 1 |
'h1 |
- |
1 |
Covered |
T95,T96,T99 |
| 1 |
'h1 |
- |
0 |
Covered |
T96,T99,T248 |
| 1 |
'h00000002 |
- |
- |
Covered |
T1,T2,T3 |
| 1 |
default |
- |
- |
Covered |
T278,T279,T443 |
| 0 |
- |
- |
- |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_reg_if.u_err
Assertion Details
dataWidthOnly32_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
2918 |
2918 |
0 |
0 |
| T1 |
1 |
1 |
0 |
0 |
| T2 |
1 |
1 |
0 |
0 |
| T3 |
1 |
1 |
0 |
0 |
| T4 |
1 |
1 |
0 |
0 |
| T5 |
1 |
1 |
0 |
0 |
| T6 |
1 |
1 |
0 |
0 |
| T30 |
1 |
1 |
0 |
0 |
| T68 |
1 |
1 |
0 |
0 |
| T104 |
1 |
1 |
0 |
0 |
| T105 |
1 |
1 |
0 |
0 |