Line Coverage for Instance : tb.dut.u_padring.gen_dio_pads[22].u_dio_pad.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 8 | 8 | 100.00 |
| CONT_ASSIGN | 39 | 0 | 0 | |
| CONT_ASSIGN | 51 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 78 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 80 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 84 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 85 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 92 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 93 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 95 | 1 | 1 | 100.00 |
38 logic unused_sigs;
39 unreachable assign unused_sigs = ^{attr_i.slew_rate,
40 attr_i.drive_strength[3:1],
41 attr_i.od_en,
42 attr_i.schmitt_en,
43 attr_i.keep_en,
44 scanmode_i,
45 pok_i};
46 //VCS coverage on
47 // pragma coverage on
48
49 // Input enable (active-high)
50 logic ie;
51 1/1 assign ie = ie_i & ~attr_i.input_disable;
Tests: T20 T21 T22
52
53 if (PadType == InputStd) begin : gen_input_only
54 //VCS coverage off
55 // pragma coverage off
56 logic unused_in_sigs;
57 assign unused_in_sigs = ^{out_i,
58 oe_i,
59 attr_i.virt_od_en,
60 attr_i.drive_strength};
61 //VCS coverage on
62 // pragma coverage on
63
64 assign in_raw_o = ie ? inout_io : 1'bz;
65 // input inversion
66 assign in_o = attr_i.invert ^ in_raw_o;
67
68 // pulls are not supported by verilator
69 `ifndef VERILATOR
70 // pullup / pulldown termination
71 assign (weak0, weak1) inout_io = attr_i.pull_en ? attr_i.pull_select : 1'bz;
72 `endif
73 end else if (PadType == BidirTol ||
74 PadType == DualBidirTol ||
75 PadType == BidirOd ||
76 PadType == BidirStd) begin : gen_bidir
77
78 1/1 assign in_raw_o = ie ? inout_io : 1'bz;
Tests: T6 T23 T12
79 // input inversion
80 1/1 assign in_o = attr_i.invert ^ in_raw_o;
Tests: T6 T23 T12
81
82 // virtual open drain emulation
83 logic oe, out;
84 1/1 assign out = out_i ^ attr_i.invert;
Tests: T12 T15 T13
85 1/1 assign oe = oe_i & ((attr_i.virt_od_en & ~out) | ~attr_i.virt_od_en);
Tests: T6 T23 T12
86
87 // drive strength attributes are not supported by verilator
88 `ifdef VERILATOR
89 assign inout_io = (oe) ? out : 1'bz;
90 `else
91 // different driver types
92 1/1 assign (strong0, strong1) inout_io = (oe && attr_i.drive_strength[0]) ? out : 1'bz;
Tests: T6 T23 T12
93 1/1 assign (pull0, pull1) inout_io = (oe && !attr_i.drive_strength[0]) ? out : 1'bz;
Tests: T6 T23 T12
94 // pullup / pulldown termination
95 1/1 assign (weak0, weak1) inout_io = attr_i.pull_en ? attr_i.pull_select : 1'bz;
Tests: T20 T21 T22
Cond Coverage for Instance : tb.dut.u_padring.gen_dio_pads[22].u_dio_pad.gen_generic.u_impl_generic
| Total | Covered | Percent |
|---|
| Conditions | 33 | 33 | 100.00 |
| Logical | 33 | 33 | 100.00 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 51
EXPRESSION (ie_i & ((~attr_i.input_disable)))
--1- ------------2------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Unreachable | |
| 1 | 0 | Covered | T20,T21,T22 |
| 1 | 1 | Covered | T1,T2,T3 |
LINE 78
EXPRESSION (ie ? inout_io : 1'bz)
-1
| -1- | Status | Tests |
|---|
| 0 | Covered | T20,T21,T22 |
| 1 | Covered | T1,T2,T3 |
LINE 80
EXPRESSION (attr_i.invert ^ in_raw_o)
------1------ ----2---
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T1,T2,T3 |
| 0 | 1 | Covered | T6,T23,T12 |
| 1 | 0 | Covered | T20,T21,T22 |
| 1 | 1 | Covered | T20,T21,T22 |
LINE 84
EXPRESSION (out_i ^ attr_i.invert)
--1-- ------2------
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T1,T2,T3 |
| 0 | 1 | Covered | T20,T21,T22 |
| 1 | 0 | Covered | T12,T15,T13 |
| 1 | 1 | Covered | T20,T21,T22 |
LINE 85
EXPRESSION (oe_i & ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en))))
--1- ---------------------------------2---------------------------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T6,T23,T24 |
| 1 | 0 | Covered | T15,T45,T46 |
| 1 | 1 | Covered | T1,T2,T3 |
LINE 85
SUB-EXPRESSION ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en)))
--------------------1------------------- -----------2----------
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T15,T45,T46 |
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T15,T45,T46 |
LINE 85
SUB-EXPRESSION (attr_i.virt_od_en & ((~gen_bidir.out)))
--------1-------- ---------2--------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T15,T45,T46 |
| 1 | 1 | Covered | T15,T45,T46 |
LINE 92
EXPRESSION ((gen_bidir.oe && attr_i.drive_strength[0]) ? gen_bidir.out : 1'bz)
---------------------1--------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T20,T22,T44 |
LINE 92
SUB-EXPRESSION (gen_bidir.oe && attr_i.drive_strength[0])
------1----- ------------2-----------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T20,T21,T22 |
| 1 | 0 | Covered | T1,T2,T3 |
| 1 | 1 | Covered | T20,T22,T44 |
LINE 93
EXPRESSION ((gen_bidir.oe && ((!attr_i.drive_strength[0]))) ? gen_bidir.out : 1'bz)
-----------------------1-----------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T6,T23,T15 |
| 1 | Covered | T1,T2,T3 |
LINE 93
SUB-EXPRESSION (gen_bidir.oe && ((!attr_i.drive_strength[0])))
------1----- --------------2--------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T6,T23,T15 |
| 1 | 0 | Covered | T20,T22,T44 |
| 1 | 1 | Covered | T1,T2,T3 |
LINE 95
EXPRESSION (attr_i.pull_en ? attr_i.pull_select : 1'bz)
-------1------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T20,T21,T22 |
Branch Coverage for Instance : tb.dut.u_padring.gen_dio_pads[22].u_dio_pad.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
| Branches |
|
8 |
8 |
100.00 |
| TERNARY |
78 |
2 |
2 |
100.00 |
| TERNARY |
92 |
2 |
2 |
100.00 |
| TERNARY |
93 |
2 |
2 |
100.00 |
| TERNARY |
95 |
2 |
2 |
100.00 |
78 assign in_raw_o = ie ? inout_io : 1'bz;
-1-
==>
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T3 |
| 0 |
Covered |
T20,T21,T22 |
92 assign (strong0, strong1) inout_io = (oe && attr_i.drive_strength[0]) ? out : 1'bz;
-1-
==>
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T20,T22,T44 |
| 0 |
Covered |
T1,T2,T3 |
93 assign (pull0, pull1) inout_io = (oe && !attr_i.drive_strength[0]) ? out : 1'bz;
-1-
==>
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T3 |
| 0 |
Covered |
T6,T23,T15 |
95 assign (weak0, weak1) inout_io = attr_i.pull_en ? attr_i.pull_select : 1'bz;
-1-
==>
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T20,T21,T22 |
| 0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_padring.gen_dio_pads[22].u_dio_pad.gen_generic.u_impl_generic
Assertion Details
| Name | Attempts | Real Successes | Failures | Incomplete |
|
AnalogNoScan_A |
1010 |
1010 |
0 |
0 |
AnalogNoScan_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
1010 |
1010 |
0 |
0 |
| T1 |
1 |
1 |
0 |
0 |
| T2 |
1 |
1 |
0 |
0 |
| T3 |
1 |
1 |
0 |
0 |
| T4 |
1 |
1 |
0 |
0 |
| T5 |
1 |
1 |
0 |
0 |
| T6 |
1 |
1 |
0 |
0 |
| T30 |
1 |
1 |
0 |
0 |
| T68 |
1 |
1 |
0 |
0 |
| T104 |
1 |
1 |
0 |
0 |
| T105 |
1 |
1 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_padring.gen_mio_pads[0].u_mio_pad.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 8 | 8 | 100.00 |
| CONT_ASSIGN | 39 | 0 | 0 | |
| CONT_ASSIGN | 51 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 78 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 80 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 84 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 85 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 92 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 93 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 95 | 1 | 1 | 100.00 |
38 logic unused_sigs;
39 unreachable assign unused_sigs = ^{attr_i.slew_rate,
40 attr_i.drive_strength[3:1],
41 attr_i.od_en,
42 attr_i.schmitt_en,
43 attr_i.keep_en,
44 scanmode_i,
45 pok_i};
46 //VCS coverage on
47 // pragma coverage on
48
49 // Input enable (active-high)
50 logic ie;
51 1/1 assign ie = ie_i & ~attr_i.input_disable;
Tests: T20 T21 T22
52
53 if (PadType == InputStd) begin : gen_input_only
54 //VCS coverage off
55 // pragma coverage off
56 logic unused_in_sigs;
57 assign unused_in_sigs = ^{out_i,
58 oe_i,
59 attr_i.virt_od_en,
60 attr_i.drive_strength};
61 //VCS coverage on
62 // pragma coverage on
63
64 assign in_raw_o = ie ? inout_io : 1'bz;
65 // input inversion
66 assign in_o = attr_i.invert ^ in_raw_o;
67
68 // pulls are not supported by verilator
69 `ifndef VERILATOR
70 // pullup / pulldown termination
71 assign (weak0, weak1) inout_io = attr_i.pull_en ? attr_i.pull_select : 1'bz;
72 `endif
73 end else if (PadType == BidirTol ||
74 PadType == DualBidirTol ||
75 PadType == BidirOd ||
76 PadType == BidirStd) begin : gen_bidir
77
78 1/1 assign in_raw_o = ie ? inout_io : 1'bz;
Tests: T6 T25 T26
79 // input inversion
80 1/1 assign in_o = attr_i.invert ^ in_raw_o;
Tests: T6 T25 T26
81
82 // virtual open drain emulation
83 logic oe, out;
84 1/1 assign out = out_i ^ attr_i.invert;
Tests: T6 T26 T27
85 1/1 assign oe = oe_i & ((attr_i.virt_od_en & ~out) | ~attr_i.virt_od_en);
Tests: T6 T26 T27
86
87 // drive strength attributes are not supported by verilator
88 `ifdef VERILATOR
89 assign inout_io = (oe) ? out : 1'bz;
90 `else
91 // different driver types
92 1/1 assign (strong0, strong1) inout_io = (oe && attr_i.drive_strength[0]) ? out : 1'bz;
Tests: T6 T25 T26
93 1/1 assign (pull0, pull1) inout_io = (oe && !attr_i.drive_strength[0]) ? out : 1'bz;
Tests: T6 T25 T26
94 // pullup / pulldown termination
95 1/1 assign (weak0, weak1) inout_io = attr_i.pull_en ? attr_i.pull_select : 1'bz;
Tests: T25 T47 T48
Cond Coverage for Instance : tb.dut.u_padring.gen_mio_pads[0].u_mio_pad.gen_generic.u_impl_generic
| Total | Covered | Percent |
|---|
| Conditions | 33 | 33 | 100.00 |
| Logical | 33 | 33 | 100.00 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 51
EXPRESSION (ie_i & ((~attr_i.input_disable)))
--1- ------------2------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Unreachable | |
| 1 | 0 | Covered | T20,T21,T22 |
| 1 | 1 | Covered | T1,T2,T3 |
LINE 78
EXPRESSION (ie ? inout_io : 1'bz)
-1
| -1- | Status | Tests |
|---|
| 0 | Covered | T20,T21,T22 |
| 1 | Covered | T1,T2,T3 |
LINE 80
EXPRESSION (attr_i.invert ^ in_raw_o)
------1------ ----2---
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T26,T27,T38 |
| 0 | 1 | Covered | T6,T25,T26 |
| 1 | 0 | Covered | T20,T21,T22 |
| 1 | 1 | Covered | T20,T21,T22 |
LINE 84
EXPRESSION (out_i ^ attr_i.invert)
--1-- ------2------
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T1,T2,T3 |
| 0 | 1 | Covered | T20,T21,T22 |
| 1 | 0 | Covered | T6,T26,T27 |
| 1 | 1 | Covered | T20,T21,T22 |
LINE 85
EXPRESSION (oe_i & ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en))))
--1- ---------------------------------2---------------------------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T20,T21,T22 |
| 1 | 1 | Covered | T6,T26,T27 |
LINE 85
SUB-EXPRESSION ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en)))
--------------------1------------------- -----------2----------
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T20,T21,T22 |
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T20,T21,T22 |
LINE 85
SUB-EXPRESSION (attr_i.virt_od_en & ((~gen_bidir.out)))
--------1-------- ---------2--------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T20,T21,T22 |
| 1 | 1 | Covered | T20,T21,T22 |
LINE 92
EXPRESSION ((gen_bidir.oe && attr_i.drive_strength[0]) ? gen_bidir.out : 1'bz)
---------------------1--------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T20,T21,T22 |
LINE 92
SUB-EXPRESSION (gen_bidir.oe && attr_i.drive_strength[0])
------1----- ------------2-----------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T25,T47,T48 |
| 1 | 0 | Covered | T6,T26,T27 |
| 1 | 1 | Covered | T20,T21,T22 |
LINE 93
EXPRESSION ((gen_bidir.oe && ((!attr_i.drive_strength[0]))) ? gen_bidir.out : 1'bz)
-----------------------1-----------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T6,T26,T27 |
LINE 93
SUB-EXPRESSION (gen_bidir.oe && ((!attr_i.drive_strength[0])))
------1----- --------------2--------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T20,T21,T22 |
| 1 | 1 | Covered | T6,T26,T27 |
LINE 95
EXPRESSION (attr_i.pull_en ? attr_i.pull_select : 1'bz)
-------1------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T25,T47,T48 |
Branch Coverage for Instance : tb.dut.u_padring.gen_mio_pads[0].u_mio_pad.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
| Branches |
|
8 |
8 |
100.00 |
| TERNARY |
78 |
2 |
2 |
100.00 |
| TERNARY |
92 |
2 |
2 |
100.00 |
| TERNARY |
93 |
2 |
2 |
100.00 |
| TERNARY |
95 |
2 |
2 |
100.00 |
78 assign in_raw_o = ie ? inout_io : 1'bz;
-1-
==>
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T3 |
| 0 |
Covered |
T20,T21,T22 |
92 assign (strong0, strong1) inout_io = (oe && attr_i.drive_strength[0]) ? out : 1'bz;
-1-
==>
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T20,T21,T22 |
| 0 |
Covered |
T1,T2,T3 |
93 assign (pull0, pull1) inout_io = (oe && !attr_i.drive_strength[0]) ? out : 1'bz;
-1-
==>
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T6,T26,T27 |
| 0 |
Covered |
T1,T2,T3 |
95 assign (weak0, weak1) inout_io = attr_i.pull_en ? attr_i.pull_select : 1'bz;
-1-
==>
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T25,T47,T48 |
| 0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_padring.gen_mio_pads[0].u_mio_pad.gen_generic.u_impl_generic
Assertion Details
| Name | Attempts | Real Successes | Failures | Incomplete |
|
AnalogNoScan_A |
1010 |
1010 |
0 |
0 |
AnalogNoScan_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
1010 |
1010 |
0 |
0 |
| T1 |
1 |
1 |
0 |
0 |
| T2 |
1 |
1 |
0 |
0 |
| T3 |
1 |
1 |
0 |
0 |
| T4 |
1 |
1 |
0 |
0 |
| T5 |
1 |
1 |
0 |
0 |
| T6 |
1 |
1 |
0 |
0 |
| T30 |
1 |
1 |
0 |
0 |
| T68 |
1 |
1 |
0 |
0 |
| T104 |
1 |
1 |
0 |
0 |
| T105 |
1 |
1 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_padring.gen_mio_pads[1].u_mio_pad.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 8 | 8 | 100.00 |
| CONT_ASSIGN | 39 | 0 | 0 | |
| CONT_ASSIGN | 51 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 78 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 80 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 84 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 85 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 92 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 93 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 95 | 1 | 1 | 100.00 |
38 logic unused_sigs;
39 unreachable assign unused_sigs = ^{attr_i.slew_rate,
40 attr_i.drive_strength[3:1],
41 attr_i.od_en,
42 attr_i.schmitt_en,
43 attr_i.keep_en,
44 scanmode_i,
45 pok_i};
46 //VCS coverage on
47 // pragma coverage on
48
49 // Input enable (active-high)
50 logic ie;
51 1/1 assign ie = ie_i & ~attr_i.input_disable;
Tests: T20 T21 T22
52
53 if (PadType == InputStd) begin : gen_input_only
54 //VCS coverage off
55 // pragma coverage off
56 logic unused_in_sigs;
57 assign unused_in_sigs = ^{out_i,
58 oe_i,
59 attr_i.virt_od_en,
60 attr_i.drive_strength};
61 //VCS coverage on
62 // pragma coverage on
63
64 assign in_raw_o = ie ? inout_io : 1'bz;
65 // input inversion
66 assign in_o = attr_i.invert ^ in_raw_o;
67
68 // pulls are not supported by verilator
69 `ifndef VERILATOR
70 // pullup / pulldown termination
71 assign (weak0, weak1) inout_io = attr_i.pull_en ? attr_i.pull_select : 1'bz;
72 `endif
73 end else if (PadType == BidirTol ||
74 PadType == DualBidirTol ||
75 PadType == BidirOd ||
76 PadType == BidirStd) begin : gen_bidir
77
78 1/1 assign in_raw_o = ie ? inout_io : 1'bz;
Tests: T6 T26 T27
79 // input inversion
80 1/1 assign in_o = attr_i.invert ^ in_raw_o;
Tests: T6 T26 T27
81
82 // virtual open drain emulation
83 logic oe, out;
84 1/1 assign out = out_i ^ attr_i.invert;
Tests: T6 T26 T27
85 1/1 assign oe = oe_i & ((attr_i.virt_od_en & ~out) | ~attr_i.virt_od_en);
Tests: T6 T26 T27
86
87 // drive strength attributes are not supported by verilator
88 `ifdef VERILATOR
89 assign inout_io = (oe) ? out : 1'bz;
90 `else
91 // different driver types
92 1/1 assign (strong0, strong1) inout_io = (oe && attr_i.drive_strength[0]) ? out : 1'bz;
Tests: T6 T26 T27
93 1/1 assign (pull0, pull1) inout_io = (oe && !attr_i.drive_strength[0]) ? out : 1'bz;
Tests: T6 T26 T27
94 // pullup / pulldown termination
95 1/1 assign (weak0, weak1) inout_io = attr_i.pull_en ? attr_i.pull_select : 1'bz;
Tests: T20 T21 T22
Cond Coverage for Instance : tb.dut.u_padring.gen_mio_pads[1].u_mio_pad.gen_generic.u_impl_generic
| Total | Covered | Percent |
|---|
| Conditions | 33 | 33 | 100.00 |
| Logical | 33 | 33 | 100.00 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 51
EXPRESSION (ie_i & ((~attr_i.input_disable)))
--1- ------------2------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Unreachable | |
| 1 | 0 | Covered | T20,T21,T22 |
| 1 | 1 | Covered | T1,T2,T3 |
LINE 78
EXPRESSION (ie ? inout_io : 1'bz)
-1
| -1- | Status | Tests |
|---|
| 0 | Covered | T20,T21,T22 |
| 1 | Covered | T1,T2,T3 |
LINE 80
EXPRESSION (attr_i.invert ^ in_raw_o)
------1------ ----2---
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T26,T27,T38 |
| 0 | 1 | Covered | T6,T26,T27 |
| 1 | 0 | Covered | T20,T21,T22 |
| 1 | 1 | Covered | T21,T22,T44 |
LINE 84
EXPRESSION (out_i ^ attr_i.invert)
--1-- ------2------
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T1,T2,T3 |
| 0 | 1 | Covered | T20,T21,T22 |
| 1 | 0 | Covered | T6,T26,T27 |
| 1 | 1 | Covered | T20,T21,T22 |
LINE 85
EXPRESSION (oe_i & ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en))))
--1- ---------------------------------2---------------------------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T20,T21,T22 |
| 1 | 1 | Covered | T6,T26,T27 |
LINE 85
SUB-EXPRESSION ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en)))
--------------------1------------------- -----------2----------
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T20,T21,T22 |
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T20,T21,T22 |
LINE 85
SUB-EXPRESSION (attr_i.virt_od_en & ((~gen_bidir.out)))
--------1-------- ---------2--------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T20,T21,T22 |
| 1 | 1 | Covered | T20,T21,T22 |
LINE 92
EXPRESSION ((gen_bidir.oe && attr_i.drive_strength[0]) ? gen_bidir.out : 1'bz)
---------------------1--------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T20,T21,T22 |
LINE 92
SUB-EXPRESSION (gen_bidir.oe && attr_i.drive_strength[0])
------1----- ------------2-----------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T20,T21,T22 |
| 1 | 0 | Covered | T6,T26,T27 |
| 1 | 1 | Covered | T20,T21,T22 |
LINE 93
EXPRESSION ((gen_bidir.oe && ((!attr_i.drive_strength[0]))) ? gen_bidir.out : 1'bz)
-----------------------1-----------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T6,T26,T27 |
LINE 93
SUB-EXPRESSION (gen_bidir.oe && ((!attr_i.drive_strength[0])))
------1----- --------------2--------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T20,T21,T22 |
| 1 | 1 | Covered | T6,T26,T27 |
LINE 95
EXPRESSION (attr_i.pull_en ? attr_i.pull_select : 1'bz)
-------1------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T20,T21,T22 |
Branch Coverage for Instance : tb.dut.u_padring.gen_mio_pads[1].u_mio_pad.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
| Branches |
|
8 |
8 |
100.00 |
| TERNARY |
78 |
2 |
2 |
100.00 |
| TERNARY |
92 |
2 |
2 |
100.00 |
| TERNARY |
93 |
2 |
2 |
100.00 |
| TERNARY |
95 |
2 |
2 |
100.00 |
78 assign in_raw_o = ie ? inout_io : 1'bz;
-1-
==>
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T3 |
| 0 |
Covered |
T20,T21,T22 |
92 assign (strong0, strong1) inout_io = (oe && attr_i.drive_strength[0]) ? out : 1'bz;
-1-
==>
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T20,T21,T22 |
| 0 |
Covered |
T1,T2,T3 |
93 assign (pull0, pull1) inout_io = (oe && !attr_i.drive_strength[0]) ? out : 1'bz;
-1-
==>
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T6,T26,T27 |
| 0 |
Covered |
T1,T2,T3 |
95 assign (weak0, weak1) inout_io = attr_i.pull_en ? attr_i.pull_select : 1'bz;
-1-
==>
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T20,T21,T22 |
| 0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_padring.gen_mio_pads[1].u_mio_pad.gen_generic.u_impl_generic
Assertion Details
| Name | Attempts | Real Successes | Failures | Incomplete |
|
AnalogNoScan_A |
1010 |
1010 |
0 |
0 |
AnalogNoScan_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
1010 |
1010 |
0 |
0 |
| T1 |
1 |
1 |
0 |
0 |
| T2 |
1 |
1 |
0 |
0 |
| T3 |
1 |
1 |
0 |
0 |
| T4 |
1 |
1 |
0 |
0 |
| T5 |
1 |
1 |
0 |
0 |
| T6 |
1 |
1 |
0 |
0 |
| T30 |
1 |
1 |
0 |
0 |
| T68 |
1 |
1 |
0 |
0 |
| T104 |
1 |
1 |
0 |
0 |
| T105 |
1 |
1 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_padring.gen_mio_pads[2].u_mio_pad.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 8 | 8 | 100.00 |
| CONT_ASSIGN | 39 | 0 | 0 | |
| CONT_ASSIGN | 51 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 78 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 80 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 84 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 85 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 92 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 93 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 95 | 1 | 1 | 100.00 |
38 logic unused_sigs;
39 unreachable assign unused_sigs = ^{attr_i.slew_rate,
40 attr_i.drive_strength[3:1],
41 attr_i.od_en,
42 attr_i.schmitt_en,
43 attr_i.keep_en,
44 scanmode_i,
45 pok_i};
46 //VCS coverage on
47 // pragma coverage on
48
49 // Input enable (active-high)
50 logic ie;
51 1/1 assign ie = ie_i & ~attr_i.input_disable;
Tests: T20 T21 T22
52
53 if (PadType == InputStd) begin : gen_input_only
54 //VCS coverage off
55 // pragma coverage off
56 logic unused_in_sigs;
57 assign unused_in_sigs = ^{out_i,
58 oe_i,
59 attr_i.virt_od_en,
60 attr_i.drive_strength};
61 //VCS coverage on
62 // pragma coverage on
63
64 assign in_raw_o = ie ? inout_io : 1'bz;
65 // input inversion
66 assign in_o = attr_i.invert ^ in_raw_o;
67
68 // pulls are not supported by verilator
69 `ifndef VERILATOR
70 // pullup / pulldown termination
71 assign (weak0, weak1) inout_io = attr_i.pull_en ? attr_i.pull_select : 1'bz;
72 `endif
73 end else if (PadType == BidirTol ||
74 PadType == DualBidirTol ||
75 PadType == BidirOd ||
76 PadType == BidirStd) begin : gen_bidir
77
78 1/1 assign in_raw_o = ie ? inout_io : 1'bz;
Tests: T6 T26 T27
79 // input inversion
80 1/1 assign in_o = attr_i.invert ^ in_raw_o;
Tests: T6 T26 T27
81
82 // virtual open drain emulation
83 logic oe, out;
84 1/1 assign out = out_i ^ attr_i.invert;
Tests: T6 T26 T27
85 1/1 assign oe = oe_i & ((attr_i.virt_od_en & ~out) | ~attr_i.virt_od_en);
Tests: T6 T26 T27
86
87 // drive strength attributes are not supported by verilator
88 `ifdef VERILATOR
89 assign inout_io = (oe) ? out : 1'bz;
90 `else
91 // different driver types
92 1/1 assign (strong0, strong1) inout_io = (oe && attr_i.drive_strength[0]) ? out : 1'bz;
Tests: T6 T26 T27
93 1/1 assign (pull0, pull1) inout_io = (oe && !attr_i.drive_strength[0]) ? out : 1'bz;
Tests: T6 T26 T27
94 // pullup / pulldown termination
95 1/1 assign (weak0, weak1) inout_io = attr_i.pull_en ? attr_i.pull_select : 1'bz;
Tests: T20 T21 T22
Cond Coverage for Instance : tb.dut.u_padring.gen_mio_pads[2].u_mio_pad.gen_generic.u_impl_generic
| Total | Covered | Percent |
|---|
| Conditions | 33 | 33 | 100.00 |
| Logical | 33 | 33 | 100.00 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 51
EXPRESSION (ie_i & ((~attr_i.input_disable)))
--1- ------------2------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Unreachable | |
| 1 | 0 | Covered | T20,T21,T22 |
| 1 | 1 | Covered | T1,T2,T3 |
LINE 78
EXPRESSION (ie ? inout_io : 1'bz)
-1
| -1- | Status | Tests |
|---|
| 0 | Covered | T20,T21,T22 |
| 1 | Covered | T1,T2,T3 |
LINE 80
EXPRESSION (attr_i.invert ^ in_raw_o)
------1------ ----2---
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T26,T27,T35 |
| 0 | 1 | Covered | T6,T26,T27 |
| 1 | 0 | Covered | T20,T21,T22 |
| 1 | 1 | Covered | T20,T21,T22 |
LINE 84
EXPRESSION (out_i ^ attr_i.invert)
--1-- ------2------
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T1,T2,T3 |
| 0 | 1 | Covered | T20,T21,T22 |
| 1 | 0 | Covered | T6,T26,T27 |
| 1 | 1 | Covered | T20,T21,T22 |
LINE 85
EXPRESSION (oe_i & ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en))))
--1- ---------------------------------2---------------------------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T20,T21,T22 |
| 1 | 1 | Covered | T6,T26,T27 |
LINE 85
SUB-EXPRESSION ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en)))
--------------------1------------------- -----------2----------
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T20,T21,T22 |
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T20,T21,T22 |
LINE 85
SUB-EXPRESSION (attr_i.virt_od_en & ((~gen_bidir.out)))
--------1-------- ---------2--------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T20,T21,T22 |
| 1 | 1 | Covered | T20,T21,T22 |
LINE 92
EXPRESSION ((gen_bidir.oe && attr_i.drive_strength[0]) ? gen_bidir.out : 1'bz)
---------------------1--------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T20,T21,T22 |
LINE 92
SUB-EXPRESSION (gen_bidir.oe && attr_i.drive_strength[0])
------1----- ------------2-----------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T20,T21,T22 |
| 1 | 0 | Covered | T6,T26,T27 |
| 1 | 1 | Covered | T20,T21,T22 |
LINE 93
EXPRESSION ((gen_bidir.oe && ((!attr_i.drive_strength[0]))) ? gen_bidir.out : 1'bz)
-----------------------1-----------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T6,T26,T27 |
LINE 93
SUB-EXPRESSION (gen_bidir.oe && ((!attr_i.drive_strength[0])))
------1----- --------------2--------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T20,T21,T22 |
| 1 | 1 | Covered | T6,T26,T27 |
LINE 95
EXPRESSION (attr_i.pull_en ? attr_i.pull_select : 1'bz)
-------1------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T20,T21,T22 |
Branch Coverage for Instance : tb.dut.u_padring.gen_mio_pads[2].u_mio_pad.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
| Branches |
|
8 |
8 |
100.00 |
| TERNARY |
78 |
2 |
2 |
100.00 |
| TERNARY |
92 |
2 |
2 |
100.00 |
| TERNARY |
93 |
2 |
2 |
100.00 |
| TERNARY |
95 |
2 |
2 |
100.00 |
78 assign in_raw_o = ie ? inout_io : 1'bz;
-1-
==>
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T3 |
| 0 |
Covered |
T20,T21,T22 |
92 assign (strong0, strong1) inout_io = (oe && attr_i.drive_strength[0]) ? out : 1'bz;
-1-
==>
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T20,T21,T22 |
| 0 |
Covered |
T1,T2,T3 |
93 assign (pull0, pull1) inout_io = (oe && !attr_i.drive_strength[0]) ? out : 1'bz;
-1-
==>
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T6,T26,T27 |
| 0 |
Covered |
T1,T2,T3 |
95 assign (weak0, weak1) inout_io = attr_i.pull_en ? attr_i.pull_select : 1'bz;
-1-
==>
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T20,T21,T22 |
| 0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_padring.gen_mio_pads[2].u_mio_pad.gen_generic.u_impl_generic
Assertion Details
| Name | Attempts | Real Successes | Failures | Incomplete |
|
AnalogNoScan_A |
1010 |
1010 |
0 |
0 |
AnalogNoScan_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
1010 |
1010 |
0 |
0 |
| T1 |
1 |
1 |
0 |
0 |
| T2 |
1 |
1 |
0 |
0 |
| T3 |
1 |
1 |
0 |
0 |
| T4 |
1 |
1 |
0 |
0 |
| T5 |
1 |
1 |
0 |
0 |
| T6 |
1 |
1 |
0 |
0 |
| T30 |
1 |
1 |
0 |
0 |
| T68 |
1 |
1 |
0 |
0 |
| T104 |
1 |
1 |
0 |
0 |
| T105 |
1 |
1 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_padring.gen_mio_pads[3].u_mio_pad.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 8 | 8 | 100.00 |
| CONT_ASSIGN | 39 | 0 | 0 | |
| CONT_ASSIGN | 51 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 78 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 80 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 84 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 85 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 92 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 93 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 95 | 1 | 1 | 100.00 |
38 logic unused_sigs;
39 unreachable assign unused_sigs = ^{attr_i.slew_rate,
40 attr_i.drive_strength[3:1],
41 attr_i.od_en,
42 attr_i.schmitt_en,
43 attr_i.keep_en,
44 scanmode_i,
45 pok_i};
46 //VCS coverage on
47 // pragma coverage on
48
49 // Input enable (active-high)
50 logic ie;
51 1/1 assign ie = ie_i & ~attr_i.input_disable;
Tests: T20 T21 T22
52
53 if (PadType == InputStd) begin : gen_input_only
54 //VCS coverage off
55 // pragma coverage off
56 logic unused_in_sigs;
57 assign unused_in_sigs = ^{out_i,
58 oe_i,
59 attr_i.virt_od_en,
60 attr_i.drive_strength};
61 //VCS coverage on
62 // pragma coverage on
63
64 assign in_raw_o = ie ? inout_io : 1'bz;
65 // input inversion
66 assign in_o = attr_i.invert ^ in_raw_o;
67
68 // pulls are not supported by verilator
69 `ifndef VERILATOR
70 // pullup / pulldown termination
71 assign (weak0, weak1) inout_io = attr_i.pull_en ? attr_i.pull_select : 1'bz;
72 `endif
73 end else if (PadType == BidirTol ||
74 PadType == DualBidirTol ||
75 PadType == BidirOd ||
76 PadType == BidirStd) begin : gen_bidir
77
78 1/1 assign in_raw_o = ie ? inout_io : 1'bz;
Tests: T6 T26 T27
79 // input inversion
80 1/1 assign in_o = attr_i.invert ^ in_raw_o;
Tests: T6 T26 T27
81
82 // virtual open drain emulation
83 logic oe, out;
84 1/1 assign out = out_i ^ attr_i.invert;
Tests: T6 T26 T27
85 1/1 assign oe = oe_i & ((attr_i.virt_od_en & ~out) | ~attr_i.virt_od_en);
Tests: T6 T26 T27
86
87 // drive strength attributes are not supported by verilator
88 `ifdef VERILATOR
89 assign inout_io = (oe) ? out : 1'bz;
90 `else
91 // different driver types
92 1/1 assign (strong0, strong1) inout_io = (oe && attr_i.drive_strength[0]) ? out : 1'bz;
Tests: T6 T26 T27
93 1/1 assign (pull0, pull1) inout_io = (oe && !attr_i.drive_strength[0]) ? out : 1'bz;
Tests: T6 T26 T27
94 // pullup / pulldown termination
95 1/1 assign (weak0, weak1) inout_io = attr_i.pull_en ? attr_i.pull_select : 1'bz;
Tests: T20 T21 T22
Cond Coverage for Instance : tb.dut.u_padring.gen_mio_pads[3].u_mio_pad.gen_generic.u_impl_generic
| Total | Covered | Percent |
|---|
| Conditions | 33 | 33 | 100.00 |
| Logical | 33 | 33 | 100.00 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 51
EXPRESSION (ie_i & ((~attr_i.input_disable)))
--1- ------------2------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Unreachable | |
| 1 | 0 | Covered | T20,T21,T22 |
| 1 | 1 | Covered | T1,T2,T3 |
LINE 78
EXPRESSION (ie ? inout_io : 1'bz)
-1
| -1- | Status | Tests |
|---|
| 0 | Covered | T20,T21,T22 |
| 1 | Covered | T1,T2,T3 |
LINE 80
EXPRESSION (attr_i.invert ^ in_raw_o)
------1------ ----2---
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T26,T27,T35 |
| 0 | 1 | Covered | T6,T26,T27 |
| 1 | 0 | Covered | T20,T21,T22 |
| 1 | 1 | Covered | T20,T21,T22 |
LINE 84
EXPRESSION (out_i ^ attr_i.invert)
--1-- ------2------
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T1,T2,T3 |
| 0 | 1 | Covered | T20,T21,T22 |
| 1 | 0 | Covered | T6,T26,T27 |
| 1 | 1 | Covered | T20,T21,T22 |
LINE 85
EXPRESSION (oe_i & ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en))))
--1- ---------------------------------2---------------------------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T20,T21,T22 |
| 1 | 1 | Covered | T6,T26,T27 |
LINE 85
SUB-EXPRESSION ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en)))
--------------------1------------------- -----------2----------
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T20,T21,T22 |
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T20,T21,T22 |
LINE 85
SUB-EXPRESSION (attr_i.virt_od_en & ((~gen_bidir.out)))
--------1-------- ---------2--------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T20,T21,T22 |
| 1 | 1 | Covered | T20,T21,T22 |
LINE 92
EXPRESSION ((gen_bidir.oe && attr_i.drive_strength[0]) ? gen_bidir.out : 1'bz)
---------------------1--------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T20,T21,T22 |
LINE 92
SUB-EXPRESSION (gen_bidir.oe && attr_i.drive_strength[0])
------1----- ------------2-----------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T20,T21,T22 |
| 1 | 0 | Covered | T6,T26,T27 |
| 1 | 1 | Covered | T20,T21,T22 |
LINE 93
EXPRESSION ((gen_bidir.oe && ((!attr_i.drive_strength[0]))) ? gen_bidir.out : 1'bz)
-----------------------1-----------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T6,T26,T27 |
LINE 93
SUB-EXPRESSION (gen_bidir.oe && ((!attr_i.drive_strength[0])))
------1----- --------------2--------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T20,T21,T22 |
| 1 | 1 | Covered | T6,T26,T27 |
LINE 95
EXPRESSION (attr_i.pull_en ? attr_i.pull_select : 1'bz)
-------1------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T20,T21,T22 |
Branch Coverage for Instance : tb.dut.u_padring.gen_mio_pads[3].u_mio_pad.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
| Branches |
|
8 |
8 |
100.00 |
| TERNARY |
78 |
2 |
2 |
100.00 |
| TERNARY |
92 |
2 |
2 |
100.00 |
| TERNARY |
93 |
2 |
2 |
100.00 |
| TERNARY |
95 |
2 |
2 |
100.00 |
78 assign in_raw_o = ie ? inout_io : 1'bz;
-1-
==>
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T3 |
| 0 |
Covered |
T20,T21,T22 |
92 assign (strong0, strong1) inout_io = (oe && attr_i.drive_strength[0]) ? out : 1'bz;
-1-
==>
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T20,T21,T22 |
| 0 |
Covered |
T1,T2,T3 |
93 assign (pull0, pull1) inout_io = (oe && !attr_i.drive_strength[0]) ? out : 1'bz;
-1-
==>
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T6,T26,T27 |
| 0 |
Covered |
T1,T2,T3 |
95 assign (weak0, weak1) inout_io = attr_i.pull_en ? attr_i.pull_select : 1'bz;
-1-
==>
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T20,T21,T22 |
| 0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_padring.gen_mio_pads[3].u_mio_pad.gen_generic.u_impl_generic
Assertion Details
| Name | Attempts | Real Successes | Failures | Incomplete |
|
AnalogNoScan_A |
1010 |
1010 |
0 |
0 |
AnalogNoScan_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
1010 |
1010 |
0 |
0 |
| T1 |
1 |
1 |
0 |
0 |
| T2 |
1 |
1 |
0 |
0 |
| T3 |
1 |
1 |
0 |
0 |
| T4 |
1 |
1 |
0 |
0 |
| T5 |
1 |
1 |
0 |
0 |
| T6 |
1 |
1 |
0 |
0 |
| T30 |
1 |
1 |
0 |
0 |
| T68 |
1 |
1 |
0 |
0 |
| T104 |
1 |
1 |
0 |
0 |
| T105 |
1 |
1 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_padring.gen_mio_pads[4].u_mio_pad.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 8 | 8 | 100.00 |
| CONT_ASSIGN | 39 | 0 | 0 | |
| CONT_ASSIGN | 51 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 78 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 80 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 84 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 85 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 92 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 93 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 95 | 1 | 1 | 100.00 |
38 logic unused_sigs;
39 unreachable assign unused_sigs = ^{attr_i.slew_rate,
40 attr_i.drive_strength[3:1],
41 attr_i.od_en,
42 attr_i.schmitt_en,
43 attr_i.keep_en,
44 scanmode_i,
45 pok_i};
46 //VCS coverage on
47 // pragma coverage on
48
49 // Input enable (active-high)
50 logic ie;
51 1/1 assign ie = ie_i & ~attr_i.input_disable;
Tests: T20 T21 T22
52
53 if (PadType == InputStd) begin : gen_input_only
54 //VCS coverage off
55 // pragma coverage off
56 logic unused_in_sigs;
57 assign unused_in_sigs = ^{out_i,
58 oe_i,
59 attr_i.virt_od_en,
60 attr_i.drive_strength};
61 //VCS coverage on
62 // pragma coverage on
63
64 assign in_raw_o = ie ? inout_io : 1'bz;
65 // input inversion
66 assign in_o = attr_i.invert ^ in_raw_o;
67
68 // pulls are not supported by verilator
69 `ifndef VERILATOR
70 // pullup / pulldown termination
71 assign (weak0, weak1) inout_io = attr_i.pull_en ? attr_i.pull_select : 1'bz;
72 `endif
73 end else if (PadType == BidirTol ||
74 PadType == DualBidirTol ||
75 PadType == BidirOd ||
76 PadType == BidirStd) begin : gen_bidir
77
78 1/1 assign in_raw_o = ie ? inout_io : 1'bz;
Tests: T6 T26 T27
79 // input inversion
80 1/1 assign in_o = attr_i.invert ^ in_raw_o;
Tests: T6 T26 T27
81
82 // virtual open drain emulation
83 logic oe, out;
84 1/1 assign out = out_i ^ attr_i.invert;
Tests: T26 T27 T39
85 1/1 assign oe = oe_i & ((attr_i.virt_od_en & ~out) | ~attr_i.virt_od_en);
Tests: T26 T27 T39
86
87 // drive strength attributes are not supported by verilator
88 `ifdef VERILATOR
89 assign inout_io = (oe) ? out : 1'bz;
90 `else
91 // different driver types
92 1/1 assign (strong0, strong1) inout_io = (oe && attr_i.drive_strength[0]) ? out : 1'bz;
Tests: T26 T27 T39
93 1/1 assign (pull0, pull1) inout_io = (oe && !attr_i.drive_strength[0]) ? out : 1'bz;
Tests: T26 T27 T39
94 // pullup / pulldown termination
95 1/1 assign (weak0, weak1) inout_io = attr_i.pull_en ? attr_i.pull_select : 1'bz;
Tests: T20 T21 T22
Cond Coverage for Instance : tb.dut.u_padring.gen_mio_pads[4].u_mio_pad.gen_generic.u_impl_generic
| Total | Covered | Percent |
|---|
| Conditions | 33 | 33 | 100.00 |
| Logical | 33 | 33 | 100.00 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 51
EXPRESSION (ie_i & ((~attr_i.input_disable)))
--1- ------------2------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Unreachable | |
| 1 | 0 | Covered | T20,T21,T22 |
| 1 | 1 | Covered | T1,T2,T3 |
LINE 78
EXPRESSION (ie ? inout_io : 1'bz)
-1
| -1- | Status | Tests |
|---|
| 0 | Covered | T20,T21,T22 |
| 1 | Covered | T1,T2,T3 |
LINE 80
EXPRESSION (attr_i.invert ^ in_raw_o)
------1------ ----2---
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T6,T26,T27 |
| 0 | 1 | Covered | T6,T26,T27 |
| 1 | 0 | Covered | T20,T21,T22 |
| 1 | 1 | Covered | T21,T22,T44 |
LINE 84
EXPRESSION (out_i ^ attr_i.invert)
--1-- ------2------
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T1,T2,T3 |
| 0 | 1 | Covered | T20,T21,T22 |
| 1 | 0 | Covered | T26,T27,T39 |
| 1 | 1 | Covered | T20,T21,T22 |
LINE 85
EXPRESSION (oe_i & ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en))))
--1- ---------------------------------2---------------------------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T20,T21,T22 |
| 1 | 1 | Covered | T26,T27,T39 |
LINE 85
SUB-EXPRESSION ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en)))
--------------------1------------------- -----------2----------
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T20,T21,T22 |
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T20,T21,T22 |
LINE 85
SUB-EXPRESSION (attr_i.virt_od_en & ((~gen_bidir.out)))
--------1-------- ---------2--------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T20,T21,T22 |
| 1 | 1 | Covered | T20,T21,T22 |
LINE 92
EXPRESSION ((gen_bidir.oe && attr_i.drive_strength[0]) ? gen_bidir.out : 1'bz)
---------------------1--------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T20,T21,T22 |
LINE 92
SUB-EXPRESSION (gen_bidir.oe && attr_i.drive_strength[0])
------1----- ------------2-----------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T20,T21,T22 |
| 1 | 0 | Covered | T26,T27,T39 |
| 1 | 1 | Covered | T20,T21,T22 |
LINE 93
EXPRESSION ((gen_bidir.oe && ((!attr_i.drive_strength[0]))) ? gen_bidir.out : 1'bz)
-----------------------1-----------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T26,T27,T39 |
LINE 93
SUB-EXPRESSION (gen_bidir.oe && ((!attr_i.drive_strength[0])))
------1----- --------------2--------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T20,T21,T22 |
| 1 | 1 | Covered | T26,T27,T39 |
LINE 95
EXPRESSION (attr_i.pull_en ? attr_i.pull_select : 1'bz)
-------1------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T20,T21,T22 |
Branch Coverage for Instance : tb.dut.u_padring.gen_mio_pads[4].u_mio_pad.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
| Branches |
|
8 |
8 |
100.00 |
| TERNARY |
78 |
2 |
2 |
100.00 |
| TERNARY |
92 |
2 |
2 |
100.00 |
| TERNARY |
93 |
2 |
2 |
100.00 |
| TERNARY |
95 |
2 |
2 |
100.00 |
78 assign in_raw_o = ie ? inout_io : 1'bz;
-1-
==>
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T3 |
| 0 |
Covered |
T20,T21,T22 |
92 assign (strong0, strong1) inout_io = (oe && attr_i.drive_strength[0]) ? out : 1'bz;
-1-
==>
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T20,T21,T22 |
| 0 |
Covered |
T1,T2,T3 |
93 assign (pull0, pull1) inout_io = (oe && !attr_i.drive_strength[0]) ? out : 1'bz;
-1-
==>
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T26,T27,T39 |
| 0 |
Covered |
T1,T2,T3 |
95 assign (weak0, weak1) inout_io = attr_i.pull_en ? attr_i.pull_select : 1'bz;
-1-
==>
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T20,T21,T22 |
| 0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_padring.gen_mio_pads[4].u_mio_pad.gen_generic.u_impl_generic
Assertion Details
| Name | Attempts | Real Successes | Failures | Incomplete |
|
AnalogNoScan_A |
1010 |
1010 |
0 |
0 |
AnalogNoScan_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
1010 |
1010 |
0 |
0 |
| T1 |
1 |
1 |
0 |
0 |
| T2 |
1 |
1 |
0 |
0 |
| T3 |
1 |
1 |
0 |
0 |
| T4 |
1 |
1 |
0 |
0 |
| T5 |
1 |
1 |
0 |
0 |
| T6 |
1 |
1 |
0 |
0 |
| T30 |
1 |
1 |
0 |
0 |
| T68 |
1 |
1 |
0 |
0 |
| T104 |
1 |
1 |
0 |
0 |
| T105 |
1 |
1 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_padring.gen_mio_pads[5].u_mio_pad.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 8 | 8 | 100.00 |
| CONT_ASSIGN | 39 | 0 | 0 | |
| CONT_ASSIGN | 51 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 78 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 80 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 84 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 85 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 92 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 93 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 95 | 1 | 1 | 100.00 |
38 logic unused_sigs;
39 unreachable assign unused_sigs = ^{attr_i.slew_rate,
40 attr_i.drive_strength[3:1],
41 attr_i.od_en,
42 attr_i.schmitt_en,
43 attr_i.keep_en,
44 scanmode_i,
45 pok_i};
46 //VCS coverage on
47 // pragma coverage on
48
49 // Input enable (active-high)
50 logic ie;
51 1/1 assign ie = ie_i & ~attr_i.input_disable;
Tests: T20 T21 T22
52
53 if (PadType == InputStd) begin : gen_input_only
54 //VCS coverage off
55 // pragma coverage off
56 logic unused_in_sigs;
57 assign unused_in_sigs = ^{out_i,
58 oe_i,
59 attr_i.virt_od_en,
60 attr_i.drive_strength};
61 //VCS coverage on
62 // pragma coverage on
63
64 assign in_raw_o = ie ? inout_io : 1'bz;
65 // input inversion
66 assign in_o = attr_i.invert ^ in_raw_o;
67
68 // pulls are not supported by verilator
69 `ifndef VERILATOR
70 // pullup / pulldown termination
71 assign (weak0, weak1) inout_io = attr_i.pull_en ? attr_i.pull_select : 1'bz;
72 `endif
73 end else if (PadType == BidirTol ||
74 PadType == DualBidirTol ||
75 PadType == BidirOd ||
76 PadType == BidirStd) begin : gen_bidir
77
78 1/1 assign in_raw_o = ie ? inout_io : 1'bz;
Tests: T6 T26 T27
79 // input inversion
80 1/1 assign in_o = attr_i.invert ^ in_raw_o;
Tests: T6 T26 T27
81
82 // virtual open drain emulation
83 logic oe, out;
84 1/1 assign out = out_i ^ attr_i.invert;
Tests: T26 T27 T63
85 1/1 assign oe = oe_i & ((attr_i.virt_od_en & ~out) | ~attr_i.virt_od_en);
Tests: T6 T26 T27
86
87 // drive strength attributes are not supported by verilator
88 `ifdef VERILATOR
89 assign inout_io = (oe) ? out : 1'bz;
90 `else
91 // different driver types
92 1/1 assign (strong0, strong1) inout_io = (oe && attr_i.drive_strength[0]) ? out : 1'bz;
Tests: T6 T26 T27
93 1/1 assign (pull0, pull1) inout_io = (oe && !attr_i.drive_strength[0]) ? out : 1'bz;
Tests: T6 T26 T27
94 // pullup / pulldown termination
95 1/1 assign (weak0, weak1) inout_io = attr_i.pull_en ? attr_i.pull_select : 1'bz;
Tests: T20 T21 T22
Cond Coverage for Instance : tb.dut.u_padring.gen_mio_pads[5].u_mio_pad.gen_generic.u_impl_generic
| Total | Covered | Percent |
|---|
| Conditions | 33 | 33 | 100.00 |
| Logical | 33 | 33 | 100.00 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 51
EXPRESSION (ie_i & ((~attr_i.input_disable)))
--1- ------------2------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Unreachable | |
| 1 | 0 | Covered | T20,T21,T22 |
| 1 | 1 | Covered | T1,T2,T3 |
LINE 78
EXPRESSION (ie ? inout_io : 1'bz)
-1
| -1- | Status | Tests |
|---|
| 0 | Covered | T20,T21,T22 |
| 1 | Covered | T1,T2,T3 |
LINE 80
EXPRESSION (attr_i.invert ^ in_raw_o)
------1------ ----2---
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T6,T26,T27 |
| 0 | 1 | Covered | T26,T27,T63 |
| 1 | 0 | Covered | T21,T22,T44 |
| 1 | 1 | Covered | T21,T22,T44 |
LINE 84
EXPRESSION (out_i ^ attr_i.invert)
--1-- ------2------
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T1,T2,T3 |
| 0 | 1 | Covered | T20,T21,T22 |
| 1 | 0 | Covered | T26,T27,T63 |
| 1 | 1 | Covered | T20,T21,T22 |
LINE 85
EXPRESSION (oe_i & ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en))))
--1- ---------------------------------2---------------------------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T20,T21,T22 |
| 1 | 1 | Covered | T6,T26,T27 |
LINE 85
SUB-EXPRESSION ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en)))
--------------------1------------------- -----------2----------
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T20,T21,T22 |
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T20,T21,T22 |
LINE 85
SUB-EXPRESSION (attr_i.virt_od_en & ((~gen_bidir.out)))
--------1-------- ---------2--------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T20,T21,T22 |
| 1 | 1 | Covered | T20,T21,T22 |
LINE 92
EXPRESSION ((gen_bidir.oe && attr_i.drive_strength[0]) ? gen_bidir.out : 1'bz)
---------------------1--------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T20,T21,T22 |
LINE 92
SUB-EXPRESSION (gen_bidir.oe && attr_i.drive_strength[0])
------1----- ------------2-----------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T20,T21,T22 |
| 1 | 0 | Covered | T6,T26,T27 |
| 1 | 1 | Covered | T20,T21,T22 |
LINE 93
EXPRESSION ((gen_bidir.oe && ((!attr_i.drive_strength[0]))) ? gen_bidir.out : 1'bz)
-----------------------1-----------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T6,T26,T27 |
LINE 93
SUB-EXPRESSION (gen_bidir.oe && ((!attr_i.drive_strength[0])))
------1----- --------------2--------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T20,T21,T22 |
| 1 | 1 | Covered | T6,T26,T27 |
LINE 95
EXPRESSION (attr_i.pull_en ? attr_i.pull_select : 1'bz)
-------1------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T20,T21,T22 |
Branch Coverage for Instance : tb.dut.u_padring.gen_mio_pads[5].u_mio_pad.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
| Branches |
|
8 |
8 |
100.00 |
| TERNARY |
78 |
2 |
2 |
100.00 |
| TERNARY |
92 |
2 |
2 |
100.00 |
| TERNARY |
93 |
2 |
2 |
100.00 |
| TERNARY |
95 |
2 |
2 |
100.00 |
78 assign in_raw_o = ie ? inout_io : 1'bz;
-1-
==>
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T3 |
| 0 |
Covered |
T20,T21,T22 |
92 assign (strong0, strong1) inout_io = (oe && attr_i.drive_strength[0]) ? out : 1'bz;
-1-
==>
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T20,T21,T22 |
| 0 |
Covered |
T1,T2,T3 |
93 assign (pull0, pull1) inout_io = (oe && !attr_i.drive_strength[0]) ? out : 1'bz;
-1-
==>
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T6,T26,T27 |
| 0 |
Covered |
T1,T2,T3 |
95 assign (weak0, weak1) inout_io = attr_i.pull_en ? attr_i.pull_select : 1'bz;
-1-
==>
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T20,T21,T22 |
| 0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_padring.gen_mio_pads[5].u_mio_pad.gen_generic.u_impl_generic
Assertion Details
| Name | Attempts | Real Successes | Failures | Incomplete |
|
AnalogNoScan_A |
1010 |
1010 |
0 |
0 |
AnalogNoScan_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
1010 |
1010 |
0 |
0 |
| T1 |
1 |
1 |
0 |
0 |
| T2 |
1 |
1 |
0 |
0 |
| T3 |
1 |
1 |
0 |
0 |
| T4 |
1 |
1 |
0 |
0 |
| T5 |
1 |
1 |
0 |
0 |
| T6 |
1 |
1 |
0 |
0 |
| T30 |
1 |
1 |
0 |
0 |
| T68 |
1 |
1 |
0 |
0 |
| T104 |
1 |
1 |
0 |
0 |
| T105 |
1 |
1 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_padring.gen_mio_pads[6].u_mio_pad.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 8 | 8 | 100.00 |
| CONT_ASSIGN | 39 | 0 | 0 | |
| CONT_ASSIGN | 51 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 78 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 80 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 84 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 85 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 92 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 93 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 95 | 1 | 1 | 100.00 |
38 logic unused_sigs;
39 unreachable assign unused_sigs = ^{attr_i.slew_rate,
40 attr_i.drive_strength[3:1],
41 attr_i.od_en,
42 attr_i.schmitt_en,
43 attr_i.keep_en,
44 scanmode_i,
45 pok_i};
46 //VCS coverage on
47 // pragma coverage on
48
49 // Input enable (active-high)
50 logic ie;
51 1/1 assign ie = ie_i & ~attr_i.input_disable;
Tests: T20 T21 T22
52
53 if (PadType == InputStd) begin : gen_input_only
54 //VCS coverage off
55 // pragma coverage off
56 logic unused_in_sigs;
57 assign unused_in_sigs = ^{out_i,
58 oe_i,
59 attr_i.virt_od_en,
60 attr_i.drive_strength};
61 //VCS coverage on
62 // pragma coverage on
63
64 assign in_raw_o = ie ? inout_io : 1'bz;
65 // input inversion
66 assign in_o = attr_i.invert ^ in_raw_o;
67
68 // pulls are not supported by verilator
69 `ifndef VERILATOR
70 // pullup / pulldown termination
71 assign (weak0, weak1) inout_io = attr_i.pull_en ? attr_i.pull_select : 1'bz;
72 `endif
73 end else if (PadType == BidirTol ||
74 PadType == DualBidirTol ||
75 PadType == BidirOd ||
76 PadType == BidirStd) begin : gen_bidir
77
78 1/1 assign in_raw_o = ie ? inout_io : 1'bz;
Tests: T6 T26 T27
79 // input inversion
80 1/1 assign in_o = attr_i.invert ^ in_raw_o;
Tests: T6 T26 T27
81
82 // virtual open drain emulation
83 logic oe, out;
84 1/1 assign out = out_i ^ attr_i.invert;
Tests: T26 T27 T39
85 1/1 assign oe = oe_i & ((attr_i.virt_od_en & ~out) | ~attr_i.virt_od_en);
Tests: T6 T26 T27
86
87 // drive strength attributes are not supported by verilator
88 `ifdef VERILATOR
89 assign inout_io = (oe) ? out : 1'bz;
90 `else
91 // different driver types
92 1/1 assign (strong0, strong1) inout_io = (oe && attr_i.drive_strength[0]) ? out : 1'bz;
Tests: T6 T26 T27
93 1/1 assign (pull0, pull1) inout_io = (oe && !attr_i.drive_strength[0]) ? out : 1'bz;
Tests: T6 T26 T27
94 // pullup / pulldown termination
95 1/1 assign (weak0, weak1) inout_io = attr_i.pull_en ? attr_i.pull_select : 1'bz;
Tests: T20 T21 T22
Cond Coverage for Instance : tb.dut.u_padring.gen_mio_pads[6].u_mio_pad.gen_generic.u_impl_generic
| Total | Covered | Percent |
|---|
| Conditions | 33 | 33 | 100.00 |
| Logical | 33 | 33 | 100.00 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 51
EXPRESSION (ie_i & ((~attr_i.input_disable)))
--1- ------------2------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Unreachable | |
| 1 | 0 | Covered | T20,T21,T22 |
| 1 | 1 | Covered | T1,T2,T3 |
LINE 78
EXPRESSION (ie ? inout_io : 1'bz)
-1
| -1- | Status | Tests |
|---|
| 0 | Covered | T20,T21,T22 |
| 1 | Covered | T1,T2,T3 |
LINE 80
EXPRESSION (attr_i.invert ^ in_raw_o)
------1------ ----2---
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T6,T26,T27 |
| 0 | 1 | Covered | T26,T27,T39 |
| 1 | 0 | Covered | T21,T22,T222 |
| 1 | 1 | Covered | T21,T22,T222 |
LINE 84
EXPRESSION (out_i ^ attr_i.invert)
--1-- ------2------
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T1,T2,T3 |
| 0 | 1 | Covered | T20,T21,T22 |
| 1 | 0 | Covered | T26,T27,T39 |
| 1 | 1 | Covered | T20,T21,T22 |
LINE 85
EXPRESSION (oe_i & ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en))))
--1- ---------------------------------2---------------------------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T20,T21,T22 |
| 1 | 1 | Covered | T6,T26,T27 |
LINE 85
SUB-EXPRESSION ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en)))
--------------------1------------------- -----------2----------
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T20,T21,T22 |
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T20,T21,T22 |
LINE 85
SUB-EXPRESSION (attr_i.virt_od_en & ((~gen_bidir.out)))
--------1-------- ---------2--------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T20,T21,T22 |
| 1 | 1 | Covered | T20,T21,T22 |
LINE 92
EXPRESSION ((gen_bidir.oe && attr_i.drive_strength[0]) ? gen_bidir.out : 1'bz)
---------------------1--------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T20,T21,T22 |
LINE 92
SUB-EXPRESSION (gen_bidir.oe && attr_i.drive_strength[0])
------1----- ------------2-----------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T20,T21,T22 |
| 1 | 0 | Covered | T6,T26,T27 |
| 1 | 1 | Covered | T20,T21,T22 |
LINE 93
EXPRESSION ((gen_bidir.oe && ((!attr_i.drive_strength[0]))) ? gen_bidir.out : 1'bz)
-----------------------1-----------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T6,T26,T27 |
LINE 93
SUB-EXPRESSION (gen_bidir.oe && ((!attr_i.drive_strength[0])))
------1----- --------------2--------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T20,T21,T22 |
| 1 | 1 | Covered | T6,T26,T27 |
LINE 95
EXPRESSION (attr_i.pull_en ? attr_i.pull_select : 1'bz)
-------1------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T20,T21,T22 |
Branch Coverage for Instance : tb.dut.u_padring.gen_mio_pads[6].u_mio_pad.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
| Branches |
|
8 |
8 |
100.00 |
| TERNARY |
78 |
2 |
2 |
100.00 |
| TERNARY |
92 |
2 |
2 |
100.00 |
| TERNARY |
93 |
2 |
2 |
100.00 |
| TERNARY |
95 |
2 |
2 |
100.00 |
78 assign in_raw_o = ie ? inout_io : 1'bz;
-1-
==>
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T3 |
| 0 |
Covered |
T20,T21,T22 |
92 assign (strong0, strong1) inout_io = (oe && attr_i.drive_strength[0]) ? out : 1'bz;
-1-
==>
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T20,T21,T22 |
| 0 |
Covered |
T1,T2,T3 |
93 assign (pull0, pull1) inout_io = (oe && !attr_i.drive_strength[0]) ? out : 1'bz;
-1-
==>
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T6,T26,T27 |
| 0 |
Covered |
T1,T2,T3 |
95 assign (weak0, weak1) inout_io = attr_i.pull_en ? attr_i.pull_select : 1'bz;
-1-
==>
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T20,T21,T22 |
| 0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_padring.gen_mio_pads[6].u_mio_pad.gen_generic.u_impl_generic
Assertion Details
| Name | Attempts | Real Successes | Failures | Incomplete |
|
AnalogNoScan_A |
1010 |
1010 |
0 |
0 |
AnalogNoScan_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
1010 |
1010 |
0 |
0 |
| T1 |
1 |
1 |
0 |
0 |
| T2 |
1 |
1 |
0 |
0 |
| T3 |
1 |
1 |
0 |
0 |
| T4 |
1 |
1 |
0 |
0 |
| T5 |
1 |
1 |
0 |
0 |
| T6 |
1 |
1 |
0 |
0 |
| T30 |
1 |
1 |
0 |
0 |
| T68 |
1 |
1 |
0 |
0 |
| T104 |
1 |
1 |
0 |
0 |
| T105 |
1 |
1 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_padring.gen_mio_pads[7].u_mio_pad.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 8 | 8 | 100.00 |
| CONT_ASSIGN | 39 | 0 | 0 | |
| CONT_ASSIGN | 51 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 78 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 80 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 84 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 85 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 92 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 93 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 95 | 1 | 1 | 100.00 |
38 logic unused_sigs;
39 unreachable assign unused_sigs = ^{attr_i.slew_rate,
40 attr_i.drive_strength[3:1],
41 attr_i.od_en,
42 attr_i.schmitt_en,
43 attr_i.keep_en,
44 scanmode_i,
45 pok_i};
46 //VCS coverage on
47 // pragma coverage on
48
49 // Input enable (active-high)
50 logic ie;
51 1/1 assign ie = ie_i & ~attr_i.input_disable;
Tests: T20 T21 T22
52
53 if (PadType == InputStd) begin : gen_input_only
54 //VCS coverage off
55 // pragma coverage off
56 logic unused_in_sigs;
57 assign unused_in_sigs = ^{out_i,
58 oe_i,
59 attr_i.virt_od_en,
60 attr_i.drive_strength};
61 //VCS coverage on
62 // pragma coverage on
63
64 assign in_raw_o = ie ? inout_io : 1'bz;
65 // input inversion
66 assign in_o = attr_i.invert ^ in_raw_o;
67
68 // pulls are not supported by verilator
69 `ifndef VERILATOR
70 // pullup / pulldown termination
71 assign (weak0, weak1) inout_io = attr_i.pull_en ? attr_i.pull_select : 1'bz;
72 `endif
73 end else if (PadType == BidirTol ||
74 PadType == DualBidirTol ||
75 PadType == BidirOd ||
76 PadType == BidirStd) begin : gen_bidir
77
78 1/1 assign in_raw_o = ie ? inout_io : 1'bz;
Tests: T5 T6 T11
79 // input inversion
80 1/1 assign in_o = attr_i.invert ^ in_raw_o;
Tests: T5 T6 T11
81
82 // virtual open drain emulation
83 logic oe, out;
84 1/1 assign out = out_i ^ attr_i.invert;
Tests: T26 T27 T39
85 1/1 assign oe = oe_i & ((attr_i.virt_od_en & ~out) | ~attr_i.virt_od_en);
Tests: T5 T26 T27
86
87 // drive strength attributes are not supported by verilator
88 `ifdef VERILATOR
89 assign inout_io = (oe) ? out : 1'bz;
90 `else
91 // different driver types
92 1/1 assign (strong0, strong1) inout_io = (oe && attr_i.drive_strength[0]) ? out : 1'bz;
Tests: T5 T26 T27
93 1/1 assign (pull0, pull1) inout_io = (oe && !attr_i.drive_strength[0]) ? out : 1'bz;
Tests: T5 T26 T27
94 // pullup / pulldown termination
95 1/1 assign (weak0, weak1) inout_io = attr_i.pull_en ? attr_i.pull_select : 1'bz;
Tests: T11 T49 T50
Cond Coverage for Instance : tb.dut.u_padring.gen_mio_pads[7].u_mio_pad.gen_generic.u_impl_generic
| Total | Covered | Percent |
|---|
| Conditions | 33 | 33 | 100.00 |
| Logical | 33 | 33 | 100.00 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 51
EXPRESSION (ie_i & ((~attr_i.input_disable)))
--1- ------------2------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Unreachable | |
| 1 | 0 | Covered | T20,T21,T22 |
| 1 | 1 | Covered | T1,T2,T3 |
LINE 78
EXPRESSION (ie ? inout_io : 1'bz)
-1
| -1- | Status | Tests |
|---|
| 0 | Covered | T20,T21,T22 |
| 1 | Covered | T1,T2,T3 |
LINE 80
EXPRESSION (attr_i.invert ^ in_raw_o)
------1------ ----2---
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T5,T6,T11 |
| 0 | 1 | Covered | T6,T11,T26 |
| 1 | 0 | Covered | T20,T21,T22 |
| 1 | 1 | Covered | T20,T21,T22 |
LINE 84
EXPRESSION (out_i ^ attr_i.invert)
--1-- ------2------
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T1,T2,T3 |
| 0 | 1 | Covered | T20,T21,T22 |
| 1 | 0 | Covered | T26,T27,T39 |
| 1 | 1 | Covered | T20,T21,T22 |
LINE 85
EXPRESSION (oe_i & ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en))))
--1- ---------------------------------2---------------------------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T20,T21,T22 |
| 1 | 1 | Covered | T5,T26,T27 |
LINE 85
SUB-EXPRESSION ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en)))
--------------------1------------------- -----------2----------
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T20,T21,T22 |
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T20,T21,T22 |
LINE 85
SUB-EXPRESSION (attr_i.virt_od_en & ((~gen_bidir.out)))
--------1-------- ---------2--------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T20,T21,T22 |
| 1 | 1 | Covered | T20,T21,T22 |
LINE 92
EXPRESSION ((gen_bidir.oe && attr_i.drive_strength[0]) ? gen_bidir.out : 1'bz)
---------------------1--------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T20,T21,T22 |
LINE 92
SUB-EXPRESSION (gen_bidir.oe && attr_i.drive_strength[0])
------1----- ------------2-----------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T20,T21,T22 |
| 1 | 0 | Covered | T5,T26,T27 |
| 1 | 1 | Covered | T20,T21,T22 |
LINE 93
EXPRESSION ((gen_bidir.oe && ((!attr_i.drive_strength[0]))) ? gen_bidir.out : 1'bz)
-----------------------1-----------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T5,T26,T27 |
LINE 93
SUB-EXPRESSION (gen_bidir.oe && ((!attr_i.drive_strength[0])))
------1----- --------------2--------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T20,T21,T22 |
| 1 | 1 | Covered | T5,T26,T27 |
LINE 95
EXPRESSION (attr_i.pull_en ? attr_i.pull_select : 1'bz)
-------1------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T11,T49,T50 |
Branch Coverage for Instance : tb.dut.u_padring.gen_mio_pads[7].u_mio_pad.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
| Branches |
|
8 |
8 |
100.00 |
| TERNARY |
78 |
2 |
2 |
100.00 |
| TERNARY |
92 |
2 |
2 |
100.00 |
| TERNARY |
93 |
2 |
2 |
100.00 |
| TERNARY |
95 |
2 |
2 |
100.00 |
78 assign in_raw_o = ie ? inout_io : 1'bz;
-1-
==>
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T3 |
| 0 |
Covered |
T20,T21,T22 |
92 assign (strong0, strong1) inout_io = (oe && attr_i.drive_strength[0]) ? out : 1'bz;
-1-
==>
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T20,T21,T22 |
| 0 |
Covered |
T1,T2,T3 |
93 assign (pull0, pull1) inout_io = (oe && !attr_i.drive_strength[0]) ? out : 1'bz;
-1-
==>
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T5,T26,T27 |
| 0 |
Covered |
T1,T2,T3 |
95 assign (weak0, weak1) inout_io = attr_i.pull_en ? attr_i.pull_select : 1'bz;
-1-
==>
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T11,T49,T50 |
| 0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_padring.gen_mio_pads[7].u_mio_pad.gen_generic.u_impl_generic
Assertion Details
| Name | Attempts | Real Successes | Failures | Incomplete |
|
AnalogNoScan_A |
1010 |
1010 |
0 |
0 |
AnalogNoScan_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
1010 |
1010 |
0 |
0 |
| T1 |
1 |
1 |
0 |
0 |
| T2 |
1 |
1 |
0 |
0 |
| T3 |
1 |
1 |
0 |
0 |
| T4 |
1 |
1 |
0 |
0 |
| T5 |
1 |
1 |
0 |
0 |
| T6 |
1 |
1 |
0 |
0 |
| T30 |
1 |
1 |
0 |
0 |
| T68 |
1 |
1 |
0 |
0 |
| T104 |
1 |
1 |
0 |
0 |
| T105 |
1 |
1 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_padring.gen_mio_pads[8].u_mio_pad.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 8 | 8 | 100.00 |
| CONT_ASSIGN | 39 | 0 | 0 | |
| CONT_ASSIGN | 51 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 78 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 80 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 84 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 85 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 92 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 93 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 95 | 1 | 1 | 100.00 |
38 logic unused_sigs;
39 unreachable assign unused_sigs = ^{attr_i.slew_rate,
40 attr_i.drive_strength[3:1],
41 attr_i.od_en,
42 attr_i.schmitt_en,
43 attr_i.keep_en,
44 scanmode_i,
45 pok_i};
46 //VCS coverage on
47 // pragma coverage on
48
49 // Input enable (active-high)
50 logic ie;
51 1/1 assign ie = ie_i & ~attr_i.input_disable;
Tests: T20 T21 T22
52
53 if (PadType == InputStd) begin : gen_input_only
54 //VCS coverage off
55 // pragma coverage off
56 logic unused_in_sigs;
57 assign unused_in_sigs = ^{out_i,
58 oe_i,
59 attr_i.virt_od_en,
60 attr_i.drive_strength};
61 //VCS coverage on
62 // pragma coverage on
63
64 assign in_raw_o = ie ? inout_io : 1'bz;
65 // input inversion
66 assign in_o = attr_i.invert ^ in_raw_o;
67
68 // pulls are not supported by verilator
69 `ifndef VERILATOR
70 // pullup / pulldown termination
71 assign (weak0, weak1) inout_io = attr_i.pull_en ? attr_i.pull_select : 1'bz;
72 `endif
73 end else if (PadType == BidirTol ||
74 PadType == DualBidirTol ||
75 PadType == BidirOd ||
76 PadType == BidirStd) begin : gen_bidir
77
78 1/1 assign in_raw_o = ie ? inout_io : 1'bz;
Tests: T5 T6 T26
79 // input inversion
80 1/1 assign in_o = attr_i.invert ^ in_raw_o;
Tests: T5 T6 T26
81
82 // virtual open drain emulation
83 logic oe, out;
84 1/1 assign out = out_i ^ attr_i.invert;
Tests: T6 T27 T39
85 1/1 assign oe = oe_i & ((attr_i.virt_od_en & ~out) | ~attr_i.virt_od_en);
Tests: T6 T27 T58
86
87 // drive strength attributes are not supported by verilator
88 `ifdef VERILATOR
89 assign inout_io = (oe) ? out : 1'bz;
90 `else
91 // different driver types
92 1/1 assign (strong0, strong1) inout_io = (oe && attr_i.drive_strength[0]) ? out : 1'bz;
Tests: T6 T27 T58
93 1/1 assign (pull0, pull1) inout_io = (oe && !attr_i.drive_strength[0]) ? out : 1'bz;
Tests: T6 T27 T58
94 // pullup / pulldown termination
95 1/1 assign (weak0, weak1) inout_io = attr_i.pull_en ? attr_i.pull_select : 1'bz;
Tests: T20 T21 T22
Cond Coverage for Instance : tb.dut.u_padring.gen_mio_pads[8].u_mio_pad.gen_generic.u_impl_generic
| Total | Covered | Percent |
|---|
| Conditions | 33 | 33 | 100.00 |
| Logical | 33 | 33 | 100.00 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 51
EXPRESSION (ie_i & ((~attr_i.input_disable)))
--1- ------------2------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Unreachable | |
| 1 | 0 | Covered | T20,T21,T22 |
| 1 | 1 | Covered | T1,T2,T3 |
LINE 78
EXPRESSION (ie ? inout_io : 1'bz)
-1
| -1- | Status | Tests |
|---|
| 0 | Covered | T20,T21,T22 |
| 1 | Covered | T1,T2,T3 |
LINE 80
EXPRESSION (attr_i.invert ^ in_raw_o)
------1------ ----2---
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T5,T26,T27 |
| 0 | 1 | Covered | T5,T6,T26 |
| 1 | 0 | Covered | T20,T21,T22 |
| 1 | 1 | Covered | T20,T21,T22 |
LINE 84
EXPRESSION (out_i ^ attr_i.invert)
--1-- ------2------
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T1,T2,T3 |
| 0 | 1 | Covered | T20,T21,T22 |
| 1 | 0 | Covered | T6,T27,T39 |
| 1 | 1 | Covered | T20,T21,T22 |
LINE 85
EXPRESSION (oe_i & ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en))))
--1- ---------------------------------2---------------------------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T20,T21,T22 |
| 1 | 1 | Covered | T6,T27,T58 |
LINE 85
SUB-EXPRESSION ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en)))
--------------------1------------------- -----------2----------
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T20,T21,T22 |
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T20,T21,T22 |
LINE 85
SUB-EXPRESSION (attr_i.virt_od_en & ((~gen_bidir.out)))
--------1-------- ---------2--------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T20,T21,T22 |
| 1 | 1 | Covered | T20,T21,T22 |
LINE 92
EXPRESSION ((gen_bidir.oe && attr_i.drive_strength[0]) ? gen_bidir.out : 1'bz)
---------------------1--------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T20,T21,T22 |
LINE 92
SUB-EXPRESSION (gen_bidir.oe && attr_i.drive_strength[0])
------1----- ------------2-----------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T20,T21,T22 |
| 1 | 0 | Covered | T6,T27,T58 |
| 1 | 1 | Covered | T20,T21,T22 |
LINE 93
EXPRESSION ((gen_bidir.oe && ((!attr_i.drive_strength[0]))) ? gen_bidir.out : 1'bz)
-----------------------1-----------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T6,T27,T58 |
LINE 93
SUB-EXPRESSION (gen_bidir.oe && ((!attr_i.drive_strength[0])))
------1----- --------------2--------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T20,T21,T22 |
| 1 | 1 | Covered | T6,T27,T58 |
LINE 95
EXPRESSION (attr_i.pull_en ? attr_i.pull_select : 1'bz)
-------1------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T20,T21,T22 |
Branch Coverage for Instance : tb.dut.u_padring.gen_mio_pads[8].u_mio_pad.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
| Branches |
|
8 |
8 |
100.00 |
| TERNARY |
78 |
2 |
2 |
100.00 |
| TERNARY |
92 |
2 |
2 |
100.00 |
| TERNARY |
93 |
2 |
2 |
100.00 |
| TERNARY |
95 |
2 |
2 |
100.00 |
78 assign in_raw_o = ie ? inout_io : 1'bz;
-1-
==>
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T3 |
| 0 |
Covered |
T20,T21,T22 |
92 assign (strong0, strong1) inout_io = (oe && attr_i.drive_strength[0]) ? out : 1'bz;
-1-
==>
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T20,T21,T22 |
| 0 |
Covered |
T1,T2,T3 |
93 assign (pull0, pull1) inout_io = (oe && !attr_i.drive_strength[0]) ? out : 1'bz;
-1-
==>
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T6,T27,T58 |
| 0 |
Covered |
T1,T2,T3 |
95 assign (weak0, weak1) inout_io = attr_i.pull_en ? attr_i.pull_select : 1'bz;
-1-
==>
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T20,T21,T22 |
| 0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_padring.gen_mio_pads[8].u_mio_pad.gen_generic.u_impl_generic
Assertion Details
| Name | Attempts | Real Successes | Failures | Incomplete |
|
AnalogNoScan_A |
1010 |
1010 |
0 |
0 |
AnalogNoScan_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
1010 |
1010 |
0 |
0 |
| T1 |
1 |
1 |
0 |
0 |
| T2 |
1 |
1 |
0 |
0 |
| T3 |
1 |
1 |
0 |
0 |
| T4 |
1 |
1 |
0 |
0 |
| T5 |
1 |
1 |
0 |
0 |
| T6 |
1 |
1 |
0 |
0 |
| T30 |
1 |
1 |
0 |
0 |
| T68 |
1 |
1 |
0 |
0 |
| T104 |
1 |
1 |
0 |
0 |
| T105 |
1 |
1 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_padring.gen_mio_pads[9].u_mio_pad.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 8 | 8 | 100.00 |
| CONT_ASSIGN | 39 | 0 | 0 | |
| CONT_ASSIGN | 51 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 78 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 80 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 84 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 85 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 92 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 93 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 95 | 1 | 1 | 100.00 |
38 logic unused_sigs;
39 unreachable assign unused_sigs = ^{attr_i.slew_rate,
40 attr_i.drive_strength[3:1],
41 attr_i.od_en,
42 attr_i.schmitt_en,
43 attr_i.keep_en,
44 scanmode_i,
45 pok_i};
46 //VCS coverage on
47 // pragma coverage on
48
49 // Input enable (active-high)
50 logic ie;
51 1/1 assign ie = ie_i & ~attr_i.input_disable;
Tests: T20 T21 T22
52
53 if (PadType == InputStd) begin : gen_input_only
54 //VCS coverage off
55 // pragma coverage off
56 logic unused_in_sigs;
57 assign unused_in_sigs = ^{out_i,
58 oe_i,
59 attr_i.virt_od_en,
60 attr_i.drive_strength};
61 //VCS coverage on
62 // pragma coverage on
63
64 assign in_raw_o = ie ? inout_io : 1'bz;
65 // input inversion
66 assign in_o = attr_i.invert ^ in_raw_o;
67
68 // pulls are not supported by verilator
69 `ifndef VERILATOR
70 // pullup / pulldown termination
71 assign (weak0, weak1) inout_io = attr_i.pull_en ? attr_i.pull_select : 1'bz;
72 `endif
73 end else if (PadType == BidirTol ||
74 PadType == DualBidirTol ||
75 PadType == BidirOd ||
76 PadType == BidirStd) begin : gen_bidir
77
78 1/1 assign in_raw_o = ie ? inout_io : 1'bz;
Tests: T6 T25 T35
79 // input inversion
80 1/1 assign in_o = attr_i.invert ^ in_raw_o;
Tests: T6 T25 T35
81
82 // virtual open drain emulation
83 logic oe, out;
84 1/1 assign out = out_i ^ attr_i.invert;
Tests: T6 T25 T8
85 1/1 assign oe = oe_i & ((attr_i.virt_od_en & ~out) | ~attr_i.virt_od_en);
Tests: T6 T25 T8
86
87 // drive strength attributes are not supported by verilator
88 `ifdef VERILATOR
89 assign inout_io = (oe) ? out : 1'bz;
90 `else
91 // different driver types
92 1/1 assign (strong0, strong1) inout_io = (oe && attr_i.drive_strength[0]) ? out : 1'bz;
Tests: T6 T25 T8
93 1/1 assign (pull0, pull1) inout_io = (oe && !attr_i.drive_strength[0]) ? out : 1'bz;
Tests: T6 T25 T8
94 // pullup / pulldown termination
95 1/1 assign (weak0, weak1) inout_io = attr_i.pull_en ? attr_i.pull_select : 1'bz;
Tests: T25 T47 T48
Cond Coverage for Instance : tb.dut.u_padring.gen_mio_pads[9].u_mio_pad.gen_generic.u_impl_generic
| Total | Covered | Percent |
|---|
| Conditions | 33 | 33 | 100.00 |
| Logical | 33 | 33 | 100.00 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 51
EXPRESSION (ie_i & ((~attr_i.input_disable)))
--1- ------------2------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Unreachable | |
| 1 | 0 | Covered | T20,T21,T22 |
| 1 | 1 | Covered | T1,T2,T3 |
LINE 78
EXPRESSION (ie ? inout_io : 1'bz)
-1
| -1- | Status | Tests |
|---|
| 0 | Covered | T20,T21,T22 |
| 1 | Covered | T1,T2,T3 |
LINE 80
EXPRESSION (attr_i.invert ^ in_raw_o)
------1------ ----2---
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T25,T35,T97 |
| 0 | 1 | Covered | T6,T25,T10 |
| 1 | 0 | Covered | T20,T21,T22 |
| 1 | 1 | Covered | T20,T21,T22 |
LINE 84
EXPRESSION (out_i ^ attr_i.invert)
--1-- ------2------
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T1,T2,T3 |
| 0 | 1 | Covered | T20,T21,T22 |
| 1 | 0 | Covered | T6,T25,T8 |
| 1 | 1 | Covered | T20,T21,T22 |
LINE 85
EXPRESSION (oe_i & ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en))))
--1- ---------------------------------2---------------------------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T20,T21,T22 |
| 1 | 1 | Covered | T6,T25,T10 |
LINE 85
SUB-EXPRESSION ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en)))
--------------------1------------------- -----------2----------
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T20,T21,T22 |
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T20,T21,T22 |
LINE 85
SUB-EXPRESSION (attr_i.virt_od_en & ((~gen_bidir.out)))
--------1-------- ---------2--------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T20,T21,T22 |
| 1 | 1 | Covered | T20,T21,T22 |
LINE 92
EXPRESSION ((gen_bidir.oe && attr_i.drive_strength[0]) ? gen_bidir.out : 1'bz)
---------------------1--------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T25,T20,T21 |
LINE 92
SUB-EXPRESSION (gen_bidir.oe && attr_i.drive_strength[0])
------1----- ------------2-----------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T25,T47,T48 |
| 1 | 0 | Covered | T6,T10,T69 |
| 1 | 1 | Covered | T25,T20,T21 |
LINE 93
EXPRESSION ((gen_bidir.oe && ((!attr_i.drive_strength[0]))) ? gen_bidir.out : 1'bz)
-----------------------1-----------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T6,T10,T69 |
LINE 93
SUB-EXPRESSION (gen_bidir.oe && ((!attr_i.drive_strength[0])))
------1----- --------------2--------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T25,T20,T21 |
| 1 | 1 | Covered | T6,T10,T69 |
LINE 95
EXPRESSION (attr_i.pull_en ? attr_i.pull_select : 1'bz)
-------1------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T25,T47,T48 |
Branch Coverage for Instance : tb.dut.u_padring.gen_mio_pads[9].u_mio_pad.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
| Branches |
|
8 |
8 |
100.00 |
| TERNARY |
78 |
2 |
2 |
100.00 |
| TERNARY |
92 |
2 |
2 |
100.00 |
| TERNARY |
93 |
2 |
2 |
100.00 |
| TERNARY |
95 |
2 |
2 |
100.00 |
78 assign in_raw_o = ie ? inout_io : 1'bz;
-1-
==>
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T3 |
| 0 |
Covered |
T20,T21,T22 |
92 assign (strong0, strong1) inout_io = (oe && attr_i.drive_strength[0]) ? out : 1'bz;
-1-
==>
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T25,T20,T21 |
| 0 |
Covered |
T1,T2,T3 |
93 assign (pull0, pull1) inout_io = (oe && !attr_i.drive_strength[0]) ? out : 1'bz;
-1-
==>
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T6,T10,T69 |
| 0 |
Covered |
T1,T2,T3 |
95 assign (weak0, weak1) inout_io = attr_i.pull_en ? attr_i.pull_select : 1'bz;
-1-
==>
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T25,T47,T48 |
| 0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_padring.gen_mio_pads[9].u_mio_pad.gen_generic.u_impl_generic
Assertion Details
| Name | Attempts | Real Successes | Failures | Incomplete |
|
AnalogNoScan_A |
1010 |
1010 |
0 |
0 |
AnalogNoScan_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
1010 |
1010 |
0 |
0 |
| T1 |
1 |
1 |
0 |
0 |
| T2 |
1 |
1 |
0 |
0 |
| T3 |
1 |
1 |
0 |
0 |
| T4 |
1 |
1 |
0 |
0 |
| T5 |
1 |
1 |
0 |
0 |
| T6 |
1 |
1 |
0 |
0 |
| T30 |
1 |
1 |
0 |
0 |
| T68 |
1 |
1 |
0 |
0 |
| T104 |
1 |
1 |
0 |
0 |
| T105 |
1 |
1 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_padring.gen_mio_pads[10].u_mio_pad.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 8 | 8 | 100.00 |
| CONT_ASSIGN | 39 | 0 | 0 | |
| CONT_ASSIGN | 51 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 78 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 80 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 84 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 85 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 92 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 93 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 95 | 1 | 1 | 100.00 |
38 logic unused_sigs;
39 unreachable assign unused_sigs = ^{attr_i.slew_rate,
40 attr_i.drive_strength[3:1],
41 attr_i.od_en,
42 attr_i.schmitt_en,
43 attr_i.keep_en,
44 scanmode_i,
45 pok_i};
46 //VCS coverage on
47 // pragma coverage on
48
49 // Input enable (active-high)
50 logic ie;
51 1/1 assign ie = ie_i & ~attr_i.input_disable;
Tests: T20 T21 T22
52
53 if (PadType == InputStd) begin : gen_input_only
54 //VCS coverage off
55 // pragma coverage off
56 logic unused_in_sigs;
57 assign unused_in_sigs = ^{out_i,
58 oe_i,
59 attr_i.virt_od_en,
60 attr_i.drive_strength};
61 //VCS coverage on
62 // pragma coverage on
63
64 assign in_raw_o = ie ? inout_io : 1'bz;
65 // input inversion
66 assign in_o = attr_i.invert ^ in_raw_o;
67
68 // pulls are not supported by verilator
69 `ifndef VERILATOR
70 // pullup / pulldown termination
71 assign (weak0, weak1) inout_io = attr_i.pull_en ? attr_i.pull_select : 1'bz;
72 `endif
73 end else if (PadType == BidirTol ||
74 PadType == DualBidirTol ||
75 PadType == BidirOd ||
76 PadType == BidirStd) begin : gen_bidir
77
78 1/1 assign in_raw_o = ie ? inout_io : 1'bz;
Tests: T6 T25 T8
79 // input inversion
80 1/1 assign in_o = attr_i.invert ^ in_raw_o;
Tests: T6 T25 T8
81
82 // virtual open drain emulation
83 logic oe, out;
84 1/1 assign out = out_i ^ attr_i.invert;
Tests: T6 T25 T10
85 1/1 assign oe = oe_i & ((attr_i.virt_od_en & ~out) | ~attr_i.virt_od_en);
Tests: T6 T25 T10
86
87 // drive strength attributes are not supported by verilator
88 `ifdef VERILATOR
89 assign inout_io = (oe) ? out : 1'bz;
90 `else
91 // different driver types
92 1/1 assign (strong0, strong1) inout_io = (oe && attr_i.drive_strength[0]) ? out : 1'bz;
Tests: T6 T25 T10
93 1/1 assign (pull0, pull1) inout_io = (oe && !attr_i.drive_strength[0]) ? out : 1'bz;
Tests: T6 T25 T10
94 // pullup / pulldown termination
95 1/1 assign (weak0, weak1) inout_io = attr_i.pull_en ? attr_i.pull_select : 1'bz;
Tests: T25 T8 T9
Cond Coverage for Instance : tb.dut.u_padring.gen_mio_pads[10].u_mio_pad.gen_generic.u_impl_generic
| Total | Covered | Percent |
|---|
| Conditions | 33 | 33 | 100.00 |
| Logical | 33 | 33 | 100.00 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 51
EXPRESSION (ie_i & ((~attr_i.input_disable)))
--1- ------------2------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Unreachable | |
| 1 | 0 | Covered | T20,T21,T22 |
| 1 | 1 | Covered | T1,T2,T3 |
LINE 78
EXPRESSION (ie ? inout_io : 1'bz)
-1
| -1- | Status | Tests |
|---|
| 0 | Covered | T20,T21,T22 |
| 1 | Covered | T1,T2,T3 |
LINE 80
EXPRESSION (attr_i.invert ^ in_raw_o)
------1------ ----2---
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T25,T35,T97 |
| 0 | 1 | Covered | T6,T25,T8 |
| 1 | 0 | Covered | T20,T21,T22 |
| 1 | 1 | Covered | T21,T22,T44 |
LINE 84
EXPRESSION (out_i ^ attr_i.invert)
--1-- ------2------
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T1,T2,T3 |
| 0 | 1 | Covered | T20,T21,T22 |
| 1 | 0 | Covered | T6,T25,T10 |
| 1 | 1 | Covered | T20,T21,T22 |
LINE 85
EXPRESSION (oe_i & ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en))))
--1- ---------------------------------2---------------------------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T20,T21,T22 |
| 1 | 1 | Covered | T6,T25,T10 |
LINE 85
SUB-EXPRESSION ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en)))
--------------------1------------------- -----------2----------
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T20,T21,T22 |
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T20,T21,T22 |
LINE 85
SUB-EXPRESSION (attr_i.virt_od_en & ((~gen_bidir.out)))
--------1-------- ---------2--------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T20,T21,T22 |
| 1 | 1 | Covered | T20,T21,T22 |
LINE 92
EXPRESSION ((gen_bidir.oe && attr_i.drive_strength[0]) ? gen_bidir.out : 1'bz)
---------------------1--------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T25,T20,T21 |
LINE 92
SUB-EXPRESSION (gen_bidir.oe && attr_i.drive_strength[0])
------1----- ------------2-----------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T25,T47,T48 |
| 1 | 0 | Covered | T6,T10,T19 |
| 1 | 1 | Covered | T25,T20,T21 |
LINE 93
EXPRESSION ((gen_bidir.oe && ((!attr_i.drive_strength[0]))) ? gen_bidir.out : 1'bz)
-----------------------1-----------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T6,T10,T19 |
LINE 93
SUB-EXPRESSION (gen_bidir.oe && ((!attr_i.drive_strength[0])))
------1----- --------------2--------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T25,T20,T21 |
| 1 | 1 | Covered | T6,T10,T19 |
LINE 95
EXPRESSION (attr_i.pull_en ? attr_i.pull_select : 1'bz)
-------1------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T25,T8,T9 |
Branch Coverage for Instance : tb.dut.u_padring.gen_mio_pads[10].u_mio_pad.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
| Branches |
|
8 |
8 |
100.00 |
| TERNARY |
78 |
2 |
2 |
100.00 |
| TERNARY |
92 |
2 |
2 |
100.00 |
| TERNARY |
93 |
2 |
2 |
100.00 |
| TERNARY |
95 |
2 |
2 |
100.00 |
78 assign in_raw_o = ie ? inout_io : 1'bz;
-1-
==>
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T3 |
| 0 |
Covered |
T20,T21,T22 |
92 assign (strong0, strong1) inout_io = (oe && attr_i.drive_strength[0]) ? out : 1'bz;
-1-
==>
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T25,T20,T21 |
| 0 |
Covered |
T1,T2,T3 |
93 assign (pull0, pull1) inout_io = (oe && !attr_i.drive_strength[0]) ? out : 1'bz;
-1-
==>
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T6,T10,T19 |
| 0 |
Covered |
T1,T2,T3 |
95 assign (weak0, weak1) inout_io = attr_i.pull_en ? attr_i.pull_select : 1'bz;
-1-
==>
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T25,T8,T9 |
| 0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_padring.gen_mio_pads[10].u_mio_pad.gen_generic.u_impl_generic
Assertion Details
| Name | Attempts | Real Successes | Failures | Incomplete |
|
AnalogNoScan_A |
1010 |
1010 |
0 |
0 |
AnalogNoScan_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
1010 |
1010 |
0 |
0 |
| T1 |
1 |
1 |
0 |
0 |
| T2 |
1 |
1 |
0 |
0 |
| T3 |
1 |
1 |
0 |
0 |
| T4 |
1 |
1 |
0 |
0 |
| T5 |
1 |
1 |
0 |
0 |
| T6 |
1 |
1 |
0 |
0 |
| T30 |
1 |
1 |
0 |
0 |
| T68 |
1 |
1 |
0 |
0 |
| T104 |
1 |
1 |
0 |
0 |
| T105 |
1 |
1 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_padring.gen_mio_pads[11].u_mio_pad.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 8 | 8 | 100.00 |
| CONT_ASSIGN | 39 | 0 | 0 | |
| CONT_ASSIGN | 51 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 78 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 80 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 84 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 85 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 92 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 93 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 95 | 1 | 1 | 100.00 |
38 logic unused_sigs;
39 unreachable assign unused_sigs = ^{attr_i.slew_rate,
40 attr_i.drive_strength[3:1],
41 attr_i.od_en,
42 attr_i.schmitt_en,
43 attr_i.keep_en,
44 scanmode_i,
45 pok_i};
46 //VCS coverage on
47 // pragma coverage on
48
49 // Input enable (active-high)
50 logic ie;
51 1/1 assign ie = ie_i & ~attr_i.input_disable;
Tests: T20 T21 T22
52
53 if (PadType == InputStd) begin : gen_input_only
54 //VCS coverage off
55 // pragma coverage off
56 logic unused_in_sigs;
57 assign unused_in_sigs = ^{out_i,
58 oe_i,
59 attr_i.virt_od_en,
60 attr_i.drive_strength};
61 //VCS coverage on
62 // pragma coverage on
63
64 assign in_raw_o = ie ? inout_io : 1'bz;
65 // input inversion
66 assign in_o = attr_i.invert ^ in_raw_o;
67
68 // pulls are not supported by verilator
69 `ifndef VERILATOR
70 // pullup / pulldown termination
71 assign (weak0, weak1) inout_io = attr_i.pull_en ? attr_i.pull_select : 1'bz;
72 `endif
73 end else if (PadType == BidirTol ||
74 PadType == DualBidirTol ||
75 PadType == BidirOd ||
76 PadType == BidirStd) begin : gen_bidir
77
78 1/1 assign in_raw_o = ie ? inout_io : 1'bz;
Tests: T5 T6 T35
79 // input inversion
80 1/1 assign in_o = attr_i.invert ^ in_raw_o;
Tests: T5 T6 T35
81
82 // virtual open drain emulation
83 logic oe, out;
84 1/1 assign out = out_i ^ attr_i.invert;
Tests: T10 T19 T69
85 1/1 assign oe = oe_i & ((attr_i.virt_od_en & ~out) | ~attr_i.virt_od_en);
Tests: T10 T19 T69
86
87 // drive strength attributes are not supported by verilator
88 `ifdef VERILATOR
89 assign inout_io = (oe) ? out : 1'bz;
90 `else
91 // different driver types
92 1/1 assign (strong0, strong1) inout_io = (oe && attr_i.drive_strength[0]) ? out : 1'bz;
Tests: T10 T19 T69
93 1/1 assign (pull0, pull1) inout_io = (oe && !attr_i.drive_strength[0]) ? out : 1'bz;
Tests: T10 T19 T69
94 // pullup / pulldown termination
95 1/1 assign (weak0, weak1) inout_io = attr_i.pull_en ? attr_i.pull_select : 1'bz;
Tests: T20 T21 T22
Cond Coverage for Instance : tb.dut.u_padring.gen_mio_pads[11].u_mio_pad.gen_generic.u_impl_generic
| Total | Covered | Percent |
|---|
| Conditions | 33 | 33 | 100.00 |
| Logical | 33 | 33 | 100.00 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 51
EXPRESSION (ie_i & ((~attr_i.input_disable)))
--1- ------------2------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Unreachable | |
| 1 | 0 | Covered | T20,T21,T22 |
| 1 | 1 | Covered | T1,T2,T3 |
LINE 78
EXPRESSION (ie ? inout_io : 1'bz)
-1
| -1- | Status | Tests |
|---|
| 0 | Covered | T20,T21,T22 |
| 1 | Covered | T1,T2,T3 |
LINE 80
EXPRESSION (attr_i.invert ^ in_raw_o)
------1------ ----2---
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T5,T6,T35 |
| 0 | 1 | Covered | T6,T10,T19 |
| 1 | 0 | Covered | T20,T21,T22 |
| 1 | 1 | Covered | T20,T21,T22 |
LINE 84
EXPRESSION (out_i ^ attr_i.invert)
--1-- ------2------
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T1,T2,T3 |
| 0 | 1 | Covered | T20,T21,T22 |
| 1 | 0 | Covered | T10,T19,T69 |
| 1 | 1 | Covered | T20,T21,T22 |
LINE 85
EXPRESSION (oe_i & ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en))))
--1- ---------------------------------2---------------------------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T20,T21,T22 |
| 1 | 1 | Covered | T10,T19,T69 |
LINE 85
SUB-EXPRESSION ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en)))
--------------------1------------------- -----------2----------
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T20,T21,T22 |
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T20,T21,T22 |
LINE 85
SUB-EXPRESSION (attr_i.virt_od_en & ((~gen_bidir.out)))
--------1-------- ---------2--------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T20,T21,T22 |
| 1 | 1 | Covered | T20,T21,T22 |
LINE 92
EXPRESSION ((gen_bidir.oe && attr_i.drive_strength[0]) ? gen_bidir.out : 1'bz)
---------------------1--------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T20,T21,T22 |
LINE 92
SUB-EXPRESSION (gen_bidir.oe && attr_i.drive_strength[0])
------1----- ------------2-----------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T20,T21,T22 |
| 1 | 0 | Covered | T10,T19,T69 |
| 1 | 1 | Covered | T20,T21,T22 |
LINE 93
EXPRESSION ((gen_bidir.oe && ((!attr_i.drive_strength[0]))) ? gen_bidir.out : 1'bz)
-----------------------1-----------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T10,T19,T69 |
LINE 93
SUB-EXPRESSION (gen_bidir.oe && ((!attr_i.drive_strength[0])))
------1----- --------------2--------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T20,T21,T22 |
| 1 | 1 | Covered | T10,T19,T69 |
LINE 95
EXPRESSION (attr_i.pull_en ? attr_i.pull_select : 1'bz)
-------1------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T20,T21,T22 |
Branch Coverage for Instance : tb.dut.u_padring.gen_mio_pads[11].u_mio_pad.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
| Branches |
|
8 |
8 |
100.00 |
| TERNARY |
78 |
2 |
2 |
100.00 |
| TERNARY |
92 |
2 |
2 |
100.00 |
| TERNARY |
93 |
2 |
2 |
100.00 |
| TERNARY |
95 |
2 |
2 |
100.00 |
78 assign in_raw_o = ie ? inout_io : 1'bz;
-1-
==>
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T3 |
| 0 |
Covered |
T20,T21,T22 |
92 assign (strong0, strong1) inout_io = (oe && attr_i.drive_strength[0]) ? out : 1'bz;
-1-
==>
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T20,T21,T22 |
| 0 |
Covered |
T1,T2,T3 |
93 assign (pull0, pull1) inout_io = (oe && !attr_i.drive_strength[0]) ? out : 1'bz;
-1-
==>
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T10,T19,T69 |
| 0 |
Covered |
T1,T2,T3 |
95 assign (weak0, weak1) inout_io = attr_i.pull_en ? attr_i.pull_select : 1'bz;
-1-
==>
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T20,T21,T22 |
| 0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_padring.gen_mio_pads[11].u_mio_pad.gen_generic.u_impl_generic
Assertion Details
| Name | Attempts | Real Successes | Failures | Incomplete |
|
AnalogNoScan_A |
1010 |
1010 |
0 |
0 |
AnalogNoScan_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
1010 |
1010 |
0 |
0 |
| T1 |
1 |
1 |
0 |
0 |
| T2 |
1 |
1 |
0 |
0 |
| T3 |
1 |
1 |
0 |
0 |
| T4 |
1 |
1 |
0 |
0 |
| T5 |
1 |
1 |
0 |
0 |
| T6 |
1 |
1 |
0 |
0 |
| T30 |
1 |
1 |
0 |
0 |
| T68 |
1 |
1 |
0 |
0 |
| T104 |
1 |
1 |
0 |
0 |
| T105 |
1 |
1 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_padring.gen_mio_pads[12].u_mio_pad.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 8 | 8 | 100.00 |
| CONT_ASSIGN | 39 | 0 | 0 | |
| CONT_ASSIGN | 51 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 78 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 80 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 84 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 85 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 92 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 93 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 95 | 1 | 1 | 100.00 |
38 logic unused_sigs;
39 unreachable assign unused_sigs = ^{attr_i.slew_rate,
40 attr_i.drive_strength[3:1],
41 attr_i.od_en,
42 attr_i.schmitt_en,
43 attr_i.keep_en,
44 scanmode_i,
45 pok_i};
46 //VCS coverage on
47 // pragma coverage on
48
49 // Input enable (active-high)
50 logic ie;
51 1/1 assign ie = ie_i & ~attr_i.input_disable;
Tests: T20 T21 T22
52
53 if (PadType == InputStd) begin : gen_input_only
54 //VCS coverage off
55 // pragma coverage off
56 logic unused_in_sigs;
57 assign unused_in_sigs = ^{out_i,
58 oe_i,
59 attr_i.virt_od_en,
60 attr_i.drive_strength};
61 //VCS coverage on
62 // pragma coverage on
63
64 assign in_raw_o = ie ? inout_io : 1'bz;
65 // input inversion
66 assign in_o = attr_i.invert ^ in_raw_o;
67
68 // pulls are not supported by verilator
69 `ifndef VERILATOR
70 // pullup / pulldown termination
71 assign (weak0, weak1) inout_io = attr_i.pull_en ? attr_i.pull_select : 1'bz;
72 `endif
73 end else if (PadType == BidirTol ||
74 PadType == DualBidirTol ||
75 PadType == BidirOd ||
76 PadType == BidirStd) begin : gen_bidir
77
78 1/1 assign in_raw_o = ie ? inout_io : 1'bz;
Tests: T6 T25 T8
79 // input inversion
80 1/1 assign in_o = attr_i.invert ^ in_raw_o;
Tests: T6 T25 T8
81
82 // virtual open drain emulation
83 logic oe, out;
84 1/1 assign out = out_i ^ attr_i.invert;
Tests: T25 T20 T21
85 1/1 assign oe = oe_i & ((attr_i.virt_od_en & ~out) | ~attr_i.virt_od_en);
Tests: T6 T25 T10
86
87 // drive strength attributes are not supported by verilator
88 `ifdef VERILATOR
89 assign inout_io = (oe) ? out : 1'bz;
90 `else
91 // different driver types
92 1/1 assign (strong0, strong1) inout_io = (oe && attr_i.drive_strength[0]) ? out : 1'bz;
Tests: T6 T25 T10
93 1/1 assign (pull0, pull1) inout_io = (oe && !attr_i.drive_strength[0]) ? out : 1'bz;
Tests: T6 T25 T10
94 // pullup / pulldown termination
95 1/1 assign (weak0, weak1) inout_io = attr_i.pull_en ? attr_i.pull_select : 1'bz;
Tests: T25 T8 T9
Cond Coverage for Instance : tb.dut.u_padring.gen_mio_pads[12].u_mio_pad.gen_generic.u_impl_generic
| Total | Covered | Percent |
|---|
| Conditions | 33 | 33 | 100.00 |
| Logical | 33 | 33 | 100.00 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 51
EXPRESSION (ie_i & ((~attr_i.input_disable)))
--1- ------------2------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Unreachable | |
| 1 | 0 | Covered | T20,T21,T22 |
| 1 | 1 | Covered | T1,T2,T3 |
LINE 78
EXPRESSION (ie ? inout_io : 1'bz)
-1
| -1- | Status | Tests |
|---|
| 0 | Covered | T20,T21,T22 |
| 1 | Covered | T1,T2,T3 |
LINE 80
EXPRESSION (attr_i.invert ^ in_raw_o)
------1------ ----2---
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T6,T25,T12 |
| 0 | 1 | Covered | T25,T8,T9 |
| 1 | 0 | Covered | T20,T21,T22 |
| 1 | 1 | Covered | T20,T21,T22 |
LINE 84
EXPRESSION (out_i ^ attr_i.invert)
--1-- ------2------
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T1,T2,T3 |
| 0 | 1 | Covered | T20,T21,T22 |
| 1 | 0 | Covered | T25,T20,T21 |
| 1 | 1 | Covered | T20,T21,T22 |
LINE 85
EXPRESSION (oe_i & ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en))))
--1- ---------------------------------2---------------------------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T20,T21,T22 |
| 1 | 1 | Covered | T6,T25,T10 |
LINE 85
SUB-EXPRESSION ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en)))
--------------------1------------------- -----------2----------
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T20,T21,T22 |
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T20,T21,T22 |
LINE 85
SUB-EXPRESSION (attr_i.virt_od_en & ((~gen_bidir.out)))
--------1-------- ---------2--------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T20,T21,T22 |
| 1 | 1 | Covered | T20,T21,T22 |
LINE 92
EXPRESSION ((gen_bidir.oe && attr_i.drive_strength[0]) ? gen_bidir.out : 1'bz)
---------------------1--------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T25,T20,T21 |
LINE 92
SUB-EXPRESSION (gen_bidir.oe && attr_i.drive_strength[0])
------1----- ------------2-----------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T25,T47,T48 |
| 1 | 0 | Covered | T6,T10,T69 |
| 1 | 1 | Covered | T25,T20,T21 |
LINE 93
EXPRESSION ((gen_bidir.oe && ((!attr_i.drive_strength[0]))) ? gen_bidir.out : 1'bz)
-----------------------1-----------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T6,T10,T69 |
LINE 93
SUB-EXPRESSION (gen_bidir.oe && ((!attr_i.drive_strength[0])))
------1----- --------------2--------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T25,T20,T21 |
| 1 | 1 | Covered | T6,T10,T69 |
LINE 95
EXPRESSION (attr_i.pull_en ? attr_i.pull_select : 1'bz)
-------1------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T25,T8,T9 |
Branch Coverage for Instance : tb.dut.u_padring.gen_mio_pads[12].u_mio_pad.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
| Branches |
|
8 |
8 |
100.00 |
| TERNARY |
78 |
2 |
2 |
100.00 |
| TERNARY |
92 |
2 |
2 |
100.00 |
| TERNARY |
93 |
2 |
2 |
100.00 |
| TERNARY |
95 |
2 |
2 |
100.00 |
78 assign in_raw_o = ie ? inout_io : 1'bz;
-1-
==>
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T3 |
| 0 |
Covered |
T20,T21,T22 |
92 assign (strong0, strong1) inout_io = (oe && attr_i.drive_strength[0]) ? out : 1'bz;
-1-
==>
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T25,T20,T21 |
| 0 |
Covered |
T1,T2,T3 |
93 assign (pull0, pull1) inout_io = (oe && !attr_i.drive_strength[0]) ? out : 1'bz;
-1-
==>
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T6,T10,T69 |
| 0 |
Covered |
T1,T2,T3 |
95 assign (weak0, weak1) inout_io = attr_i.pull_en ? attr_i.pull_select : 1'bz;
-1-
==>
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T25,T8,T9 |
| 0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_padring.gen_mio_pads[12].u_mio_pad.gen_generic.u_impl_generic
Assertion Details
| Name | Attempts | Real Successes | Failures | Incomplete |
|
AnalogNoScan_A |
1010 |
1010 |
0 |
0 |
AnalogNoScan_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
1010 |
1010 |
0 |
0 |
| T1 |
1 |
1 |
0 |
0 |
| T2 |
1 |
1 |
0 |
0 |
| T3 |
1 |
1 |
0 |
0 |
| T4 |
1 |
1 |
0 |
0 |
| T5 |
1 |
1 |
0 |
0 |
| T6 |
1 |
1 |
0 |
0 |
| T30 |
1 |
1 |
0 |
0 |
| T68 |
1 |
1 |
0 |
0 |
| T104 |
1 |
1 |
0 |
0 |
| T105 |
1 |
1 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_padring.gen_mio_pads[13].u_mio_pad.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 8 | 8 | 100.00 |
| CONT_ASSIGN | 39 | 0 | 0 | |
| CONT_ASSIGN | 51 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 78 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 80 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 84 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 85 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 92 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 93 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 95 | 1 | 1 | 100.00 |
38 logic unused_sigs;
39 unreachable assign unused_sigs = ^{attr_i.slew_rate,
40 attr_i.drive_strength[3:1],
41 attr_i.od_en,
42 attr_i.schmitt_en,
43 attr_i.keep_en,
44 scanmode_i,
45 pok_i};
46 //VCS coverage on
47 // pragma coverage on
48
49 // Input enable (active-high)
50 logic ie;
51 1/1 assign ie = ie_i & ~attr_i.input_disable;
Tests: T20 T21 T22
52
53 if (PadType == InputStd) begin : gen_input_only
54 //VCS coverage off
55 // pragma coverage off
56 logic unused_in_sigs;
57 assign unused_in_sigs = ^{out_i,
58 oe_i,
59 attr_i.virt_od_en,
60 attr_i.drive_strength};
61 //VCS coverage on
62 // pragma coverage on
63
64 assign in_raw_o = ie ? inout_io : 1'bz;
65 // input inversion
66 assign in_o = attr_i.invert ^ in_raw_o;
67
68 // pulls are not supported by verilator
69 `ifndef VERILATOR
70 // pullup / pulldown termination
71 assign (weak0, weak1) inout_io = attr_i.pull_en ? attr_i.pull_select : 1'bz;
72 `endif
73 end else if (PadType == BidirTol ||
74 PadType == DualBidirTol ||
75 PadType == BidirOd ||
76 PadType == BidirStd) begin : gen_bidir
77
78 1/1 assign in_raw_o = ie ? inout_io : 1'bz;
Tests: T5 T6 T25
79 // input inversion
80 1/1 assign in_o = attr_i.invert ^ in_raw_o;
Tests: T5 T6 T25
81
82 // virtual open drain emulation
83 logic oe, out;
84 1/1 assign out = out_i ^ attr_i.invert;
Tests: T10 T19 T69
85 1/1 assign oe = oe_i & ((attr_i.virt_od_en & ~out) | ~attr_i.virt_od_en);
Tests: T6 T10 T19
86
87 // drive strength attributes are not supported by verilator
88 `ifdef VERILATOR
89 assign inout_io = (oe) ? out : 1'bz;
90 `else
91 // different driver types
92 1/1 assign (strong0, strong1) inout_io = (oe && attr_i.drive_strength[0]) ? out : 1'bz;
Tests: T6 T25 T10
93 1/1 assign (pull0, pull1) inout_io = (oe && !attr_i.drive_strength[0]) ? out : 1'bz;
Tests: T6 T25 T10
94 // pullup / pulldown termination
95 1/1 assign (weak0, weak1) inout_io = attr_i.pull_en ? attr_i.pull_select : 1'bz;
Tests: T25 T10 T47
Cond Coverage for Instance : tb.dut.u_padring.gen_mio_pads[13].u_mio_pad.gen_generic.u_impl_generic
| Total | Covered | Percent |
|---|
| Conditions | 33 | 33 | 100.00 |
| Logical | 33 | 33 | 100.00 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 51
EXPRESSION (ie_i & ((~attr_i.input_disable)))
--1- ------------2------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Unreachable | |
| 1 | 0 | Covered | T20,T21,T22 |
| 1 | 1 | Covered | T1,T2,T3 |
LINE 78
EXPRESSION (ie ? inout_io : 1'bz)
-1
| -1- | Status | Tests |
|---|
| 0 | Covered | T20,T21,T22 |
| 1 | Covered | T1,T2,T3 |
LINE 80
EXPRESSION (attr_i.invert ^ in_raw_o)
------1------ ----2---
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T5,T6,T25 |
| 0 | 1 | Covered | T25,T28,T132 |
| 1 | 0 | Covered | T20,T21,T22 |
| 1 | 1 | Covered | T20,T21,T22 |
LINE 84
EXPRESSION (out_i ^ attr_i.invert)
--1-- ------2------
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T1,T2,T3 |
| 0 | 1 | Covered | T20,T21,T22 |
| 1 | 0 | Covered | T10,T19,T69 |
| 1 | 1 | Covered | T21,T22,T44 |
LINE 85
EXPRESSION (oe_i & ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en))))
--1- ---------------------------------2---------------------------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T20,T21,T22 |
| 1 | 1 | Covered | T6,T10,T19 |
LINE 85
SUB-EXPRESSION ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en)))
--------------------1------------------- -----------2----------
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T20,T21,T22 |
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T20,T21,T22 |
LINE 85
SUB-EXPRESSION (attr_i.virt_od_en & ((~gen_bidir.out)))
--------1-------- ---------2--------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T20,T21,T22 |
| 1 | 1 | Covered | T20,T21,T22 |
LINE 92
EXPRESSION ((gen_bidir.oe && attr_i.drive_strength[0]) ? gen_bidir.out : 1'bz)
---------------------1--------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T20,T21,T22 |
LINE 92
SUB-EXPRESSION (gen_bidir.oe && attr_i.drive_strength[0])
------1----- ------------2-----------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T25,T47,T48 |
| 1 | 0 | Covered | T6,T10,T19 |
| 1 | 1 | Covered | T20,T21,T22 |
LINE 93
EXPRESSION ((gen_bidir.oe && ((!attr_i.drive_strength[0]))) ? gen_bidir.out : 1'bz)
-----------------------1-----------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T6,T10,T19 |
LINE 93
SUB-EXPRESSION (gen_bidir.oe && ((!attr_i.drive_strength[0])))
------1----- --------------2--------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T20,T21,T22 |
| 1 | 1 | Covered | T6,T10,T19 |
LINE 95
EXPRESSION (attr_i.pull_en ? attr_i.pull_select : 1'bz)
-------1------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T25,T10,T47 |
Branch Coverage for Instance : tb.dut.u_padring.gen_mio_pads[13].u_mio_pad.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
| Branches |
|
8 |
8 |
100.00 |
| TERNARY |
78 |
2 |
2 |
100.00 |
| TERNARY |
92 |
2 |
2 |
100.00 |
| TERNARY |
93 |
2 |
2 |
100.00 |
| TERNARY |
95 |
2 |
2 |
100.00 |
78 assign in_raw_o = ie ? inout_io : 1'bz;
-1-
==>
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T3 |
| 0 |
Covered |
T20,T21,T22 |
92 assign (strong0, strong1) inout_io = (oe && attr_i.drive_strength[0]) ? out : 1'bz;
-1-
==>
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T20,T21,T22 |
| 0 |
Covered |
T1,T2,T3 |
93 assign (pull0, pull1) inout_io = (oe && !attr_i.drive_strength[0]) ? out : 1'bz;
-1-
==>
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T6,T10,T19 |
| 0 |
Covered |
T1,T2,T3 |
95 assign (weak0, weak1) inout_io = attr_i.pull_en ? attr_i.pull_select : 1'bz;
-1-
==>
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T25,T10,T47 |
| 0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_padring.gen_mio_pads[13].u_mio_pad.gen_generic.u_impl_generic
Assertion Details
| Name | Attempts | Real Successes | Failures | Incomplete |
|
AnalogNoScan_A |
1010 |
1010 |
0 |
0 |
AnalogNoScan_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
1010 |
1010 |
0 |
0 |
| T1 |
1 |
1 |
0 |
0 |
| T2 |
1 |
1 |
0 |
0 |
| T3 |
1 |
1 |
0 |
0 |
| T4 |
1 |
1 |
0 |
0 |
| T5 |
1 |
1 |
0 |
0 |
| T6 |
1 |
1 |
0 |
0 |
| T30 |
1 |
1 |
0 |
0 |
| T68 |
1 |
1 |
0 |
0 |
| T104 |
1 |
1 |
0 |
0 |
| T105 |
1 |
1 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_padring.gen_mio_pads[14].u_mio_pad.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 8 | 8 | 100.00 |
| CONT_ASSIGN | 39 | 0 | 0 | |
| CONT_ASSIGN | 51 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 78 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 80 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 84 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 85 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 92 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 93 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 95 | 1 | 1 | 100.00 |
38 logic unused_sigs;
39 unreachable assign unused_sigs = ^{attr_i.slew_rate,
40 attr_i.drive_strength[3:1],
41 attr_i.od_en,
42 attr_i.schmitt_en,
43 attr_i.keep_en,
44 scanmode_i,
45 pok_i};
46 //VCS coverage on
47 // pragma coverage on
48
49 // Input enable (active-high)
50 logic ie;
51 1/1 assign ie = ie_i & ~attr_i.input_disable;
Tests: T20 T21 T22
52
53 if (PadType == InputStd) begin : gen_input_only
54 //VCS coverage off
55 // pragma coverage off
56 logic unused_in_sigs;
57 assign unused_in_sigs = ^{out_i,
58 oe_i,
59 attr_i.virt_od_en,
60 attr_i.drive_strength};
61 //VCS coverage on
62 // pragma coverage on
63
64 assign in_raw_o = ie ? inout_io : 1'bz;
65 // input inversion
66 assign in_o = attr_i.invert ^ in_raw_o;
67
68 // pulls are not supported by verilator
69 `ifndef VERILATOR
70 // pullup / pulldown termination
71 assign (weak0, weak1) inout_io = attr_i.pull_en ? attr_i.pull_select : 1'bz;
72 `endif
73 end else if (PadType == BidirTol ||
74 PadType == DualBidirTol ||
75 PadType == BidirOd ||
76 PadType == BidirStd) begin : gen_bidir
77
78 1/1 assign in_raw_o = ie ? inout_io : 1'bz;
Tests: T1 T2 T3
79 // input inversion
80 1/1 assign in_o = attr_i.invert ^ in_raw_o;
Tests: T1 T2 T3
81
82 // virtual open drain emulation
83 logic oe, out;
84 1/1 assign out = out_i ^ attr_i.invert;
Tests: T1 T2 T3
85 1/1 assign oe = oe_i & ((attr_i.virt_od_en & ~out) | ~attr_i.virt_od_en);
Tests: T1 T2 T3
86
87 // drive strength attributes are not supported by verilator
88 `ifdef VERILATOR
89 assign inout_io = (oe) ? out : 1'bz;
90 `else
91 // different driver types
92 1/1 assign (strong0, strong1) inout_io = (oe && attr_i.drive_strength[0]) ? out : 1'bz;
Tests: T1 T2 T3
93 1/1 assign (pull0, pull1) inout_io = (oe && !attr_i.drive_strength[0]) ? out : 1'bz;
Tests: T1 T2 T3
94 // pullup / pulldown termination
95 1/1 assign (weak0, weak1) inout_io = attr_i.pull_en ? attr_i.pull_select : 1'bz;
Tests: T25 T10 T47
Cond Coverage for Instance : tb.dut.u_padring.gen_mio_pads[14].u_mio_pad.gen_generic.u_impl_generic
| Total | Covered | Percent |
|---|
| Conditions | 33 | 33 | 100.00 |
| Logical | 33 | 33 | 100.00 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 51
EXPRESSION (ie_i & ((~attr_i.input_disable)))
--1- ------------2------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Unreachable | |
| 1 | 0 | Covered | T20,T21,T22 |
| 1 | 1 | Covered | T1,T2,T3 |
LINE 78
EXPRESSION (ie ? inout_io : 1'bz)
-1
| -1- | Status | Tests |
|---|
| 0 | Covered | T20,T21,T22 |
| 1 | Covered | T1,T2,T3 |
LINE 80
EXPRESSION (attr_i.invert ^ in_raw_o)
------1------ ----2---
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T28,T132,T35 |
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T20,T21,T22 |
| 1 | 1 | Covered | T20,T21,T22 |
LINE 84
EXPRESSION (out_i ^ attr_i.invert)
--1-- ------2------
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T1,T2,T3 |
| 0 | 1 | Covered | T20,T21,T22 |
| 1 | 0 | Covered | T1,T2,T3 |
| 1 | 1 | Covered | T21,T22,T44 |
LINE 85
EXPRESSION (oe_i & ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en))))
--1- ---------------------------------2---------------------------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T20,T21,T22 |
| 1 | 1 | Covered | T1,T2,T3 |
LINE 85
SUB-EXPRESSION ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en)))
--------------------1------------------- -----------2----------
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T20,T21,T22 |
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T20,T21,T22 |
LINE 85
SUB-EXPRESSION (attr_i.virt_od_en & ((~gen_bidir.out)))
--------1-------- ---------2--------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T20,T21,T22 |
| 1 | 1 | Covered | T20,T21,T22 |
LINE 92
EXPRESSION ((gen_bidir.oe && attr_i.drive_strength[0]) ? gen_bidir.out : 1'bz)
---------------------1--------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T25,T47,T48 |
LINE 92
SUB-EXPRESSION (gen_bidir.oe && attr_i.drive_strength[0])
------1----- ------------2-----------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T25,T47,T48 |
| 1 | 0 | Covered | T1,T2,T3 |
| 1 | 1 | Covered | T25,T47,T48 |
LINE 93
EXPRESSION ((gen_bidir.oe && ((!attr_i.drive_strength[0]))) ? gen_bidir.out : 1'bz)
-----------------------1-----------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 93
SUB-EXPRESSION (gen_bidir.oe && ((!attr_i.drive_strength[0])))
------1----- --------------2--------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T25,T47,T48 |
| 1 | 1 | Covered | T1,T2,T3 |
LINE 95
EXPRESSION (attr_i.pull_en ? attr_i.pull_select : 1'bz)
-------1------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T25,T10,T47 |
Branch Coverage for Instance : tb.dut.u_padring.gen_mio_pads[14].u_mio_pad.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
| Branches |
|
8 |
8 |
100.00 |
| TERNARY |
78 |
2 |
2 |
100.00 |
| TERNARY |
92 |
2 |
2 |
100.00 |
| TERNARY |
93 |
2 |
2 |
100.00 |
| TERNARY |
95 |
2 |
2 |
100.00 |
78 assign in_raw_o = ie ? inout_io : 1'bz;
-1-
==>
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T3 |
| 0 |
Covered |
T20,T21,T22 |
92 assign (strong0, strong1) inout_io = (oe && attr_i.drive_strength[0]) ? out : 1'bz;
-1-
==>
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T25,T47,T48 |
| 0 |
Covered |
T1,T2,T3 |
93 assign (pull0, pull1) inout_io = (oe && !attr_i.drive_strength[0]) ? out : 1'bz;
-1-
==>
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T3 |
| 0 |
Covered |
T1,T2,T3 |
95 assign (weak0, weak1) inout_io = attr_i.pull_en ? attr_i.pull_select : 1'bz;
-1-
==>
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T25,T10,T47 |
| 0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_padring.gen_mio_pads[14].u_mio_pad.gen_generic.u_impl_generic
Assertion Details
| Name | Attempts | Real Successes | Failures | Incomplete |
|
AnalogNoScan_A |
1010 |
1010 |
0 |
0 |
AnalogNoScan_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
1010 |
1010 |
0 |
0 |
| T1 |
1 |
1 |
0 |
0 |
| T2 |
1 |
1 |
0 |
0 |
| T3 |
1 |
1 |
0 |
0 |
| T4 |
1 |
1 |
0 |
0 |
| T5 |
1 |
1 |
0 |
0 |
| T6 |
1 |
1 |
0 |
0 |
| T30 |
1 |
1 |
0 |
0 |
| T68 |
1 |
1 |
0 |
0 |
| T104 |
1 |
1 |
0 |
0 |
| T105 |
1 |
1 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_padring.gen_mio_pads[15].u_mio_pad.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 8 | 8 | 100.00 |
| CONT_ASSIGN | 39 | 0 | 0 | |
| CONT_ASSIGN | 51 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 78 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 80 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 84 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 85 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 92 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 93 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 95 | 1 | 1 | 100.00 |
38 logic unused_sigs;
39 unreachable assign unused_sigs = ^{attr_i.slew_rate,
40 attr_i.drive_strength[3:1],
41 attr_i.od_en,
42 attr_i.schmitt_en,
43 attr_i.keep_en,
44 scanmode_i,
45 pok_i};
46 //VCS coverage on
47 // pragma coverage on
48
49 // Input enable (active-high)
50 logic ie;
51 1/1 assign ie = ie_i & ~attr_i.input_disable;
Tests: T20 T21 T22
52
53 if (PadType == InputStd) begin : gen_input_only
54 //VCS coverage off
55 // pragma coverage off
56 logic unused_in_sigs;
57 assign unused_in_sigs = ^{out_i,
58 oe_i,
59 attr_i.virt_od_en,
60 attr_i.drive_strength};
61 //VCS coverage on
62 // pragma coverage on
63
64 assign in_raw_o = ie ? inout_io : 1'bz;
65 // input inversion
66 assign in_o = attr_i.invert ^ in_raw_o;
67
68 // pulls are not supported by verilator
69 `ifndef VERILATOR
70 // pullup / pulldown termination
71 assign (weak0, weak1) inout_io = attr_i.pull_en ? attr_i.pull_select : 1'bz;
72 `endif
73 end else if (PadType == BidirTol ||
74 PadType == DualBidirTol ||
75 PadType == BidirOd ||
76 PadType == BidirStd) begin : gen_bidir
77
78 1/1 assign in_raw_o = ie ? inout_io : 1'bz;
Tests: T6 T25 T27
79 // input inversion
80 1/1 assign in_o = attr_i.invert ^ in_raw_o;
Tests: T6 T25 T27
81
82 // virtual open drain emulation
83 logic oe, out;
84 1/1 assign out = out_i ^ attr_i.invert;
Tests: T27 T10 T39
85 1/1 assign oe = oe_i & ((attr_i.virt_od_en & ~out) | ~attr_i.virt_od_en);
Tests: T6 T27 T10
86
87 // drive strength attributes are not supported by verilator
88 `ifdef VERILATOR
89 assign inout_io = (oe) ? out : 1'bz;
90 `else
91 // different driver types
92 1/1 assign (strong0, strong1) inout_io = (oe && attr_i.drive_strength[0]) ? out : 1'bz;
Tests: T6 T25 T27
93 1/1 assign (pull0, pull1) inout_io = (oe && !attr_i.drive_strength[0]) ? out : 1'bz;
Tests: T6 T25 T27
94 // pullup / pulldown termination
95 1/1 assign (weak0, weak1) inout_io = attr_i.pull_en ? attr_i.pull_select : 1'bz;
Tests: T25 T10 T47
Cond Coverage for Instance : tb.dut.u_padring.gen_mio_pads[15].u_mio_pad.gen_generic.u_impl_generic
| Total | Covered | Percent |
|---|
| Conditions | 33 | 33 | 100.00 |
| Logical | 33 | 33 | 100.00 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 51
EXPRESSION (ie_i & ((~attr_i.input_disable)))
--1- ------------2------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Unreachable | |
| 1 | 0 | Covered | T20,T21,T22 |
| 1 | 1 | Covered | T1,T2,T3 |
LINE 78
EXPRESSION (ie ? inout_io : 1'bz)
-1
| -1- | Status | Tests |
|---|
| 0 | Covered | T20,T21,T22 |
| 1 | Covered | T1,T2,T3 |
LINE 80
EXPRESSION (attr_i.invert ^ in_raw_o)
------1------ ----2---
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T6,T27,T12 |
| 0 | 1 | Covered | T25,T27,T12 |
| 1 | 0 | Covered | T20,T21,T22 |
| 1 | 1 | Covered | T20,T21,T22 |
LINE 84
EXPRESSION (out_i ^ attr_i.invert)
--1-- ------2------
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T1,T2,T3 |
| 0 | 1 | Covered | T20,T21,T22 |
| 1 | 0 | Covered | T27,T10,T39 |
| 1 | 1 | Covered | T20,T21,T22 |
LINE 85
EXPRESSION (oe_i & ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en))))
--1- ---------------------------------2---------------------------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T20,T21,T22 |
| 1 | 1 | Covered | T6,T27,T10 |
LINE 85
SUB-EXPRESSION ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en)))
--------------------1------------------- -----------2----------
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T20,T21,T22 |
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T20,T21,T22 |
LINE 85
SUB-EXPRESSION (attr_i.virt_od_en & ((~gen_bidir.out)))
--------1-------- ---------2--------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T20,T21,T22 |
| 1 | 1 | Covered | T20,T21,T22 |
LINE 92
EXPRESSION ((gen_bidir.oe && attr_i.drive_strength[0]) ? gen_bidir.out : 1'bz)
---------------------1--------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T20,T21,T22 |
LINE 92
SUB-EXPRESSION (gen_bidir.oe && attr_i.drive_strength[0])
------1----- ------------2-----------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T25,T47,T48 |
| 1 | 0 | Covered | T6,T27,T10 |
| 1 | 1 | Covered | T20,T21,T22 |
LINE 93
EXPRESSION ((gen_bidir.oe && ((!attr_i.drive_strength[0]))) ? gen_bidir.out : 1'bz)
-----------------------1-----------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T6,T27,T10 |
LINE 93
SUB-EXPRESSION (gen_bidir.oe && ((!attr_i.drive_strength[0])))
------1----- --------------2--------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T20,T21,T22 |
| 1 | 1 | Covered | T6,T27,T10 |
LINE 95
EXPRESSION (attr_i.pull_en ? attr_i.pull_select : 1'bz)
-------1------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T25,T10,T47 |
Branch Coverage for Instance : tb.dut.u_padring.gen_mio_pads[15].u_mio_pad.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
| Branches |
|
8 |
8 |
100.00 |
| TERNARY |
78 |
2 |
2 |
100.00 |
| TERNARY |
92 |
2 |
2 |
100.00 |
| TERNARY |
93 |
2 |
2 |
100.00 |
| TERNARY |
95 |
2 |
2 |
100.00 |
78 assign in_raw_o = ie ? inout_io : 1'bz;
-1-
==>
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T3 |
| 0 |
Covered |
T20,T21,T22 |
92 assign (strong0, strong1) inout_io = (oe && attr_i.drive_strength[0]) ? out : 1'bz;
-1-
==>
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T20,T21,T22 |
| 0 |
Covered |
T1,T2,T3 |
93 assign (pull0, pull1) inout_io = (oe && !attr_i.drive_strength[0]) ? out : 1'bz;
-1-
==>
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T6,T27,T10 |
| 0 |
Covered |
T1,T2,T3 |
95 assign (weak0, weak1) inout_io = attr_i.pull_en ? attr_i.pull_select : 1'bz;
-1-
==>
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T25,T10,T47 |
| 0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_padring.gen_mio_pads[15].u_mio_pad.gen_generic.u_impl_generic
Assertion Details
| Name | Attempts | Real Successes | Failures | Incomplete |
|
AnalogNoScan_A |
1010 |
1010 |
0 |
0 |
AnalogNoScan_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
1010 |
1010 |
0 |
0 |
| T1 |
1 |
1 |
0 |
0 |
| T2 |
1 |
1 |
0 |
0 |
| T3 |
1 |
1 |
0 |
0 |
| T4 |
1 |
1 |
0 |
0 |
| T5 |
1 |
1 |
0 |
0 |
| T6 |
1 |
1 |
0 |
0 |
| T30 |
1 |
1 |
0 |
0 |
| T68 |
1 |
1 |
0 |
0 |
| T104 |
1 |
1 |
0 |
0 |
| T105 |
1 |
1 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_padring.gen_mio_pads[16].u_mio_pad.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 8 | 8 | 100.00 |
| CONT_ASSIGN | 39 | 0 | 0 | |
| CONT_ASSIGN | 51 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 78 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 80 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 84 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 85 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 92 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 93 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 95 | 1 | 1 | 100.00 |
38 logic unused_sigs;
39 unreachable assign unused_sigs = ^{attr_i.slew_rate,
40 attr_i.drive_strength[3:1],
41 attr_i.od_en,
42 attr_i.schmitt_en,
43 attr_i.keep_en,
44 scanmode_i,
45 pok_i};
46 //VCS coverage on
47 // pragma coverage on
48
49 // Input enable (active-high)
50 logic ie;
51 1/1 assign ie = ie_i & ~attr_i.input_disable;
Tests: T20 T21 T22
52
53 if (PadType == InputStd) begin : gen_input_only
54 //VCS coverage off
55 // pragma coverage off
56 logic unused_in_sigs;
57 assign unused_in_sigs = ^{out_i,
58 oe_i,
59 attr_i.virt_od_en,
60 attr_i.drive_strength};
61 //VCS coverage on
62 // pragma coverage on
63
64 assign in_raw_o = ie ? inout_io : 1'bz;
65 // input inversion
66 assign in_o = attr_i.invert ^ in_raw_o;
67
68 // pulls are not supported by verilator
69 `ifndef VERILATOR
70 // pullup / pulldown termination
71 assign (weak0, weak1) inout_io = attr_i.pull_en ? attr_i.pull_select : 1'bz;
72 `endif
73 end else if (PadType == BidirTol ||
74 PadType == DualBidirTol ||
75 PadType == BidirOd ||
76 PadType == BidirStd) begin : gen_bidir
77
78 1/1 assign in_raw_o = ie ? inout_io : 1'bz;
Tests: T6 T27 T12
79 // input inversion
80 1/1 assign in_o = attr_i.invert ^ in_raw_o;
Tests: T6 T27 T12
81
82 // virtual open drain emulation
83 logic oe, out;
84 1/1 assign out = out_i ^ attr_i.invert;
Tests: T6 T27 T12
85 1/1 assign oe = oe_i & ((attr_i.virt_od_en & ~out) | ~attr_i.virt_od_en);
Tests: T6 T27 T12
86
87 // drive strength attributes are not supported by verilator
88 `ifdef VERILATOR
89 assign inout_io = (oe) ? out : 1'bz;
90 `else
91 // different driver types
92 1/1 assign (strong0, strong1) inout_io = (oe && attr_i.drive_strength[0]) ? out : 1'bz;
Tests: T6 T27 T12
93 1/1 assign (pull0, pull1) inout_io = (oe && !attr_i.drive_strength[0]) ? out : 1'bz;
Tests: T6 T27 T12
94 // pullup / pulldown termination
95 1/1 assign (weak0, weak1) inout_io = attr_i.pull_en ? attr_i.pull_select : 1'bz;
Tests: T20 T21 T22
Cond Coverage for Instance : tb.dut.u_padring.gen_mio_pads[16].u_mio_pad.gen_generic.u_impl_generic
| Total | Covered | Percent |
|---|
| Conditions | 33 | 33 | 100.00 |
| Logical | 33 | 33 | 100.00 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 51
EXPRESSION (ie_i & ((~attr_i.input_disable)))
--1- ------------2------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Unreachable | |
| 1 | 0 | Covered | T20,T21,T22 |
| 1 | 1 | Covered | T1,T2,T3 |
LINE 78
EXPRESSION (ie ? inout_io : 1'bz)
-1
| -1- | Status | Tests |
|---|
| 0 | Covered | T20,T21,T22 |
| 1 | Covered | T1,T2,T3 |
LINE 80
EXPRESSION (attr_i.invert ^ in_raw_o)
------1------ ----2---
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T27,T12,T15 |
| 0 | 1 | Covered | T6,T27,T12 |
| 1 | 0 | Covered | T21,T22,T44 |
| 1 | 1 | Covered | T21,T22,T44 |
LINE 84
EXPRESSION (out_i ^ attr_i.invert)
--1-- ------2------
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T1,T2,T3 |
| 0 | 1 | Covered | T20,T21,T22 |
| 1 | 0 | Covered | T6,T27,T12 |
| 1 | 1 | Covered | T21,T22,T44 |
LINE 85
EXPRESSION (oe_i & ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en))))
--1- ---------------------------------2---------------------------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T20,T21,T22 |
| 1 | 1 | Covered | T6,T27,T12 |
LINE 85
SUB-EXPRESSION ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en)))
--------------------1------------------- -----------2----------
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T20,T21,T22 |
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T20,T21,T22 |
LINE 85
SUB-EXPRESSION (attr_i.virt_od_en & ((~gen_bidir.out)))
--------1-------- ---------2--------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T20,T21,T22 |
| 1 | 1 | Covered | T20,T21,T22 |
LINE 92
EXPRESSION ((gen_bidir.oe && attr_i.drive_strength[0]) ? gen_bidir.out : 1'bz)
---------------------1--------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T20,T21,T22 |
LINE 92
SUB-EXPRESSION (gen_bidir.oe && attr_i.drive_strength[0])
------1----- ------------2-----------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T20,T21,T22 |
| 1 | 0 | Covered | T6,T27,T12 |
| 1 | 1 | Covered | T20,T21,T22 |
LINE 93
EXPRESSION ((gen_bidir.oe && ((!attr_i.drive_strength[0]))) ? gen_bidir.out : 1'bz)
-----------------------1-----------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T6,T27,T12 |
LINE 93
SUB-EXPRESSION (gen_bidir.oe && ((!attr_i.drive_strength[0])))
------1----- --------------2--------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T20,T21,T22 |
| 1 | 1 | Covered | T6,T27,T12 |
LINE 95
EXPRESSION (attr_i.pull_en ? attr_i.pull_select : 1'bz)
-------1------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T20,T21,T22 |
Branch Coverage for Instance : tb.dut.u_padring.gen_mio_pads[16].u_mio_pad.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
| Branches |
|
8 |
8 |
100.00 |
| TERNARY |
78 |
2 |
2 |
100.00 |
| TERNARY |
92 |
2 |
2 |
100.00 |
| TERNARY |
93 |
2 |
2 |
100.00 |
| TERNARY |
95 |
2 |
2 |
100.00 |
78 assign in_raw_o = ie ? inout_io : 1'bz;
-1-
==>
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T3 |
| 0 |
Covered |
T20,T21,T22 |
92 assign (strong0, strong1) inout_io = (oe && attr_i.drive_strength[0]) ? out : 1'bz;
-1-
==>
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T20,T21,T22 |
| 0 |
Covered |
T1,T2,T3 |
93 assign (pull0, pull1) inout_io = (oe && !attr_i.drive_strength[0]) ? out : 1'bz;
-1-
==>
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T6,T27,T12 |
| 0 |
Covered |
T1,T2,T3 |
95 assign (weak0, weak1) inout_io = attr_i.pull_en ? attr_i.pull_select : 1'bz;
-1-
==>
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T20,T21,T22 |
| 0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_padring.gen_mio_pads[16].u_mio_pad.gen_generic.u_impl_generic
Assertion Details
| Name | Attempts | Real Successes | Failures | Incomplete |
|
AnalogNoScan_A |
1010 |
1010 |
0 |
0 |
AnalogNoScan_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
1010 |
1010 |
0 |
0 |
| T1 |
1 |
1 |
0 |
0 |
| T2 |
1 |
1 |
0 |
0 |
| T3 |
1 |
1 |
0 |
0 |
| T4 |
1 |
1 |
0 |
0 |
| T5 |
1 |
1 |
0 |
0 |
| T6 |
1 |
1 |
0 |
0 |
| T30 |
1 |
1 |
0 |
0 |
| T68 |
1 |
1 |
0 |
0 |
| T104 |
1 |
1 |
0 |
0 |
| T105 |
1 |
1 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_padring.gen_mio_pads[17].u_mio_pad.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 8 | 8 | 100.00 |
| CONT_ASSIGN | 39 | 0 | 0 | |
| CONT_ASSIGN | 51 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 78 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 80 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 84 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 85 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 92 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 93 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 95 | 1 | 1 | 100.00 |
38 logic unused_sigs;
39 unreachable assign unused_sigs = ^{attr_i.slew_rate,
40 attr_i.drive_strength[3:1],
41 attr_i.od_en,
42 attr_i.schmitt_en,
43 attr_i.keep_en,
44 scanmode_i,
45 pok_i};
46 //VCS coverage on
47 // pragma coverage on
48
49 // Input enable (active-high)
50 logic ie;
51 1/1 assign ie = ie_i & ~attr_i.input_disable;
Tests: T20 T21 T22
52
53 if (PadType == InputStd) begin : gen_input_only
54 //VCS coverage off
55 // pragma coverage off
56 logic unused_in_sigs;
57 assign unused_in_sigs = ^{out_i,
58 oe_i,
59 attr_i.virt_od_en,
60 attr_i.drive_strength};
61 //VCS coverage on
62 // pragma coverage on
63
64 assign in_raw_o = ie ? inout_io : 1'bz;
65 // input inversion
66 assign in_o = attr_i.invert ^ in_raw_o;
67
68 // pulls are not supported by verilator
69 `ifndef VERILATOR
70 // pullup / pulldown termination
71 assign (weak0, weak1) inout_io = attr_i.pull_en ? attr_i.pull_select : 1'bz;
72 `endif
73 end else if (PadType == BidirTol ||
74 PadType == DualBidirTol ||
75 PadType == BidirOd ||
76 PadType == BidirStd) begin : gen_bidir
77
78 1/1 assign in_raw_o = ie ? inout_io : 1'bz;
Tests: T6 T27 T12
79 // input inversion
80 1/1 assign in_o = attr_i.invert ^ in_raw_o;
Tests: T6 T27 T12
81
82 // virtual open drain emulation
83 logic oe, out;
84 1/1 assign out = out_i ^ attr_i.invert;
Tests: T6 T27 T10
85 1/1 assign oe = oe_i & ((attr_i.virt_od_en & ~out) | ~attr_i.virt_od_en);
Tests: T6 T27 T10
86
87 // drive strength attributes are not supported by verilator
88 `ifdef VERILATOR
89 assign inout_io = (oe) ? out : 1'bz;
90 `else
91 // different driver types
92 1/1 assign (strong0, strong1) inout_io = (oe && attr_i.drive_strength[0]) ? out : 1'bz;
Tests: T6 T27 T10
93 1/1 assign (pull0, pull1) inout_io = (oe && !attr_i.drive_strength[0]) ? out : 1'bz;
Tests: T6 T27 T10
94 // pullup / pulldown termination
95 1/1 assign (weak0, weak1) inout_io = attr_i.pull_en ? attr_i.pull_select : 1'bz;
Tests: T20 T21 T22
Cond Coverage for Instance : tb.dut.u_padring.gen_mio_pads[17].u_mio_pad.gen_generic.u_impl_generic
| Total | Covered | Percent |
|---|
| Conditions | 33 | 33 | 100.00 |
| Logical | 33 | 33 | 100.00 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 51
EXPRESSION (ie_i & ((~attr_i.input_disable)))
--1- ------------2------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Unreachable | |
| 1 | 0 | Covered | T20,T21,T22 |
| 1 | 1 | Covered | T1,T2,T3 |
LINE 78
EXPRESSION (ie ? inout_io : 1'bz)
-1
| -1- | Status | Tests |
|---|
| 0 | Covered | T20,T21,T22 |
| 1 | Covered | T1,T2,T3 |
LINE 80
EXPRESSION (attr_i.invert ^ in_raw_o)
------1------ ----2---
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T27,T12,T66 |
| 0 | 1 | Covered | T6,T27,T12 |
| 1 | 0 | Covered | T20,T21,T22 |
| 1 | 1 | Covered | T20,T21,T22 |
LINE 84
EXPRESSION (out_i ^ attr_i.invert)
--1-- ------2------
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T1,T2,T3 |
| 0 | 1 | Covered | T20,T21,T22 |
| 1 | 0 | Covered | T6,T27,T10 |
| 1 | 1 | Covered | T20,T21,T22 |
LINE 85
EXPRESSION (oe_i & ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en))))
--1- ---------------------------------2---------------------------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T20,T21,T22 |
| 1 | 1 | Covered | T6,T27,T10 |
LINE 85
SUB-EXPRESSION ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en)))
--------------------1------------------- -----------2----------
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T20,T21,T22 |
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T20,T21,T22 |
LINE 85
SUB-EXPRESSION (attr_i.virt_od_en & ((~gen_bidir.out)))
--------1-------- ---------2--------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T20,T21,T22 |
| 1 | 1 | Covered | T20,T21,T22 |
LINE 92
EXPRESSION ((gen_bidir.oe && attr_i.drive_strength[0]) ? gen_bidir.out : 1'bz)
---------------------1--------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T20,T21,T22 |
LINE 92
SUB-EXPRESSION (gen_bidir.oe && attr_i.drive_strength[0])
------1----- ------------2-----------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T20,T21,T22 |
| 1 | 0 | Covered | T6,T27,T10 |
| 1 | 1 | Covered | T20,T21,T22 |
LINE 93
EXPRESSION ((gen_bidir.oe && ((!attr_i.drive_strength[0]))) ? gen_bidir.out : 1'bz)
-----------------------1-----------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T6,T27,T10 |
LINE 93
SUB-EXPRESSION (gen_bidir.oe && ((!attr_i.drive_strength[0])))
------1----- --------------2--------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T20,T21,T22 |
| 1 | 1 | Covered | T6,T27,T10 |
LINE 95
EXPRESSION (attr_i.pull_en ? attr_i.pull_select : 1'bz)
-------1------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T20,T21,T22 |
Branch Coverage for Instance : tb.dut.u_padring.gen_mio_pads[17].u_mio_pad.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
| Branches |
|
8 |
8 |
100.00 |
| TERNARY |
78 |
2 |
2 |
100.00 |
| TERNARY |
92 |
2 |
2 |
100.00 |
| TERNARY |
93 |
2 |
2 |
100.00 |
| TERNARY |
95 |
2 |
2 |
100.00 |
78 assign in_raw_o = ie ? inout_io : 1'bz;
-1-
==>
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T3 |
| 0 |
Covered |
T20,T21,T22 |
92 assign (strong0, strong1) inout_io = (oe && attr_i.drive_strength[0]) ? out : 1'bz;
-1-
==>
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T20,T21,T22 |
| 0 |
Covered |
T1,T2,T3 |
93 assign (pull0, pull1) inout_io = (oe && !attr_i.drive_strength[0]) ? out : 1'bz;
-1-
==>
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T6,T27,T10 |
| 0 |
Covered |
T1,T2,T3 |
95 assign (weak0, weak1) inout_io = attr_i.pull_en ? attr_i.pull_select : 1'bz;
-1-
==>
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T20,T21,T22 |
| 0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_padring.gen_mio_pads[17].u_mio_pad.gen_generic.u_impl_generic
Assertion Details
| Name | Attempts | Real Successes | Failures | Incomplete |
|
AnalogNoScan_A |
1010 |
1010 |
0 |
0 |
AnalogNoScan_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
1010 |
1010 |
0 |
0 |
| T1 |
1 |
1 |
0 |
0 |
| T2 |
1 |
1 |
0 |
0 |
| T3 |
1 |
1 |
0 |
0 |
| T4 |
1 |
1 |
0 |
0 |
| T5 |
1 |
1 |
0 |
0 |
| T6 |
1 |
1 |
0 |
0 |
| T30 |
1 |
1 |
0 |
0 |
| T68 |
1 |
1 |
0 |
0 |
| T104 |
1 |
1 |
0 |
0 |
| T105 |
1 |
1 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_padring.gen_mio_pads[18].u_mio_pad.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 8 | 8 | 100.00 |
| CONT_ASSIGN | 39 | 0 | 0 | |
| CONT_ASSIGN | 51 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 78 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 80 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 84 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 85 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 92 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 93 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 95 | 1 | 1 | 100.00 |
38 logic unused_sigs;
39 unreachable assign unused_sigs = ^{attr_i.slew_rate,
40 attr_i.drive_strength[3:1],
41 attr_i.od_en,
42 attr_i.schmitt_en,
43 attr_i.keep_en,
44 scanmode_i,
45 pok_i};
46 //VCS coverage on
47 // pragma coverage on
48
49 // Input enable (active-high)
50 logic ie;
51 1/1 assign ie = ie_i & ~attr_i.input_disable;
Tests: T20 T21 T22
52
53 if (PadType == InputStd) begin : gen_input_only
54 //VCS coverage off
55 // pragma coverage off
56 logic unused_in_sigs;
57 assign unused_in_sigs = ^{out_i,
58 oe_i,
59 attr_i.virt_od_en,
60 attr_i.drive_strength};
61 //VCS coverage on
62 // pragma coverage on
63
64 assign in_raw_o = ie ? inout_io : 1'bz;
65 // input inversion
66 assign in_o = attr_i.invert ^ in_raw_o;
67
68 // pulls are not supported by verilator
69 `ifndef VERILATOR
70 // pullup / pulldown termination
71 assign (weak0, weak1) inout_io = attr_i.pull_en ? attr_i.pull_select : 1'bz;
72 `endif
73 end else if (PadType == BidirTol ||
74 PadType == DualBidirTol ||
75 PadType == BidirOd ||
76 PadType == BidirStd) begin : gen_bidir
77
78 1/1 assign in_raw_o = ie ? inout_io : 1'bz;
Tests: T2 T6 T27
79 // input inversion
80 1/1 assign in_o = attr_i.invert ^ in_raw_o;
Tests: T2 T6 T27
81
82 // virtual open drain emulation
83 logic oe, out;
84 1/1 assign out = out_i ^ attr_i.invert;
Tests: T2 T6 T27
85 1/1 assign oe = oe_i & ((attr_i.virt_od_en & ~out) | ~attr_i.virt_od_en);
Tests: T2 T6 T27
86
87 // drive strength attributes are not supported by verilator
88 `ifdef VERILATOR
89 assign inout_io = (oe) ? out : 1'bz;
90 `else
91 // different driver types
92 1/1 assign (strong0, strong1) inout_io = (oe && attr_i.drive_strength[0]) ? out : 1'bz;
Tests: T2 T6 T27
93 1/1 assign (pull0, pull1) inout_io = (oe && !attr_i.drive_strength[0]) ? out : 1'bz;
Tests: T2 T6 T27
94 // pullup / pulldown termination
95 1/1 assign (weak0, weak1) inout_io = attr_i.pull_en ? attr_i.pull_select : 1'bz;
Tests: T20 T21 T22
Cond Coverage for Instance : tb.dut.u_padring.gen_mio_pads[18].u_mio_pad.gen_generic.u_impl_generic
| Total | Covered | Percent |
|---|
| Conditions | 33 | 33 | 100.00 |
| Logical | 33 | 33 | 100.00 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 51
EXPRESSION (ie_i & ((~attr_i.input_disable)))
--1- ------------2------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Unreachable | |
| 1 | 0 | Covered | T20,T21,T22 |
| 1 | 1 | Covered | T1,T2,T3 |
LINE 78
EXPRESSION (ie ? inout_io : 1'bz)
-1
| -1- | Status | Tests |
|---|
| 0 | Covered | T20,T21,T22 |
| 1 | Covered | T1,T2,T3 |
LINE 80
EXPRESSION (attr_i.invert ^ in_raw_o)
------1------ ----2---
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T2,T27,T59 |
| 0 | 1 | Covered | T2,T6,T27 |
| 1 | 0 | Covered | T20,T21,T22 |
| 1 | 1 | Covered | T20,T21,T22 |
LINE 84
EXPRESSION (out_i ^ attr_i.invert)
--1-- ------2------
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T1,T2,T3 |
| 0 | 1 | Covered | T20,T21,T22 |
| 1 | 0 | Covered | T2,T6,T27 |
| 1 | 1 | Covered | T20,T21,T22 |
LINE 85
EXPRESSION (oe_i & ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en))))
--1- ---------------------------------2---------------------------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T20,T21,T22 |
| 1 | 1 | Covered | T2,T6,T27 |
LINE 85
SUB-EXPRESSION ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en)))
--------------------1------------------- -----------2----------
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T20,T21,T22 |
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T20,T21,T22 |
LINE 85
SUB-EXPRESSION (attr_i.virt_od_en & ((~gen_bidir.out)))
--------1-------- ---------2--------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T20,T21,T22 |
| 1 | 1 | Covered | T20,T21,T22 |
LINE 92
EXPRESSION ((gen_bidir.oe && attr_i.drive_strength[0]) ? gen_bidir.out : 1'bz)
---------------------1--------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T20,T21,T22 |
LINE 92
SUB-EXPRESSION (gen_bidir.oe && attr_i.drive_strength[0])
------1----- ------------2-----------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T20,T21,T22 |
| 1 | 0 | Covered | T2,T6,T27 |
| 1 | 1 | Covered | T20,T21,T22 |
LINE 93
EXPRESSION ((gen_bidir.oe && ((!attr_i.drive_strength[0]))) ? gen_bidir.out : 1'bz)
-----------------------1-----------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T2,T6,T27 |
LINE 93
SUB-EXPRESSION (gen_bidir.oe && ((!attr_i.drive_strength[0])))
------1----- --------------2--------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T20,T21,T22 |
| 1 | 1 | Covered | T2,T6,T27 |
LINE 95
EXPRESSION (attr_i.pull_en ? attr_i.pull_select : 1'bz)
-------1------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T20,T21,T22 |
Branch Coverage for Instance : tb.dut.u_padring.gen_mio_pads[18].u_mio_pad.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
| Branches |
|
8 |
8 |
100.00 |
| TERNARY |
78 |
2 |
2 |
100.00 |
| TERNARY |
92 |
2 |
2 |
100.00 |
| TERNARY |
93 |
2 |
2 |
100.00 |
| TERNARY |
95 |
2 |
2 |
100.00 |
78 assign in_raw_o = ie ? inout_io : 1'bz;
-1-
==>
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T3 |
| 0 |
Covered |
T20,T21,T22 |
92 assign (strong0, strong1) inout_io = (oe && attr_i.drive_strength[0]) ? out : 1'bz;
-1-
==>
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T20,T21,T22 |
| 0 |
Covered |
T1,T2,T3 |
93 assign (pull0, pull1) inout_io = (oe && !attr_i.drive_strength[0]) ? out : 1'bz;
-1-
==>
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T2,T6,T27 |
| 0 |
Covered |
T1,T2,T3 |
95 assign (weak0, weak1) inout_io = attr_i.pull_en ? attr_i.pull_select : 1'bz;
-1-
==>
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T20,T21,T22 |
| 0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_padring.gen_mio_pads[18].u_mio_pad.gen_generic.u_impl_generic
Assertion Details
| Name | Attempts | Real Successes | Failures | Incomplete |
|
AnalogNoScan_A |
1010 |
1010 |
0 |
0 |
AnalogNoScan_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
1010 |
1010 |
0 |
0 |
| T1 |
1 |
1 |
0 |
0 |
| T2 |
1 |
1 |
0 |
0 |
| T3 |
1 |
1 |
0 |
0 |
| T4 |
1 |
1 |
0 |
0 |
| T5 |
1 |
1 |
0 |
0 |
| T6 |
1 |
1 |
0 |
0 |
| T30 |
1 |
1 |
0 |
0 |
| T68 |
1 |
1 |
0 |
0 |
| T104 |
1 |
1 |
0 |
0 |
| T105 |
1 |
1 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_padring.gen_mio_pads[19].u_mio_pad.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 8 | 8 | 100.00 |
| CONT_ASSIGN | 39 | 0 | 0 | |
| CONT_ASSIGN | 51 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 78 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 80 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 84 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 85 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 92 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 93 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 95 | 1 | 1 | 100.00 |
38 logic unused_sigs;
39 unreachable assign unused_sigs = ^{attr_i.slew_rate,
40 attr_i.drive_strength[3:1],
41 attr_i.od_en,
42 attr_i.schmitt_en,
43 attr_i.keep_en,
44 scanmode_i,
45 pok_i};
46 //VCS coverage on
47 // pragma coverage on
48
49 // Input enable (active-high)
50 logic ie;
51 1/1 assign ie = ie_i & ~attr_i.input_disable;
Tests: T20 T21 T22
52
53 if (PadType == InputStd) begin : gen_input_only
54 //VCS coverage off
55 // pragma coverage off
56 logic unused_in_sigs;
57 assign unused_in_sigs = ^{out_i,
58 oe_i,
59 attr_i.virt_od_en,
60 attr_i.drive_strength};
61 //VCS coverage on
62 // pragma coverage on
63
64 assign in_raw_o = ie ? inout_io : 1'bz;
65 // input inversion
66 assign in_o = attr_i.invert ^ in_raw_o;
67
68 // pulls are not supported by verilator
69 `ifndef VERILATOR
70 // pullup / pulldown termination
71 assign (weak0, weak1) inout_io = attr_i.pull_en ? attr_i.pull_select : 1'bz;
72 `endif
73 end else if (PadType == BidirTol ||
74 PadType == DualBidirTol ||
75 PadType == BidirOd ||
76 PadType == BidirStd) begin : gen_bidir
77
78 1/1 assign in_raw_o = ie ? inout_io : 1'bz;
Tests: T2 T6 T27
79 // input inversion
80 1/1 assign in_o = attr_i.invert ^ in_raw_o;
Tests: T2 T6 T27
81
82 // virtual open drain emulation
83 logic oe, out;
84 1/1 assign out = out_i ^ attr_i.invert;
Tests: T2 T6 T27
85 1/1 assign oe = oe_i & ((attr_i.virt_od_en & ~out) | ~attr_i.virt_od_en);
Tests: T2 T6 T27
86
87 // drive strength attributes are not supported by verilator
88 `ifdef VERILATOR
89 assign inout_io = (oe) ? out : 1'bz;
90 `else
91 // different driver types
92 1/1 assign (strong0, strong1) inout_io = (oe && attr_i.drive_strength[0]) ? out : 1'bz;
Tests: T2 T6 T27
93 1/1 assign (pull0, pull1) inout_io = (oe && !attr_i.drive_strength[0]) ? out : 1'bz;
Tests: T2 T6 T27
94 // pullup / pulldown termination
95 1/1 assign (weak0, weak1) inout_io = attr_i.pull_en ? attr_i.pull_select : 1'bz;
Tests: T20 T21 T22
Cond Coverage for Instance : tb.dut.u_padring.gen_mio_pads[19].u_mio_pad.gen_generic.u_impl_generic
| Total | Covered | Percent |
|---|
| Conditions | 33 | 33 | 100.00 |
| Logical | 33 | 33 | 100.00 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 51
EXPRESSION (ie_i & ((~attr_i.input_disable)))
--1- ------------2------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Unreachable | |
| 1 | 0 | Covered | T20,T21,T22 |
| 1 | 1 | Covered | T1,T2,T3 |
LINE 78
EXPRESSION (ie ? inout_io : 1'bz)
-1
| -1- | Status | Tests |
|---|
| 0 | Covered | T20,T21,T22 |
| 1 | Covered | T1,T2,T3 |
LINE 80
EXPRESSION (attr_i.invert ^ in_raw_o)
------1------ ----2---
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T2,T27,T59 |
| 0 | 1 | Covered | T2,T6,T27 |
| 1 | 0 | Covered | T20,T21,T22 |
| 1 | 1 | Covered | T20,T21,T22 |
LINE 84
EXPRESSION (out_i ^ attr_i.invert)
--1-- ------2------
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T1,T2,T3 |
| 0 | 1 | Covered | T20,T21,T22 |
| 1 | 0 | Covered | T2,T6,T27 |
| 1 | 1 | Covered | T20,T21,T22 |
LINE 85
EXPRESSION (oe_i & ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en))))
--1- ---------------------------------2---------------------------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T20,T21,T22 |
| 1 | 1 | Covered | T2,T6,T27 |
LINE 85
SUB-EXPRESSION ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en)))
--------------------1------------------- -----------2----------
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T20,T21,T22 |
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T20,T21,T22 |
LINE 85
SUB-EXPRESSION (attr_i.virt_od_en & ((~gen_bidir.out)))
--------1-------- ---------2--------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T20,T21,T22 |
| 1 | 1 | Covered | T20,T21,T22 |
LINE 92
EXPRESSION ((gen_bidir.oe && attr_i.drive_strength[0]) ? gen_bidir.out : 1'bz)
---------------------1--------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T20,T21,T22 |
LINE 92
SUB-EXPRESSION (gen_bidir.oe && attr_i.drive_strength[0])
------1----- ------------2-----------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T20,T21,T22 |
| 1 | 0 | Covered | T2,T6,T27 |
| 1 | 1 | Covered | T20,T21,T22 |
LINE 93
EXPRESSION ((gen_bidir.oe && ((!attr_i.drive_strength[0]))) ? gen_bidir.out : 1'bz)
-----------------------1-----------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T2,T6,T27 |
LINE 93
SUB-EXPRESSION (gen_bidir.oe && ((!attr_i.drive_strength[0])))
------1----- --------------2--------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T20,T21,T22 |
| 1 | 1 | Covered | T2,T6,T27 |
LINE 95
EXPRESSION (attr_i.pull_en ? attr_i.pull_select : 1'bz)
-------1------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T20,T21,T22 |
Branch Coverage for Instance : tb.dut.u_padring.gen_mio_pads[19].u_mio_pad.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
| Branches |
|
8 |
8 |
100.00 |
| TERNARY |
78 |
2 |
2 |
100.00 |
| TERNARY |
92 |
2 |
2 |
100.00 |
| TERNARY |
93 |
2 |
2 |
100.00 |
| TERNARY |
95 |
2 |
2 |
100.00 |
78 assign in_raw_o = ie ? inout_io : 1'bz;
-1-
==>
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T3 |
| 0 |
Covered |
T20,T21,T22 |
92 assign (strong0, strong1) inout_io = (oe && attr_i.drive_strength[0]) ? out : 1'bz;
-1-
==>
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T20,T21,T22 |
| 0 |
Covered |
T1,T2,T3 |
93 assign (pull0, pull1) inout_io = (oe && !attr_i.drive_strength[0]) ? out : 1'bz;
-1-
==>
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T2,T6,T27 |
| 0 |
Covered |
T1,T2,T3 |
95 assign (weak0, weak1) inout_io = attr_i.pull_en ? attr_i.pull_select : 1'bz;
-1-
==>
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T20,T21,T22 |
| 0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_padring.gen_mio_pads[19].u_mio_pad.gen_generic.u_impl_generic
Assertion Details
| Name | Attempts | Real Successes | Failures | Incomplete |
|
AnalogNoScan_A |
1010 |
1010 |
0 |
0 |
AnalogNoScan_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
1010 |
1010 |
0 |
0 |
| T1 |
1 |
1 |
0 |
0 |
| T2 |
1 |
1 |
0 |
0 |
| T3 |
1 |
1 |
0 |
0 |
| T4 |
1 |
1 |
0 |
0 |
| T5 |
1 |
1 |
0 |
0 |
| T6 |
1 |
1 |
0 |
0 |
| T30 |
1 |
1 |
0 |
0 |
| T68 |
1 |
1 |
0 |
0 |
| T104 |
1 |
1 |
0 |
0 |
| T105 |
1 |
1 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_padring.gen_mio_pads[20].u_mio_pad.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 8 | 8 | 100.00 |
| CONT_ASSIGN | 39 | 0 | 0 | |
| CONT_ASSIGN | 51 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 78 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 80 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 84 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 85 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 92 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 93 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 95 | 1 | 1 | 100.00 |
38 logic unused_sigs;
39 unreachable assign unused_sigs = ^{attr_i.slew_rate,
40 attr_i.drive_strength[3:1],
41 attr_i.od_en,
42 attr_i.schmitt_en,
43 attr_i.keep_en,
44 scanmode_i,
45 pok_i};
46 //VCS coverage on
47 // pragma coverage on
48
49 // Input enable (active-high)
50 logic ie;
51 1/1 assign ie = ie_i & ~attr_i.input_disable;
Tests: T20 T21 T22
52
53 if (PadType == InputStd) begin : gen_input_only
54 //VCS coverage off
55 // pragma coverage off
56 logic unused_in_sigs;
57 assign unused_in_sigs = ^{out_i,
58 oe_i,
59 attr_i.virt_od_en,
60 attr_i.drive_strength};
61 //VCS coverage on
62 // pragma coverage on
63
64 assign in_raw_o = ie ? inout_io : 1'bz;
65 // input inversion
66 assign in_o = attr_i.invert ^ in_raw_o;
67
68 // pulls are not supported by verilator
69 `ifndef VERILATOR
70 // pullup / pulldown termination
71 assign (weak0, weak1) inout_io = attr_i.pull_en ? attr_i.pull_select : 1'bz;
72 `endif
73 end else if (PadType == BidirTol ||
74 PadType == DualBidirTol ||
75 PadType == BidirOd ||
76 PadType == BidirStd) begin : gen_bidir
77
78 1/1 assign in_raw_o = ie ? inout_io : 1'bz;
Tests: T2 T6 T27
79 // input inversion
80 1/1 assign in_o = attr_i.invert ^ in_raw_o;
Tests: T2 T6 T27
81
82 // virtual open drain emulation
83 logic oe, out;
84 1/1 assign out = out_i ^ attr_i.invert;
Tests: T2 T27 T33
85 1/1 assign oe = oe_i & ((attr_i.virt_od_en & ~out) | ~attr_i.virt_od_en);
Tests: T2 T6 T27
86
87 // drive strength attributes are not supported by verilator
88 `ifdef VERILATOR
89 assign inout_io = (oe) ? out : 1'bz;
90 `else
91 // different driver types
92 1/1 assign (strong0, strong1) inout_io = (oe && attr_i.drive_strength[0]) ? out : 1'bz;
Tests: T2 T6 T27
93 1/1 assign (pull0, pull1) inout_io = (oe && !attr_i.drive_strength[0]) ? out : 1'bz;
Tests: T2 T6 T27
94 // pullup / pulldown termination
95 1/1 assign (weak0, weak1) inout_io = attr_i.pull_en ? attr_i.pull_select : 1'bz;
Tests: T20 T21 T22
Cond Coverage for Instance : tb.dut.u_padring.gen_mio_pads[20].u_mio_pad.gen_generic.u_impl_generic
| Total | Covered | Percent |
|---|
| Conditions | 33 | 33 | 100.00 |
| Logical | 33 | 33 | 100.00 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 51
EXPRESSION (ie_i & ((~attr_i.input_disable)))
--1- ------------2------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Unreachable | |
| 1 | 0 | Covered | T20,T21,T22 |
| 1 | 1 | Covered | T1,T2,T3 |
LINE 78
EXPRESSION (ie ? inout_io : 1'bz)
-1
| -1- | Status | Tests |
|---|
| 0 | Covered | T20,T21,T22 |
| 1 | Covered | T1,T2,T3 |
LINE 80
EXPRESSION (attr_i.invert ^ in_raw_o)
------1------ ----2---
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T2,T6,T27 |
| 0 | 1 | Covered | T2,T27,T61 |
| 1 | 0 | Covered | T20,T21,T222 |
| 1 | 1 | Covered | T20,T222,T230 |
LINE 84
EXPRESSION (out_i ^ attr_i.invert)
--1-- ------2------
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T1,T2,T3 |
| 0 | 1 | Covered | T20,T21,T22 |
| 1 | 0 | Covered | T2,T27,T33 |
| 1 | 1 | Covered | T20,T21,T22 |
LINE 85
EXPRESSION (oe_i & ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en))))
--1- ---------------------------------2---------------------------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T20,T21,T22 |
| 1 | 1 | Covered | T2,T6,T27 |
LINE 85
SUB-EXPRESSION ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en)))
--------------------1------------------- -----------2----------
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T20,T21,T22 |
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T20,T21,T22 |
LINE 85
SUB-EXPRESSION (attr_i.virt_od_en & ((~gen_bidir.out)))
--------1-------- ---------2--------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T20,T21,T22 |
| 1 | 1 | Covered | T20,T21,T22 |
LINE 92
EXPRESSION ((gen_bidir.oe && attr_i.drive_strength[0]) ? gen_bidir.out : 1'bz)
---------------------1--------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T20,T21,T22 |
LINE 92
SUB-EXPRESSION (gen_bidir.oe && attr_i.drive_strength[0])
------1----- ------------2-----------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T20,T21,T22 |
| 1 | 0 | Covered | T2,T6,T27 |
| 1 | 1 | Covered | T20,T21,T22 |
LINE 93
EXPRESSION ((gen_bidir.oe && ((!attr_i.drive_strength[0]))) ? gen_bidir.out : 1'bz)
-----------------------1-----------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T2,T6,T27 |
LINE 93
SUB-EXPRESSION (gen_bidir.oe && ((!attr_i.drive_strength[0])))
------1----- --------------2--------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T20,T21,T22 |
| 1 | 1 | Covered | T2,T6,T27 |
LINE 95
EXPRESSION (attr_i.pull_en ? attr_i.pull_select : 1'bz)
-------1------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T20,T21,T22 |
Branch Coverage for Instance : tb.dut.u_padring.gen_mio_pads[20].u_mio_pad.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
| Branches |
|
8 |
8 |
100.00 |
| TERNARY |
78 |
2 |
2 |
100.00 |
| TERNARY |
92 |
2 |
2 |
100.00 |
| TERNARY |
93 |
2 |
2 |
100.00 |
| TERNARY |
95 |
2 |
2 |
100.00 |
78 assign in_raw_o = ie ? inout_io : 1'bz;
-1-
==>
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T3 |
| 0 |
Covered |
T20,T21,T22 |
92 assign (strong0, strong1) inout_io = (oe && attr_i.drive_strength[0]) ? out : 1'bz;
-1-
==>
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T20,T21,T22 |
| 0 |
Covered |
T1,T2,T3 |
93 assign (pull0, pull1) inout_io = (oe && !attr_i.drive_strength[0]) ? out : 1'bz;
-1-
==>
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T2,T6,T27 |
| 0 |
Covered |
T1,T2,T3 |
95 assign (weak0, weak1) inout_io = attr_i.pull_en ? attr_i.pull_select : 1'bz;
-1-
==>
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T20,T21,T22 |
| 0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_padring.gen_mio_pads[20].u_mio_pad.gen_generic.u_impl_generic
Assertion Details
| Name | Attempts | Real Successes | Failures | Incomplete |
|
AnalogNoScan_A |
1010 |
1010 |
0 |
0 |
AnalogNoScan_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
1010 |
1010 |
0 |
0 |
| T1 |
1 |
1 |
0 |
0 |
| T2 |
1 |
1 |
0 |
0 |
| T3 |
1 |
1 |
0 |
0 |
| T4 |
1 |
1 |
0 |
0 |
| T5 |
1 |
1 |
0 |
0 |
| T6 |
1 |
1 |
0 |
0 |
| T30 |
1 |
1 |
0 |
0 |
| T68 |
1 |
1 |
0 |
0 |
| T104 |
1 |
1 |
0 |
0 |
| T105 |
1 |
1 |
0 |
0 |