Unified Coverage Report :: Module Instance :: tb.dut.u_padring.gen_mio_pads[21].u_mio_pad.gen_generic.u_impl_generic

Module Instance : tb.dut.u_padring.gen_mio_pads[21].u_mio_pad.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_mio_pads[21].u_mio_pad

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_padring.gen_mio_pads[22].u_mio_pad.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_mio_pads[22].u_mio_pad

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_padring.gen_mio_pads[23].u_mio_pad.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_mio_pads[23].u_mio_pad

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_padring.gen_mio_pads[24].u_mio_pad.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_mio_pads[24].u_mio_pad

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_padring.gen_mio_pads[25].u_mio_pad.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_mio_pads[25].u_mio_pad

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_padring.gen_mio_pads[26].u_mio_pad.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_mio_pads[26].u_mio_pad

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_padring.gen_mio_pads[27].u_mio_pad.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_mio_pads[27].u_mio_pad

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_padring.gen_mio_pads[28].u_mio_pad.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_mio_pads[28].u_mio_pad

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_padring.gen_mio_pads[29].u_mio_pad.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_mio_pads[29].u_mio_pad

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_padring.gen_mio_pads[30].u_mio_pad.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_mio_pads[30].u_mio_pad

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_padring.gen_mio_pads[31].u_mio_pad.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_mio_pads[31].u_mio_pad

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_padring.gen_mio_pads[32].u_mio_pad.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_mio_pads[32].u_mio_pad

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_padring.gen_mio_pads[33].u_mio_pad.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_mio_pads[33].u_mio_pad

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_padring.gen_mio_pads[34].u_mio_pad.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_mio_pads[34].u_mio_pad

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_padring.gen_mio_pads[35].u_mio_pad.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_mio_pads[35].u_mio_pad

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_padring.gen_mio_pads[36].u_mio_pad.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_mio_pads[36].u_mio_pad

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_padring.gen_mio_pads[37].u_mio_pad.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_mio_pads[37].u_mio_pad

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_padring.gen_mio_pads[38].u_mio_pad.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_mio_pads[38].u_mio_pad

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_padring.gen_mio_pads[39].u_mio_pad.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_mio_pads[39].u_mio_pad

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_padring.gen_mio_pads[40].u_mio_pad.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_mio_pads[40].u_mio_pad

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_padring.gen_mio_pads[41].u_mio_pad.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_mio_pads[41].u_mio_pad

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_padring.gen_mio_pads[42].u_mio_pad.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_mio_pads[42].u_mio_pad

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_padring.gen_mio_pads[21].u_mio_pad.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		8	8	100.00
CONT_ASSIGN	39	0	0
CONT_ASSIGN	51	1	1	100.00
CONT_ASSIGN	78	1	1	100.00
CONT_ASSIGN	80	1	1	100.00
CONT_ASSIGN	84	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	93	1	1	100.00
CONT_ASSIGN	95	1	1	100.00

38                        logic unused_sigs;
39         unreachable    assign unused_sigs = ^{attr_i.slew_rate,
40                                               attr_i.drive_strength[3:1],
41                                               attr_i.od_en,
42                                               attr_i.schmitt_en,
43                                               attr_i.keep_en,
44                                               scanmode_i,
45                                               pok_i};
46                        //VCS coverage on
47                        // pragma coverage on
48                      
49                        // Input enable (active-high)
50                        logic ie;
51         1/1            assign ie = ie_i & ~attr_i.input_disable;
           Tests:       T22 T23 T24 
52                      
53                        if (PadType == InputStd) begin : gen_input_only
54                          //VCS coverage off
55                          // pragma coverage off
56                          logic unused_in_sigs;
57                          assign unused_in_sigs = ^{out_i,
58                                                    oe_i,
59                                                    attr_i.virt_od_en,
60                                                    attr_i.drive_strength};
61                          //VCS coverage on
62                          // pragma coverage on
63                      
64                          assign in_raw_o = ie ? inout_io : 1'bz;
65                          // input inversion
66                          assign in_o = attr_i.invert ^ in_raw_o;
67                      
68                        // pulls are not supported by verilator
69                        `ifndef VERILATOR
70                          // pullup / pulldown termination
71                          assign (weak0, weak1) inout_io = attr_i.pull_en ? attr_i.pull_select : 1'bz;
72                        `endif
73                        end else if (PadType == BidirTol ||
74                                     PadType == DualBidirTol ||
75                                     PadType == BidirOd ||
76                                     PadType == BidirStd) begin : gen_bidir
77                      
78         1/1              assign in_raw_o = ie ? inout_io : 1'bz;
           Tests:       T2 T28 T35 
79                          // input inversion
80         1/1              assign in_o = attr_i.invert ^ in_raw_o;
           Tests:       T2 T28 T35 
81                      
82                          // virtual open drain emulation
83                          logic oe, out;
84         1/1              assign out = out_i ^ attr_i.invert;
           Tests:       T2 T28 T43 
85         1/1              assign oe  = oe_i & ((attr_i.virt_od_en & ~out) | ~attr_i.virt_od_en);
           Tests:       T2 T28 T35 
86                      
87                        // drive strength attributes are not supported by verilator
88                        `ifdef VERILATOR
89                          assign inout_io = (oe)   ? out : 1'bz;
90                        `else
91                          // different driver types
92         1/1              assign (strong0, strong1) inout_io = (oe && attr_i.drive_strength[0]) ? out : 1'bz;
           Tests:       T2 T28 T35 
93         1/1              assign (pull0, pull1)     inout_io = (oe && !attr_i.drive_strength[0]) ? out : 1'bz;
           Tests:       T2 T28 T35 
94                          // pullup / pulldown termination
95         1/1              assign (weak0, weak1)     inout_io = attr_i.pull_en ? attr_i.pull_select : 1'bz;
           Tests:       T22 T23 T24 

---

Cond Coverage for Instance : tb.dut.u_padring.gen_mio_pads[21].u_mio_pad.gen_generic.u_impl_generic

	Total	Covered	Percent
Conditions	33	33	100.00
Logical	33	33	100.00
Non-Logical	0	0
Event	0	0

 LINE       51
 EXPRESSION (ie_i & ((~attr_i.input_disable)))
             --1-   ------------2------------

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Covered	T22,T23,T24
1	1	Covered	T1,T2,T3

 LINE       78
 EXPRESSION (ie ? inout_io : 1'bz)
             -1

-1-	Status	Tests
0	Covered	T22,T23,T24
1	Covered	T1,T2,T3

 LINE       80
 EXPRESSION (attr_i.invert ^ in_raw_o)
             ------1------   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T2,T28,T35
0	1	Covered	T2,T28,T35
1	0	Covered	T23,T24,T216
1	1	Covered	T23,T24,T216

 LINE       84
 EXPRESSION (out_i ^ attr_i.invert)
             --1--   ------2------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T22,T23,T24
1	0	Covered	T2,T28,T43
1	1	Covered	T22,T23,T24

 LINE       85
 EXPRESSION (oe_i & ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en))))
             --1-   ---------------------------------2---------------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T22,T23,T24
1	1	Covered	T2,T28,T35

 LINE       85
 SUB-EXPRESSION ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en)))
                 --------------------1-------------------   -----------2----------

-1-	-2-	Status	Tests
0	0	Covered	T22,T23,T24
0	1	Covered	T1,T2,T3
1	0	Covered	T22,T23,T24

 LINE       85
 SUB-EXPRESSION (attr_i.virt_od_en & ((~gen_bidir.out)))
                 --------1--------   ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T22,T23,T24
1	1	Covered	T22,T23,T24

 LINE       92
 EXPRESSION ((gen_bidir.oe && attr_i.drive_strength[0]) ? gen_bidir.out : 1'bz)
             ---------------------1--------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T22,T23,T24

 LINE       92
 SUB-EXPRESSION (gen_bidir.oe && attr_i.drive_strength[0])
                 ------1-----    ------------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T22,T23,T24
1	0	Covered	T2,T28,T35
1	1	Covered	T22,T23,T24

 LINE       93
 EXPRESSION ((gen_bidir.oe && ((!attr_i.drive_strength[0]))) ? gen_bidir.out : 1'bz)
             -----------------------1-----------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T28,T35

 LINE       93
 SUB-EXPRESSION (gen_bidir.oe && ((!attr_i.drive_strength[0])))
                 ------1-----    --------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T22,T23,T24
1	1	Covered	T2,T28,T35

 LINE       95
 EXPRESSION (attr_i.pull_en ? attr_i.pull_select : 1'bz)
             -------1------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T22,T23,T24

---

Branch Coverage for Instance : tb.dut.u_padring.gen_mio_pads[21].u_mio_pad.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
TERNARY	78	2	2	100.00
TERNARY	92	2	2	100.00
TERNARY	93	2	2	100.00
TERNARY	95	2	2	100.00

78             assign in_raw_o = ie ? inout_io : 1'bz;
                                    -1-  
                                    ==>  
                                    ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T22,T23,T24

92             assign (strong0, strong1) inout_io = (oe && attr_i.drive_strength[0]) ? out : 1'bz;
                                                                                     -1-  
                                                                                     ==>  
                                                                                     ==>  

Branches:

-1-	Status	Tests
1	Covered	T22,T23,T24
0	Covered	T1,T2,T3

93             assign (pull0, pull1)     inout_io = (oe && !attr_i.drive_strength[0]) ? out : 1'bz;
                                                                                      -1-  
                                                                                      ==>  
                                                                                      ==>  

Branches:

-1-	Status	Tests
1	Covered	T2,T28,T35
0	Covered	T1,T2,T3

95             assign (weak0, weak1)     inout_io = attr_i.pull_en ? attr_i.pull_select : 1'bz;
                                                                   -1-  
                                                                   ==>  
                                                                   ==>  

Branches:

-1-	Status	Tests
1	Covered	T22,T23,T24
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_padring.gen_mio_pads[21].u_mio_pad.gen_generic.u_impl_generic

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AnalogNoScan_A	1021	1021	0	0

AnalogNoScan_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1021	1021	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T38	1	1	0	0
T39	1	1	0	0
T106	1	1	0	0

Line Coverage for Instance : tb.dut.u_padring.gen_mio_pads[22].u_mio_pad.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		8	8	100.00
CONT_ASSIGN	39	0	0
CONT_ASSIGN	51	1	1	100.00
CONT_ASSIGN	78	1	1	100.00
CONT_ASSIGN	80	1	1	100.00
CONT_ASSIGN	84	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	93	1	1	100.00
CONT_ASSIGN	95	1	1	100.00

38                        logic unused_sigs;
39         unreachable    assign unused_sigs = ^{attr_i.slew_rate,
40                                               attr_i.drive_strength[3:1],
41                                               attr_i.od_en,
42                                               attr_i.schmitt_en,
43                                               attr_i.keep_en,
44                                               scanmode_i,
45                                               pok_i};
46                        //VCS coverage on
47                        // pragma coverage on
48                      
49                        // Input enable (active-high)
50                        logic ie;
51         1/1            assign ie = ie_i & ~attr_i.input_disable;
           Tests:       T22 T23 T24 
52                      
53                        if (PadType == InputStd) begin : gen_input_only
54                          //VCS coverage off
55                          // pragma coverage off
56                          logic unused_in_sigs;
57                          assign unused_in_sigs = ^{out_i,
58                                                    oe_i,
59                                                    attr_i.virt_od_en,
60                                                    attr_i.drive_strength};
61                          //VCS coverage on
62                          // pragma coverage on
63                      
64                          assign in_raw_o = ie ? inout_io : 1'bz;
65                          // input inversion
66                          assign in_o = attr_i.invert ^ in_raw_o;
67                      
68                        // pulls are not supported by verilator
69                        `ifndef VERILATOR
70                          // pullup / pulldown termination
71                          assign (weak0, weak1) inout_io = attr_i.pull_en ? attr_i.pull_select : 1'bz;
72                        `endif
73                        end else if (PadType == BidirTol ||
74                                     PadType == DualBidirTol ||
75                                     PadType == BidirOd ||
76                                     PadType == BidirStd) begin : gen_bidir
77                      
78         1/1              assign in_raw_o = ie ? inout_io : 1'bz;
           Tests:       T1 T2 T3 
79                          // input inversion
80         1/1              assign in_o = attr_i.invert ^ in_raw_o;
           Tests:       T1 T2 T3 
81                      
82                          // virtual open drain emulation
83                          logic oe, out;
84         1/1              assign out = out_i ^ attr_i.invert;
           Tests:       T22 T23 T24 
85         1/1              assign oe  = oe_i & ((attr_i.virt_od_en & ~out) | ~attr_i.virt_od_en);
           Tests:       T22 T23 T24 
86                      
87                        // drive strength attributes are not supported by verilator
88                        `ifdef VERILATOR
89                          assign inout_io = (oe)   ? out : 1'bz;
90                        `else
91                          // different driver types
92         1/1              assign (strong0, strong1) inout_io = (oe && attr_i.drive_strength[0]) ? out : 1'bz;
           Tests:       T22 T23 T24 
93         1/1              assign (pull0, pull1)     inout_io = (oe && !attr_i.drive_strength[0]) ? out : 1'bz;
           Tests:       T22 T23 T24 
94                          // pullup / pulldown termination
95         1/1              assign (weak0, weak1)     inout_io = attr_i.pull_en ? attr_i.pull_select : 1'bz;
           Tests:       T63 T64 T65 

---

Cond Coverage for Instance : tb.dut.u_padring.gen_mio_pads[22].u_mio_pad.gen_generic.u_impl_generic

	Total	Covered	Percent
Conditions	33	33	100.00
Logical	33	33	100.00
Non-Logical	0	0
Event	0	0

 LINE       51
 EXPRESSION (ie_i & ((~attr_i.input_disable)))
             --1-   ------------2------------

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Covered	T22,T23,T24
1	1	Covered	T1,T2,T3

 LINE       78
 EXPRESSION (ie ? inout_io : 1'bz)
             -1

-1-	Status	Tests
0	Covered	T22,T23,T24
1	Covered	T1,T2,T3

 LINE       80
 EXPRESSION (attr_i.invert ^ in_raw_o)
             ------1------   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T63,T64,T65
1	0	Covered	T22,T23,T24
1	1	Covered	T22,T23,T24

 LINE       84
 EXPRESSION (out_i ^ attr_i.invert)
             --1--   ------2------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T22,T23,T24
1	0	Covered	T22,T23,T24
1	1	Covered	T22,T23,T24

 LINE       85
 EXPRESSION (oe_i & ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en))))
             --1-   ---------------------------------2---------------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T22,T23,T24
1	1	Covered	T22,T23,T24

 LINE       85
 SUB-EXPRESSION ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en)))
                 --------------------1-------------------   -----------2----------

-1-	-2-	Status	Tests
0	0	Covered	T22,T23,T24
0	1	Covered	T1,T2,T3
1	0	Covered	T22,T23,T24

 LINE       85
 SUB-EXPRESSION (attr_i.virt_od_en & ((~gen_bidir.out)))
                 --------1--------   ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T22,T23,T24
1	1	Covered	T22,T23,T24

 LINE       92
 EXPRESSION ((gen_bidir.oe && attr_i.drive_strength[0]) ? gen_bidir.out : 1'bz)
             ---------------------1--------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T22,T23,T24

 LINE       92
 SUB-EXPRESSION (gen_bidir.oe && attr_i.drive_strength[0])
                 ------1-----    ------------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T22,T23,T24
1	0	Covered	T22,T23,T24
1	1	Covered	T22,T23,T24

 LINE       93
 EXPRESSION ((gen_bidir.oe && ((!attr_i.drive_strength[0]))) ? gen_bidir.out : 1'bz)
             -----------------------1-----------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T22,T23,T24

 LINE       93
 SUB-EXPRESSION (gen_bidir.oe && ((!attr_i.drive_strength[0])))
                 ------1-----    --------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T22,T23,T24
1	1	Covered	T22,T23,T24

 LINE       95
 EXPRESSION (attr_i.pull_en ? attr_i.pull_select : 1'bz)
             -------1------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T63,T64,T65

---

Branch Coverage for Instance : tb.dut.u_padring.gen_mio_pads[22].u_mio_pad.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
TERNARY	78	2	2	100.00
TERNARY	92	2	2	100.00
TERNARY	93	2	2	100.00
TERNARY	95	2	2	100.00

78             assign in_raw_o = ie ? inout_io : 1'bz;
                                    -1-  
                                    ==>  
                                    ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T22,T23,T24

92             assign (strong0, strong1) inout_io = (oe && attr_i.drive_strength[0]) ? out : 1'bz;
                                                                                     -1-  
                                                                                     ==>  
                                                                                     ==>  

Branches:

-1-	Status	Tests
1	Covered	T22,T23,T24
0	Covered	T1,T2,T3

93             assign (pull0, pull1)     inout_io = (oe && !attr_i.drive_strength[0]) ? out : 1'bz;
                                                                                      -1-  
                                                                                      ==>  
                                                                                      ==>  

Branches:

-1-	Status	Tests
1	Covered	T22,T23,T24
0	Covered	T1,T2,T3

95             assign (weak0, weak1)     inout_io = attr_i.pull_en ? attr_i.pull_select : 1'bz;
                                                                   -1-  
                                                                   ==>  
                                                                   ==>  

Branches:

-1-	Status	Tests
1	Covered	T63,T64,T65
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_padring.gen_mio_pads[22].u_mio_pad.gen_generic.u_impl_generic

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AnalogNoScan_A	1021	1021	0	0

AnalogNoScan_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1021	1021	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T38	1	1	0	0
T39	1	1	0	0
T106	1	1	0	0

Line Coverage for Instance : tb.dut.u_padring.gen_mio_pads[23].u_mio_pad.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		8	8	100.00
CONT_ASSIGN	39	0	0
CONT_ASSIGN	51	1	1	100.00
CONT_ASSIGN	78	1	1	100.00
CONT_ASSIGN	80	1	1	100.00
CONT_ASSIGN	84	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	93	1	1	100.00
CONT_ASSIGN	95	1	1	100.00

38                        logic unused_sigs;
39         unreachable    assign unused_sigs = ^{attr_i.slew_rate,
40                                               attr_i.drive_strength[3:1],
41                                               attr_i.od_en,
42                                               attr_i.schmitt_en,
43                                               attr_i.keep_en,
44                                               scanmode_i,
45                                               pok_i};
46                        //VCS coverage on
47                        // pragma coverage on
48                      
49                        // Input enable (active-high)
50                        logic ie;
51         1/1            assign ie = ie_i & ~attr_i.input_disable;
           Tests:       T22 T23 T24 
52                      
53                        if (PadType == InputStd) begin : gen_input_only
54                          //VCS coverage off
55                          // pragma coverage off
56                          logic unused_in_sigs;
57                          assign unused_in_sigs = ^{out_i,
58                                                    oe_i,
59                                                    attr_i.virt_od_en,
60                                                    attr_i.drive_strength};
61                          //VCS coverage on
62                          // pragma coverage on
63                      
64                          assign in_raw_o = ie ? inout_io : 1'bz;
65                          // input inversion
66                          assign in_o = attr_i.invert ^ in_raw_o;
67                      
68                        // pulls are not supported by verilator
69                        `ifndef VERILATOR
70                          // pullup / pulldown termination
71                          assign (weak0, weak1) inout_io = attr_i.pull_en ? attr_i.pull_select : 1'bz;
72                        `endif
73                        end else if (PadType == BidirTol ||
74                                     PadType == DualBidirTol ||
75                                     PadType == BidirOd ||
76                                     PadType == BidirStd) begin : gen_bidir
77                      
78         1/1              assign in_raw_o = ie ? inout_io : 1'bz;
           Tests:       T1 T2 T3 
79                          // input inversion
80         1/1              assign in_o = attr_i.invert ^ in_raw_o;
           Tests:       T1 T2 T3 
81                      
82                          // virtual open drain emulation
83                          logic oe, out;
84         1/1              assign out = out_i ^ attr_i.invert;
           Tests:       T22 T23 T24 
85         1/1              assign oe  = oe_i & ((attr_i.virt_od_en & ~out) | ~attr_i.virt_od_en);
           Tests:       T49 T22 T23 
86                      
87                        // drive strength attributes are not supported by verilator
88                        `ifdef VERILATOR
89                          assign inout_io = (oe)   ? out : 1'bz;
90                        `else
91                          // different driver types
92         1/1              assign (strong0, strong1) inout_io = (oe && attr_i.drive_strength[0]) ? out : 1'bz;
           Tests:       T49 T22 T23 
93         1/1              assign (pull0, pull1)     inout_io = (oe && !attr_i.drive_strength[0]) ? out : 1'bz;
           Tests:       T49 T22 T23 
94                          // pullup / pulldown termination
95         1/1              assign (weak0, weak1)     inout_io = attr_i.pull_en ? attr_i.pull_select : 1'bz;
           Tests:       T63 T64 T65 

---

Cond Coverage for Instance : tb.dut.u_padring.gen_mio_pads[23].u_mio_pad.gen_generic.u_impl_generic

	Total	Covered	Percent
Conditions	33	33	100.00
Logical	33	33	100.00
Non-Logical	0	0
Event	0	0

 LINE       51
 EXPRESSION (ie_i & ((~attr_i.input_disable)))
             --1-   ------------2------------

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Covered	T22,T23,T24
1	1	Covered	T1,T2,T3

 LINE       78
 EXPRESSION (ie ? inout_io : 1'bz)
             -1

-1-	Status	Tests
0	Covered	T22,T23,T24
1	Covered	T1,T2,T3

 LINE       80
 EXPRESSION (attr_i.invert ^ in_raw_o)
             ------1------   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T21,T238,T239
1	0	Covered	T22,T23,T24
1	1	Covered	T22,T23,T24

 LINE       84
 EXPRESSION (out_i ^ attr_i.invert)
             --1--   ------2------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T22,T23,T24
1	0	Covered	T22,T23,T24
1	1	Covered	T22,T23,T24

 LINE       85
 EXPRESSION (oe_i & ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en))))
             --1-   ---------------------------------2---------------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T22,T23,T24
1	1	Covered	T49,T22,T23

 LINE       85
 SUB-EXPRESSION ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en)))
                 --------------------1-------------------   -----------2----------

-1-	-2-	Status	Tests
0	0	Covered	T22,T23,T24
0	1	Covered	T1,T2,T3
1	0	Covered	T22,T23,T24

 LINE       85
 SUB-EXPRESSION (attr_i.virt_od_en & ((~gen_bidir.out)))
                 --------1--------   ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T22,T23,T24
1	1	Covered	T22,T23,T24

 LINE       92
 EXPRESSION ((gen_bidir.oe && attr_i.drive_strength[0]) ? gen_bidir.out : 1'bz)
             ---------------------1--------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T22,T23,T24

 LINE       92
 SUB-EXPRESSION (gen_bidir.oe && attr_i.drive_strength[0])
                 ------1-----    ------------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T22,T23,T24
1	0	Covered	T49,T22,T23
1	1	Covered	T22,T23,T24

 LINE       93
 EXPRESSION ((gen_bidir.oe && ((!attr_i.drive_strength[0]))) ? gen_bidir.out : 1'bz)
             -----------------------1-----------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T49,T22,T23

 LINE       93
 SUB-EXPRESSION (gen_bidir.oe && ((!attr_i.drive_strength[0])))
                 ------1-----    --------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T22,T23,T24
1	1	Covered	T49,T22,T23

 LINE       95
 EXPRESSION (attr_i.pull_en ? attr_i.pull_select : 1'bz)
             -------1------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T63,T64,T65

---

Branch Coverage for Instance : tb.dut.u_padring.gen_mio_pads[23].u_mio_pad.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
TERNARY	78	2	2	100.00
TERNARY	92	2	2	100.00
TERNARY	93	2	2	100.00
TERNARY	95	2	2	100.00

78             assign in_raw_o = ie ? inout_io : 1'bz;
                                    -1-  
                                    ==>  
                                    ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T22,T23,T24

92             assign (strong0, strong1) inout_io = (oe && attr_i.drive_strength[0]) ? out : 1'bz;
                                                                                     -1-  
                                                                                     ==>  
                                                                                     ==>  

Branches:

-1-	Status	Tests
1	Covered	T22,T23,T24
0	Covered	T1,T2,T3

93             assign (pull0, pull1)     inout_io = (oe && !attr_i.drive_strength[0]) ? out : 1'bz;
                                                                                      -1-  
                                                                                      ==>  
                                                                                      ==>  

Branches:

-1-	Status	Tests
1	Covered	T49,T22,T23
0	Covered	T1,T2,T3

95             assign (weak0, weak1)     inout_io = attr_i.pull_en ? attr_i.pull_select : 1'bz;
                                                                   -1-  
                                                                   ==>  
                                                                   ==>  

Branches:

-1-	Status	Tests
1	Covered	T63,T64,T65
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_padring.gen_mio_pads[23].u_mio_pad.gen_generic.u_impl_generic

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AnalogNoScan_A	1021	1021	0	0

AnalogNoScan_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1021	1021	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T38	1	1	0	0
T39	1	1	0	0
T106	1	1	0	0

Line Coverage for Instance : tb.dut.u_padring.gen_mio_pads[24].u_mio_pad.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		8	8	100.00
CONT_ASSIGN	39	0	0
CONT_ASSIGN	51	1	1	100.00
CONT_ASSIGN	78	1	1	100.00
CONT_ASSIGN	80	1	1	100.00
CONT_ASSIGN	84	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	93	1	1	100.00
CONT_ASSIGN	95	1	1	100.00

38                        logic unused_sigs;
39         unreachable    assign unused_sigs = ^{attr_i.slew_rate,
40                                               attr_i.drive_strength[3:1],
41                                               attr_i.od_en,
42                                               attr_i.schmitt_en,
43                                               attr_i.keep_en,
44                                               scanmode_i,
45                                               pok_i};
46                        //VCS coverage on
47                        // pragma coverage on
48                      
49                        // Input enable (active-high)
50                        logic ie;
51         1/1            assign ie = ie_i & ~attr_i.input_disable;
           Tests:       T22 T23 T24 
52                      
53                        if (PadType == InputStd) begin : gen_input_only
54                          //VCS coverage off
55                          // pragma coverage off
56                          logic unused_in_sigs;
57                          assign unused_in_sigs = ^{out_i,
58                                                    oe_i,
59                                                    attr_i.virt_od_en,
60                                                    attr_i.drive_strength};
61                          //VCS coverage on
62                          // pragma coverage on
63                      
64                          assign in_raw_o = ie ? inout_io : 1'bz;
65                          // input inversion
66                          assign in_o = attr_i.invert ^ in_raw_o;
67                      
68                        // pulls are not supported by verilator
69                        `ifndef VERILATOR
70                          // pullup / pulldown termination
71                          assign (weak0, weak1) inout_io = attr_i.pull_en ? attr_i.pull_select : 1'bz;
72                        `endif
73                        end else if (PadType == BidirTol ||
74                                     PadType == DualBidirTol ||
75                                     PadType == BidirOd ||
76                                     PadType == BidirStd) begin : gen_bidir
77                      
78         1/1              assign in_raw_o = ie ? inout_io : 1'bz;
           Tests:       T1 T2 T3 
79                          // input inversion
80         1/1              assign in_o = attr_i.invert ^ in_raw_o;
           Tests:       T1 T2 T3 
81                      
82                          // virtual open drain emulation
83                          logic oe, out;
84         1/1              assign out = out_i ^ attr_i.invert;
           Tests:       T21 T49 T22 
85         1/1              assign oe  = oe_i & ((attr_i.virt_od_en & ~out) | ~attr_i.virt_od_en);
           Tests:       T21 T49 T22 
86                      
87                        // drive strength attributes are not supported by verilator
88                        `ifdef VERILATOR
89                          assign inout_io = (oe)   ? out : 1'bz;
90                        `else
91                          // different driver types
92         1/1              assign (strong0, strong1) inout_io = (oe && attr_i.drive_strength[0]) ? out : 1'bz;
           Tests:       T21 T49 T22 
93         1/1              assign (pull0, pull1)     inout_io = (oe && !attr_i.drive_strength[0]) ? out : 1'bz;
           Tests:       T21 T49 T22 
94                          // pullup / pulldown termination
95         1/1              assign (weak0, weak1)     inout_io = attr_i.pull_en ? attr_i.pull_select : 1'bz;
           Tests:       T63 T64 T65 

---

Cond Coverage for Instance : tb.dut.u_padring.gen_mio_pads[24].u_mio_pad.gen_generic.u_impl_generic

	Total	Covered	Percent
Conditions	33	33	100.00
Logical	33	33	100.00
Non-Logical	0	0
Event	0	0

 LINE       51
 EXPRESSION (ie_i & ((~attr_i.input_disable)))
             --1-   ------------2------------

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Covered	T22,T23,T24
1	1	Covered	T1,T2,T3

 LINE       78
 EXPRESSION (ie ? inout_io : 1'bz)
             -1

-1-	Status	Tests
0	Covered	T22,T23,T24
1	Covered	T1,T2,T3

 LINE       80
 EXPRESSION (attr_i.invert ^ in_raw_o)
             ------1------   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T21,T49,T238
1	0	Covered	T22,T23,T24
1	1	Covered	T22,T23,T24

 LINE       84
 EXPRESSION (out_i ^ attr_i.invert)
             --1--   ------2------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T22,T23,T24
1	0	Covered	T21,T49,T22
1	1	Covered	T22,T23,T24

 LINE       85
 EXPRESSION (oe_i & ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en))))
             --1-   ---------------------------------2---------------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T22,T23,T24
1	1	Covered	T21,T49,T22

 LINE       85
 SUB-EXPRESSION ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en)))
                 --------------------1-------------------   -----------2----------

-1-	-2-	Status	Tests
0	0	Covered	T22,T23,T24
0	1	Covered	T1,T2,T3
1	0	Covered	T22,T23,T24

 LINE       85
 SUB-EXPRESSION (attr_i.virt_od_en & ((~gen_bidir.out)))
                 --------1--------   ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T22,T23,T24
1	1	Covered	T22,T23,T24

 LINE       92
 EXPRESSION ((gen_bidir.oe && attr_i.drive_strength[0]) ? gen_bidir.out : 1'bz)
             ---------------------1--------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T22,T23,T24

 LINE       92
 SUB-EXPRESSION (gen_bidir.oe && attr_i.drive_strength[0])
                 ------1-----    ------------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T22,T23,T24
1	0	Covered	T21,T49,T22
1	1	Covered	T22,T23,T24

 LINE       93
 EXPRESSION ((gen_bidir.oe && ((!attr_i.drive_strength[0]))) ? gen_bidir.out : 1'bz)
             -----------------------1-----------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T21,T49,T22

 LINE       93
 SUB-EXPRESSION (gen_bidir.oe && ((!attr_i.drive_strength[0])))
                 ------1-----    --------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T22,T23,T24
1	1	Covered	T21,T49,T22

 LINE       95
 EXPRESSION (attr_i.pull_en ? attr_i.pull_select : 1'bz)
             -------1------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T63,T64,T65

---

Branch Coverage for Instance : tb.dut.u_padring.gen_mio_pads[24].u_mio_pad.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
TERNARY	78	2	2	100.00
TERNARY	92	2	2	100.00
TERNARY	93	2	2	100.00
TERNARY	95	2	2	100.00

78             assign in_raw_o = ie ? inout_io : 1'bz;
                                    -1-  
                                    ==>  
                                    ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T22,T23,T24

92             assign (strong0, strong1) inout_io = (oe && attr_i.drive_strength[0]) ? out : 1'bz;
                                                                                     -1-  
                                                                                     ==>  
                                                                                     ==>  

Branches:

-1-	Status	Tests
1	Covered	T22,T23,T24
0	Covered	T1,T2,T3

93             assign (pull0, pull1)     inout_io = (oe && !attr_i.drive_strength[0]) ? out : 1'bz;
                                                                                      -1-  
                                                                                      ==>  
                                                                                      ==>  

Branches:

-1-	Status	Tests
1	Covered	T21,T49,T22
0	Covered	T1,T2,T3

95             assign (weak0, weak1)     inout_io = attr_i.pull_en ? attr_i.pull_select : 1'bz;
                                                                   -1-  
                                                                   ==>  
                                                                   ==>  

Branches:

-1-	Status	Tests
1	Covered	T63,T64,T65
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_padring.gen_mio_pads[24].u_mio_pad.gen_generic.u_impl_generic

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AnalogNoScan_A	1021	1021	0	0

AnalogNoScan_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1021	1021	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T38	1	1	0	0
T39	1	1	0	0
T106	1	1	0	0

Line Coverage for Instance : tb.dut.u_padring.gen_mio_pads[25].u_mio_pad.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		8	8	100.00
CONT_ASSIGN	39	0	0
CONT_ASSIGN	51	1	1	100.00
CONT_ASSIGN	78	1	1	100.00
CONT_ASSIGN	80	1	1	100.00
CONT_ASSIGN	84	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	93	1	1	100.00
CONT_ASSIGN	95	1	1	100.00

38                        logic unused_sigs;
39         unreachable    assign unused_sigs = ^{attr_i.slew_rate,
40                                               attr_i.drive_strength[3:1],
41                                               attr_i.od_en,
42                                               attr_i.schmitt_en,
43                                               attr_i.keep_en,
44                                               scanmode_i,
45                                               pok_i};
46                        //VCS coverage on
47                        // pragma coverage on
48                      
49                        // Input enable (active-high)
50                        logic ie;
51         1/1            assign ie = ie_i & ~attr_i.input_disable;
           Tests:       T22 T23 T24 
52                      
53                        if (PadType == InputStd) begin : gen_input_only
54                          //VCS coverage off
55                          // pragma coverage off
56                          logic unused_in_sigs;
57                          assign unused_in_sigs = ^{out_i,
58                                                    oe_i,
59                                                    attr_i.virt_od_en,
60                                                    attr_i.drive_strength};
61                          //VCS coverage on
62                          // pragma coverage on
63                      
64                          assign in_raw_o = ie ? inout_io : 1'bz;
65                          // input inversion
66                          assign in_o = attr_i.invert ^ in_raw_o;
67                      
68                        // pulls are not supported by verilator
69                        `ifndef VERILATOR
70                          // pullup / pulldown termination
71                          assign (weak0, weak1) inout_io = attr_i.pull_en ? attr_i.pull_select : 1'bz;
72                        `endif
73                        end else if (PadType == BidirTol ||
74                                     PadType == DualBidirTol ||
75                                     PadType == BidirOd ||
76                                     PadType == BidirStd) begin : gen_bidir
77                      
78         1/1              assign in_raw_o = ie ? inout_io : 1'bz;
           Tests:       T1 T2 T3 
79                          // input inversion
80         1/1              assign in_o = attr_i.invert ^ in_raw_o;
           Tests:       T1 T2 T3 
81                      
82                          // virtual open drain emulation
83                          logic oe, out;
84         1/1              assign out = out_i ^ attr_i.invert;
           Tests:       T21 T49 T22 
85         1/1              assign oe  = oe_i & ((attr_i.virt_od_en & ~out) | ~attr_i.virt_od_en);
           Tests:       T21 T49 T22 
86                      
87                        // drive strength attributes are not supported by verilator
88                        `ifdef VERILATOR
89                          assign inout_io = (oe)   ? out : 1'bz;
90                        `else
91                          // different driver types
92         1/1              assign (strong0, strong1) inout_io = (oe && attr_i.drive_strength[0]) ? out : 1'bz;
           Tests:       T21 T49 T22 
93         1/1              assign (pull0, pull1)     inout_io = (oe && !attr_i.drive_strength[0]) ? out : 1'bz;
           Tests:       T21 T49 T22 
94                          // pullup / pulldown termination
95         1/1              assign (weak0, weak1)     inout_io = attr_i.pull_en ? attr_i.pull_select : 1'bz;
           Tests:       T1 T2 T3 

---

Cond Coverage for Instance : tb.dut.u_padring.gen_mio_pads[25].u_mio_pad.gen_generic.u_impl_generic

	Total	Covered	Percent
Conditions	33	33	100.00
Logical	33	33	100.00
Non-Logical	0	0
Event	0	0

 LINE       51
 EXPRESSION (ie_i & ((~attr_i.input_disable)))
             --1-   ------------2------------

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Covered	T22,T23,T24
1	1	Covered	T1,T2,T3

 LINE       78
 EXPRESSION (ie ? inout_io : 1'bz)
             -1

-1-	Status	Tests
0	Covered	T22,T23,T24
1	Covered	T1,T2,T3

 LINE       80
 EXPRESSION (attr_i.invert ^ in_raw_o)
             ------1------   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T131,T30,T45
0	1	Covered	T1,T2,T3
1	0	Covered	T22,T23,T216
1	1	Covered	T22,T23,T217

 LINE       84
 EXPRESSION (out_i ^ attr_i.invert)
             --1--   ------2------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T22,T23,T24
1	0	Covered	T21,T49,T22
1	1	Covered	T22,T23,T24

 LINE       85
 EXPRESSION (oe_i & ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en))))
             --1-   ---------------------------------2---------------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T22,T23,T24
1	1	Covered	T21,T49,T22

 LINE       85
 SUB-EXPRESSION ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en)))
                 --------------------1-------------------   -----------2----------

-1-	-2-	Status	Tests
0	0	Covered	T22,T23,T24
0	1	Covered	T1,T2,T3
1	0	Covered	T22,T23,T24

 LINE       85
 SUB-EXPRESSION (attr_i.virt_od_en & ((~gen_bidir.out)))
                 --------1--------   ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T22,T23,T24
1	1	Covered	T22,T23,T24

 LINE       92
 EXPRESSION ((gen_bidir.oe && attr_i.drive_strength[0]) ? gen_bidir.out : 1'bz)
             ---------------------1--------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T22,T23,T24

 LINE       92
 SUB-EXPRESSION (gen_bidir.oe && attr_i.drive_strength[0])
                 ------1-----    ------------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T22,T23,T24
1	0	Covered	T21,T49,T22
1	1	Covered	T22,T23,T24

 LINE       93
 EXPRESSION ((gen_bidir.oe && ((!attr_i.drive_strength[0]))) ? gen_bidir.out : 1'bz)
             -----------------------1-----------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T21,T49,T22

 LINE       93
 SUB-EXPRESSION (gen_bidir.oe && ((!attr_i.drive_strength[0])))
                 ------1-----    --------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T22,T23,T24
1	1	Covered	T21,T49,T22

 LINE       95
 EXPRESSION (attr_i.pull_en ? attr_i.pull_select : 1'bz)
             -------1------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_padring.gen_mio_pads[25].u_mio_pad.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
TERNARY	78	2	2	100.00
TERNARY	92	2	2	100.00
TERNARY	93	2	2	100.00
TERNARY	95	2	2	100.00

78             assign in_raw_o = ie ? inout_io : 1'bz;
                                    -1-  
                                    ==>  
                                    ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T22,T23,T24

92             assign (strong0, strong1) inout_io = (oe && attr_i.drive_strength[0]) ? out : 1'bz;
                                                                                     -1-  
                                                                                     ==>  
                                                                                     ==>  

Branches:

-1-	Status	Tests
1	Covered	T22,T23,T24
0	Covered	T1,T2,T3

93             assign (pull0, pull1)     inout_io = (oe && !attr_i.drive_strength[0]) ? out : 1'bz;
                                                                                      -1-  
                                                                                      ==>  
                                                                                      ==>  

Branches:

-1-	Status	Tests
1	Covered	T21,T49,T22
0	Covered	T1,T2,T3

95             assign (weak0, weak1)     inout_io = attr_i.pull_en ? attr_i.pull_select : 1'bz;
                                                                   -1-  
                                                                   ==>  
                                                                   ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_padring.gen_mio_pads[25].u_mio_pad.gen_generic.u_impl_generic

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AnalogNoScan_A	1021	1021	0	0

AnalogNoScan_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1021	1021	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T38	1	1	0	0
T39	1	1	0	0
T106	1	1	0	0

Line Coverage for Instance : tb.dut.u_padring.gen_mio_pads[26].u_mio_pad.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		8	8	100.00
CONT_ASSIGN	39	0	0
CONT_ASSIGN	51	1	1	100.00
CONT_ASSIGN	78	1	1	100.00
CONT_ASSIGN	80	1	1	100.00
CONT_ASSIGN	84	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	93	1	1	100.00
CONT_ASSIGN	95	1	1	100.00

38                        logic unused_sigs;
39         unreachable    assign unused_sigs = ^{attr_i.slew_rate,
40                                               attr_i.drive_strength[3:1],
41                                               attr_i.od_en,
42                                               attr_i.schmitt_en,
43                                               attr_i.keep_en,
44                                               scanmode_i,
45                                               pok_i};
46                        //VCS coverage on
47                        // pragma coverage on
48                      
49                        // Input enable (active-high)
50                        logic ie;
51         1/1            assign ie = ie_i & ~attr_i.input_disable;
           Tests:       T22 T23 T24 
52                      
53                        if (PadType == InputStd) begin : gen_input_only
54                          //VCS coverage off
55                          // pragma coverage off
56                          logic unused_in_sigs;
57                          assign unused_in_sigs = ^{out_i,
58                                                    oe_i,
59                                                    attr_i.virt_od_en,
60                                                    attr_i.drive_strength};
61                          //VCS coverage on
62                          // pragma coverage on
63                      
64                          assign in_raw_o = ie ? inout_io : 1'bz;
65                          // input inversion
66                          assign in_o = attr_i.invert ^ in_raw_o;
67                      
68                        // pulls are not supported by verilator
69                        `ifndef VERILATOR
70                          // pullup / pulldown termination
71                          assign (weak0, weak1) inout_io = attr_i.pull_en ? attr_i.pull_select : 1'bz;
72                        `endif
73                        end else if (PadType == BidirTol ||
74                                     PadType == DualBidirTol ||
75                                     PadType == BidirOd ||
76                                     PadType == BidirStd) begin : gen_bidir
77                      
78         1/1              assign in_raw_o = ie ? inout_io : 1'bz;
           Tests:       T1 T2 T3 
79                          // input inversion
80         1/1              assign in_o = attr_i.invert ^ in_raw_o;
           Tests:       T1 T2 T3 
81                      
82                          // virtual open drain emulation
83                          logic oe, out;
84         1/1              assign out = out_i ^ attr_i.invert;
           Tests:       T1 T2 T3 
85         1/1              assign oe  = oe_i & ((attr_i.virt_od_en & ~out) | ~attr_i.virt_od_en);
           Tests:       T1 T2 T3 
86                      
87                        // drive strength attributes are not supported by verilator
88                        `ifdef VERILATOR
89                          assign inout_io = (oe)   ? out : 1'bz;
90                        `else
91                          // different driver types
92         1/1              assign (strong0, strong1) inout_io = (oe && attr_i.drive_strength[0]) ? out : 1'bz;
           Tests:       T1 T2 T3 
93         1/1              assign (pull0, pull1)     inout_io = (oe && !attr_i.drive_strength[0]) ? out : 1'bz;
           Tests:       T1 T2 T3 
94                          // pullup / pulldown termination
95         1/1              assign (weak0, weak1)     inout_io = attr_i.pull_en ? attr_i.pull_select : 1'bz;
           Tests:       T22 T23 T24 

---

Cond Coverage for Instance : tb.dut.u_padring.gen_mio_pads[26].u_mio_pad.gen_generic.u_impl_generic

	Total	Covered	Percent
Conditions	33	33	100.00
Logical	33	33	100.00
Non-Logical	0	0
Event	0	0

 LINE       51
 EXPRESSION (ie_i & ((~attr_i.input_disable)))
             --1-   ------------2------------

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Covered	T22,T23,T24
1	1	Covered	T1,T2,T3

 LINE       78
 EXPRESSION (ie ? inout_io : 1'bz)
             -1

-1-	Status	Tests
0	Covered	T22,T23,T24
1	Covered	T1,T2,T3

 LINE       80
 EXPRESSION (attr_i.invert ^ in_raw_o)
             ------1------   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T131,T30,T45
0	1	Covered	T1,T2,T3
1	0	Covered	T22,T23,T24
1	1	Covered	T22,T23,T216

 LINE       84
 EXPRESSION (out_i ^ attr_i.invert)
             --1--   ------2------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T22,T23,T24
1	0	Covered	T1,T2,T3
1	1	Covered	T22,T23,T24

 LINE       85
 EXPRESSION (oe_i & ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en))))
             --1-   ---------------------------------2---------------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T22,T23,T24
1	1	Covered	T1,T2,T3

 LINE       85
 SUB-EXPRESSION ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en)))
                 --------------------1-------------------   -----------2----------

-1-	-2-	Status	Tests
0	0	Covered	T22,T23,T24
0	1	Covered	T1,T2,T3
1	0	Covered	T22,T23,T24

 LINE       85
 SUB-EXPRESSION (attr_i.virt_od_en & ((~gen_bidir.out)))
                 --------1--------   ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T22,T23,T24
1	1	Covered	T22,T23,T24

 LINE       92
 EXPRESSION ((gen_bidir.oe && attr_i.drive_strength[0]) ? gen_bidir.out : 1'bz)
             ---------------------1--------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T22,T23,T24

 LINE       92
 SUB-EXPRESSION (gen_bidir.oe && attr_i.drive_strength[0])
                 ------1-----    ------------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T22,T23,T24
1	0	Covered	T1,T2,T3
1	1	Covered	T22,T23,T24

 LINE       93
 EXPRESSION ((gen_bidir.oe && ((!attr_i.drive_strength[0]))) ? gen_bidir.out : 1'bz)
             -----------------------1-----------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       93
 SUB-EXPRESSION (gen_bidir.oe && ((!attr_i.drive_strength[0])))
                 ------1-----    --------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T22,T23,T24
1	1	Covered	T1,T2,T3

 LINE       95
 EXPRESSION (attr_i.pull_en ? attr_i.pull_select : 1'bz)
             -------1------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T22,T23,T24

---

Branch Coverage for Instance : tb.dut.u_padring.gen_mio_pads[26].u_mio_pad.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
TERNARY	78	2	2	100.00
TERNARY	92	2	2	100.00
TERNARY	93	2	2	100.00
TERNARY	95	2	2	100.00

78             assign in_raw_o = ie ? inout_io : 1'bz;
                                    -1-  
                                    ==>  
                                    ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T22,T23,T24

92             assign (strong0, strong1) inout_io = (oe && attr_i.drive_strength[0]) ? out : 1'bz;
                                                                                     -1-  
                                                                                     ==>  
                                                                                     ==>  

Branches:

-1-	Status	Tests
1	Covered	T22,T23,T24
0	Covered	T1,T2,T3

93             assign (pull0, pull1)     inout_io = (oe && !attr_i.drive_strength[0]) ? out : 1'bz;
                                                                                      -1-  
                                                                                      ==>  
                                                                                      ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

95             assign (weak0, weak1)     inout_io = attr_i.pull_en ? attr_i.pull_select : 1'bz;
                                                                   -1-  
                                                                   ==>  
                                                                   ==>  

Branches:

-1-	Status	Tests
1	Covered	T22,T23,T24
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_padring.gen_mio_pads[26].u_mio_pad.gen_generic.u_impl_generic

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AnalogNoScan_A	1021	1021	0	0

AnalogNoScan_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1021	1021	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T38	1	1	0	0
T39	1	1	0	0
T106	1	1	0	0

Line Coverage for Instance : tb.dut.u_padring.gen_mio_pads[27].u_mio_pad.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		8	8	100.00
CONT_ASSIGN	39	0	0
CONT_ASSIGN	51	1	1	100.00
CONT_ASSIGN	78	1	1	100.00
CONT_ASSIGN	80	1	1	100.00
CONT_ASSIGN	84	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	93	1	1	100.00
CONT_ASSIGN	95	1	1	100.00

38                        logic unused_sigs;
39         unreachable    assign unused_sigs = ^{attr_i.slew_rate,
40                                               attr_i.drive_strength[3:1],
41                                               attr_i.od_en,
42                                               attr_i.schmitt_en,
43                                               attr_i.keep_en,
44                                               scanmode_i,
45                                               pok_i};
46                        //VCS coverage on
47                        // pragma coverage on
48                      
49                        // Input enable (active-high)
50                        logic ie;
51         1/1            assign ie = ie_i & ~attr_i.input_disable;
           Tests:       T22 T23 T24 
52                      
53                        if (PadType == InputStd) begin : gen_input_only
54                          //VCS coverage off
55                          // pragma coverage off
56                          logic unused_in_sigs;
57                          assign unused_in_sigs = ^{out_i,
58                                                    oe_i,
59                                                    attr_i.virt_od_en,
60                                                    attr_i.drive_strength};
61                          //VCS coverage on
62                          // pragma coverage on
63                      
64                          assign in_raw_o = ie ? inout_io : 1'bz;
65                          // input inversion
66                          assign in_o = attr_i.invert ^ in_raw_o;
67                      
68                        // pulls are not supported by verilator
69                        `ifndef VERILATOR
70                          // pullup / pulldown termination
71                          assign (weak0, weak1) inout_io = attr_i.pull_en ? attr_i.pull_select : 1'bz;
72                        `endif
73                        end else if (PadType == BidirTol ||
74                                     PadType == DualBidirTol ||
75                                     PadType == BidirOd ||
76                                     PadType == BidirStd) begin : gen_bidir
77                      
78         1/1              assign in_raw_o = ie ? inout_io : 1'bz;
           Tests:       T1 T2 T3 
79                          // input inversion
80         1/1              assign in_o = attr_i.invert ^ in_raw_o;
           Tests:       T1 T2 T3 
81                      
82                          // virtual open drain emulation
83                          logic oe, out;
84         1/1              assign out = out_i ^ attr_i.invert;
           Tests:       T21 T22 T23 
85         1/1              assign oe  = oe_i & ((attr_i.virt_od_en & ~out) | ~attr_i.virt_od_en);
           Tests:       T21 T22 T23 
86                      
87                        // drive strength attributes are not supported by verilator
88                        `ifdef VERILATOR
89                          assign inout_io = (oe)   ? out : 1'bz;
90                        `else
91                          // different driver types
92         1/1              assign (strong0, strong1) inout_io = (oe && attr_i.drive_strength[0]) ? out : 1'bz;
           Tests:       T21 T22 T23 
93         1/1              assign (pull0, pull1)     inout_io = (oe && !attr_i.drive_strength[0]) ? out : 1'bz;
           Tests:       T21 T22 T23 
94                          // pullup / pulldown termination
95         1/1              assign (weak0, weak1)     inout_io = attr_i.pull_en ? attr_i.pull_select : 1'bz;
           Tests:       T22 T23 T24 

---

Cond Coverage for Instance : tb.dut.u_padring.gen_mio_pads[27].u_mio_pad.gen_generic.u_impl_generic

	Total	Covered	Percent
Conditions	33	33	100.00
Logical	33	33	100.00
Non-Logical	0	0
Event	0	0

 LINE       51
 EXPRESSION (ie_i & ((~attr_i.input_disable)))
             --1-   ------------2------------

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Covered	T22,T23,T24
1	1	Covered	T1,T2,T3

 LINE       78
 EXPRESSION (ie ? inout_io : 1'bz)
             -1

-1-	Status	Tests
0	Covered	T22,T23,T24
1	Covered	T1,T2,T3

 LINE       80
 EXPRESSION (attr_i.invert ^ in_raw_o)
             ------1------   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T95,T40,T92
1	0	Covered	T22,T23,T24
1	1	Covered	T22,T23,T24

 LINE       84
 EXPRESSION (out_i ^ attr_i.invert)
             --1--   ------2------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T22,T23,T24
1	0	Covered	T21,T23,T24
1	1	Covered	T22,T23,T24

 LINE       85
 EXPRESSION (oe_i & ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en))))
             --1-   ---------------------------------2---------------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T22,T23,T24
1	1	Covered	T21,T22,T23

 LINE       85
 SUB-EXPRESSION ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en)))
                 --------------------1-------------------   -----------2----------

-1-	-2-	Status	Tests
0	0	Covered	T22,T23,T24
0	1	Covered	T1,T2,T3
1	0	Covered	T22,T23,T24

 LINE       85
 SUB-EXPRESSION (attr_i.virt_od_en & ((~gen_bidir.out)))
                 --------1--------   ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T22,T23,T24
1	1	Covered	T22,T23,T24

 LINE       92
 EXPRESSION ((gen_bidir.oe && attr_i.drive_strength[0]) ? gen_bidir.out : 1'bz)
             ---------------------1--------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T22,T23,T24

 LINE       92
 SUB-EXPRESSION (gen_bidir.oe && attr_i.drive_strength[0])
                 ------1-----    ------------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T22,T23,T24
1	0	Covered	T21,T22,T23
1	1	Covered	T22,T23,T24

 LINE       93
 EXPRESSION ((gen_bidir.oe && ((!attr_i.drive_strength[0]))) ? gen_bidir.out : 1'bz)
             -----------------------1-----------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T21,T22,T23

 LINE       93
 SUB-EXPRESSION (gen_bidir.oe && ((!attr_i.drive_strength[0])))
                 ------1-----    --------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T22,T23,T24
1	1	Covered	T21,T22,T23

 LINE       95
 EXPRESSION (attr_i.pull_en ? attr_i.pull_select : 1'bz)
             -------1------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T22,T23,T24

---

Branch Coverage for Instance : tb.dut.u_padring.gen_mio_pads[27].u_mio_pad.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
TERNARY	78	2	2	100.00
TERNARY	92	2	2	100.00
TERNARY	93	2	2	100.00
TERNARY	95	2	2	100.00

78             assign in_raw_o = ie ? inout_io : 1'bz;
                                    -1-  
                                    ==>  
                                    ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T22,T23,T24

92             assign (strong0, strong1) inout_io = (oe && attr_i.drive_strength[0]) ? out : 1'bz;
                                                                                     -1-  
                                                                                     ==>  
                                                                                     ==>  

Branches:

-1-	Status	Tests
1	Covered	T22,T23,T24
0	Covered	T1,T2,T3

93             assign (pull0, pull1)     inout_io = (oe && !attr_i.drive_strength[0]) ? out : 1'bz;
                                                                                      -1-  
                                                                                      ==>  
                                                                                      ==>  

Branches:

-1-	Status	Tests
1	Covered	T21,T22,T23
0	Covered	T1,T2,T3

95             assign (weak0, weak1)     inout_io = attr_i.pull_en ? attr_i.pull_select : 1'bz;
                                                                   -1-  
                                                                   ==>  
                                                                   ==>  

Branches:

-1-	Status	Tests
1	Covered	T22,T23,T24
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_padring.gen_mio_pads[27].u_mio_pad.gen_generic.u_impl_generic

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AnalogNoScan_A	1021	1021	0	0

AnalogNoScan_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1021	1021	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T38	1	1	0	0
T39	1	1	0	0
T106	1	1	0	0

Line Coverage for Instance : tb.dut.u_padring.gen_mio_pads[28].u_mio_pad.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		8	8	100.00
CONT_ASSIGN	39	0	0
CONT_ASSIGN	51	1	1	100.00
CONT_ASSIGN	78	1	1	100.00
CONT_ASSIGN	80	1	1	100.00
CONT_ASSIGN	84	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	93	1	1	100.00
CONT_ASSIGN	95	1	1	100.00

38                        logic unused_sigs;
39         unreachable    assign unused_sigs = ^{attr_i.slew_rate,
40                                               attr_i.drive_strength[3:1],
41                                               attr_i.od_en,
42                                               attr_i.schmitt_en,
43                                               attr_i.keep_en,
44                                               scanmode_i,
45                                               pok_i};
46                        //VCS coverage on
47                        // pragma coverage on
48                      
49                        // Input enable (active-high)
50                        logic ie;
51         1/1            assign ie = ie_i & ~attr_i.input_disable;
           Tests:       T22 T23 T24 
52                      
53                        if (PadType == InputStd) begin : gen_input_only
54                          //VCS coverage off
55                          // pragma coverage off
56                          logic unused_in_sigs;
57                          assign unused_in_sigs = ^{out_i,
58                                                    oe_i,
59                                                    attr_i.virt_od_en,
60                                                    attr_i.drive_strength};
61                          //VCS coverage on
62                          // pragma coverage on
63                      
64                          assign in_raw_o = ie ? inout_io : 1'bz;
65                          // input inversion
66                          assign in_o = attr_i.invert ^ in_raw_o;
67                      
68                        // pulls are not supported by verilator
69                        `ifndef VERILATOR
70                          // pullup / pulldown termination
71                          assign (weak0, weak1) inout_io = attr_i.pull_en ? attr_i.pull_select : 1'bz;
72                        `endif
73                        end else if (PadType == BidirTol ||
74                                     PadType == DualBidirTol ||
75                                     PadType == BidirOd ||
76                                     PadType == BidirStd) begin : gen_bidir
77                      
78         1/1              assign in_raw_o = ie ? inout_io : 1'bz;
           Tests:       T5 T36 T37 
79                          // input inversion
80         1/1              assign in_o = attr_i.invert ^ in_raw_o;
           Tests:       T5 T36 T37 
81                      
82                          // virtual open drain emulation
83                          logic oe, out;
84         1/1              assign out = out_i ^ attr_i.invert;
           Tests:       T22 T23 T24 
85         1/1              assign oe  = oe_i & ((attr_i.virt_od_en & ~out) | ~attr_i.virt_od_en);
           Tests:       T22 T23 T24 
86                      
87                        // drive strength attributes are not supported by verilator
88                        `ifdef VERILATOR
89                          assign inout_io = (oe)   ? out : 1'bz;
90                        `else
91                          // different driver types
92         1/1              assign (strong0, strong1) inout_io = (oe && attr_i.drive_strength[0]) ? out : 1'bz;
           Tests:       T22 T23 T24 
93         1/1              assign (pull0, pull1)     inout_io = (oe && !attr_i.drive_strength[0]) ? out : 1'bz;
           Tests:       T22 T23 T24 
94                          // pullup / pulldown termination
95         1/1              assign (weak0, weak1)     inout_io = attr_i.pull_en ? attr_i.pull_select : 1'bz;
           Tests:       T22 T23 T24 

---

Cond Coverage for Instance : tb.dut.u_padring.gen_mio_pads[28].u_mio_pad.gen_generic.u_impl_generic

	Total	Covered	Percent
Conditions	33	33	100.00
Logical	33	33	100.00
Non-Logical	0	0
Event	0	0

 LINE       51
 EXPRESSION (ie_i & ((~attr_i.input_disable)))
             --1-   ------------2------------

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Covered	T22,T23,T24
1	1	Covered	T1,T2,T3

 LINE       78
 EXPRESSION (ie ? inout_io : 1'bz)
             -1

-1-	Status	Tests
0	Covered	T22,T23,T24
1	Covered	T1,T2,T3

 LINE       80
 EXPRESSION (attr_i.invert ^ in_raw_o)
             ------1------   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T5,T36,T37
0	1	Covered	T5,T36,T37
1	0	Covered	T22,T23,T24
1	1	Covered	T22,T23,T24

 LINE       84
 EXPRESSION (out_i ^ attr_i.invert)
             --1--   ------2------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T22,T23,T24
1	0	Covered	T22,T23,T24
1	1	Covered	T22,T23,T24

 LINE       85
 EXPRESSION (oe_i & ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en))))
             --1-   ---------------------------------2---------------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T22,T23,T24
1	1	Covered	T22,T23,T24

 LINE       85
 SUB-EXPRESSION ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en)))
                 --------------------1-------------------   -----------2----------

-1-	-2-	Status	Tests
0	0	Covered	T22,T23,T24
0	1	Covered	T1,T2,T3
1	0	Covered	T22,T23,T24

 LINE       85
 SUB-EXPRESSION (attr_i.virt_od_en & ((~gen_bidir.out)))
                 --------1--------   ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T22,T23,T24
1	1	Covered	T22,T23,T24

 LINE       92
 EXPRESSION ((gen_bidir.oe && attr_i.drive_strength[0]) ? gen_bidir.out : 1'bz)
             ---------------------1--------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T22,T23,T24

 LINE       92
 SUB-EXPRESSION (gen_bidir.oe && attr_i.drive_strength[0])
                 ------1-----    ------------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T22,T23,T24
1	0	Covered	T22,T23,T24
1	1	Covered	T22,T23,T24

 LINE       93
 EXPRESSION ((gen_bidir.oe && ((!attr_i.drive_strength[0]))) ? gen_bidir.out : 1'bz)
             -----------------------1-----------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T22,T23,T24

 LINE       93
 SUB-EXPRESSION (gen_bidir.oe && ((!attr_i.drive_strength[0])))
                 ------1-----    --------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T22,T23,T24
1	1	Covered	T22,T23,T24

 LINE       95
 EXPRESSION (attr_i.pull_en ? attr_i.pull_select : 1'bz)
             -------1------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T22,T23,T24

---

Branch Coverage for Instance : tb.dut.u_padring.gen_mio_pads[28].u_mio_pad.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
TERNARY	78	2	2	100.00
TERNARY	92	2	2	100.00
TERNARY	93	2	2	100.00
TERNARY	95	2	2	100.00

78             assign in_raw_o = ie ? inout_io : 1'bz;
                                    -1-  
                                    ==>  
                                    ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T22,T23,T24

92             assign (strong0, strong1) inout_io = (oe && attr_i.drive_strength[0]) ? out : 1'bz;
                                                                                     -1-  
                                                                                     ==>  
                                                                                     ==>  

Branches:

-1-	Status	Tests
1	Covered	T22,T23,T24
0	Covered	T1,T2,T3

93             assign (pull0, pull1)     inout_io = (oe && !attr_i.drive_strength[0]) ? out : 1'bz;
                                                                                      -1-  
                                                                                      ==>  
                                                                                      ==>  

Branches:

-1-	Status	Tests
1	Covered	T22,T23,T24
0	Covered	T1,T2,T3

95             assign (weak0, weak1)     inout_io = attr_i.pull_en ? attr_i.pull_select : 1'bz;
                                                                   -1-  
                                                                   ==>  
                                                                   ==>  

Branches:

-1-	Status	Tests
1	Covered	T22,T23,T24
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_padring.gen_mio_pads[28].u_mio_pad.gen_generic.u_impl_generic

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AnalogNoScan_A	1021	1021	0	0

AnalogNoScan_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1021	1021	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T38	1	1	0	0
T39	1	1	0	0
T106	1	1	0	0

Line Coverage for Instance : tb.dut.u_padring.gen_mio_pads[29].u_mio_pad.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		8	8	100.00
CONT_ASSIGN	39	0	0
CONT_ASSIGN	51	1	1	100.00
CONT_ASSIGN	78	1	1	100.00
CONT_ASSIGN	80	1	1	100.00
CONT_ASSIGN	84	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	93	1	1	100.00
CONT_ASSIGN	95	1	1	100.00

38                        logic unused_sigs;
39         unreachable    assign unused_sigs = ^{attr_i.slew_rate,
40                                               attr_i.drive_strength[3:1],
41                                               attr_i.od_en,
42                                               attr_i.schmitt_en,
43                                               attr_i.keep_en,
44                                               scanmode_i,
45                                               pok_i};
46                        //VCS coverage on
47                        // pragma coverage on
48                      
49                        // Input enable (active-high)
50                        logic ie;
51         1/1            assign ie = ie_i & ~attr_i.input_disable;
           Tests:       T22 T23 T24 
52                      
53                        if (PadType == InputStd) begin : gen_input_only
54                          //VCS coverage off
55                          // pragma coverage off
56                          logic unused_in_sigs;
57                          assign unused_in_sigs = ^{out_i,
58                                                    oe_i,
59                                                    attr_i.virt_od_en,
60                                                    attr_i.drive_strength};
61                          //VCS coverage on
62                          // pragma coverage on
63                      
64                          assign in_raw_o = ie ? inout_io : 1'bz;
65                          // input inversion
66                          assign in_o = attr_i.invert ^ in_raw_o;
67                      
68                        // pulls are not supported by verilator
69                        `ifndef VERILATOR
70                          // pullup / pulldown termination
71                          assign (weak0, weak1) inout_io = attr_i.pull_en ? attr_i.pull_select : 1'bz;
72                        `endif
73                        end else if (PadType == BidirTol ||
74                                     PadType == DualBidirTol ||
75                                     PadType == BidirOd ||
76                                     PadType == BidirStd) begin : gen_bidir
77                      
78         1/1              assign in_raw_o = ie ? inout_io : 1'bz;
           Tests:       T38 T39 T7 
79                          // input inversion
80         1/1              assign in_o = attr_i.invert ^ in_raw_o;
           Tests:       T38 T39 T7 
81                      
82                          // virtual open drain emulation
83                          logic oe, out;
84         1/1              assign out = out_i ^ attr_i.invert;
           Tests:       T15 T17 T233 
85         1/1              assign oe  = oe_i & ((attr_i.virt_od_en & ~out) | ~attr_i.virt_od_en);
           Tests:       T15 T17 T21 
86                      
87                        // drive strength attributes are not supported by verilator
88                        `ifdef VERILATOR
89                          assign inout_io = (oe)   ? out : 1'bz;
90                        `else
91                          // different driver types
92         1/1              assign (strong0, strong1) inout_io = (oe && attr_i.drive_strength[0]) ? out : 1'bz;
           Tests:       T15 T17 T21 
93         1/1              assign (pull0, pull1)     inout_io = (oe && !attr_i.drive_strength[0]) ? out : 1'bz;
           Tests:       T15 T17 T21 
94                          // pullup / pulldown termination
95         1/1              assign (weak0, weak1)     inout_io = attr_i.pull_en ? attr_i.pull_select : 1'bz;
           Tests:       T22 T23 T24 

---

Cond Coverage for Instance : tb.dut.u_padring.gen_mio_pads[29].u_mio_pad.gen_generic.u_impl_generic

	Total	Covered	Percent
Conditions	33	33	100.00
Logical	33	33	100.00
Non-Logical	0	0
Event	0	0

 LINE       51
 EXPRESSION (ie_i & ((~attr_i.input_disable)))
             --1-   ------------2------------

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Covered	T22,T23,T24
1	1	Covered	T1,T2,T3

 LINE       78
 EXPRESSION (ie ? inout_io : 1'bz)
             -1

-1-	Status	Tests
0	Covered	T22,T23,T24
1	Covered	T1,T2,T3

 LINE       80
 EXPRESSION (attr_i.invert ^ in_raw_o)
             ------1------   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T38,T39,T7
0	1	Covered	T38,T39,T7
1	0	Covered	T22,T23,T216
1	1	Covered	T22,T23,T216

 LINE       84
 EXPRESSION (out_i ^ attr_i.invert)
             --1--   ------2------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T22,T23,T24
1	0	Covered	T15,T17,T233
1	1	Covered	T22,T23,T24

 LINE       85
 EXPRESSION (oe_i & ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en))))
             --1-   ---------------------------------2---------------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T22,T23,T24
1	1	Covered	T15,T17,T21

 LINE       85
 SUB-EXPRESSION ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en)))
                 --------------------1-------------------   -----------2----------

-1-	-2-	Status	Tests
0	0	Covered	T22,T23,T24
0	1	Covered	T1,T2,T3
1	0	Covered	T22,T23,T24

 LINE       85
 SUB-EXPRESSION (attr_i.virt_od_en & ((~gen_bidir.out)))
                 --------1--------   ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T22,T23,T24
1	1	Covered	T22,T23,T24

 LINE       92
 EXPRESSION ((gen_bidir.oe && attr_i.drive_strength[0]) ? gen_bidir.out : 1'bz)
             ---------------------1--------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T22,T23,T24

 LINE       92
 SUB-EXPRESSION (gen_bidir.oe && attr_i.drive_strength[0])
                 ------1-----    ------------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T22,T23,T24
1	0	Covered	T15,T17,T21
1	1	Covered	T22,T23,T24

 LINE       93
 EXPRESSION ((gen_bidir.oe && ((!attr_i.drive_strength[0]))) ? gen_bidir.out : 1'bz)
             -----------------------1-----------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T15,T17,T21

 LINE       93
 SUB-EXPRESSION (gen_bidir.oe && ((!attr_i.drive_strength[0])))
                 ------1-----    --------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T22,T23,T24
1	1	Covered	T15,T17,T21

 LINE       95
 EXPRESSION (attr_i.pull_en ? attr_i.pull_select : 1'bz)
             -------1------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T22,T23,T24

---

Branch Coverage for Instance : tb.dut.u_padring.gen_mio_pads[29].u_mio_pad.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
TERNARY	78	2	2	100.00
TERNARY	92	2	2	100.00
TERNARY	93	2	2	100.00
TERNARY	95	2	2	100.00

78             assign in_raw_o = ie ? inout_io : 1'bz;
                                    -1-  
                                    ==>  
                                    ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T22,T23,T24

92             assign (strong0, strong1) inout_io = (oe && attr_i.drive_strength[0]) ? out : 1'bz;
                                                                                     -1-  
                                                                                     ==>  
                                                                                     ==>  

Branches:

-1-	Status	Tests
1	Covered	T22,T23,T24
0	Covered	T1,T2,T3

93             assign (pull0, pull1)     inout_io = (oe && !attr_i.drive_strength[0]) ? out : 1'bz;
                                                                                      -1-  
                                                                                      ==>  
                                                                                      ==>  

Branches:

-1-	Status	Tests
1	Covered	T15,T17,T21
0	Covered	T1,T2,T3

95             assign (weak0, weak1)     inout_io = attr_i.pull_en ? attr_i.pull_select : 1'bz;
                                                                   -1-  
                                                                   ==>  
                                                                   ==>  

Branches:

-1-	Status	Tests
1	Covered	T22,T23,T24
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_padring.gen_mio_pads[29].u_mio_pad.gen_generic.u_impl_generic

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AnalogNoScan_A	1021	1021	0	0

AnalogNoScan_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1021	1021	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T38	1	1	0	0
T39	1	1	0	0
T106	1	1	0	0

Line Coverage for Instance : tb.dut.u_padring.gen_mio_pads[30].u_mio_pad.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		8	8	100.00
CONT_ASSIGN	39	0	0
CONT_ASSIGN	51	1	1	100.00
CONT_ASSIGN	78	1	1	100.00
CONT_ASSIGN	80	1	1	100.00
CONT_ASSIGN	84	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	93	1	1	100.00
CONT_ASSIGN	95	1	1	100.00

38                        logic unused_sigs;
39         unreachable    assign unused_sigs = ^{attr_i.slew_rate,
40                                               attr_i.drive_strength[3:1],
41                                               attr_i.od_en,
42                                               attr_i.schmitt_en,
43                                               attr_i.keep_en,
44                                               scanmode_i,
45                                               pok_i};
46                        //VCS coverage on
47                        // pragma coverage on
48                      
49                        // Input enable (active-high)
50                        logic ie;
51         1/1            assign ie = ie_i & ~attr_i.input_disable;
           Tests:       T22 T23 T24 
52                      
53                        if (PadType == InputStd) begin : gen_input_only
54                          //VCS coverage off
55                          // pragma coverage off
56                          logic unused_in_sigs;
57                          assign unused_in_sigs = ^{out_i,
58                                                    oe_i,
59                                                    attr_i.virt_od_en,
60                                                    attr_i.drive_strength};
61                          //VCS coverage on
62                          // pragma coverage on
63                      
64                          assign in_raw_o = ie ? inout_io : 1'bz;
65                          // input inversion
66                          assign in_o = attr_i.invert ^ in_raw_o;
67                      
68                        // pulls are not supported by verilator
69                        `ifndef VERILATOR
70                          // pullup / pulldown termination
71                          assign (weak0, weak1) inout_io = attr_i.pull_en ? attr_i.pull_select : 1'bz;
72                        `endif
73                        end else if (PadType == BidirTol ||
74                                     PadType == DualBidirTol ||
75                                     PadType == BidirOd ||
76                                     PadType == BidirStd) begin : gen_bidir
77                      
78         1/1              assign in_raw_o = ie ? inout_io : 1'bz;
           Tests:       T40 T92 T41 
79                          // input inversion
80         1/1              assign in_o = attr_i.invert ^ in_raw_o;
           Tests:       T40 T41 T42 
81                      
82                          // virtual open drain emulation
83                          logic oe, out;
84         1/1              assign out = out_i ^ attr_i.invert;
           Tests:       T22 T23 T24 
85         1/1              assign oe  = oe_i & ((attr_i.virt_od_en & ~out) | ~attr_i.virt_od_en);
           Tests:       T21 T49 T22 
86                      
87                        // drive strength attributes are not supported by verilator
88                        `ifdef VERILATOR
89                          assign inout_io = (oe)   ? out : 1'bz;
90                        `else
91                          // different driver types
92         1/1              assign (strong0, strong1) inout_io = (oe && attr_i.drive_strength[0]) ? out : 1'bz;
           Tests:       T21 T49 T22 
93         1/1              assign (pull0, pull1)     inout_io = (oe && !attr_i.drive_strength[0]) ? out : 1'bz;
           Tests:       T21 T49 T22 
94                          // pullup / pulldown termination
95         1/1              assign (weak0, weak1)     inout_io = attr_i.pull_en ? attr_i.pull_select : 1'bz;
           Tests:       T22 T23 T24 

---

Cond Coverage for Instance : tb.dut.u_padring.gen_mio_pads[30].u_mio_pad.gen_generic.u_impl_generic

	Total	Covered	Percent
Conditions	33	33	100.00
Logical	33	33	100.00
Non-Logical	0	0
Event	0	0

 LINE       51
 EXPRESSION (ie_i & ((~attr_i.input_disable)))
             --1-   ------------2------------

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Covered	T22,T23,T24
1	1	Covered	T1,T2,T3

 LINE       78
 EXPRESSION (ie ? inout_io : 1'bz)
             -1

-1-	Status	Tests
0	Covered	T22,T23,T24
1	Covered	T1,T2,T3

 LINE       80
 EXPRESSION (attr_i.invert ^ in_raw_o)
             ------1------   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T44,T36,T47
1	0	Covered	T22,T23,T24
1	1	Covered	T22,T23,T24

 LINE       84
 EXPRESSION (out_i ^ attr_i.invert)
             --1--   ------2------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T22,T23,T24
1	0	Covered	T22,T23,T24
1	1	Covered	T22,T23,T24

 LINE       85
 EXPRESSION (oe_i & ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en))))
             --1-   ---------------------------------2---------------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T22,T23,T24
1	1	Covered	T21,T49,T22

 LINE       85
 SUB-EXPRESSION ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en)))
                 --------------------1-------------------   -----------2----------

-1-	-2-	Status	Tests
0	0	Covered	T22,T23,T24
0	1	Covered	T1,T2,T3
1	0	Covered	T22,T23,T24

 LINE       85
 SUB-EXPRESSION (attr_i.virt_od_en & ((~gen_bidir.out)))
                 --------1--------   ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T22,T23,T24
1	1	Covered	T22,T23,T24

 LINE       92
 EXPRESSION ((gen_bidir.oe && attr_i.drive_strength[0]) ? gen_bidir.out : 1'bz)
             ---------------------1--------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T22,T23,T24

 LINE       92
 SUB-EXPRESSION (gen_bidir.oe && attr_i.drive_strength[0])
                 ------1-----    ------------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T22,T23,T24
1	0	Covered	T21,T49,T22
1	1	Covered	T22,T23,T24

 LINE       93
 EXPRESSION ((gen_bidir.oe && ((!attr_i.drive_strength[0]))) ? gen_bidir.out : 1'bz)
             -----------------------1-----------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T21,T49,T22

 LINE       93
 SUB-EXPRESSION (gen_bidir.oe && ((!attr_i.drive_strength[0])))
                 ------1-----    --------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T22,T23,T24
1	1	Covered	T21,T49,T22

 LINE       95
 EXPRESSION (attr_i.pull_en ? attr_i.pull_select : 1'bz)
             -------1------

-1-	Status	Tests
0	Covered	T22,T23,T24
1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_padring.gen_mio_pads[30].u_mio_pad.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
TERNARY	78	2	2	100.00
TERNARY	92	2	2	100.00
TERNARY	93	2	2	100.00
TERNARY	95	2	2	100.00

78             assign in_raw_o = ie ? inout_io : 1'bz;
                                    -1-  
                                    ==>  
                                    ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T22,T23,T24

92             assign (strong0, strong1) inout_io = (oe && attr_i.drive_strength[0]) ? out : 1'bz;
                                                                                     -1-  
                                                                                     ==>  
                                                                                     ==>  

Branches:

-1-	Status	Tests
1	Covered	T22,T23,T24
0	Covered	T1,T2,T3

93             assign (pull0, pull1)     inout_io = (oe && !attr_i.drive_strength[0]) ? out : 1'bz;
                                                                                      -1-  
                                                                                      ==>  
                                                                                      ==>  

Branches:

-1-	Status	Tests
1	Covered	T21,T49,T22
0	Covered	T1,T2,T3

95             assign (weak0, weak1)     inout_io = attr_i.pull_en ? attr_i.pull_select : 1'bz;
                                                                   -1-  
                                                                   ==>  
                                                                   ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T22,T23,T24

---

Assert Coverage for Instance : tb.dut.u_padring.gen_mio_pads[30].u_mio_pad.gen_generic.u_impl_generic

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AnalogNoScan_A	1021	1021	0	0

AnalogNoScan_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1021	1021	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T38	1	1	0	0
T39	1	1	0	0
T106	1	1	0	0

Line Coverage for Instance : tb.dut.u_padring.gen_mio_pads[31].u_mio_pad.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		8	8	100.00
CONT_ASSIGN	39	0	0
CONT_ASSIGN	51	1	1	100.00
CONT_ASSIGN	78	1	1	100.00
CONT_ASSIGN	80	1	1	100.00
CONT_ASSIGN	84	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	93	1	1	100.00
CONT_ASSIGN	95	1	1	100.00

38                        logic unused_sigs;
39         unreachable    assign unused_sigs = ^{attr_i.slew_rate,
40                                               attr_i.drive_strength[3:1],
41                                               attr_i.od_en,
42                                               attr_i.schmitt_en,
43                                               attr_i.keep_en,
44                                               scanmode_i,
45                                               pok_i};
46                        //VCS coverage on
47                        // pragma coverage on
48                      
49                        // Input enable (active-high)
50                        logic ie;
51         1/1            assign ie = ie_i & ~attr_i.input_disable;
           Tests:       T22 T23 T24 
52                      
53                        if (PadType == InputStd) begin : gen_input_only
54                          //VCS coverage off
55                          // pragma coverage off
56                          logic unused_in_sigs;
57                          assign unused_in_sigs = ^{out_i,
58                                                    oe_i,
59                                                    attr_i.virt_od_en,
60                                                    attr_i.drive_strength};
61                          //VCS coverage on
62                          // pragma coverage on
63                      
64                          assign in_raw_o = ie ? inout_io : 1'bz;
65                          // input inversion
66                          assign in_o = attr_i.invert ^ in_raw_o;
67                      
68                        // pulls are not supported by verilator
69                        `ifndef VERILATOR
70                          // pullup / pulldown termination
71                          assign (weak0, weak1) inout_io = attr_i.pull_en ? attr_i.pull_select : 1'bz;
72                        `endif
73                        end else if (PadType == BidirTol ||
74                                     PadType == DualBidirTol ||
75                                     PadType == BidirOd ||
76                                     PadType == BidirStd) begin : gen_bidir
77                      
78         1/1              assign in_raw_o = ie ? inout_io : 1'bz;
           Tests:       T28 T33 T15 
79                          // input inversion
80         1/1              assign in_o = attr_i.invert ^ in_raw_o;
           Tests:       T28 T33 T15 
81                      
82                          // virtual open drain emulation
83                          logic oe, out;
84         1/1              assign out = out_i ^ attr_i.invert;
           Tests:       T28 T15 T17 
85         1/1              assign oe  = oe_i & ((attr_i.virt_od_en & ~out) | ~attr_i.virt_od_en);
           Tests:       T28 T15 T17 
86                      
87                        // drive strength attributes are not supported by verilator
88                        `ifdef VERILATOR
89                          assign inout_io = (oe)   ? out : 1'bz;
90                        `else
91                          // different driver types
92         1/1              assign (strong0, strong1) inout_io = (oe && attr_i.drive_strength[0]) ? out : 1'bz;
           Tests:       T28 T15 T17 
93         1/1              assign (pull0, pull1)     inout_io = (oe && !attr_i.drive_strength[0]) ? out : 1'bz;
           Tests:       T28 T15 T17 
94                          // pullup / pulldown termination
95         1/1              assign (weak0, weak1)     inout_io = attr_i.pull_en ? attr_i.pull_select : 1'bz;
           Tests:       T22 T23 T24 

---

Cond Coverage for Instance : tb.dut.u_padring.gen_mio_pads[31].u_mio_pad.gen_generic.u_impl_generic

	Total	Covered	Percent
Conditions	33	33	100.00
Logical	33	33	100.00
Non-Logical	0	0
Event	0	0

 LINE       51
 EXPRESSION (ie_i & ((~attr_i.input_disable)))
             --1-   ------------2------------

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Covered	T22,T23,T24
1	1	Covered	T1,T2,T3

 LINE       78
 EXPRESSION (ie ? inout_io : 1'bz)
             -1

-1-	Status	Tests
0	Covered	T22,T23,T24
1	Covered	T1,T2,T3

 LINE       80
 EXPRESSION (attr_i.invert ^ in_raw_o)
             ------1------   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T28,T33,T15
0	1	Covered	T28,T33,T15
1	0	Covered	T22,T23,T24
1	1	Covered	T22,T23,T24

 LINE       84
 EXPRESSION (out_i ^ attr_i.invert)
             --1--   ------2------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T22,T23,T24
1	0	Covered	T28,T15,T17
1	1	Covered	T22,T23,T24

 LINE       85
 EXPRESSION (oe_i & ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en))))
             --1-   ---------------------------------2---------------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T22,T23,T24
1	1	Covered	T28,T15,T17

 LINE       85
 SUB-EXPRESSION ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en)))
                 --------------------1-------------------   -----------2----------

-1-	-2-	Status	Tests
0	0	Covered	T22,T23,T24
0	1	Covered	T1,T2,T3
1	0	Covered	T22,T23,T24

 LINE       85
 SUB-EXPRESSION (attr_i.virt_od_en & ((~gen_bidir.out)))
                 --------1--------   ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T22,T23,T24
1	1	Covered	T22,T23,T24

 LINE       92
 EXPRESSION ((gen_bidir.oe && attr_i.drive_strength[0]) ? gen_bidir.out : 1'bz)
             ---------------------1--------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T22,T23,T24

 LINE       92
 SUB-EXPRESSION (gen_bidir.oe && attr_i.drive_strength[0])
                 ------1-----    ------------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T22,T23,T24
1	0	Covered	T28,T15,T17
1	1	Covered	T22,T23,T24

 LINE       93
 EXPRESSION ((gen_bidir.oe && ((!attr_i.drive_strength[0]))) ? gen_bidir.out : 1'bz)
             -----------------------1-----------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T28,T15,T17

 LINE       93
 SUB-EXPRESSION (gen_bidir.oe && ((!attr_i.drive_strength[0])))
                 ------1-----    --------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T22,T23,T24
1	1	Covered	T28,T15,T17

 LINE       95
 EXPRESSION (attr_i.pull_en ? attr_i.pull_select : 1'bz)
             -------1------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T22,T23,T24

---

Branch Coverage for Instance : tb.dut.u_padring.gen_mio_pads[31].u_mio_pad.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
TERNARY	78	2	2	100.00
TERNARY	92	2	2	100.00
TERNARY	93	2	2	100.00
TERNARY	95	2	2	100.00

78             assign in_raw_o = ie ? inout_io : 1'bz;
                                    -1-  
                                    ==>  
                                    ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T22,T23,T24

92             assign (strong0, strong1) inout_io = (oe && attr_i.drive_strength[0]) ? out : 1'bz;
                                                                                     -1-  
                                                                                     ==>  
                                                                                     ==>  

Branches:

-1-	Status	Tests
1	Covered	T22,T23,T24
0	Covered	T1,T2,T3

93             assign (pull0, pull1)     inout_io = (oe && !attr_i.drive_strength[0]) ? out : 1'bz;
                                                                                      -1-  
                                                                                      ==>  
                                                                                      ==>  

Branches:

-1-	Status	Tests
1	Covered	T28,T15,T17
0	Covered	T1,T2,T3

95             assign (weak0, weak1)     inout_io = attr_i.pull_en ? attr_i.pull_select : 1'bz;
                                                                   -1-  
                                                                   ==>  
                                                                   ==>  

Branches:

-1-	Status	Tests
1	Covered	T22,T23,T24
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_padring.gen_mio_pads[31].u_mio_pad.gen_generic.u_impl_generic

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AnalogNoScan_A	1021	1021	0	0

AnalogNoScan_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1021	1021	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T38	1	1	0	0
T39	1	1	0	0
T106	1	1	0	0

Line Coverage for Instance : tb.dut.u_padring.gen_mio_pads[32].u_mio_pad.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		8	8	100.00
CONT_ASSIGN	39	0	0
CONT_ASSIGN	51	1	1	100.00
CONT_ASSIGN	78	1	1	100.00
CONT_ASSIGN	80	1	1	100.00
CONT_ASSIGN	84	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	93	1	1	100.00
CONT_ASSIGN	95	1	1	100.00

38                        logic unused_sigs;
39         unreachable    assign unused_sigs = ^{attr_i.slew_rate,
40                                               attr_i.drive_strength[3:1],
41                                               attr_i.od_en,
42                                               attr_i.schmitt_en,
43                                               attr_i.keep_en,
44                                               scanmode_i,
45                                               pok_i};
46                        //VCS coverage on
47                        // pragma coverage on
48                      
49                        // Input enable (active-high)
50                        logic ie;
51         1/1            assign ie = ie_i & ~attr_i.input_disable;
           Tests:       T22 T23 T24 
52                      
53                        if (PadType == InputStd) begin : gen_input_only
54                          //VCS coverage off
55                          // pragma coverage off
56                          logic unused_in_sigs;
57                          assign unused_in_sigs = ^{out_i,
58                                                    oe_i,
59                                                    attr_i.virt_od_en,
60                                                    attr_i.drive_strength};
61                          //VCS coverage on
62                          // pragma coverage on
63                      
64                          assign in_raw_o = ie ? inout_io : 1'bz;
65                          // input inversion
66                          assign in_o = attr_i.invert ^ in_raw_o;
67                      
68                        // pulls are not supported by verilator
69                        `ifndef VERILATOR
70                          // pullup / pulldown termination
71                          assign (weak0, weak1) inout_io = attr_i.pull_en ? attr_i.pull_select : 1'bz;
72                        `endif
73                        end else if (PadType == BidirTol ||
74                                     PadType == DualBidirTol ||
75                                     PadType == BidirOd ||
76                                     PadType == BidirStd) begin : gen_bidir
77                      
78         1/1              assign in_raw_o = ie ? inout_io : 1'bz;
           Tests:       T28 T43 T30 
79                          // input inversion
80         1/1              assign in_o = attr_i.invert ^ in_raw_o;
           Tests:       T28 T43 T30 
81                      
82                          // virtual open drain emulation
83                          logic oe, out;
84         1/1              assign out = out_i ^ attr_i.invert;
           Tests:       T28 T43 T77 
85         1/1              assign oe  = oe_i & ((attr_i.virt_od_en & ~out) | ~attr_i.virt_od_en);
           Tests:       T28 T43 T77 
86                      
87                        // drive strength attributes are not supported by verilator
88                        `ifdef VERILATOR
89                          assign inout_io = (oe)   ? out : 1'bz;
90                        `else
91                          // different driver types
92         1/1              assign (strong0, strong1) inout_io = (oe && attr_i.drive_strength[0]) ? out : 1'bz;
           Tests:       T28 T43 T77 
93         1/1              assign (pull0, pull1)     inout_io = (oe && !attr_i.drive_strength[0]) ? out : 1'bz;
           Tests:       T28 T43 T77 
94                          // pullup / pulldown termination
95         1/1              assign (weak0, weak1)     inout_io = attr_i.pull_en ? attr_i.pull_select : 1'bz;
           Tests:       T22 T23 T24 

---

Cond Coverage for Instance : tb.dut.u_padring.gen_mio_pads[32].u_mio_pad.gen_generic.u_impl_generic

	Total	Covered	Percent
Conditions	33	33	100.00
Logical	33	33	100.00
Non-Logical	0	0
Event	0	0

 LINE       51
 EXPRESSION (ie_i & ((~attr_i.input_disable)))
             --1-   ------------2------------

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Covered	T22,T23,T24
1	1	Covered	T1,T2,T3

 LINE       78
 EXPRESSION (ie ? inout_io : 1'bz)
             -1

-1-	Status	Tests
0	Covered	T22,T23,T24
1	Covered	T1,T2,T3

 LINE       80
 EXPRESSION (attr_i.invert ^ in_raw_o)
             ------1------   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T28,T43,T30
0	1	Covered	T28,T43,T77
1	0	Covered	T22,T23,T216
1	1	Covered	T22,T23,T24

 LINE       84
 EXPRESSION (out_i ^ attr_i.invert)
             --1--   ------2------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T22,T23,T24
1	0	Covered	T28,T43,T77
1	1	Covered	T22,T23,T24

 LINE       85
 EXPRESSION (oe_i & ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en))))
             --1-   ---------------------------------2---------------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T22,T23,T216
1	1	Covered	T28,T43,T77

 LINE       85
 SUB-EXPRESSION ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en)))
                 --------------------1-------------------   -----------2----------

-1-	-2-	Status	Tests
0	0	Covered	T22,T23,T24
0	1	Covered	T1,T2,T3
1	0	Covered	T22,T23,T24

 LINE       85
 SUB-EXPRESSION (attr_i.virt_od_en & ((~gen_bidir.out)))
                 --------1--------   ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T22,T23,T24
1	1	Covered	T22,T23,T24

 LINE       92
 EXPRESSION ((gen_bidir.oe && attr_i.drive_strength[0]) ? gen_bidir.out : 1'bz)
             ---------------------1--------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T22,T23,T24

 LINE       92
 SUB-EXPRESSION (gen_bidir.oe && attr_i.drive_strength[0])
                 ------1-----    ------------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T22,T23,T24
1	0	Covered	T28,T43,T77
1	1	Covered	T22,T23,T24

 LINE       93
 EXPRESSION ((gen_bidir.oe && ((!attr_i.drive_strength[0]))) ? gen_bidir.out : 1'bz)
             -----------------------1-----------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T28,T43,T77

 LINE       93
 SUB-EXPRESSION (gen_bidir.oe && ((!attr_i.drive_strength[0])))
                 ------1-----    --------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T22,T23,T24
1	1	Covered	T28,T43,T77

 LINE       95
 EXPRESSION (attr_i.pull_en ? attr_i.pull_select : 1'bz)
             -------1------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T22,T23,T24

---

Branch Coverage for Instance : tb.dut.u_padring.gen_mio_pads[32].u_mio_pad.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
TERNARY	78	2	2	100.00
TERNARY	92	2	2	100.00
TERNARY	93	2	2	100.00
TERNARY	95	2	2	100.00

78             assign in_raw_o = ie ? inout_io : 1'bz;
                                    -1-  
                                    ==>  
                                    ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T22,T23,T24

92             assign (strong0, strong1) inout_io = (oe && attr_i.drive_strength[0]) ? out : 1'bz;
                                                                                     -1-  
                                                                                     ==>  
                                                                                     ==>  

Branches:

-1-	Status	Tests
1	Covered	T22,T23,T24
0	Covered	T1,T2,T3

93             assign (pull0, pull1)     inout_io = (oe && !attr_i.drive_strength[0]) ? out : 1'bz;
                                                                                      -1-  
                                                                                      ==>  
                                                                                      ==>  

Branches:

-1-	Status	Tests
1	Covered	T28,T43,T77
0	Covered	T1,T2,T3

95             assign (weak0, weak1)     inout_io = attr_i.pull_en ? attr_i.pull_select : 1'bz;
                                                                   -1-  
                                                                   ==>  
                                                                   ==>  

Branches:

-1-	Status	Tests
1	Covered	T22,T23,T24
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_padring.gen_mio_pads[32].u_mio_pad.gen_generic.u_impl_generic

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AnalogNoScan_A	1021	1021	0	0

AnalogNoScan_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1021	1021	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T38	1	1	0	0
T39	1	1	0	0
T106	1	1	0	0

Line Coverage for Instance : tb.dut.u_padring.gen_mio_pads[33].u_mio_pad.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		8	8	100.00
CONT_ASSIGN	39	0	0
CONT_ASSIGN	51	1	1	100.00
CONT_ASSIGN	78	1	1	100.00
CONT_ASSIGN	80	1	1	100.00
CONT_ASSIGN	84	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	93	1	1	100.00
CONT_ASSIGN	95	1	1	100.00

38                        logic unused_sigs;
39         unreachable    assign unused_sigs = ^{attr_i.slew_rate,
40                                               attr_i.drive_strength[3:1],
41                                               attr_i.od_en,
42                                               attr_i.schmitt_en,
43                                               attr_i.keep_en,
44                                               scanmode_i,
45                                               pok_i};
46                        //VCS coverage on
47                        // pragma coverage on
48                      
49                        // Input enable (active-high)
50                        logic ie;
51         1/1            assign ie = ie_i & ~attr_i.input_disable;
           Tests:       T22 T23 T24 
52                      
53                        if (PadType == InputStd) begin : gen_input_only
54                          //VCS coverage off
55                          // pragma coverage off
56                          logic unused_in_sigs;
57                          assign unused_in_sigs = ^{out_i,
58                                                    oe_i,
59                                                    attr_i.virt_od_en,
60                                                    attr_i.drive_strength};
61                          //VCS coverage on
62                          // pragma coverage on
63                      
64                          assign in_raw_o = ie ? inout_io : 1'bz;
65                          // input inversion
66                          assign in_o = attr_i.invert ^ in_raw_o;
67                      
68                        // pulls are not supported by verilator
69                        `ifndef VERILATOR
70                          // pullup / pulldown termination
71                          assign (weak0, weak1) inout_io = attr_i.pull_en ? attr_i.pull_select : 1'bz;
72                        `endif
73                        end else if (PadType == BidirTol ||
74                                     PadType == DualBidirTol ||
75                                     PadType == BidirOd ||
76                                     PadType == BidirStd) begin : gen_bidir
77                      
78         1/1              assign in_raw_o = ie ? inout_io : 1'bz;
           Tests:       T28 T43 T30 
79                          // input inversion
80         1/1              assign in_o = attr_i.invert ^ in_raw_o;
           Tests:       T28 T43 T30 
81                      
82                          // virtual open drain emulation
83                          logic oe, out;
84         1/1              assign out = out_i ^ attr_i.invert;
           Tests:       T28 T43 T77 
85         1/1              assign oe  = oe_i & ((attr_i.virt_od_en & ~out) | ~attr_i.virt_od_en);
           Tests:       T28 T43 T77 
86                      
87                        // drive strength attributes are not supported by verilator
88                        `ifdef VERILATOR
89                          assign inout_io = (oe)   ? out : 1'bz;
90                        `else
91                          // different driver types
92         1/1              assign (strong0, strong1) inout_io = (oe && attr_i.drive_strength[0]) ? out : 1'bz;
           Tests:       T28 T43 T77 
93         1/1              assign (pull0, pull1)     inout_io = (oe && !attr_i.drive_strength[0]) ? out : 1'bz;
           Tests:       T28 T43 T77 
94                          // pullup / pulldown termination
95         1/1              assign (weak0, weak1)     inout_io = attr_i.pull_en ? attr_i.pull_select : 1'bz;
           Tests:       T22 T23 T24 

---

Cond Coverage for Instance : tb.dut.u_padring.gen_mio_pads[33].u_mio_pad.gen_generic.u_impl_generic

	Total	Covered	Percent
Conditions	33	33	100.00
Logical	33	33	100.00
Non-Logical	0	0
Event	0	0

 LINE       51
 EXPRESSION (ie_i & ((~attr_i.input_disable)))
             --1-   ------------2------------

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Covered	T22,T23,T24
1	1	Covered	T1,T2,T3

 LINE       78
 EXPRESSION (ie ? inout_io : 1'bz)
             -1

-1-	Status	Tests
0	Covered	T22,T23,T24
1	Covered	T1,T2,T3

 LINE       80
 EXPRESSION (attr_i.invert ^ in_raw_o)
             ------1------   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T28,T43,T30
0	1	Covered	T28,T43,T77
1	0	Covered	T23,T24,T216
1	1	Covered	T23,T24,T216

 LINE       84
 EXPRESSION (out_i ^ attr_i.invert)
             --1--   ------2------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T22,T23,T24
1	0	Covered	T28,T43,T77
1	1	Covered	T22,T23,T24

 LINE       85
 EXPRESSION (oe_i & ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en))))
             --1-   ---------------------------------2---------------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T22,T23,T24
1	1	Covered	T28,T43,T77

 LINE       85
 SUB-EXPRESSION ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en)))
                 --------------------1-------------------   -----------2----------

-1-	-2-	Status	Tests
0	0	Covered	T22,T23,T24
0	1	Covered	T1,T2,T3
1	0	Covered	T22,T23,T24

 LINE       85
 SUB-EXPRESSION (attr_i.virt_od_en & ((~gen_bidir.out)))
                 --------1--------   ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T22,T23,T24
1	1	Covered	T22,T23,T24

 LINE       92
 EXPRESSION ((gen_bidir.oe && attr_i.drive_strength[0]) ? gen_bidir.out : 1'bz)
             ---------------------1--------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T22,T23,T24

 LINE       92
 SUB-EXPRESSION (gen_bidir.oe && attr_i.drive_strength[0])
                 ------1-----    ------------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T22,T23,T24
1	0	Covered	T28,T43,T77
1	1	Covered	T22,T23,T24

 LINE       93
 EXPRESSION ((gen_bidir.oe && ((!attr_i.drive_strength[0]))) ? gen_bidir.out : 1'bz)
             -----------------------1-----------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T28,T43,T77

 LINE       93
 SUB-EXPRESSION (gen_bidir.oe && ((!attr_i.drive_strength[0])))
                 ------1-----    --------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T22,T23,T24
1	1	Covered	T28,T43,T77

 LINE       95
 EXPRESSION (attr_i.pull_en ? attr_i.pull_select : 1'bz)
             -------1------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T22,T23,T24

---

Branch Coverage for Instance : tb.dut.u_padring.gen_mio_pads[33].u_mio_pad.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
TERNARY	78	2	2	100.00
TERNARY	92	2	2	100.00
TERNARY	93	2	2	100.00
TERNARY	95	2	2	100.00

78             assign in_raw_o = ie ? inout_io : 1'bz;
                                    -1-  
                                    ==>  
                                    ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T22,T23,T24

92             assign (strong0, strong1) inout_io = (oe && attr_i.drive_strength[0]) ? out : 1'bz;
                                                                                     -1-  
                                                                                     ==>  
                                                                                     ==>  

Branches:

-1-	Status	Tests
1	Covered	T22,T23,T24
0	Covered	T1,T2,T3

93             assign (pull0, pull1)     inout_io = (oe && !attr_i.drive_strength[0]) ? out : 1'bz;
                                                                                      -1-  
                                                                                      ==>  
                                                                                      ==>  

Branches:

-1-	Status	Tests
1	Covered	T28,T43,T77
0	Covered	T1,T2,T3

95             assign (weak0, weak1)     inout_io = attr_i.pull_en ? attr_i.pull_select : 1'bz;
                                                                   -1-  
                                                                   ==>  
                                                                   ==>  

Branches:

-1-	Status	Tests
1	Covered	T22,T23,T24
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_padring.gen_mio_pads[33].u_mio_pad.gen_generic.u_impl_generic

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AnalogNoScan_A	1021	1021	0	0

AnalogNoScan_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1021	1021	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T38	1	1	0	0
T39	1	1	0	0
T106	1	1	0	0

Line Coverage for Instance : tb.dut.u_padring.gen_mio_pads[34].u_mio_pad.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		8	8	100.00
CONT_ASSIGN	39	0	0
CONT_ASSIGN	51	1	1	100.00
CONT_ASSIGN	78	1	1	100.00
CONT_ASSIGN	80	1	1	100.00
CONT_ASSIGN	84	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	93	1	1	100.00
CONT_ASSIGN	95	1	1	100.00

38                        logic unused_sigs;
39         unreachable    assign unused_sigs = ^{attr_i.slew_rate,
40                                               attr_i.drive_strength[3:1],
41                                               attr_i.od_en,
42                                               attr_i.schmitt_en,
43                                               attr_i.keep_en,
44                                               scanmode_i,
45                                               pok_i};
46                        //VCS coverage on
47                        // pragma coverage on
48                      
49                        // Input enable (active-high)
50                        logic ie;
51         1/1            assign ie = ie_i & ~attr_i.input_disable;
           Tests:       T22 T23 T24 
52                      
53                        if (PadType == InputStd) begin : gen_input_only
54                          //VCS coverage off
55                          // pragma coverage off
56                          logic unused_in_sigs;
57                          assign unused_in_sigs = ^{out_i,
58                                                    oe_i,
59                                                    attr_i.virt_od_en,
60                                                    attr_i.drive_strength};
61                          //VCS coverage on
62                          // pragma coverage on
63                      
64                          assign in_raw_o = ie ? inout_io : 1'bz;
65                          // input inversion
66                          assign in_o = attr_i.invert ^ in_raw_o;
67                      
68                        // pulls are not supported by verilator
69                        `ifndef VERILATOR
70                          // pullup / pulldown termination
71                          assign (weak0, weak1) inout_io = attr_i.pull_en ? attr_i.pull_select : 1'bz;
72                        `endif
73                        end else if (PadType == BidirTol ||
74                                     PadType == DualBidirTol ||
75                                     PadType == BidirOd ||
76                                     PadType == BidirStd) begin : gen_bidir
77                      
78         1/1              assign in_raw_o = ie ? inout_io : 1'bz;
           Tests:       T28 T43 T30 
79                          // input inversion
80         1/1              assign in_o = attr_i.invert ^ in_raw_o;
           Tests:       T28 T43 T30 
81                      
82                          // virtual open drain emulation
83                          logic oe, out;
84         1/1              assign out = out_i ^ attr_i.invert;
           Tests:       T28 T43 T77 
85         1/1              assign oe  = oe_i & ((attr_i.virt_od_en & ~out) | ~attr_i.virt_od_en);
           Tests:       T28 T43 T77 
86                      
87                        // drive strength attributes are not supported by verilator
88                        `ifdef VERILATOR
89                          assign inout_io = (oe)   ? out : 1'bz;
90                        `else
91                          // different driver types
92         1/1              assign (strong0, strong1) inout_io = (oe && attr_i.drive_strength[0]) ? out : 1'bz;
           Tests:       T28 T43 T77 
93         1/1              assign (pull0, pull1)     inout_io = (oe && !attr_i.drive_strength[0]) ? out : 1'bz;
           Tests:       T28 T43 T77 
94                          // pullup / pulldown termination
95         1/1              assign (weak0, weak1)     inout_io = attr_i.pull_en ? attr_i.pull_select : 1'bz;
           Tests:       T22 T23 T24 

---

Cond Coverage for Instance : tb.dut.u_padring.gen_mio_pads[34].u_mio_pad.gen_generic.u_impl_generic

	Total	Covered	Percent
Conditions	33	33	100.00
Logical	33	33	100.00
Non-Logical	0	0
Event	0	0

 LINE       51
 EXPRESSION (ie_i & ((~attr_i.input_disable)))
             --1-   ------------2------------

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Covered	T22,T23,T24
1	1	Covered	T1,T2,T3

 LINE       78
 EXPRESSION (ie ? inout_io : 1'bz)
             -1

-1-	Status	Tests
0	Covered	T22,T23,T24
1	Covered	T1,T2,T3

 LINE       80
 EXPRESSION (attr_i.invert ^ in_raw_o)
             ------1------   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T28,T43,T30
0	1	Covered	T28,T43,T77
1	0	Covered	T22,T23,T24
1	1	Covered	T22,T23,T24

 LINE       84
 EXPRESSION (out_i ^ attr_i.invert)
             --1--   ------2------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T22,T23,T24
1	0	Covered	T28,T43,T77
1	1	Covered	T22,T23,T24

 LINE       85
 EXPRESSION (oe_i & ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en))))
             --1-   ---------------------------------2---------------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T22,T23,T24
1	1	Covered	T28,T43,T77

 LINE       85
 SUB-EXPRESSION ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en)))
                 --------------------1-------------------   -----------2----------

-1-	-2-	Status	Tests
0	0	Covered	T22,T23,T24
0	1	Covered	T1,T2,T3
1	0	Covered	T22,T23,T24

 LINE       85
 SUB-EXPRESSION (attr_i.virt_od_en & ((~gen_bidir.out)))
                 --------1--------   ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T22,T23,T24
1	1	Covered	T22,T23,T24

 LINE       92
 EXPRESSION ((gen_bidir.oe && attr_i.drive_strength[0]) ? gen_bidir.out : 1'bz)
             ---------------------1--------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T22,T23,T24

 LINE       92
 SUB-EXPRESSION (gen_bidir.oe && attr_i.drive_strength[0])
                 ------1-----    ------------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T22,T23,T24
1	0	Covered	T28,T43,T77
1	1	Covered	T22,T23,T24

 LINE       93
 EXPRESSION ((gen_bidir.oe && ((!attr_i.drive_strength[0]))) ? gen_bidir.out : 1'bz)
             -----------------------1-----------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T28,T43,T77

 LINE       93
 SUB-EXPRESSION (gen_bidir.oe && ((!attr_i.drive_strength[0])))
                 ------1-----    --------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T22,T23,T24
1	1	Covered	T28,T43,T77

 LINE       95
 EXPRESSION (attr_i.pull_en ? attr_i.pull_select : 1'bz)
             -------1------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T22,T23,T24

---

Branch Coverage for Instance : tb.dut.u_padring.gen_mio_pads[34].u_mio_pad.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
TERNARY	78	2	2	100.00
TERNARY	92	2	2	100.00
TERNARY	93	2	2	100.00
TERNARY	95	2	2	100.00

78             assign in_raw_o = ie ? inout_io : 1'bz;
                                    -1-  
                                    ==>  
                                    ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T22,T23,T24

92             assign (strong0, strong1) inout_io = (oe && attr_i.drive_strength[0]) ? out : 1'bz;
                                                                                     -1-  
                                                                                     ==>  
                                                                                     ==>  

Branches:

-1-	Status	Tests
1	Covered	T22,T23,T24
0	Covered	T1,T2,T3

93             assign (pull0, pull1)     inout_io = (oe && !attr_i.drive_strength[0]) ? out : 1'bz;
                                                                                      -1-  
                                                                                      ==>  
                                                                                      ==>  

Branches:

-1-	Status	Tests
1	Covered	T28,T43,T77
0	Covered	T1,T2,T3

95             assign (weak0, weak1)     inout_io = attr_i.pull_en ? attr_i.pull_select : 1'bz;
                                                                   -1-  
                                                                   ==>  
                                                                   ==>  

Branches:

-1-	Status	Tests
1	Covered	T22,T23,T24
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_padring.gen_mio_pads[34].u_mio_pad.gen_generic.u_impl_generic

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AnalogNoScan_A	1021	1021	0	0

AnalogNoScan_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1021	1021	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T38	1	1	0	0
T39	1	1	0	0
T106	1	1	0	0

Line Coverage for Instance : tb.dut.u_padring.gen_mio_pads[35].u_mio_pad.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		8	8	100.00
CONT_ASSIGN	39	0	0
CONT_ASSIGN	51	1	1	100.00
CONT_ASSIGN	78	1	1	100.00
CONT_ASSIGN	80	1	1	100.00
CONT_ASSIGN	84	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	93	1	1	100.00
CONT_ASSIGN	95	1	1	100.00

38                        logic unused_sigs;
39         unreachable    assign unused_sigs = ^{attr_i.slew_rate,
40                                               attr_i.drive_strength[3:1],
41                                               attr_i.od_en,
42                                               attr_i.schmitt_en,
43                                               attr_i.keep_en,
44                                               scanmode_i,
45                                               pok_i};
46                        //VCS coverage on
47                        // pragma coverage on
48                      
49                        // Input enable (active-high)
50                        logic ie;
51         1/1            assign ie = ie_i & ~attr_i.input_disable;
           Tests:       T22 T23 T24 
52                      
53                        if (PadType == InputStd) begin : gen_input_only
54                          //VCS coverage off
55                          // pragma coverage off
56                          logic unused_in_sigs;
57                          assign unused_in_sigs = ^{out_i,
58                                                    oe_i,
59                                                    attr_i.virt_od_en,
60                                                    attr_i.drive_strength};
61                          //VCS coverage on
62                          // pragma coverage on
63                      
64                          assign in_raw_o = ie ? inout_io : 1'bz;
65                          // input inversion
66                          assign in_o = attr_i.invert ^ in_raw_o;
67                      
68                        // pulls are not supported by verilator
69                        `ifndef VERILATOR
70                          // pullup / pulldown termination
71                          assign (weak0, weak1) inout_io = attr_i.pull_en ? attr_i.pull_select : 1'bz;
72                        `endif
73                        end else if (PadType == BidirTol ||
74                                     PadType == DualBidirTol ||
75                                     PadType == BidirOd ||
76                                     PadType == BidirStd) begin : gen_bidir
77                      
78         1/1              assign in_raw_o = ie ? inout_io : 1'bz;
           Tests:       T44 T28 T36 
79                          // input inversion
80         1/1              assign in_o = attr_i.invert ^ in_raw_o;
           Tests:       T44 T28 T36 
81                      
82                          // virtual open drain emulation
83                          logic oe, out;
84         1/1              assign out = out_i ^ attr_i.invert;
           Tests:       T28 T13 T50 
85         1/1              assign oe  = oe_i & ((attr_i.virt_od_en & ~out) | ~attr_i.virt_od_en);
           Tests:       T28 T13 T50 
86                      
87                        // drive strength attributes are not supported by verilator
88                        `ifdef VERILATOR
89                          assign inout_io = (oe)   ? out : 1'bz;
90                        `else
91                          // different driver types
92         1/1              assign (strong0, strong1) inout_io = (oe && attr_i.drive_strength[0]) ? out : 1'bz;
           Tests:       T28 T13 T50 
93         1/1              assign (pull0, pull1)     inout_io = (oe && !attr_i.drive_strength[0]) ? out : 1'bz;
           Tests:       T28 T13 T50 
94                          // pullup / pulldown termination
95         1/1              assign (weak0, weak1)     inout_io = attr_i.pull_en ? attr_i.pull_select : 1'bz;
           Tests:       T22 T23 T24 

---

Cond Coverage for Instance : tb.dut.u_padring.gen_mio_pads[35].u_mio_pad.gen_generic.u_impl_generic

	Total	Covered	Percent
Conditions	33	33	100.00
Logical	33	33	100.00
Non-Logical	0	0
Event	0	0

 LINE       51
 EXPRESSION (ie_i & ((~attr_i.input_disable)))
             --1-   ------------2------------

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Covered	T22,T23,T24
1	1	Covered	T1,T2,T3

 LINE       78
 EXPRESSION (ie ? inout_io : 1'bz)
             -1

-1-	Status	Tests
0	Covered	T22,T23,T24
1	Covered	T1,T2,T3

 LINE       80
 EXPRESSION (attr_i.invert ^ in_raw_o)
             ------1------   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T44,T28,T36
0	1	Covered	T44,T28,T36
1	0	Covered	T22,T23,T24
1	1	Covered	T23,T24,T216

 LINE       84
 EXPRESSION (out_i ^ attr_i.invert)
             --1--   ------2------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T22,T23,T24
1	0	Covered	T28,T13,T50
1	1	Covered	T22,T23,T24

 LINE       85
 EXPRESSION (oe_i & ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en))))
             --1-   ---------------------------------2---------------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T22,T23,T24
1	1	Covered	T28,T13,T50

 LINE       85
 SUB-EXPRESSION ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en)))
                 --------------------1-------------------   -----------2----------

-1-	-2-	Status	Tests
0	0	Covered	T22,T23,T24
0	1	Covered	T1,T2,T3
1	0	Covered	T22,T23,T24

 LINE       85
 SUB-EXPRESSION (attr_i.virt_od_en & ((~gen_bidir.out)))
                 --------1--------   ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T22,T23,T24
1	1	Covered	T22,T23,T24

 LINE       92
 EXPRESSION ((gen_bidir.oe && attr_i.drive_strength[0]) ? gen_bidir.out : 1'bz)
             ---------------------1--------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T22,T23,T24

 LINE       92
 SUB-EXPRESSION (gen_bidir.oe && attr_i.drive_strength[0])
                 ------1-----    ------------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T22,T23,T24
1	0	Covered	T28,T13,T50
1	1	Covered	T22,T23,T24

 LINE       93
 EXPRESSION ((gen_bidir.oe && ((!attr_i.drive_strength[0]))) ? gen_bidir.out : 1'bz)
             -----------------------1-----------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T28,T13,T50

 LINE       93
 SUB-EXPRESSION (gen_bidir.oe && ((!attr_i.drive_strength[0])))
                 ------1-----    --------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T22,T23,T24
1	1	Covered	T28,T13,T50

 LINE       95
 EXPRESSION (attr_i.pull_en ? attr_i.pull_select : 1'bz)
             -------1------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T22,T23,T24

---

Branch Coverage for Instance : tb.dut.u_padring.gen_mio_pads[35].u_mio_pad.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
TERNARY	78	2	2	100.00
TERNARY	92	2	2	100.00
TERNARY	93	2	2	100.00
TERNARY	95	2	2	100.00

78             assign in_raw_o = ie ? inout_io : 1'bz;
                                    -1-  
                                    ==>  
                                    ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T22,T23,T24

92             assign (strong0, strong1) inout_io = (oe && attr_i.drive_strength[0]) ? out : 1'bz;
                                                                                     -1-  
                                                                                     ==>  
                                                                                     ==>  

Branches:

-1-	Status	Tests
1	Covered	T22,T23,T24
0	Covered	T1,T2,T3

93             assign (pull0, pull1)     inout_io = (oe && !attr_i.drive_strength[0]) ? out : 1'bz;
                                                                                      -1-  
                                                                                      ==>  
                                                                                      ==>  

Branches:

-1-	Status	Tests
1	Covered	T28,T13,T50
0	Covered	T1,T2,T3

95             assign (weak0, weak1)     inout_io = attr_i.pull_en ? attr_i.pull_select : 1'bz;
                                                                   -1-  
                                                                   ==>  
                                                                   ==>  

Branches:

-1-	Status	Tests
1	Covered	T22,T23,T24
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_padring.gen_mio_pads[35].u_mio_pad.gen_generic.u_impl_generic

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AnalogNoScan_A	1021	1021	0	0

AnalogNoScan_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1021	1021	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T38	1	1	0	0
T39	1	1	0	0
T106	1	1	0	0

Line Coverage for Instance : tb.dut.u_padring.gen_mio_pads[36].u_mio_pad.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		8	8	100.00
CONT_ASSIGN	39	0	0
CONT_ASSIGN	51	1	1	100.00
CONT_ASSIGN	78	1	1	100.00
CONT_ASSIGN	80	1	1	100.00
CONT_ASSIGN	84	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	93	1	1	100.00
CONT_ASSIGN	95	1	1	100.00

38                        logic unused_sigs;
39         unreachable    assign unused_sigs = ^{attr_i.slew_rate,
40                                               attr_i.drive_strength[3:1],
41                                               attr_i.od_en,
42                                               attr_i.schmitt_en,
43                                               attr_i.keep_en,
44                                               scanmode_i,
45                                               pok_i};
46                        //VCS coverage on
47                        // pragma coverage on
48                      
49                        // Input enable (active-high)
50                        logic ie;
51         1/1            assign ie = ie_i & ~attr_i.input_disable;
           Tests:       T22 T23 T24 
52                      
53                        if (PadType == InputStd) begin : gen_input_only
54                          //VCS coverage off
55                          // pragma coverage off
56                          logic unused_in_sigs;
57                          assign unused_in_sigs = ^{out_i,
58                                                    oe_i,
59                                                    attr_i.virt_od_en,
60                                                    attr_i.drive_strength};
61                          //VCS coverage on
62                          // pragma coverage on
63                      
64                          assign in_raw_o = ie ? inout_io : 1'bz;
65                          // input inversion
66                          assign in_o = attr_i.invert ^ in_raw_o;
67                      
68                        // pulls are not supported by verilator
69                        `ifndef VERILATOR
70                          // pullup / pulldown termination
71                          assign (weak0, weak1) inout_io = attr_i.pull_en ? attr_i.pull_select : 1'bz;
72                        `endif
73                        end else if (PadType == BidirTol ||
74                                     PadType == DualBidirTol ||
75                                     PadType == BidirOd ||
76                                     PadType == BidirStd) begin : gen_bidir
77                      
78         1/1              assign in_raw_o = ie ? inout_io : 1'bz;
           Tests:       T44 T28 T36 
79                          // input inversion
80         1/1              assign in_o = attr_i.invert ^ in_raw_o;
           Tests:       T44 T28 T36 
81                      
82                          // virtual open drain emulation
83                          logic oe, out;
84         1/1              assign out = out_i ^ attr_i.invert;
           Tests:       T44 T28 T36 
85         1/1              assign oe  = oe_i & ((attr_i.virt_od_en & ~out) | ~attr_i.virt_od_en);
           Tests:       T44 T28 T36 
86                      
87                        // drive strength attributes are not supported by verilator
88                        `ifdef VERILATOR
89                          assign inout_io = (oe)   ? out : 1'bz;
90                        `else
91                          // different driver types
92         1/1              assign (strong0, strong1) inout_io = (oe && attr_i.drive_strength[0]) ? out : 1'bz;
           Tests:       T44 T28 T36 
93         1/1              assign (pull0, pull1)     inout_io = (oe && !attr_i.drive_strength[0]) ? out : 1'bz;
           Tests:       T44 T28 T36 
94                          // pullup / pulldown termination
95         1/1              assign (weak0, weak1)     inout_io = attr_i.pull_en ? attr_i.pull_select : 1'bz;
           Tests:       T22 T23 T24 

---

Cond Coverage for Instance : tb.dut.u_padring.gen_mio_pads[36].u_mio_pad.gen_generic.u_impl_generic

	Total	Covered	Percent
Conditions	33	33	100.00
Logical	33	33	100.00
Non-Logical	0	0
Event	0	0

 LINE       51
 EXPRESSION (ie_i & ((~attr_i.input_disable)))
             --1-   ------------2------------

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Covered	T22,T23,T24
1	1	Covered	T1,T2,T3

 LINE       78
 EXPRESSION (ie ? inout_io : 1'bz)
             -1

-1-	Status	Tests
0	Covered	T22,T23,T24
1	Covered	T1,T2,T3

 LINE       80
 EXPRESSION (attr_i.invert ^ in_raw_o)
             ------1------   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T44,T28,T36
0	1	Covered	T44,T28,T36
1	0	Covered	T22,T23,T216
1	1	Covered	T22,T23,T24

 LINE       84
 EXPRESSION (out_i ^ attr_i.invert)
             --1--   ------2------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T22,T23,T24
1	0	Covered	T44,T28,T36
1	1	Covered	T22,T23,T24

 LINE       85
 EXPRESSION (oe_i & ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en))))
             --1-   ---------------------------------2---------------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T22,T23,T24
1	1	Covered	T44,T28,T36

 LINE       85
 SUB-EXPRESSION ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en)))
                 --------------------1-------------------   -----------2----------

-1-	-2-	Status	Tests
0	0	Covered	T22,T23,T24
0	1	Covered	T1,T2,T3
1	0	Covered	T22,T23,T24

 LINE       85
 SUB-EXPRESSION (attr_i.virt_od_en & ((~gen_bidir.out)))
                 --------1--------   ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T22,T23,T24
1	1	Covered	T22,T23,T24

 LINE       92
 EXPRESSION ((gen_bidir.oe && attr_i.drive_strength[0]) ? gen_bidir.out : 1'bz)
             ---------------------1--------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T22,T23,T24

 LINE       92
 SUB-EXPRESSION (gen_bidir.oe && attr_i.drive_strength[0])
                 ------1-----    ------------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T22,T23,T24
1	0	Covered	T44,T28,T36
1	1	Covered	T22,T23,T24

 LINE       93
 EXPRESSION ((gen_bidir.oe && ((!attr_i.drive_strength[0]))) ? gen_bidir.out : 1'bz)
             -----------------------1-----------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T44,T28,T36

 LINE       93
 SUB-EXPRESSION (gen_bidir.oe && ((!attr_i.drive_strength[0])))
                 ------1-----    --------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T22,T23,T24
1	1	Covered	T44,T28,T36

 LINE       95
 EXPRESSION (attr_i.pull_en ? attr_i.pull_select : 1'bz)
             -------1------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T22,T23,T24

---

Branch Coverage for Instance : tb.dut.u_padring.gen_mio_pads[36].u_mio_pad.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
TERNARY	78	2	2	100.00
TERNARY	92	2	2	100.00
TERNARY	93	2	2	100.00
TERNARY	95	2	2	100.00

78             assign in_raw_o = ie ? inout_io : 1'bz;
                                    -1-  
                                    ==>  
                                    ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T22,T23,T24

92             assign (strong0, strong1) inout_io = (oe && attr_i.drive_strength[0]) ? out : 1'bz;
                                                                                     -1-  
                                                                                     ==>  
                                                                                     ==>  

Branches:

-1-	Status	Tests
1	Covered	T22,T23,T24
0	Covered	T1,T2,T3

93             assign (pull0, pull1)     inout_io = (oe && !attr_i.drive_strength[0]) ? out : 1'bz;
                                                                                      -1-  
                                                                                      ==>  
                                                                                      ==>  

Branches:

-1-	Status	Tests
1	Covered	T44,T28,T36
0	Covered	T1,T2,T3

95             assign (weak0, weak1)     inout_io = attr_i.pull_en ? attr_i.pull_select : 1'bz;
                                                                   -1-  
                                                                   ==>  
                                                                   ==>  

Branches:

-1-	Status	Tests
1	Covered	T22,T23,T24
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_padring.gen_mio_pads[36].u_mio_pad.gen_generic.u_impl_generic

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AnalogNoScan_A	1021	1021	0	0

AnalogNoScan_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1021	1021	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T38	1	1	0	0
T39	1	1	0	0
T106	1	1	0	0

Line Coverage for Instance : tb.dut.u_padring.gen_mio_pads[37].u_mio_pad.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		8	8	100.00
CONT_ASSIGN	39	0	0
CONT_ASSIGN	51	1	1	100.00
CONT_ASSIGN	78	1	1	100.00
CONT_ASSIGN	80	1	1	100.00
CONT_ASSIGN	84	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	93	1	1	100.00
CONT_ASSIGN	95	1	1	100.00

38                        logic unused_sigs;
39         unreachable    assign unused_sigs = ^{attr_i.slew_rate,
40                                               attr_i.drive_strength[3:1],
41                                               attr_i.od_en,
42                                               attr_i.schmitt_en,
43                                               attr_i.keep_en,
44                                               scanmode_i,
45                                               pok_i};
46                        //VCS coverage on
47                        // pragma coverage on
48                      
49                        // Input enable (active-high)
50                        logic ie;
51         1/1            assign ie = ie_i & ~attr_i.input_disable;
           Tests:       T22 T23 T24 
52                      
53                        if (PadType == InputStd) begin : gen_input_only
54                          //VCS coverage off
55                          // pragma coverage off
56                          logic unused_in_sigs;
57                          assign unused_in_sigs = ^{out_i,
58                                                    oe_i,
59                                                    attr_i.virt_od_en,
60                                                    attr_i.drive_strength};
61                          //VCS coverage on
62                          // pragma coverage on
63                      
64                          assign in_raw_o = ie ? inout_io : 1'bz;
65                          // input inversion
66                          assign in_o = attr_i.invert ^ in_raw_o;
67                      
68                        // pulls are not supported by verilator
69                        `ifndef VERILATOR
70                          // pullup / pulldown termination
71                          assign (weak0, weak1) inout_io = attr_i.pull_en ? attr_i.pull_select : 1'bz;
72                        `endif
73                        end else if (PadType == BidirTol ||
74                                     PadType == DualBidirTol ||
75                                     PadType == BidirOd ||
76                                     PadType == BidirStd) begin : gen_bidir
77                      
78         1/1              assign in_raw_o = ie ? inout_io : 1'bz;
           Tests:       T44 T28 T36 
79                          // input inversion
80         1/1              assign in_o = attr_i.invert ^ in_raw_o;
           Tests:       T44 T28 T36 
81                      
82                          // virtual open drain emulation
83                          logic oe, out;
84         1/1              assign out = out_i ^ attr_i.invert;
           Tests:       T28 T13 T50 
85         1/1              assign oe  = oe_i & ((attr_i.virt_od_en & ~out) | ~attr_i.virt_od_en);
           Tests:       T28 T13 T50 
86                      
87                        // drive strength attributes are not supported by verilator
88                        `ifdef VERILATOR
89                          assign inout_io = (oe)   ? out : 1'bz;
90                        `else
91                          // different driver types
92         1/1              assign (strong0, strong1) inout_io = (oe && attr_i.drive_strength[0]) ? out : 1'bz;
           Tests:       T28 T13 T50 
93         1/1              assign (pull0, pull1)     inout_io = (oe && !attr_i.drive_strength[0]) ? out : 1'bz;
           Tests:       T28 T13 T50 
94                          // pullup / pulldown termination
95         1/1              assign (weak0, weak1)     inout_io = attr_i.pull_en ? attr_i.pull_select : 1'bz;
           Tests:       T22 T23 T24 

---

Cond Coverage for Instance : tb.dut.u_padring.gen_mio_pads[37].u_mio_pad.gen_generic.u_impl_generic

	Total	Covered	Percent
Conditions	33	33	100.00
Logical	33	33	100.00
Non-Logical	0	0
Event	0	0

 LINE       51
 EXPRESSION (ie_i & ((~attr_i.input_disable)))
             --1-   ------------2------------

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Covered	T22,T23,T24
1	1	Covered	T1,T2,T3

 LINE       78
 EXPRESSION (ie ? inout_io : 1'bz)
             -1

-1-	Status	Tests
0	Covered	T22,T23,T24
1	Covered	T1,T2,T3

 LINE       80
 EXPRESSION (attr_i.invert ^ in_raw_o)
             ------1------   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T44,T28,T36
0	1	Covered	T44,T28,T36
1	0	Covered	T23,T24,T216
1	1	Covered	T23,T24,T216

 LINE       84
 EXPRESSION (out_i ^ attr_i.invert)
             --1--   ------2------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T22,T23,T24
1	0	Covered	T28,T13,T50
1	1	Covered	T22,T23,T24

 LINE       85
 EXPRESSION (oe_i & ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en))))
             --1-   ---------------------------------2---------------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T22,T23,T24
1	1	Covered	T28,T13,T50

 LINE       85
 SUB-EXPRESSION ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en)))
                 --------------------1-------------------   -----------2----------

-1-	-2-	Status	Tests
0	0	Covered	T22,T23,T24
0	1	Covered	T1,T2,T3
1	0	Covered	T22,T23,T24

 LINE       85
 SUB-EXPRESSION (attr_i.virt_od_en & ((~gen_bidir.out)))
                 --------1--------   ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T22,T23,T24
1	1	Covered	T22,T23,T24

 LINE       92
 EXPRESSION ((gen_bidir.oe && attr_i.drive_strength[0]) ? gen_bidir.out : 1'bz)
             ---------------------1--------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T22,T23,T24

 LINE       92
 SUB-EXPRESSION (gen_bidir.oe && attr_i.drive_strength[0])
                 ------1-----    ------------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T22,T23,T24
1	0	Covered	T28,T13,T50
1	1	Covered	T22,T23,T24

 LINE       93
 EXPRESSION ((gen_bidir.oe && ((!attr_i.drive_strength[0]))) ? gen_bidir.out : 1'bz)
             -----------------------1-----------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T28,T13,T50

 LINE       93
 SUB-EXPRESSION (gen_bidir.oe && ((!attr_i.drive_strength[0])))
                 ------1-----    --------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T22,T23,T24
1	1	Covered	T28,T13,T50

 LINE       95
 EXPRESSION (attr_i.pull_en ? attr_i.pull_select : 1'bz)
             -------1------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T22,T23,T24

---

Branch Coverage for Instance : tb.dut.u_padring.gen_mio_pads[37].u_mio_pad.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
TERNARY	78	2	2	100.00
TERNARY	92	2	2	100.00
TERNARY	93	2	2	100.00
TERNARY	95	2	2	100.00

78             assign in_raw_o = ie ? inout_io : 1'bz;
                                    -1-  
                                    ==>  
                                    ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T22,T23,T24

92             assign (strong0, strong1) inout_io = (oe && attr_i.drive_strength[0]) ? out : 1'bz;
                                                                                     -1-  
                                                                                     ==>  
                                                                                     ==>  

Branches:

-1-	Status	Tests
1	Covered	T22,T23,T24
0	Covered	T1,T2,T3

93             assign (pull0, pull1)     inout_io = (oe && !attr_i.drive_strength[0]) ? out : 1'bz;
                                                                                      -1-  
                                                                                      ==>  
                                                                                      ==>  

Branches:

-1-	Status	Tests
1	Covered	T28,T13,T50
0	Covered	T1,T2,T3

95             assign (weak0, weak1)     inout_io = attr_i.pull_en ? attr_i.pull_select : 1'bz;
                                                                   -1-  
                                                                   ==>  
                                                                   ==>  

Branches:

-1-	Status	Tests
1	Covered	T22,T23,T24
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_padring.gen_mio_pads[37].u_mio_pad.gen_generic.u_impl_generic

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AnalogNoScan_A	1021	1021	0	0

AnalogNoScan_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1021	1021	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T38	1	1	0	0
T39	1	1	0	0
T106	1	1	0	0

Line Coverage for Instance : tb.dut.u_padring.gen_mio_pads[38].u_mio_pad.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		8	8	100.00
CONT_ASSIGN	39	0	0
CONT_ASSIGN	51	1	1	100.00
CONT_ASSIGN	78	1	1	100.00
CONT_ASSIGN	80	1	1	100.00
CONT_ASSIGN	84	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	93	1	1	100.00
CONT_ASSIGN	95	1	1	100.00

38                        logic unused_sigs;
39         unreachable    assign unused_sigs = ^{attr_i.slew_rate,
40                                               attr_i.drive_strength[3:1],
41                                               attr_i.od_en,
42                                               attr_i.schmitt_en,
43                                               attr_i.keep_en,
44                                               scanmode_i,
45                                               pok_i};
46                        //VCS coverage on
47                        // pragma coverage on
48                      
49                        // Input enable (active-high)
50                        logic ie;
51         1/1            assign ie = ie_i & ~attr_i.input_disable;
           Tests:       T22 T23 T24 
52                      
53                        if (PadType == InputStd) begin : gen_input_only
54                          //VCS coverage off
55                          // pragma coverage off
56                          logic unused_in_sigs;
57                          assign unused_in_sigs = ^{out_i,
58                                                    oe_i,
59                                                    attr_i.virt_od_en,
60                                                    attr_i.drive_strength};
61                          //VCS coverage on
62                          // pragma coverage on
63                      
64                          assign in_raw_o = ie ? inout_io : 1'bz;
65                          // input inversion
66                          assign in_o = attr_i.invert ^ in_raw_o;
67                      
68                        // pulls are not supported by verilator
69                        `ifndef VERILATOR
70                          // pullup / pulldown termination
71                          assign (weak0, weak1) inout_io = attr_i.pull_en ? attr_i.pull_select : 1'bz;
72                        `endif
73                        end else if (PadType == BidirTol ||
74                                     PadType == DualBidirTol ||
75                                     PadType == BidirOd ||
76                                     PadType == BidirStd) begin : gen_bidir
77                      
78         1/1              assign in_raw_o = ie ? inout_io : 1'bz;
           Tests:       T44 T28 T36 
79                          // input inversion
80         1/1              assign in_o = attr_i.invert ^ in_raw_o;
           Tests:       T44 T28 T36 
81                      
82                          // virtual open drain emulation
83                          logic oe, out;
84         1/1              assign out = out_i ^ attr_i.invert;
           Tests:       T28 T13 T50 
85         1/1              assign oe  = oe_i & ((attr_i.virt_od_en & ~out) | ~attr_i.virt_od_en);
           Tests:       T28 T13 T50 
86                      
87                        // drive strength attributes are not supported by verilator
88                        `ifdef VERILATOR
89                          assign inout_io = (oe)   ? out : 1'bz;
90                        `else
91                          // different driver types
92         1/1              assign (strong0, strong1) inout_io = (oe && attr_i.drive_strength[0]) ? out : 1'bz;
           Tests:       T28 T13 T50 
93         1/1              assign (pull0, pull1)     inout_io = (oe && !attr_i.drive_strength[0]) ? out : 1'bz;
           Tests:       T28 T13 T50 
94                          // pullup / pulldown termination
95         1/1              assign (weak0, weak1)     inout_io = attr_i.pull_en ? attr_i.pull_select : 1'bz;
           Tests:       T22 T23 T24 

---

Cond Coverage for Instance : tb.dut.u_padring.gen_mio_pads[38].u_mio_pad.gen_generic.u_impl_generic

	Total	Covered	Percent
Conditions	33	33	100.00
Logical	33	33	100.00
Non-Logical	0	0
Event	0	0

 LINE       51
 EXPRESSION (ie_i & ((~attr_i.input_disable)))
             --1-   ------------2------------

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Covered	T22,T23,T24
1	1	Covered	T1,T2,T3

 LINE       78
 EXPRESSION (ie ? inout_io : 1'bz)
             -1

-1-	Status	Tests
0	Covered	T22,T23,T24
1	Covered	T1,T2,T3

 LINE       80
 EXPRESSION (attr_i.invert ^ in_raw_o)
             ------1------   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T44,T28,T36
0	1	Covered	T44,T28,T36
1	0	Covered	T22,T23,T24
1	1	Covered	T22,T23,T24

 LINE       84
 EXPRESSION (out_i ^ attr_i.invert)
             --1--   ------2------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T22,T23,T24
1	0	Covered	T28,T13,T50
1	1	Covered	T22,T23,T24

 LINE       85
 EXPRESSION (oe_i & ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en))))
             --1-   ---------------------------------2---------------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T22,T23,T24
1	1	Covered	T28,T13,T50

 LINE       85
 SUB-EXPRESSION ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en)))
                 --------------------1-------------------   -----------2----------

-1-	-2-	Status	Tests
0	0	Covered	T22,T23,T24
0	1	Covered	T1,T2,T3
1	0	Covered	T22,T23,T24

 LINE       85
 SUB-EXPRESSION (attr_i.virt_od_en & ((~gen_bidir.out)))
                 --------1--------   ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T22,T23,T24
1	1	Covered	T22,T23,T24

 LINE       92
 EXPRESSION ((gen_bidir.oe && attr_i.drive_strength[0]) ? gen_bidir.out : 1'bz)
             ---------------------1--------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T22,T23,T24

 LINE       92
 SUB-EXPRESSION (gen_bidir.oe && attr_i.drive_strength[0])
                 ------1-----    ------------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T22,T23,T24
1	0	Covered	T28,T13,T50
1	1	Covered	T22,T23,T24

 LINE       93
 EXPRESSION ((gen_bidir.oe && ((!attr_i.drive_strength[0]))) ? gen_bidir.out : 1'bz)
             -----------------------1-----------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T28,T13,T50

 LINE       93
 SUB-EXPRESSION (gen_bidir.oe && ((!attr_i.drive_strength[0])))
                 ------1-----    --------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T22,T23,T24
1	1	Covered	T28,T13,T50

 LINE       95
 EXPRESSION (attr_i.pull_en ? attr_i.pull_select : 1'bz)
             -------1------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T22,T23,T24

---

Branch Coverage for Instance : tb.dut.u_padring.gen_mio_pads[38].u_mio_pad.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
TERNARY	78	2	2	100.00
TERNARY	92	2	2	100.00
TERNARY	93	2	2	100.00
TERNARY	95	2	2	100.00

78             assign in_raw_o = ie ? inout_io : 1'bz;
                                    -1-  
                                    ==>  
                                    ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T22,T23,T24

92             assign (strong0, strong1) inout_io = (oe && attr_i.drive_strength[0]) ? out : 1'bz;
                                                                                     -1-  
                                                                                     ==>  
                                                                                     ==>  

Branches:

-1-	Status	Tests
1	Covered	T22,T23,T24
0	Covered	T1,T2,T3

93             assign (pull0, pull1)     inout_io = (oe && !attr_i.drive_strength[0]) ? out : 1'bz;
                                                                                      -1-  
                                                                                      ==>  
                                                                                      ==>  

Branches:

-1-	Status	Tests
1	Covered	T28,T13,T50
0	Covered	T1,T2,T3

95             assign (weak0, weak1)     inout_io = attr_i.pull_en ? attr_i.pull_select : 1'bz;
                                                                   -1-  
                                                                   ==>  
                                                                   ==>  

Branches:

-1-	Status	Tests
1	Covered	T22,T23,T24
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_padring.gen_mio_pads[38].u_mio_pad.gen_generic.u_impl_generic

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AnalogNoScan_A	1021	1021	0	0

AnalogNoScan_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1021	1021	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T38	1	1	0	0
T39	1	1	0	0
T106	1	1	0	0

Line Coverage for Instance : tb.dut.u_padring.gen_mio_pads[39].u_mio_pad.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		8	8	100.00
CONT_ASSIGN	39	0	0
CONT_ASSIGN	51	1	1	100.00
CONT_ASSIGN	78	1	1	100.00
CONT_ASSIGN	80	1	1	100.00
CONT_ASSIGN	84	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	93	1	1	100.00
CONT_ASSIGN	95	1	1	100.00

38                        logic unused_sigs;
39         unreachable    assign unused_sigs = ^{attr_i.slew_rate,
40                                               attr_i.drive_strength[3:1],
41                                               attr_i.od_en,
42                                               attr_i.schmitt_en,
43                                               attr_i.keep_en,
44                                               scanmode_i,
45                                               pok_i};
46                        //VCS coverage on
47                        // pragma coverage on
48                      
49                        // Input enable (active-high)
50                        logic ie;
51         1/1            assign ie = ie_i & ~attr_i.input_disable;
           Tests:       T22 T23 T24 
52                      
53                        if (PadType == InputStd) begin : gen_input_only
54                          //VCS coverage off
55                          // pragma coverage off
56                          logic unused_in_sigs;
57                          assign unused_in_sigs = ^{out_i,
58                                                    oe_i,
59                                                    attr_i.virt_od_en,
60                                                    attr_i.drive_strength};
61                          //VCS coverage on
62                          // pragma coverage on
63                      
64                          assign in_raw_o = ie ? inout_io : 1'bz;
65                          // input inversion
66                          assign in_o = attr_i.invert ^ in_raw_o;
67                      
68                        // pulls are not supported by verilator
69                        `ifndef VERILATOR
70                          // pullup / pulldown termination
71                          assign (weak0, weak1) inout_io = attr_i.pull_en ? attr_i.pull_select : 1'bz;
72                        `endif
73                        end else if (PadType == BidirTol ||
74                                     PadType == DualBidirTol ||
75                                     PadType == BidirOd ||
76                                     PadType == BidirStd) begin : gen_bidir
77                      
78         1/1              assign in_raw_o = ie ? inout_io : 1'bz;
           Tests:       T44 T28 T36 
79                          // input inversion
80         1/1              assign in_o = attr_i.invert ^ in_raw_o;
           Tests:       T44 T28 T36 
81                      
82                          // virtual open drain emulation
83                          logic oe, out;
84         1/1              assign out = out_i ^ attr_i.invert;
           Tests:       T28 T50 T51 
85         1/1              assign oe  = oe_i & ((attr_i.virt_od_en & ~out) | ~attr_i.virt_od_en);
           Tests:       T28 T50 T51 
86                      
87                        // drive strength attributes are not supported by verilator
88                        `ifdef VERILATOR
89                          assign inout_io = (oe)   ? out : 1'bz;
90                        `else
91                          // different driver types
92         1/1              assign (strong0, strong1) inout_io = (oe && attr_i.drive_strength[0]) ? out : 1'bz;
           Tests:       T28 T50 T51 
93         1/1              assign (pull0, pull1)     inout_io = (oe && !attr_i.drive_strength[0]) ? out : 1'bz;
           Tests:       T28 T50 T51 
94                          // pullup / pulldown termination
95         1/1              assign (weak0, weak1)     inout_io = attr_i.pull_en ? attr_i.pull_select : 1'bz;
           Tests:       T22 T23 T24 

---

Cond Coverage for Instance : tb.dut.u_padring.gen_mio_pads[39].u_mio_pad.gen_generic.u_impl_generic

	Total	Covered	Percent
Conditions	33	33	100.00
Logical	33	33	100.00
Non-Logical	0	0
Event	0	0

 LINE       51
 EXPRESSION (ie_i & ((~attr_i.input_disable)))
             --1-   ------------2------------

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Covered	T22,T23,T24
1	1	Covered	T1,T2,T3

 LINE       78
 EXPRESSION (ie ? inout_io : 1'bz)
             -1

-1-	Status	Tests
0	Covered	T22,T23,T24
1	Covered	T1,T2,T3

 LINE       80
 EXPRESSION (attr_i.invert ^ in_raw_o)
             ------1------   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T44,T28,T36
0	1	Covered	T44,T28,T36
1	0	Covered	T22,T23,T24
1	1	Covered	T22,T23,T24

 LINE       84
 EXPRESSION (out_i ^ attr_i.invert)
             --1--   ------2------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T22,T23,T24
1	0	Covered	T28,T50,T51
1	1	Covered	T22,T23,T24

 LINE       85
 EXPRESSION (oe_i & ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en))))
             --1-   ---------------------------------2---------------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T22,T23,T24
1	1	Covered	T28,T50,T51

 LINE       85
 SUB-EXPRESSION ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en)))
                 --------------------1-------------------   -----------2----------

-1-	-2-	Status	Tests
0	0	Covered	T22,T23,T24
0	1	Covered	T1,T2,T3
1	0	Covered	T22,T23,T24

 LINE       85
 SUB-EXPRESSION (attr_i.virt_od_en & ((~gen_bidir.out)))
                 --------1--------   ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T22,T23,T24
1	1	Covered	T22,T23,T24

 LINE       92
 EXPRESSION ((gen_bidir.oe && attr_i.drive_strength[0]) ? gen_bidir.out : 1'bz)
             ---------------------1--------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T22,T23,T24

 LINE       92
 SUB-EXPRESSION (gen_bidir.oe && attr_i.drive_strength[0])
                 ------1-----    ------------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T22,T23,T24
1	0	Covered	T28,T50,T51
1	1	Covered	T22,T23,T24

 LINE       93
 EXPRESSION ((gen_bidir.oe && ((!attr_i.drive_strength[0]))) ? gen_bidir.out : 1'bz)
             -----------------------1-----------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T28,T50,T51

 LINE       93
 SUB-EXPRESSION (gen_bidir.oe && ((!attr_i.drive_strength[0])))
                 ------1-----    --------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T22,T23,T24
1	1	Covered	T28,T50,T51

 LINE       95
 EXPRESSION (attr_i.pull_en ? attr_i.pull_select : 1'bz)
             -------1------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T22,T23,T24

---

Branch Coverage for Instance : tb.dut.u_padring.gen_mio_pads[39].u_mio_pad.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
TERNARY	78	2	2	100.00
TERNARY	92	2	2	100.00
TERNARY	93	2	2	100.00
TERNARY	95	2	2	100.00

78             assign in_raw_o = ie ? inout_io : 1'bz;
                                    -1-  
                                    ==>  
                                    ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T22,T23,T24

92             assign (strong0, strong1) inout_io = (oe && attr_i.drive_strength[0]) ? out : 1'bz;
                                                                                     -1-  
                                                                                     ==>  
                                                                                     ==>  

Branches:

-1-	Status	Tests
1	Covered	T22,T23,T24
0	Covered	T1,T2,T3

93             assign (pull0, pull1)     inout_io = (oe && !attr_i.drive_strength[0]) ? out : 1'bz;
                                                                                      -1-  
                                                                                      ==>  
                                                                                      ==>  

Branches:

-1-	Status	Tests
1	Covered	T28,T50,T51
0	Covered	T1,T2,T3

95             assign (weak0, weak1)     inout_io = attr_i.pull_en ? attr_i.pull_select : 1'bz;
                                                                   -1-  
                                                                   ==>  
                                                                   ==>  

Branches:

-1-	Status	Tests
1	Covered	T22,T23,T24
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_padring.gen_mio_pads[39].u_mio_pad.gen_generic.u_impl_generic

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AnalogNoScan_A	1021	1021	0	0

AnalogNoScan_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1021	1021	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T38	1	1	0	0
T39	1	1	0	0
T106	1	1	0	0

Line Coverage for Instance : tb.dut.u_padring.gen_mio_pads[40].u_mio_pad.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		8	8	100.00
CONT_ASSIGN	39	0	0
CONT_ASSIGN	51	1	1	100.00
CONT_ASSIGN	78	1	1	100.00
CONT_ASSIGN	80	1	1	100.00
CONT_ASSIGN	84	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	93	1	1	100.00
CONT_ASSIGN	95	1	1	100.00

38                        logic unused_sigs;
39         unreachable    assign unused_sigs = ^{attr_i.slew_rate,
40                                               attr_i.drive_strength[3:1],
41                                               attr_i.od_en,
42                                               attr_i.schmitt_en,
43                                               attr_i.keep_en,
44                                               scanmode_i,
45                                               pok_i};
46                        //VCS coverage on
47                        // pragma coverage on
48                      
49                        // Input enable (active-high)
50                        logic ie;
51         1/1            assign ie = ie_i & ~attr_i.input_disable;
           Tests:       T22 T23 T24 
52                      
53                        if (PadType == InputStd) begin : gen_input_only
54                          //VCS coverage off
55                          // pragma coverage off
56                          logic unused_in_sigs;
57                          assign unused_in_sigs = ^{out_i,
58                                                    oe_i,
59                                                    attr_i.virt_od_en,
60                                                    attr_i.drive_strength};
61                          //VCS coverage on
62                          // pragma coverage on
63                      
64                          assign in_raw_o = ie ? inout_io : 1'bz;
65                          // input inversion
66                          assign in_o = attr_i.invert ^ in_raw_o;
67                      
68                        // pulls are not supported by verilator
69                        `ifndef VERILATOR
70                          // pullup / pulldown termination
71                          assign (weak0, weak1) inout_io = attr_i.pull_en ? attr_i.pull_select : 1'bz;
72                        `endif
73                        end else if (PadType == BidirTol ||
74                                     PadType == DualBidirTol ||
75                                     PadType == BidirOd ||
76                                     PadType == BidirStd) begin : gen_bidir
77                      
78         1/1              assign in_raw_o = ie ? inout_io : 1'bz;
           Tests:       T1 T2 T3 
79                          // input inversion
80         1/1              assign in_o = attr_i.invert ^ in_raw_o;
           Tests:       T1 T2 T3 
81                      
82                          // virtual open drain emulation
83                          logic oe, out;
84         1/1              assign out = out_i ^ attr_i.invert;
           Tests:       T28 T15 T13 
85         1/1              assign oe  = oe_i & ((attr_i.virt_od_en & ~out) | ~attr_i.virt_od_en);
           Tests:       T28 T15 T13 
86                      
87                        // drive strength attributes are not supported by verilator
88                        `ifdef VERILATOR
89                          assign inout_io = (oe)   ? out : 1'bz;
90                        `else
91                          // different driver types
92         1/1              assign (strong0, strong1) inout_io = (oe && attr_i.drive_strength[0]) ? out : 1'bz;
           Tests:       T28 T15 T13 
93         1/1              assign (pull0, pull1)     inout_io = (oe && !attr_i.drive_strength[0]) ? out : 1'bz;
           Tests:       T28 T15 T13 
94                          // pullup / pulldown termination
95         1/1              assign (weak0, weak1)     inout_io = attr_i.pull_en ? attr_i.pull_select : 1'bz;
           Tests:       T22 T23 T24 

---

Cond Coverage for Instance : tb.dut.u_padring.gen_mio_pads[40].u_mio_pad.gen_generic.u_impl_generic

	Total	Covered	Percent
Conditions	33	33	100.00
Logical	33	33	100.00
Non-Logical	0	0
Event	0	0

 LINE       51
 EXPRESSION (ie_i & ((~attr_i.input_disable)))
             --1-   ------------2------------

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Covered	T22,T23,T24
1	1	Covered	T1,T2,T3

 LINE       78
 EXPRESSION (ie ? inout_io : 1'bz)
             -1

-1-	Status	Tests
0	Covered	T22,T23,T24
1	Covered	T1,T2,T3

 LINE       80
 EXPRESSION (attr_i.invert ^ in_raw_o)
             ------1------   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T28,T15,T40
1	0	Covered	T22,T23,T24
1	1	Covered	T22,T23,T24

 LINE       84
 EXPRESSION (out_i ^ attr_i.invert)
             --1--   ------2------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T22,T23,T24
1	0	Covered	T28,T15,T13
1	1	Covered	T22,T23,T24

 LINE       85
 EXPRESSION (oe_i & ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en))))
             --1-   ---------------------------------2---------------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T22,T23,T24
1	1	Covered	T28,T15,T13

 LINE       85
 SUB-EXPRESSION ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en)))
                 --------------------1-------------------   -----------2----------

-1-	-2-	Status	Tests
0	0	Covered	T22,T23,T24
0	1	Covered	T1,T2,T3
1	0	Covered	T22,T23,T24

 LINE       85
 SUB-EXPRESSION (attr_i.virt_od_en & ((~gen_bidir.out)))
                 --------1--------   ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T22,T23,T24
1	1	Covered	T22,T23,T24

 LINE       92
 EXPRESSION ((gen_bidir.oe && attr_i.drive_strength[0]) ? gen_bidir.out : 1'bz)
             ---------------------1--------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T22,T23,T24

 LINE       92
 SUB-EXPRESSION (gen_bidir.oe && attr_i.drive_strength[0])
                 ------1-----    ------------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T22,T23,T24
1	0	Covered	T28,T15,T13
1	1	Covered	T22,T23,T24

 LINE       93
 EXPRESSION ((gen_bidir.oe && ((!attr_i.drive_strength[0]))) ? gen_bidir.out : 1'bz)
             -----------------------1-----------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T28,T15,T13

 LINE       93
 SUB-EXPRESSION (gen_bidir.oe && ((!attr_i.drive_strength[0])))
                 ------1-----    --------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T22,T23,T24
1	1	Covered	T28,T15,T13

 LINE       95
 EXPRESSION (attr_i.pull_en ? attr_i.pull_select : 1'bz)
             -------1------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T22,T23,T24

---

Branch Coverage for Instance : tb.dut.u_padring.gen_mio_pads[40].u_mio_pad.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
TERNARY	78	2	2	100.00
TERNARY	92	2	2	100.00
TERNARY	93	2	2	100.00
TERNARY	95	2	2	100.00

78             assign in_raw_o = ie ? inout_io : 1'bz;
                                    -1-  
                                    ==>  
                                    ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T22,T23,T24

92             assign (strong0, strong1) inout_io = (oe && attr_i.drive_strength[0]) ? out : 1'bz;
                                                                                     -1-  
                                                                                     ==>  
                                                                                     ==>  

Branches:

-1-	Status	Tests
1	Covered	T22,T23,T24
0	Covered	T1,T2,T3

93             assign (pull0, pull1)     inout_io = (oe && !attr_i.drive_strength[0]) ? out : 1'bz;
                                                                                      -1-  
                                                                                      ==>  
                                                                                      ==>  

Branches:

-1-	Status	Tests
1	Covered	T28,T15,T13
0	Covered	T1,T2,T3

95             assign (weak0, weak1)     inout_io = attr_i.pull_en ? attr_i.pull_select : 1'bz;
                                                                   -1-  
                                                                   ==>  
                                                                   ==>  

Branches:

-1-	Status	Tests
1	Covered	T22,T23,T24
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_padring.gen_mio_pads[40].u_mio_pad.gen_generic.u_impl_generic

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AnalogNoScan_A	1021	1021	0	0

AnalogNoScan_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1021	1021	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T38	1	1	0	0
T39	1	1	0	0
T106	1	1	0	0

Line Coverage for Instance : tb.dut.u_padring.gen_mio_pads[41].u_mio_pad.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		8	8	100.00
CONT_ASSIGN	39	0	0
CONT_ASSIGN	51	1	1	100.00
CONT_ASSIGN	78	1	1	100.00
CONT_ASSIGN	80	1	1	100.00
CONT_ASSIGN	84	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	93	1	1	100.00
CONT_ASSIGN	95	1	1	100.00

38                        logic unused_sigs;
39         unreachable    assign unused_sigs = ^{attr_i.slew_rate,
40                                               attr_i.drive_strength[3:1],
41                                               attr_i.od_en,
42                                               attr_i.schmitt_en,
43                                               attr_i.keep_en,
44                                               scanmode_i,
45                                               pok_i};
46                        //VCS coverage on
47                        // pragma coverage on
48                      
49                        // Input enable (active-high)
50                        logic ie;
51         1/1            assign ie = ie_i & ~attr_i.input_disable;
           Tests:       T22 T23 T24 
52                      
53                        if (PadType == InputStd) begin : gen_input_only
54                          //VCS coverage off
55                          // pragma coverage off
56                          logic unused_in_sigs;
57                          assign unused_in_sigs = ^{out_i,
58                                                    oe_i,
59                                                    attr_i.virt_od_en,
60                                                    attr_i.drive_strength};
61                          //VCS coverage on
62                          // pragma coverage on
63                      
64                          assign in_raw_o = ie ? inout_io : 1'bz;
65                          // input inversion
66                          assign in_o = attr_i.invert ^ in_raw_o;
67                      
68                        // pulls are not supported by verilator
69                        `ifndef VERILATOR
70                          // pullup / pulldown termination
71                          assign (weak0, weak1) inout_io = attr_i.pull_en ? attr_i.pull_select : 1'bz;
72                        `endif
73                        end else if (PadType == BidirTol ||
74                                     PadType == DualBidirTol ||
75                                     PadType == BidirOd ||
76                                     PadType == BidirStd) begin : gen_bidir
77                      
78         1/1              assign in_raw_o = ie ? inout_io : 1'bz;
           Tests:       T28 T15 T30 
79                          // input inversion
80         1/1              assign in_o = attr_i.invert ^ in_raw_o;
           Tests:       T28 T15 T30 
81                      
82                          // virtual open drain emulation
83                          logic oe, out;
84         1/1              assign out = out_i ^ attr_i.invert;
           Tests:       T28 T15 T13 
85         1/1              assign oe  = oe_i & ((attr_i.virt_od_en & ~out) | ~attr_i.virt_od_en);
           Tests:       T28 T15 T13 
86                      
87                        // drive strength attributes are not supported by verilator
88                        `ifdef VERILATOR
89                          assign inout_io = (oe)   ? out : 1'bz;
90                        `else
91                          // different driver types
92         1/1              assign (strong0, strong1) inout_io = (oe && attr_i.drive_strength[0]) ? out : 1'bz;
           Tests:       T28 T15 T13 
93         1/1              assign (pull0, pull1)     inout_io = (oe && !attr_i.drive_strength[0]) ? out : 1'bz;
           Tests:       T28 T15 T13 
94                          // pullup / pulldown termination
95         1/1              assign (weak0, weak1)     inout_io = attr_i.pull_en ? attr_i.pull_select : 1'bz;
           Tests:       T22 T23 T24 

---

Cond Coverage for Instance : tb.dut.u_padring.gen_mio_pads[41].u_mio_pad.gen_generic.u_impl_generic

	Total	Covered	Percent
Conditions	33	33	100.00
Logical	33	33	100.00
Non-Logical	0	0
Event	0	0

 LINE       51
 EXPRESSION (ie_i & ((~attr_i.input_disable)))
             --1-   ------------2------------

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Covered	T22,T23,T24
1	1	Covered	T1,T2,T3

 LINE       78
 EXPRESSION (ie ? inout_io : 1'bz)
             -1

-1-	Status	Tests
0	Covered	T22,T23,T24
1	Covered	T1,T2,T3

 LINE       80
 EXPRESSION (attr_i.invert ^ in_raw_o)
             ------1------   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T28,T15,T30
0	1	Covered	T28,T15,T13
1	0	Covered	T22,T23,T24
1	1	Covered	T22,T23,T24

 LINE       84
 EXPRESSION (out_i ^ attr_i.invert)
             --1--   ------2------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T22,T23,T24
1	0	Covered	T28,T15,T13
1	1	Covered	T22,T23,T24

 LINE       85
 EXPRESSION (oe_i & ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en))))
             --1-   ---------------------------------2---------------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T22,T23,T24
1	1	Covered	T28,T15,T13

 LINE       85
 SUB-EXPRESSION ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en)))
                 --------------------1-------------------   -----------2----------

-1-	-2-	Status	Tests
0	0	Covered	T22,T23,T24
0	1	Covered	T1,T2,T3
1	0	Covered	T22,T23,T24

 LINE       85
 SUB-EXPRESSION (attr_i.virt_od_en & ((~gen_bidir.out)))
                 --------1--------   ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T22,T23,T24
1	1	Covered	T22,T23,T24

 LINE       92
 EXPRESSION ((gen_bidir.oe && attr_i.drive_strength[0]) ? gen_bidir.out : 1'bz)
             ---------------------1--------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T22,T23,T24

 LINE       92
 SUB-EXPRESSION (gen_bidir.oe && attr_i.drive_strength[0])
                 ------1-----    ------------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T22,T23,T24
1	0	Covered	T28,T15,T13
1	1	Covered	T22,T23,T24

 LINE       93
 EXPRESSION ((gen_bidir.oe && ((!attr_i.drive_strength[0]))) ? gen_bidir.out : 1'bz)
             -----------------------1-----------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T28,T15,T13

 LINE       93
 SUB-EXPRESSION (gen_bidir.oe && ((!attr_i.drive_strength[0])))
                 ------1-----    --------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T22,T23,T24
1	1	Covered	T28,T15,T13

 LINE       95
 EXPRESSION (attr_i.pull_en ? attr_i.pull_select : 1'bz)
             -------1------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T22,T23,T24

---

Branch Coverage for Instance : tb.dut.u_padring.gen_mio_pads[41].u_mio_pad.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
TERNARY	78	2	2	100.00
TERNARY	92	2	2	100.00
TERNARY	93	2	2	100.00
TERNARY	95	2	2	100.00

78             assign in_raw_o = ie ? inout_io : 1'bz;
                                    -1-  
                                    ==>  
                                    ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T22,T23,T24

92             assign (strong0, strong1) inout_io = (oe && attr_i.drive_strength[0]) ? out : 1'bz;
                                                                                     -1-  
                                                                                     ==>  
                                                                                     ==>  

Branches:

-1-	Status	Tests
1	Covered	T22,T23,T24
0	Covered	T1,T2,T3

93             assign (pull0, pull1)     inout_io = (oe && !attr_i.drive_strength[0]) ? out : 1'bz;
                                                                                      -1-  
                                                                                      ==>  
                                                                                      ==>  

Branches:

-1-	Status	Tests
1	Covered	T28,T15,T13
0	Covered	T1,T2,T3

95             assign (weak0, weak1)     inout_io = attr_i.pull_en ? attr_i.pull_select : 1'bz;
                                                                   -1-  
                                                                   ==>  
                                                                   ==>  

Branches:

-1-	Status	Tests
1	Covered	T22,T23,T24
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_padring.gen_mio_pads[41].u_mio_pad.gen_generic.u_impl_generic

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AnalogNoScan_A	1021	1021	0	0

AnalogNoScan_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1021	1021	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T38	1	1	0	0
T39	1	1	0	0
T106	1	1	0	0

Line Coverage for Instance : tb.dut.u_padring.gen_mio_pads[42].u_mio_pad.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		8	8	100.00
CONT_ASSIGN	39	0	0
CONT_ASSIGN	51	1	1	100.00
CONT_ASSIGN	78	1	1	100.00
CONT_ASSIGN	80	1	1	100.00
CONT_ASSIGN	84	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	93	1	1	100.00
CONT_ASSIGN	95	1	1	100.00

38                        logic unused_sigs;
39         unreachable    assign unused_sigs = ^{attr_i.slew_rate,
40                                               attr_i.drive_strength[3:1],
41                                               attr_i.od_en,
42                                               attr_i.schmitt_en,
43                                               attr_i.keep_en,
44                                               scanmode_i,
45                                               pok_i};
46                        //VCS coverage on
47                        // pragma coverage on
48                      
49                        // Input enable (active-high)
50                        logic ie;
51         1/1            assign ie = ie_i & ~attr_i.input_disable;
           Tests:       T22 T23 T24 
52                      
53                        if (PadType == InputStd) begin : gen_input_only
54                          //VCS coverage off
55                          // pragma coverage off
56                          logic unused_in_sigs;
57                          assign unused_in_sigs = ^{out_i,
58                                                    oe_i,
59                                                    attr_i.virt_od_en,
60                                                    attr_i.drive_strength};
61                          //VCS coverage on
62                          // pragma coverage on
63                      
64                          assign in_raw_o = ie ? inout_io : 1'bz;
65                          // input inversion
66                          assign in_o = attr_i.invert ^ in_raw_o;
67                      
68                        // pulls are not supported by verilator
69                        `ifndef VERILATOR
70                          // pullup / pulldown termination
71                          assign (weak0, weak1) inout_io = attr_i.pull_en ? attr_i.pull_select : 1'bz;
72                        `endif
73                        end else if (PadType == BidirTol ||
74                                     PadType == DualBidirTol ||
75                                     PadType == BidirOd ||
76                                     PadType == BidirStd) begin : gen_bidir
77                      
78         1/1              assign in_raw_o = ie ? inout_io : 1'bz;
           Tests:       T1 T2 T3 
79                          // input inversion
80         1/1              assign in_o = attr_i.invert ^ in_raw_o;
           Tests:       T1 T2 T3 
81                      
82                          // virtual open drain emulation
83                          logic oe, out;
84         1/1              assign out = out_i ^ attr_i.invert;
           Tests:       T28 T13 T50 
85         1/1              assign oe  = oe_i & ((attr_i.virt_od_en & ~out) | ~attr_i.virt_od_en);
           Tests:       T28 T13 T50 
86                      
87                        // drive strength attributes are not supported by verilator
88                        `ifdef VERILATOR
89                          assign inout_io = (oe)   ? out : 1'bz;
90                        `else
91                          // different driver types
92         1/1              assign (strong0, strong1) inout_io = (oe && attr_i.drive_strength[0]) ? out : 1'bz;
           Tests:       T28 T13 T50 
93         1/1              assign (pull0, pull1)     inout_io = (oe && !attr_i.drive_strength[0]) ? out : 1'bz;
           Tests:       T28 T13 T50 
94                          // pullup / pulldown termination
95         1/1              assign (weak0, weak1)     inout_io = attr_i.pull_en ? attr_i.pull_select : 1'bz;
           Tests:       T22 T23 T24 

---

Cond Coverage for Instance : tb.dut.u_padring.gen_mio_pads[42].u_mio_pad.gen_generic.u_impl_generic

	Total	Covered	Percent
Conditions	33	33	100.00
Logical	33	33	100.00
Non-Logical	0	0
Event	0	0

 LINE       51
 EXPRESSION (ie_i & ((~attr_i.input_disable)))
             --1-   ------------2------------

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Covered	T22,T23,T24
1	1	Covered	T1,T2,T3

 LINE       78
 EXPRESSION (ie ? inout_io : 1'bz)
             -1

-1-	Status	Tests
0	Covered	T22,T23,T24
1	Covered	T1,T2,T3

 LINE       80
 EXPRESSION (attr_i.invert ^ in_raw_o)
             ------1------   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T28,T40,T41
1	0	Covered	T22,T23,T24
1	1	Covered	T22,T23,T216

 LINE       84
 EXPRESSION (out_i ^ attr_i.invert)
             --1--   ------2------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T22,T23,T24
1	0	Covered	T28,T13,T50
1	1	Covered	T22,T23,T24

 LINE       85
 EXPRESSION (oe_i & ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en))))
             --1-   ---------------------------------2---------------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T22,T23,T24
1	1	Covered	T28,T13,T50

 LINE       85
 SUB-EXPRESSION ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en)))
                 --------------------1-------------------   -----------2----------

-1-	-2-	Status	Tests
0	0	Covered	T22,T23,T24
0	1	Covered	T1,T2,T3
1	0	Covered	T22,T23,T24

 LINE       85
 SUB-EXPRESSION (attr_i.virt_od_en & ((~gen_bidir.out)))
                 --------1--------   ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T22,T23,T24
1	1	Covered	T22,T23,T24

 LINE       92
 EXPRESSION ((gen_bidir.oe && attr_i.drive_strength[0]) ? gen_bidir.out : 1'bz)
             ---------------------1--------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T22,T23,T24

 LINE       92
 SUB-EXPRESSION (gen_bidir.oe && attr_i.drive_strength[0])
                 ------1-----    ------------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T22,T23,T24
1	0	Covered	T28,T13,T50
1	1	Covered	T22,T23,T24

 LINE       93
 EXPRESSION ((gen_bidir.oe && ((!attr_i.drive_strength[0]))) ? gen_bidir.out : 1'bz)
             -----------------------1-----------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T28,T13,T50

 LINE       93
 SUB-EXPRESSION (gen_bidir.oe && ((!attr_i.drive_strength[0])))
                 ------1-----    --------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T22,T23,T24
1	1	Covered	T28,T13,T50

 LINE       95
 EXPRESSION (attr_i.pull_en ? attr_i.pull_select : 1'bz)
             -------1------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T22,T23,T24

---

Branch Coverage for Instance : tb.dut.u_padring.gen_mio_pads[42].u_mio_pad.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
TERNARY	78	2	2	100.00
TERNARY	92	2	2	100.00
TERNARY	93	2	2	100.00
TERNARY	95	2	2	100.00

78             assign in_raw_o = ie ? inout_io : 1'bz;
                                    -1-  
                                    ==>  
                                    ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T22,T23,T24

92             assign (strong0, strong1) inout_io = (oe && attr_i.drive_strength[0]) ? out : 1'bz;
                                                                                     -1-  
                                                                                     ==>  
                                                                                     ==>  

Branches:

-1-	Status	Tests
1	Covered	T22,T23,T24
0	Covered	T1,T2,T3

93             assign (pull0, pull1)     inout_io = (oe && !attr_i.drive_strength[0]) ? out : 1'bz;
                                                                                      -1-  
                                                                                      ==>  
                                                                                      ==>  

Branches:

-1-	Status	Tests
1	Covered	T28,T13,T50
0	Covered	T1,T2,T3

95             assign (weak0, weak1)     inout_io = attr_i.pull_en ? attr_i.pull_select : 1'bz;
                                                                   -1-  
                                                                   ==>  
                                                                   ==>  

Branches:

-1-	Status	Tests
1	Covered	T22,T23,T24
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_padring.gen_mio_pads[42].u_mio_pad.gen_generic.u_impl_generic

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AnalogNoScan_A	1021	1021	0	0

AnalogNoScan_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1021	1021	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T38	1	1	0	0
T39	1	1	0	0
T106	1	1	0	0