Unified Coverage Report :: Module :: prim_arbiter_fixed

Module : prim_arbiter_fixed

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.88	100.00	86.67			100.00	92.86

Source File(s) :
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.top_earlgrey.u_rv_core_ibex.u_ibus_trans.u_sel_region	94.88	100.00	86.67			100.00	92.86
tb.dut.top_earlgrey.u_rv_core_ibex.u_dbus_trans.u_sel_region	94.88	100.00	86.67			100.00	92.86

---

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_ibus_trans.u_sel_region

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.88	100.00	86.67			100.00	92.86

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.88	100.00	86.67			100.00	92.86

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00		u_ibus_trans

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_dbus_trans.u_sel_region

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.88	100.00	86.67			100.00	92.86

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.88	100.00	86.67			100.00	92.86

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00		u_dbus_trans

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : prim_arbiter_fixed

	Line No.	Total	Covered	Percent
TOTAL		16	16	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	87	1	1	100.00
CONT_ASSIGN	87	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
ALWAYS	105	6	6	100.00
CONT_ASSIGN	121	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	132	1	1	100.00

84                                  // forward path
85         2/2                      assign req_tree[Pa]      = req_i[offset];
           Tests:       T206 T208 T272  | T206 T208 T272 
86                                  assign idx_tree[Pa]      = offset;
87         2/2                      assign data_tree[Pa]     = data_i[offset];
           Tests:       T206 T208 T272  | T206 T208 T272 
88                                  // backward (grant) path
89         2/2                      assign gnt_o[offset]     = gnt_tree[Pa];
           Tests:       T206 T208 T272  | T206 T208 T272 
90                      
91                                end else begin : gen_tie_off
92                                  // forward path
93                                  assign req_tree[Pa]  = '0;
94                                  assign idx_tree[Pa]  = '0;
95                                  assign data_tree[Pa] = '0;
96                                  logic unused_sigs;
97                                  assign unused_sigs = gnt_tree[Pa];
98                                end
99                              // this creates the node assignments
100                             end else begin : gen_nodes
101                               // forward path
102                               logic sel; // local helper variable
103                               always_comb begin : p_node
104                                 // this always gives priority to the left child
105        1/1                      sel = ~req_tree[C0];
           Tests:       T206 T208 T272 
106                                 // propagate requests
107        1/1                      req_tree[Pa]  = req_tree[C0] | req_tree[C1];
           Tests:       T206 T208 T272 
108                                 // data and index muxes
109        1/1                      idx_tree[Pa]  = (sel) ? idx_tree[C1]  : idx_tree[C0];
           Tests:       T206 T208 T272 
110        1/1                      data_tree[Pa] = (sel) ? data_tree[C1] : data_tree[C0];
           Tests:       T206 T208 T272 
111                                 // propagate the grants back to the input
112        1/1                      gnt_tree[C0] = gnt_tree[Pa] & ~sel;
           Tests:       T206 T208 T272 
113        1/1                      gnt_tree[C1] = gnt_tree[Pa] &  sel;
           Tests:       T206 T208 T272 
114                               end
115                             end
116                           end : gen_level
117                         end : gen_tree
118                     
119                         // the results can be found at the tree root
120                         if (EnDataPort) begin : gen_data_port
121        1/1                assign data_o      = data_tree[0];
           Tests:       T206 T208 T272 
122                         end else begin : gen_no_dataport
123                           logic [DW-1:0] unused_data;
124                           assign unused_data = data_tree[0];
125                           assign data_o = '1;
126                         end
127                     
128        1/1              assign idx_o       = idx_tree[0];
           Tests:       T206 T208 T272 
129        1/1              assign valid_o     = req_tree[0];
           Tests:       T206 T208 T272 
130                     
131                         // this propagates a grant back to the input
132        1/1              assign gnt_tree[0] = valid_o & ready_i;
           Tests:       T206 T208 T272 

---

Cond Coverage for Module : prim_arbiter_fixed

	Total	Covered	Percent
Conditions	15	13	86.67
Logical	15	13	86.67
Non-Logical	0	0
Event	0	0

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T206,T208,T272
0	1	Covered	T206,T208,T272
1	0	Not Covered

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T206,T208,T272
1	Covered	T206,T208,T272

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T206,T208,T272
1	Covered	T206,T208,T272

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T206,T208,T272
1	1	Covered	T206,T208,T272

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T206,T208,T272
1	0	Covered	T206,T208,T272
1	1	Covered	T206,T208,T272

 LINE       132
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable
1	1	Covered	T206,T208,T272

---

Branch Coverage for Module : prim_arbiter_fixed

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00

109                    idx_tree[Pa]  = (sel) ? idx_tree[C1]  : idx_tree[C0];
                                             -1-  
                                             ==>  
                                             ==>  

Branches:

-1-	Status	Tests
1	Covered	T206,T208,T272
0	Covered	T206,T208,T272

110                    data_tree[Pa] = (sel) ? data_tree[C1] : data_tree[C0];
                                             -1-  
                                             ==>  
                                             ==>  

Branches:

-1-	Status	Tests
1	Covered	T206,T208,T272
0	Covered	T206,T208,T272

---

Assert Coverage for Module : prim_arbiter_fixed

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	14	14	100.00	13	92.86
Cover properties	0	0		0
Cover sequences	0	0		0
Total	14	14	100.00	13	92.86

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	1017022748	1001616218	0	0
CheckNGreaterZero_A	2042	2042	0	0
GntImpliesReady_A	1017022748	8382	0	0
GntImpliesValid_A	1017022748	8382	0	0
GrantKnown_A	1017022748	1001616218	0	0
IdxKnown_A	1017022748	1001616218	0	0
IndexIsCorrect_A	1017022748	8382	0	0
NoReadyValidNoGrant_A	1017022748	0	0	0
Priority_A	1017022748	8382	0	0
ReadyAndValidImplyGrant_A	1017022748	8382	0	0
ReqAndReadyImplyGrant_A	1017022748	8382	0	0
ReqImpliesValid_A	1017022748	8382	0	0
ValidKnown_A	1017022748	1001616218	0	0
gen_data_port_assertion.DataFlow_A	1017022748	8382	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1017022748	1001616218	0	0
T1	84466	84350	0	0
T2	172452	172336	0	0
T3	137970	137860	0	0
T4	133406	133290	0	0
T5	147898	147796	0	0
T6	164600	164490	0	0
T7	224874	224764	0	0
T38	160174	160072	0	0
T39	141364	141248	0	0
T106	141736	141626	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2042	2042	0	0
T1	2	2	0	0
T2	2	2	0	0
T3	2	2	0	0
T4	2	2	0	0
T5	2	2	0	0
T6	2	2	0	0
T7	2	2	0	0
T38	2	2	0	0
T39	2	2	0	0
T106	2	2	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1017022748	8382	0	0
T94	369154	0	0	0
T165	359712	0	0	0
T206	183378	2795	0	0
T207	183466	0	0	0
T208	0	2791	0	0
T266	1298052	0	0	0
T272	0	2796	0	0
T319	443506	0	0	0
T335	566418	0	0	0
T336	224824	0	0	0
T337	158968	0	0	0
T338	223432	0	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1017022748	8382	0	0
T94	369154	0	0	0
T165	359712	0	0	0
T206	183378	2795	0	0
T207	183466	0	0	0
T208	0	2791	0	0
T266	1298052	0	0	0
T272	0	2796	0	0
T319	443506	0	0	0
T335	566418	0	0	0
T336	224824	0	0	0
T337	158968	0	0	0
T338	223432	0	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1017022748	1001616218	0	0
T1	84466	84350	0	0
T2	172452	172336	0	0
T3	137970	137860	0	0
T4	133406	133290	0	0
T5	147898	147796	0	0
T6	164600	164490	0	0
T7	224874	224764	0	0
T38	160174	160072	0	0
T39	141364	141248	0	0
T106	141736	141626	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1017022748	1001616218	0	0
T1	84466	84350	0	0
T2	172452	172336	0	0
T3	137970	137860	0	0
T4	133406	133290	0	0
T5	147898	147796	0	0
T6	164600	164490	0	0
T7	224874	224764	0	0
T38	160174	160072	0	0
T39	141364	141248	0	0
T106	141736	141626	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1017022748	8382	0	0
T94	369154	0	0	0
T165	359712	0	0	0
T206	183378	2795	0	0
T207	183466	0	0	0
T208	0	2791	0	0
T266	1298052	0	0	0
T272	0	2796	0	0
T319	443506	0	0	0
T335	566418	0	0	0
T336	224824	0	0	0
T337	158968	0	0	0
T338	223432	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1017022748	0	0	0

Priority_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1017022748	8382	0	0
T94	369154	0	0	0
T165	359712	0	0	0
T206	183378	2795	0	0
T207	183466	0	0	0
T208	0	2791	0	0
T266	1298052	0	0	0
T272	0	2796	0	0
T319	443506	0	0	0
T335	566418	0	0	0
T336	224824	0	0	0
T337	158968	0	0	0
T338	223432	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1017022748	8382	0	0
T94	369154	0	0	0
T165	359712	0	0	0
T206	183378	2795	0	0
T207	183466	0	0	0
T208	0	2791	0	0
T266	1298052	0	0	0
T272	0	2796	0	0
T319	443506	0	0	0
T335	566418	0	0	0
T336	224824	0	0	0
T337	158968	0	0	0
T338	223432	0	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1017022748	8382	0	0
T94	369154	0	0	0
T165	359712	0	0	0
T206	183378	2795	0	0
T207	183466	0	0	0
T208	0	2791	0	0
T266	1298052	0	0	0
T272	0	2796	0	0
T319	443506	0	0	0
T335	566418	0	0	0
T336	224824	0	0	0
T337	158968	0	0	0
T338	223432	0	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1017022748	8382	0	0
T94	369154	0	0	0
T165	359712	0	0	0
T206	183378	2795	0	0
T207	183466	0	0	0
T208	0	2791	0	0
T266	1298052	0	0	0
T272	0	2796	0	0
T319	443506	0	0	0
T335	566418	0	0	0
T336	224824	0	0	0
T337	158968	0	0	0
T338	223432	0	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1017022748	1001616218	0	0
T1	84466	84350	0	0
T2	172452	172336	0	0
T3	137970	137860	0	0
T4	133406	133290	0	0
T5	147898	147796	0	0
T6	164600	164490	0	0
T7	224874	224764	0	0
T38	160174	160072	0	0
T39	141364	141248	0	0
T106	141736	141626	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1017022748	8382	0	0
T94	369154	0	0	0
T165	359712	0	0	0
T206	183378	2795	0	0
T207	183466	0	0	0
T208	0	2791	0	0
T266	1298052	0	0	0
T272	0	2796	0	0
T319	443506	0	0	0
T335	566418	0	0	0
T336	224824	0	0	0
T337	158968	0	0	0
T338	223432	0	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_ibus_trans.u_sel_region

	Line No.	Total	Covered	Percent
TOTAL		16	16	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	87	1	1	100.00
CONT_ASSIGN	87	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
ALWAYS	105	6	6	100.00
CONT_ASSIGN	121	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	132	1	1	100.00

84                                  // forward path
85         2/2                      assign req_tree[Pa]      = req_i[offset];
           Tests:       T206 T208 T272  | T206 T208 T272 
86                                  assign idx_tree[Pa]      = offset;
87         2/2                      assign data_tree[Pa]     = data_i[offset];
           Tests:       T206 T208 T272  | T206 T208 T272 
88                                  // backward (grant) path
89         2/2                      assign gnt_o[offset]     = gnt_tree[Pa];
           Tests:       T206 T208 T272  | T206 T208 T272 
90                      
91                                end else begin : gen_tie_off
92                                  // forward path
93                                  assign req_tree[Pa]  = '0;
94                                  assign idx_tree[Pa]  = '0;
95                                  assign data_tree[Pa] = '0;
96                                  logic unused_sigs;
97                                  assign unused_sigs = gnt_tree[Pa];
98                                end
99                              // this creates the node assignments
100                             end else begin : gen_nodes
101                               // forward path
102                               logic sel; // local helper variable
103                               always_comb begin : p_node
104                                 // this always gives priority to the left child
105        1/1                      sel = ~req_tree[C0];
           Tests:       T206 T208 T272 
106                                 // propagate requests
107        1/1                      req_tree[Pa]  = req_tree[C0] | req_tree[C1];
           Tests:       T206 T208 T272 
108                                 // data and index muxes
109        1/1                      idx_tree[Pa]  = (sel) ? idx_tree[C1]  : idx_tree[C0];
           Tests:       T206 T208 T272 
110        1/1                      data_tree[Pa] = (sel) ? data_tree[C1] : data_tree[C0];
           Tests:       T206 T208 T272 
111                                 // propagate the grants back to the input
112        1/1                      gnt_tree[C0] = gnt_tree[Pa] & ~sel;
           Tests:       T206 T208 T272 
113        1/1                      gnt_tree[C1] = gnt_tree[Pa] &  sel;
           Tests:       T206 T208 T272 
114                               end
115                             end
116                           end : gen_level
117                         end : gen_tree
118                     
119                         // the results can be found at the tree root
120                         if (EnDataPort) begin : gen_data_port
121        1/1                assign data_o      = data_tree[0];
           Tests:       T206 T208 T272 
122                         end else begin : gen_no_dataport
123                           logic [DW-1:0] unused_data;
124                           assign unused_data = data_tree[0];
125                           assign data_o = '1;
126                         end
127                     
128        1/1              assign idx_o       = idx_tree[0];
           Tests:       T206 T208 T272 
129        1/1              assign valid_o     = req_tree[0];
           Tests:       T206 T208 T272 
130                     
131                         // this propagates a grant back to the input
132        1/1              assign gnt_tree[0] = valid_o & ready_i;
           Tests:       T206 T208 T272 

---

Cond Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_ibus_trans.u_sel_region

	Total	Covered	Percent
Conditions	15	13	86.67
Logical	15	13	86.67
Non-Logical	0	0
Event	0	0

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T206,T208,T272
0	1	Covered	T206,T208,T272
1	0	Not Covered

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T206,T208,T272
1	Covered	T206,T208,T272

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T206,T208,T272
1	Covered	T206,T208,T272

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T206,T208,T272
1	1	Covered	T206,T208,T272

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T206,T208,T272
1	0	Covered	T206,T208,T272
1	1	Covered	T206,T208,T272

 LINE       132
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable
1	1	Covered	T206,T208,T272

---

Branch Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_ibus_trans.u_sel_region

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00

109                    idx_tree[Pa]  = (sel) ? idx_tree[C1]  : idx_tree[C0];
                                             -1-  
                                             ==>  
                                             ==>  

Branches:

-1-	Status	Tests
1	Covered	T206,T208,T272
0	Covered	T206,T208,T272

110                    data_tree[Pa] = (sel) ? data_tree[C1] : data_tree[C0];
                                             -1-  
                                             ==>  
                                             ==>  

Branches:

-1-	Status	Tests
1	Covered	T206,T208,T272
0	Covered	T206,T208,T272

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_ibus_trans.u_sel_region

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	14	14	100.00	13	92.86
Cover properties	0	0		0
Cover sequences	0	0		0
Total	14	14	100.00	13	92.86

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	508511374	500808109	0	0
CheckNGreaterZero_A	1021	1021	0	0
GntImpliesReady_A	508511374	5192	0	0
GntImpliesValid_A	508511374	5192	0	0
GrantKnown_A	508511374	500808109	0	0
IdxKnown_A	508511374	500808109	0	0
IndexIsCorrect_A	508511374	5192	0	0
NoReadyValidNoGrant_A	508511374	0	0	0
Priority_A	508511374	5192	0	0
ReadyAndValidImplyGrant_A	508511374	5192	0	0
ReqAndReadyImplyGrant_A	508511374	5192	0	0
ReqImpliesValid_A	508511374	5192	0	0
ValidKnown_A	508511374	500808109	0	0
gen_data_port_assertion.DataFlow_A	508511374	5192	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	508511374	500808109	0	0
T1	42233	42175	0	0
T2	86226	86168	0	0
T3	68985	68930	0	0
T4	66703	66645	0	0
T5	73949	73898	0	0
T6	82300	82245	0	0
T7	112437	112382	0	0
T38	80087	80036	0	0
T39	70682	70624	0	0
T106	70868	70813	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1021	1021	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T38	1	1	0	0
T39	1	1	0	0
T106	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	508511374	5192	0	0
T94	184577	0	0	0
T165	179856	0	0	0
T206	91689	1732	0	0
T207	91733	0	0	0
T208	0	1728	0	0
T266	649026	0	0	0
T272	0	1732	0	0
T319	221753	0	0	0
T335	283209	0	0	0
T336	112412	0	0	0
T337	79484	0	0	0
T338	111716	0	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	508511374	5192	0	0
T94	184577	0	0	0
T165	179856	0	0	0
T206	91689	1732	0	0
T207	91733	0	0	0
T208	0	1728	0	0
T266	649026	0	0	0
T272	0	1732	0	0
T319	221753	0	0	0
T335	283209	0	0	0
T336	112412	0	0	0
T337	79484	0	0	0
T338	111716	0	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	508511374	500808109	0	0
T1	42233	42175	0	0
T2	86226	86168	0	0
T3	68985	68930	0	0
T4	66703	66645	0	0
T5	73949	73898	0	0
T6	82300	82245	0	0
T7	112437	112382	0	0
T38	80087	80036	0	0
T39	70682	70624	0	0
T106	70868	70813	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	508511374	500808109	0	0
T1	42233	42175	0	0
T2	86226	86168	0	0
T3	68985	68930	0	0
T4	66703	66645	0	0
T5	73949	73898	0	0
T6	82300	82245	0	0
T7	112437	112382	0	0
T38	80087	80036	0	0
T39	70682	70624	0	0
T106	70868	70813	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	508511374	5192	0	0
T94	184577	0	0	0
T165	179856	0	0	0
T206	91689	1732	0	0
T207	91733	0	0	0
T208	0	1728	0	0
T266	649026	0	0	0
T272	0	1732	0	0
T319	221753	0	0	0
T335	283209	0	0	0
T336	112412	0	0	0
T337	79484	0	0	0
T338	111716	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	508511374	0	0	0

Priority_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	508511374	5192	0	0
T94	184577	0	0	0
T165	179856	0	0	0
T206	91689	1732	0	0
T207	91733	0	0	0
T208	0	1728	0	0
T266	649026	0	0	0
T272	0	1732	0	0
T319	221753	0	0	0
T335	283209	0	0	0
T336	112412	0	0	0
T337	79484	0	0	0
T338	111716	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	508511374	5192	0	0
T94	184577	0	0	0
T165	179856	0	0	0
T206	91689	1732	0	0
T207	91733	0	0	0
T208	0	1728	0	0
T266	649026	0	0	0
T272	0	1732	0	0
T319	221753	0	0	0
T335	283209	0	0	0
T336	112412	0	0	0
T337	79484	0	0	0
T338	111716	0	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	508511374	5192	0	0
T94	184577	0	0	0
T165	179856	0	0	0
T206	91689	1732	0	0
T207	91733	0	0	0
T208	0	1728	0	0
T266	649026	0	0	0
T272	0	1732	0	0
T319	221753	0	0	0
T335	283209	0	0	0
T336	112412	0	0	0
T337	79484	0	0	0
T338	111716	0	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	508511374	5192	0	0
T94	184577	0	0	0
T165	179856	0	0	0
T206	91689	1732	0	0
T207	91733	0	0	0
T208	0	1728	0	0
T266	649026	0	0	0
T272	0	1732	0	0
T319	221753	0	0	0
T335	283209	0	0	0
T336	112412	0	0	0
T337	79484	0	0	0
T338	111716	0	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	508511374	500808109	0	0
T1	42233	42175	0	0
T2	86226	86168	0	0
T3	68985	68930	0	0
T4	66703	66645	0	0
T5	73949	73898	0	0
T6	82300	82245	0	0
T7	112437	112382	0	0
T38	80087	80036	0	0
T39	70682	70624	0	0
T106	70868	70813	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	508511374	5192	0	0
T94	184577	0	0	0
T165	179856	0	0	0
T206	91689	1732	0	0
T207	91733	0	0	0
T208	0	1728	0	0
T266	649026	0	0	0
T272	0	1732	0	0
T319	221753	0	0	0
T335	283209	0	0	0
T336	112412	0	0	0
T337	79484	0	0	0
T338	111716	0	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_dbus_trans.u_sel_region

	Line No.	Total	Covered	Percent
TOTAL		16	16	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	87	1	1	100.00
CONT_ASSIGN	87	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
ALWAYS	105	6	6	100.00
CONT_ASSIGN	121	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	132	1	1	100.00

84                                  // forward path
85         2/2                      assign req_tree[Pa]      = req_i[offset];
           Tests:       T206 T208 T272  | T206 T208 T272 
86                                  assign idx_tree[Pa]      = offset;
87         2/2                      assign data_tree[Pa]     = data_i[offset];
           Tests:       T206 T208 T272  | T206 T208 T272 
88                                  // backward (grant) path
89         2/2                      assign gnt_o[offset]     = gnt_tree[Pa];
           Tests:       T206 T208 T272  | T206 T208 T272 
90                      
91                                end else begin : gen_tie_off
92                                  // forward path
93                                  assign req_tree[Pa]  = '0;
94                                  assign idx_tree[Pa]  = '0;
95                                  assign data_tree[Pa] = '0;
96                                  logic unused_sigs;
97                                  assign unused_sigs = gnt_tree[Pa];
98                                end
99                              // this creates the node assignments
100                             end else begin : gen_nodes
101                               // forward path
102                               logic sel; // local helper variable
103                               always_comb begin : p_node
104                                 // this always gives priority to the left child
105        1/1                      sel = ~req_tree[C0];
           Tests:       T206 T208 T272 
106                                 // propagate requests
107        1/1                      req_tree[Pa]  = req_tree[C0] | req_tree[C1];
           Tests:       T206 T208 T272 
108                                 // data and index muxes
109        1/1                      idx_tree[Pa]  = (sel) ? idx_tree[C1]  : idx_tree[C0];
           Tests:       T206 T208 T272 
110        1/1                      data_tree[Pa] = (sel) ? data_tree[C1] : data_tree[C0];
           Tests:       T206 T208 T272 
111                                 // propagate the grants back to the input
112        1/1                      gnt_tree[C0] = gnt_tree[Pa] & ~sel;
           Tests:       T206 T208 T272 
113        1/1                      gnt_tree[C1] = gnt_tree[Pa] &  sel;
           Tests:       T206 T208 T272 
114                               end
115                             end
116                           end : gen_level
117                         end : gen_tree
118                     
119                         // the results can be found at the tree root
120                         if (EnDataPort) begin : gen_data_port
121        1/1                assign data_o      = data_tree[0];
           Tests:       T206 T208 T272 
122                         end else begin : gen_no_dataport
123                           logic [DW-1:0] unused_data;
124                           assign unused_data = data_tree[0];
125                           assign data_o = '1;
126                         end
127                     
128        1/1              assign idx_o       = idx_tree[0];
           Tests:       T206 T208 T272 
129        1/1              assign valid_o     = req_tree[0];
           Tests:       T206 T208 T272 
130                     
131                         // this propagates a grant back to the input
132        1/1              assign gnt_tree[0] = valid_o & ready_i;
           Tests:       T206 T208 T272 

---

Cond Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_dbus_trans.u_sel_region

	Total	Covered	Percent
Conditions	15	13	86.67
Logical	15	13	86.67
Non-Logical	0	0
Event	0	0

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T206,T208,T272
0	1	Covered	T206,T208,T272
1	0	Not Covered

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T206,T208,T272
1	Covered	T206,T208,T272

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T206,T208,T272
1	Covered	T206,T208,T272

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T206,T208,T272
1	1	Covered	T206,T208,T272

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T206,T208,T272
1	0	Covered	T206,T208,T272
1	1	Covered	T206,T208,T272

 LINE       132
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable
1	1	Covered	T206,T208,T272

---

Branch Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_dbus_trans.u_sel_region

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00

109                    idx_tree[Pa]  = (sel) ? idx_tree[C1]  : idx_tree[C0];
                                             -1-  
                                             ==>  
                                             ==>  

Branches:

-1-	Status	Tests
1	Covered	T206,T208,T272
0	Covered	T206,T208,T272

110                    data_tree[Pa] = (sel) ? data_tree[C1] : data_tree[C0];
                                             -1-  
                                             ==>  
                                             ==>  

Branches:

-1-	Status	Tests
1	Covered	T206,T208,T272
0	Covered	T206,T208,T272

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_dbus_trans.u_sel_region

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	14	14	100.00	13	92.86
Cover properties	0	0		0
Cover sequences	0	0		0
Total	14	14	100.00	13	92.86

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	508511374	500808109	0	0
CheckNGreaterZero_A	1021	1021	0	0
GntImpliesReady_A	508511374	3190	0	0
GntImpliesValid_A	508511374	3190	0	0
GrantKnown_A	508511374	500808109	0	0
IdxKnown_A	508511374	500808109	0	0
IndexIsCorrect_A	508511374	3190	0	0
NoReadyValidNoGrant_A	508511374	0	0	0
Priority_A	508511374	3190	0	0
ReadyAndValidImplyGrant_A	508511374	3190	0	0
ReqAndReadyImplyGrant_A	508511374	3190	0	0
ReqImpliesValid_A	508511374	3190	0	0
ValidKnown_A	508511374	500808109	0	0
gen_data_port_assertion.DataFlow_A	508511374	3190	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	508511374	500808109	0	0
T1	42233	42175	0	0
T2	86226	86168	0	0
T3	68985	68930	0	0
T4	66703	66645	0	0
T5	73949	73898	0	0
T6	82300	82245	0	0
T7	112437	112382	0	0
T38	80087	80036	0	0
T39	70682	70624	0	0
T106	70868	70813	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1021	1021	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T38	1	1	0	0
T39	1	1	0	0
T106	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	508511374	3190	0	0
T94	184577	0	0	0
T165	179856	0	0	0
T206	91689	1063	0	0
T207	91733	0	0	0
T208	0	1063	0	0
T266	649026	0	0	0
T272	0	1064	0	0
T319	221753	0	0	0
T335	283209	0	0	0
T336	112412	0	0	0
T337	79484	0	0	0
T338	111716	0	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	508511374	3190	0	0
T94	184577	0	0	0
T165	179856	0	0	0
T206	91689	1063	0	0
T207	91733	0	0	0
T208	0	1063	0	0
T266	649026	0	0	0
T272	0	1064	0	0
T319	221753	0	0	0
T335	283209	0	0	0
T336	112412	0	0	0
T337	79484	0	0	0
T338	111716	0	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	508511374	500808109	0	0
T1	42233	42175	0	0
T2	86226	86168	0	0
T3	68985	68930	0	0
T4	66703	66645	0	0
T5	73949	73898	0	0
T6	82300	82245	0	0
T7	112437	112382	0	0
T38	80087	80036	0	0
T39	70682	70624	0	0
T106	70868	70813	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	508511374	500808109	0	0
T1	42233	42175	0	0
T2	86226	86168	0	0
T3	68985	68930	0	0
T4	66703	66645	0	0
T5	73949	73898	0	0
T6	82300	82245	0	0
T7	112437	112382	0	0
T38	80087	80036	0	0
T39	70682	70624	0	0
T106	70868	70813	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	508511374	3190	0	0
T94	184577	0	0	0
T165	179856	0	0	0
T206	91689	1063	0	0
T207	91733	0	0	0
T208	0	1063	0	0
T266	649026	0	0	0
T272	0	1064	0	0
T319	221753	0	0	0
T335	283209	0	0	0
T336	112412	0	0	0
T337	79484	0	0	0
T338	111716	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	508511374	0	0	0

Priority_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	508511374	3190	0	0
T94	184577	0	0	0
T165	179856	0	0	0
T206	91689	1063	0	0
T207	91733	0	0	0
T208	0	1063	0	0
T266	649026	0	0	0
T272	0	1064	0	0
T319	221753	0	0	0
T335	283209	0	0	0
T336	112412	0	0	0
T337	79484	0	0	0
T338	111716	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	508511374	3190	0	0
T94	184577	0	0	0
T165	179856	0	0	0
T206	91689	1063	0	0
T207	91733	0	0	0
T208	0	1063	0	0
T266	649026	0	0	0
T272	0	1064	0	0
T319	221753	0	0	0
T335	283209	0	0	0
T336	112412	0	0	0
T337	79484	0	0	0
T338	111716	0	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	508511374	3190	0	0
T94	184577	0	0	0
T165	179856	0	0	0
T206	91689	1063	0	0
T207	91733	0	0	0
T208	0	1063	0	0
T266	649026	0	0	0
T272	0	1064	0	0
T319	221753	0	0	0
T335	283209	0	0	0
T336	112412	0	0	0
T337	79484	0	0	0
T338	111716	0	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	508511374	3190	0	0
T94	184577	0	0	0
T165	179856	0	0	0
T206	91689	1063	0	0
T207	91733	0	0	0
T208	0	1063	0	0
T266	649026	0	0	0
T272	0	1064	0	0
T319	221753	0	0	0
T335	283209	0	0	0
T336	112412	0	0	0
T337	79484	0	0	0
T338	111716	0	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	508511374	500808109	0	0
T1	42233	42175	0	0
T2	86226	86168	0	0
T3	68985	68930	0	0
T4	66703	66645	0	0
T5	73949	73898	0	0
T6	82300	82245	0	0
T7	112437	112382	0	0
T38	80087	80036	0	0
T39	70682	70624	0	0
T106	70868	70813	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	508511374	3190	0	0
T94	184577	0	0	0
T165	179856	0	0	0
T206	91689	1063	0	0
T207	91733	0	0	0
T208	0	1063	0	0
T266	649026	0	0	0
T272	0	1064	0	0
T319	221753	0	0	0
T335	283209	0	0	0
T336	112412	0	0	0
T337	79484	0	0	0
T338	111716	0	0	0