Go
back
71 if (offset < NumSrc) begin : gen_assign
72 185/186 ==> assign vld_tree[Pa] = valid_i[offset];
Tests: T131 T346 T350 | T131 T346 T350 | T131 T346 T351 | T131 T346 T351 | T346 T352 T353 | T346 T352 T353 | T346 T352 T353 | T346 T352 T353 | T131 T346 T350 | T32 T346 T132 | T32 T346 T132 | T32 T346 T132 | T32 T346 T132 | T346 T352 T353 | T346 T352 T353 | T346 T352 T353 | T346 T352 T353 | T32 T346 T132 | T31 T37 T346 | T31 T37 T346 | T31 T37 T346 | T31 T37 T346 | T346 T352 T353 | T346 T352 T353 | T346 T352 T353 | T346 T352 T353 | T31 T37 T346 | T29 T72 T73 | T29 T72 T73 | T29 T72 T73 | T29 T72 T73 | T346 T352 T353 | T346 T352 T353 | T346 T352 T353 | T346 T352 T353 | T29 T72 T73 | T28 T344 T51 | T28 T344 T51 | T28 T344 T51 | T28 T344 T51 | T28 T344 T51 | T28 T344 T51 | T28 T344 T51 | T28 T344 T51 | T28 T344 T51 | T28 T344 T51 | T28 T344 T51 | T28 T344 T51 | T28 T344 T51 | T28 T344 T51 | T28 T344 T51 | T28 T344 T51 | T28 T344 T51 | T28 T344 T51 | T28 T344 T51 | T28 T344 T51 | T28 T344 T51 | T28 T344 T51 | T28 T344 T51 | T28 T344 T51 | T28 T344 T51 | T28 T344 T51 | T28 T344 T51 | T28 T344 T51 | T28 T344 T51 | T28 T344 T51 | T28 T344 T51 | T28 T344 T51 | T11 T128 T226 | T128 T186 T187 | T128 T186 T187 | T128 T186 T187 | T128 T186 T187 | T14 T128 T58 | T128 T186 T187 | T128 T186 T187 | T68 T344 T69 | T68 T344 T69 | T344 T354 T355 | T344 T354 T355 | T344 T354 T355 | T344 T354 T355 | T344 T354 T355 | T344 T354 T355 | T344 T354 T355 | T68 T344 T69 | T344 T354 T355 | T344 T354 T355 | T344 T354 T355 | T344 T354 T355 | T344 T354 T355 | T34 T344 T70 | T34 T344 T70 | T344 T354 T355 | T344 T354 T355 | T344 T354 T355 | T344 T354 T355 | T344 T354 T355 | T344 T354 T355 | T344 T354 T355 | T34 T344 T70 | T344 T354 T355 | T344 T354 T355 | T344 T354 T355 | T344 T354 T355 | T344 T354 T355 | T71 T344 T308 | T71 T344 T308 | T344 T354 T355 | T344 T354 T355 | T344 T354 T355 | T344 T354 T355 | T344 T354 T355 | T344 T354 T355 | T344 T354 T355 | T35 T71 T344 | T344 T354 T355 | T344 T354 T355 | T344 T354 T355 | T344 T354 T355 | T344 T354 T355 | T2 T128 T186 | T2 T128 T135 | T128 T186 T187 | T128 T186 T187 | T128 T186 T187 | T89 T188 T295 | T88 T356 T189 | T53 T344 T301 | T189 T344 T357 | T128 T186 T187 | T128 T186 T187 | T128 T186 T187 | T128 T186 T187 | T346 T352 T353 | T346 T352 T353 | T346 T352 T353 | T346 T352 T353 | T346 T352 T353 | T346 T352 T353 | T346 T352 T353 | T346 T352 T353 | T346 T352 T353 | T346 T352 T353 | T346 T352 T353 | T346 T352 T353 | T346 T352 T353 | T346 T352 T353 | T346 T352 T353 | T346 T352 T353 | T346 T352 T353 | T346 T352 T353 | T5 T6 T27 | T75 T346 T234 | T138 T344 T139 | T358 T268 T344 | T267 T268 T375 | T177 T128 T359 | T128 T186 T187 | T121 T225 T145 | T121 T225 T145 | T225 T145 T344 | T225 T145 T344 | T121 T225 T145 | T344 T354 T355 | T347 T348 T344 | T344 T354 T355 | T344 T354 T355 | T128 T186 T187 | T128 T186 T187 | T128 T186 T187 | T160 T128 T144 | T128 T186 T187 | T344 T354 T355 | T344 T360 T361 | T344 T354 T355 | T344 T354 T355 | T344 T354 T355 | T344 T354 T355 | T344 T354 T355 | T344 T354 T355 | T344 T360 T361 | T344 T354 T355 | T344 T360 T361 | T344 T354 T355
73 assign idx_tree[Pa] = offset;
74 186/186 assign max_tree[Pa] = values_i[offset];
Tests: T283 T284 T345 | T131 T346 T283 | T131 T346 T283 | T131 T346 T283 | T131 T346 T283 | T131 T346 T283 | T131 T346 T283 | T131 T346 T283 | T131 T346 T283 | T131 T346 T283 | T32 T346 T283 | T32 T346 T283 | T32 T346 T283 | T32 T346 T283 | T32 T346 T283 | T32 T346 T283 | T32 T346 T283 | T32 T346 T283 | T32 T346 T283 | T31 T37 T346 | T31 T37 T346 | T31 T37 T346 | T31 T37 T346 | T31 T37 T346 | T31 T37 T346 | T31 T37 T346 | T31 T37 T346 | T31 T37 T346 | T29 T72 T73 | T29 T72 T73 | T29 T72 T73 | T29 T72 T73 | T29 T72 T73 | T29 T72 T73 | T29 T72 T73 | T29 T72 T73 | T29 T72 T73 | T28 T346 T283 | T28 T346 T283 | T28 T346 T283 | T28 T346 T283 | T28 T346 T283 | T28 T346 T283 | T28 T346 T283 | T28 T346 T283 | T28 T346 T283 | T28 T346 T283 | T28 T346 T283 | T28 T346 T283 | T28 T346 T283 | T28 T346 T283 | T28 T346 T283 | T28 T346 T283 | T28 T346 T283 | T28 T346 T283 | T28 T346 T283 | T28 T346 T283 | T28 T346 T283 | T28 T346 T283 | T28 T346 T283 | T28 T346 T283 | T28 T346 T283 | T28 T346 T283 | T28 T346 T283 | T28 T346 T283 | T28 T346 T283 | T28 T346 T283 | T28 T346 T283 | T28 T346 T283 | T14 T28 T11 | T14 T346 T283 | T14 T346 T283 | T14 T11 T12 | T14 T11 T12 | T14 T346 T283 | T346 T283 T128 | T346 T283 T128 | T68 T346 T283 | T68 T346 T283 | T346 T283 T128 | T68 T346 T283 | T68 T346 T283 | T68 T346 T283 | T68 T346 T283 | T68 T346 T283 | T346 T283 T128 | T68 T346 T283 | T346 T283 T128 | T346 T283 T128 | T346 T283 T128 | T346 T283 T128 | T346 T283 T128 | T34 T346 T283 | T34 T346 T283 | T346 T283 T128 | T34 T346 T283 | T34 T346 T283 | T34 T346 T283 | T34 T346 T283 | T34 T346 T283 | T346 T283 T128 | T34 T346 T283 | T346 T283 T128 | T346 T283 T128 | T346 T283 T128 | T346 T283 T128 | T346 T283 T128 | T71 T346 T283 | T71 T346 T283 | T346 T283 T128 | T71 T346 T283 | T71 T346 T283 | T71 T346 T283 | T71 T346 T283 | T71 T346 T283 | T346 T283 T128 | T35 T71 T346 | T35 T346 T283 | T346 T283 T128 | T35 T346 T283 | T35 T346 T283 | T35 T346 T283 | T2 T346 T283 | T2 T346 T283 | T346 T283 T128 | T346 T283 T128 | T346 T283 T128 | T53 T88 T89 | T53 T88 T89 | T53 T88 T89 | T53 T88 T89 | T11 T12 T346 | T11 T12 T346 | T346 T283 T128 | T346 T283 T128 | T346 T283 T128 | T346 T283 T128 | T346 T283 T128 | T346 T283 T128 | T346 T283 T128 | T346 T283 T128 | T346 T283 T128 | T346 T283 T128 | T346 T283 T128 | T346 T283 T128 | T346 T283 T128 | T346 T283 T128 | T346 T283 T128 | T346 T283 T128 | T346 T283 T128 | T346 T283 T128 | T346 T283 T128 | T346 T283 T128 | T5 T6 T27 | T75 T346 T283 | T138 T346 T283 | T53 T88 T89 | T267 T53 T88 | T177 T346 T283 | T346 T283 T128 | T121 T225 T145 | T121 T225 T145 | T121 T225 T145 | T121 T225 T145 | T121 T225 T145 | T346 T283 T128 | T347 T348 T346 | T347 T348 T346 | T346 T283 T128 | T346 T283 T128 | T346 T283 T128 | T346 T283 T128 | T160 T346 T283 | T346 T283 T128 | T346 T283 T128 | T346 T283 T128 | T346 T283 T128 | T346 T283 T128 | T346 T283 T128 | T346 T283 T128 | T346 T283 T128 | T346 T283 T128 | T346 T283 T128 | T346 T283 T128 | T346 T283 T128 | T346 T283 T128
75 end else begin : gen_tie_off
76 assign vld_tree[Pa] = '0;
77 assign idx_tree[Pa] = '0;
78 assign max_tree[Pa] = '0;
79 end
80 // This creates the node assignments.
81 end else begin : gen_nodes
82 logic sel; // Local helper variable
83 // In case only one of the parents is valid, forward that one
84 // In case both parents are valid, forward the one with higher value
85 185/185(70 unreachable) assign sel = (~vld_tree[C0] & vld_tree[C1]) |
Tests: T2 T5 T6 | T2 T14 T31 | T31 T28 T29 | T2 T14 T28 | T5 T6 T121 | T31 T29 T131 | T28 T29 T72 | T14 T28 T34 | T2 T35 T34 | T5 T6 T27 | T121 T225 T145 | T131 T32 T346 | T31 T29 T32 | T28 T29 T72 | T28 T346 T283 | T14 T28 T11 | T34 T68 T346 | T34 T71 T346 | T2 T35 T89 | T53 T88 T89 | T5 T6 T27 | T121 T225 T145 | T346 T283 T128 | T131 T346 T283 | T131 T32 T346 | T31 T32 T37 | T31 T29 T37 | T28 T29 T72 | T28 T346 T283 | T28 T346 T283 | T28 T346 T283 | T28 T11 T346 | T14 T11 T68 | T68 T346 T283 | T34 T346 T283 | T34 T346 T283 | T71 T346 T283 | T35 T71 T346 | T2 T35 T89 | T11 T53 T88 | T346 T283 T128 | T346 T283 T128 | T5 T6 T27 | T121 T225 T145 | T160 T346 T283 | T346 T283 T128 | T131 T346 T283 | T131 T346 T283 | T131 T32 T346 | T32 T346 T283 | T31 T32 T37 | T31 T37 T346 | T31 T37 T346 | T29 T72 T73 | T29 T72 T73 | T28 T29 T72 | T28 T346 T283 | T28 T346 T283 | T28 T346 T283 | T28 T346 T283 | T28 T346 T283 | T28 T346 T283 | T28 T346 T283 | T14 T28 T11 | T14 T11 T12 | T68 T346 T283 | T68 T346 T283 | T68 T346 T283 | T346 T283 T128 | T34 T346 T283 | T34 T346 T283 | T34 T346 T283 | T71 T346 T283 | T71 T346 T283 | T71 T346 T283 | T35 T71 T346 | T2 T35 T346 | T89 T188 T295 | T53 T88 T89 | T11 T12 T346 | T346 T283 T128 | T346 T283 T128 | T346 T283 T128 | T346 T283 T128 | T5 T6 T27 | T267 T53 T88 | T121 T225 T145 | T121 T225 T145 | T346 T283 T128 | T160 T346 T283 | T346 T283 T128 | T346 T283 T128 | T131 T346 T283 | T131 T346 T283 | T131 T346 T283 | T131 T346 T283 | T131 T346 T283 | T32 T346 T283 | T32 T346 T283 | T32 T346 T283 | T32 T346 T283 | T31 T32 T37 | T31 T37 T346 | T31 T37 T346 | T31 T37 T346 | T31 T37 T346 | T29 T72 T73 | T29 T72 T73 | T29 T72 T73 | T29 T72 T73 | T28 T29 T72 | T28 T346 T283 | T28 T346 T283 | T28 T346 T283 | T28 T346 T283 | T28 T346 T283 | T28 T346 T283 | T28 T346 T283 | T28 T346 T283 | T28 T346 T283 | T28 T346 T283 | T28 T346 T283 | T28 T346 T283 | T28 T346 T283 | T28 T346 T283 | T28 T346 T283 | T14 T28 T11 | T14 T346 T283 | T14 T11 T12 | T14 T346 T283 | T68 T346 T283 | T68 T346 T283 | T68 T346 T283 | T68 T346 T283 | T68 T346 T283 | T68 T346 T283 | T346 T283 T128 | T346 T283 T128 | T34 T346 T283 | T34 T346 T283 | T34 T346 T283 | T34 T346 T283 | T34 T346 T283 | T346 T283 T128 | T346 T283 T128 | T71 T346 T283 | T71 T346 T283 | T71 T346 T283 | T71 T346 T283 | T71 T346 T283 | T35 T71 T346 | T35 T346 T283 | T35 T346 T283 | T2 T346 T283 | T346 T283 T128 | T53 T88 T89 | T53 T88 T89 | T11 T53 T88 | T11 T12 T346 | T346 T283 T128 | T346 T283 T128 | T346 T283 T128 | T346 T283 T128 | T346 T283 T128 | T346 T283 T128 | T346 T283 T128 | T346 T283 T128 | T346 T283 T128 | T5 T6 T27 | T138 T75 T346 | T267 T53 T88 | T177 T346 T283 | T121 T225 T145 | T121 T225 T145 | T121 T225 T145 | T347 T348 T346 | T346 T283 T128 | T346 T283 T128 | T160 T346 T283 | T346 T283 T128 | T346 T283 T128 | T346 T283 T128 | T346 T283 T128 | T346 T283 T128 | T346 T283 T128
86 (vld_tree[C0] & vld_tree[C1] & logic'(max_tree[C1] > max_tree[C0]));
87 // Forwarding muxes
88 // Note: these ternaries have triggered a synthesis bug in Vivado versions older
89 // than 2020.2. If the problem resurfaces again, have a look at issue #1408.
90 188/188(67 unreachable) assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
Tests: T2 T5 T6 | T2 T14 T31 | T5 T6 T121 | T31 T28 T29 | T2 T14 T28 | T5 T6 T121 | T31 T29 T131 | T28 T29 T72 | T14 T28 T34 | T2 T35 T34 | T5 T6 T27 | T121 T225 T145 | T131 T32 T346 | T31 T29 T32 | T28 T29 T72 | T28 T344 T51 | T14 T28 T11 | T34 T68 T344 | T34 T71 T344 | T2 T35 T89 | T53 T88 T356 | T5 T6 T27 | T121 T225 T145 | T344 T360 T361 | T131 T346 T351 | T131 T32 T346 | T31 T32 T37 | T31 T29 T37 | T28 T29 T72 | T28 T344 T51 | T28 T344 T51 | T28 T344 T51 | T28 T11 T128 | T14 T68 T128 | T68 T344 T69 | T34 T344 T70 | T34 T344 T70 | T71 T344 T308 | T35 T71 T344 | T2 T89 T188 | T53 T88 T356 | T346 T352 T353 | T346 T352 T353 | T5 T6 T27 | T121 T225 T145 | T160 T128 T344 | T344 T360 T361 | T344 T360 T361 | T131 T346 T351 | T131 T346 T351 | T131 T32 T346 | T32 T346 T132 | T31 T32 T37 | T31 T37 T346 | T31 T37 T346 | T29 T72 T73 | T346 T352 T353 | T28 T29 T72 | T28 T344 T51 | T28 T344 T51 | T28 T344 T51 | T28 T344 T51 | T28 T344 T51 | T28 T344 T51 | T28 T344 T51 | T28 T11 T128 | T14 T128 T58 | T68 T128 T344 | T344 T354 T355 | T68 T344 T69 | T344 T354 T355 | T34 T344 T70 | T344 T354 T355 | T34 T344 T70 | T71 T344 T308 | T71 T344 T308 | T344 T354 T355 | T35 T71 T344 | T2 T128 T344 | T89 T188 T295 | T53 T88 T356 | T346 T128 T186 | T346 T352 T353 | T346 T352 T353 | T346 T352 T353 | T346 T352 T353 | T5 T6 T27 | T267 T358 T268 | T121 T225 T145 | T121 T225 T145 | T128 T344 T186 | T160 T128 T344 | T344 T354 T355 | T344 T360 T361 | T344 T360 T361 | T131 T346 T350 | T131 T346 T351 | T131 T346 T351 | T346 T352 T353 | T131 T346 T350 | T32 T346 T132 | T32 T346 T132 | T346 T352 T353 | T346 T352 T353 | T31 T32 T37 | T31 T37 T346 | T31 T37 T346 | T346 T352 T353 | T31 T37 T346 | T29 T72 T73 | T29 T72 T73 | T346 T352 T353 | T346 T352 T353 | T28 T29 T72 | T28 T344 T51 | T28 T344 T51 | T28 T344 T51 | T28 T344 T51 | T28 T344 T51 | T28 T344 T51 | T28 T344 T51 | T28 T344 T51 | T28 T344 T51 | T28 T344 T51 | T28 T344 T51 | T28 T344 T51 | T28 T344 T51 | T28 T344 T51 | T28 T344 T51 | T28 T11 T128 | T128 T186 T187 | T128 T186 T187 | T14 T128 T58 | T68 T128 T344 | T68 T344 T69 | T344 T354 T355 | T344 T354 T355 | T344 T354 T355 | T68 T344 T69 | T344 T354 T355 | T344 T354 T355 | T34 T344 T70 | T344 T354 T355 | T344 T354 T355 | T344 T354 T355 | T34 T344 T70 | T344 T354 T355 | T344 T354 T355 | T71 T344 T308 | T71 T344 T308 | T344 T354 T355 | T344 T354 T355 | T344 T354 T355 | T35 T71 T344 | T344 T354 T355 | T344 T354 T355 | T2 T128 T135 | T128 T186 T187 | T89 T188 T295 | T53 T88 T356 | T189 T128 T344 | T128 T186 T187 | T346 T128 T186 | T346 T352 T353 | T346 T352 T353 | T346 T352 T353 | T346 T352 T353 | T346 T352 T353 | T346 T352 T353 | T346 T352 T353 | T346 T352 T353 | T5 T6 T27 | T138 T75 T346 | T267 T358 T268 | T177 T128 T359 | T121 T225 T145 | T225 T145 T344 | T121 T225 T145 | T347 T348 T344 | T128 T344 T186 | T128 T186 T187 | T160 T128 T144 | T344 T360 T361 | T344 T354 T355 | T344 T354 T355 | T344 T354 T355 | T344 T360 T361 | T344 T360 T361
91 188/255 ==> assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
Tests: T2 T5 T6 | T2 T14 T31 | T5 T6 T121 | T31 T28 T29 | T2 T14 T28 | T5 T6 T121 | T31 T29 T131 | T28 T29 T72 | T14 T28 T34 | T2 T35 T34 | T5 T6 T27 | T121 T225 T145 | T131 T32 T346 | T31 T29 T32 | T28 T29 T72 | T28 T344 T51 | T14 T28 T11 | T34 T68 T344 | T34 T71 T344 | T2 T35 T89 | T53 T346 T189 | T5 T6 T27 | T121 T225 T145 | T344 T360 T361 | T131 T346 T351 | T131 T32 T346 | T31 T32 T37 | T31 T29 T37 | T28 T29 T72 | T28 T344 T51 | T28 T344 T51 | T28 T344 T51 | T28 T11 T128 | T14 T68 T128 | T68 T344 T69 | T34 T344 T70 | T34 T344 T70 | T71 T344 T308 | T35 T71 T344 | T2 T89 T188 | T53 T346 T189 | T346 T352 T353 | T346 T352 T353 | T5 T6 T27 | T121 T225 T145 | T160 T128 T344 | T344 T360 T361 | T344 T354 T355 | T131 T346 T351 | T346 T352 T353 | T131 T32 T346 | T32 T346 T132 | T31 T32 T37 | T31 T37 T346 | T31 T37 T346 | T29 T72 T73 | T346 T352 T353 | T28 T344 T51 | T28 T344 T51 | T28 T344 T51 | T28 T344 T51 | T28 T344 T51 | T28 T344 T51 | T28 T344 T51 | T28 T344 T51 | T11 T128 T226 | T14 T128 T58 | T68 T344 T69 | T344 T354 T355 | T68 T344 T69 | T344 T354 T355 | T34 T344 T70 | T344 T354 T355 | T34 T344 T70 | T71 T344 T308 | T344 T354 T355 | T344 T354 T355 | T344 T354 T355 | T2 T128 T344 | T89 T188 T295 | T53 T189 T128 | T346 T128 T186 | T346 T352 T353 | T346 T352 T353 | T346 T352 T353 | T346 T352 T353 | T5 T6 T27 | T267 T268 T375 | T121 T225 T145 | T347 T348 T344 | T128 T186 T187 | T128 T344 T360 | T344 T354 T355 | T344 T360 T361 | T344 T354 T355 | T131 T346 T350 | T131 T346 T351 | T346 T352 T353 | T346 T352 T353 | T131 T346 T350 | T32 T346 T132 | T32 T346 T132 | T346 T352 T353 | T346 T352 T353 | T31 T37 T346 | T31 T37 T346 | T346 T352 T353 | T346 T352 T353 | T31 T37 T346 | T29 T72 T73 | T29 T72 T73 | T346 T352 T353 | T346 T352 T353 | T28 T344 T51 | T28 T344 T51 | T28 T344 T51 | T28 T344 T51 | T28 T344 T51 | T28 T344 T51 | T28 T344 T51 | T28 T344 T51 | T28 T344 T51 | T28 T344 T51 | T28 T344 T51 | T28 T344 T51 | T28 T344 T51 | T28 T344 T51 | T28 T344 T51 | T28 T344 T51 | T11 T128 T226 | T128 T186 T187 | T128 T186 T187 | T128 T186 T187 | T68 T344 T69 | T344 T354 T355 | T344 T354 T355 | T344 T354 T355 | T344 T354 T355 | T344 T354 T355 | T344 T354 T355 | T344 T354 T355 | T34 T344 T70 | T344 T354 T355 | T344 T354 T355 | T344 T354 T355 | T34 T344 T70 | T344 T354 T355 | T344 T354 T355 | T71 T344 T308 | T344 T354 T355 | T344 T354 T355 | T344 T354 T355 | T344 T354 T355 | T344 T354 T355 | T344 T354 T355 | T344 T354 T355 | T2 T128 T135 | T128 T186 T187 | T89 T188 T295 | T53 T344 T301 | T128 T186 T187 | T128 T186 T187 | T346 T352 T353 | T346 T352 T353 | T346 T352 T353 | T346 T352 T353 | T346 T352 T353 | T346 T352 T353 | T346 T352 T353 | T346 T352 T353 | T346 T352 T353 | T5 T6 T27 | T138 T344 T139 | T267 T268 T375 | T128 T186 T187 | T121 T225 T145 | T225 T145 T344 | T344 T354 T355 | T344 T354 T355 | T128 T186 T187 | T128 T186 T187 | T128 T186 T187 | T344 T360 T361 | T344 T354 T355 | T344 T354 T355 | T344 T354 T355 | T344 T354 T355 | T344 T354 T355
92 188/255 ==> assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
Tests: T2 T5 T6 | T2 T14 T31 | T5 T6 T121 | T31 T28 T29 | T2 T14 T28 | T5 T6 T121 | T31 T29 T131 | T28 T29 T72 | T14 T28 T34 | T2 T35 T34 | T5 T6 T27 | T121 T225 T145 | T131 T32 T346 | T31 T29 T32 | T28 T29 T72 | T28 T346 T283 | T14 T28 T11 | T34 T68 T346 | T34 T71 T346 | T2 T35 T89 | T53 T88 T89 | T5 T6 T27 | T121 T225 T145 | T346 T283 T128 | T131 T346 T283 | T131 T32 T346 | T31 T32 T37 | T31 T29 T37 | T28 T29 T72 | T28 T346 T283 | T28 T346 T283 | T28 T346 T283 | T28 T11 T346 | T14 T11 T68 | T68 T346 T283 | T34 T346 T283 | T34 T346 T283 | T71 T346 T283 | T35 T71 T346 | T2 T35 T89 | T11 T53 T88 | T346 T283 T128 | T346 T283 T128 | T5 T6 T27 | T121 T225 T145 | T160 T346 T283 | T346 T283 T128 | T346 T283 T128 | T131 T346 T283 | T131 T346 T283 | T131 T32 T346 | T32 T346 T283 | T31 T32 T37 | T31 T37 T346 | T31 T37 T346 | T29 T72 T73 | T29 T72 T73 | T28 T29 T72 | T28 T346 T283 | T28 T346 T283 | T28 T346 T283 | T28 T346 T283 | T28 T346 T283 | T28 T346 T283 | T28 T346 T283 | T14 T28 T11 | T14 T11 T12 | T68 T346 T283 | T68 T346 T283 | T68 T346 T283 | T346 T283 T128 | T34 T346 T283 | T34 T346 T283 | T34 T346 T283 | T71 T346 T283 | T71 T346 T283 | T71 T346 T283 | T35 T71 T346 | T2 T35 T346 | T89 T188 T295 | T53 T88 T89 | T11 T12 T346 | T346 T283 T128 | T346 T283 T128 | T346 T283 T128 | T346 T283 T128 | T5 T6 T27 | T267 T53 T88 | T121 T225 T145 | T121 T225 T145 | T346 T283 T128 | T160 T346 T283 | T346 T283 T128 | T346 T283 T128 | T346 T283 T128 | T131 T346 T283 | T131 T346 T283 | T131 T346 T283 | T131 T346 T283 | T131 T346 T283 | T32 T346 T283 | T32 T346 T283 | T32 T346 T283 | T32 T346 T283 | T31 T32 T37 | T31 T37 T346 | T31 T37 T346 | T31 T37 T346 | T31 T37 T346 | T29 T72 T73 | T29 T72 T73 | T29 T72 T73 | T29 T72 T73 | T28 T29 T72 | T28 T346 T283 | T28 T346 T283 | T28 T346 T283 | T28 T346 T283 | T28 T346 T283 | T28 T346 T283 | T28 T346 T283 | T28 T346 T283 | T28 T346 T283 | T28 T346 T283 | T28 T346 T283 | T28 T346 T283 | T28 T346 T283 | T28 T346 T283 | T28 T346 T283 | T14 T28 T11 | T14 T346 T283 | T14 T11 T12 | T14 T346 T283 | T68 T346 T283 | T68 T346 T283 | T68 T346 T283 | T68 T346 T283 | T68 T346 T283 | T68 T346 T283 | T346 T283 T128 | T346 T283 T128 | T34 T346 T283 | T34 T346 T283 | T34 T346 T283 | T34 T346 T283 | T34 T346 T283 | T346 T283 T128 | T346 T283 T128 | T71 T346 T283 | T71 T346 T283 | T71 T346 T283 | T71 T346 T283 | T71 T346 T283 | T35 T71 T346 | T35 T346 T283 | T35 T346 T283 | T2 T346 T283 | T346 T283 T128 | T53 T88 T89 | T53 T88 T89 | T11 T53 T88 | T11 T12 T346 | T346 T283 T128 | T346 T283 T128 | T346 T283 T128 | T346 T283 T128 | T346 T283 T128 | T346 T283 T128 | T346 T283 T128 | T346 T283 T128 | T346 T283 T128 | T5 T6 T27 | T138 T75 T346 | T267 T53 T88 | T177 T346 T283 | T121 T225 T145 | T121 T225 T145 | T121 T225 T145 | T347 T348 T346 | T346 T283 T128 | T346 T283 T128 | T160 T346 T283 | T346 T283 T128 | T346 T283 T128 | T346 T283 T128 | T346 T283 T128 | T346 T283 T128 | T346 T283 T128
93 end
94 end : gen_level
95 end : gen_tree
96
97
98 // The results can be found at the tree root
99 1/1 assign max_valid_o = vld_tree[0];
Tests: T2 T5 T6
100 1/1 assign max_idx_o = idx_tree[0];
Tests: T2 T5 T6
101 1/1 assign max_value_o = max_tree[0];
Tests: T2 T5 T6
102
103 ////////////////
104 // Assertions //
105 ////////////////
106
107 `ifdef INC_ASSERT
108 //VCS coverage off
109 // pragma coverage off
110
111 // Helper functions for assertions below.
112 function automatic logic [Width-1:0] max_value (input logic [NumSrc-1:0][Width-1:0] values_i,
113 input logic [NumSrc-1:0] valid_i);
114 unreachable logic [Width-1:0] value = '0;
115 unreachable for (int k = 0; k < NumSrc; k++) begin
116 unreachable if (valid_i[k] && values_i[k] > value) begin
117 unreachable value = values_i[k];
118 end
==> MISSING_ELSE
119 end
120 unreachable return value;
121 endfunction : max_value
122
123 function automatic logic [SrcWidth-1:0] max_idx (input logic [NumSrc-1:0][Width-1:0] values_i,
124 input logic [NumSrc-1:0] valid_i);
125 unreachable logic [Width-1:0] value = '0;
126 unreachable logic [SrcWidth-1:0] idx = '0;
127 unreachable for (int k = NumSrc-1; k >= 0; k--) begin
128 unreachable if (valid_i[k] && values_i[k] >= value) begin
129 unreachable value = values_i[k];
130 unreachable idx = k;
131 end
==> MISSING_ELSE
132 end
133 unreachable return idx;
134 endfunction : max_idx
135
136 logic [Width-1:0] max_value_exp;
137 logic [SrcWidth-1:0] max_idx_exp;
138 unreachable assign max_value_exp = max_value(values_i, valid_i);
139 unreachable assign max_idx_exp = max_idx(values_i, valid_i);