Unified Coverage Report :: Module :: prim_max_tree

Module : prim_max_tree

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
91.53	89.27	76.85			100.00	100.00

Source File(s) :
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/default/sim-vcs/../src/lowrisc_prim_max_tree_0/rtl/prim_max_tree.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.top_earlgrey.u_rv_plic.gen_target[0].u_target.u_prim_max_tree	91.53	89.27	76.85			100.00	100.00

Line Coverage for Module : prim_max_tree

	Line No.	Total	Covered	Percent
TOTAL		1258	1123	89.27
CONT_ASSIGN	72	1	0	0.00
CONT_ASSIGN	72	1	1	100.00
CONT_ASSIGN	72	1	1	100.00
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CONT_ASSIGN	92	1	0	0.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ROUTINE	114	0	0
ROUTINE	125	0	0
CONT_ASSIGN	138	0	0
CONT_ASSIGN	139	0	0

Click here to see the source line report.

---

Cond Coverage for Module : prim_max_tree

	Total	Covered	Percent
Conditions	3313	2546	76.85
Logical	3313	2546	76.85
Non-Logical	0	0
Event	0	0

This module contains a very large number of conditions, so the report has been split into multiple pages, by source line number. Click on the line number range in the table below to see the condition coverage for that section of the module.

Line numbers	Percent
85	63.78
85	63.17
85	61.58
85	56.82
85	57.42
85-90	100.00
90	100.00
90-91	100.00
91-92	100.00
92	100.00
92	100.00

---

Branch Coverage for Module : prim_max_tree

	Line No.	Total	Covered	Percent
Branches		1320	1320	100.00
TERNARY	90	2	2	100.00
TERNARY	91	2	2	100.00
TERNARY	92	2	2	100.00
TERNARY	90	2	2	100.00
TERNARY	91	2	2	100.00
TERNARY	92	2	2	100.00
TERNARY	90	1	1	100.00
TERNARY	91	1	1	100.00
TERNARY	92	1	1	100.00
TERNARY	90	2	2	100.00
TERNARY	91	2	2	100.00
TERNARY	92	2	2	100.00
TERNARY	90	2	2	100.00
TERNARY	91	2	2	100.00
TERNARY	92	2	2	100.00
TERNARY	90	2	2	100.00
TERNARY	91	2	2	100.00
TERNARY	92	2	2	100.00
TERNARY	90	1	1	100.00
TERNARY	91	1	1	100.00
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TERNARY	90	2	2	100.00
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TERNARY	90	2	2	100.00
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TERNARY	90	2	2	100.00
TERNARY	91	2	2	100.00
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TERNARY	90	2	2	100.00
TERNARY	91	2	2	100.00
TERNARY	92	2	2	100.00
TERNARY	90	2	2	100.00
TERNARY	91	2	2	100.00
TERNARY	92	2	2	100.00
TERNARY	90	1	1	100.00
TERNARY	91	1	1	100.00
TERNARY	92	1	1	100.00
TERNARY	90	1	1	100.00
TERNARY	91	1	1	100.00
TERNARY	92	1	1	100.00
TERNARY	90	2	2	100.00
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TERNARY	92	2	2	100.00
TERNARY	90	2	2	100.00
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TERNARY	92	2	2	100.00
TERNARY	90	2	2	100.00
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TERNARY	90	2	2	100.00
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TERNARY	90	2	2	100.00
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TERNARY	90	2	2	100.00
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TERNARY	90	1	1	100.00
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TERNARY	92	1	1	100.00
TERNARY	90	1	1	100.00
TERNARY	91	1	1	100.00
TERNARY	92	1	1	100.00
TERNARY	90	1	1	100.00
TERNARY	91	1	1	100.00
TERNARY	92	1	1	100.00
TERNARY	90	2	2	100.00
TERNARY	91	2	2	100.00
TERNARY	92	2	2	100.00
TERNARY	90	2	2	100.00
TERNARY	91	2	2	100.00
TERNARY	92	2	2	100.00
TERNARY	90	2	2	100.00
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TERNARY	90	2	2	100.00
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TERNARY	90	2	2	100.00
TERNARY	91	2	2	100.00
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TERNARY	90	2	2	100.00
TERNARY	91	2	2	100.00
TERNARY	92	2	2	100.00
TERNARY	90	2	2	100.00
TERNARY	91	2	2	100.00
TERNARY	92	2	2	100.00
TERNARY	90	2	2	100.00
TERNARY	91	2	2	100.00
TERNARY	92	2	2	100.00
TERNARY	90	2	2	100.00
TERNARY	91	2	2	100.00
TERNARY	92	2	2	100.00
TERNARY	90	2	2	100.00
TERNARY	91	2	2	100.00
TERNARY	92	2	2	100.00
TERNARY	90	2	2	100.00
TERNARY	91	2	2	100.00
TERNARY	92	2	2	100.00
TERNARY	90	2	2	100.00
TERNARY	91	2	2	100.00
TERNARY	92	2	2	100.00
TERNARY	90	2	2	100.00
TERNARY	91	2	2	100.00
TERNARY	92	2	2	100.00
TERNARY	90	2	2	100.00
TERNARY	91	2	2	100.00
TERNARY	92	2	2	100.00
TERNARY	90	2	2	100.00
TERNARY	91	2	2	100.00
TERNARY	92	2	2	100.00
TERNARY	90	2	2	100.00
TERNARY	91	2	2	100.00
TERNARY	92	2	2	100.00
TERNARY	90	2	2	100.00
TERNARY	91	2	2	100.00
TERNARY	92	2	2	100.00
TERNARY	90	2	2	100.00
TERNARY	91	2	2	100.00
TERNARY	92	2	2	100.00
TERNARY	90	2	2	100.00
TERNARY	91	2	2	100.00
TERNARY	92	2	2	100.00
TERNARY	90	2	2	100.00
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TERNARY	92	1	1	100.00
TERNARY	90	1	1	100.00
TERNARY	91	1	1	100.00
TERNARY	92	1	1	100.00
TERNARY	90	1	1	100.00
TERNARY	91	1	1	100.00
TERNARY	92	1	1	100.00
TERNARY	90	1	1	100.00
TERNARY	91	1	1	100.00
TERNARY	92	1	1	100.00
TERNARY	90	1	1	100.00
TERNARY	91	1	1	100.00
TERNARY	92	1	1	100.00
TERNARY	90	1	1	100.00
TERNARY	91	1	1	100.00
TERNARY	92	1	1	100.00
TERNARY	90	1	1	100.00
TERNARY	91	1	1	100.00
TERNARY	92	1	1	100.00
TERNARY	90	1	1	100.00
TERNARY	91	1	1	100.00
TERNARY	92	1	1	100.00
TERNARY	90	1	1	100.00
TERNARY	91	1	1	100.00
TERNARY	92	1	1	100.00
TERNARY	90	1	1	100.00
TERNARY	91	1	1	100.00
TERNARY	92	1	1	100.00
TERNARY	90	1	1	100.00
TERNARY	91	1	1	100.00
TERNARY	92	1	1	100.00

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T121
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T121
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T121
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T2,T14,T28
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T2,T14,T28
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T2,T14,T28
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T28,T29,T72
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T28,T29,T72
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T28,T29,T72
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T2,T35,T34
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T2,T35,T34
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T2,T35,T34
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T121,T225,T145
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T121,T225,T145
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T121,T225,T145
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T31,T29,T32
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T31,T29,T32
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T31,T29,T32
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T28,T344,T51
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T28,T344,T51
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T28,T344,T51
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T34,T68,T344
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T34,T68,T344
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T34,T68,T344
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T2,T35,T89
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T2,T35,T89
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T2,T35,T89
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T27
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T27
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T27
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T344,T360,T361
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T344,T360,T361
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T344,T360,T361
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T131,T32,T346
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T131,T32,T346
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T131,T32,T346
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T31,T29,T37
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T31,T29,T37
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T31,T29,T37
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T28,T344,T51
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T28,T344,T51
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T28,T344,T51
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T28,T344,T51
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T28,T344,T51
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T28,T344,T51
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T14,T68,T128
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T14,T68,T128
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T14,T68,T128
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T34,T344,T70
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T34,T344,T70
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T34,T344,T70
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T71,T344,T308
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T71,T344,T308
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T71,T344,T308
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T2,T89,T188
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T2,T89,T188
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T2,T89,T188
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T346,T352,T353
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T346,T352,T353
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T346,T352,T353
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T27
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T27
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T27
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T160,T128,T344
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T160,T128,T344
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T160,T128,T344
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T344,T360,T361
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T344,T360,T361
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T344,T360,T361
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T131,T346,T351
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T131,T346,T351
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T131,T346,T351
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T32,T346,T132
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T32,T346,T132
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T32,T346,T132
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T31,T37,T346
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T31,T37,T346
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T31,T37,T346
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T29,T72,T73
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T29,T72,T73
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T29,T72,T73
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T28,T29,T72
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T28,T29,T72
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T28,T29,T72
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T28,T344,T51
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T28,T344,T51
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T28,T344,T51
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T28,T344,T51
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T28,T344,T51
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T28,T344,T51
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T28,T344,T51
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T28,T344,T51
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T28,T344,T51
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T28,T11,T128
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T28,T11,T128
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T28,T11,T128
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T68,T128,T344
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T68,T128,T344
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T68,T128,T344
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T68,T344,T69
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T68,T344,T69
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T68,T344,T69
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T34,T344,T70
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T34,T344,T70
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T34,T344,T70
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T34,T344,T70
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T34,T344,T70
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T34,T344,T70
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T71,T344,T308
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T71,T344,T308
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T71,T344,T308
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T35,T71,T344
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T35,T71,T344
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T35,T71,T344
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T89,T188,T295
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T89,T188,T295
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T89,T188,T295
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T346,T128,T186
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T346,T128,T186
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T346,T128,T186
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T346,T352,T353
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T346,T352,T353
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T346,T352,T353
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T346,T352,T353
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T346,T352,T353
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T346,T352,T353
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T267,T358,T268
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T267,T358,T268
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T267,T358,T268
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T121,T225,T145
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T121,T225,T145
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T121,T225,T145
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T160,T128,T344
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T160,T128,T344
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T160,T128,T344
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T344,T360,T361
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T344,T360,T361
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T344,T360,T361
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T131,T346,T351
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T131,T346,T351
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T131,T346,T351
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T346,T352,T353
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T346,T352,T353
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T346,T352,T353
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T32,T346,T132
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T32,T346,T132
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T32,T346,T132
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T346,T352,T353
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T346,T352,T353
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T346,T352,T353
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T31,T32,T37
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T31,T32,T37
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T31,T32,T37
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T31,T37,T346
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T31,T37,T346
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T31,T37,T346
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T31,T37,T346
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T31,T37,T346
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T31,T37,T346
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T29,T72,T73
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T29,T72,T73
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T29,T72,T73
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T346,T352,T353
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T346,T352,T353
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T346,T352,T353
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T28,T344,T51
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T28,T344,T51
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T28,T344,T51
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T28,T344,T51
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T28,T344,T51
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T28,T344,T51
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T28,T344,T51
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T28,T344,T51
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T28,T344,T51
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T28,T344,T51
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T28,T344,T51
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T28,T344,T51
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T28,T344,T51
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T28,T344,T51
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T28,T344,T51
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T28,T344,T51
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T28,T344,T51
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T28,T344,T51
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T28,T344,T51
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T28,T344,T51
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T28,T344,T51
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T28,T344,T51
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T28,T344,T51
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T28,T344,T51
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T128,T186,T187
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T128,T186,T187
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T128,T186,T187
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T14,T128,T58
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T14,T128,T58
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T14,T128,T58
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T68,T344,T69
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T68,T344,T69
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T68,T344,T69
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T344,T354,T355
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T344,T354,T355
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T344,T354,T355
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T68,T344,T69
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T68,T344,T69
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T68,T344,T69
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T344,T354,T355
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T344,T354,T355
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T344,T354,T355
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T344,T354,T355
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T344,T354,T355
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T344,T354,T355
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T344,T354,T355
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T344,T354,T355
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T344,T354,T355
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T344,T354,T355
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T344,T354,T355
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T344,T354,T355
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T71,T344,T308
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T71,T344,T308
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T71,T344,T308
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T344,T354,T355
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T344,T354,T355
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T344,T354,T355
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T344,T354,T355
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T344,T354,T355
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T344,T354,T355
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T344,T354,T355
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T344,T354,T355
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T344,T354,T355
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T2,T128,T135
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T2,T128,T135
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T2,T128,T135
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T89,T188,T295
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T89,T188,T295
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T89,T188,T295
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T189,T128,T344
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T189,T128,T344
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T189,T128,T344
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T346,T128,T186
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T346,T128,T186
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T346,T128,T186
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T346,T352,T353
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T346,T352,T353
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T346,T352,T353
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T346,T352,T353
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T346,T352,T353
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T346,T352,T353
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T346,T352,T353
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T346,T352,T353
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T346,T352,T353
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T346,T352,T353
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T346,T352,T353
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T346,T352,T353
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T138,T75,T346
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T138,T75,T346
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T138,T75,T346
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T177,T128,T359
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T177,T128,T359
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T177,T128,T359
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T225,T145,T344
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T225,T145,T344
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T225,T145,T344
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T347,T348,T344
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T347,T348,T344
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T347,T348,T344
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T128,T186,T187
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T128,T186,T187
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T128,T186,T187
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T344,T360,T361
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T344,T360,T361
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T344,T360,T361
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T344,T354,T355
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T344,T354,T355
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T344,T354,T355
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T344,T360,T361
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T344,T360,T361
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T344,T360,T361
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T131,T346,T350
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T131,T346,T350
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T131,T346,T350
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T131,T346,T351
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T131,T346,T351
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T131,T346,T351
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T346,T352,T353
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T346,T352,T353
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T346,T352,T353
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T346,T352,T353
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T346,T352,T353
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T346,T352,T353
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T131,T346,T350
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T131,T346,T350
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T131,T346,T350
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T32,T346,T132
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T32,T346,T132
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T32,T346,T132
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T32,T346,T132
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T32,T346,T132
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T32,T346,T132
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T346,T352,T353
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T346,T352,T353
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T346,T352,T353
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T346,T352,T353
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T346,T352,T353
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T346,T352,T353
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T31,T37,T346
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T31,T37,T346
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T31,T37,T346
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T31,T37,T346
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T31,T37,T346
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T31,T37,T346
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T346,T352,T353
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T346,T352,T353
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T346,T352,T353
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T346,T352,T353
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T346,T352,T353
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T346,T352,T353
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T31,T37,T346
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T31,T37,T346
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T31,T37,T346
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T29,T72,T73
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T29,T72,T73
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T29,T72,T73
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T29,T72,T73
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T29,T72,T73
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T29,T72,T73
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T346,T352,T353
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T346,T352,T353
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T346,T352,T353
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T346,T352,T353
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T346,T352,T353
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T346,T352,T353
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T28,T344,T51
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T28,T344,T51
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T28,T344,T51
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T28,T344,T51
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T28,T344,T51
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T28,T344,T51
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T28,T344,T51
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T28,T344,T51
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T28,T344,T51
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T28,T344,T51
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T28,T344,T51
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T28,T344,T51
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T28,T344,T51
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T28,T344,T51
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T28,T344,T51
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T28,T344,T51
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T28,T344,T51
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T28,T344,T51
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T28,T344,T51
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T28,T344,T51
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T28,T344,T51
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T28,T344,T51
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T28,T344,T51
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T28,T344,T51
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T28,T344,T51
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T28,T344,T51
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T28,T344,T51
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T28,T344,T51
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T28,T344,T51
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T28,T344,T51
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T28,T344,T51
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T28,T344,T51
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T28,T344,T51
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T28,T344,T51
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T28,T344,T51
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T28,T344,T51
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T28,T344,T51
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T28,T344,T51
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T28,T344,T51
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T28,T344,T51
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T28,T344,T51
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T28,T344,T51
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T28,T344,T51
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T28,T344,T51
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T28,T344,T51
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T28,T344,T51
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T28,T344,T51
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T28,T344,T51
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T11,T128,T226
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T11,T128,T226
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T11,T128,T226
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T128,T186,T187
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T128,T186,T187
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T128,T186,T187
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T128,T186,T187
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T128,T186,T187
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T128,T186,T187
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T128,T186,T187
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T128,T186,T187
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T128,T186,T187
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T68,T344,T69
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T68,T344,T69
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T68,T344,T69
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T344,T354,T355
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T344,T354,T355
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T344,T354,T355
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T344,T354,T355
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T344,T354,T355
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T344,T354,T355
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T344,T354,T355
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T344,T354,T355
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T344,T354,T355
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T344,T354,T355
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T344,T354,T355
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T344,T354,T355
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T344,T354,T355
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T344,T354,T355
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T344,T354,T355
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T344,T354,T355
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T344,T354,T355
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T344,T354,T355
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T344,T354,T355
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T344,T354,T355
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T344,T354,T355
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T34,T344,T70
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T34,T344,T70
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T34,T344,T70
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T344,T354,T355
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T344,T354,T355
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T344,T354,T355
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T344,T354,T355
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T344,T354,T355
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T344,T354,T355
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T344,T354,T355
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T344,T354,T355
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T344,T354,T355
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T34,T344,T70
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T34,T344,T70
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T34,T344,T70
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T344,T354,T355
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T344,T354,T355
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T344,T354,T355
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T344,T354,T355
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T344,T354,T355
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T344,T354,T355
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T71,T344,T308
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T71,T344,T308
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T71,T344,T308
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T344,T354,T355
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T344,T354,T355
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T344,T354,T355
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T344,T354,T355
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T344,T354,T355
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T344,T354,T355
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T344,T354,T355
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T344,T354,T355
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T344,T354,T355
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T344,T354,T355
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T344,T354,T355
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T344,T354,T355
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T344,T354,T355
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T344,T354,T355
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T344,T354,T355
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T344,T354,T355
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T344,T354,T355
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T344,T354,T355
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T344,T354,T355
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T344,T354,T355
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T344,T354,T355
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T2,T128,T135
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T2,T128,T135
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T2,T128,T135
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T128,T186,T187
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T128,T186,T187
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T128,T186,T187
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T89,T188,T295
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T89,T188,T295
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T89,T188,T295
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T53,T344,T301
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T53,T344,T301
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T53,T344,T301
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T128,T186,T187
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T128,T186,T187
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T128,T186,T187
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T128,T186,T187
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T128,T186,T187
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T128,T186,T187
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T346,T352,T353
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T346,T352,T353
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T346,T352,T353
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T346,T352,T353
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T346,T352,T353
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T346,T352,T353
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T346,T352,T353
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T346,T352,T353
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T346,T352,T353
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T346,T352,T353
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T346,T352,T353
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T346,T352,T353
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T346,T352,T353
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T346,T352,T353
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T346,T352,T353
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T346,T352,T353
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T346,T352,T353
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T346,T352,T353
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T346,T352,T353
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T346,T352,T353
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T346,T352,T353
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T346,T352,T353
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T346,T352,T353
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T346,T352,T353
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T346,T352,T353
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T346,T352,T353
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T346,T352,T353
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T27
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T27
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T27
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T138,T344,T139
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T138,T344,T139
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T138,T344,T139
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T267,T268,T375
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T267,T268,T375
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T267,T268,T375
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T128,T186,T187
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T128,T186,T187
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T128,T186,T187
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T121,T225,T145
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T121,T225,T145
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T121,T225,T145
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T225,T145,T344
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T225,T145,T344
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T225,T145,T344
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T344,T354,T355
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T344,T354,T355
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T344,T354,T355
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T344,T354,T355
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T344,T354,T355
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T344,T354,T355
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T128,T186,T187
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T128,T186,T187
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T128,T186,T187
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T128,T186,T187
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T128,T186,T187
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T128,T186,T187
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T128,T186,T187
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T128,T186,T187
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T128,T186,T187
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T344,T360,T361
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T344,T360,T361
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T344,T360,T361
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T344,T354,T355
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T344,T354,T355
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T344,T354,T355
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T344,T354,T355
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T344,T354,T355
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T344,T354,T355
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T344,T354,T355
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T344,T354,T355
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T344,T354,T355
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T344,T354,T355
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T344,T354,T355
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T344,T354,T355
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T344,T354,T355
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T344,T354,T355
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==>  
                                               ==>  

Branches:

-1-	Status	Tests
1	Covered	T344,T354,T355
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

90                 assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

91                 assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

92                 assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
                                               -1-  
                                               ==> (Unreachable)  
                                               ==>  

Branches:

-1-	Status	Tests
1	Unreachable
0	Covered	T1,T2,T3

---

Assert Coverage for Module : prim_max_tree

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
MaxComputationInvalid_A	508511374	506423937	0	0
MaxComputation_A	508511374	1980350	0	0
MaxIndexComputationInvalid_A	508511374	506423937	0	0
MaxIndexComputation_A	508511374	1980350	0	0
NumSources_A	1021	1021	0	0
ValidInImpliesValidOut_A	508511374	508404287	0	0

MaxComputationInvalid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	508511374	506423937	0	0
T1	42233	42175	0	0
T2	86226	85936	0	0
T3	68985	68930	0	0
T4	66703	66645	0	0
T5	73949	73693	0	0
T6	82300	80166	0	0
T7	112437	112382	0	0
T38	80087	80036	0	0
T39	70682	70624	0	0
T106	70868	70813	0	0

MaxComputation_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	508511374	1980350	0	0
T2	86226	232	0	0
T3	68985	0	0	0
T4	66703	0	0	0
T5	73949	205	0	0
T6	82300	2079	0	0
T7	112437	0	0	0
T8	147842	0	0	0
T14	0	8100	0	0
T27	0	560	0	0
T28	0	5404	0	0
T29	0	1213	0	0
T31	0	1201	0	0
T38	80087	0	0	0
T39	70682	0	0	0
T106	70868	0	0	0
T121	0	1554	0	0
T267	0	201	0	0

MaxIndexComputationInvalid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	508511374	506423937	0	0
T1	42233	42175	0	0
T2	86226	85936	0	0
T3	68985	68930	0	0
T4	66703	66645	0	0
T5	73949	73693	0	0
T6	82300	80166	0	0
T7	112437	112382	0	0
T38	80087	80036	0	0
T39	70682	70624	0	0
T106	70868	70813	0	0

MaxIndexComputation_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	508511374	1980350	0	0
T2	86226	232	0	0
T3	68985	0	0	0
T4	66703	0	0	0
T5	73949	205	0	0
T6	82300	2079	0	0
T7	112437	0	0	0
T8	147842	0	0	0
T14	0	8100	0	0
T27	0	560	0	0
T28	0	5404	0	0
T29	0	1213	0	0
T31	0	1201	0	0
T38	80087	0	0	0
T39	70682	0	0	0
T106	70868	0	0	0
T121	0	1554	0	0
T267	0	201	0	0

NumSources_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1021	1021	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T38	1	1	0	0
T39	1	1	0	0
T106	1	1	0	0

ValidInImpliesValidOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	508511374	508404287	0	0
T1	42233	42175	0	0
T2	86226	86168	0	0
T3	68985	68930	0	0
T4	66703	66645	0	0
T5	73949	73898	0	0
T6	82300	82245	0	0
T7	112437	112382	0	0
T38	80087	80036	0	0
T39	70682	70624	0	0
T106	70868	70813	0	0