Go
back
71 if (offset < NumSrc) begin : gen_assign
72 185/186 ==> assign vld_tree[Pa] = valid_i[offset];
Tests: T68 T322 T296 | T68 T322 T296 | T68 T322 T328 | T68 T322 T328 | T322 T329 T330 | T322 T329 T330 | T322 T329 T330 | T322 T329 T330 | T68 T322 T296 | T28 T132 T322 | T28 T132 T322 | T28 T132 T322 | T28 T132 T322 | T322 T329 T330 | T322 T329 T330 | T322 T329 T330 | T322 T329 T330 | T28 T132 T322 | T63 T64 T322 | T63 T64 T322 | T63 T64 T322 | T63 T64 T322 | T322 T329 T330 | T322 T329 T330 | T322 T329 T330 | T322 T329 T330 | T63 T64 T322 | T38 T65 T322 | T38 T65 T322 | T38 T65 T322 | T38 T65 T322 | T322 T329 T330 | T322 T329 T330 | T322 T329 T330 | T322 T329 T330 | T38 T65 T322 | T27 T331 T40 | T27 T331 T40 | T27 T331 T40 | T27 T331 T40 | T27 T331 T40 | T27 T331 T40 | T27 T331 T40 | T27 T331 T40 | T27 T331 T40 | T27 T331 T40 | T27 T331 T40 | T27 T331 T40 | T27 T331 T40 | T27 T331 T40 | T27 T331 T40 | T27 T331 T40 | T27 T331 T40 | T27 T331 T40 | T27 T331 T40 | T27 T331 T40 | T27 T331 T40 | T27 T331 T40 | T27 T331 T40 | T27 T331 T40 | T27 T331 T40 | T27 T331 T40 | T27 T331 T40 | T27 T331 T40 | T27 T331 T40 | T27 T331 T40 | T27 T331 T40 | T27 T331 T40 | T8 T127 T232 | T127 T190 T191 | T127 T190 T191 | T127 T190 T191 | T127 T190 T191 | T11 T127 T49 | T127 T190 T191 | T127 T190 T191 | T58 T331 T129 | T58 T331 T129 | T331 T332 T333 | T331 T332 T333 | T331 T332 T333 | T331 T332 T333 | T331 T332 T333 | T331 T332 T333 | T331 T332 T333 | T58 T331 T129 | T331 T332 T333 | T331 T332 T333 | T331 T332 T333 | T331 T332 T333 | T331 T332 T333 | T60 T331 T140 | T60 T331 T140 | T331 T332 T333 | T331 T332 T333 | T331 T332 T333 | T331 T332 T333 | T331 T332 T333 | T331 T332 T333 | T331 T332 T333 | T59 T60 T331 | T331 T332 T333 | T331 T332 T333 | T331 T332 T333 | T331 T332 T333 | T331 T332 T333 | T61 T331 T141 | T61 T331 T141 | T331 T332 T333 | T331 T332 T333 | T331 T332 T333 | T331 T332 T333 | T331 T332 T333 | T331 T332 T333 | T331 T332 T333 | T61 T331 T62 | T331 T332 T333 | T331 T332 T333 | T331 T332 T333 | T331 T332 T333 | T331 T332 T333 | T2 T127 T136 | T2 T127 T190 | T127 T190 T191 | T127 T190 T191 | T127 T190 T191 | T229 T335 T192 | T83 T336 T192 | T331 T337 T338 | T43 T81 T192 | T127 T190 T191 | T127 T190 T191 | T127 T190 T191 | T127 T190 T191 | T322 T329 T330 | T322 T329 T330 | T322 T329 T330 | T322 T329 T330 | T322 T329 T330 | T322 T329 T330 | T322 T329 T330 | T322 T329 T330 | T322 T329 T330 | T322 T329 T330 | T322 T329 T330 | T322 T329 T330 | T322 T329 T330 | T322 T329 T330 | T322 T329 T330 | T322 T329 T330 | T322 T329 T330 | T322 T329 T330 | T5 T23 T26 | T67 T322 T240 | T142 T143 T331 | T287 T265 T351 | T264 T265 T192 | T179 T127 T339 | T127 T190 T191 | T3 T231 T148 | T3 T231 T148 | T231 T148 T331 | T231 T148 T331 | T3 T231 T148 | T331 T332 T333 | T326 T327 T331 | T331 T332 T333 | T331 T332 T333 | T127 T190 T191 | T127 T190 T191 | T127 T190 T191 | T162 T127 T185 | T127 T190 T191 | T331 T332 T333 | T331 T340 T332 | T331 T332 T333 | T331 T332 T333 | T331 T332 T333 | T331 T332 T333 | T331 T332 T333 | T331 T332 T333 | T331 T340 T332 | T331 T332 T333 | T331 T340 T332 | T331 T332 T333
73 assign idx_tree[Pa] = offset;
74 186/186 assign max_tree[Pa] = values_i[offset];
Tests: T281 T282 T98 | T68 T281 T127 | T68 T281 T127 | T68 T281 T127 | T68 T281 T127 | T68 T281 T127 | T68 T281 T127 | T68 T281 T127 | T68 T281 T127 | T68 T281 T127 | T28 T132 T281 | T28 T132 T281 | T28 T132 T281 | T28 T132 T281 | T28 T132 T281 | T28 T132 T281 | T28 T132 T281 | T28 T132 T281 | T28 T132 T281 | T63 T64 T281 | T63 T64 T281 | T63 T64 T281 | T63 T64 T281 | T63 T64 T281 | T63 T64 T281 | T63 T64 T281 | T63 T64 T281 | T63 T64 T281 | T38 T65 T281 | T38 T65 T281 | T38 T65 T281 | T38 T65 T281 | T38 T65 T281 | T38 T65 T281 | T38 T65 T281 | T38 T65 T281 | T38 T65 T281 | T27 T281 T127 | T27 T281 T127 | T27 T281 T127 | T27 T281 T127 | T27 T281 T127 | T27 T281 T127 | T27 T281 T127 | T27 T281 T127 | T27 T281 T127 | T27 T281 T127 | T27 T281 T127 | T27 T281 T127 | T27 T281 T127 | T27 T281 T127 | T27 T281 T127 | T27 T281 T127 | T27 T281 T127 | T27 T281 T127 | T27 T281 T127 | T27 T281 T127 | T27 T281 T127 | T27 T281 T127 | T27 T281 T127 | T27 T281 T127 | T27 T281 T127 | T27 T281 T127 | T27 T281 T127 | T27 T281 T127 | T27 T281 T127 | T27 T281 T127 | T27 T281 T127 | T27 T281 T127 | T11 T27 T8 | T11 T281 T127 | T11 T281 T127 | T11 T8 T9 | T11 T8 T9 | T11 T281 T127 | T281 T127 T322 | T281 T127 T322 | T58 T281 T127 | T58 T281 T127 | T281 T127 T322 | T58 T281 T127 | T58 T281 T127 | T58 T281 T127 | T58 T281 T127 | T58 T281 T127 | T281 T127 T322 | T58 T281 T127 | T281 T127 T322 | T281 T127 T322 | T281 T127 T322 | T281 T127 T322 | T281 T127 T322 | T60 T281 T127 | T60 T281 T127 | T281 T127 T322 | T60 T281 T127 | T60 T281 T127 | T60 T281 T127 | T60 T281 T127 | T60 T281 T127 | T281 T127 T322 | T59 T60 T281 | T59 T281 T127 | T281 T127 T322 | T59 T281 T127 | T59 T281 T127 | T59 T281 T127 | T61 T281 T127 | T61 T281 T127 | T281 T127 T322 | T61 T281 T127 | T61 T281 T127 | T61 T281 T127 | T61 T281 T127 | T61 T281 T127 | T281 T127 T322 | T61 T281 T127 | T281 T127 T322 | T281 T127 T322 | T281 T127 T322 | T281 T127 T322 | T281 T127 T322 | T2 T281 T127 | T2 T281 T127 | T281 T127 T322 | T281 T127 T322 | T281 T127 T322 | T43 T81 T83 | T43 T81 T83 | T43 T81 T83 | T43 T81 T83 | T8 T9 T281 | T8 T9 T281 | T281 T127 T322 | T281 T127 T322 | T281 T127 T322 | T281 T127 T322 | T281 T127 T322 | T281 T127 T322 | T281 T127 T322 | T281 T127 T322 | T281 T127 T322 | T281 T127 T322 | T281 T127 T322 | T281 T127 T322 | T281 T127 T322 | T281 T127 T322 | T281 T127 T322 | T281 T127 T322 | T281 T127 T322 | T281 T127 T322 | T281 T127 T322 | T281 T127 T322 | T5 T23 T26 | T67 T281 T127 | T142 T281 T127 | T43 T81 T83 | T264 T43 T81 | T179 T281 T127 | T281 T127 T322 | T3 T231 T148 | T3 T231 T148 | T3 T231 T148 | T3 T231 T148 | T3 T231 T148 | T281 T127 T322 | T326 T327 T281 | T326 T327 T281 | T281 T127 T322 | T281 T127 T322 | T281 T127 T322 | T281 T127 T322 | T162 T281 T127 | T281 T127 T322 | T281 T127 T322 | T281 T127 T322 | T281 T127 T322 | T281 T127 T322 | T281 T127 T322 | T281 T127 T322 | T281 T127 T322 | T281 T127 T322 | T281 T127 T322 | T281 T127 T322 | T281 T127 T322 | T281 T127 T322
75 end else begin : gen_tie_off
76 assign vld_tree[Pa] = '0;
77 assign idx_tree[Pa] = '0;
78 assign max_tree[Pa] = '0;
79 end
80 // This creates the node assignments.
81 end else begin : gen_nodes
82 logic sel; // Local helper variable
83 // In case only one of the parents is valid, forward that one
84 // In case both parents are valid, forward the one with higher value
85 185/185(70 unreachable) assign sel = (~vld_tree[C0] & vld_tree[C1]) |
Tests: T2 T3 T5 | T2 T68 T11 | T68 T28 T27 | T2 T11 T27 | T3 T5 T23 | T68 T28 T132 | T27 T38 T65 | T11 T27 T8 | T2 T59 T60 | T5 T23 T264 | T3 T231 T148 | T68 T28 T132 | T28 T132 T38 | T27 T38 T65 | T27 T281 T127 | T11 T27 T8 | T60 T58 T281 | T59 T60 T61 | T2 T61 T229 | T43 T81 T83 | T5 T23 T264 | T3 T231 T148 | T281 T127 T322 | T68 T281 T127 | T68 T28 T132 | T28 T132 T63 | T38 T63 T65 | T27 T38 T65 | T27 T281 T127 | T27 T281 T127 | T27 T281 T127 | T27 T8 T281 | T11 T8 T58 | T58 T281 T127 | T60 T281 T127 | T59 T60 T281 | T59 T61 T281 | T61 T281 T127 | T2 T229 T335 | T8 T43 T81 | T281 T127 T322 | T281 T127 T322 | T5 T23 T264 | T3 T231 T148 | T162 T281 T127 | T281 T127 T322 | T68 T281 T127 | T68 T281 T127 | T68 T28 T132 | T28 T132 T281 | T28 T132 T63 | T63 T64 T281 | T63 T64 T281 | T38 T65 T281 | T38 T65 T281 | T27 T38 T65 | T27 T281 T127 | T27 T281 T127 | T27 T281 T127 | T27 T281 T127 | T27 T281 T127 | T27 T281 T127 | T27 T281 T127 | T11 T27 T8 | T11 T8 T9 | T58 T281 T127 | T58 T281 T127 | T58 T281 T127 | T281 T127 T322 | T60 T281 T127 | T60 T281 T127 | T59 T60 T281 | T59 T61 T281 | T61 T281 T127 | T61 T281 T127 | T61 T281 T127 | T2 T281 T127 | T229 T335 T192 | T43 T81 T83 | T8 T9 T281 | T281 T127 T322 | T281 T127 T322 | T281 T127 T322 | T281 T127 T322 | T5 T23 T26 | T264 T43 T81 | T3 T231 T148 | T3 T231 T148 | T281 T127 T322 | T162 T281 T127 | T281 T127 T322 | T281 T127 T322 | T68 T281 T127 | T68 T281 T127 | T68 T281 T127 | T68 T281 T127 | T68 T281 T127 | T28 T132 T281 | T28 T132 T281 | T28 T132 T281 | T28 T132 T281 | T28 T132 T63 | T63 T64 T281 | T63 T64 T281 | T63 T64 T281 | T63 T64 T281 | T38 T65 T281 | T38 T65 T281 | T38 T65 T281 | T38 T65 T281 | T27 T38 T65 | T27 T281 T127 | T27 T281 T127 | T27 T281 T127 | T27 T281 T127 | T27 T281 T127 | T27 T281 T127 | T27 T281 T127 | T27 T281 T127 | T27 T281 T127 | T27 T281 T127 | T27 T281 T127 | T27 T281 T127 | T27 T281 T127 | T27 T281 T127 | T27 T281 T127 | T11 T27 T8 | T11 T281 T127 | T11 T8 T9 | T11 T281 T127 | T58 T281 T127 | T58 T281 T127 | T58 T281 T127 | T58 T281 T127 | T58 T281 T127 | T58 T281 T127 | T281 T127 T322 | T281 T127 T322 | T60 T281 T127 | T60 T281 T127 | T60 T281 T127 | T60 T281 T127 | T59 T60 T281 | T59 T281 T127 | T59 T281 T127 | T59 T61 T281 | T61 T281 T127 | T61 T281 T127 | T61 T281 T127 | T61 T281 T127 | T61 T281 T127 | T281 T127 T322 | T281 T127 T322 | T2 T281 T127 | T281 T127 T322 | T43 T81 T83 | T43 T81 T83 | T8 T43 T81 | T8 T9 T281 | T281 T127 T322 | T281 T127 T322 | T281 T127 T322 | T281 T127 T322 | T281 T127 T322 | T281 T127 T322 | T281 T127 T322 | T281 T127 T322 | T281 T127 T322 | T5 T23 T26 | T142 T67 T281 | T264 T43 T81 | T179 T281 T127 | T3 T231 T148 | T3 T231 T148 | T3 T231 T148 | T326 T327 T281 | T281 T127 T322 | T281 T127 T322 | T162 T281 T127 | T281 T127 T322 | T281 T127 T322 | T281 T127 T322 | T281 T127 T322 | T281 T127 T322 | T281 T127 T322
86 (vld_tree[C0] & vld_tree[C1] & logic'(max_tree[C1] > max_tree[C0]));
87 // Forwarding muxes
88 // Note: these ternaries have triggered a synthesis bug in Vivado versions older
89 // than 2020.2. If the problem resurfaces again, have a look at issue #1408.
90 188/188(67 unreachable) assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0];
Tests: T2 T3 T5 | T2 T68 T11 | T3 T5 T23 | T68 T28 T27 | T2 T11 T27 | T3 T5 T23 | T68 T28 T132 | T27 T38 T65 | T11 T27 T8 | T2 T59 T60 | T5 T23 T264 | T3 T231 T148 | T68 T28 T132 | T28 T132 T38 | T27 T38 T65 | T27 T331 T40 | T11 T27 T8 | T60 T58 T331 | T59 T60 T61 | T2 T61 T229 | T43 T81 T83 | T5 T23 T264 | T3 T231 T148 | T331 T340 T332 | T68 T322 T328 | T68 T28 T132 | T28 T132 T63 | T38 T63 T65 | T27 T38 T65 | T27 T331 T40 | T27 T331 T40 | T27 T331 T40 | T27 T8 T127 | T11 T58 T127 | T58 T331 T129 | T60 T331 T140 | T59 T60 T331 | T61 T331 T141 | T61 T331 T62 | T2 T229 T335 | T43 T81 T83 | T322 T329 T330 | T322 T329 T330 | T5 T23 T264 | T3 T231 T148 | T162 T127 T331 | T331 T340 T332 | T331 T340 T332 | T68 T322 T328 | T68 T322 T328 | T68 T28 T132 | T28 T132 T322 | T28 T132 T63 | T63 T64 T322 | T63 T64 T322 | T38 T65 T322 | T322 T329 T330 | T27 T38 T65 | T27 T331 T40 | T27 T331 T40 | T27 T331 T40 | T27 T331 T40 | T27 T331 T40 | T27 T331 T40 | T27 T331 T40 | T27 T8 T127 | T11 T127 T49 | T58 T127 T331 | T331 T332 T333 | T58 T331 T129 | T331 T332 T333 | T60 T331 T140 | T331 T332 T333 | T59 T60 T331 | T61 T331 T141 | T61 T331 T141 | T331 T332 T333 | T61 T331 T62 | T2 T127 T331 | T229 T335 T192 | T43 T81 T83 | T127 T322 T190 | T322 T329 T330 | T322 T329 T330 | T322 T329 T330 | T322 T329 T330 | T5 T23 T26 | T264 T287 T265 | T3 T231 T148 | T3 T231 T148 | T127 T331 T190 | T162 T127 T331 | T331 T332 T333 | T331 T340 T332 | T331 T340 T332 | T68 T322 T296 | T68 T322 T328 | T68 T322 T328 | T322 T329 T330 | T68 T322 T296 | T28 T132 T322 | T28 T132 T322 | T322 T329 T330 | T322 T329 T330 | T28 T132 T63 | T63 T64 T322 | T63 T64 T322 | T322 T329 T330 | T63 T64 T322 | T38 T65 T322 | T38 T65 T322 | T322 T329 T330 | T322 T329 T330 | T27 T38 T65 | T27 T331 T40 | T27 T331 T40 | T27 T331 T40 | T27 T331 T40 | T27 T331 T40 | T27 T331 T40 | T27 T331 T40 | T27 T331 T40 | T27 T331 T40 | T27 T331 T40 | T27 T331 T40 | T27 T331 T40 | T27 T331 T40 | T27 T331 T40 | T27 T331 T40 | T27 T8 T127 | T127 T190 T191 | T127 T190 T191 | T11 T127 T49 | T58 T127 T331 | T58 T331 T129 | T331 T332 T333 | T331 T332 T333 | T331 T332 T333 | T58 T331 T129 | T331 T332 T333 | T331 T332 T333 | T60 T331 T140 | T331 T332 T333 | T331 T332 T333 | T331 T332 T333 | T59 T60 T331 | T331 T332 T333 | T331 T332 T333 | T61 T331 T141 | T61 T331 T141 | T331 T332 T333 | T331 T332 T333 | T331 T332 T333 | T61 T331 T62 | T331 T332 T333 | T331 T332 T333 | T2 T127 T136 | T127 T190 T191 | T229 T335 T192 | T83 T336 T192 | T43 T81 T192 | T127 T190 T191 | T127 T322 T190 | T322 T329 T330 | T322 T329 T330 | T322 T329 T330 | T322 T329 T330 | T322 T329 T330 | T322 T329 T330 | T322 T329 T330 | T322 T329 T330 | T5 T23 T26 | T142 T67 T322 | T264 T287 T265 | T179 T127 T339 | T3 T231 T148 | T231 T148 T331 | T3 T231 T148 | T326 T327 T331 | T127 T331 T190 | T127 T190 T191 | T162 T127 T185 | T331 T340 T332 | T331 T332 T333 | T331 T332 T333 | T331 T332 T333 | T331 T340 T332 | T331 T340 T332
91 188/255 ==> assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0];
Tests: T2 T3 T5 | T2 T68 T11 | T3 T5 T23 | T68 T28 T27 | T2 T11 T27 | T3 T5 T23 | T68 T28 T132 | T27 T38 T65 | T11 T27 T8 | T2 T59 T60 | T5 T23 T264 | T3 T231 T148 | T68 T28 T132 | T28 T132 T38 | T27 T38 T65 | T27 T331 T40 | T11 T27 T8 | T60 T58 T331 | T59 T60 T61 | T2 T61 T229 | T43 T81 T192 | T5 T23 T264 | T3 T231 T148 | T331 T340 T332 | T68 T322 T328 | T68 T28 T132 | T28 T132 T63 | T38 T63 T65 | T27 T38 T65 | T27 T331 T40 | T27 T331 T40 | T27 T331 T40 | T27 T8 T127 | T11 T58 T127 | T58 T331 T129 | T60 T331 T140 | T59 T60 T331 | T61 T331 T141 | T61 T331 T62 | T2 T229 T335 | T43 T81 T192 | T322 T329 T330 | T322 T329 T330 | T5 T23 T264 | T3 T231 T148 | T162 T127 T331 | T331 T340 T332 | T331 T332 T333 | T68 T322 T328 | T322 T329 T330 | T68 T28 T132 | T28 T132 T322 | T28 T132 T63 | T63 T64 T322 | T63 T64 T322 | T38 T65 T322 | T322 T329 T330 | T27 T331 T40 | T27 T331 T40 | T27 T331 T40 | T27 T331 T40 | T27 T331 T40 | T27 T331 T40 | T27 T331 T40 | T27 T331 T40 | T8 T127 T232 | T11 T127 T49 | T58 T331 T129 | T331 T332 T333 | T58 T331 T129 | T331 T332 T333 | T60 T331 T140 | T331 T332 T333 | T59 T60 T331 | T61 T331 T141 | T331 T332 T333 | T331 T332 T333 | T331 T332 T333 | T2 T127 T331 | T229 T335 T192 | T43 T81 T192 | T127 T322 T190 | T322 T329 T330 | T322 T329 T330 | T322 T329 T330 | T322 T329 T330 | T5 T23 T26 | T264 T265 T192 | T3 T231 T148 | T326 T327 T331 | T127 T190 T191 | T127 T331 T340 | T331 T332 T333 | T331 T340 T332 | T331 T332 T333 | T68 T322 T296 | T68 T322 T328 | T322 T329 T330 | T322 T329 T330 | T68 T322 T296 | T28 T132 T322 | T28 T132 T322 | T322 T329 T330 | T322 T329 T330 | T63 T64 T322 | T63 T64 T322 | T322 T329 T330 | T322 T329 T330 | T63 T64 T322 | T38 T65 T322 | T38 T65 T322 | T322 T329 T330 | T322 T329 T330 | T27 T331 T40 | T27 T331 T40 | T27 T331 T40 | T27 T331 T40 | T27 T331 T40 | T27 T331 T40 | T27 T331 T40 | T27 T331 T40 | T27 T331 T40 | T27 T331 T40 | T27 T331 T40 | T27 T331 T40 | T27 T331 T40 | T27 T331 T40 | T27 T331 T40 | T27 T331 T40 | T8 T127 T232 | T127 T190 T191 | T127 T190 T191 | T127 T190 T191 | T58 T331 T129 | T331 T332 T333 | T331 T332 T333 | T331 T332 T333 | T331 T332 T333 | T331 T332 T333 | T331 T332 T333 | T331 T332 T333 | T60 T331 T140 | T331 T332 T333 | T331 T332 T333 | T331 T332 T333 | T59 T60 T331 | T331 T332 T333 | T331 T332 T333 | T61 T331 T141 | T331 T332 T333 | T331 T332 T333 | T331 T332 T333 | T331 T332 T333 | T331 T332 T333 | T331 T332 T333 | T331 T332 T333 | T2 T127 T190 | T127 T190 T191 | T229 T335 T192 | T331 T337 T338 | T127 T190 T191 | T127 T190 T191 | T322 T329 T330 | T322 T329 T330 | T322 T329 T330 | T322 T329 T330 | T322 T329 T330 | T322 T329 T330 | T322 T329 T330 | T322 T329 T330 | T322 T329 T330 | T5 T23 T26 | T142 T143 T331 | T264 T265 T192 | T127 T190 T191 | T3 T231 T148 | T231 T148 T331 | T331 T332 T333 | T331 T332 T333 | T127 T190 T191 | T127 T190 T191 | T127 T190 T191 | T331 T340 T332 | T331 T332 T333 | T331 T332 T333 | T331 T332 T333 | T331 T332 T333 | T331 T332 T333
92 188/255 ==> assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0];
Tests: T2 T3 T5 | T2 T68 T11 | T3 T5 T23 | T68 T28 T27 | T2 T11 T27 | T3 T5 T23 | T68 T28 T132 | T27 T38 T65 | T11 T27 T8 | T2 T59 T60 | T5 T23 T264 | T3 T231 T148 | T68 T28 T132 | T28 T132 T38 | T27 T38 T65 | T27 T281 T127 | T11 T27 T8 | T60 T58 T281 | T59 T60 T61 | T2 T61 T229 | T43 T81 T83 | T5 T23 T264 | T3 T231 T148 | T281 T127 T322 | T68 T281 T127 | T68 T28 T132 | T28 T132 T63 | T38 T63 T65 | T27 T38 T65 | T27 T281 T127 | T27 T281 T127 | T27 T281 T127 | T27 T8 T281 | T11 T8 T58 | T58 T281 T127 | T60 T281 T127 | T59 T60 T281 | T59 T61 T281 | T61 T281 T127 | T2 T229 T335 | T8 T43 T81 | T281 T127 T322 | T281 T127 T322 | T5 T23 T264 | T3 T231 T148 | T162 T281 T127 | T281 T127 T322 | T281 T127 T322 | T68 T281 T127 | T68 T281 T127 | T68 T28 T132 | T28 T132 T281 | T28 T132 T63 | T63 T64 T281 | T63 T64 T281 | T38 T65 T281 | T38 T65 T281 | T27 T38 T65 | T27 T281 T127 | T27 T281 T127 | T27 T281 T127 | T27 T281 T127 | T27 T281 T127 | T27 T281 T127 | T27 T281 T127 | T11 T27 T8 | T11 T8 T9 | T58 T281 T127 | T58 T281 T127 | T58 T281 T127 | T281 T127 T322 | T60 T281 T127 | T60 T281 T127 | T59 T60 T281 | T59 T61 T281 | T61 T281 T127 | T61 T281 T127 | T61 T281 T127 | T2 T281 T127 | T229 T335 T192 | T43 T81 T83 | T8 T9 T281 | T281 T127 T322 | T281 T127 T322 | T281 T127 T322 | T281 T127 T322 | T5 T23 T26 | T264 T43 T81 | T3 T231 T148 | T3 T231 T148 | T281 T127 T322 | T162 T281 T127 | T281 T127 T322 | T281 T127 T322 | T281 T127 T322 | T68 T281 T127 | T68 T281 T127 | T68 T281 T127 | T68 T281 T127 | T68 T281 T127 | T28 T132 T281 | T28 T132 T281 | T28 T132 T281 | T28 T132 T281 | T28 T132 T63 | T63 T64 T281 | T63 T64 T281 | T63 T64 T281 | T63 T64 T281 | T38 T65 T281 | T38 T65 T281 | T38 T65 T281 | T38 T65 T281 | T27 T38 T65 | T27 T281 T127 | T27 T281 T127 | T27 T281 T127 | T27 T281 T127 | T27 T281 T127 | T27 T281 T127 | T27 T281 T127 | T27 T281 T127 | T27 T281 T127 | T27 T281 T127 | T27 T281 T127 | T27 T281 T127 | T27 T281 T127 | T27 T281 T127 | T27 T281 T127 | T11 T27 T8 | T11 T281 T127 | T11 T8 T9 | T11 T281 T127 | T58 T281 T127 | T58 T281 T127 | T58 T281 T127 | T58 T281 T127 | T58 T281 T127 | T58 T281 T127 | T281 T127 T322 | T281 T127 T322 | T60 T281 T127 | T60 T281 T127 | T60 T281 T127 | T60 T281 T127 | T59 T60 T281 | T59 T281 T127 | T59 T281 T127 | T59 T61 T281 | T61 T281 T127 | T61 T281 T127 | T61 T281 T127 | T61 T281 T127 | T61 T281 T127 | T281 T127 T322 | T281 T127 T322 | T2 T281 T127 | T281 T127 T322 | T43 T81 T83 | T43 T81 T83 | T8 T43 T81 | T8 T9 T281 | T281 T127 T322 | T281 T127 T322 | T281 T127 T322 | T281 T127 T322 | T281 T127 T322 | T281 T127 T322 | T281 T127 T322 | T281 T127 T322 | T281 T127 T322 | T5 T23 T26 | T142 T67 T281 | T264 T43 T81 | T179 T281 T127 | T3 T231 T148 | T3 T231 T148 | T3 T231 T148 | T326 T327 T281 | T281 T127 T322 | T281 T127 T322 | T162 T281 T127 | T281 T127 T322 | T281 T127 T322 | T281 T127 T322 | T281 T127 T322 | T281 T127 T322 | T281 T127 T322
93 end
94 end : gen_level
95 end : gen_tree
96
97
98 // The results can be found at the tree root
99 1/1 assign max_valid_o = vld_tree[0];
Tests: T2 T3 T5
100 1/1 assign max_idx_o = idx_tree[0];
Tests: T2 T3 T5
101 1/1 assign max_value_o = max_tree[0];
Tests: T2 T3 T5
102
103 ////////////////
104 // Assertions //
105 ////////////////
106
107 `ifdef INC_ASSERT
108 //VCS coverage off
109 // pragma coverage off
110
111 // Helper functions for assertions below.
112 function automatic logic [Width-1:0] max_value (input logic [NumSrc-1:0][Width-1:0] values_i,
113 input logic [NumSrc-1:0] valid_i);
114 unreachable logic [Width-1:0] value = '0;
115 unreachable for (int k = 0; k < NumSrc; k++) begin
116 unreachable if (valid_i[k] && values_i[k] > value) begin
117 unreachable value = values_i[k];
118 end
==> MISSING_ELSE
119 end
120 unreachable return value;
121 endfunction : max_value
122
123 function automatic logic [SrcWidth-1:0] max_idx (input logic [NumSrc-1:0][Width-1:0] values_i,
124 input logic [NumSrc-1:0] valid_i);
125 unreachable logic [Width-1:0] value = '0;
126 unreachable logic [SrcWidth-1:0] idx = '0;
127 unreachable for (int k = NumSrc-1; k >= 0; k--) begin
128 unreachable if (valid_i[k] && values_i[k] >= value) begin
129 unreachable value = values_i[k];
130 unreachable idx = k;
131 end
==> MISSING_ELSE
132 end
133 unreachable return idx;
134 endfunction : max_idx
135
136 logic [Width-1:0] max_value_exp;
137 logic [SrcWidth-1:0] max_idx_exp;
138 unreachable assign max_value_exp = max_value(values_i, valid_i);
139 unreachable assign max_idx_exp = max_idx(values_i, valid_i);