ALERT_HANDLER Simulation Results

Wednesday December 27 2023 20:02:24 UTC

GitHub Revision: 0c759b93ab

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 85416116840666724748485424200434981761468351851988553961117902923833034512693

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	alert_handler_smoke	1.194m	2.663ms	50	50	100.00
V1	csr_hw_reset	alert_handler_csr_hw_reset	9.550s	273.895us	5	5	100.00
V1	csr_rw	alert_handler_csr_rw	9.250s	257.865us	20	20	100.00
V1	csr_bit_bash	alert_handler_csr_bit_bash	8.079m	8.708ms	5	5	100.00
V1	csr_aliasing	alert_handler_csr_aliasing	4.776m	20.002ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	alert_handler_csr_mem_rw_with_rand_reset	7.230s	140.458us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	alert_handler_csr_rw	9.250s	257.865us	20	20	100.00
		alert_handler_csr_aliasing	4.776m	20.002ms	5	5	100.00
V1		TOTAL			105	105	100.00
V2	esc_accum	alert_handler_esc_alert_accum	5.240m	11.608ms	50	50	100.00
V2	esc_timeout	alert_handler_esc_intr_timeout	1.081m	1.240ms	50	50	100.00
V2	entropy	alert_handler_entropy	54.671m	61.559ms	50	50	100.00
V2	sig_int_fail	alert_handler_sig_int_fail	1.110m	4.482ms	49	50	98.00
V2	clk_skew	alert_handler_smoke	1.194m	2.663ms	50	50	100.00
V2	random_alerts	alert_handler_random_alerts	1.088m	4.997ms	50	50	100.00
V2	random_classes	alert_handler_random_classes	58.320s	1.058ms	50	50	100.00
V2	ping_timeout	alert_handler_ping_timeout	10.810m	18.033ms	50	50	100.00
V2	lpg	alert_handler_lpg	58.473m	250.107ms	50	50	100.00
		alert_handler_lpg_stub_clk	56.345m	220.379ms	50	50	100.00
V2	stress_all	alert_handler_stress_all	59.437m	61.711ms	50	50	100.00
V2	alert_handler_entropy_stress_test	alert_handler_entropy_stress	53.060s	5.114ms	20	20	100.00
V2	alert_handler_alert_accum_saturation	alert_handler_alert_accum_saturation	3.880s	50.179us	20	20	100.00
V2	intr_test	alert_handler_intr_test	1.590s	11.381us	50	50	100.00
V2	tl_d_oob_addr_access	alert_handler_tl_errors	22.650s	1.338ms	20	20	100.00
V2	tl_d_illegal_access	alert_handler_tl_errors	22.650s	1.338ms	20	20	100.00
V2	tl_d_outstanding_access	alert_handler_csr_hw_reset	9.550s	273.895us	5	5	100.00
		alert_handler_csr_rw	9.250s	257.865us	20	20	100.00
		alert_handler_csr_aliasing	4.776m	20.002ms	5	5	100.00
		alert_handler_same_csr_outstanding	41.930s	661.122us	20	20	100.00
V2	tl_d_partial_access	alert_handler_csr_hw_reset	9.550s	273.895us	5	5	100.00
		alert_handler_csr_rw	9.250s	257.865us	20	20	100.00
		alert_handler_csr_aliasing	4.776m	20.002ms	5	5	100.00
		alert_handler_same_csr_outstanding	41.930s	661.122us	20	20	100.00
V2		TOTAL			629	630	99.84
V2S	shadow_reg_update_error	alert_handler_shadow_reg_errors	6.188m	24.303ms	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	alert_handler_shadow_reg_errors	6.188m	24.303ms	20	20	100.00
V2S	shadow_reg_storage_error	alert_handler_shadow_reg_errors	6.188m	24.303ms	20	20	100.00
V2S	shadowed_reset_glitch	alert_handler_shadow_reg_errors	6.188m	24.303ms	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	alert_handler_shadow_reg_errors_with_csr_rw	18.962m	28.305ms	20	20	100.00
V2S	tl_intg_err	alert_handler_sec_cm	23.670s	1.590ms	5	5	100.00
		alert_handler_tl_intg_err	1.070m	928.280us	20	20	100.00
V2S	sec_cm_bus_integrity	alert_handler_tl_intg_err	1.070m	928.280us	20	20	100.00
V2S	sec_cm_config_shadow	alert_handler_shadow_reg_errors	6.188m	24.303ms	20	20	100.00
V2S	sec_cm_ping_timer_config_regwen	alert_handler_smoke	1.194m	2.663ms	50	50	100.00
V2S	sec_cm_alert_config_regwen	alert_handler_smoke	1.194m	2.663ms	50	50	100.00
V2S	sec_cm_alert_loc_config_regwen	alert_handler_smoke	1.194m	2.663ms	50	50	100.00
V2S	sec_cm_class_config_regwen	alert_handler_smoke	1.194m	2.663ms	50	50	100.00
V2S	sec_cm_alert_intersig_diff	alert_handler_sig_int_fail	1.110m	4.482ms	49	50	98.00
V2S	sec_cm_lpg_intersig_mubi	alert_handler_lpg	58.473m	250.107ms	50	50	100.00
V2S	sec_cm_esc_intersig_diff	alert_handler_sig_int_fail	1.110m	4.482ms	49	50	98.00
V2S	sec_cm_alert_rx_intersig_bkgn_chk	alert_handler_entropy	54.671m	61.559ms	50	50	100.00
V2S	sec_cm_esc_tx_intersig_bkgn_chk	alert_handler_entropy	54.671m	61.559ms	50	50	100.00
V2S	sec_cm_esc_timer_fsm_sparse	alert_handler_sec_cm	23.670s	1.590ms	5	5	100.00
V2S	sec_cm_ping_timer_fsm_sparse	alert_handler_sec_cm	23.670s	1.590ms	5	5	100.00
V2S	sec_cm_esc_timer_fsm_local_esc	alert_handler_sec_cm	23.670s	1.590ms	5	5	100.00
V2S	sec_cm_ping_timer_fsm_local_esc	alert_handler_sec_cm	23.670s	1.590ms	5	5	100.00
V2S	sec_cm_esc_timer_fsm_global_esc	alert_handler_sec_cm	23.670s	1.590ms	5	5	100.00
V2S	sec_cm_accu_ctr_redun	alert_handler_sec_cm	23.670s	1.590ms	5	5	100.00
V2S	sec_cm_esc_timer_ctr_redun	alert_handler_sec_cm	23.670s	1.590ms	5	5	100.00
V2S	sec_cm_ping_timer_ctr_redun	alert_handler_sec_cm	23.670s	1.590ms	5	5	100.00
V2S	sec_cm_ping_timer_lfsr_redun	alert_handler_sec_cm	23.670s	1.590ms	5	5	100.00
V2S		TOTAL			65	65	100.00
V3	stress_all_with_rand_reset	alert_handler_stress_all_with_rand_reset	2.314h	87.826ms	49	50	98.00
V3		TOTAL			49	50	98.00
		TOTAL			848	850	99.76

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	15	15	14	93.33
V2S	4	4	4	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
99.67	99.99	98.68	99.97	100.00	100.00	99.30	99.72

Failure Buckets

• Job alert_handler-sim-vcs_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 1 failures:

  • Test alert_handler_stress_all_with_rand_reset has 1 failures.

    • 5.alert_handler_stress_all_with_rand_reset.113175983181198573579209140468598258206151594260398312734980341928029363233065
      Log /container/opentitan-public/scratch/os_regression/alert_handler-sim-vcs/5.alert_handler_stress_all_with_rand_reset/latest/run.log

        Job ID: smart:efc76de5-2187-49e3-95e1-6fd8cf279481
      

• UVM_ERROR (alert_handler_scoreboard.sv:479) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: alert_handler_reg_block.classc_state has 1 failures:

  • Test alert_handler_sig_int_fail has 1 failures.

    • 11.alert_handler_sig_int_fail.43296228273208207540039183804534332838534604692072349580315176956674177421653
      Line 257, in log /container/opentitan-public/scratch/os_regression/alert_handler-sim-vcs/11.alert_handler_sig_int_fail/latest/run.log

        UVM_ERROR @ 320645381 ps: (alert_handler_scoreboard.sv:479) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 7 [0x7]) reg name: alert_handler_reg_block.classc_state
        UVM_INFO @ 320645381 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

Past Results

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