Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_alert_handler_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_alert_handler_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_alert_handler_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_alert_handler_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_alert_handler_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	52624415	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

24879270

1

T1

92

T2

2961

T3

1430

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	12292171	1			T1	19		T2	1702		T3	551
values[0x0]	32568417	1			T1	156		T2	3581		T3	1988
values[0x1]	32643097	1			T1	155		T2	3635		T3	1938

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	45819791	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

31683894

1

T1

136

T2

3736

T3

1801

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	234131	1			T10	53		T5	6		T14	4
valid_sources[0x01]	230189	1			T4	2		T10	74		T5	3
valid_sources[0x02]	236780	1			T10	36		T5	15		T17	16
valid_sources[0x03]	237286	1			T4	1		T10	17		T5	7
valid_sources[0x04]	227851	1			T10	35		T5	5		T17	23
valid_sources[0x05]	513977	1			T10	30		T5	4		T17	12
valid_sources[0x06]	248023	1			T4	2		T10	43		T5	5
valid_sources[0x07]	230519	1			T10	56		T5	2		T14	4
valid_sources[0x08]	233385	1			T10	28		T5	8		T14	2
valid_sources[0x09]	228860	1			T10	53		T5	6		T14	1
valid_sources[0x0a]	678721	1			T4	4		T10	21		T5	2
valid_sources[0x0b]	233540	1			T10	32		T14	6		T17	26
valid_sources[0x0c]	439966	1			T4	2		T10	30		T12	6875
valid_sources[0x0d]	228590	1			T4	3		T10	80		T17	9
valid_sources[0x0e]	232421	1			T10	26		T5	9		T14	1
valid_sources[0x0f]	237971	1			T4	3		T10	26		T5	11
valid_sources[0x10]	647182	1			T10	51		T5	9		T14	2
valid_sources[0x11]	241158	1			T4	13		T10	47		T14	1
valid_sources[0x12]	234818	1			T10	31		T5	4		T14	4
valid_sources[0x13]	232303	1			T4	2		T10	37		T5	11
valid_sources[0x14]	229153	1			T4	14		T10	26		T5	6
valid_sources[0x15]	231014	1			T4	1		T10	18		T5	11
valid_sources[0x16]	249291	1			T2	8918		T4	7		T10	39
valid_sources[0x17]	228872	1			T4	1		T10	47		T14	1
valid_sources[0x18]	240553	1			T4	5		T10	63		T5	1
valid_sources[0x19]	230194	1			T4	2		T10	69		T5	12
valid_sources[0x1a]	227782	1			T10	65		T14	1		T17	18
valid_sources[0x1b]	236245	1			T3	4477		T10	58		T5	3
valid_sources[0x1c]	235956	1			T10	43		T5	7		T17	13
valid_sources[0x1d]	229060	1			T10	27		T5	4		T14	10
valid_sources[0x1e]	231160	1			T10	31		T5	3		T14	1
valid_sources[0x1f]	228708	1			T10	59		T5	2		T17	22
valid_sources[0x20]	268976	1			T10	23		T5	5		T14	4
valid_sources[0x21]	776837	1			T10	59		T5	11		T17	16
valid_sources[0x22]	237664	1			T4	5		T10	69		T5	8
valid_sources[0x23]	556100	1			T4	2		T10	46		T5	13
valid_sources[0x24]	233461	1			T4	6		T10	50		T5	9
valid_sources[0x25]	230806	1			T10	25		T14	1		T17	23
valid_sources[0x26]	234589	1			T10	31		T5	11		T14	2
valid_sources[0x27]	232574	1			T4	4		T10	51		T5	1
valid_sources[0x28]	230003	1			T10	76		T5	5		T17	10
valid_sources[0x29]	229573	1			T10	41		T5	6		T14	1
valid_sources[0x2a]	227999	1			T4	4		T10	25		T5	11
valid_sources[0x2b]	231603	1			T4	3		T10	32		T5	5
valid_sources[0x2c]	238765	1			T10	33		T5	15		T14	1
valid_sources[0x2d]	227687	1			T10	14		T5	8		T14	1
valid_sources[0x2e]	229502	1			T4	9		T10	30		T5	5
valid_sources[0x2f]	241705	1			T10	56		T5	4		T17	10
valid_sources[0x30]	228056	1			T10	1		T5	6		T17	9
valid_sources[0x31]	230648	1			T10	80		T5	8		T14	3
valid_sources[0x32]	228535	1			T10	35		T5	18		T14	1
valid_sources[0x33]	563885	1			T10	19		T5	5		T17	3
valid_sources[0x34]	228689	1			T4	9		T10	41		T5	18
valid_sources[0x35]	227535	1			T4	1		T10	6		T5	3
valid_sources[0x36]	231796	1			T10	45		T14	1		T17	11
valid_sources[0x37]	246525	1			T10	35		T5	7		T14	6
valid_sources[0x38]	246529	1			T4	3		T10	26		T5	6
valid_sources[0x39]	233458	1			T10	54		T5	3		T14	1
valid_sources[0x3a]	231782	1			T10	33		T5	9		T14	4
valid_sources[0x3b]	711791	1			T4	4		T10	13		T5	9
valid_sources[0x3c]	235150	1			T10	29		T5	3		T14	2
valid_sources[0x3d]	233427	1			T10	21		T5	5		T14	1
valid_sources[0x3e]	230688	1			T4	5		T10	63		T5	1
valid_sources[0x3f]	230106	1			T4	2		T10	25		T5	13
valid_sources[0x40]	225317	1			T4	4		T10	40		T5	8
valid_sources[0x41]	235105	1			T10	40		T5	3		T17	15
valid_sources[0x42]	231358	1			T4	5		T10	38		T5	8
valid_sources[0x43]	246940	1			T4	1		T14	2		T17	16
valid_sources[0x44]	227125	1			T10	18		T5	5		T14	4
valid_sources[0x45]	228782	1			T4	2		T10	30		T5	8
valid_sources[0x46]	230051	1			T10	38		T5	2		T17	5
valid_sources[0x47]	230642	1			T10	19		T5	4		T14	1
valid_sources[0x48]	234901	1			T4	1		T10	71		T5	6
valid_sources[0x49]	543388	1			T4	1		T10	24		T5	7
valid_sources[0x4a]	230787	1			T1	330		T4	1		T10	12
valid_sources[0x4b]	236361	1			T10	4		T5	7		T17	3
valid_sources[0x4c]	233576	1			T10	24		T5	2		T14	3
valid_sources[0x4d]	229365	1			T4	3		T10	37		T5	3
valid_sources[0x4e]	236455	1			T10	38		T5	7		T14	1
valid_sources[0x4f]	243080	1			T10	36		T5	1		T14	1
valid_sources[0x50]	228716	1			T10	13		T5	9		T14	1
valid_sources[0x51]	234305	1			T4	5		T10	8		T5	4
valid_sources[0x52]	473973	1			T10	67		T5	14		T14	1
valid_sources[0x53]	696603	1			T10	66		T5	7		T17	15
valid_sources[0x54]	453488	1			T10	37		T5	13		T17	17
valid_sources[0x55]	271689	1			T10	31		T5	6		T14	4
valid_sources[0x56]	237236	1			T4	10		T10	12		T5	6
valid_sources[0x57]	230661	1			T10	54		T5	6		T17	10
valid_sources[0x58]	233922	1			T10	62		T5	2		T14	3
valid_sources[0x59]	233041	1			T10	29		T5	7		T14	4
valid_sources[0x5a]	233408	1			T4	2		T10	37		T5	8
valid_sources[0x5b]	231944	1			T10	60		T5	2		T17	17
valid_sources[0x5c]	229919	1			T4	1		T10	32		T5	9
valid_sources[0x5d]	642985	1			T4	2		T10	38		T5	5
valid_sources[0x5e]	680905	1			T10	22		T5	10		T17	9
valid_sources[0x5f]	229423	1			T10	23		T5	3		T14	2
valid_sources[0x60]	230466	1			T10	12		T5	8		T17	15
valid_sources[0x61]	245696	1			T4	8		T10	75		T5	11
valid_sources[0x62]	228194	1			T10	34		T5	16		T14	3
valid_sources[0x63]	230481	1			T4	1		T10	4		T5	3
valid_sources[0x64]	254878	1			T4	4		T10	62		T5	2
valid_sources[0x65]	713207	1			T10	79		T5	7		T14	1
valid_sources[0x66]	230212	1			T10	45		T5	6		T14	1
valid_sources[0x67]	460280	1			T10	27		T5	5		T14	7
valid_sources[0x68]	251428	1			T10	70		T5	3		T17	9
valid_sources[0x69]	233346	1			T4	4		T10	35		T5	2
valid_sources[0x6a]	230325	1			T4	1		T10	45		T5	11
valid_sources[0x6b]	246181	1			T10	10		T5	8		T14	2
valid_sources[0x6c]	709372	1			T10	51		T5	20		T14	1
valid_sources[0x6d]	240351	1			T10	42		T17	22		T6	2
valid_sources[0x6e]	231126	1			T10	61		T5	2		T14	1
valid_sources[0x6f]	231514	1			T10	36		T5	2		T17	13
valid_sources[0x70]	246197	1			T10	30		T5	2		T14	9
valid_sources[0x71]	229172	1			T4	2		T10	20		T5	7
valid_sources[0x72]	230838	1			T4	9		T10	74		T5	8
valid_sources[0x73]	229844	1			T4	1		T10	2		T5	6
valid_sources[0x74]	229245	1			T10	70		T5	4		T14	2
valid_sources[0x75]	692851	1			T4	2		T10	15		T5	7
valid_sources[0x76]	901388	1			T10	11		T5	4		T14	2
valid_sources[0x77]	230972	1			T4	5		T10	50		T5	7
valid_sources[0x78]	241451	1			T10	1		T5	6		T14	3
valid_sources[0x79]	229268	1			T10	33		T5	2		T17	23
valid_sources[0x7a]	230221	1			T4	3		T10	33		T5	1
valid_sources[0x7b]	231591	1			T10	56		T14	4		T17	23
valid_sources[0x7c]	227717	1			T10	18		T5	3		T17	14
valid_sources[0x7d]	233116	1			T10	44		T5	9		T14	1
valid_sources[0x7e]	265160	1			T4	1		T10	27		T5	17
valid_sources[0x7f]	250837	1			T10	52		T17	10		T6	3
valid_sources[0x80]	229192	1			T10	68		T5	11		T17	14

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

5878807

1

T1

7

T2

836

T3

268

values[0x0]

all_enables

biggest_size

12140841

1

T1

62

T2

1348

T3

756

values[0x1]

all_enables

biggest_size

6859622

1

T1

23

T2

777

T3

406