Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_alert_handler_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_alert_handler_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_alert_handler_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_alert_handler_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_alert_handler_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	62186556	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

30354856

1

T1

89

T2

550

T3

110

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	14037056	1			T1	19		T2	630		T3	21
values[0x0]	38122928	1			T1	152		T2	447		T3	156
values[0x1]	40381428	1			T1	159		T2	435		T3	161

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	52898215	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

39643197

1

T1

117

T2

683

T3

136

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	315526	1			T1	5		T4	2		T12	2
valid_sources[0x01]	285365	1			T3	2		T12	4		T14	13
valid_sources[0x02]	288708	1			T3	2		T4	6		T12	14
valid_sources[0x03]	296104	1			T3	2		T12	4		T14	3
valid_sources[0x04]	778018	1			T3	1		T4	4		T12	14
valid_sources[0x05]	355947	1			T3	1		T12	12		T14	36
valid_sources[0x06]	296641	1			T3	1		T12	12		T14	38
valid_sources[0x07]	289725	1			T4	3		T12	5		T14	27
valid_sources[0x08]	765802	1			T3	1		T12	15		T14	31
valid_sources[0x09]	290864	1			T3	1		T12	9		T14	49
valid_sources[0x0a]	305850	1			T3	5		T4	6		T12	11
valid_sources[0x0b]	305580	1			T3	1		T4	1		T12	6
valid_sources[0x0c]	290553	1			T1	3		T3	4		T12	6
valid_sources[0x0d]	299981	1			T3	1		T4	25		T12	6
valid_sources[0x0e]	609456	1			T12	10		T14	13		T13	13
valid_sources[0x0f]	287256	1			T3	3		T12	3		T14	64
valid_sources[0x10]	289643	1			T12	7		T14	29		T13	18
valid_sources[0x11]	303770	1			T4	3		T12	14		T14	13
valid_sources[0x12]	298105	1			T3	1		T4	1		T12	13
valid_sources[0x13]	298074	1			T4	2		T12	10		T14	22
valid_sources[0x14]	283024	1			T3	1		T12	13		T14	13
valid_sources[0x15]	291622	1			T1	1		T3	3		T4	1
valid_sources[0x16]	549417	1			T1	17		T3	2		T12	10
valid_sources[0x17]	287767	1			T3	2		T12	6		T14	63
valid_sources[0x18]	303512	1			T3	2		T12	9		T14	26
valid_sources[0x19]	657586	1			T3	2		T12	12		T14	8
valid_sources[0x1a]	574310	1			T1	3		T3	2		T4	1
valid_sources[0x1b]	289955	1			T12	16		T14	16		T13	12
valid_sources[0x1c]	285549	1			T1	3		T4	6		T12	12
valid_sources[0x1d]	535251	1			T3	1		T12	11		T14	34
valid_sources[0x1e]	342428	1			T3	2		T12	3		T14	46
valid_sources[0x1f]	295557	1			T3	3		T4	6		T12	7
valid_sources[0x20]	469125	1			T3	7		T4	2		T12	5
valid_sources[0x21]	341625	1			T12	7		T14	14		T13	15
valid_sources[0x22]	297194	1			T3	3		T4	1		T12	12
valid_sources[0x23]	297572	1			T12	15		T14	25		T13	19
valid_sources[0x24]	294176	1			T4	13		T12	10		T14	12
valid_sources[0x25]	295270	1			T1	17		T3	3		T4	3
valid_sources[0x26]	286650	1			T3	3		T4	20		T12	15
valid_sources[0x27]	295833	1			T1	13		T3	1		T4	1
valid_sources[0x28]	326561	1			T3	2		T12	7		T14	16
valid_sources[0x29]	293857	1			T1	2		T3	5		T4	6
valid_sources[0x2a]	305611	1			T1	3		T3	3		T12	13
valid_sources[0x2b]	655605	1			T12	8		T14	28		T13	16
valid_sources[0x2c]	305887	1			T3	2		T12	7		T14	18
valid_sources[0x2d]	304605	1			T4	8		T12	10		T14	15
valid_sources[0x2e]	296179	1			T3	1		T4	4		T12	11
valid_sources[0x2f]	285318	1			T4	3		T12	9		T14	14
valid_sources[0x30]	289989	1			T12	9		T14	24		T13	12
valid_sources[0x31]	330893	1			T3	1		T12	5		T14	17
valid_sources[0x32]	668782	1			T3	4		T4	3		T12	6
valid_sources[0x33]	819989	1			T3	1		T4	12		T12	6
valid_sources[0x34]	301843	1			T4	7		T12	10		T14	30
valid_sources[0x35]	295146	1			T4	7		T12	3		T14	20
valid_sources[0x36]	296407	1			T1	11		T4	3		T12	11
valid_sources[0x37]	297176	1			T12	10		T14	4		T13	14
valid_sources[0x38]	295355	1			T3	1		T4	4		T12	12
valid_sources[0x39]	296338	1			T3	1		T4	1		T12	7
valid_sources[0x3a]	296500	1			T12	12		T14	3		T13	17
valid_sources[0x3b]	293742	1			T3	1		T11	4525		T12	10
valid_sources[0x3c]	302593	1			T3	1		T12	11		T14	29
valid_sources[0x3d]	293164	1			T4	1		T12	10		T14	14
valid_sources[0x3e]	284147	1			T1	2		T3	2		T12	9
valid_sources[0x3f]	286707	1			T1	3		T4	7		T12	9
valid_sources[0x40]	289618	1			T12	12		T14	9		T13	11
valid_sources[0x41]	297926	1			T1	8		T3	2		T4	7
valid_sources[0x42]	299408	1			T1	4		T3	1		T4	2
valid_sources[0x43]	300865	1			T3	1		T4	3		T12	7
valid_sources[0x44]	292581	1			T12	4		T14	11		T13	20
valid_sources[0x45]	292088	1			T1	1		T3	1		T4	1
valid_sources[0x46]	523275	1			T3	2		T4	15		T12	14
valid_sources[0x47]	315706	1			T3	3		T4	2		T12	4
valid_sources[0x48]	524523	1			T3	2		T12	6		T14	8
valid_sources[0x49]	316441	1			T3	2		T4	2		T12	9
valid_sources[0x4a]	284768	1			T3	1		T4	6		T12	11
valid_sources[0x4b]	289295	1			T2	1512		T3	1		T4	1
valid_sources[0x4c]	294779	1			T1	4		T3	3		T4	2
valid_sources[0x4d]	286029	1			T1	2		T12	8		T14	26
valid_sources[0x4e]	310656	1			T4	7		T12	5		T14	32
valid_sources[0x4f]	291798	1			T3	2		T12	13		T14	1
valid_sources[0x50]	332667	1			T1	5		T3	1		T4	4
valid_sources[0x51]	294654	1			T1	5		T3	2		T12	12
valid_sources[0x52]	290769	1			T12	13		T14	17		T13	16
valid_sources[0x53]	289892	1			T3	3		T4	4		T12	9
valid_sources[0x54]	293656	1			T12	13		T14	26		T13	17
valid_sources[0x55]	302532	1			T3	1		T4	5		T12	11
valid_sources[0x56]	300184	1			T3	1		T12	11		T14	20
valid_sources[0x57]	287748	1			T4	3		T12	12		T14	35
valid_sources[0x58]	292754	1			T3	2		T4	7		T12	10
valid_sources[0x59]	659248	1			T3	2		T4	15		T12	3
valid_sources[0x5a]	286336	1			T3	3		T4	2		T12	6
valid_sources[0x5b]	296931	1			T3	1		T12	9		T14	33
valid_sources[0x5c]	293128	1			T4	17		T12	8		T14	19
valid_sources[0x5d]	284643	1			T3	1		T4	2		T12	8
valid_sources[0x5e]	289558	1			T3	2		T4	1		T12	8
valid_sources[0x5f]	299370	1			T3	1		T4	2		T12	8
valid_sources[0x60]	295447	1			T3	4		T12	5		T14	12
valid_sources[0x61]	291811	1			T4	2		T12	10		T14	16
valid_sources[0x62]	302628	1			T1	2		T4	1		T12	10
valid_sources[0x63]	286312	1			T3	3		T4	8		T12	11
valid_sources[0x64]	298084	1			T3	2		T12	11		T14	27
valid_sources[0x65]	288754	1			T3	1		T4	3		T12	7
valid_sources[0x66]	290550	1			T3	1		T4	6		T12	10
valid_sources[0x67]	291102	1			T12	6		T14	24		T13	21
valid_sources[0x68]	279935	1			T1	6		T3	2		T4	3
valid_sources[0x69]	307320	1			T3	6		T4	3		T12	13
valid_sources[0x6a]	842546	1			T1	8		T3	2		T4	1
valid_sources[0x6b]	293095	1			T1	4		T4	12		T12	6
valid_sources[0x6c]	291224	1			T3	1		T4	2		T12	12
valid_sources[0x6d]	300672	1			T3	3		T12	10		T14	7
valid_sources[0x6e]	287459	1			T3	1		T12	4		T14	36
valid_sources[0x6f]	287115	1			T3	3		T12	8		T14	35
valid_sources[0x70]	297393	1			T3	1		T4	2		T12	8
valid_sources[0x71]	280178	1			T3	2		T4	3		T12	6
valid_sources[0x72]	286069	1			T3	1		T4	1		T12	13
valid_sources[0x73]	518441	1			T4	10		T12	12		T14	25
valid_sources[0x74]	294496	1			T4	19		T12	8		T14	18
valid_sources[0x75]	850299	1			T4	6		T12	3		T14	50
valid_sources[0x76]	299665	1			T4	4		T12	13		T14	18
valid_sources[0x77]	334878	1			T1	23		T3	2		T12	6
valid_sources[0x78]	305619	1			T1	2		T4	9		T12	8
valid_sources[0x79]	300019	1			T3	3		T4	8		T12	5
valid_sources[0x7a]	301212	1			T1	1		T3	2		T12	12
valid_sources[0x7b]	636492	1			T3	1		T4	6		T12	5
valid_sources[0x7c]	287924	1			T3	1		T4	5		T12	18
valid_sources[0x7d]	576743	1			T1	1		T3	1		T12	8
valid_sources[0x7e]	304666	1			T1	4		T3	1		T4	6
valid_sources[0x7f]	556330	1			T3	2		T4	3		T12	11
valid_sources[0x80]	285964	1			T12	11		T14	19		T13	9

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

7037850

1

T1

8

T2

296

T3

12

values[0x0]

all_enables

biggest_size

14684799

1

T1

50

T2

159

T3

65

values[0x1]

all_enables

biggest_size

8632207

1

T1

31

T2

95

T3

33