Tests
dashboard | hierarchy | modlist | groups | tests | asserts
Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
99.25 99.99 98.72 97.09 100.00 100.00 99.38 99.56


Total test records in report: 827
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html | tests13.html | tests14.html | tests15.html | tests16.html
T204 /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/cover_reg_top/15.alert_handler_tl_intg_err.1165235985 Feb 09 03:38:22 AM UTC 25 Feb 09 03:39:45 AM UTC 25 931895643 ps
T780 /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/cover_reg_top/17.alert_handler_intr_test.3298128193 Feb 09 03:39:45 AM UTC 25 Feb 09 03:39:49 AM UTC 25 15704885 ps
T781 /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/cover_reg_top/17.alert_handler_tl_errors.2206425016 Feb 09 03:39:38 AM UTC 25 Feb 09 03:39:49 AM UTC 25 919395740 ps
T195 /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/cover_reg_top/17.alert_handler_tl_intg_err.321674020 Feb 09 03:39:42 AM UTC 25 Feb 09 03:39:50 AM UTC 25 56439729 ps
T168 /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/cover_reg_top/11.alert_handler_shadow_reg_errors.3181939118 Feb 09 03:36:04 AM UTC 25 Feb 09 03:39:52 AM UTC 25 6042661171 ps
T782 /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/cover_reg_top/16.alert_handler_same_csr_outstanding.1700925547 Feb 09 03:39:24 AM UTC 25 Feb 09 03:39:55 AM UTC 25 358208892 ps
T783 /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/cover_reg_top/17.alert_handler_csr_mem_rw_with_rand_reset.3209174311 Feb 09 03:39:51 AM UTC 25 Feb 09 03:39:58 AM UTC 25 34101912 ps
T784 /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/cover_reg_top/17.alert_handler_csr_rw.530955452 Feb 09 03:39:50 AM UTC 25 Feb 09 03:40:02 AM UTC 25 370326046 ps
T165 /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/cover_reg_top/13.alert_handler_shadow_reg_errors.2134388437 Feb 09 03:37:15 AM UTC 25 Feb 09 03:40:08 AM UTC 25 2014761256 ps
T785 /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/cover_reg_top/18.alert_handler_intr_test.1471206998 Feb 09 03:40:06 AM UTC 25 Feb 09 03:40:10 AM UTC 25 16307344 ps
T786 /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/cover_reg_top/18.alert_handler_tl_errors.2640830771 Feb 09 03:39:59 AM UTC 25 Feb 09 03:40:10 AM UTC 25 79930160 ps
T787 /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/cover_reg_top/18.alert_handler_csr_rw.2180681565 Feb 09 03:40:10 AM UTC 25 Feb 09 03:40:16 AM UTC 25 58169439 ps
T788 /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/cover_reg_top/18.alert_handler_csr_mem_rw_with_rand_reset.3948079374 Feb 09 03:40:11 AM UTC 25 Feb 09 03:40:19 AM UTC 25 52039146 ps
T789 /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/cover_reg_top/18.alert_handler_same_csr_outstanding.1422904554 Feb 09 03:40:11 AM UTC 25 Feb 09 03:40:41 AM UTC 25 255674693 ps
T790 /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/cover_reg_top/3.alert_handler_csr_bit_bash.4076397373 Feb 09 03:29:59 AM UTC 25 Feb 09 03:40:54 AM UTC 25 142639089983 ps
T202 /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/cover_reg_top/18.alert_handler_tl_intg_err.2016359868 Feb 09 03:40:03 AM UTC 25 Feb 09 03:40:55 AM UTC 25 2108123778 ps
T172 /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/cover_reg_top/6.alert_handler_shadow_reg_errors_with_csr_rw.3212557114 Feb 09 03:32:42 AM UTC 25 Feb 09 03:40:58 AM UTC 25 9423512529 ps
T791 /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/cover_reg_top/19.alert_handler_intr_test.492845571 Feb 09 03:40:57 AM UTC 25 Feb 09 03:41:00 AM UTC 25 7164497 ps
T201 /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/cover_reg_top/19.alert_handler_tl_intg_err.3910684738 Feb 09 03:40:56 AM UTC 25 Feb 09 03:41:01 AM UTC 25 53760265 ps
T792 /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/cover_reg_top/17.alert_handler_same_csr_outstanding.1346890241 Feb 09 03:39:51 AM UTC 25 Feb 09 03:41:04 AM UTC 25 1408361251 ps
T793 /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/cover_reg_top/19.alert_handler_tl_errors.2568119470 Feb 09 03:40:43 AM UTC 25 Feb 09 03:41:07 AM UTC 25 201769863 ps
T794 /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/cover_reg_top/20.alert_handler_intr_test.2500032247 Feb 09 03:41:05 AM UTC 25 Feb 09 03:41:09 AM UTC 25 20165575 ps
T795 /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/cover_reg_top/19.alert_handler_csr_rw.3657423952 Feb 09 03:41:00 AM UTC 25 Feb 09 03:41:09 AM UTC 25 62754544 ps
T796 /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/cover_reg_top/21.alert_handler_intr_test.3095038610 Feb 09 03:41:08 AM UTC 25 Feb 09 03:41:11 AM UTC 25 8139656 ps
T797 /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/cover_reg_top/19.alert_handler_csr_mem_rw_with_rand_reset.2614824494 Feb 09 03:41:02 AM UTC 25 Feb 09 03:41:12 AM UTC 25 270281069 ps
T798 /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/cover_reg_top/22.alert_handler_intr_test.3780932491 Feb 09 03:41:10 AM UTC 25 Feb 09 03:41:13 AM UTC 25 9231609 ps
T799 /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/cover_reg_top/23.alert_handler_intr_test.721072487 Feb 09 03:41:10 AM UTC 25 Feb 09 03:41:14 AM UTC 25 6766191 ps
T800 /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/cover_reg_top/24.alert_handler_intr_test.2138119392 Feb 09 03:41:12 AM UTC 25 Feb 09 03:41:16 AM UTC 25 7441563 ps
T801 /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/cover_reg_top/25.alert_handler_intr_test.3802048564 Feb 09 03:41:13 AM UTC 25 Feb 09 03:41:17 AM UTC 25 11504987 ps
T802 /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/cover_reg_top/26.alert_handler_intr_test.656687564 Feb 09 03:41:15 AM UTC 25 Feb 09 03:41:18 AM UTC 25 8611902 ps
T803 /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/cover_reg_top/27.alert_handler_intr_test.769614266 Feb 09 03:41:15 AM UTC 25 Feb 09 03:41:18 AM UTC 25 8186197 ps
T804 /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/cover_reg_top/28.alert_handler_intr_test.1776372246 Feb 09 03:41:17 AM UTC 25 Feb 09 03:41:20 AM UTC 25 17700378 ps
T805 /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/cover_reg_top/29.alert_handler_intr_test.586254909 Feb 09 03:41:18 AM UTC 25 Feb 09 03:41:21 AM UTC 25 8152374 ps
T806 /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/cover_reg_top/31.alert_handler_intr_test.2670271560 Feb 09 03:41:19 AM UTC 25 Feb 09 03:41:22 AM UTC 25 17002784 ps
T807 /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/cover_reg_top/30.alert_handler_intr_test.853422705 Feb 09 03:41:19 AM UTC 25 Feb 09 03:41:23 AM UTC 25 20224824 ps
T808 /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/cover_reg_top/33.alert_handler_intr_test.3475971345 Feb 09 03:41:23 AM UTC 25 Feb 09 03:41:26 AM UTC 25 8307532 ps
T809 /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/cover_reg_top/32.alert_handler_intr_test.1476673701 Feb 09 03:41:22 AM UTC 25 Feb 09 03:41:26 AM UTC 25 28989280 ps
T810 /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/cover_reg_top/35.alert_handler_intr_test.1393985513 Feb 09 03:41:24 AM UTC 25 Feb 09 03:41:27 AM UTC 25 17436301 ps
T811 /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/cover_reg_top/34.alert_handler_intr_test.3211867650 Feb 09 03:41:24 AM UTC 25 Feb 09 03:41:28 AM UTC 25 8617343 ps
T812 /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/cover_reg_top/37.alert_handler_intr_test.1416414900 Feb 09 03:41:27 AM UTC 25 Feb 09 03:41:31 AM UTC 25 12432428 ps
T813 /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/cover_reg_top/36.alert_handler_intr_test.3478675260 Feb 09 03:41:27 AM UTC 25 Feb 09 03:41:31 AM UTC 25 12965262 ps
T161 /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/cover_reg_top/15.alert_handler_shadow_reg_errors.455239728 Feb 09 03:38:12 AM UTC 25 Feb 09 03:41:32 AM UTC 25 6595803632 ps
T814 /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/cover_reg_top/39.alert_handler_intr_test.418873310 Feb 09 03:41:29 AM UTC 25 Feb 09 03:41:32 AM UTC 25 8126196 ps
T815 /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/cover_reg_top/38.alert_handler_intr_test.2717477706 Feb 09 03:41:29 AM UTC 25 Feb 09 03:41:33 AM UTC 25 13155751 ps
T816 /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/cover_reg_top/41.alert_handler_intr_test.429936080 Feb 09 03:41:32 AM UTC 25 Feb 09 03:41:35 AM UTC 25 16091353 ps
T817 /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/cover_reg_top/40.alert_handler_intr_test.3192888194 Feb 09 03:41:32 AM UTC 25 Feb 09 03:41:35 AM UTC 25 9260352 ps
T818 /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/cover_reg_top/42.alert_handler_intr_test.2323347373 Feb 09 03:41:33 AM UTC 25 Feb 09 03:41:36 AM UTC 25 21407484 ps
T819 /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/cover_reg_top/43.alert_handler_intr_test.3858235918 Feb 09 03:41:33 AM UTC 25 Feb 09 03:41:36 AM UTC 25 43376652 ps
T820 /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/cover_reg_top/44.alert_handler_intr_test.3444047626 Feb 09 03:41:34 AM UTC 25 Feb 09 03:41:38 AM UTC 25 8542816 ps
T821 /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/cover_reg_top/19.alert_handler_same_csr_outstanding.4195390080 Feb 09 03:41:01 AM UTC 25 Feb 09 03:41:39 AM UTC 25 785583812 ps
T822 /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/cover_reg_top/45.alert_handler_intr_test.2410569756 Feb 09 03:41:37 AM UTC 25 Feb 09 03:41:40 AM UTC 25 7550010 ps
T823 /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/cover_reg_top/46.alert_handler_intr_test.4115744609 Feb 09 03:41:37 AM UTC 25 Feb 09 03:41:40 AM UTC 25 15819248 ps
T824 /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/cover_reg_top/47.alert_handler_intr_test.461259491 Feb 09 03:41:37 AM UTC 25 Feb 09 03:41:40 AM UTC 25 21791962 ps
T825 /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/cover_reg_top/48.alert_handler_intr_test.1459534883 Feb 09 03:41:37 AM UTC 25 Feb 09 03:41:40 AM UTC 25 7568873 ps
T826 /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/cover_reg_top/49.alert_handler_intr_test.2625790311 Feb 09 03:41:39 AM UTC 25 Feb 09 03:41:42 AM UTC 25 15476823 ps
T175 /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/cover_reg_top/7.alert_handler_shadow_reg_errors_with_csr_rw.2274399573 Feb 09 03:33:26 AM UTC 25 Feb 09 03:42:03 AM UTC 25 9546142699 ps
T176 /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/cover_reg_top/9.alert_handler_shadow_reg_errors.2832372115 Feb 09 03:35:06 AM UTC 25 Feb 09 03:42:16 AM UTC 25 6426633165 ps
T178 /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/cover_reg_top/16.alert_handler_shadow_reg_errors.783622837 Feb 09 03:39:04 AM UTC 25 Feb 09 03:42:26 AM UTC 25 10351999129 ps
T184 /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/cover_reg_top/8.alert_handler_shadow_reg_errors_with_csr_rw.825147203 Feb 09 03:34:42 AM UTC 25 Feb 09 03:42:29 AM UTC 25 12423862784 ps
T162 /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/cover_reg_top/18.alert_handler_shadow_reg_errors.1319045291 Feb 09 03:39:55 AM UTC 25 Feb 09 03:42:46 AM UTC 25 22567297969 ps
T181 /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/cover_reg_top/12.alert_handler_shadow_reg_errors.1213461724 Feb 09 03:36:34 AM UTC 25 Feb 09 03:42:50 AM UTC 25 10349496005 ps
T163 /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/cover_reg_top/17.alert_handler_shadow_reg_errors.963864552 Feb 09 03:39:37 AM UTC 25 Feb 09 03:43:39 AM UTC 25 1968027955 ps
T187 /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/cover_reg_top/14.alert_handler_shadow_reg_errors_with_csr_rw.4233134844 Feb 09 03:37:42 AM UTC 25 Feb 09 03:43:39 AM UTC 25 2716715497 ps
T398 /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/cover_reg_top/10.alert_handler_shadow_reg_errors_with_csr_rw.3536369181 Feb 09 03:35:31 AM UTC 25 Feb 09 03:43:56 AM UTC 25 26604253448 ps
T180 /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/cover_reg_top/14.alert_handler_shadow_reg_errors.3879296656 Feb 09 03:37:55 AM UTC 25 Feb 09 03:44:12 AM UTC 25 28598800241 ps
T182 /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/cover_reg_top/19.alert_handler_shadow_reg_errors.812890739 Feb 09 03:40:20 AM UTC 25 Feb 09 03:44:16 AM UTC 25 12817793682 ps
T179 /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/cover_reg_top/15.alert_handler_shadow_reg_errors_with_csr_rw.1128587009 Feb 09 03:38:08 AM UTC 25 Feb 09 03:44:59 AM UTC 25 4585249161 ps
T185 /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/cover_reg_top/16.alert_handler_shadow_reg_errors_with_csr_rw.1964414684 Feb 09 03:38:58 AM UTC 25 Feb 09 03:46:27 AM UTC 25 40112888231 ps
T183 /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/cover_reg_top/18.alert_handler_shadow_reg_errors_with_csr_rw.4288538406 Feb 09 03:39:53 AM UTC 25 Feb 09 03:47:58 AM UTC 25 68873044392 ps
T399 /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/cover_reg_top/19.alert_handler_shadow_reg_errors_with_csr_rw.395176462 Feb 09 03:40:17 AM UTC 25 Feb 09 03:48:00 AM UTC 25 7548342278 ps
T188 /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/cover_reg_top/12.alert_handler_shadow_reg_errors_with_csr_rw.1995309616 Feb 09 03:36:29 AM UTC 25 Feb 09 03:50:32 AM UTC 25 5062694443 ps
T396 /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/cover_reg_top/4.alert_handler_shadow_reg_errors_with_csr_rw.1703242468 Feb 09 03:30:19 AM UTC 25 Feb 09 03:51:08 AM UTC 25 16827197683 ps
T400 /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/cover_reg_top/5.alert_handler_shadow_reg_errors_with_csr_rw.2726864844 Feb 09 03:31:57 AM UTC 25 Feb 09 03:51:13 AM UTC 25 51101519172 ps
T186 /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/cover_reg_top/13.alert_handler_shadow_reg_errors_with_csr_rw.1551279390 Feb 09 03:37:10 AM UTC 25 Feb 09 03:51:46 AM UTC 25 10992018136 ps
T397 /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/cover_reg_top/9.alert_handler_shadow_reg_errors_with_csr_rw.2166794709 Feb 09 03:35:04 AM UTC 25 Feb 09 03:52:05 AM UTC 25 135210254403 ps
T401 /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/cover_reg_top/11.alert_handler_shadow_reg_errors_with_csr_rw.1541792121 Feb 09 03:35:58 AM UTC 25 Feb 09 03:54:34 AM UTC 25 110497064727 ps
T827 /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/cover_reg_top/17.alert_handler_shadow_reg_errors_with_csr_rw.3166413136 Feb 09 03:39:27 AM UTC 25 Feb 09 03:57:05 AM UTC 25 271856920281 ps

Test location /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default/0.alert_handler_sig_int_fail.827566908
Short name T13
Test name
Test status
Simulation time 273828285 ps
CPU time 21.73 seconds
Started Feb 08 07:04:38 PM UTC 25
Finished Feb 08 07:05:01 PM UTC 25
Peak memory 263204 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo
/hw/dv/tools/sim.tcl +ntb_random_seed=827566908 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default.vdb -cm_l
og /dev/null -cm_name 0.alert_handler_sig_int_fail.827566908
Directory /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/0.alert_handler_sig_int_fail/latest

Test location /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default/1.alert_handler_sec_cm.76290274
Short name T6
Test name
Test status
Simulation time 3929844478 ps
CPU time 29.91 seconds
Started Feb 08 07:04:51 PM UTC 25
Finished Feb 08 07:05:23 PM UTC 25
Peak memory 297352 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=76290274 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=ale
rt_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_sec_cm.76290274
Directory /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/1.alert_handler_sec_cm/latest

Test location /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default/2.alert_handler_random_classes.3545272714
Short name T24
Test name
Test status
Simulation time 106040008 ps
CPU time 16.74 seconds
Started Feb 08 07:04:58 PM UTC 25
Finished Feb 08 07:05:16 PM UTC 25
Peak memory 263208 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo
/hw/dv/tools/sim.tcl +ntb_random_seed=3545272714 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_class
es_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default.vdb -c
m_log /dev/null -cm_name 2.alert_handler_random_classes.3545272714
Directory /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/2.alert_handler_random_classes/latest

Test location /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default/0.alert_handler_entropy_stress.4198894579
Short name T5
Test name
Test status
Simulation time 3341918099 ps
CPU time 32 seconds
Started Feb 08 07:04:38 PM UTC 25
Finished Feb 08 07:05:12 PM UTC 25
Peak memory 263276 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
paces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4198894579 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_en
tropy_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 0.alert_handler_entropy_stress.4198894579
Directory /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/0.alert_handler_entropy_stress/latest

Test location /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default/2.alert_handler_stress_all_with_rand_reset.2970409774
Short name T103
Test name
Test status
Simulation time 84119145088 ps
CPU time 1810.98 seconds
Started Feb 08 07:05:17 PM UTC 25
Finished Feb 08 07:35:49 PM UTC 25
Peak memory 300196 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=ale
rt_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=29704
09774 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_stress_all
_with_rand_reset.2970409774
Directory /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/2.alert_handler_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/cover_reg_top/2.alert_handler_tl_intg_err.3469362095
Short name T191
Test name
Test status
Simulation time 162919018 ps
CPU time 29.95 seconds
Started Feb 09 03:27:36 AM UTC 25
Finished Feb 09 03:28:07 AM UTC 25
Peak memory 252120 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3469362095 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TE
ST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/alert_handler-sim-vc
s/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_tl_intg_err.3469362095
Directory /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/2.alert_handler_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default/1.alert_handler_stress_all.1063189100
Short name T42
Test name
Test status
Simulation time 4869629286 ps
CPU time 69.85 seconds
Started Feb 08 07:04:45 PM UTC 25
Finished Feb 08 07:05:57 PM UTC 25
Peak memory 265512 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1063189100 -assert nopostproc +UVM_TESTNAME=ale
rt_handler_base_test +UVM_TEST_SEQ=alert_handler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os
_regression/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_stress_all.1063189100
Directory /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/1.alert_handler_stress_all/latest

Test location /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default/16.alert_handler_stress_all.3568532762
Short name T109
Test name
Test status
Simulation time 24068647296 ps
CPU time 1407.64 seconds
Started Feb 08 07:32:08 PM UTC 25
Finished Feb 08 07:55:51 PM UTC 25
Peak memory 302116 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3568532762 -assert nopostproc +UVM_TESTNAME=ale
rt_handler_base_test +UVM_TEST_SEQ=alert_handler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os
_regression/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_stress_all.3568532762
Directory /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/16.alert_handler_stress_all/latest

Test location /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default/2.alert_handler_esc_intr_timeout.877587583
Short name T15
Test name
Test status
Simulation time 3406886640 ps
CPU time 44.49 seconds
Started Feb 08 07:05:00 PM UTC 25
Finished Feb 08 07:05:46 PM UTC 25
Peak memory 263476 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo
/hw/dv/tools/sim.tcl +ntb_random_seed=877587583 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_time
out_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 2.alert_handler_esc_intr_timeout.877587583
Directory /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/2.alert_handler_esc_intr_timeout/latest

Test location /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default/4.alert_handler_entropy.1655286732
Short name T138
Test name
Test status
Simulation time 66114261929 ps
CPU time 1376.45 seconds
Started Feb 08 07:06:15 PM UTC 25
Finished Feb 08 07:29:27 PM UTC 25
Peak memory 298036 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1655286732 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST
_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_entropy.1655286732
Directory /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/4.alert_handler_entropy/latest

Test location /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/cover_reg_top/2.alert_handler_shadow_reg_errors.2306815432
Short name T167
Test name
Test status
Simulation time 6471339631 ps
CPU time 267.73 seconds
Started Feb 09 03:27:32 AM UTC 25
Finished Feb 09 03:32:04 AM UTC 25
Peak memory 279064 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2306815432 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +
UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/alert_handler-
sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_shadow_reg_errors.2306815432
Directory /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/2.alert_handler_shadow_reg_errors/latest

Test location /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default/7.alert_handler_lpg.4211881083
Short name T333
Test name
Test status
Simulation time 126013724873 ps
CPU time 2056.73 seconds
Started Feb 08 07:08:25 PM UTC 25
Finished Feb 08 07:43:06 PM UTC 25
Peak memory 285728 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4211881083 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST
_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_lpg.4211881083
Directory /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/7.alert_handler_lpg/latest

Test location /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default/0.alert_handler_esc_alert_accum.197959431
Short name T33
Test name
Test status
Simulation time 1167987968 ps
CPU time 24.34 seconds
Started Feb 08 07:04:38 PM UTC 25
Finished Feb 08 07:05:04 PM UTC 25
Peak memory 269284 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo
/hw/dv/tools/sim.tcl +ntb_random_seed=197959431 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_acc
um_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default.vdb -c
m_log /dev/null -cm_name 0.alert_handler_esc_alert_accum.197959431
Directory /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/0.alert_handler_esc_alert_accum/latest

Test location /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default/6.alert_handler_stress_all.19437461
Short name T64
Test name
Test status
Simulation time 36062550995 ps
CPU time 2011.03 seconds
Started Feb 08 07:07:50 PM UTC 25
Finished Feb 08 07:41:42 PM UTC 25
Peak memory 298220 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=19437461 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_stress_all.19437461
Directory /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/6.alert_handler_stress_all/latest

Test location /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default/8.alert_handler_stress_all_with_rand_reset.1686679257
Short name T313
Test name
Test status
Simulation time 70197878160 ps
CPU time 7948.93 seconds
Started Feb 08 07:10:28 PM UTC 25
Finished Feb 08 09:24:27 PM UTC 25
Peak memory 370532 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=ale
rt_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=16866
79257 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_stress_all
_with_rand_reset.1686679257
Directory /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/8.alert_handler_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default/39.alert_handler_stress_all.547936934
Short name T591
Test name
Test status
Simulation time 19831309244 ps
CPU time 138.44 seconds
Started Feb 08 08:45:38 PM UTC 25
Finished Feb 08 08:47:59 PM UTC 25
Peak memory 269424 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=547936934 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_
regression/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_stress_all.547936934
Directory /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/39.alert_handler_stress_all/latest

Test location /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default/44.alert_handler_stress_all.3347144576
Short name T696
Test name
Test status
Simulation time 61543817573 ps
CPU time 1807.29 seconds
Started Feb 08 09:04:43 PM UTC 25
Finished Feb 08 09:35:13 PM UTC 25
Peak memory 302820 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3347144576 -assert nopostproc +UVM_TESTNAME=ale
rt_handler_base_test +UVM_TEST_SEQ=alert_handler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os
_regression/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_stress_all.3347144576
Directory /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/44.alert_handler_stress_all/latest

Test location /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/cover_reg_top/10.alert_handler_shadow_reg_errors.480958589
Short name T173
Test name
Test status
Simulation time 3966954945 ps
CPU time 203.97 seconds
Started Feb 09 03:35:38 AM UTC 25
Finished Feb 09 03:39:05 AM UTC 25
Peak memory 279068 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=480958589 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +U
VM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/alert_handler-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.alert_handler_shadow_reg_errors.480958589
Directory /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/10.alert_handler_shadow_reg_errors/latest

Test location /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/cover_reg_top/5.alert_handler_shadow_reg_errors_with_csr_rw.2726864844
Short name T400
Test name
Test status
Simulation time 51101519172 ps
CPU time 1142.76 seconds
Started Feb 09 03:31:57 AM UTC 25
Finished Feb 09 03:51:13 AM UTC 25
Peak memory 279060 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_sc
b=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2726864844 -assert nopostpro
c +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.alert_handler_shadow_reg_errors_with_csr_
rw.2726864844
Directory /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/5.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default/26.alert_handler_sig_int_fail.3164597510
Short name T107
Test name
Test status
Simulation time 1027387068 ps
CPU time 44.93 seconds
Started Feb 08 08:03:29 PM UTC 25
Finished Feb 08 08:04:16 PM UTC 25
Peak memory 263144 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo
/hw/dv/tools/sim.tcl +ntb_random_seed=3164597510 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default.vdb -cm_
log /dev/null -cm_name 26.alert_handler_sig_int_fail.3164597510
Directory /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/26.alert_handler_sig_int_fail/latest

Test location /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default/5.alert_handler_ping_timeout.2385013520
Short name T340
Test name
Test status
Simulation time 28549230825 ps
CPU time 407.77 seconds
Started Feb 08 07:07:12 PM UTC 25
Finished Feb 08 07:14:05 PM UTC 25
Peak memory 263204 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2385013520 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST
_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/alert_handler-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_ping_timeout.2385013520
Directory /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/5.alert_handler_ping_timeout/latest

Test location /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/cover_reg_top/0.alert_handler_csr_rw.3580462500
Short name T209
Test name
Test status
Simulation time 1153555461 ps
CPU time 14.9 seconds
Started Feb 09 03:22:47 AM UTC 25
Finished Feb 09 03:23:03 AM UTC 25
Peak memory 251996 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3580462500 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=al
ert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_csr_rw.3580462500
Directory /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/0.alert_handler_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/cover_reg_top/7.alert_handler_shadow_reg_errors.2638061363
Short name T164
Test name
Test status
Simulation time 7552010114 ps
CPU time 335.84 seconds
Started Feb 09 03:33:38 AM UTC 25
Finished Feb 09 03:39:19 AM UTC 25
Peak memory 279060 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2638061363 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +
UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/alert_handler-
sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.alert_handler_shadow_reg_errors.2638061363
Directory /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/7.alert_handler_shadow_reg_errors/latest

Test location /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default/13.alert_handler_lpg.2182957142
Short name T356
Test name
Test status
Simulation time 35517665387 ps
CPU time 2487.68 seconds
Started Feb 08 07:21:38 PM UTC 25
Finished Feb 08 08:03:33 PM UTC 25
Peak memory 302380 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2182957142 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST
_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_lpg.2182957142
Directory /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/13.alert_handler_lpg/latest

Test location /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default/6.alert_handler_entropy.31431296
Short name T82
Test name
Test status
Simulation time 39208749227 ps
CPU time 979.8 seconds
Started Feb 08 07:07:38 PM UTC 25
Finished Feb 08 07:24:09 PM UTC 25
Peak memory 285804 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=31431296 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_S
EQ=alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_entropy.31431296
Directory /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/6.alert_handler_entropy/latest

Test location /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/cover_reg_top/0.alert_handler_intr_test.1056680502
Short name T192
Test name
Test status
Simulation time 36320157 ps
CPU time 2.33 seconds
Started Feb 09 03:22:32 AM UTC 25
Finished Feb 09 03:22:36 AM UTC 25
Peak memory 249808 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1056680502 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert
_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/c
over_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_intr_test.1056680502
Directory /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/0.alert_handler_intr_test/latest

Test location /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default/27.alert_handler_lpg.2185055330
Short name T368
Test name
Test status
Simulation time 137388802931 ps
CPU time 2401.73 seconds
Started Feb 08 08:06:48 PM UTC 25
Finished Feb 08 08:47:17 PM UTC 25
Peak memory 288480 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2185055330 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST
_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_lpg.2185055330
Directory /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/27.alert_handler_lpg/latest

Test location /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/cover_reg_top/15.alert_handler_shadow_reg_errors.455239728
Short name T161
Test name
Test status
Simulation time 6595803632 ps
CPU time 196.63 seconds
Started Feb 09 03:38:12 AM UTC 25
Finished Feb 09 03:41:32 AM UTC 25
Peak memory 285412 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=455239728 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +U
VM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/alert_handler-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.alert_handler_shadow_reg_errors.455239728
Directory /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/15.alert_handler_shadow_reg_errors/latest

Test location /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default/3.alert_handler_sig_int_fail.972102788
Short name T54
Test name
Test status
Simulation time 1314590970 ps
CPU time 42.71 seconds
Started Feb 08 07:05:32 PM UTC 25
Finished Feb 08 07:06:17 PM UTC 25
Peak memory 263340 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo
/hw/dv/tools/sim.tcl +ntb_random_seed=972102788 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default.vdb -cm_l
og /dev/null -cm_name 3.alert_handler_sig_int_fail.972102788
Directory /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/3.alert_handler_sig_int_fail/latest

Test location /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default/0.alert_handler_ping_timeout.3231488448
Short name T18
Test name
Test status
Simulation time 16828371928 ps
CPU time 339.62 seconds
Started Feb 08 07:04:38 PM UTC 25
Finished Feb 08 07:10:22 PM UTC 25
Peak memory 269348 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3231488448 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST
_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/alert_handler-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_ping_timeout.3231488448
Directory /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/0.alert_handler_ping_timeout/latest

Test location /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/cover_reg_top/11.alert_handler_shadow_reg_errors_with_csr_rw.1541792121
Short name T401
Test name
Test status
Simulation time 110497064727 ps
CPU time 1103.06 seconds
Started Feb 09 03:35:58 AM UTC 25
Finished Feb 09 03:54:34 AM UTC 25
Peak memory 279260 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_sc
b=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1541792121 -assert nopostpro
c +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.alert_handler_shadow_reg_errors_with_csr
_rw.1541792121
Directory /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/11.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default/5.alert_handler_esc_intr_timeout.2473842387
Short name T93
Test name
Test status
Simulation time 666620246 ps
CPU time 43.88 seconds
Started Feb 08 07:06:47 PM UTC 25
Finished Feb 08 07:07:33 PM UTC 25
Peak memory 263144 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo
/hw/dv/tools/sim.tcl +ntb_random_seed=2473842387 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_tim
eout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 5.alert_handler_esc_intr_timeout.2473842387
Directory /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/5.alert_handler_esc_intr_timeout/latest

Test location /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default/7.alert_handler_ping_timeout.3087961408
Short name T286
Test name
Test status
Simulation time 24187058123 ps
CPU time 465.57 seconds
Started Feb 08 07:08:23 PM UTC 25
Finished Feb 08 07:16:14 PM UTC 25
Peak memory 263204 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3087961408 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST
_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/alert_handler-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_ping_timeout.3087961408
Directory /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/7.alert_handler_ping_timeout/latest

Test location /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default/8.alert_handler_lpg.3886773813
Short name T287
Test name
Test status
Simulation time 178174603240 ps
CPU time 2346.88 seconds
Started Feb 08 07:09:45 PM UTC 25
Finished Feb 08 07:49:20 PM UTC 25
Peak memory 285800 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3886773813 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST
_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_lpg.3886773813
Directory /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/8.alert_handler_lpg/latest

Test location /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/cover_reg_top/3.alert_handler_tl_intg_err.1330570225
Short name T207
Test name
Test status
Simulation time 9768093692 ps
CPU time 107.97 seconds
Started Feb 09 03:29:41 AM UTC 25
Finished Feb 09 03:31:31 AM UTC 25
Peak memory 252248 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1330570225 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TE
ST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/alert_handler-sim-vc
s/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_tl_intg_err.1330570225
Directory /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/3.alert_handler_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/cover_reg_top/12.alert_handler_shadow_reg_errors_with_csr_rw.1995309616
Short name T188
Test name
Test status
Simulation time 5062694443 ps
CPU time 832.85 seconds
Started Feb 09 03:36:29 AM UTC 25
Finished Feb 09 03:50:32 AM UTC 25
Peak memory 279196 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_sc
b=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1995309616 -assert nopostpro
c +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.alert_handler_shadow_reg_errors_with_csr
_rw.1995309616
Directory /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/12.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default/3.alert_handler_random_classes.4079292147
Short name T53
Test name
Test status
Simulation time 6209546860 ps
CPU time 36.66 seconds
Started Feb 08 07:05:26 PM UTC 25
Finished Feb 08 07:06:04 PM UTC 25
Peak memory 269344 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo
/hw/dv/tools/sim.tcl +ntb_random_seed=4079292147 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_class
es_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default.vdb -c
m_log /dev/null -cm_name 3.alert_handler_random_classes.4079292147
Directory /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/3.alert_handler_random_classes/latest

Test location /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default/15.alert_handler_ping_timeout.2228496701
Short name T276
Test name
Test status
Simulation time 52764457370 ps
CPU time 674.81 seconds
Started Feb 08 07:28:14 PM UTC 25
Finished Feb 08 07:39:37 PM UTC 25
Peak memory 263200 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2228496701 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST
_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/alert_handler-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_ping_timeout.2228496701
Directory /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/15.alert_handler_ping_timeout/latest

Test location /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default/13.alert_handler_stress_all.3396832702
Short name T124
Test name
Test status
Simulation time 59274306180 ps
CPU time 2265.41 seconds
Started Feb 08 07:21:59 PM UTC 25
Finished Feb 08 08:00:10 PM UTC 25
Peak memory 300364 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3396832702 -assert nopostproc +UVM_TESTNAME=ale
rt_handler_base_test +UVM_TEST_SEQ=alert_handler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os
_regression/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_stress_all.3396832702
Directory /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/13.alert_handler_stress_all/latest

Test location /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default/5.alert_handler_entropy.3767551428
Short name T65
Test name
Test status
Simulation time 33114458147 ps
CPU time 2178.08 seconds
Started Feb 08 07:06:56 PM UTC 25
Finished Feb 08 07:43:39 PM UTC 25
Peak memory 285996 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3767551428 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST
_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_entropy.3767551428
Directory /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/5.alert_handler_entropy/latest

Test location /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/cover_reg_top/15.alert_handler_shadow_reg_errors_with_csr_rw.1128587009
Short name T179
Test name
Test status
Simulation time 4585249161 ps
CPU time 405.85 seconds
Started Feb 09 03:38:08 AM UTC 25
Finished Feb 09 03:44:59 AM UTC 25
Peak memory 279060 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_sc
b=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1128587009 -assert nopostpro
c +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.alert_handler_shadow_reg_errors_with_csr
_rw.1128587009
Directory /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/15.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default/0.alert_handler_stress_all_with_rand_reset.4001665906
Short name T298
Test name
Test status
Simulation time 358456971378 ps
CPU time 7140.48 seconds
Started Feb 08 07:04:38 PM UTC 25
Finished Feb 08 09:04:58 PM UTC 25
Peak memory 337388 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=ale
rt_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=40016
65906 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_stress_all
_with_rand_reset.4001665906
Directory /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/0.alert_handler_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default/15.alert_handler_lpg.1727670724
Short name T375
Test name
Test status
Simulation time 33714238512 ps
CPU time 2708.4 seconds
Started Feb 08 07:28:22 PM UTC 25
Finished Feb 08 08:14:02 PM UTC 25
Peak memory 295972 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1727670724 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST
_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_lpg.1727670724
Directory /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/15.alert_handler_lpg/latest

Test location /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default/1.alert_handler_ping_timeout.77048936
Short name T16
Test name
Test status
Simulation time 15871298606 ps
CPU time 244.95 seconds
Started Feb 08 07:04:40 PM UTC 25
Finished Feb 08 07:08:48 PM UTC 25
Peak memory 263272 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=77048936 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_S
EQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/alert_handler-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_ping_timeout.77048936
Directory /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/1.alert_handler_ping_timeout/latest

Test location /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default/1.alert_handler_esc_alert_accum.657898410
Short name T147
Test name
Test status
Simulation time 2003007759 ps
CPU time 208.83 seconds
Started Feb 08 07:04:39 PM UTC 25
Finished Feb 08 07:08:11 PM UTC 25
Peak memory 269292 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo
/hw/dv/tools/sim.tcl +ntb_random_seed=657898410 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_acc
um_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default.vdb -c
m_log /dev/null -cm_name 1.alert_handler_esc_alert_accum.657898410
Directory /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/1.alert_handler_esc_alert_accum/latest

Test location /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/cover_reg_top/4.alert_handler_shadow_reg_errors.3585781276
Short name T160
Test name
Test status
Simulation time 13313117765 ps
CPU time 286.97 seconds
Started Feb 09 03:30:30 AM UTC 25
Finished Feb 09 03:35:21 AM UTC 25
Peak memory 279064 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3585781276 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +
UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/alert_handler-
sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_shadow_reg_errors.3585781276
Directory /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/4.alert_handler_shadow_reg_errors/latest

Test location /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/cover_reg_top/4.alert_handler_intr_test.476274876
Short name T388
Test name
Test status
Simulation time 12605523 ps
CPU time 2.49 seconds
Started Feb 09 03:31:23 AM UTC 25
Finished Feb 09 03:31:27 AM UTC 25
Peak memory 249808 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=476274876 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_
handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/co
ver_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_intr_test.476274876
Directory /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/4.alert_handler_intr_test/latest

Test location /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default/49.alert_handler_stress_all_with_rand_reset.2090374611
Short name T225
Test name
Test status
Simulation time 1125046182758 ps
CPU time 10684.1 seconds
Started Feb 08 09:16:45 PM UTC 25
Finished Feb 09 12:16:42 AM UTC 25
Peak memory 419684 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=ale
rt_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=20903
74611 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_stress_al
l_with_rand_reset.2090374611
Directory /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/49.alert_handler_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/cover_reg_top/19.alert_handler_shadow_reg_errors_with_csr_rw.395176462
Short name T399
Test name
Test status
Simulation time 7548342278 ps
CPU time 456.93 seconds
Started Feb 09 03:40:17 AM UTC 25
Finished Feb 09 03:48:00 AM UTC 25
Peak memory 279200 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_sc
b=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=395176462 -assert nopostproc
+UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r
epo/scratch/os_regression/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.alert_handler_shadow_reg_errors_with_csr_rw.395176462
Directory /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/19.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default/18.alert_handler_ping_timeout.1710771812
Short name T349
Test name
Test status
Simulation time 60953968117 ps
CPU time 549.29 seconds
Started Feb 08 07:39:37 PM UTC 25
Finished Feb 08 07:48:53 PM UTC 25
Peak memory 269356 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1710771812 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST
_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/alert_handler-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_ping_timeout.1710771812
Directory /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/18.alert_handler_ping_timeout/latest

Test location /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default/31.alert_handler_lpg.3784092587
Short name T386
Test name
Test status
Simulation time 41240450186 ps
CPU time 2789.65 seconds
Started Feb 08 08:18:13 PM UTC 25
Finished Feb 08 09:05:14 PM UTC 25
Peak memory 304936 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3784092587 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST
_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_lpg.3784092587
Directory /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/31.alert_handler_lpg/latest

Test location /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default/1.alert_handler_sig_int_fail.4226421954
Short name T51
Test name
Test status
Simulation time 6653510415 ps
CPU time 74.56 seconds
Started Feb 08 07:04:39 PM UTC 25
Finished Feb 08 07:05:55 PM UTC 25
Peak memory 263204 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo
/hw/dv/tools/sim.tcl +ntb_random_seed=4226421954 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default.vdb -cm_
log /dev/null -cm_name 1.alert_handler_sig_int_fail.4226421954
Directory /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/1.alert_handler_sig_int_fail/latest

Test location /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default/10.alert_handler_stress_all.754757108
Short name T140
Test name
Test status
Simulation time 633903693438 ps
CPU time 3107.35 seconds
Started Feb 08 07:13:49 PM UTC 25
Finished Feb 08 08:06:09 PM UTC 25
Peak memory 315112 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=754757108 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_
regression/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_stress_all.754757108
Directory /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/10.alert_handler_stress_all/latest

Test location /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default/30.alert_handler_ping_timeout.3799127738
Short name T358
Test name
Test status
Simulation time 15719638591 ps
CPU time 593.13 seconds
Started Feb 08 08:14:45 PM UTC 25
Finished Feb 08 08:24:45 PM UTC 25
Peak memory 263192 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3799127738 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST
_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/alert_handler-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_ping_timeout.3799127738
Directory /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/30.alert_handler_ping_timeout/latest

Test location /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/cover_reg_top/3.alert_handler_shadow_reg_errors_with_csr_rw.2388421766
Short name T170
Test name
Test status
Simulation time 6416446085 ps
CPU time 446.63 seconds
Started Feb 09 03:29:00 AM UTC 25
Finished Feb 09 03:36:32 AM UTC 25
Peak memory 279136 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_sc
b=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2388421766 -assert nopostpro
c +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_shadow_reg_errors_with_csr_
rw.2388421766
Directory /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/3.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default/47.alert_handler_lpg_stub_clk.2143638527
Short name T44
Test name
Test status
Simulation time 10259891870 ps
CPU time 900.22 seconds
Started Feb 08 09:11:16 PM UTC 25
Finished Feb 08 09:26:27 PM UTC 25
Peak memory 285992 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2143638527 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST
_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/alert_handler-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_lpg_stub_clk.2143638527
Directory /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/47.alert_handler_lpg_stub_clk/latest

Test location /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default/11.alert_handler_sig_int_fail.3467986191
Short name T100
Test name
Test status
Simulation time 199436272 ps
CPU time 24.83 seconds
Started Feb 08 07:15:20 PM UTC 25
Finished Feb 08 07:15:46 PM UTC 25
Peak memory 269552 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo
/hw/dv/tools/sim.tcl +ntb_random_seed=3467986191 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default.vdb -cm_
log /dev/null -cm_name 11.alert_handler_sig_int_fail.3467986191
Directory /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/11.alert_handler_sig_int_fail/latest

Test location /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default/29.alert_handler_lpg.2327509201
Short name T380
Test name
Test status
Simulation time 43728515315 ps
CPU time 3059.23 seconds
Started Feb 08 08:11:41 PM UTC 25
Finished Feb 08 09:03:13 PM UTC 25
Peak memory 305128 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2327509201 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST
_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_lpg.2327509201
Directory /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/29.alert_handler_lpg/latest

Test location /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default/40.alert_handler_lpg.551712683
Short name T697
Test name
Test status
Simulation time 467200481612 ps
CPU time 2950.06 seconds
Started Feb 08 08:48:00 PM UTC 25
Finished Feb 08 09:37:42 PM UTC 25
Peak memory 305196 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=551712683 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_
SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/cove
rage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_lpg.551712683
Directory /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/40.alert_handler_lpg/latest

Test location /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/cover_reg_top/6.alert_handler_shadow_reg_errors_with_csr_rw.3212557114
Short name T172
Test name
Test status
Simulation time 9423512529 ps
CPU time 488.71 seconds
Started Feb 09 03:32:42 AM UTC 25
Finished Feb 09 03:40:58 AM UTC 25
Peak memory 281184 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_sc
b=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3212557114 -assert nopostpro
c +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.alert_handler_shadow_reg_errors_with_csr_
rw.3212557114
Directory /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/6.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default/0.alert_handler_alert_accum_saturation.1383951617
Short name T1
Test name
Test status
Simulation time 37764779 ps
CPU time 3.4 seconds
Started Feb 08 07:04:38 PM UTC 25
Finished Feb 08 07:04:43 PM UTC 25
Peak memory 263472 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
paces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1383951617 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_al
ert_accum_saturation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/cover
age/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_alert_accum_saturation.1383951617
Directory /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/0.alert_handler_alert_accum_saturation/latest

Test location /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default/1.alert_handler_alert_accum_saturation.693509140
Short name T3
Test name
Test status
Simulation time 69142652 ps
CPU time 3.66 seconds
Started Feb 08 07:04:45 PM UTC 25
Finished Feb 08 07:04:50 PM UTC 25
Peak memory 263432 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
paces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=693509140 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ale
rt_accum_saturation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/covera
ge/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_alert_accum_saturation.693509140
Directory /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/1.alert_handler_alert_accum_saturation/latest

Test location /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default/12.alert_handler_alert_accum_saturation.3263390973
Short name T256
Test name
Test status
Simulation time 24168640 ps
CPU time 4.09 seconds
Started Feb 08 07:19:40 PM UTC 25
Finished Feb 08 07:19:45 PM UTC 25
Peak memory 263624 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
paces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3263390973 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_al
ert_accum_saturation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/cover
age/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_alert_accum_saturation.3263390973
Directory /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/12.alert_handler_alert_accum_saturation/latest

Test location /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default/13.alert_handler_alert_accum_saturation.643182292
Short name T77
Test name
Test status
Simulation time 445366763 ps
CPU time 6.41 seconds
Started Feb 08 07:22:09 PM UTC 25
Finished Feb 08 07:22:16 PM UTC 25
Peak memory 263408 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
paces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=643182292 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ale
rt_accum_saturation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/covera
ge/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_alert_accum_saturation.643182292
Directory /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/13.alert_handler_alert_accum_saturation/latest

Test location /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default/0.alert_handler_random_classes.2011048438
Short name T2
Test name
Test status
Simulation time 63664784 ps
CPU time 7.2 seconds
Started Feb 08 07:04:35 PM UTC 25
Finished Feb 08 07:04:44 PM UTC 25
Peak memory 267496 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo
/hw/dv/tools/sim.tcl +ntb_random_seed=2011048438 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_class
es_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default.vdb -c
m_log /dev/null -cm_name 0.alert_handler_random_classes.2011048438
Directory /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/0.alert_handler_random_classes/latest

Test location /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default/20.alert_handler_stress_all_with_rand_reset.496218726
Short name T74
Test name
Test status
Simulation time 300596113077 ps
CPU time 5876.11 seconds
Started Feb 08 07:49:10 PM UTC 25
Finished Feb 08 09:28:09 PM UTC 25
Peak memory 335788 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=ale
rt_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=49621
8726 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_stress_all
_with_rand_reset.496218726
Directory /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/20.alert_handler_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default/21.alert_handler_ping_timeout.1974809921
Short name T290
Test name
Test status
Simulation time 103594102635 ps
CPU time 394.46 seconds
Started Feb 08 07:51:13 PM UTC 25
Finished Feb 08 07:57:52 PM UTC 25
Peak memory 263192 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1974809921 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST
_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/alert_handler-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_ping_timeout.1974809921
Directory /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/21.alert_handler_ping_timeout/latest

Test location /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default/41.alert_handler_smoke.1904834092
Short name T284
Test name
Test status
Simulation time 2915073572 ps
CPU time 66.22 seconds
Started Feb 08 08:49:28 PM UTC 25
Finished Feb 08 08:50:36 PM UTC 25
Peak memory 269608 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo
/hw/dv/tools/sim.tcl +ntb_random_seed=1904834092 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default.vdb -cm_log /de
v/null -cm_name 41.alert_handler_smoke.1904834092
Directory /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/41.alert_handler_smoke/latest

Test location /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default/6.alert_handler_esc_alert_accum.2129308496
Short name T304
Test name
Test status
Simulation time 6016477721 ps
CPU time 458.25 seconds
Started Feb 08 07:07:34 PM UTC 25
Finished Feb 08 07:15:19 PM UTC 25
Peak memory 269420 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo
/hw/dv/tools/sim.tcl +ntb_random_seed=2129308496 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_ac
cum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 6.alert_handler_esc_alert_accum.2129308496
Directory /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/6.alert_handler_esc_alert_accum/latest

Test location /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default/6.alert_handler_ping_timeout.835300936
Short name T344
Test name
Test status
Simulation time 6184263736 ps
CPU time 318.34 seconds
Started Feb 08 07:07:44 PM UTC 25
Finished Feb 08 07:13:07 PM UTC 25
Peak memory 263196 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=835300936 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_
SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/alert_handler-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_ping_timeout.835300936
Directory /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/6.alert_handler_ping_timeout/latest

Test location /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/cover_reg_top/16.alert_handler_tl_intg_err.1302021312
Short name T199
Test name
Test status
Simulation time 140458237 ps
CPU time 10.7 seconds
Started Feb 09 03:39:08 AM UTC 25
Finished Feb 09 03:39:19 AM UTC 25
Peak memory 250068 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1302021312 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TE
ST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/alert_handler-sim-vc
s/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.alert_handler_tl_intg_err.1302021312
Directory /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/16.alert_handler_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/cover_reg_top/0.alert_handler_csr_aliasing.33777071
Short name T228
Test name
Test status
Simulation time 1136382229 ps
CPU time 209.97 seconds
Started Feb 09 03:23:04 AM UTC 25
Finished Feb 09 03:26:37 AM UTC 25
Peak memory 251916 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=33777071 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SE
Q=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/cov
erage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_csr_aliasing.33777071
Directory /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/0.alert_handler_csr_aliasing/latest

Test location /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default/42.alert_handler_stress_all_with_rand_reset.2849268624
Short name T324
Test name
Test status
Simulation time 51566693253 ps
CPU time 2919.33 seconds
Started Feb 08 08:53:56 PM UTC 25
Finished Feb 08 09:43:11 PM UTC 25
Peak memory 300900 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=ale
rt_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=28492
68624 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_stress_al
l_with_rand_reset.2849268624
Directory /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/42.alert_handler_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/cover_reg_top/9.alert_handler_tl_intg_err.3044649095
Short name T196
Test name
Test status
Simulation time 783013084 ps
CPU time 43.39 seconds
Started Feb 09 03:35:21 AM UTC 25
Finished Feb 09 03:36:06 AM UTC 25
Peak memory 249944 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3044649095 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TE
ST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/alert_handler-sim-vc
s/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.alert_handler_tl_intg_err.3044649095
Directory /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/9.alert_handler_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/cover_reg_top/18.alert_handler_shadow_reg_errors.1319045291
Short name T162
Test name
Test status
Simulation time 22567297969 ps
CPU time 167.94 seconds
Started Feb 09 03:39:55 AM UTC 25
Finished Feb 09 03:42:46 AM UTC 25
Peak memory 279144 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1319045291 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +
UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/alert_handler-
sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.alert_handler_shadow_reg_errors.1319045291
Directory /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/18.alert_handler_shadow_reg_errors/latest

Test location /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/cover_reg_top/10.alert_handler_intr_test.1574982922
Short name T744
Test name
Test status
Simulation time 29444561 ps
CPU time 2.22 seconds
Started Feb 09 03:35:46 AM UTC 25
Finished Feb 09 03:35:49 AM UTC 25
Peak memory 250016 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1574982922 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert
_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/c
over_reg_top.vdb -cm_log /dev/null -cm_name 10.alert_handler_intr_test.1574982922
Directory /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/10.alert_handler_intr_test/latest

Test location /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default/13.alert_handler_random_classes.489135062
Short name T282
Test name
Test status
Simulation time 2597479331 ps
CPU time 60.21 seconds
Started Feb 08 07:20:39 PM UTC 25
Finished Feb 08 07:21:41 PM UTC 25
Peak memory 263212 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo
/hw/dv/tools/sim.tcl +ntb_random_seed=489135062 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classe
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default.vdb -cm
_log /dev/null -cm_name 13.alert_handler_random_classes.489135062
Directory /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/13.alert_handler_random_classes/latest

Test location /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default/14.alert_handler_smoke.3689422860
Short name T84
Test name
Test status
Simulation time 1257280453 ps
CPU time 110.13 seconds
Started Feb 08 07:23:29 PM UTC 25
Finished Feb 08 07:25:22 PM UTC 25
Peak memory 269352 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo
/hw/dv/tools/sim.tcl +ntb_random_seed=3689422860 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default.vdb -cm_log /de
v/null -cm_name 14.alert_handler_smoke.3689422860
Directory /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/14.alert_handler_smoke/latest

Test location /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default/19.alert_handler_sig_int_fail.57473960
Short name T318
Test name
Test status
Simulation time 2146728350 ps
CPU time 102.58 seconds
Started Feb 08 07:42:38 PM UTC 25
Finished Feb 08 07:44:23 PM UTC 25
Peak memory 269544 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo
/hw/dv/tools/sim.tcl +ntb_random_seed=57473960 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default.vdb -cm_lo
g /dev/null -cm_name 19.alert_handler_sig_int_fail.57473960
Directory /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/19.alert_handler_sig_int_fail/latest

Test location /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default/2.alert_handler_lpg.605785464
Short name T354
Test name
Test status
Simulation time 188417828202 ps
CPU time 3311.87 seconds
Started Feb 08 07:05:07 PM UTC 25
Finished Feb 08 08:00:55 PM UTC 25
Peak memory 298984 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=605785464 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_
SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/cove
rage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_lpg.605785464
Directory /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/2.alert_handler_lpg/latest

Test location /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default/20.alert_handler_ping_timeout.853293919
Short name T308
Test name
Test status
Simulation time 15299670177 ps
CPU time 343.95 seconds
Started Feb 08 07:47:59 PM UTC 25
Finished Feb 08 07:53:48 PM UTC 25
Peak memory 263200 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=853293919 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_
SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/alert_handler-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_ping_timeout.853293919
Directory /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/20.alert_handler_ping_timeout/latest

Test location /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default/20.alert_handler_sig_int_fail.4202527237
Short name T319
Test name
Test status
Simulation time 1558804441 ps
CPU time 83.34 seconds
Started Feb 08 07:47:38 PM UTC 25
Finished Feb 08 07:49:03 PM UTC 25
Peak memory 269360 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo
/hw/dv/tools/sim.tcl +ntb_random_seed=4202527237 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default.vdb -cm_
log /dev/null -cm_name 20.alert_handler_sig_int_fail.4202527237
Directory /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/20.alert_handler_sig_int_fail/latest

Test location /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default/21.alert_handler_random_classes.2745377550
Short name T105
Test name
Test status
Simulation time 447067127 ps
CPU time 27.42 seconds
Started Feb 08 07:50:09 PM UTC 25
Finished Feb 08 07:50:38 PM UTC 25
Peak memory 269548 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo
/hw/dv/tools/sim.tcl +ntb_random_seed=2745377550 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_class
es_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default.vdb -c
m_log /dev/null -cm_name 21.alert_handler_random_classes.2745377550
Directory /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/21.alert_handler_random_classes/latest

Test location /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default/21.alert_handler_sig_int_fail.1425336438
Short name T321
Test name
Test status
Simulation time 1304360747 ps
CPU time 82.2 seconds
Started Feb 08 07:50:39 PM UTC 25
Finished Feb 08 07:52:03 PM UTC 25
Peak memory 269552 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo
/hw/dv/tools/sim.tcl +ntb_random_seed=1425336438 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default.vdb -cm_
log /dev/null -cm_name 21.alert_handler_sig_int_fail.1425336438
Directory /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/21.alert_handler_sig_int_fail/latest

Test location /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default/27.alert_handler_stress_all_with_rand_reset.2841855368
Short name T247
Test name
Test status
Simulation time 275411357894 ps
CPU time 6072.75 seconds
Started Feb 08 08:07:30 PM UTC 25
Finished Feb 08 09:49:49 PM UTC 25
Peak memory 354144 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=ale
rt_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=28418
55368 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_stress_al
l_with_rand_reset.2841855368
Directory /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/27.alert_handler_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default/28.alert_handler_sig_int_fail.2770149055
Short name T322
Test name
Test status
Simulation time 270079312 ps
CPU time 25.56 seconds
Started Feb 08 08:08:47 PM UTC 25
Finished Feb 08 08:09:14 PM UTC 25
Peak memory 263144 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo
/hw/dv/tools/sim.tcl +ntb_random_seed=2770149055 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default.vdb -cm_
log /dev/null -cm_name 28.alert_handler_sig_int_fail.2770149055
Directory /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/28.alert_handler_sig_int_fail/latest

Test location /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default/29.alert_handler_stress_all_with_rand_reset.1571298483
Short name T330
Test name
Test status
Simulation time 24851182379 ps
CPU time 3246.02 seconds
Started Feb 08 08:12:40 PM UTC 25
Finished Feb 08 09:07:23 PM UTC 25
Peak memory 337764 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=ale
rt_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=15712
98483 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_stress_al
l_with_rand_reset.1571298483
Directory /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/29.alert_handler_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default/30.alert_handler_stress_all_with_rand_reset.1624826967
Short name T215
Test name
Test status
Simulation time 16837680180 ps
CPU time 1262.72 seconds
Started Feb 08 08:16:05 PM UTC 25
Finished Feb 08 08:37:22 PM UTC 25
Peak memory 296100 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=ale
rt_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=16248
26967 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_stress_al
l_with_rand_reset.1624826967
Directory /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/30.alert_handler_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default/31.alert_handler_stress_all.3830935056
Short name T73
Test name
Test status
Simulation time 863855519485 ps
CPU time 3240.61 seconds
Started Feb 08 08:18:25 PM UTC 25
Finished Feb 08 09:13:01 PM UTC 25
Peak memory 304868 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3830935056 -assert nopostproc +UVM_TESTNAME=ale
rt_handler_base_test +UVM_TEST_SEQ=alert_handler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os
_regression/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_stress_all.3830935056
Directory /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/31.alert_handler_stress_all/latest

Test location /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default/32.alert_handler_stress_all.2278908410
Short name T302
Test name
Test status
Simulation time 16734059617 ps
CPU time 983.83 seconds
Started Feb 08 08:20:37 PM UTC 25
Finished Feb 08 08:37:11 PM UTC 25
Peak memory 279664 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2278908410 -assert nopostproc +UVM_TESTNAME=ale
rt_handler_base_test +UVM_TEST_SEQ=alert_handler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os
_regression/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_stress_all.2278908410
Directory /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/32.alert_handler_stress_all/latest

Test location /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default/34.alert_handler_sig_int_fail.1990298888
Short name T317
Test name
Test status
Simulation time 8640732247 ps
CPU time 72.26 seconds
Started Feb 08 08:27:35 PM UTC 25
Finished Feb 08 08:28:50 PM UTC 25
Peak memory 263212 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo
/hw/dv/tools/sim.tcl +ntb_random_seed=1990298888 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default.vdb -cm_
log /dev/null -cm_name 34.alert_handler_sig_int_fail.1990298888
Directory /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/34.alert_handler_sig_int_fail/latest

Test location /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default/40.alert_handler_stress_all.3338633197
Short name T314
Test name
Test status
Simulation time 66419332910 ps
CPU time 409.2 seconds
Started Feb 08 08:48:36 PM UTC 25
Finished Feb 08 08:55:30 PM UTC 25
Peak memory 279588 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3338633197 -assert nopostproc +UVM_TESTNAME=ale
rt_handler_base_test +UVM_TEST_SEQ=alert_handler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os
_regression/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_stress_all.3338633197
Directory /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/40.alert_handler_stress_all/latest

Test location /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/cover_reg_top/0.alert_handler_shadow_reg_errors.2430120230
Short name T156
Test name
Test status
Simulation time 1599579295 ps
CPU time 103.24 seconds
Started Feb 09 03:20:35 AM UTC 25
Finished Feb 09 03:22:20 AM UTC 25
Peak memory 269024 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2430120230 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +
UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/alert_handler-
sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_shadow_reg_errors.2430120230
Directory /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/0.alert_handler_shadow_reg_errors/latest

Test location /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/cover_reg_top/12.alert_handler_shadow_reg_errors.1213461724
Short name T181
Test name
Test status
Simulation time 10349496005 ps
CPU time 371.61 seconds
Started Feb 09 03:36:34 AM UTC 25
Finished Feb 09 03:42:50 AM UTC 25
Peak memory 285212 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1213461724 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +
UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/alert_handler-
sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.alert_handler_shadow_reg_errors.1213461724
Directory /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/12.alert_handler_shadow_reg_errors/latest

Test location /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/cover_reg_top/15.alert_handler_tl_intg_err.1165235985
Short name T204
Test name
Test status
Simulation time 931895643 ps
CPU time 80.51 seconds
Started Feb 09 03:38:22 AM UTC 25
Finished Feb 09 03:39:45 AM UTC 25
Peak memory 260108 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1165235985 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TE
ST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/alert_handler-sim-vc
s/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.alert_handler_tl_intg_err.1165235985
Directory /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/15.alert_handler_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/cover_reg_top/4.alert_handler_tl_intg_err.1668284691
Short name T200
Test name
Test status
Simulation time 318735181 ps
CPU time 61.33 seconds
Started Feb 09 03:30:53 AM UTC 25
Finished Feb 09 03:31:56 AM UTC 25
Peak memory 252120 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1668284691 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TE
ST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/alert_handler-sim-vc
s/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_tl_intg_err.1668284691
Directory /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/4.alert_handler_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/cover_reg_top/6.alert_handler_tl_intg_err.3543979732
Short name T197
Test name
Test status
Simulation time 107205271 ps
CPU time 6.41 seconds
Started Feb 09 03:33:11 AM UTC 25
Finished Feb 09 03:33:18 AM UTC 25
Peak memory 249872 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3543979732 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TE
ST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/alert_handler-sim-vc
s/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.alert_handler_tl_intg_err.3543979732
Directory /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/6.alert_handler_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/cover_reg_top/11.alert_handler_shadow_reg_errors.3181939118
Short name T168
Test name
Test status
Simulation time 6042661171 ps
CPU time 225.07 seconds
Started Feb 09 03:36:04 AM UTC 25
Finished Feb 09 03:39:52 AM UTC 25
Peak memory 285416 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3181939118 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +
UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/alert_handler-
sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.alert_handler_shadow_reg_errors.3181939118
Directory /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/11.alert_handler_shadow_reg_errors/latest

Test location /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/cover_reg_top/11.alert_handler_tl_intg_err.3430615210
Short name T206
Test name
Test status
Simulation time 97613997 ps
CPU time 4.06 seconds
Started Feb 09 03:36:11 AM UTC 25
Finished Feb 09 03:36:16 AM UTC 25
Peak memory 250068 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3430615210 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TE
ST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/alert_handler-sim-vc
s/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.alert_handler_tl_intg_err.3430615210
Directory /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/11.alert_handler_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/cover_reg_top/14.alert_handler_shadow_reg_errors.3879296656
Short name T180
Test name
Test status
Simulation time 28598800241 ps
CPU time 372.41 seconds
Started Feb 09 03:37:55 AM UTC 25
Finished Feb 09 03:44:12 AM UTC 25
Peak memory 279272 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3879296656 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +
UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/alert_handler-
sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.alert_handler_shadow_reg_errors.3879296656
Directory /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/14.alert_handler_shadow_reg_errors/latest

Test location /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/cover_reg_top/17.alert_handler_tl_intg_err.321674020
Short name T195
Test name
Test status
Simulation time 56439729 ps
CPU time 6.43 seconds
Started Feb 09 03:39:42 AM UTC 25
Finished Feb 09 03:39:50 AM UTC 25
Peak memory 250072 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=321674020 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TES
T_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs
/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.alert_handler_tl_intg_err.321674020
Directory /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/17.alert_handler_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/cover_reg_top/5.alert_handler_tl_intg_err.572739993
Short name T208
Test name
Test status
Simulation time 217412963 ps
CPU time 32.42 seconds
Started Feb 09 03:32:06 AM UTC 25
Finished Feb 09 03:32:40 AM UTC 25
Peak memory 262160 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=572739993 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TES
T_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs
/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.alert_handler_tl_intg_err.572739993
Directory /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/5.alert_handler_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/cover_reg_top/8.alert_handler_tl_intg_err.340627420
Short name T212
Test name
Test status
Simulation time 316659487 ps
CPU time 60.06 seconds
Started Feb 09 03:34:51 AM UTC 25
Finished Feb 09 03:35:53 AM UTC 25
Peak memory 251920 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=340627420 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TES
T_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs
/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.alert_handler_tl_intg_err.340627420
Directory /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/8.alert_handler_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/cover_reg_top/0.alert_handler_tl_intg_err.1175822331
Short name T189
Test name
Test status
Simulation time 96947447 ps
CPU time 3.78 seconds
Started Feb 09 03:22:26 AM UTC 25
Finished Feb 09 03:22:31 AM UTC 25
Peak memory 249868 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1175822331 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TE
ST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/alert_handler-sim-vc
s/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_tl_intg_err.1175822331
Directory /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/0.alert_handler_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/cover_reg_top/10.alert_handler_tl_intg_err.1741071884
Short name T205
Test name
Test status
Simulation time 461719619 ps
CPU time 35.14 seconds
Started Feb 09 03:35:40 AM UTC 25
Finished Feb 09 03:36:17 AM UTC 25
Peak memory 251868 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1741071884 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TE
ST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/alert_handler-sim-vc
s/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.alert_handler_tl_intg_err.1741071884
Directory /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/10.alert_handler_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/cover_reg_top/18.alert_handler_tl_intg_err.2016359868
Short name T202
Test name
Test status
Simulation time 2108123778 ps
CPU time 50.78 seconds
Started Feb 09 03:40:03 AM UTC 25
Finished Feb 09 03:40:55 AM UTC 25
Peak memory 251916 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2016359868 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TE
ST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/alert_handler-sim-vc
s/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.alert_handler_tl_intg_err.2016359868
Directory /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/18.alert_handler_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/cover_reg_top/19.alert_handler_tl_intg_err.3910684738
Short name T201
Test name
Test status
Simulation time 53760265 ps
CPU time 4.34 seconds
Started Feb 09 03:40:56 AM UTC 25
Finished Feb 09 03:41:01 AM UTC 25
Peak memory 250004 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3910684738 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TE
ST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/alert_handler-sim-vc
s/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.alert_handler_tl_intg_err.3910684738
Directory /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/19.alert_handler_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/cover_reg_top/7.alert_handler_tl_intg_err.1965379817
Short name T203
Test name
Test status
Simulation time 1230436643 ps
CPU time 115.56 seconds
Started Feb 09 03:34:16 AM UTC 25
Finished Feb 09 03:36:14 AM UTC 25
Peak memory 252056 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1965379817 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TE
ST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/alert_handler-sim-vc
s/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.alert_handler_tl_intg_err.1965379817
Directory /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/7.alert_handler_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default/35.alert_handler_stress_all_with_rand_reset.2175491305
Short name T46
Test name
Test status
Simulation time 27808066055 ps
CPU time 466.98 seconds
Started Feb 08 08:32:55 PM UTC 25
Finished Feb 08 08:40:48 PM UTC 25
Peak memory 282028 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=ale
rt_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=21754
91305 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_stress_al
l_with_rand_reset.2175491305
Directory /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/35.alert_handler_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/cover_reg_top/0.alert_handler_csr_bit_bash.3281555674
Short name T226
Test name
Test status
Simulation time 3271320473 ps
CPU time 154.71 seconds
Started Feb 09 03:22:47 AM UTC 25
Finished Feb 09 03:25:24 AM UTC 25
Peak memory 252056 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3281555674 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_
SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/c
overage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_csr_bit_bash.3281555674
Directory /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/0.alert_handler_csr_bit_bash/latest

Test location /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/cover_reg_top/0.alert_handler_csr_hw_reset.2840123201
Short name T193
Test name
Test status
Simulation time 206612647 ps
CPU time 8.41 seconds
Started Feb 09 03:22:36 AM UTC 25
Finished Feb 09 03:22:46 AM UTC 25
Peak memory 262360 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2840123201 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_
SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/c
overage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_csr_hw_reset.2840123201
Directory /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/0.alert_handler_csr_hw_reset/latest

Test location /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/cover_reg_top/0.alert_handler_csr_mem_rw_with_rand_reset.9820728
Short name T211
Test name
Test status
Simulation time 38547264 ps
CPU time 8.31 seconds
Started Feb 09 03:23:54 AM UTC 25
Finished Feb 09 03:24:03 AM UTC 25
Peak memory 268376 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=9820728 -assert nopostproc +UVM
_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s
cratch/os_regression/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_csr_mem_rw_with_rand_reset.9820728
Directory /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/0.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/cover_reg_top/0.alert_handler_same_csr_outstanding.2612370994
Short name T210
Test name
Test status
Simulation time 380339874 ps
CPU time 20.17 seconds
Started Feb 09 03:23:32 AM UTC 25
Finished Feb 09 03:23:53 AM UTC 25
Peak memory 260320 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2612370994 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/alert_handl
er-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_same_csr_outstanding.2612370994
Directory /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/0.alert_handler_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/cover_reg_top/0.alert_handler_shadow_reg_errors_with_csr_rw.2648294968
Short name T169
Test name
Test status
Simulation time 30340624241 ps
CPU time 760.15 seconds
Started Feb 09 03:20:20 AM UTC 25
Finished Feb 09 03:33:10 AM UTC 25
Peak memory 279060 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_sc
b=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2648294968 -assert nopostpro
c +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_shadow_reg_errors_with_csr_
rw.2648294968
Directory /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/0.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/cover_reg_top/0.alert_handler_tl_errors.3458666861
Short name T712
Test name
Test status
Simulation time 508907245 ps
CPU time 23.47 seconds
Started Feb 09 03:22:21 AM UTC 25
Finished Feb 09 03:22:46 AM UTC 25
Peak memory 266392 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3458666861 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert
_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/c
over_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_tl_errors.3458666861
Directory /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/0.alert_handler_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/cover_reg_top/1.alert_handler_csr_aliasing.3287445970
Short name T402
Test name
Test status
Simulation time 4748641399 ps
CPU time 219.1 seconds
Started Feb 09 03:25:58 AM UTC 25
Finished Feb 09 03:29:41 AM UTC 25
Peak memory 249936 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3287445970 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_
SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/c
overage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_csr_aliasing.3287445970
Directory /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/1.alert_handler_csr_aliasing/latest

Test location /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/cover_reg_top/1.alert_handler_csr_bit_bash.3569530267
Short name T231
Test name
Test status
Simulation time 8899159531 ps
CPU time 209.87 seconds
Started Feb 09 03:25:56 AM UTC 25
Finished Feb 09 03:29:29 AM UTC 25
Peak memory 250136 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3569530267 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_
SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/c
overage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_csr_bit_bash.3569530267
Directory /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/1.alert_handler_csr_bit_bash/latest

Test location /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/cover_reg_top/1.alert_handler_csr_hw_reset.49398520
Short name T227
Test name
Test status
Simulation time 23779510 ps
CPU time 5.3 seconds
Started Feb 09 03:25:49 AM UTC 25
Finished Feb 09 03:25:55 AM UTC 25
Peak memory 251988 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=49398520 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SE
Q=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/cov
erage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_csr_hw_reset.49398520
Directory /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/1.alert_handler_csr_hw_reset/latest

Test location /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/cover_reg_top/1.alert_handler_csr_mem_rw_with_rand_reset.2378630352
Short name T250
Test name
Test status
Simulation time 256150569 ps
CPU time 14.18 seconds
Started Feb 09 03:26:38 AM UTC 25
Finished Feb 09 03:26:54 AM UTC 25
Peak memory 266316 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2378630352 -assert nopostproc +
UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep
o/scratch/os_regression/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_csr_mem_rw_with_rand_reset.2378630352
Directory /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/1.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/cover_reg_top/1.alert_handler_csr_rw.1064838239
Short name T233
Test name
Test status
Simulation time 36844041 ps
CPU time 4.14 seconds
Started Feb 09 03:25:52 AM UTC 25
Finished Feb 09 03:25:57 AM UTC 25
Peak memory 252188 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1064838239 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=al
ert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_csr_rw.1064838239
Directory /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/1.alert_handler_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/cover_reg_top/1.alert_handler_intr_test.3679706354
Short name T194
Test name
Test status
Simulation time 7284558 ps
CPU time 2.23 seconds
Started Feb 09 03:25:47 AM UTC 25
Finished Feb 09 03:25:51 AM UTC 25
Peak memory 250008 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3679706354 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert
_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/c
over_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_intr_test.3679706354
Directory /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/1.alert_handler_intr_test/latest

Test location /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/cover_reg_top/1.alert_handler_same_csr_outstanding.343126705
Short name T234
Test name
Test status
Simulation time 624754365 ps
CPU time 60.83 seconds
Started Feb 09 03:26:32 AM UTC 25
Finished Feb 09 03:27:35 AM UTC 25
Peak memory 260112 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=343126705 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test
+UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/alert_handle
r-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_same_csr_outstanding.343126705
Directory /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/1.alert_handler_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/cover_reg_top/1.alert_handler_shadow_reg_errors.2247911337
Short name T158
Test name
Test status
Simulation time 26981134462 ps
CPU time 360.27 seconds
Started Feb 09 03:24:24 AM UTC 25
Finished Feb 09 03:30:29 AM UTC 25
Peak memory 279064 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2247911337 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +
UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/alert_handler-
sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_shadow_reg_errors.2247911337
Directory /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/1.alert_handler_shadow_reg_errors/latest

Test location /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/cover_reg_top/1.alert_handler_shadow_reg_errors_with_csr_rw.3634540038
Short name T157
Test name
Test status
Simulation time 13786590555 ps
CPU time 276.58 seconds
Started Feb 09 03:24:04 AM UTC 25
Finished Feb 09 03:28:45 AM UTC 25
Peak memory 279060 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_sc
b=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3634540038 -assert nopostpro
c +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_shadow_reg_errors_with_csr_
rw.3634540038
Directory /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/1.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/cover_reg_top/1.alert_handler_tl_errors.113328214
Short name T713
Test name
Test status
Simulation time 757363860 ps
CPU time 20.33 seconds
Started Feb 09 03:25:25 AM UTC 25
Finished Feb 09 03:25:47 AM UTC 25
Peak memory 264344 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=113328214 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_
handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/co
ver_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_tl_errors.113328214
Directory /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/1.alert_handler_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/cover_reg_top/1.alert_handler_tl_intg_err.2014847680
Short name T190
Test name
Test status
Simulation time 114790794 ps
CPU time 4.83 seconds
Started Feb 09 03:25:41 AM UTC 25
Finished Feb 09 03:25:47 AM UTC 25
Peak memory 251916 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2014847680 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TE
ST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/alert_handler-sim-vc
s/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_tl_intg_err.2014847680
Directory /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/1.alert_handler_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/cover_reg_top/10.alert_handler_csr_mem_rw_with_rand_reset.1107672197
Short name T747
Test name
Test status
Simulation time 196793211 ps
CPU time 7.72 seconds
Started Feb 09 03:35:54 AM UTC 25
Finished Feb 09 03:36:03 AM UTC 25
Peak memory 251980 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1107672197 -assert nopostproc +
UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep
o/scratch/os_regression/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.alert_handler_csr_mem_rw_with_rand_reset.1107672197
Directory /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/10.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/cover_reg_top/10.alert_handler_csr_rw.1736627152
Short name T746
Test name
Test status
Simulation time 34582953 ps
CPU time 6.54 seconds
Started Feb 09 03:35:50 AM UTC 25
Finished Feb 09 03:35:57 AM UTC 25
Peak memory 251952 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1736627152 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=al
ert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.alert_handler_csr_rw.1736627152
Directory /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/10.alert_handler_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/cover_reg_top/10.alert_handler_same_csr_outstanding.752724685
Short name T752
Test name
Test status
Simulation time 2431168163 ps
CPU time 55.36 seconds
Started Feb 09 03:35:54 AM UTC 25
Finished Feb 09 03:36:51 AM UTC 25
Peak memory 260180 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=752724685 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test
+UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/alert_handle
r-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.alert_handler_same_csr_outstanding.752724685
Directory /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/10.alert_handler_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/cover_reg_top/10.alert_handler_shadow_reg_errors_with_csr_rw.3536369181
Short name T398
Test name
Test status
Simulation time 26604253448 ps
CPU time 499.44 seconds
Started Feb 09 03:35:31 AM UTC 25
Finished Feb 09 03:43:56 AM UTC 25
Peak memory 279056 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_sc
b=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3536369181 -assert nopostpro
c +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.alert_handler_shadow_reg_errors_with_csr
_rw.3536369181
Directory /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/10.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/cover_reg_top/10.alert_handler_tl_errors.559455307
Short name T745
Test name
Test status
Simulation time 344207865 ps
CPU time 11.98 seconds
Started Feb 09 03:35:40 AM UTC 25
Finished Feb 09 03:35:54 AM UTC 25
Peak memory 262208 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=559455307 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_
handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/co
ver_reg_top.vdb -cm_log /dev/null -cm_name 10.alert_handler_tl_errors.559455307
Directory /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/10.alert_handler_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/cover_reg_top/11.alert_handler_csr_mem_rw_with_rand_reset.1924795731
Short name T749
Test name
Test status
Simulation time 129077386 ps
CPU time 7.7 seconds
Started Feb 09 03:36:19 AM UTC 25
Finished Feb 09 03:36:28 AM UTC 25
Peak memory 262220 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1924795731 -assert nopostproc +
UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep
o/scratch/os_regression/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.alert_handler_csr_mem_rw_with_rand_reset.1924795731
Directory /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/11.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/cover_reg_top/11.alert_handler_csr_rw.1338579901
Short name T750
Test name
Test status
Simulation time 114107286 ps
CPU time 14.03 seconds
Started Feb 09 03:36:18 AM UTC 25
Finished Feb 09 03:36:33 AM UTC 25
Peak memory 249876 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1338579901 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=al
ert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.alert_handler_csr_rw.1338579901
Directory /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/11.alert_handler_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/cover_reg_top/11.alert_handler_intr_test.712124892
Short name T748
Test name
Test status
Simulation time 12007837 ps
CPU time 2.59 seconds
Started Feb 09 03:36:14 AM UTC 25
Finished Feb 09 03:36:18 AM UTC 25
Peak memory 250008 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=712124892 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_
handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/co
ver_reg_top.vdb -cm_log /dev/null -cm_name 11.alert_handler_intr_test.712124892
Directory /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/11.alert_handler_intr_test/latest

Test location /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/cover_reg_top/11.alert_handler_same_csr_outstanding.1843233894
Short name T753
Test name
Test status
Simulation time 1242820293 ps
CPU time 34.71 seconds
Started Feb 09 03:36:18 AM UTC 25
Finished Feb 09 03:36:54 AM UTC 25
Peak memory 262164 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1843233894 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/alert_handl
er-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.alert_handler_same_csr_outstanding.1843233894
Directory /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/11.alert_handler_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/cover_reg_top/11.alert_handler_tl_errors.3064951769
Short name T751
Test name
Test status
Simulation time 304622801 ps
CPU time 30.53 seconds
Started Feb 09 03:36:07 AM UTC 25
Finished Feb 09 03:36:39 AM UTC 25
Peak memory 262240 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3064951769 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert
_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/c
over_reg_top.vdb -cm_log /dev/null -cm_name 11.alert_handler_tl_errors.3064951769
Directory /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/11.alert_handler_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/cover_reg_top/12.alert_handler_csr_mem_rw_with_rand_reset.3089535082
Short name T757
Test name
Test status
Simulation time 606381954 ps
CPU time 13.46 seconds
Started Feb 09 03:37:04 AM UTC 25
Finished Feb 09 03:37:19 AM UTC 25
Peak memory 251980 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3089535082 -assert nopostproc +
UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep
o/scratch/os_regression/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.alert_handler_csr_mem_rw_with_rand_reset.3089535082
Directory /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/12.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/cover_reg_top/12.alert_handler_csr_rw.3223514919
Short name T755
Test name
Test status
Simulation time 114200354 ps
CPU time 7.42 seconds
Started Feb 09 03:36:54 AM UTC 25
Finished Feb 09 03:37:03 AM UTC 25
Peak memory 250076 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3223514919 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=al
ert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.alert_handler_csr_rw.3223514919
Directory /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/12.alert_handler_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/cover_reg_top/12.alert_handler_intr_test.530250867
Short name T754
Test name
Test status
Simulation time 9972831 ps
CPU time 2.52 seconds
Started Feb 09 03:36:52 AM UTC 25
Finished Feb 09 03:36:56 AM UTC 25
Peak memory 249880 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=530250867 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_
handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/co
ver_reg_top.vdb -cm_log /dev/null -cm_name 12.alert_handler_intr_test.530250867
Directory /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/12.alert_handler_intr_test/latest

Test location /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/cover_reg_top/12.alert_handler_same_csr_outstanding.3009786025
Short name T763
Test name
Test status
Simulation time 501011790 ps
CPU time 58.21 seconds
Started Feb 09 03:36:57 AM UTC 25
Finished Feb 09 03:37:57 AM UTC 25
Peak memory 260120 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3009786025 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/alert_handl
er-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.alert_handler_same_csr_outstanding.3009786025
Directory /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/12.alert_handler_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/cover_reg_top/12.alert_handler_tl_errors.983454137
Short name T756
Test name
Test status
Simulation time 339451552 ps
CPU time 33.16 seconds
Started Feb 09 03:36:35 AM UTC 25
Finished Feb 09 03:37:09 AM UTC 25
Peak memory 262224 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=983454137 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_
handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/co
ver_reg_top.vdb -cm_log /dev/null -cm_name 12.alert_handler_tl_errors.983454137
Directory /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/12.alert_handler_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/cover_reg_top/12.alert_handler_tl_intg_err.1491634348
Short name T198
Test name
Test status
Simulation time 654928732 ps
CPU time 56.45 seconds
Started Feb 09 03:36:40 AM UTC 25
Finished Feb 09 03:37:38 AM UTC 25
Peak memory 262156 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1491634348 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TE
ST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/alert_handler-sim-vc
s/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.alert_handler_tl_intg_err.1491634348
Directory /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/12.alert_handler_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/cover_reg_top/13.alert_handler_csr_mem_rw_with_rand_reset.3627590572
Short name T762
Test name
Test status
Simulation time 839676240 ps
CPU time 14.41 seconds
Started Feb 09 03:37:39 AM UTC 25
Finished Feb 09 03:37:55 AM UTC 25
Peak memory 256076 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3627590572 -assert nopostproc +
UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep
o/scratch/os_regression/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.alert_handler_csr_mem_rw_with_rand_reset.3627590572
Directory /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/13.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/cover_reg_top/13.alert_handler_csr_rw.3705091066
Short name T760
Test name
Test status
Simulation time 212606730 ps
CPU time 4.61 seconds
Started Feb 09 03:37:35 AM UTC 25
Finished Feb 09 03:37:41 AM UTC 25
Peak memory 250076 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3705091066 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=al
ert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.alert_handler_csr_rw.3705091066
Directory /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/13.alert_handler_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/cover_reg_top/13.alert_handler_intr_test.4169129923
Short name T759
Test name
Test status
Simulation time 28554885 ps
CPU time 2.34 seconds
Started Feb 09 03:37:31 AM UTC 25
Finished Feb 09 03:37:35 AM UTC 25
Peak memory 249812 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4169129923 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert
_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/c
over_reg_top.vdb -cm_log /dev/null -cm_name 13.alert_handler_intr_test.4169129923
Directory /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/13.alert_handler_intr_test/latest

Test location /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/cover_reg_top/13.alert_handler_same_csr_outstanding.101979243
Short name T765
Test name
Test status
Simulation time 329081958 ps
CPU time 27.98 seconds
Started Feb 09 03:37:37 AM UTC 25
Finished Feb 09 03:38:07 AM UTC 25
Peak memory 260188 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=101979243 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test
+UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/alert_handle
r-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.alert_handler_same_csr_outstanding.101979243
Directory /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/13.alert_handler_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/cover_reg_top/13.alert_handler_shadow_reg_errors.2134388437
Short name T165
Test name
Test status
Simulation time 2014761256 ps
CPU time 170.83 seconds
Started Feb 09 03:37:15 AM UTC 25
Finished Feb 09 03:40:08 AM UTC 25
Peak memory 279080 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2134388437 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +
UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/alert_handler-
sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.alert_handler_shadow_reg_errors.2134388437
Directory /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/13.alert_handler_shadow_reg_errors/latest

Test location /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/cover_reg_top/13.alert_handler_shadow_reg_errors_with_csr_rw.1551279390
Short name T186
Test name
Test status
Simulation time 10992018136 ps
CPU time 864.68 seconds
Started Feb 09 03:37:10 AM UTC 25
Finished Feb 09 03:51:46 AM UTC 25
Peak memory 285200 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_sc
b=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1551279390 -assert nopostpro
c +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.alert_handler_shadow_reg_errors_with_csr
_rw.1551279390
Directory /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/13.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/cover_reg_top/13.alert_handler_tl_errors.4001508364
Short name T761
Test name
Test status
Simulation time 1396697414 ps
CPU time 32.1 seconds
Started Feb 09 03:37:20 AM UTC 25
Finished Feb 09 03:37:53 AM UTC 25
Peak memory 262300 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4001508364 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert
_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/c
over_reg_top.vdb -cm_log /dev/null -cm_name 13.alert_handler_tl_errors.4001508364
Directory /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/13.alert_handler_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/cover_reg_top/13.alert_handler_tl_intg_err.2564795180
Short name T758
Test name
Test status
Simulation time 47797780 ps
CPU time 5.19 seconds
Started Feb 09 03:37:24 AM UTC 25
Finished Feb 09 03:37:30 AM UTC 25
Peak memory 252116 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2564795180 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TE
ST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/alert_handler-sim-vc
s/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.alert_handler_tl_intg_err.2564795180
Directory /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/13.alert_handler_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/cover_reg_top/14.alert_handler_csr_mem_rw_with_rand_reset.2400106809
Short name T769
Test name
Test status
Simulation time 69704890 ps
CPU time 8.93 seconds
Started Feb 09 03:38:08 AM UTC 25
Finished Feb 09 03:38:18 AM UTC 25
Peak memory 252244 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2400106809 -assert nopostproc +
UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep
o/scratch/os_regression/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.alert_handler_csr_mem_rw_with_rand_reset.2400106809
Directory /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/14.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/cover_reg_top/14.alert_handler_csr_rw.3275477987
Short name T768
Test name
Test status
Simulation time 174946052 ps
CPU time 5.25 seconds
Started Feb 09 03:38:05 AM UTC 25
Finished Feb 09 03:38:11 AM UTC 25
Peak memory 251924 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3275477987 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=al
ert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.alert_handler_csr_rw.3275477987
Directory /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/14.alert_handler_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/cover_reg_top/14.alert_handler_intr_test.3170901860
Short name T766
Test name
Test status
Simulation time 44856630 ps
CPU time 2.16 seconds
Started Feb 09 03:38:04 AM UTC 25
Finished Feb 09 03:38:07 AM UTC 25
Peak memory 250012 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3170901860 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert
_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/c
over_reg_top.vdb -cm_log /dev/null -cm_name 14.alert_handler_intr_test.3170901860
Directory /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/14.alert_handler_intr_test/latest

Test location /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/cover_reg_top/14.alert_handler_same_csr_outstanding.3666764713
Short name T770
Test name
Test status
Simulation time 88980244 ps
CPU time 12.9 seconds
Started Feb 09 03:38:08 AM UTC 25
Finished Feb 09 03:38:22 AM UTC 25
Peak memory 260120 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3666764713 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/alert_handl
er-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.alert_handler_same_csr_outstanding.3666764713
Directory /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/14.alert_handler_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/cover_reg_top/14.alert_handler_shadow_reg_errors_with_csr_rw.4233134844
Short name T187
Test name
Test status
Simulation time 2716715497 ps
CPU time 352.05 seconds
Started Feb 09 03:37:42 AM UTC 25
Finished Feb 09 03:43:39 AM UTC 25
Peak memory 279060 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_sc
b=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4233134844 -assert nopostpro
c +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.alert_handler_shadow_reg_errors_with_csr
_rw.4233134844
Directory /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/14.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/cover_reg_top/14.alert_handler_tl_errors.1112992753
Short name T767
Test name
Test status
Simulation time 159232541 ps
CPU time 9.92 seconds
Started Feb 09 03:37:56 AM UTC 25
Finished Feb 09 03:38:07 AM UTC 25
Peak memory 262228 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1112992753 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert
_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/c
over_reg_top.vdb -cm_log /dev/null -cm_name 14.alert_handler_tl_errors.1112992753
Directory /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/14.alert_handler_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/cover_reg_top/14.alert_handler_tl_intg_err.1314836795
Short name T764
Test name
Test status
Simulation time 110817785 ps
CPU time 3.96 seconds
Started Feb 09 03:37:58 AM UTC 25
Finished Feb 09 03:38:03 AM UTC 25
Peak memory 249872 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1314836795 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TE
ST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/alert_handler-sim-vc
s/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.alert_handler_tl_intg_err.1314836795
Directory /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/14.alert_handler_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/cover_reg_top/15.alert_handler_csr_mem_rw_with_rand_reset.909230857
Short name T774
Test name
Test status
Simulation time 129740343 ps
CPU time 14.39 seconds
Started Feb 09 03:38:51 AM UTC 25
Finished Feb 09 03:39:06 AM UTC 25
Peak memory 249932 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=909230857 -assert nopostproc +U
VM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo
/scratch/os_regression/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.alert_handler_csr_mem_rw_with_rand_reset.909230857
Directory /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/15.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/cover_reg_top/15.alert_handler_csr_rw.3872869143
Short name T773
Test name
Test status
Simulation time 490392403 ps
CPU time 9.7 seconds
Started Feb 09 03:38:46 AM UTC 25
Finished Feb 09 03:38:57 AM UTC 25
Peak memory 250076 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3872869143 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=al
ert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.alert_handler_csr_rw.3872869143
Directory /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/15.alert_handler_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/cover_reg_top/15.alert_handler_intr_test.2004771880
Short name T771
Test name
Test status
Simulation time 6819395 ps
CPU time 2.33 seconds
Started Feb 09 03:38:42 AM UTC 25
Finished Feb 09 03:38:45 AM UTC 25
Peak memory 250076 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2004771880 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert
_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/c
over_reg_top.vdb -cm_log /dev/null -cm_name 15.alert_handler_intr_test.2004771880
Directory /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/15.alert_handler_intr_test/latest

Test location /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/cover_reg_top/15.alert_handler_same_csr_outstanding.2538266535
Short name T775
Test name
Test status
Simulation time 692921712 ps
CPU time 35.11 seconds
Started Feb 09 03:38:46 AM UTC 25
Finished Feb 09 03:39:23 AM UTC 25
Peak memory 260120 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2538266535 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/alert_handl
er-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.alert_handler_same_csr_outstanding.2538266535
Directory /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/15.alert_handler_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/cover_reg_top/15.alert_handler_tl_errors.1864174875
Short name T772
Test name
Test status
Simulation time 256354310 ps
CPU time 24.96 seconds
Started Feb 09 03:38:19 AM UTC 25
Finished Feb 09 03:38:45 AM UTC 25
Peak memory 262228 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1864174875 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert
_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/c
over_reg_top.vdb -cm_log /dev/null -cm_name 15.alert_handler_tl_errors.1864174875
Directory /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/15.alert_handler_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/cover_reg_top/16.alert_handler_csr_mem_rw_with_rand_reset.3529674014
Short name T778
Test name
Test status
Simulation time 287612569 ps
CPU time 9.91 seconds
Started Feb 09 03:39:24 AM UTC 25
Finished Feb 09 03:39:35 AM UTC 25
Peak memory 252180 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3529674014 -assert nopostproc +
UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep
o/scratch/os_regression/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.alert_handler_csr_mem_rw_with_rand_reset.3529674014
Directory /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/16.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/cover_reg_top/16.alert_handler_csr_rw.2321215140
Short name T777
Test name
Test status
Simulation time 46607274 ps
CPU time 5.39 seconds
Started Feb 09 03:39:20 AM UTC 25
Finished Feb 09 03:39:26 AM UTC 25
Peak memory 249876 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2321215140 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=al
ert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.alert_handler_csr_rw.2321215140
Directory /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/16.alert_handler_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/cover_reg_top/16.alert_handler_intr_test.3747382621
Short name T776
Test name
Test status
Simulation time 16289561 ps
CPU time 2.38 seconds
Started Feb 09 03:39:20 AM UTC 25
Finished Feb 09 03:39:23 AM UTC 25
Peak memory 249816 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3747382621 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert
_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/c
over_reg_top.vdb -cm_log /dev/null -cm_name 16.alert_handler_intr_test.3747382621
Directory /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/16.alert_handler_intr_test/latest

Test location /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/cover_reg_top/16.alert_handler_same_csr_outstanding.1700925547
Short name T782
Test name
Test status
Simulation time 358208892 ps
CPU time 29.36 seconds
Started Feb 09 03:39:24 AM UTC 25
Finished Feb 09 03:39:55 AM UTC 25
Peak memory 260120 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1700925547 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/alert_handl
er-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.alert_handler_same_csr_outstanding.1700925547
Directory /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/16.alert_handler_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/cover_reg_top/16.alert_handler_shadow_reg_errors.783622837
Short name T178
Test name
Test status
Simulation time 10351999129 ps
CPU time 198.57 seconds
Started Feb 09 03:39:04 AM UTC 25
Finished Feb 09 03:42:26 AM UTC 25
Peak memory 279068 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=783622837 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +U
VM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/alert_handler-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.alert_handler_shadow_reg_errors.783622837
Directory /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/16.alert_handler_shadow_reg_errors/latest

Test location /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/cover_reg_top/16.alert_handler_shadow_reg_errors_with_csr_rw.1964414684
Short name T185
Test name
Test status
Simulation time 40112888231 ps
CPU time 443.29 seconds
Started Feb 09 03:38:58 AM UTC 25
Finished Feb 09 03:46:27 AM UTC 25
Peak memory 283420 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_sc
b=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1964414684 -assert nopostpro
c +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.alert_handler_shadow_reg_errors_with_csr
_rw.1964414684
Directory /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/16.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/cover_reg_top/16.alert_handler_tl_errors.297752237
Short name T779
Test name
Test status
Simulation time 4933390805 ps
CPU time 34.31 seconds
Started Feb 09 03:39:05 AM UTC 25
Finished Feb 09 03:39:41 AM UTC 25
Peak memory 262288 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=297752237 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_
handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/co
ver_reg_top.vdb -cm_log /dev/null -cm_name 16.alert_handler_tl_errors.297752237
Directory /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/16.alert_handler_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/cover_reg_top/17.alert_handler_csr_mem_rw_with_rand_reset.3209174311
Short name T783
Test name
Test status
Simulation time 34101912 ps
CPU time 5.8 seconds
Started Feb 09 03:39:51 AM UTC 25
Finished Feb 09 03:39:58 AM UTC 25
Peak memory 252244 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3209174311 -assert nopostproc +
UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep
o/scratch/os_regression/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.alert_handler_csr_mem_rw_with_rand_reset.3209174311
Directory /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/17.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/cover_reg_top/17.alert_handler_csr_rw.530955452
Short name T784
Test name
Test status
Simulation time 370326046 ps
CPU time 11.39 seconds
Started Feb 09 03:39:50 AM UTC 25
Finished Feb 09 03:40:02 AM UTC 25
Peak memory 249872 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=530955452 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=ale
rt_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage
/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.alert_handler_csr_rw.530955452
Directory /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/17.alert_handler_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/cover_reg_top/17.alert_handler_intr_test.3298128193
Short name T780
Test name
Test status
Simulation time 15704885 ps
CPU time 2.35 seconds
Started Feb 09 03:39:45 AM UTC 25
Finished Feb 09 03:39:49 AM UTC 25
Peak memory 249888 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3298128193 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert
_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/c
over_reg_top.vdb -cm_log /dev/null -cm_name 17.alert_handler_intr_test.3298128193
Directory /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/17.alert_handler_intr_test/latest

Test location /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/cover_reg_top/17.alert_handler_same_csr_outstanding.1346890241
Short name T792
Test name
Test status
Simulation time 1408361251 ps
CPU time 71.31 seconds
Started Feb 09 03:39:51 AM UTC 25
Finished Feb 09 03:41:04 AM UTC 25
Peak memory 262432 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1346890241 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/alert_handl
er-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.alert_handler_same_csr_outstanding.1346890241
Directory /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/17.alert_handler_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/cover_reg_top/17.alert_handler_shadow_reg_errors.963864552
Short name T163
Test name
Test status
Simulation time 1968027955 ps
CPU time 237.98 seconds
Started Feb 09 03:39:37 AM UTC 25
Finished Feb 09 03:43:39 AM UTC 25
Peak memory 279004 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=963864552 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +U
VM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/alert_handler-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.alert_handler_shadow_reg_errors.963864552
Directory /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/17.alert_handler_shadow_reg_errors/latest

Test location /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/cover_reg_top/17.alert_handler_shadow_reg_errors_with_csr_rw.3166413136
Short name T827
Test name
Test status
Simulation time 271856920281 ps
CPU time 1045.9 seconds
Started Feb 09 03:39:27 AM UTC 25
Finished Feb 09 03:57:05 AM UTC 25
Peak memory 285204 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_sc
b=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3166413136 -assert nopostpro
c +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.alert_handler_shadow_reg_errors_with_csr
_rw.3166413136
Directory /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/17.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/cover_reg_top/17.alert_handler_tl_errors.2206425016
Short name T781
Test name
Test status
Simulation time 919395740 ps
CPU time 10.05 seconds
Started Feb 09 03:39:38 AM UTC 25
Finished Feb 09 03:39:49 AM UTC 25
Peak memory 266400 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2206425016 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert
_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/c
over_reg_top.vdb -cm_log /dev/null -cm_name 17.alert_handler_tl_errors.2206425016
Directory /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/17.alert_handler_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/cover_reg_top/18.alert_handler_csr_mem_rw_with_rand_reset.3948079374
Short name T788
Test name
Test status
Simulation time 52039146 ps
CPU time 6.72 seconds
Started Feb 09 03:40:11 AM UTC 25
Finished Feb 09 03:40:19 AM UTC 25
Peak memory 252180 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3948079374 -assert nopostproc +
UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep
o/scratch/os_regression/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.alert_handler_csr_mem_rw_with_rand_reset.3948079374
Directory /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/18.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/cover_reg_top/18.alert_handler_csr_rw.2180681565
Short name T787
Test name
Test status
Simulation time 58169439 ps
CPU time 5.28 seconds
Started Feb 09 03:40:10 AM UTC 25
Finished Feb 09 03:40:16 AM UTC 25
Peak memory 249948 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2180681565 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=al
ert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.alert_handler_csr_rw.2180681565
Directory /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/18.alert_handler_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/cover_reg_top/18.alert_handler_intr_test.1471206998
Short name T785
Test name
Test status
Simulation time 16307344 ps
CPU time 2.41 seconds
Started Feb 09 03:40:06 AM UTC 25
Finished Feb 09 03:40:10 AM UTC 25
Peak memory 249816 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1471206998 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert
_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/c
over_reg_top.vdb -cm_log /dev/null -cm_name 18.alert_handler_intr_test.1471206998
Directory /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/18.alert_handler_intr_test/latest

Test location /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/cover_reg_top/18.alert_handler_same_csr_outstanding.1422904554
Short name T789
Test name
Test status
Simulation time 255674693 ps
CPU time 28.92 seconds
Started Feb 09 03:40:11 AM UTC 25
Finished Feb 09 03:40:41 AM UTC 25
Peak memory 252000 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1422904554 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/alert_handl
er-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.alert_handler_same_csr_outstanding.1422904554
Directory /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/18.alert_handler_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/cover_reg_top/18.alert_handler_shadow_reg_errors_with_csr_rw.4288538406
Short name T183
Test name
Test status
Simulation time 68873044392 ps
CPU time 479.23 seconds
Started Feb 09 03:39:53 AM UTC 25
Finished Feb 09 03:47:58 AM UTC 25
Peak memory 279060 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_sc
b=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4288538406 -assert nopostpro
c +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.alert_handler_shadow_reg_errors_with_csr
_rw.4288538406
Directory /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/18.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/cover_reg_top/18.alert_handler_tl_errors.2640830771
Short name T786
Test name
Test status
Simulation time 79930160 ps
CPU time 10.33 seconds
Started Feb 09 03:39:59 AM UTC 25
Finished Feb 09 03:40:10 AM UTC 25
Peak memory 262228 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2640830771 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert
_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/c
over_reg_top.vdb -cm_log /dev/null -cm_name 18.alert_handler_tl_errors.2640830771
Directory /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/18.alert_handler_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/cover_reg_top/19.alert_handler_csr_mem_rw_with_rand_reset.2614824494
Short name T797
Test name
Test status
Simulation time 270281069 ps
CPU time 8.93 seconds
Started Feb 09 03:41:02 AM UTC 25
Finished Feb 09 03:41:12 AM UTC 25
Peak memory 251980 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2614824494 -assert nopostproc +
UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep
o/scratch/os_regression/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.alert_handler_csr_mem_rw_with_rand_reset.2614824494
Directory /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/19.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/cover_reg_top/19.alert_handler_csr_rw.3657423952
Short name T795
Test name
Test status
Simulation time 62754544 ps
CPU time 8.01 seconds
Started Feb 09 03:41:00 AM UTC 25
Finished Feb 09 03:41:09 AM UTC 25
Peak memory 249876 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3657423952 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=al
ert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.alert_handler_csr_rw.3657423952
Directory /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/19.alert_handler_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/cover_reg_top/19.alert_handler_intr_test.492845571
Short name T791
Test name
Test status
Simulation time 7164497 ps
CPU time 2.25 seconds
Started Feb 09 03:40:57 AM UTC 25
Finished Feb 09 03:41:00 AM UTC 25
Peak memory 247760 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=492845571 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_
handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/co
ver_reg_top.vdb -cm_log /dev/null -cm_name 19.alert_handler_intr_test.492845571
Directory /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/19.alert_handler_intr_test/latest

Test location /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/cover_reg_top/19.alert_handler_same_csr_outstanding.4195390080
Short name T821
Test name
Test status
Simulation time 785583812 ps
CPU time 36.39 seconds
Started Feb 09 03:41:01 AM UTC 25
Finished Feb 09 03:41:39 AM UTC 25
Peak memory 260320 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4195390080 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/alert_handl
er-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.alert_handler_same_csr_outstanding.4195390080
Directory /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/19.alert_handler_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/cover_reg_top/19.alert_handler_shadow_reg_errors.812890739
Short name T182
Test name
Test status
Simulation time 12817793682 ps
CPU time 232.85 seconds
Started Feb 09 03:40:20 AM UTC 25
Finished Feb 09 03:44:16 AM UTC 25
Peak memory 285212 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=812890739 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +U
VM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/alert_handler-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.alert_handler_shadow_reg_errors.812890739
Directory /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/19.alert_handler_shadow_reg_errors/latest

Test location /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/cover_reg_top/19.alert_handler_tl_errors.2568119470
Short name T793
Test name
Test status
Simulation time 201769863 ps
CPU time 22.43 seconds
Started Feb 09 03:40:43 AM UTC 25
Finished Feb 09 03:41:07 AM UTC 25
Peak memory 262240 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2568119470 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert
_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/c
over_reg_top.vdb -cm_log /dev/null -cm_name 19.alert_handler_tl_errors.2568119470
Directory /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/19.alert_handler_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/cover_reg_top/2.alert_handler_csr_aliasing.3675843513
Short name T236
Test name
Test status
Simulation time 4533225105 ps
CPU time 199.99 seconds
Started Feb 09 03:28:20 AM UTC 25
Finished Feb 09 03:31:43 AM UTC 25
Peak memory 251984 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3675843513 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_
SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/c
overage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_csr_aliasing.3675843513
Directory /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/2.alert_handler_csr_aliasing/latest

Test location /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/cover_reg_top/2.alert_handler_csr_bit_bash.3667846783
Short name T393
Test name
Test status
Simulation time 1639212990 ps
CPU time 215.04 seconds
Started Feb 09 03:28:13 AM UTC 25
Finished Feb 09 03:31:51 AM UTC 25
Peak memory 251920 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3667846783 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_
SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/c
overage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_csr_bit_bash.3667846783
Directory /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/2.alert_handler_csr_bit_bash/latest

Test location /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/cover_reg_top/2.alert_handler_csr_hw_reset.3506771374
Short name T229
Test name
Test status
Simulation time 122794643 ps
CPU time 8.21 seconds
Started Feb 09 03:28:09 AM UTC 25
Finished Feb 09 03:28:19 AM UTC 25
Peak memory 262160 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3506771374 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_
SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/c
overage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_csr_hw_reset.3506771374
Directory /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/2.alert_handler_csr_hw_reset/latest

Test location /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/cover_reg_top/2.alert_handler_csr_mem_rw_with_rand_reset.987992960
Short name T278
Test name
Test status
Simulation time 258227515 ps
CPU time 10.77 seconds
Started Feb 09 03:28:47 AM UTC 25
Finished Feb 09 03:28:59 AM UTC 25
Peak memory 252180 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=987992960 -assert nopostproc +U
VM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo
/scratch/os_regression/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_csr_mem_rw_with_rand_reset.987992960
Directory /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/2.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/cover_reg_top/2.alert_handler_csr_rw.2923067410
Short name T230
Test name
Test status
Simulation time 226048893 ps
CPU time 9.25 seconds
Started Feb 09 03:28:13 AM UTC 25
Finished Feb 09 03:28:23 AM UTC 25
Peak memory 249948 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2923067410 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=al
ert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_csr_rw.2923067410
Directory /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/2.alert_handler_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/cover_reg_top/2.alert_handler_intr_test.921432465
Short name T263
Test name
Test status
Simulation time 6479943 ps
CPU time 2.23 seconds
Started Feb 09 03:28:08 AM UTC 25
Finished Feb 09 03:28:11 AM UTC 25
Peak memory 250008 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=921432465 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_
handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/co
ver_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_intr_test.921432465
Directory /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/2.alert_handler_intr_test/latest

Test location /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/cover_reg_top/2.alert_handler_same_csr_outstanding.2828186863
Short name T232
Test name
Test status
Simulation time 715704897 ps
CPU time 74.56 seconds
Started Feb 09 03:28:24 AM UTC 25
Finished Feb 09 03:29:40 AM UTC 25
Peak memory 260120 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2828186863 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/alert_handl
er-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_same_csr_outstanding.2828186863
Directory /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/2.alert_handler_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/cover_reg_top/2.alert_handler_shadow_reg_errors_with_csr_rw.1882936156
Short name T177
Test name
Test status
Simulation time 28966758418 ps
CPU time 632.92 seconds
Started Feb 09 03:26:54 AM UTC 25
Finished Feb 09 03:37:35 AM UTC 25
Peak memory 279064 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_sc
b=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1882936156 -assert nopostpro
c +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_shadow_reg_errors_with_csr_
rw.1882936156
Directory /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/2.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/cover_reg_top/2.alert_handler_tl_errors.2098181306
Short name T279
Test name
Test status
Simulation time 1299825042 ps
CPU time 30.84 seconds
Started Feb 09 03:27:36 AM UTC 25
Finished Feb 09 03:28:08 AM UTC 25
Peak memory 268568 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2098181306 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert
_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/c
over_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_tl_errors.2098181306
Directory /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/2.alert_handler_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/cover_reg_top/20.alert_handler_intr_test.2500032247
Short name T794
Test name
Test status
Simulation time 20165575 ps
CPU time 2.21 seconds
Started Feb 09 03:41:05 AM UTC 25
Finished Feb 09 03:41:09 AM UTC 25
Peak memory 249820 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2500032247 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert
_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/c
over_reg_top.vdb -cm_log /dev/null -cm_name 20.alert_handler_intr_test.2500032247
Directory /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/20.alert_handler_intr_test/latest

Test location /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/cover_reg_top/21.alert_handler_intr_test.3095038610
Short name T796
Test name
Test status
Simulation time 8139656 ps
CPU time 2.21 seconds
Started Feb 09 03:41:08 AM UTC 25
Finished Feb 09 03:41:11 AM UTC 25
Peak memory 250016 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3095038610 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert
_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/c
over_reg_top.vdb -cm_log /dev/null -cm_name 21.alert_handler_intr_test.3095038610
Directory /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/21.alert_handler_intr_test/latest

Test location /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/cover_reg_top/22.alert_handler_intr_test.3780932491
Short name T798
Test name
Test status
Simulation time 9231609 ps
CPU time 2.13 seconds
Started Feb 09 03:41:10 AM UTC 25
Finished Feb 09 03:41:13 AM UTC 25
Peak memory 249772 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3780932491 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert
_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/c
over_reg_top.vdb -cm_log /dev/null -cm_name 22.alert_handler_intr_test.3780932491
Directory /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/22.alert_handler_intr_test/latest

Test location /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/cover_reg_top/23.alert_handler_intr_test.721072487
Short name T799
Test name
Test status
Simulation time 6766191 ps
CPU time 2.32 seconds
Started Feb 09 03:41:10 AM UTC 25
Finished Feb 09 03:41:14 AM UTC 25
Peak memory 249752 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=721072487 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_
handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/co
ver_reg_top.vdb -cm_log /dev/null -cm_name 23.alert_handler_intr_test.721072487
Directory /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/23.alert_handler_intr_test/latest

Test location /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/cover_reg_top/24.alert_handler_intr_test.2138119392
Short name T800
Test name
Test status
Simulation time 7441563 ps
CPU time 2.27 seconds
Started Feb 09 03:41:12 AM UTC 25
Finished Feb 09 03:41:16 AM UTC 25
Peak memory 249888 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2138119392 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert
_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/c
over_reg_top.vdb -cm_log /dev/null -cm_name 24.alert_handler_intr_test.2138119392
Directory /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/24.alert_handler_intr_test/latest

Test location /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/cover_reg_top/25.alert_handler_intr_test.3802048564
Short name T801
Test name
Test status
Simulation time 11504987 ps
CPU time 2.51 seconds
Started Feb 09 03:41:13 AM UTC 25
Finished Feb 09 03:41:17 AM UTC 25
Peak memory 247764 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3802048564 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert
_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/c
over_reg_top.vdb -cm_log /dev/null -cm_name 25.alert_handler_intr_test.3802048564
Directory /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/25.alert_handler_intr_test/latest

Test location /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/cover_reg_top/26.alert_handler_intr_test.656687564
Short name T802
Test name
Test status
Simulation time 8611902 ps
CPU time 2.41 seconds
Started Feb 09 03:41:15 AM UTC 25
Finished Feb 09 03:41:18 AM UTC 25
Peak memory 249808 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=656687564 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_
handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/co
ver_reg_top.vdb -cm_log /dev/null -cm_name 26.alert_handler_intr_test.656687564
Directory /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/26.alert_handler_intr_test/latest

Test location /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/cover_reg_top/27.alert_handler_intr_test.769614266
Short name T803
Test name
Test status
Simulation time 8186197 ps
CPU time 2.41 seconds
Started Feb 09 03:41:15 AM UTC 25
Finished Feb 09 03:41:18 AM UTC 25
Peak memory 249808 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=769614266 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_
handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/co
ver_reg_top.vdb -cm_log /dev/null -cm_name 27.alert_handler_intr_test.769614266
Directory /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/27.alert_handler_intr_test/latest

Test location /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/cover_reg_top/28.alert_handler_intr_test.1776372246
Short name T804
Test name
Test status
Simulation time 17700378 ps
CPU time 2.12 seconds
Started Feb 09 03:41:17 AM UTC 25
Finished Feb 09 03:41:20 AM UTC 25
Peak memory 250016 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1776372246 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert
_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/c
over_reg_top.vdb -cm_log /dev/null -cm_name 28.alert_handler_intr_test.1776372246
Directory /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/28.alert_handler_intr_test/latest

Test location /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/cover_reg_top/29.alert_handler_intr_test.586254909
Short name T805
Test name
Test status
Simulation time 8152374 ps
CPU time 2.33 seconds
Started Feb 09 03:41:18 AM UTC 25
Finished Feb 09 03:41:21 AM UTC 25
Peak memory 249944 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=586254909 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_
handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/co
ver_reg_top.vdb -cm_log /dev/null -cm_name 29.alert_handler_intr_test.586254909
Directory /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/29.alert_handler_intr_test/latest

Test location /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/cover_reg_top/3.alert_handler_csr_aliasing.1750820070
Short name T734
Test name
Test status
Simulation time 4061142157 ps
CPU time 297.96 seconds
Started Feb 09 03:30:00 AM UTC 25
Finished Feb 09 03:35:03 AM UTC 25
Peak memory 252184 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1750820070 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_
SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/c
overage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_csr_aliasing.1750820070
Directory /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/3.alert_handler_csr_aliasing/latest

Test location /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/cover_reg_top/3.alert_handler_csr_bit_bash.4076397373
Short name T790
Test name
Test status
Simulation time 142639089983 ps
CPU time 646.19 seconds
Started Feb 09 03:29:59 AM UTC 25
Finished Feb 09 03:40:54 AM UTC 25
Peak memory 249940 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4076397373 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_
SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/c
overage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_csr_bit_bash.4076397373
Directory /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/3.alert_handler_csr_bit_bash/latest

Test location /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/cover_reg_top/3.alert_handler_csr_hw_reset.2563130719
Short name T714
Test name
Test status
Simulation time 264042121 ps
CPU time 9.33 seconds
Started Feb 09 03:29:49 AM UTC 25
Finished Feb 09 03:29:59 AM UTC 25
Peak memory 262292 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2563130719 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_
SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/c
overage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_csr_hw_reset.2563130719
Directory /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/3.alert_handler_csr_hw_reset/latest

Test location /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/cover_reg_top/3.alert_handler_csr_mem_rw_with_rand_reset.2948557427
Short name T395
Test name
Test status
Simulation time 120983580 ps
CPU time 7.79 seconds
Started Feb 09 03:30:09 AM UTC 25
Finished Feb 09 03:30:17 AM UTC 25
Peak memory 268436 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2948557427 -assert nopostproc +
UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep
o/scratch/os_regression/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_csr_mem_rw_with_rand_reset.2948557427
Directory /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/3.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/cover_reg_top/3.alert_handler_csr_rw.1075893487
Short name T394
Test name
Test status
Simulation time 133859633 ps
CPU time 6.83 seconds
Started Feb 09 03:29:50 AM UTC 25
Finished Feb 09 03:29:58 AM UTC 25
Peak memory 249876 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1075893487 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=al
ert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_csr_rw.1075893487
Directory /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/3.alert_handler_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/cover_reg_top/3.alert_handler_intr_test.272523504
Short name T389
Test name
Test status
Simulation time 13785263 ps
CPU time 2.33 seconds
Started Feb 09 03:29:46 AM UTC 25
Finished Feb 09 03:29:49 AM UTC 25
Peak memory 249808 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=272523504 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_
handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/co
ver_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_intr_test.272523504
Directory /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/3.alert_handler_intr_test/latest

Test location /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/cover_reg_top/3.alert_handler_same_csr_outstanding.3068618353
Short name T235
Test name
Test status
Simulation time 323198657 ps
CPU time 35.47 seconds
Started Feb 09 03:30:03 AM UTC 25
Finished Feb 09 03:30:40 AM UTC 25
Peak memory 260120 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3068618353 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/alert_handl
er-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_same_csr_outstanding.3068618353
Directory /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/3.alert_handler_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/cover_reg_top/3.alert_handler_shadow_reg_errors.4128906642
Short name T171
Test name
Test status
Simulation time 7805273423 ps
CPU time 466.04 seconds
Started Feb 09 03:29:30 AM UTC 25
Finished Feb 09 03:37:23 AM UTC 25
Peak memory 279060 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4128906642 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +
UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/alert_handler-
sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_shadow_reg_errors.4128906642
Directory /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/3.alert_handler_shadow_reg_errors/latest

Test location /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/cover_reg_top/3.alert_handler_tl_errors.2375989354
Short name T715
Test name
Test status
Simulation time 213435280 ps
CPU time 20.38 seconds
Started Feb 09 03:29:41 AM UTC 25
Finished Feb 09 03:30:03 AM UTC 25
Peak memory 266520 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2375989354 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert
_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/c
over_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_tl_errors.2375989354
Directory /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/3.alert_handler_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/cover_reg_top/30.alert_handler_intr_test.853422705
Short name T807
Test name
Test status
Simulation time 20224824 ps
CPU time 2.14 seconds
Started Feb 09 03:41:19 AM UTC 25
Finished Feb 09 03:41:23 AM UTC 25
Peak memory 249808 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=853422705 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_
handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/co
ver_reg_top.vdb -cm_log /dev/null -cm_name 30.alert_handler_intr_test.853422705
Directory /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/30.alert_handler_intr_test/latest

Test location /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/cover_reg_top/31.alert_handler_intr_test.2670271560
Short name T806
Test name
Test status
Simulation time 17002784 ps
CPU time 2.07 seconds
Started Feb 09 03:41:19 AM UTC 25
Finished Feb 09 03:41:22 AM UTC 25
Peak memory 250016 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2670271560 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert
_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/c
over_reg_top.vdb -cm_log /dev/null -cm_name 31.alert_handler_intr_test.2670271560
Directory /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/31.alert_handler_intr_test/latest

Test location /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/cover_reg_top/32.alert_handler_intr_test.1476673701
Short name T809
Test name
Test status
Simulation time 28989280 ps
CPU time 3.55 seconds
Started Feb 09 03:41:22 AM UTC 25
Finished Feb 09 03:41:26 AM UTC 25
Peak memory 249816 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1476673701 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert
_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/c
over_reg_top.vdb -cm_log /dev/null -cm_name 32.alert_handler_intr_test.1476673701
Directory /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/32.alert_handler_intr_test/latest

Test location /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/cover_reg_top/33.alert_handler_intr_test.3475971345
Short name T808
Test name
Test status
Simulation time 8307532 ps
CPU time 2.32 seconds
Started Feb 09 03:41:23 AM UTC 25
Finished Feb 09 03:41:26 AM UTC 25
Peak memory 249812 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3475971345 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert
_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/c
over_reg_top.vdb -cm_log /dev/null -cm_name 33.alert_handler_intr_test.3475971345
Directory /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/33.alert_handler_intr_test/latest

Test location /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/cover_reg_top/34.alert_handler_intr_test.3211867650
Short name T811
Test name
Test status
Simulation time 8617343 ps
CPU time 2.44 seconds
Started Feb 09 03:41:24 AM UTC 25
Finished Feb 09 03:41:28 AM UTC 25
Peak memory 250012 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3211867650 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert
_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/c
over_reg_top.vdb -cm_log /dev/null -cm_name 34.alert_handler_intr_test.3211867650
Directory /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/34.alert_handler_intr_test/latest

Test location /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/cover_reg_top/35.alert_handler_intr_test.1393985513
Short name T810
Test name
Test status
Simulation time 17436301 ps
CPU time 2.11 seconds
Started Feb 09 03:41:24 AM UTC 25
Finished Feb 09 03:41:27 AM UTC 25
Peak memory 250016 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1393985513 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert
_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/c
over_reg_top.vdb -cm_log /dev/null -cm_name 35.alert_handler_intr_test.1393985513
Directory /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/35.alert_handler_intr_test/latest

Test location /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/cover_reg_top/36.alert_handler_intr_test.3478675260
Short name T813
Test name
Test status
Simulation time 12965262 ps
CPU time 2.56 seconds
Started Feb 09 03:41:27 AM UTC 25
Finished Feb 09 03:41:31 AM UTC 25
Peak memory 249720 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3478675260 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert
_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/c
over_reg_top.vdb -cm_log /dev/null -cm_name 36.alert_handler_intr_test.3478675260
Directory /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/36.alert_handler_intr_test/latest

Test location /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/cover_reg_top/37.alert_handler_intr_test.1416414900
Short name T812
Test name
Test status
Simulation time 12432428 ps
CPU time 2.3 seconds
Started Feb 09 03:41:27 AM UTC 25
Finished Feb 09 03:41:31 AM UTC 25
Peak memory 249612 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1416414900 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert
_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/c
over_reg_top.vdb -cm_log /dev/null -cm_name 37.alert_handler_intr_test.1416414900
Directory /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/37.alert_handler_intr_test/latest

Test location /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/cover_reg_top/38.alert_handler_intr_test.2717477706
Short name T815
Test name
Test status
Simulation time 13155751 ps
CPU time 2.71 seconds
Started Feb 09 03:41:29 AM UTC 25
Finished Feb 09 03:41:33 AM UTC 25
Peak memory 250016 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2717477706 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert
_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/c
over_reg_top.vdb -cm_log /dev/null -cm_name 38.alert_handler_intr_test.2717477706
Directory /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/38.alert_handler_intr_test/latest

Test location /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/cover_reg_top/39.alert_handler_intr_test.418873310
Short name T814
Test name
Test status
Simulation time 8126196 ps
CPU time 2.07 seconds
Started Feb 09 03:41:29 AM UTC 25
Finished Feb 09 03:41:32 AM UTC 25
Peak memory 250008 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=418873310 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_
handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/co
ver_reg_top.vdb -cm_log /dev/null -cm_name 39.alert_handler_intr_test.418873310
Directory /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/39.alert_handler_intr_test/latest

Test location /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/cover_reg_top/4.alert_handler_csr_aliasing.3118118672
Short name T732
Test name
Test status
Simulation time 8618712424 ps
CPU time 185.63 seconds
Started Feb 09 03:31:42 AM UTC 25
Finished Feb 09 03:34:51 AM UTC 25
Peak memory 252184 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3118118672 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_
SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/c
overage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_csr_aliasing.3118118672
Directory /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/4.alert_handler_csr_aliasing/latest

Test location /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/cover_reg_top/4.alert_handler_csr_bit_bash.2614580202
Short name T742
Test name
Test status
Simulation time 8566106880 ps
CPU time 237.66 seconds
Started Feb 09 03:31:38 AM UTC 25
Finished Feb 09 03:35:39 AM UTC 25
Peak memory 251984 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2614580202 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_
SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/c
overage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_csr_bit_bash.2614580202
Directory /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/4.alert_handler_csr_bit_bash/latest

Test location /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/cover_reg_top/4.alert_handler_csr_hw_reset.2847252574
Short name T717
Test name
Test status
Simulation time 212358368 ps
CPU time 8.43 seconds
Started Feb 09 03:31:27 AM UTC 25
Finished Feb 09 03:31:37 AM UTC 25
Peak memory 262360 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2847252574 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_
SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/c
overage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_csr_hw_reset.2847252574
Directory /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/4.alert_handler_csr_hw_reset/latest

Test location /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/cover_reg_top/4.alert_handler_csr_mem_rw_with_rand_reset.3296699036
Short name T719
Test name
Test status
Simulation time 154227225 ps
CPU time 13.2 seconds
Started Feb 09 03:31:52 AM UTC 25
Finished Feb 09 03:32:07 AM UTC 25
Peak memory 262424 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3296699036 -assert nopostproc +
UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep
o/scratch/os_regression/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_csr_mem_rw_with_rand_reset.3296699036
Directory /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/4.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/cover_reg_top/4.alert_handler_csr_rw.1495311764
Short name T718
Test name
Test status
Simulation time 337667235 ps
CPU time 7.59 seconds
Started Feb 09 03:31:32 AM UTC 25
Finished Feb 09 03:31:41 AM UTC 25
Peak memory 250076 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1495311764 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=al
ert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_csr_rw.1495311764
Directory /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/4.alert_handler_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/cover_reg_top/4.alert_handler_same_csr_outstanding.1779999806
Short name T237
Test name
Test status
Simulation time 94322533 ps
CPU time 19.48 seconds
Started Feb 09 03:31:44 AM UTC 25
Finished Feb 09 03:32:05 AM UTC 25
Peak memory 260192 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1779999806 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/alert_handl
er-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_same_csr_outstanding.1779999806
Directory /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/4.alert_handler_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/cover_reg_top/4.alert_handler_shadow_reg_errors_with_csr_rw.1703242468
Short name T396
Test name
Test status
Simulation time 16827197683 ps
CPU time 1235.15 seconds
Started Feb 09 03:30:19 AM UTC 25
Finished Feb 09 03:51:08 AM UTC 25
Peak memory 279136 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_sc
b=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1703242468 -assert nopostpro
c +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_shadow_reg_errors_with_csr_
rw.1703242468
Directory /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/4.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/cover_reg_top/4.alert_handler_tl_errors.1471833612
Short name T716
Test name
Test status
Simulation time 90363794 ps
CPU time 10.25 seconds
Started Feb 09 03:30:41 AM UTC 25
Finished Feb 09 03:30:52 AM UTC 25
Peak memory 262224 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1471833612 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert
_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/c
over_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_tl_errors.1471833612
Directory /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/4.alert_handler_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/cover_reg_top/40.alert_handler_intr_test.3192888194
Short name T817
Test name
Test status
Simulation time 9260352 ps
CPU time 2.51 seconds
Started Feb 09 03:41:32 AM UTC 25
Finished Feb 09 03:41:35 AM UTC 25
Peak memory 249816 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3192888194 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert
_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/c
over_reg_top.vdb -cm_log /dev/null -cm_name 40.alert_handler_intr_test.3192888194
Directory /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/40.alert_handler_intr_test/latest

Test location /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/cover_reg_top/41.alert_handler_intr_test.429936080
Short name T816
Test name
Test status
Simulation time 16091353 ps
CPU time 2.43 seconds
Started Feb 09 03:41:32 AM UTC 25
Finished Feb 09 03:41:35 AM UTC 25
Peak memory 249808 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=429936080 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_
handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/co
ver_reg_top.vdb -cm_log /dev/null -cm_name 41.alert_handler_intr_test.429936080
Directory /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/41.alert_handler_intr_test/latest

Test location /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/cover_reg_top/42.alert_handler_intr_test.2323347373
Short name T818
Test name
Test status
Simulation time 21407484 ps
CPU time 1.97 seconds
Started Feb 09 03:41:33 AM UTC 25
Finished Feb 09 03:41:36 AM UTC 25
Peak memory 247992 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2323347373 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert
_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/c
over_reg_top.vdb -cm_log /dev/null -cm_name 42.alert_handler_intr_test.2323347373
Directory /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/42.alert_handler_intr_test/latest

Test location /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/cover_reg_top/43.alert_handler_intr_test.3858235918
Short name T819
Test name
Test status
Simulation time 43376652 ps
CPU time 2.08 seconds
Started Feb 09 03:41:33 AM UTC 25
Finished Feb 09 03:41:36 AM UTC 25
Peak memory 249820 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3858235918 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert
_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/c
over_reg_top.vdb -cm_log /dev/null -cm_name 43.alert_handler_intr_test.3858235918
Directory /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/43.alert_handler_intr_test/latest

Test location /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/cover_reg_top/44.alert_handler_intr_test.3444047626
Short name T820
Test name
Test status
Simulation time 8542816 ps
CPU time 2.41 seconds
Started Feb 09 03:41:34 AM UTC 25
Finished Feb 09 03:41:38 AM UTC 25
Peak memory 249816 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3444047626 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert
_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/c
over_reg_top.vdb -cm_log /dev/null -cm_name 44.alert_handler_intr_test.3444047626
Directory /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/44.alert_handler_intr_test/latest

Test location /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/cover_reg_top/45.alert_handler_intr_test.2410569756
Short name T822
Test name
Test status
Simulation time 7550010 ps
CPU time 2.08 seconds
Started Feb 09 03:41:37 AM UTC 25
Finished Feb 09 03:41:40 AM UTC 25
Peak memory 247836 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2410569756 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert
_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/c
over_reg_top.vdb -cm_log /dev/null -cm_name 45.alert_handler_intr_test.2410569756
Directory /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/45.alert_handler_intr_test/latest

Test location /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/cover_reg_top/46.alert_handler_intr_test.4115744609
Short name T823
Test name
Test status
Simulation time 15819248 ps
CPU time 2.05 seconds
Started Feb 09 03:41:37 AM UTC 25
Finished Feb 09 03:41:40 AM UTC 25
Peak memory 250016 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4115744609 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert
_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/c
over_reg_top.vdb -cm_log /dev/null -cm_name 46.alert_handler_intr_test.4115744609
Directory /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/46.alert_handler_intr_test/latest

Test location /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/cover_reg_top/47.alert_handler_intr_test.461259491
Short name T824
Test name
Test status
Simulation time 21791962 ps
CPU time 2.22 seconds
Started Feb 09 03:41:37 AM UTC 25
Finished Feb 09 03:41:40 AM UTC 25
Peak memory 249808 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=461259491 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_
handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/co
ver_reg_top.vdb -cm_log /dev/null -cm_name 47.alert_handler_intr_test.461259491
Directory /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/47.alert_handler_intr_test/latest

Test location /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/cover_reg_top/48.alert_handler_intr_test.1459534883
Short name T825
Test name
Test status
Simulation time 7568873 ps
CPU time 2.31 seconds
Started Feb 09 03:41:37 AM UTC 25
Finished Feb 09 03:41:40 AM UTC 25
Peak memory 249888 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1459534883 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert
_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/c
over_reg_top.vdb -cm_log /dev/null -cm_name 48.alert_handler_intr_test.1459534883
Directory /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/48.alert_handler_intr_test/latest

Test location /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/cover_reg_top/49.alert_handler_intr_test.2625790311
Short name T826
Test name
Test status
Simulation time 15476823 ps
CPU time 2.07 seconds
Started Feb 09 03:41:39 AM UTC 25
Finished Feb 09 03:41:42 AM UTC 25
Peak memory 250016 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2625790311 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert
_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/c
over_reg_top.vdb -cm_log /dev/null -cm_name 49.alert_handler_intr_test.2625790311
Directory /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/49.alert_handler_intr_test/latest

Test location /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/cover_reg_top/5.alert_handler_csr_mem_rw_with_rand_reset.2822595146
Short name T722
Test name
Test status
Simulation time 63539769 ps
CPU time 7.46 seconds
Started Feb 09 03:32:40 AM UTC 25
Finished Feb 09 03:32:49 AM UTC 25
Peak memory 250004 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2822595146 -assert nopostproc +
UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep
o/scratch/os_regression/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.alert_handler_csr_mem_rw_with_rand_reset.2822595146
Directory /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/5.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/cover_reg_top/5.alert_handler_csr_rw.3066199712
Short name T720
Test name
Test status
Simulation time 101045796 ps
CPU time 11.51 seconds
Started Feb 09 03:32:12 AM UTC 25
Finished Feb 09 03:32:25 AM UTC 25
Peak memory 249876 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3066199712 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=al
ert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.alert_handler_csr_rw.3066199712
Directory /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/5.alert_handler_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/cover_reg_top/5.alert_handler_intr_test.2750704581
Short name T390
Test name
Test status
Simulation time 12123840 ps
CPU time 2.12 seconds
Started Feb 09 03:32:08 AM UTC 25
Finished Feb 09 03:32:11 AM UTC 25
Peak memory 250008 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2750704581 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert
_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/c
over_reg_top.vdb -cm_log /dev/null -cm_name 5.alert_handler_intr_test.2750704581
Directory /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/5.alert_handler_intr_test/latest

Test location /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/cover_reg_top/5.alert_handler_same_csr_outstanding.46455751
Short name T238
Test name
Test status
Simulation time 1703790526 ps
CPU time 31.73 seconds
Started Feb 09 03:32:25 AM UTC 25
Finished Feb 09 03:32:58 AM UTC 25
Peak memory 262356 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=46455751 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test
+UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/alert_handler
-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.alert_handler_same_csr_outstanding.46455751
Directory /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/5.alert_handler_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/cover_reg_top/5.alert_handler_shadow_reg_errors.1890203573
Short name T174
Test name
Test status
Simulation time 2330910189 ps
CPU time 242.23 seconds
Started Feb 09 03:32:04 AM UTC 25
Finished Feb 09 03:36:10 AM UTC 25
Peak memory 281112 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1890203573 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +
UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/alert_handler-
sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.alert_handler_shadow_reg_errors.1890203573
Directory /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/5.alert_handler_shadow_reg_errors/latest

Test location /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/cover_reg_top/5.alert_handler_tl_errors.3921882207
Short name T721
Test name
Test status
Simulation time 3608271676 ps
CPU time 35.08 seconds
Started Feb 09 03:32:05 AM UTC 25
Finished Feb 09 03:32:41 AM UTC 25
Peak memory 262360 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3921882207 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert
_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/c
over_reg_top.vdb -cm_log /dev/null -cm_name 5.alert_handler_tl_errors.3921882207
Directory /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/5.alert_handler_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/cover_reg_top/6.alert_handler_csr_mem_rw_with_rand_reset.2772809804
Short name T726
Test name
Test status
Simulation time 219982836 ps
CPU time 13.96 seconds
Started Feb 09 03:33:22 AM UTC 25
Finished Feb 09 03:33:37 AM UTC 25
Peak memory 262296 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2772809804 -assert nopostproc +
UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep
o/scratch/os_regression/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.alert_handler_csr_mem_rw_with_rand_reset.2772809804
Directory /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/6.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/cover_reg_top/6.alert_handler_csr_rw.435909209
Short name T725
Test name
Test status
Simulation time 97060799 ps
CPU time 3.68 seconds
Started Feb 09 03:33:16 AM UTC 25
Finished Feb 09 03:33:21 AM UTC 25
Peak memory 250072 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=435909209 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=ale
rt_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage
/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.alert_handler_csr_rw.435909209
Directory /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/6.alert_handler_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/cover_reg_top/6.alert_handler_intr_test.3681417821
Short name T724
Test name
Test status
Simulation time 12136211 ps
CPU time 2.23 seconds
Started Feb 09 03:33:12 AM UTC 25
Finished Feb 09 03:33:16 AM UTC 25
Peak memory 249880 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3681417821 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert
_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/c
over_reg_top.vdb -cm_log /dev/null -cm_name 6.alert_handler_intr_test.3681417821
Directory /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/6.alert_handler_intr_test/latest

Test location /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/cover_reg_top/6.alert_handler_same_csr_outstanding.3129729084
Short name T727
Test name
Test status
Simulation time 2828040598 ps
CPU time 43 seconds
Started Feb 09 03:33:19 AM UTC 25
Finished Feb 09 03:34:03 AM UTC 25
Peak memory 260256 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3129729084 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/alert_handl
er-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.alert_handler_same_csr_outstanding.3129729084
Directory /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/6.alert_handler_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/cover_reg_top/6.alert_handler_shadow_reg_errors.1829709273
Short name T159
Test name
Test status
Simulation time 1259953203 ps
CPU time 118.76 seconds
Started Feb 09 03:32:49 AM UTC 25
Finished Feb 09 03:34:50 AM UTC 25
Peak memory 283092 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1829709273 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +
UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/alert_handler-
sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.alert_handler_shadow_reg_errors.1829709273
Directory /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/6.alert_handler_shadow_reg_errors/latest

Test location /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/cover_reg_top/6.alert_handler_tl_errors.2842985019
Short name T723
Test name
Test status
Simulation time 160101138 ps
CPU time 9.93 seconds
Started Feb 09 03:32:58 AM UTC 25
Finished Feb 09 03:33:10 AM UTC 25
Peak memory 262296 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2842985019 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert
_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/c
over_reg_top.vdb -cm_log /dev/null -cm_name 6.alert_handler_tl_errors.2842985019
Directory /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/6.alert_handler_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/cover_reg_top/7.alert_handler_csr_mem_rw_with_rand_reset.3966420175
Short name T731
Test name
Test status
Simulation time 99707165 ps
CPU time 7.28 seconds
Started Feb 09 03:34:38 AM UTC 25
Finished Feb 09 03:34:46 AM UTC 25
Peak memory 251980 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3966420175 -assert nopostproc +
UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep
o/scratch/os_regression/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.alert_handler_csr_mem_rw_with_rand_reset.3966420175
Directory /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/7.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/cover_reg_top/7.alert_handler_csr_rw.2343670945
Short name T729
Test name
Test status
Simulation time 158888588 ps
CPU time 14.85 seconds
Started Feb 09 03:34:20 AM UTC 25
Finished Feb 09 03:34:36 AM UTC 25
Peak memory 251924 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2343670945 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=al
ert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.alert_handler_csr_rw.2343670945
Directory /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/7.alert_handler_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/cover_reg_top/7.alert_handler_intr_test.747838428
Short name T392
Test name
Test status
Simulation time 8148230 ps
CPU time 2.09 seconds
Started Feb 09 03:34:17 AM UTC 25
Finished Feb 09 03:34:20 AM UTC 25
Peak memory 250008 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=747838428 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_
handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/co
ver_reg_top.vdb -cm_log /dev/null -cm_name 7.alert_handler_intr_test.747838428
Directory /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/7.alert_handler_intr_test/latest

Test location /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/cover_reg_top/7.alert_handler_same_csr_outstanding.2279806456
Short name T730
Test name
Test status
Simulation time 962617917 ps
CPU time 18.13 seconds
Started Feb 09 03:34:22 AM UTC 25
Finished Feb 09 03:34:41 AM UTC 25
Peak memory 260384 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2279806456 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/alert_handl
er-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.alert_handler_same_csr_outstanding.2279806456
Directory /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/7.alert_handler_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/cover_reg_top/7.alert_handler_shadow_reg_errors_with_csr_rw.2274399573
Short name T175
Test name
Test status
Simulation time 9546142699 ps
CPU time 509.86 seconds
Started Feb 09 03:33:26 AM UTC 25
Finished Feb 09 03:42:03 AM UTC 25
Peak memory 281108 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_sc
b=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2274399573 -assert nopostpro
c +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.alert_handler_shadow_reg_errors_with_csr_
rw.2274399573
Directory /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/7.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/cover_reg_top/7.alert_handler_tl_errors.167427377
Short name T728
Test name
Test status
Simulation time 77413257 ps
CPU time 9.22 seconds
Started Feb 09 03:34:04 AM UTC 25
Finished Feb 09 03:34:15 AM UTC 25
Peak memory 262292 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=167427377 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_
handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/co
ver_reg_top.vdb -cm_log /dev/null -cm_name 7.alert_handler_tl_errors.167427377
Directory /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/7.alert_handler_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/cover_reg_top/8.alert_handler_csr_mem_rw_with_rand_reset.1319583971
Short name T736
Test name
Test status
Simulation time 384248948 ps
CPU time 13.05 seconds
Started Feb 09 03:34:57 AM UTC 25
Finished Feb 09 03:35:11 AM UTC 25
Peak memory 252052 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1319583971 -assert nopostproc +
UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep
o/scratch/os_regression/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.alert_handler_csr_mem_rw_with_rand_reset.1319583971
Directory /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/8.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/cover_reg_top/8.alert_handler_csr_rw.1243805479
Short name T735
Test name
Test status
Simulation time 491795035 ps
CPU time 11.11 seconds
Started Feb 09 03:34:53 AM UTC 25
Finished Feb 09 03:35:05 AM UTC 25
Peak memory 250076 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1243805479 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=al
ert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.alert_handler_csr_rw.1243805479
Directory /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/8.alert_handler_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/cover_reg_top/8.alert_handler_intr_test.2725167373
Short name T733
Test name
Test status
Simulation time 7982297 ps
CPU time 2.39 seconds
Started Feb 09 03:34:53 AM UTC 25
Finished Feb 09 03:34:56 AM UTC 25
Peak memory 250072 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2725167373 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert
_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/c
over_reg_top.vdb -cm_log /dev/null -cm_name 8.alert_handler_intr_test.2725167373
Directory /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/8.alert_handler_intr_test/latest

Test location /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/cover_reg_top/8.alert_handler_same_csr_outstanding.2875967371
Short name T739
Test name
Test status
Simulation time 742226889 ps
CPU time 32.44 seconds
Started Feb 09 03:34:53 AM UTC 25
Finished Feb 09 03:35:27 AM UTC 25
Peak memory 260120 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2875967371 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes
t +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/alert_handl
er-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.alert_handler_same_csr_outstanding.2875967371
Directory /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/8.alert_handler_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/cover_reg_top/8.alert_handler_shadow_reg_errors.2052804844
Short name T166
Test name
Test status
Simulation time 5327860029 ps
CPU time 286.02 seconds
Started Feb 09 03:34:47 AM UTC 25
Finished Feb 09 03:39:37 AM UTC 25
Peak memory 279136 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2052804844 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +
UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/alert_handler-
sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.alert_handler_shadow_reg_errors.2052804844
Directory /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/8.alert_handler_shadow_reg_errors/latest

Test location /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/cover_reg_top/8.alert_handler_shadow_reg_errors_with_csr_rw.825147203
Short name T184
Test name
Test status
Simulation time 12423862784 ps
CPU time 460.86 seconds
Started Feb 09 03:34:42 AM UTC 25
Finished Feb 09 03:42:29 AM UTC 25
Peak memory 283156 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_sc
b=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=825147203 -assert nopostproc
+UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r
epo/scratch/os_regression/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.alert_handler_shadow_reg_errors_with_csr_rw.825147203
Directory /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/8.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/cover_reg_top/8.alert_handler_tl_errors.1978042820
Short name T738
Test name
Test status
Simulation time 881378553 ps
CPU time 28.21 seconds
Started Feb 09 03:34:51 AM UTC 25
Finished Feb 09 03:35:20 AM UTC 25
Peak memory 262232 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1978042820 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert
_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/c
over_reg_top.vdb -cm_log /dev/null -cm_name 8.alert_handler_tl_errors.1978042820
Directory /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/8.alert_handler_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/cover_reg_top/9.alert_handler_csr_mem_rw_with_rand_reset.3211324602
Short name T741
Test name
Test status
Simulation time 123712889 ps
CPU time 8.38 seconds
Started Feb 09 03:35:27 AM UTC 25
Finished Feb 09 03:35:37 AM UTC 25
Peak memory 266316 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3211324602 -assert nopostproc +
UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep
o/scratch/os_regression/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.alert_handler_csr_mem_rw_with_rand_reset.3211324602
Directory /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/9.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/cover_reg_top/9.alert_handler_csr_rw.1522851287
Short name T740
Test name
Test status
Simulation time 185755206 ps
CPU time 6.94 seconds
Started Feb 09 03:35:22 AM UTC 25
Finished Feb 09 03:35:30 AM UTC 25
Peak memory 250076 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1522851287 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=al
ert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.alert_handler_csr_rw.1522851287
Directory /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/9.alert_handler_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/cover_reg_top/9.alert_handler_intr_test.809985439
Short name T391
Test name
Test status
Simulation time 10551104 ps
CPU time 2 seconds
Started Feb 09 03:35:22 AM UTC 25
Finished Feb 09 03:35:25 AM UTC 25
Peak memory 247860 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=809985439 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_
handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/co
ver_reg_top.vdb -cm_log /dev/null -cm_name 9.alert_handler_intr_test.809985439
Directory /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/9.alert_handler_intr_test/latest

Test location /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/cover_reg_top/9.alert_handler_same_csr_outstanding.279223389
Short name T743
Test name
Test status
Simulation time 337334463 ps
CPU time 17.83 seconds
Started Feb 09 03:35:26 AM UTC 25
Finished Feb 09 03:35:45 AM UTC 25
Peak memory 260184 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=279223389 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test
+UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/alert_handle
r-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.alert_handler_same_csr_outstanding.279223389
Directory /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/9.alert_handler_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/cover_reg_top/9.alert_handler_shadow_reg_errors.2832372115
Short name T176
Test name
Test status
Simulation time 6426633165 ps
CPU time 423.76 seconds
Started Feb 09 03:35:06 AM UTC 25
Finished Feb 09 03:42:16 AM UTC 25
Peak memory 279264 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2832372115 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +
UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/alert_handler-
sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.alert_handler_shadow_reg_errors.2832372115
Directory /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/9.alert_handler_shadow_reg_errors/latest

Test location /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/cover_reg_top/9.alert_handler_shadow_reg_errors_with_csr_rw.2166794709
Short name T397
Test name
Test status
Simulation time 135210254403 ps
CPU time 1009.41 seconds
Started Feb 09 03:35:04 AM UTC 25
Finished Feb 09 03:52:05 AM UTC 25
Peak memory 285408 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_sc
b=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2166794709 -assert nopostpro
c +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.alert_handler_shadow_reg_errors_with_csr_
rw.2166794709
Directory /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/9.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/cover_reg_top/9.alert_handler_tl_errors.2856064387
Short name T737
Test name
Test status
Simulation time 199411477 ps
CPU time 6.29 seconds
Started Feb 09 03:35:12 AM UTC 25
Finished Feb 09 03:35:20 AM UTC 25
Peak memory 264272 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2856064387 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert
_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/c
over_reg_top.vdb -cm_log /dev/null -cm_name 9.alert_handler_tl_errors.2856064387
Directory /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/9.alert_handler_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default/0.alert_handler_entropy.2851740460
Short name T141
Test name
Test status
Simulation time 25057534316 ps
CPU time 1428.69 seconds
Started Feb 08 07:04:38 PM UTC 25
Finished Feb 08 07:28:43 PM UTC 25
Peak memory 285724 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2851740460 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST
_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_entropy.2851740460
Directory /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/0.alert_handler_entropy/latest

Test location /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default/0.alert_handler_esc_intr_timeout.3888881989
Short name T26
Test name
Test status
Simulation time 1267281321 ps
CPU time 46.36 seconds
Started Feb 08 07:04:38 PM UTC 25
Finished Feb 08 07:05:26 PM UTC 25
Peak memory 263140 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo
/hw/dv/tools/sim.tcl +ntb_random_seed=3888881989 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_tim
eout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 0.alert_handler_esc_intr_timeout.3888881989
Directory /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/0.alert_handler_esc_intr_timeout/latest

Test location /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default/0.alert_handler_lpg.2735110800
Short name T332
Test name
Test status
Simulation time 14564296390 ps
CPU time 1594.22 seconds
Started Feb 08 07:04:38 PM UTC 25
Finished Feb 08 07:31:32 PM UTC 25
Peak memory 298084 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2735110800 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST
_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_lpg.2735110800
Directory /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/0.alert_handler_lpg/latest

Test location /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default/0.alert_handler_lpg_stub_clk.3145751683
Short name T456
Test name
Test status
Simulation time 93013485692 ps
CPU time 2788.85 seconds
Started Feb 08 07:04:38 PM UTC 25
Finished Feb 08 07:51:39 PM UTC 25
Peak memory 304936 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3145751683 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST
_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/alert_handler-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_lpg_stub_clk.3145751683
Directory /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/0.alert_handler_lpg_stub_clk/latest

Test location /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default/0.alert_handler_random_alerts.2486219984
Short name T32
Test name
Test status
Simulation time 1254696244 ps
CPU time 22.24 seconds
Started Feb 08 07:04:35 PM UTC 25
Finished Feb 08 07:04:59 PM UTC 25
Peak memory 269608 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo
/hw/dv/tools/sim.tcl +ntb_random_seed=2486219984 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alert
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default.vdb -cm
_log /dev/null -cm_name 0.alert_handler_random_alerts.2486219984
Directory /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/0.alert_handler_random_alerts/latest

Test location /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default/0.alert_handler_sec_cm.3710660723
Short name T4
Test name
Test status
Simulation time 845070970 ps
CPU time 12.33 seconds
Started Feb 08 07:04:39 PM UTC 25
Finished Feb 08 07:04:52 PM UTC 25
Peak memory 297384 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3710660723 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=a
lert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/covera
ge/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_sec_cm.3710660723
Directory /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/0.alert_handler_sec_cm/latest

Test location /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default/0.alert_handler_smoke.696853615
Short name T9
Test name
Test status
Simulation time 636132990 ps
CPU time 34.48 seconds
Started Feb 08 07:04:35 PM UTC 25
Finished Feb 08 07:05:11 PM UTC 25
Peak memory 269280 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo
/hw/dv/tools/sim.tcl +ntb_random_seed=696853615 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev
/null -cm_name 0.alert_handler_smoke.696853615
Directory /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/0.alert_handler_smoke/latest

Test location /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default/0.alert_handler_stress_all.1950088023
Short name T12
Test name
Test status
Simulation time 664224457 ps
CPU time 16.4 seconds
Started Feb 08 07:04:38 PM UTC 25
Finished Feb 08 07:04:56 PM UTC 25
Peak memory 268916 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1950088023 -assert nopostproc +UVM_TESTNAME=ale
rt_handler_base_test +UVM_TEST_SEQ=alert_handler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os
_regression/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_stress_all.1950088023
Directory /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/0.alert_handler_stress_all/latest

Test location /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default/1.alert_handler_entropy.772354251
Short name T139
Test name
Test status
Simulation time 8074086837 ps
CPU time 1005.22 seconds
Started Feb 08 07:04:39 PM UTC 25
Finished Feb 08 07:21:37 PM UTC 25
Peak memory 286028 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=772354251 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_
SEQ=alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/
coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_entropy.772354251
Directory /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/1.alert_handler_entropy/latest

Test location /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default/1.alert_handler_entropy_stress.2464867525
Short name T7
Test name
Test status
Simulation time 4382680039 ps
CPU time 76.17 seconds
Started Feb 08 07:04:44 PM UTC 25
Finished Feb 08 07:06:02 PM UTC 25
Peak memory 263204 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
paces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2464867525 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_en
tropy_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 1.alert_handler_entropy_stress.2464867525
Directory /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/1.alert_handler_entropy_stress/latest

Test location /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default/1.alert_handler_esc_intr_timeout.3379729074
Short name T14
Test name
Test status
Simulation time 888686243 ps
CPU time 20.22 seconds
Started Feb 08 07:04:39 PM UTC 25
Finished Feb 08 07:05:00 PM UTC 25
Peak memory 263468 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo
/hw/dv/tools/sim.tcl +ntb_random_seed=3379729074 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_tim
eout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 1.alert_handler_esc_intr_timeout.3379729074
Directory /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/1.alert_handler_esc_intr_timeout/latest

Test location /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default/1.alert_handler_lpg.1482368116
Short name T335
Test name
Test status
Simulation time 25516491320 ps
CPU time 1284.9 seconds
Started Feb 08 07:04:41 PM UTC 25
Finished Feb 08 07:26:20 PM UTC 25
Peak memory 285988 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1482368116 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST
_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_lpg.1482368116
Directory /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/1.alert_handler_lpg/latest

Test location /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default/1.alert_handler_lpg_stub_clk.1209545057
Short name T283
Test name
Test status
Simulation time 18190685705 ps
CPU time 1646.75 seconds
Started Feb 08 07:04:44 PM UTC 25
Finished Feb 08 07:32:29 PM UTC 25
Peak memory 302184 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1209545057 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST
_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/alert_handler-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_lpg_stub_clk.1209545057
Directory /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/1.alert_handler_lpg_stub_clk/latest

Test location /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default/1.alert_handler_random_alerts.3270143694
Short name T11
Test name
Test status
Simulation time 646558046 ps
CPU time 15.98 seconds
Started Feb 08 07:04:39 PM UTC 25
Finished Feb 08 07:04:56 PM UTC 25
Peak memory 269280 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo
/hw/dv/tools/sim.tcl +ntb_random_seed=3270143694 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alert
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default.vdb -cm
_log /dev/null -cm_name 1.alert_handler_random_alerts.3270143694
Directory /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/1.alert_handler_random_alerts/latest

Test location /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default/1.alert_handler_random_classes.1532539665
Short name T47
Test name
Test status
Simulation time 218733104 ps
CPU time 29.74 seconds
Started Feb 08 07:04:39 PM UTC 25
Finished Feb 08 07:05:10 PM UTC 25
Peak memory 263400 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo
/hw/dv/tools/sim.tcl +ntb_random_seed=1532539665 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_class
es_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default.vdb -c
m_log /dev/null -cm_name 1.alert_handler_random_classes.1532539665
Directory /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/1.alert_handler_random_classes/latest

Test location /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default/1.alert_handler_smoke.138546649
Short name T262
Test name
Test status
Simulation time 1236941536 ps
CPU time 100.77 seconds
Started Feb 08 07:04:39 PM UTC 25
Finished Feb 08 07:06:22 PM UTC 25
Peak memory 269356 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo
/hw/dv/tools/sim.tcl +ntb_random_seed=138546649 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev
/null -cm_name 1.alert_handler_smoke.138546649
Directory /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/1.alert_handler_smoke/latest

Test location /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default/1.alert_handler_stress_all_with_rand_reset.1315110747
Short name T38
Test name
Test status
Simulation time 242906078597 ps
CPU time 1385.39 seconds
Started Feb 08 07:04:50 PM UTC 25
Finished Feb 08 07:28:12 PM UTC 25
Peak memory 302316 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=ale
rt_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=13151
10747 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_stress_all
_with_rand_reset.1315110747
Directory /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/1.alert_handler_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default/10.alert_handler_alert_accum_saturation.1447898130
Short name T254
Test name
Test status
Simulation time 59260315 ps
CPU time 4.57 seconds
Started Feb 08 07:13:59 PM UTC 25
Finished Feb 08 07:14:04 PM UTC 25
Peak memory 263432 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
paces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1447898130 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_al
ert_accum_saturation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/cover
age/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_alert_accum_saturation.1447898130
Directory /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/10.alert_handler_alert_accum_saturation/latest

Test location /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default/10.alert_handler_entropy.2688538682
Short name T503
Test name
Test status
Simulation time 38408405621 ps
CPU time 3346.56 seconds
Started Feb 08 07:13:08 PM UTC 25
Finished Feb 08 08:09:34 PM UTC 25
Peak memory 304888 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2688538682 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST
_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_entropy.2688538682
Directory /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/10.alert_handler_entropy/latest

Test location /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default/10.alert_handler_entropy_stress.4246886758
Short name T412
Test name
Test status
Simulation time 4265912932 ps
CPU time 75.05 seconds
Started Feb 08 07:13:33 PM UTC 25
Finished Feb 08 07:14:50 PM UTC 25
Peak memory 263280 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
paces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4246886758 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_en
tropy_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 10.alert_handler_entropy_stress.4246886758
Directory /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/10.alert_handler_entropy_stress/latest

Test location /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default/10.alert_handler_esc_alert_accum.2293226402
Short name T338
Test name
Test status
Simulation time 1689265172 ps
CPU time 138.68 seconds
Started Feb 08 07:13:00 PM UTC 25
Finished Feb 08 07:15:21 PM UTC 25
Peak memory 269552 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo
/hw/dv/tools/sim.tcl +ntb_random_seed=2293226402 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_ac
cum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 10.alert_handler_esc_alert_accum.2293226402
Directory /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/10.alert_handler_esc_alert_accum/latest

Test location /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default/10.alert_handler_esc_intr_timeout.527110328
Short name T409
Test name
Test status
Simulation time 204269488 ps
CPU time 18.74 seconds
Started Feb 08 07:12:57 PM UTC 25
Finished Feb 08 07:13:17 PM UTC 25
Peak memory 263400 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo
/hw/dv/tools/sim.tcl +ntb_random_seed=527110328 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_time
out_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 10.alert_handler_esc_intr_timeout.527110328
Directory /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/10.alert_handler_esc_intr_timeout/latest

Test location /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default/10.alert_handler_lpg.2963879529
Short name T334
Test name
Test status
Simulation time 89254070110 ps
CPU time 1719.43 seconds
Started Feb 08 07:13:17 PM UTC 25
Finished Feb 08 07:42:16 PM UTC 25
Peak memory 285752 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2963879529 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST
_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_lpg.2963879529
Directory /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/10.alert_handler_lpg/latest

Test location /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default/10.alert_handler_lpg_stub_clk.764802439
Short name T106
Test name
Test status
Simulation time 173310513511 ps
CPU time 2433.23 seconds
Started Feb 08 07:13:30 PM UTC 25
Finished Feb 08 07:54:32 PM UTC 25
Peak memory 296232 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=764802439 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_
SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/alert_handler-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_lpg_stub_clk.764802439
Directory /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/10.alert_handler_lpg_stub_clk/latest

Test location /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default/10.alert_handler_ping_timeout.62355039
Short name T36
Test name
Test status
Simulation time 2868249978 ps
CPU time 110.04 seconds
Started Feb 08 07:13:16 PM UTC 25
Finished Feb 08 07:15:08 PM UTC 25
Peak memory 263200 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=62355039 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_S
EQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/alert_handler-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_ping_timeout.62355039
Directory /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/10.alert_handler_ping_timeout/latest

Test location /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default/10.alert_handler_random_alerts.1728320197
Short name T411
Test name
Test status
Simulation time 2079372347 ps
CPU time 91.24 seconds
Started Feb 08 07:12:24 PM UTC 25
Finished Feb 08 07:13:58 PM UTC 25
Peak memory 269548 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo
/hw/dv/tools/sim.tcl +ntb_random_seed=1728320197 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alert
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default.vdb -cm
_log /dev/null -cm_name 10.alert_handler_random_alerts.1728320197
Directory /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/10.alert_handler_random_alerts/latest

Test location /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default/10.alert_handler_random_classes.667209491
Short name T285
Test name
Test status
Simulation time 590429534 ps
CPU time 32.01 seconds
Started Feb 08 07:12:25 PM UTC 25
Finished Feb 08 07:12:59 PM UTC 25
Peak memory 263212 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo
/hw/dv/tools/sim.tcl +ntb_random_seed=667209491 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classe
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default.vdb -cm
_log /dev/null -cm_name 10.alert_handler_random_classes.667209491
Directory /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/10.alert_handler_random_classes/latest

Test location /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default/10.alert_handler_sig_int_fail.3352179517
Short name T266
Test name
Test status
Simulation time 113992614 ps
CPU time 11.58 seconds
Started Feb 08 07:13:03 PM UTC 25
Finished Feb 08 07:13:16 PM UTC 25
Peak memory 265520 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo
/hw/dv/tools/sim.tcl +ntb_random_seed=3352179517 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default.vdb -cm_
log /dev/null -cm_name 10.alert_handler_sig_int_fail.3352179517
Directory /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/10.alert_handler_sig_int_fail/latest

Test location /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default/10.alert_handler_smoke.1650773666
Short name T408
Test name
Test status
Simulation time 5110290405 ps
CPU time 36.24 seconds
Started Feb 08 07:12:24 PM UTC 25
Finished Feb 08 07:13:02 PM UTC 25
Peak memory 269344 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo
/hw/dv/tools/sim.tcl +ntb_random_seed=1650773666 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default.vdb -cm_log /de
v/null -cm_name 10.alert_handler_smoke.1650773666
Directory /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/10.alert_handler_smoke/latest

Test location /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default/11.alert_handler_alert_accum_saturation.485475167
Short name T255
Test name
Test status
Simulation time 42071170 ps
CPU time 5.44 seconds
Started Feb 08 07:16:16 PM UTC 25
Finished Feb 08 07:16:23 PM UTC 25
Peak memory 263408 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
paces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=485475167 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ale
rt_accum_saturation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/covera
ge/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_alert_accum_saturation.485475167
Directory /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/11.alert_handler_alert_accum_saturation/latest

Test location /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default/11.alert_handler_entropy.1176923768
Short name T218
Test name
Test status
Simulation time 22986121531 ps
CPU time 842.95 seconds
Started Feb 08 07:15:22 PM UTC 25
Finished Feb 08 07:29:36 PM UTC 25
Peak memory 279584 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1176923768 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST
_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_entropy.1176923768
Directory /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/11.alert_handler_entropy/latest

Test location /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default/11.alert_handler_entropy_stress.1729233954
Short name T416
Test name
Test status
Simulation time 3518149365 ps
CPU time 60.14 seconds
Started Feb 08 07:15:48 PM UTC 25
Finished Feb 08 07:16:50 PM UTC 25
Peak memory 263280 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
paces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1729233954 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_en
tropy_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 11.alert_handler_entropy_stress.1729233954
Directory /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/11.alert_handler_entropy_stress/latest

Test location /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default/11.alert_handler_esc_alert_accum.3311362001
Short name T415
Test name
Test status
Simulation time 652692165 ps
CPU time 37.64 seconds
Started Feb 08 07:15:19 PM UTC 25
Finished Feb 08 07:15:58 PM UTC 25
Peak memory 269552 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo
/hw/dv/tools/sim.tcl +ntb_random_seed=3311362001 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_ac
cum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 11.alert_handler_esc_alert_accum.3311362001
Directory /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/11.alert_handler_esc_alert_accum/latest

Test location /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default/11.alert_handler_esc_intr_timeout.4249383341
Short name T414
Test name
Test status
Simulation time 144275239 ps
CPU time 23.68 seconds
Started Feb 08 07:15:15 PM UTC 25
Finished Feb 08 07:15:41 PM UTC 25
Peak memory 263468 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo
/hw/dv/tools/sim.tcl +ntb_random_seed=4249383341 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_tim
eout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 11.alert_handler_esc_intr_timeout.4249383341
Directory /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/11.alert_handler_esc_intr_timeout/latest

Test location /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default/11.alert_handler_lpg.3229609204
Short name T365
Test name
Test status
Simulation time 57176708938 ps
CPU time 3515.26 seconds
Started Feb 08 07:15:41 PM UTC 25
Finished Feb 08 08:14:55 PM UTC 25
Peak memory 304964 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3229609204 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST
_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_lpg.3229609204
Directory /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/11.alert_handler_lpg/latest

Test location /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default/11.alert_handler_lpg_stub_clk.2056277137
Short name T114
Test name
Test status
Simulation time 60016270920 ps
CPU time 1887.84 seconds
Started Feb 08 07:15:45 PM UTC 25
Finished Feb 08 07:47:35 PM UTC 25
Peak memory 302112 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2056277137 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST
_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/alert_handler-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_lpg_stub_clk.2056277137
Directory /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/11.alert_handler_lpg_stub_clk/latest

Test location /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default/11.alert_handler_ping_timeout.3960779181
Short name T339
Test name
Test status
Simulation time 45133281090 ps
CPU time 712.84 seconds
Started Feb 08 07:15:23 PM UTC 25
Finished Feb 08 07:27:26 PM UTC 25
Peak memory 263200 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3960779181 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST
_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/alert_handler-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_ping_timeout.3960779181
Directory /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/11.alert_handler_ping_timeout/latest

Test location /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default/11.alert_handler_random_alerts.1785265605
Short name T48
Test name
Test status
Simulation time 388856772 ps
CPU time 21.86 seconds
Started Feb 08 07:14:51 PM UTC 25
Finished Feb 08 07:15:14 PM UTC 25
Peak memory 263140 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo
/hw/dv/tools/sim.tcl +ntb_random_seed=1785265605 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alert
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default.vdb -cm
_log /dev/null -cm_name 11.alert_handler_random_alerts.1785265605
Directory /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/11.alert_handler_random_alerts/latest

Test location /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default/11.alert_handler_random_classes.356764121
Short name T294
Test name
Test status
Simulation time 276682641 ps
CPU time 33.46 seconds
Started Feb 08 07:15:09 PM UTC 25
Finished Feb 08 07:15:45 PM UTC 25
Peak memory 263144 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo
/hw/dv/tools/sim.tcl +ntb_random_seed=356764121 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classe
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default.vdb -cm
_log /dev/null -cm_name 11.alert_handler_random_classes.356764121
Directory /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/11.alert_handler_random_classes/latest

Test location /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default/11.alert_handler_smoke.1711065997
Short name T413
Test name
Test status
Simulation time 1565520610 ps
CPU time 70.23 seconds
Started Feb 08 07:14:06 PM UTC 25
Finished Feb 08 07:15:18 PM UTC 25
Peak memory 269544 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo
/hw/dv/tools/sim.tcl +ntb_random_seed=1711065997 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default.vdb -cm_log /de
v/null -cm_name 11.alert_handler_smoke.1711065997
Directory /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/11.alert_handler_smoke/latest

Test location /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default/11.alert_handler_stress_all.601980719
Short name T417
Test name
Test status
Simulation time 2233026851 ps
CPU time 69.62 seconds
Started Feb 08 07:15:59 PM UTC 25
Finished Feb 08 07:17:10 PM UTC 25
Peak memory 269616 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=601980719 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_
regression/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_stress_all.601980719
Directory /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/11.alert_handler_stress_all/latest

Test location /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default/11.alert_handler_stress_all_with_rand_reset.1451169141
Short name T155
Test name
Test status
Simulation time 159979348270 ps
CPU time 3599.18 seconds
Started Feb 08 07:16:23 PM UTC 25
Finished Feb 08 08:17:03 PM UTC 25
Peak memory 321380 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=ale
rt_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=14511
69141 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_stress_al
l_with_rand_reset.1451169141
Directory /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/11.alert_handler_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default/12.alert_handler_entropy.911219873
Short name T277
Test name
Test status
Simulation time 106015046295 ps
CPU time 1278.8 seconds
Started Feb 08 07:18:04 PM UTC 25
Finished Feb 08 07:39:38 PM UTC 25
Peak memory 295996 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=911219873 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_
SEQ=alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/
coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_entropy.911219873
Directory /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/12.alert_handler_entropy/latest

Test location /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default/12.alert_handler_entropy_stress.2009970410
Short name T423
Test name
Test status
Simulation time 220833324 ps
CPU time 19.78 seconds
Started Feb 08 07:19:10 PM UTC 25
Finished Feb 08 07:19:31 PM UTC 25
Peak memory 263408 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
paces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2009970410 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_en
tropy_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 12.alert_handler_entropy_stress.2009970410
Directory /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/12.alert_handler_entropy_stress/latest

Test location /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default/12.alert_handler_esc_alert_accum.1647625960
Short name T422
Test name
Test status
Simulation time 2292796328 ps
CPU time 84.89 seconds
Started Feb 08 07:17:30 PM UTC 25
Finished Feb 08 07:18:57 PM UTC 25
Peak memory 269344 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo
/hw/dv/tools/sim.tcl +ntb_random_seed=1647625960 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_ac
cum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 12.alert_handler_esc_alert_accum.1647625960
Directory /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/12.alert_handler_esc_alert_accum/latest

Test location /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default/12.alert_handler_esc_intr_timeout.1134931174
Short name T419
Test name
Test status
Simulation time 64141439 ps
CPU time 10.71 seconds
Started Feb 08 07:17:17 PM UTC 25
Finished Feb 08 07:17:29 PM UTC 25
Peak memory 263212 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo
/hw/dv/tools/sim.tcl +ntb_random_seed=1134931174 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_tim
eout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 12.alert_handler_esc_intr_timeout.1134931174
Directory /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/12.alert_handler_esc_intr_timeout/latest

Test location /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default/12.alert_handler_lpg.1483599746
Short name T355
Test name
Test status
Simulation time 91174603474 ps
CPU time 2590.37 seconds
Started Feb 08 07:18:57 PM UTC 25
Finished Feb 08 08:02:35 PM UTC 25
Peak memory 300136 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1483599746 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST
_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_lpg.1483599746
Directory /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/12.alert_handler_lpg/latest

Test location /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default/12.alert_handler_lpg_stub_clk.2789412368
Short name T498
Test name
Test status
Simulation time 78249974391 ps
CPU time 2935.18 seconds
Started Feb 08 07:19:01 PM UTC 25
Finished Feb 08 08:08:29 PM UTC 25
Peak memory 298856 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2789412368 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST
_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/alert_handler-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_lpg_stub_clk.2789412368
Directory /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/12.alert_handler_lpg_stub_clk/latest

Test location /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default/12.alert_handler_ping_timeout.2668714568
Short name T79
Test name
Test status
Simulation time 12759947699 ps
CPU time 288.62 seconds
Started Feb 08 07:18:36 PM UTC 25
Finished Feb 08 07:23:29 PM UTC 25
Peak memory 263196 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2668714568 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST
_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/alert_handler-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_ping_timeout.2668714568
Directory /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/12.alert_handler_ping_timeout/latest

Test location /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default/12.alert_handler_random_alerts.899726647
Short name T421
Test name
Test status
Simulation time 1057995627 ps
CPU time 70.97 seconds
Started Feb 08 07:16:50 PM UTC 25
Finished Feb 08 07:18:03 PM UTC 25
Peak memory 269280 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo
/hw/dv/tools/sim.tcl +ntb_random_seed=899726647 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default.vdb -cm_
log /dev/null -cm_name 12.alert_handler_random_alerts.899726647
Directory /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/12.alert_handler_random_alerts/latest

Test location /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default/12.alert_handler_random_classes.1440220070
Short name T420
Test name
Test status
Simulation time 3933387240 ps
CPU time 42.76 seconds
Started Feb 08 07:17:11 PM UTC 25
Finished Feb 08 07:17:56 PM UTC 25
Peak memory 263468 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo
/hw/dv/tools/sim.tcl +ntb_random_seed=1440220070 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_class
es_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default.vdb -c
m_log /dev/null -cm_name 12.alert_handler_random_classes.1440220070
Directory /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/12.alert_handler_random_classes/latest

Test location /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default/12.alert_handler_sig_int_fail.714227729
Short name T264
Test name
Test status
Simulation time 479908559 ps
CPU time 36.72 seconds
Started Feb 08 07:17:57 PM UTC 25
Finished Feb 08 07:18:35 PM UTC 25
Peak memory 263212 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo
/hw/dv/tools/sim.tcl +ntb_random_seed=714227729 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default.vdb -cm_l
og /dev/null -cm_name 12.alert_handler_sig_int_fail.714227729
Directory /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/12.alert_handler_sig_int_fail/latest

Test location /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default/12.alert_handler_smoke.2576134694
Short name T418
Test name
Test status
Simulation time 484848611 ps
CPU time 44.64 seconds
Started Feb 08 07:16:29 PM UTC 25
Finished Feb 08 07:17:16 PM UTC 25
Peak memory 269280 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo
/hw/dv/tools/sim.tcl +ntb_random_seed=2576134694 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default.vdb -cm_log /de
v/null -cm_name 12.alert_handler_smoke.2576134694
Directory /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/12.alert_handler_smoke/latest

Test location /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default/12.alert_handler_stress_all.3502291108
Short name T306
Test name
Test status
Simulation time 752445177 ps
CPU time 46.37 seconds
Started Feb 08 07:19:32 PM UTC 25
Finished Feb 08 07:20:21 PM UTC 25
Peak memory 269488 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3502291108 -assert nopostproc +UVM_TESTNAME=ale
rt_handler_base_test +UVM_TEST_SEQ=alert_handler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os
_regression/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_stress_all.3502291108
Directory /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/12.alert_handler_stress_all/latest

Test location /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default/13.alert_handler_entropy.2809150207
Short name T454
Test name
Test status
Simulation time 43645176728 ps
CPU time 1761.06 seconds
Started Feb 08 07:21:18 PM UTC 25
Finished Feb 08 07:51:00 PM UTC 25
Peak memory 302184 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2809150207 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST
_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_entropy.2809150207
Directory /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/13.alert_handler_entropy/latest

Test location /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default/13.alert_handler_entropy_stress.2615430463
Short name T76
Test name
Test status
Simulation time 168593009 ps
CPU time 10.02 seconds
Started Feb 08 07:21:46 PM UTC 25
Finished Feb 08 07:21:58 PM UTC 25
Peak memory 263216 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
paces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2615430463 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_en
tropy_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 13.alert_handler_entropy_stress.2615430463
Directory /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/13.alert_handler_entropy_stress/latest

Test location /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default/13.alert_handler_esc_alert_accum.737395262
Short name T80
Test name
Test status
Simulation time 14994080608 ps
CPU time 162.56 seconds
Started Feb 08 07:21:02 PM UTC 25
Finished Feb 08 07:23:47 PM UTC 25
Peak memory 269348 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo
/hw/dv/tools/sim.tcl +ntb_random_seed=737395262 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_acc
um_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default.vdb -c
m_log /dev/null -cm_name 13.alert_handler_esc_alert_accum.737395262
Directory /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/13.alert_handler_esc_alert_accum/latest

Test location /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default/13.alert_handler_esc_intr_timeout.626489932
Short name T425
Test name
Test status
Simulation time 413246326 ps
CPU time 5.64 seconds
Started Feb 08 07:21:00 PM UTC 25
Finished Feb 08 07:21:06 PM UTC 25
Peak memory 252896 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo
/hw/dv/tools/sim.tcl +ntb_random_seed=626489932 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_time
out_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 13.alert_handler_esc_intr_timeout.626489932
Directory /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/13.alert_handler_esc_intr_timeout/latest

Test location /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default/13.alert_handler_lpg_stub_clk.2770089708
Short name T479
Test name
Test status
Simulation time 163832329603 ps
CPU time 2312.84 seconds
Started Feb 08 07:21:42 PM UTC 25
Finished Feb 08 08:00:40 PM UTC 25
Peak memory 298016 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2770089708 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST
_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/alert_handler-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_lpg_stub_clk.2770089708
Directory /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/13.alert_handler_lpg_stub_clk/latest

Test location /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default/13.alert_handler_ping_timeout.3813897404
Short name T362
Test name
Test status
Simulation time 18292947467 ps
CPU time 244.55 seconds
Started Feb 08 07:21:31 PM UTC 25
Finished Feb 08 07:25:39 PM UTC 25
Peak memory 263272 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3813897404 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST
_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/alert_handler-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_ping_timeout.3813897404
Directory /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/13.alert_handler_ping_timeout/latest

Test location /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default/13.alert_handler_random_alerts.3714031966
Short name T424
Test name
Test status
Simulation time 496975492 ps
CPU time 30.72 seconds
Started Feb 08 07:20:26 PM UTC 25
Finished Feb 08 07:20:59 PM UTC 25
Peak memory 269284 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo
/hw/dv/tools/sim.tcl +ntb_random_seed=3714031966 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alert
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default.vdb -cm
_log /dev/null -cm_name 13.alert_handler_random_alerts.3714031966
Directory /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/13.alert_handler_random_alerts/latest

Test location /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default/13.alert_handler_sig_int_fail.2693246119
Short name T59
Test name
Test status
Simulation time 543623851 ps
CPU time 35.42 seconds
Started Feb 08 07:21:07 PM UTC 25
Finished Feb 08 07:21:44 PM UTC 25
Peak memory 269288 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo
/hw/dv/tools/sim.tcl +ntb_random_seed=2693246119 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default.vdb -cm_
log /dev/null -cm_name 13.alert_handler_sig_int_fail.2693246119
Directory /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/13.alert_handler_sig_int_fail/latest

Test location /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default/13.alert_handler_smoke.2729878675
Short name T37
Test name
Test status
Simulation time 194801198 ps
CPU time 16.13 seconds
Started Feb 08 07:20:21 PM UTC 25
Finished Feb 08 07:20:39 PM UTC 25
Peak memory 263400 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo
/hw/dv/tools/sim.tcl +ntb_random_seed=2729878675 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default.vdb -cm_log /de
v/null -cm_name 13.alert_handler_smoke.2729878675
Directory /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/13.alert_handler_smoke/latest

Test location /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default/13.alert_handler_stress_all_with_rand_reset.2834548601
Short name T128
Test name
Test status
Simulation time 55327375014 ps
CPU time 3767.3 seconds
Started Feb 08 07:22:18 PM UTC 25
Finished Feb 08 08:25:48 PM UTC 25
Peak memory 337764 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=ale
rt_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=28345
48601 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_stress_al
l_with_rand_reset.2834548601
Directory /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/13.alert_handler_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default/14.alert_handler_alert_accum_saturation.4055744264
Short name T257
Test name
Test status
Simulation time 22978900 ps
CPU time 4.27 seconds
Started Feb 08 07:26:22 PM UTC 25
Finished Feb 08 07:26:27 PM UTC 25
Peak memory 263360 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
paces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4055744264 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_al
ert_accum_saturation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/cover
age/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_alert_accum_saturation.4055744264
Directory /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/14.alert_handler_alert_accum_saturation/latest

Test location /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default/14.alert_handler_entropy.1565378016
Short name T68
Test name
Test status
Simulation time 44374403166 ps
CPU time 1591.28 seconds
Started Feb 08 07:24:53 PM UTC 25
Finished Feb 08 07:51:43 PM UTC 25
Peak memory 285728 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1565378016 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST
_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_entropy.1565378016
Directory /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/14.alert_handler_entropy/latest

Test location /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default/14.alert_handler_entropy_stress.222271313
Short name T426
Test name
Test status
Simulation time 1352969159 ps
CPU time 56.97 seconds
Started Feb 08 07:25:40 PM UTC 25
Finished Feb 08 07:26:39 PM UTC 25
Peak memory 263140 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
paces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=222271313 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ent
ropy_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 14.alert_handler_entropy_stress.222271313
Directory /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/14.alert_handler_entropy_stress/latest

Test location /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default/14.alert_handler_esc_alert_accum.1696600854
Short name T280
Test name
Test status
Simulation time 2210211896 ps
CPU time 61.63 seconds
Started Feb 08 07:24:11 PM UTC 25
Finished Feb 08 07:25:14 PM UTC 25
Peak memory 269612 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo
/hw/dv/tools/sim.tcl +ntb_random_seed=1696600854 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_ac
cum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 14.alert_handler_esc_alert_accum.1696600854
Directory /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/14.alert_handler_esc_alert_accum/latest

Test location /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default/14.alert_handler_esc_intr_timeout.2128722649
Short name T83
Test name
Test status
Simulation time 1431099643 ps
CPU time 26.37 seconds
Started Feb 08 07:23:50 PM UTC 25
Finished Feb 08 07:24:18 PM UTC 25
Peak memory 267500 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo
/hw/dv/tools/sim.tcl +ntb_random_seed=2128722649 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_tim
eout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 14.alert_handler_esc_intr_timeout.2128722649
Directory /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/14.alert_handler_esc_intr_timeout/latest

Test location /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default/14.alert_handler_lpg.581263044
Short name T363
Test name
Test status
Simulation time 51452798653 ps
CPU time 2575.39 seconds
Started Feb 08 07:25:23 PM UTC 25
Finished Feb 08 08:08:45 PM UTC 25
Peak memory 302408 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=581263044 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_
SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/cove
rage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_lpg.581263044
Directory /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/14.alert_handler_lpg/latest

Test location /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default/14.alert_handler_lpg_stub_clk.2391330893
Short name T453
Test name
Test status
Simulation time 133696444839 ps
CPU time 1485.84 seconds
Started Feb 08 07:25:25 PM UTC 25
Finished Feb 08 07:50:27 PM UTC 25
Peak memory 302380 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2391330893 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST
_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/alert_handler-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_lpg_stub_clk.2391330893
Directory /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/14.alert_handler_lpg_stub_clk/latest

Test location /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default/14.alert_handler_ping_timeout.1012332887
Short name T270
Test name
Test status
Simulation time 140949754782 ps
CPU time 629.52 seconds
Started Feb 08 07:25:15 PM UTC 25
Finished Feb 08 07:35:53 PM UTC 25
Peak memory 263276 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1012332887 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST
_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/alert_handler-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_ping_timeout.1012332887
Directory /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/14.alert_handler_ping_timeout/latest

Test location /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default/14.alert_handler_random_alerts.860249845
Short name T81
Test name
Test status
Simulation time 148701339 ps
CPU time 17.55 seconds
Started Feb 08 07:23:30 PM UTC 25
Finished Feb 08 07:23:49 PM UTC 25
Peak memory 263144 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo
/hw/dv/tools/sim.tcl +ntb_random_seed=860249845 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default.vdb -cm_
log /dev/null -cm_name 14.alert_handler_random_alerts.860249845
Directory /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/14.alert_handler_random_alerts/latest

Test location /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default/14.alert_handler_random_classes.3677547723
Short name T60
Test name
Test status
Simulation time 3609468891 ps
CPU time 62.04 seconds
Started Feb 08 07:23:49 PM UTC 25
Finished Feb 08 07:24:52 PM UTC 25
Peak memory 263276 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo
/hw/dv/tools/sim.tcl +ntb_random_seed=3677547723 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_class
es_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default.vdb -c
m_log /dev/null -cm_name 14.alert_handler_random_classes.3677547723
Directory /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/14.alert_handler_random_classes/latest

Test location /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default/14.alert_handler_sig_int_fail.4078445228
Short name T307
Test name
Test status
Simulation time 793194750 ps
CPU time 64.02 seconds
Started Feb 08 07:24:18 PM UTC 25
Finished Feb 08 07:25:24 PM UTC 25
Peak memory 269296 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo
/hw/dv/tools/sim.tcl +ntb_random_seed=4078445228 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default.vdb -cm_
log /dev/null -cm_name 14.alert_handler_sig_int_fail.4078445228
Directory /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/14.alert_handler_sig_int_fail/latest

Test location /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default/14.alert_handler_stress_all.2238010294
Short name T137
Test name
Test status
Simulation time 27714020375 ps
CPU time 2005.77 seconds
Started Feb 08 07:26:08 PM UTC 25
Finished Feb 08 07:59:57 PM UTC 25
Peak memory 302384 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2238010294 -assert nopostproc +UVM_TESTNAME=ale
rt_handler_base_test +UVM_TEST_SEQ=alert_handler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os
_regression/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_stress_all.2238010294
Directory /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/14.alert_handler_stress_all/latest

Test location /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default/15.alert_handler_alert_accum_saturation.1931572787
Short name T219
Test name
Test status
Simulation time 156613975 ps
CPU time 4.72 seconds
Started Feb 08 07:29:38 PM UTC 25
Finished Feb 08 07:29:44 PM UTC 25
Peak memory 263624 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
paces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1931572787 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_al
ert_accum_saturation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/cover
age/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_alert_accum_saturation.1931572787
Directory /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/15.alert_handler_alert_accum_saturation/latest

Test location /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default/15.alert_handler_entropy.2055701718
Short name T451
Test name
Test status
Simulation time 43313700753 ps
CPU time 1242.33 seconds
Started Feb 08 07:28:12 PM UTC 25
Finished Feb 08 07:49:08 PM UTC 25
Peak memory 285752 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2055701718 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST
_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_entropy.2055701718
Directory /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/15.alert_handler_entropy/latest

Test location /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default/15.alert_handler_entropy_stress.4009348522
Short name T430
Test name
Test status
Simulation time 6671117174 ps
CPU time 117.71 seconds
Started Feb 08 07:28:44 PM UTC 25
Finished Feb 08 07:30:44 PM UTC 25
Peak memory 263472 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
paces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4009348522 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_en
tropy_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 15.alert_handler_entropy_stress.4009348522
Directory /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/15.alert_handler_entropy_stress/latest

Test location /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default/15.alert_handler_esc_alert_accum.4149298368
Short name T431
Test name
Test status
Simulation time 1640552868 ps
CPU time 178.31 seconds
Started Feb 08 07:27:54 PM UTC 25
Finished Feb 08 07:30:56 PM UTC 25
Peak memory 269288 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo
/hw/dv/tools/sim.tcl +ntb_random_seed=4149298368 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_ac
cum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 15.alert_handler_esc_alert_accum.4149298368
Directory /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/15.alert_handler_esc_alert_accum/latest

Test location /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default/15.alert_handler_esc_intr_timeout.1082366246
Short name T429
Test name
Test status
Simulation time 89541220 ps
CPU time 11.44 seconds
Started Feb 08 07:27:41 PM UTC 25
Finished Feb 08 07:27:54 PM UTC 25
Peak memory 263140 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo
/hw/dv/tools/sim.tcl +ntb_random_seed=1082366246 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_tim
eout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 15.alert_handler_esc_intr_timeout.1082366246
Directory /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/15.alert_handler_esc_intr_timeout/latest

Test location /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default/15.alert_handler_lpg_stub_clk.3741394858
Short name T301
Test name
Test status
Simulation time 32204707037 ps
CPU time 2135.11 seconds
Started Feb 08 07:28:23 PM UTC 25
Finished Feb 08 08:04:22 PM UTC 25
Peak memory 300328 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3741394858 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST
_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/alert_handler-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_lpg_stub_clk.3741394858
Directory /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/15.alert_handler_lpg_stub_clk/latest

Test location /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default/15.alert_handler_random_alerts.3894157287
Short name T62
Test name
Test status
Simulation time 445240225 ps
CPU time 43.97 seconds
Started Feb 08 07:27:26 PM UTC 25
Finished Feb 08 07:28:11 PM UTC 25
Peak memory 269356 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo
/hw/dv/tools/sim.tcl +ntb_random_seed=3894157287 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alert
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default.vdb -cm
_log /dev/null -cm_name 15.alert_handler_random_alerts.3894157287
Directory /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/15.alert_handler_random_alerts/latest

Test location /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default/15.alert_handler_random_classes.1752509688
Short name T428
Test name
Test status
Simulation time 166485912 ps
CPU time 11.57 seconds
Started Feb 08 07:27:27 PM UTC 25
Finished Feb 08 07:27:40 PM UTC 25
Peak memory 263212 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo
/hw/dv/tools/sim.tcl +ntb_random_seed=1752509688 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_class
es_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default.vdb -c
m_log /dev/null -cm_name 15.alert_handler_random_classes.1752509688
Directory /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/15.alert_handler_random_classes/latest

Test location /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default/15.alert_handler_sig_int_fail.162782042
Short name T43
Test name
Test status
Simulation time 399839839 ps
CPU time 25.55 seconds
Started Feb 08 07:27:55 PM UTC 25
Finished Feb 08 07:28:22 PM UTC 25
Peak memory 269548 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo
/hw/dv/tools/sim.tcl +ntb_random_seed=162782042 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default.vdb -cm_l
og /dev/null -cm_name 15.alert_handler_sig_int_fail.162782042
Directory /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/15.alert_handler_sig_int_fail/latest

Test location /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default/15.alert_handler_smoke.2923881439
Short name T427
Test name
Test status
Simulation time 457662085 ps
CPU time 43.38 seconds
Started Feb 08 07:26:39 PM UTC 25
Finished Feb 08 07:27:24 PM UTC 25
Peak memory 269544 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo
/hw/dv/tools/sim.tcl +ntb_random_seed=2923881439 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default.vdb -cm_log /de
v/null -cm_name 15.alert_handler_smoke.2923881439
Directory /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/15.alert_handler_smoke/latest

Test location /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default/15.alert_handler_stress_all.3906053327
Short name T69
Test name
Test status
Simulation time 27064292109 ps
CPU time 1579.87 seconds
Started Feb 08 07:29:30 PM UTC 25
Finished Feb 08 07:56:09 PM UTC 25
Peak memory 302116 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3906053327 -assert nopostproc +UVM_TESTNAME=ale
rt_handler_base_test +UVM_TEST_SEQ=alert_handler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os
_regression/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_stress_all.3906053327
Directory /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/15.alert_handler_stress_all/latest

Test location /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default/15.alert_handler_stress_all_with_rand_reset.2546521825
Short name T293
Test name
Test status
Simulation time 81929247474 ps
CPU time 9276.54 seconds
Started Feb 08 07:29:45 PM UTC 25
Finished Feb 08 10:06:03 PM UTC 25
Peak memory 403372 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=ale
rt_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=25465
21825 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_stress_al
l_with_rand_reset.2546521825
Directory /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/15.alert_handler_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default/16.alert_handler_alert_accum_saturation.713357819
Short name T258
Test name
Test status
Simulation time 78864983 ps
CPU time 7.14 seconds
Started Feb 08 07:32:27 PM UTC 25
Finished Feb 08 07:32:35 PM UTC 25
Peak memory 263336 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
paces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=713357819 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ale
rt_accum_saturation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/covera
ge/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_alert_accum_saturation.713357819
Directory /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/16.alert_handler_alert_accum_saturation/latest

Test location /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default/16.alert_handler_entropy.2271686001
Short name T476
Test name
Test status
Simulation time 171728429209 ps
CPU time 1707.03 seconds
Started Feb 08 07:31:27 PM UTC 25
Finished Feb 08 08:00:13 PM UTC 25
Peak memory 285828 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2271686001 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST
_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_entropy.2271686001
Directory /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/16.alert_handler_entropy/latest

Test location /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default/16.alert_handler_entropy_stress.1695292802
Short name T433
Test name
Test status
Simulation time 402215239 ps
CPU time 18.15 seconds
Started Feb 08 07:32:06 PM UTC 25
Finished Feb 08 07:32:26 PM UTC 25
Peak memory 263408 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
paces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1695292802 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_en
tropy_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 16.alert_handler_entropy_stress.1695292802
Directory /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/16.alert_handler_entropy_stress/latest

Test location /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default/16.alert_handler_esc_alert_accum.889547709
Short name T435
Test name
Test status
Simulation time 13370778761 ps
CPU time 115.21 seconds
Started Feb 08 07:30:57 PM UTC 25
Finished Feb 08 07:32:55 PM UTC 25
Peak memory 269348 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo
/hw/dv/tools/sim.tcl +ntb_random_seed=889547709 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_acc
um_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default.vdb -c
m_log /dev/null -cm_name 16.alert_handler_esc_alert_accum.889547709
Directory /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/16.alert_handler_esc_alert_accum/latest

Test location /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default/16.alert_handler_esc_intr_timeout.4275146537
Short name T432
Test name
Test status
Simulation time 331568898 ps
CPU time 45.03 seconds
Started Feb 08 07:30:46 PM UTC 25
Finished Feb 08 07:31:33 PM UTC 25
Peak memory 269288 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo
/hw/dv/tools/sim.tcl +ntb_random_seed=4275146537 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_tim
eout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 16.alert_handler_esc_intr_timeout.4275146537
Directory /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/16.alert_handler_esc_intr_timeout/latest

Test location /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default/16.alert_handler_lpg.2647730575
Short name T370
Test name
Test status
Simulation time 43659247120 ps
CPU time 1539.75 seconds
Started Feb 08 07:31:36 PM UTC 25
Finished Feb 08 07:57:33 PM UTC 25
Peak memory 285928 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2647730575 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST
_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_lpg.2647730575
Directory /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/16.alert_handler_lpg/latest

Test location /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default/16.alert_handler_lpg_stub_clk.781896716
Short name T455
Test name
Test status
Simulation time 12939341809 ps
CPU time 1159.99 seconds
Started Feb 08 07:31:37 PM UTC 25
Finished Feb 08 07:51:10 PM UTC 25
Peak memory 296232 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=781896716 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_
SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/alert_handler-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_lpg_stub_clk.781896716
Directory /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/16.alert_handler_lpg_stub_clk/latest

Test location /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default/16.alert_handler_ping_timeout.1049809844
Short name T352
Test name
Test status
Simulation time 135901650192 ps
CPU time 490.09 seconds
Started Feb 08 07:31:36 PM UTC 25
Finished Feb 08 07:39:53 PM UTC 25
Peak memory 263464 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1049809844 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST
_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/alert_handler-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_ping_timeout.1049809844
Directory /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/16.alert_handler_ping_timeout/latest

Test location /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default/16.alert_handler_random_alerts.647828856
Short name T63
Test name
Test status
Simulation time 1194148101 ps
CPU time 38.87 seconds
Started Feb 08 07:29:58 PM UTC 25
Finished Feb 08 07:30:39 PM UTC 25
Peak memory 269356 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo
/hw/dv/tools/sim.tcl +ntb_random_seed=647828856 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default.vdb -cm_
log /dev/null -cm_name 16.alert_handler_random_alerts.647828856
Directory /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/16.alert_handler_random_alerts/latest

Test location /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default/16.alert_handler_random_classes.3811423160
Short name T121
Test name
Test status
Simulation time 589384691 ps
CPU time 44.95 seconds
Started Feb 08 07:30:40 PM UTC 25
Finished Feb 08 07:31:26 PM UTC 25
Peak memory 263404 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo
/hw/dv/tools/sim.tcl +ntb_random_seed=3811423160 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_class
es_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default.vdb -c
m_log /dev/null -cm_name 16.alert_handler_random_classes.3811423160
Directory /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/16.alert_handler_random_classes/latest

Test location /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default/16.alert_handler_sig_int_fail.2546713158
Short name T342
Test name
Test status
Simulation time 236420874 ps
CPU time 41.54 seconds
Started Feb 08 07:31:23 PM UTC 25
Finished Feb 08 07:32:06 PM UTC 25
Peak memory 269552 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo
/hw/dv/tools/sim.tcl +ntb_random_seed=2546713158 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default.vdb -cm_
log /dev/null -cm_name 16.alert_handler_sig_int_fail.2546713158
Directory /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/16.alert_handler_sig_int_fail/latest

Test location /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default/16.alert_handler_smoke.243814565
Short name T220
Test name
Test status
Simulation time 37935578 ps
CPU time 7.18 seconds
Started Feb 08 07:29:49 PM UTC 25
Finished Feb 08 07:29:58 PM UTC 25
Peak memory 263208 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo
/hw/dv/tools/sim.tcl +ntb_random_seed=243814565 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev
/null -cm_name 16.alert_handler_smoke.243814565
Directory /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/16.alert_handler_smoke/latest

Test location /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default/17.alert_handler_alert_accum_saturation.241817307
Short name T259
Test name
Test status
Simulation time 138895763 ps
CPU time 5.38 seconds
Started Feb 08 07:35:54 PM UTC 25
Finished Feb 08 07:36:01 PM UTC 25
Peak memory 263336 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
paces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=241817307 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ale
rt_accum_saturation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/covera
ge/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_alert_accum_saturation.241817307
Directory /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/17.alert_handler_alert_accum_saturation/latest

Test location /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default/17.alert_handler_entropy.2875240473
Short name T494
Test name
Test status
Simulation time 30144014909 ps
CPU time 1881.15 seconds
Started Feb 08 07:34:46 PM UTC 25
Finished Feb 08 08:06:29 PM UTC 25
Peak memory 296232 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2875240473 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST
_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_entropy.2875240473
Directory /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/17.alert_handler_entropy/latest

Test location /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default/17.alert_handler_entropy_stress.804806666
Short name T271
Test name
Test status
Simulation time 398093154 ps
CPU time 28.86 seconds
Started Feb 08 07:35:51 PM UTC 25
Finished Feb 08 07:36:21 PM UTC 25
Peak memory 263404 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
paces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=804806666 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ent
ropy_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 17.alert_handler_entropy_stress.804806666
Directory /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/17.alert_handler_entropy_stress/latest

Test location /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default/17.alert_handler_esc_alert_accum.3709019540
Short name T439
Test name
Test status
Simulation time 1047389625 ps
CPU time 133.52 seconds
Started Feb 08 07:33:31 PM UTC 25
Finished Feb 08 07:35:48 PM UTC 25
Peak memory 269284 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo
/hw/dv/tools/sim.tcl +ntb_random_seed=3709019540 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_ac
cum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 17.alert_handler_esc_alert_accum.3709019540
Directory /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/17.alert_handler_esc_alert_accum/latest

Test location /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default/17.alert_handler_esc_intr_timeout.1714139208
Short name T102
Test name
Test status
Simulation time 2210121410 ps
CPU time 103.22 seconds
Started Feb 08 07:32:59 PM UTC 25
Finished Feb 08 07:34:45 PM UTC 25
Peak memory 269420 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo
/hw/dv/tools/sim.tcl +ntb_random_seed=1714139208 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_tim
eout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 17.alert_handler_esc_intr_timeout.1714139208
Directory /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/17.alert_handler_esc_intr_timeout/latest

Test location /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default/17.alert_handler_lpg.2775423657
Short name T366
Test name
Test status
Simulation time 217821709085 ps
CPU time 3315.66 seconds
Started Feb 08 07:35:20 PM UTC 25
Finished Feb 08 08:31:13 PM UTC 25
Peak memory 302812 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2775423657 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST
_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_lpg.2775423657
Directory /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/17.alert_handler_lpg/latest

Test location /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default/17.alert_handler_lpg_stub_clk.983189875
Short name T311
Test name
Test status
Simulation time 32782836340 ps
CPU time 1982.87 seconds
Started Feb 08 07:35:49 PM UTC 25
Finished Feb 08 08:09:14 PM UTC 25
Peak memory 285800 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=983189875 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_
SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/alert_handler-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_lpg_stub_clk.983189875
Directory /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/17.alert_handler_lpg_stub_clk/latest

Test location /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default/17.alert_handler_ping_timeout.2159161301
Short name T113
Test name
Test status
Simulation time 30159733920 ps
CPU time 443.76 seconds
Started Feb 08 07:34:50 PM UTC 25
Finished Feb 08 07:42:20 PM UTC 25
Peak memory 269608 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2159161301 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST
_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/alert_handler-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_ping_timeout.2159161301
Directory /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/17.alert_handler_ping_timeout/latest

Test location /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default/17.alert_handler_random_alerts.1854814290
Short name T438
Test name
Test status
Simulation time 1034369930 ps
CPU time 62.46 seconds
Started Feb 08 07:32:36 PM UTC 25
Finished Feb 08 07:33:40 PM UTC 25
Peak memory 269552 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo
/hw/dv/tools/sim.tcl +ntb_random_seed=1854814290 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alert
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default.vdb -cm
_log /dev/null -cm_name 17.alert_handler_random_alerts.1854814290
Directory /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/17.alert_handler_random_alerts/latest

Test location /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default/17.alert_handler_random_classes.1567480823
Short name T437
Test name
Test status
Simulation time 324170404 ps
CPU time 33.32 seconds
Started Feb 08 07:32:56 PM UTC 25
Finished Feb 08 07:33:31 PM UTC 25
Peak memory 269280 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo
/hw/dv/tools/sim.tcl +ntb_random_seed=1567480823 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_class
es_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default.vdb -c
m_log /dev/null -cm_name 17.alert_handler_random_classes.1567480823
Directory /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/17.alert_handler_random_classes/latest

Test location /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default/17.alert_handler_sig_int_fail.4183402232
Short name T122
Test name
Test status
Simulation time 722520380 ps
CPU time 66 seconds
Started Feb 08 07:33:41 PM UTC 25
Finished Feb 08 07:34:49 PM UTC 25
Peak memory 263144 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo
/hw/dv/tools/sim.tcl +ntb_random_seed=4183402232 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default.vdb -cm_
log /dev/null -cm_name 17.alert_handler_sig_int_fail.4183402232
Directory /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/17.alert_handler_sig_int_fail/latest

Test location /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default/17.alert_handler_smoke.2984004042
Short name T436
Test name
Test status
Simulation time 219367348 ps
CPU time 23.39 seconds
Started Feb 08 07:32:34 PM UTC 25
Finished Feb 08 07:32:58 PM UTC 25
Peak memory 269280 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo
/hw/dv/tools/sim.tcl +ntb_random_seed=2984004042 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default.vdb -cm_log /de
v/null -cm_name 17.alert_handler_smoke.2984004042
Directory /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/17.alert_handler_smoke/latest

Test location /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default/17.alert_handler_stress_all.1103180865
Short name T461
Test name
Test status
Simulation time 8621166017 ps
CPU time 1060.5 seconds
Started Feb 08 07:35:51 PM UTC 25
Finished Feb 08 07:53:45 PM UTC 25
Peak memory 286000 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1103180865 -assert nopostproc +UVM_TESTNAME=ale
rt_handler_base_test +UVM_TEST_SEQ=alert_handler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os
_regression/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_stress_all.1103180865
Directory /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/17.alert_handler_stress_all/latest

Test location /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default/18.alert_handler_alert_accum_saturation.288586085
Short name T260
Test name
Test status
Simulation time 88702731 ps
CPU time 6.23 seconds
Started Feb 08 07:40:50 PM UTC 25
Finished Feb 08 07:40:57 PM UTC 25
Peak memory 263664 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
paces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=288586085 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ale
rt_accum_saturation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/covera
ge/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_alert_accum_saturation.288586085
Directory /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/18.alert_handler_alert_accum_saturation/latest

Test location /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default/18.alert_handler_entropy.2335996583
Short name T469
Test name
Test status
Simulation time 93214681766 ps
CPU time 996.78 seconds
Started Feb 08 07:39:32 PM UTC 25
Finished Feb 08 07:56:22 PM UTC 25
Peak memory 285996 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2335996583 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST
_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_entropy.2335996583
Directory /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/18.alert_handler_entropy/latest

Test location /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default/18.alert_handler_entropy_stress.960870002
Short name T440
Test name
Test status
Simulation time 372116681 ps
CPU time 31.94 seconds
Started Feb 08 07:39:53 PM UTC 25
Finished Feb 08 07:40:27 PM UTC 25
Peak memory 263212 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
paces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=960870002 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ent
ropy_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 18.alert_handler_entropy_stress.960870002
Directory /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/18.alert_handler_entropy_stress/latest

Test location /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default/18.alert_handler_esc_alert_accum.2324642995
Short name T441
Test name
Test status
Simulation time 8961885076 ps
CPU time 137.34 seconds
Started Feb 08 07:38:29 PM UTC 25
Finished Feb 08 07:40:49 PM UTC 25
Peak memory 269616 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo
/hw/dv/tools/sim.tcl +ntb_random_seed=2324642995 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_ac
cum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 18.alert_handler_esc_alert_accum.2324642995
Directory /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/18.alert_handler_esc_alert_accum/latest

Test location /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default/18.alert_handler_esc_intr_timeout.2456697511
Short name T275
Test name
Test status
Simulation time 1339626754 ps
CPU time 43.24 seconds
Started Feb 08 07:37:52 PM UTC 25
Finished Feb 08 07:38:37 PM UTC 25
Peak memory 263408 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo
/hw/dv/tools/sim.tcl +ntb_random_seed=2456697511 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_tim
eout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 18.alert_handler_esc_intr_timeout.2456697511
Directory /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/18.alert_handler_esc_intr_timeout/latest

Test location /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default/18.alert_handler_lpg.3512658397
Short name T373
Test name
Test status
Simulation time 344530691175 ps
CPU time 3456.09 seconds
Started Feb 08 07:39:40 PM UTC 25
Finished Feb 08 08:37:54 PM UTC 25
Peak memory 305128 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3512658397 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST
_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_lpg.3512658397
Directory /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/18.alert_handler_lpg/latest

Test location /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default/18.alert_handler_lpg_stub_clk.516792182
Short name T112
Test name
Test status
Simulation time 17194351810 ps
CPU time 1312.95 seconds
Started Feb 08 07:39:42 PM UTC 25
Finished Feb 08 08:01:51 PM UTC 25
Peak memory 285756 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=516792182 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_
SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/alert_handler-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_lpg_stub_clk.516792182
Directory /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/18.alert_handler_lpg_stub_clk/latest

Test location /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default/18.alert_handler_random_alerts.1915614542
Short name T273
Test name
Test status
Simulation time 118419326 ps
CPU time 19.36 seconds
Started Feb 08 07:36:44 PM UTC 25
Finished Feb 08 07:37:04 PM UTC 25
Peak memory 269284 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo
/hw/dv/tools/sim.tcl +ntb_random_seed=1915614542 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alert
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default.vdb -cm
_log /dev/null -cm_name 18.alert_handler_random_alerts.1915614542
Directory /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/18.alert_handler_random_alerts/latest

Test location /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default/18.alert_handler_random_classes.2863164227
Short name T274
Test name
Test status
Simulation time 943989883 ps
CPU time 44.29 seconds
Started Feb 08 07:37:05 PM UTC 25
Finished Feb 08 07:37:51 PM UTC 25
Peak memory 263136 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo
/hw/dv/tools/sim.tcl +ntb_random_seed=2863164227 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_class
es_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default.vdb -c
m_log /dev/null -cm_name 18.alert_handler_random_classes.2863164227
Directory /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/18.alert_handler_random_classes/latest

Test location /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default/18.alert_handler_sig_int_fail.431445173
Short name T346
Test name
Test status
Simulation time 2338322286 ps
CPU time 61.32 seconds
Started Feb 08 07:38:38 PM UTC 25
Finished Feb 08 07:39:41 PM UTC 25
Peak memory 263308 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo
/hw/dv/tools/sim.tcl +ntb_random_seed=431445173 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default.vdb -cm_l
og /dev/null -cm_name 18.alert_handler_sig_int_fail.431445173
Directory /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/18.alert_handler_sig_int_fail/latest

Test location /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default/18.alert_handler_smoke.1599322339
Short name T272
Test name
Test status
Simulation time 527820252 ps
CPU time 18.56 seconds
Started Feb 08 07:36:22 PM UTC 25
Finished Feb 08 07:36:42 PM UTC 25
Peak memory 263144 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo
/hw/dv/tools/sim.tcl +ntb_random_seed=1599322339 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default.vdb -cm_log /de
v/null -cm_name 18.alert_handler_smoke.1599322339
Directory /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/18.alert_handler_smoke/latest

Test location /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default/18.alert_handler_stress_all.104650050
Short name T70
Test name
Test status
Simulation time 403736472836 ps
CPU time 2343.74 seconds
Started Feb 08 07:40:28 PM UTC 25
Finished Feb 08 08:19:57 PM UTC 25
Peak memory 303596 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=104650050 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_
regression/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_stress_all.104650050
Directory /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/18.alert_handler_stress_all/latest

Test location /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default/19.alert_handler_alert_accum_saturation.297897979
Short name T261
Test name
Test status
Simulation time 19568087 ps
CPU time 4.47 seconds
Started Feb 08 07:44:25 PM UTC 25
Finished Feb 08 07:44:30 PM UTC 25
Peak memory 263332 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
paces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=297897979 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ale
rt_accum_saturation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/covera
ge/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_alert_accum_saturation.297897979
Directory /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/19.alert_handler_alert_accum_saturation/latest

Test location /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default/19.alert_handler_entropy.2806719847
Short name T125
Test name
Test status
Simulation time 8677862436 ps
CPU time 1254.52 seconds
Started Feb 08 07:42:38 PM UTC 25
Finished Feb 08 08:03:49 PM UTC 25
Peak memory 285796 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2806719847 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST
_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_entropy.2806719847
Directory /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/19.alert_handler_entropy/latest

Test location /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default/19.alert_handler_entropy_stress.858031732
Short name T446
Test name
Test status
Simulation time 500195137 ps
CPU time 21 seconds
Started Feb 08 07:44:01 PM UTC 25
Finished Feb 08 07:44:24 PM UTC 25
Peak memory 263472 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
paces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=858031732 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ent
ropy_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 19.alert_handler_entropy_stress.858031732
Directory /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/19.alert_handler_entropy_stress/latest

Test location /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default/19.alert_handler_esc_alert_accum.3635331474
Short name T449
Test name
Test status
Simulation time 11167812401 ps
CPU time 331.1 seconds
Started Feb 08 07:42:23 PM UTC 25
Finished Feb 08 07:47:58 PM UTC 25
Peak memory 269620 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo
/hw/dv/tools/sim.tcl +ntb_random_seed=3635331474 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_ac
cum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 19.alert_handler_esc_alert_accum.3635331474
Directory /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/19.alert_handler_esc_alert_accum/latest

Test location /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default/19.alert_handler_esc_intr_timeout.1313152418
Short name T444
Test name
Test status
Simulation time 127653163 ps
CPU time 13.9 seconds
Started Feb 08 07:42:20 PM UTC 25
Finished Feb 08 07:42:36 PM UTC 25
Peak memory 263276 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo
/hw/dv/tools/sim.tcl +ntb_random_seed=1313152418 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_tim
eout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 19.alert_handler_esc_intr_timeout.1313152418
Directory /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/19.alert_handler_esc_intr_timeout/latest

Test location /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default/19.alert_handler_lpg.782903334
Short name T385
Test name
Test status
Simulation time 19422630451 ps
CPU time 1675.02 seconds
Started Feb 08 07:43:40 PM UTC 25
Finished Feb 08 08:11:54 PM UTC 25
Peak memory 296004 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=782903334 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_
SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/cove
rage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_lpg.782903334
Directory /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/19.alert_handler_lpg/latest

Test location /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default/19.alert_handler_lpg_stub_clk.3417252815
Short name T489
Test name
Test status
Simulation time 33763420192 ps
CPU time 1257.62 seconds
Started Feb 08 07:43:40 PM UTC 25
Finished Feb 08 08:04:53 PM UTC 25
Peak memory 285800 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3417252815 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST
_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/alert_handler-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_lpg_stub_clk.3417252815
Directory /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/19.alert_handler_lpg_stub_clk/latest

Test location /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default/19.alert_handler_ping_timeout.2375153241
Short name T350
Test name
Test status
Simulation time 26459914332 ps
CPU time 573.54 seconds
Started Feb 08 07:43:08 PM UTC 25
Finished Feb 08 07:52:49 PM UTC 25
Peak memory 263204 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2375153241 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST
_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/alert_handler-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_ping_timeout.2375153241
Directory /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/19.alert_handler_ping_timeout/latest

Test location /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default/19.alert_handler_random_alerts.3909432799
Short name T443
Test name
Test status
Simulation time 522860876 ps
CPU time 26.04 seconds
Started Feb 08 07:41:54 PM UTC 25
Finished Feb 08 07:42:21 PM UTC 25
Peak memory 263140 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo
/hw/dv/tools/sim.tcl +ntb_random_seed=3909432799 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alert
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default.vdb -cm
_log /dev/null -cm_name 19.alert_handler_random_alerts.3909432799
Directory /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/19.alert_handler_random_alerts/latest

Test location /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default/19.alert_handler_random_classes.3287214954
Short name T445
Test name
Test status
Simulation time 818848655 ps
CPU time 78.01 seconds
Started Feb 08 07:42:18 PM UTC 25
Finished Feb 08 07:43:38 PM UTC 25
Peak memory 269420 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo
/hw/dv/tools/sim.tcl +ntb_random_seed=3287214954 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_class
es_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default.vdb -c
m_log /dev/null -cm_name 19.alert_handler_random_classes.3287214954
Directory /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/19.alert_handler_random_classes/latest

Test location /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default/19.alert_handler_smoke.2463269511
Short name T442
Test name
Test status
Simulation time 50009489 ps
CPU time 6.58 seconds
Started Feb 08 07:41:45 PM UTC 25
Finished Feb 08 07:41:53 PM UTC 25
Peak memory 265184 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo
/hw/dv/tools/sim.tcl +ntb_random_seed=2463269511 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default.vdb -cm_log /de
v/null -cm_name 19.alert_handler_smoke.2463269511
Directory /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/19.alert_handler_smoke/latest

Test location /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default/19.alert_handler_stress_all.610238619
Short name T296
Test name
Test status
Simulation time 3081408319 ps
CPU time 79.34 seconds
Started Feb 08 07:44:25 PM UTC 25
Finished Feb 08 07:45:46 PM UTC 25
Peak memory 269612 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=610238619 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_
regression/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_stress_all.610238619
Directory /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/19.alert_handler_stress_all/latest

Test location /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default/2.alert_handler_alert_accum_saturation.1215841653
Short name T25
Test name
Test status
Simulation time 32006976 ps
CPU time 4.87 seconds
Started Feb 08 07:05:16 PM UTC 25
Finished Feb 08 07:05:23 PM UTC 25
Peak memory 263332 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
paces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1215841653 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_al
ert_accum_saturation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/cover
age/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_alert_accum_saturation.1215841653
Directory /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/2.alert_handler_alert_accum_saturation/latest

Test location /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default/2.alert_handler_entropy.429750332
Short name T345
Test name
Test status
Simulation time 23780163885 ps
CPU time 1568.04 seconds
Started Feb 08 07:05:05 PM UTC 25
Finished Feb 08 07:31:33 PM UTC 25
Peak memory 285720 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=429750332 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_
SEQ=alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/
coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_entropy.429750332
Directory /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/2.alert_handler_entropy/latest

Test location /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default/2.alert_handler_entropy_stress.2623547118
Short name T8
Test name
Test status
Simulation time 1104421816 ps
CPU time 59.33 seconds
Started Feb 08 07:05:12 PM UTC 25
Finished Feb 08 07:06:13 PM UTC 25
Peak memory 263140 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
paces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2623547118 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_en
tropy_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 2.alert_handler_entropy_stress.2623547118
Directory /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/2.alert_handler_entropy_stress/latest

Test location /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default/2.alert_handler_esc_alert_accum.2944299040
Short name T336
Test name
Test status
Simulation time 8904612502 ps
CPU time 139.92 seconds
Started Feb 08 07:05:01 PM UTC 25
Finished Feb 08 07:07:23 PM UTC 25
Peak memory 269420 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo
/hw/dv/tools/sim.tcl +ntb_random_seed=2944299040 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_ac
cum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 2.alert_handler_esc_alert_accum.2944299040
Directory /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/2.alert_handler_esc_alert_accum/latest

Test location /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default/2.alert_handler_lpg_stub_clk.4086637088
Short name T384
Test name
Test status
Simulation time 65329388919 ps
CPU time 1785.72 seconds
Started Feb 08 07:05:11 PM UTC 25
Finished Feb 08 07:35:17 PM UTC 25
Peak memory 298016 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4086637088 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST
_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/alert_handler-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_lpg_stub_clk.4086637088
Directory /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/2.alert_handler_lpg_stub_clk/latest

Test location /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default/2.alert_handler_ping_timeout.3616674198
Short name T130
Test name
Test status
Simulation time 9455298944 ps
CPU time 399.65 seconds
Started Feb 08 07:05:05 PM UTC 25
Finished Feb 08 07:11:50 PM UTC 25
Peak memory 263200 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3616674198 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST
_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/alert_handler-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_ping_timeout.3616674198
Directory /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/2.alert_handler_ping_timeout/latest

Test location /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default/2.alert_handler_random_alerts.2355304344
Short name T29
Test name
Test status
Simulation time 653317389 ps
CPU time 38.76 seconds
Started Feb 08 07:04:57 PM UTC 25
Finished Feb 08 07:05:37 PM UTC 25
Peak memory 269544 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo
/hw/dv/tools/sim.tcl +ntb_random_seed=2355304344 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alert
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default.vdb -cm
_log /dev/null -cm_name 2.alert_handler_random_alerts.2355304344
Directory /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/2.alert_handler_random_alerts/latest

Test location /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default/2.alert_handler_sec_cm.2358212834
Short name T10
Test name
Test status
Simulation time 832772114 ps
CPU time 34.19 seconds
Started Feb 08 07:05:23 PM UTC 25
Finished Feb 08 07:05:59 PM UTC 25
Peak memory 295340 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2358212834 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=a
lert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/covera
ge/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_sec_cm.2358212834
Directory /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/2.alert_handler_sec_cm/latest

Test location /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default/2.alert_handler_sig_int_fail.877303326
Short name T27
Test name
Test status
Simulation time 1144480568 ps
CPU time 25.15 seconds
Started Feb 08 07:05:02 PM UTC 25
Finished Feb 08 07:05:28 PM UTC 25
Peak memory 269292 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo
/hw/dv/tools/sim.tcl +ntb_random_seed=877303326 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default.vdb -cm_l
og /dev/null -cm_name 2.alert_handler_sig_int_fail.877303326
Directory /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/2.alert_handler_sig_int_fail/latest

Test location /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default/2.alert_handler_smoke.1278307378
Short name T30
Test name
Test status
Simulation time 2950072152 ps
CPU time 56.97 seconds
Started Feb 08 07:04:54 PM UTC 25
Finished Feb 08 07:05:52 PM UTC 25
Peak memory 263200 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo
/hw/dv/tools/sim.tcl +ntb_random_seed=1278307378 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default.vdb -cm_log /de
v/null -cm_name 2.alert_handler_smoke.1278307378
Directory /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/2.alert_handler_smoke/latest

Test location /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default/2.alert_handler_stress_all.1228617097
Short name T104
Test name
Test status
Simulation time 80582490198 ps
CPU time 2341.93 seconds
Started Feb 08 07:05:13 PM UTC 25
Finished Feb 08 07:44:40 PM UTC 25
Peak memory 300772 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1228617097 -assert nopostproc +UVM_TESTNAME=ale
rt_handler_base_test +UVM_TEST_SEQ=alert_handler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os
_regression/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_stress_all.1228617097
Directory /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/2.alert_handler_stress_all/latest

Test location /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default/20.alert_handler_entropy.399612481
Short name T513
Test name
Test status
Simulation time 53977883050 ps
CPU time 1552.24 seconds
Started Feb 08 07:47:41 PM UTC 25
Finished Feb 08 08:13:51 PM UTC 25
Peak memory 302116 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=399612481 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_
SEQ=alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/
coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_entropy.399612481
Directory /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/20.alert_handler_entropy/latest

Test location /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default/20.alert_handler_esc_alert_accum.2077130606
Short name T450
Test name
Test status
Simulation time 4089411478 ps
CPU time 131.55 seconds
Started Feb 08 07:46:52 PM UTC 25
Finished Feb 08 07:49:07 PM UTC 25
Peak memory 269352 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo
/hw/dv/tools/sim.tcl +ntb_random_seed=2077130606 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_ac
cum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 20.alert_handler_esc_alert_accum.2077130606
Directory /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/20.alert_handler_esc_alert_accum/latest

Test location /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default/20.alert_handler_esc_intr_timeout.1272737600
Short name T448
Test name
Test status
Simulation time 214395760 ps
CPU time 12.47 seconds
Started Feb 08 07:46:37 PM UTC 25
Finished Feb 08 07:46:51 PM UTC 25
Peak memory 263140 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo
/hw/dv/tools/sim.tcl +ntb_random_seed=1272737600 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_tim
eout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 20.alert_handler_esc_intr_timeout.1272737600
Directory /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/20.alert_handler_esc_intr_timeout/latest

Test location /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default/20.alert_handler_lpg.1395225889
Short name T367
Test name
Test status
Simulation time 24736663083 ps
CPU time 1262.76 seconds
Started Feb 08 07:48:55 PM UTC 25
Finished Feb 08 08:10:11 PM UTC 25
Peak memory 285724 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1395225889 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST
_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_lpg.1395225889
Directory /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/20.alert_handler_lpg/latest

Test location /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default/20.alert_handler_lpg_stub_clk.224457188
Short name T527
Test name
Test status
Simulation time 82668660034 ps
CPU time 1794.8 seconds
Started Feb 08 07:49:04 PM UTC 25
Finished Feb 08 08:19:20 PM UTC 25
Peak memory 302372 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=224457188 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_
SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/alert_handler-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_lpg_stub_clk.224457188
Directory /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/20.alert_handler_lpg_stub_clk/latest

Test location /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default/20.alert_handler_random_alerts.595876125
Short name T66
Test name
Test status
Simulation time 2458995791 ps
CPU time 55.99 seconds
Started Feb 08 07:45:39 PM UTC 25
Finished Feb 08 07:46:37 PM UTC 25
Peak memory 269420 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo
/hw/dv/tools/sim.tcl +ntb_random_seed=595876125 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default.vdb -cm_
log /dev/null -cm_name 20.alert_handler_random_alerts.595876125
Directory /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/20.alert_handler_random_alerts/latest

Test location /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default/20.alert_handler_random_classes.4206708223
Short name T67
Test name
Test status
Simulation time 2640957584 ps
CPU time 110.89 seconds
Started Feb 08 07:45:47 PM UTC 25
Finished Feb 08 07:47:40 PM UTC 25
Peak memory 263468 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo
/hw/dv/tools/sim.tcl +ntb_random_seed=4206708223 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_class
es_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default.vdb -c
m_log /dev/null -cm_name 20.alert_handler_random_classes.4206708223
Directory /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/20.alert_handler_random_classes/latest

Test location /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default/20.alert_handler_smoke.3645213405
Short name T447
Test name
Test status
Simulation time 2094788950 ps
CPU time 54.13 seconds
Started Feb 08 07:44:42 PM UTC 25
Finished Feb 08 07:45:38 PM UTC 25
Peak memory 269280 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo
/hw/dv/tools/sim.tcl +ntb_random_seed=3645213405 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default.vdb -cm_log /de
v/null -cm_name 20.alert_handler_smoke.3645213405
Directory /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/20.alert_handler_smoke/latest

Test location /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default/20.alert_handler_stress_all.1728606792
Short name T288
Test name
Test status
Simulation time 623038916 ps
CPU time 63.55 seconds
Started Feb 08 07:49:08 PM UTC 25
Finished Feb 08 07:50:13 PM UTC 25
Peak memory 269288 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1728606792 -assert nopostproc +UVM_TESTNAME=ale
rt_handler_base_test +UVM_TEST_SEQ=alert_handler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os
_regression/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_stress_all.1728606792
Directory /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/20.alert_handler_stress_all/latest

Test location /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default/21.alert_handler_entropy.4172748921
Short name T492
Test name
Test status
Simulation time 8855844319 ps
CPU time 871.24 seconds
Started Feb 08 07:51:04 PM UTC 25
Finished Feb 08 08:05:46 PM UTC 25
Peak memory 285992 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4172748921 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST
_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_entropy.4172748921
Directory /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/21.alert_handler_entropy/latest

Test location /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default/21.alert_handler_esc_alert_accum.3022301235
Short name T460
Test name
Test status
Simulation time 3860074905 ps
CPU time 129.1 seconds
Started Feb 08 07:50:30 PM UTC 25
Finished Feb 08 07:52:42 PM UTC 25
Peak memory 269424 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo
/hw/dv/tools/sim.tcl +ntb_random_seed=3022301235 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_ac
cum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 21.alert_handler_esc_alert_accum.3022301235
Directory /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/21.alert_handler_esc_alert_accum/latest

Test location /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default/21.alert_handler_esc_intr_timeout.1595060208
Short name T458
Test name
Test status
Simulation time 1047963569 ps
CPU time 93.42 seconds
Started Feb 08 07:50:14 PM UTC 25
Finished Feb 08 07:51:50 PM UTC 25
Peak memory 269284 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo
/hw/dv/tools/sim.tcl +ntb_random_seed=1595060208 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_tim
eout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 21.alert_handler_esc_intr_timeout.1595060208
Directory /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/21.alert_handler_esc_intr_timeout/latest

Test location /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default/21.alert_handler_lpg.1994551263
Short name T379
Test name
Test status
Simulation time 7644431251 ps
CPU time 935.67 seconds
Started Feb 08 07:51:42 PM UTC 25
Finished Feb 08 08:07:29 PM UTC 25
Peak memory 285996 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1994551263 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST
_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_lpg.1994551263
Directory /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/21.alert_handler_lpg/latest

Test location /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default/21.alert_handler_lpg_stub_clk.275036974
Short name T556
Test name
Test status
Simulation time 44995470304 ps
CPU time 2569.48 seconds
Started Feb 08 07:51:44 PM UTC 25
Finished Feb 08 08:35:01 PM UTC 25
Peak memory 304856 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=275036974 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_
SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/alert_handler-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_lpg_stub_clk.275036974
Directory /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/21.alert_handler_lpg_stub_clk/latest

Test location /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default/21.alert_handler_random_alerts.1918033755
Short name T457
Test name
Test status
Simulation time 5534727751 ps
CPU time 101.58 seconds
Started Feb 08 07:50:05 PM UTC 25
Finished Feb 08 07:51:49 PM UTC 25
Peak memory 269420 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo
/hw/dv/tools/sim.tcl +ntb_random_seed=1918033755 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alert
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default.vdb -cm
_log /dev/null -cm_name 21.alert_handler_random_alerts.1918033755
Directory /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/21.alert_handler_random_alerts/latest

Test location /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default/21.alert_handler_smoke.1152140134
Short name T452
Test name
Test status
Simulation time 409973827 ps
CPU time 40.27 seconds
Started Feb 08 07:49:22 PM UTC 25
Finished Feb 08 07:50:03 PM UTC 25
Peak memory 269544 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo
/hw/dv/tools/sim.tcl +ntb_random_seed=1152140134 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default.vdb -cm_log /de
v/null -cm_name 21.alert_handler_smoke.1152140134
Directory /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/21.alert_handler_smoke/latest

Test location /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default/21.alert_handler_stress_all.861813594
Short name T347
Test name
Test status
Simulation time 3023295158 ps
CPU time 79.86 seconds
Started Feb 08 07:51:49 PM UTC 25
Finished Feb 08 07:53:12 PM UTC 25
Peak memory 269352 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=861813594 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_
regression/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_stress_all.861813594
Directory /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/21.alert_handler_stress_all/latest

Test location /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default/21.alert_handler_stress_all_with_rand_reset.68378467
Short name T222
Test name
Test status
Simulation time 99517555333 ps
CPU time 10071.3 seconds
Started Feb 08 07:51:50 PM UTC 25
Finished Feb 08 10:41:37 PM UTC 25
Peak memory 370868 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=ale
rt_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=68378
467 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_stress_all_
with_rand_reset.68378467
Directory /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/21.alert_handler_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default/22.alert_handler_entropy.1815863432
Short name T538
Test name
Test status
Simulation time 66465138458 ps
CPU time 2033.56 seconds
Started Feb 08 07:53:22 PM UTC 25
Finished Feb 08 08:27:37 PM UTC 25
Peak memory 300764 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1815863432 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST
_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_entropy.1815863432
Directory /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/22.alert_handler_entropy/latest

Test location /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default/22.alert_handler_esc_alert_accum.2300439982
Short name T300
Test name
Test status
Simulation time 1562985440 ps
CPU time 121.83 seconds
Started Feb 08 07:53:05 PM UTC 25
Finished Feb 08 07:55:10 PM UTC 25
Peak memory 263408 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo
/hw/dv/tools/sim.tcl +ntb_random_seed=2300439982 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_ac
cum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 22.alert_handler_esc_alert_accum.2300439982
Directory /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/22.alert_handler_esc_alert_accum/latest

Test location /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default/22.alert_handler_esc_intr_timeout.330434735
Short name T136
Test name
Test status
Simulation time 119571327 ps
CPU time 13.39 seconds
Started Feb 08 07:52:50 PM UTC 25
Finished Feb 08 07:53:05 PM UTC 25
Peak memory 263140 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo
/hw/dv/tools/sim.tcl +ntb_random_seed=330434735 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_time
out_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 22.alert_handler_esc_intr_timeout.330434735
Directory /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/22.alert_handler_esc_intr_timeout/latest

Test location /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default/22.alert_handler_lpg.2343726826
Short name T378
Test name
Test status
Simulation time 9821592758 ps
CPU time 1026.3 seconds
Started Feb 08 07:53:49 PM UTC 25
Finished Feb 08 08:11:07 PM UTC 25
Peak memory 285728 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2343726826 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST
_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_lpg.2343726826
Directory /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/22.alert_handler_lpg/latest

Test location /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default/22.alert_handler_lpg_stub_clk.273041861
Short name T519
Test name
Test status
Simulation time 10495884122 ps
CPU time 1366.48 seconds
Started Feb 08 07:53:57 PM UTC 25
Finished Feb 08 08:17:00 PM UTC 25
Peak memory 302376 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=273041861 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_
SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/alert_handler-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_lpg_stub_clk.273041861
Directory /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/22.alert_handler_lpg_stub_clk/latest

Test location /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default/22.alert_handler_ping_timeout.3866009509
Short name T364
Test name
Test status
Simulation time 135380777240 ps
CPU time 441.36 seconds
Started Feb 08 07:53:47 PM UTC 25
Finished Feb 08 08:01:13 PM UTC 25
Peak memory 263196 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3866009509 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST
_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/alert_handler-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_ping_timeout.3866009509
Directory /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/22.alert_handler_ping_timeout/latest

Test location /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default/22.alert_handler_random_alerts.3603225008
Short name T462
Test name
Test status
Simulation time 3220951699 ps
CPU time 76.77 seconds
Started Feb 08 07:52:37 PM UTC 25
Finished Feb 08 07:53:56 PM UTC 25
Peak memory 269348 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo
/hw/dv/tools/sim.tcl +ntb_random_seed=3603225008 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alert
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default.vdb -cm
_log /dev/null -cm_name 22.alert_handler_random_alerts.3603225008
Directory /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/22.alert_handler_random_alerts/latest

Test location /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default/22.alert_handler_random_classes.491867178
Short name T281
Test name
Test status
Simulation time 1221701279 ps
CPU time 36.07 seconds
Started Feb 08 07:52:43 PM UTC 25
Finished Feb 08 07:53:21 PM UTC 25
Peak memory 269548 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo
/hw/dv/tools/sim.tcl +ntb_random_seed=491867178 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classe
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default.vdb -cm
_log /dev/null -cm_name 22.alert_handler_random_classes.491867178
Directory /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/22.alert_handler_random_classes/latest

Test location /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default/22.alert_handler_sig_int_fail.2401450130
Short name T463
Test name
Test status
Simulation time 1800850607 ps
CPU time 44.81 seconds
Started Feb 08 07:53:12 PM UTC 25
Finished Feb 08 07:53:59 PM UTC 25
Peak memory 263408 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo
/hw/dv/tools/sim.tcl +ntb_random_seed=2401450130 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default.vdb -cm_
log /dev/null -cm_name 22.alert_handler_sig_int_fail.2401450130
Directory /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/22.alert_handler_sig_int_fail/latest

Test location /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default/22.alert_handler_smoke.2302246864
Short name T459
Test name
Test status
Simulation time 1530836102 ps
CPU time 30.62 seconds
Started Feb 08 07:52:04 PM UTC 25
Finished Feb 08 07:52:36 PM UTC 25
Peak memory 269280 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo
/hw/dv/tools/sim.tcl +ntb_random_seed=2302246864 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default.vdb -cm_log /de
v/null -cm_name 22.alert_handler_smoke.2302246864
Directory /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/22.alert_handler_smoke/latest

Test location /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default/22.alert_handler_stress_all.3914851126
Short name T297
Test name
Test status
Simulation time 871300596 ps
CPU time 88.51 seconds
Started Feb 08 07:54:00 PM UTC 25
Finished Feb 08 07:55:31 PM UTC 25
Peak memory 263216 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3914851126 -assert nopostproc +UVM_TESTNAME=ale
rt_handler_base_test +UVM_TEST_SEQ=alert_handler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os
_regression/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_stress_all.3914851126
Directory /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/22.alert_handler_stress_all/latest

Test location /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default/22.alert_handler_stress_all_with_rand_reset.558317345
Short name T213
Test name
Test status
Simulation time 51035662622 ps
CPU time 1808.57 seconds
Started Feb 08 07:54:25 PM UTC 25
Finished Feb 08 08:24:53 PM UTC 25
Peak memory 300196 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=ale
rt_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=55831
7345 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_stress_all
_with_rand_reset.558317345
Directory /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/22.alert_handler_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default/23.alert_handler_entropy.2347077144
Short name T550
Test name
Test status
Simulation time 60973628115 ps
CPU time 2246.75 seconds
Started Feb 08 07:55:54 PM UTC 25
Finished Feb 08 08:33:46 PM UTC 25
Peak memory 304860 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2347077144 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST
_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_entropy.2347077144
Directory /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/23.alert_handler_entropy/latest

Test location /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default/23.alert_handler_esc_alert_accum.1139199416
Short name T477
Test name
Test status
Simulation time 28162094797 ps
CPU time 284.39 seconds
Started Feb 08 07:55:31 PM UTC 25
Finished Feb 08 08:00:20 PM UTC 25
Peak memory 265584 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo
/hw/dv/tools/sim.tcl +ntb_random_seed=1139199416 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_ac
cum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 23.alert_handler_esc_alert_accum.1139199416
Directory /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/23.alert_handler_esc_alert_accum/latest

Test location /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default/23.alert_handler_esc_intr_timeout.584492366
Short name T467
Test name
Test status
Simulation time 296268030 ps
CPU time 36.87 seconds
Started Feb 08 07:55:21 PM UTC 25
Finished Feb 08 07:55:59 PM UTC 25
Peak memory 269280 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo
/hw/dv/tools/sim.tcl +ntb_random_seed=584492366 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_time
out_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 23.alert_handler_esc_intr_timeout.584492366
Directory /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/23.alert_handler_esc_intr_timeout/latest

Test location /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default/23.alert_handler_lpg.3536723489
Short name T383
Test name
Test status
Simulation time 84635845260 ps
CPU time 2786.45 seconds
Started Feb 08 07:56:12 PM UTC 25
Finished Feb 08 08:43:09 PM UTC 25
Peak memory 300840 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3536723489 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST
_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_lpg.3536723489
Directory /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/23.alert_handler_lpg/latest

Test location /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default/23.alert_handler_lpg_stub_clk.1982379824
Short name T564
Test name
Test status
Simulation time 270540345038 ps
CPU time 2513.29 seconds
Started Feb 08 07:56:12 PM UTC 25
Finished Feb 08 08:38:33 PM UTC 25
Peak memory 288740 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1982379824 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST
_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/alert_handler-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_lpg_stub_clk.1982379824
Directory /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/23.alert_handler_lpg_stub_clk/latest

Test location /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default/23.alert_handler_ping_timeout.1017105355
Short name T481
Test name
Test status
Simulation time 4555939794 ps
CPU time 281.51 seconds
Started Feb 08 07:56:00 PM UTC 25
Finished Feb 08 08:00:46 PM UTC 25
Peak memory 263196 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1017105355 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST
_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/alert_handler-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_ping_timeout.1017105355
Directory /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/23.alert_handler_ping_timeout/latest

Test location /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default/23.alert_handler_random_alerts.956911247
Short name T466
Test name
Test status
Simulation time 591262533 ps
CPU time 58.54 seconds
Started Feb 08 07:54:45 PM UTC 25
Finished Feb 08 07:55:45 PM UTC 25
Peak memory 263400 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo
/hw/dv/tools/sim.tcl +ntb_random_seed=956911247 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default.vdb -cm_
log /dev/null -cm_name 23.alert_handler_random_alerts.956911247
Directory /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/23.alert_handler_random_alerts/latest

Test location /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default/23.alert_handler_random_classes.1738793839
Short name T468
Test name
Test status
Simulation time 543292770 ps
CPU time 58.62 seconds
Started Feb 08 07:55:11 PM UTC 25
Finished Feb 08 07:56:11 PM UTC 25
Peak memory 263212 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo
/hw/dv/tools/sim.tcl +ntb_random_seed=1738793839 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_class
es_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default.vdb -c
m_log /dev/null -cm_name 23.alert_handler_random_classes.1738793839
Directory /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/23.alert_handler_random_classes/latest

Test location /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default/23.alert_handler_sig_int_fail.2069772003
Short name T470
Test name
Test status
Simulation time 1224431634 ps
CPU time 37.01 seconds
Started Feb 08 07:55:45 PM UTC 25
Finished Feb 08 07:56:24 PM UTC 25
Peak memory 263216 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo
/hw/dv/tools/sim.tcl +ntb_random_seed=2069772003 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default.vdb -cm_
log /dev/null -cm_name 23.alert_handler_sig_int_fail.2069772003
Directory /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/23.alert_handler_sig_int_fail/latest

Test location /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default/23.alert_handler_smoke.2678013672
Short name T465
Test name
Test status
Simulation time 1819429644 ps
CPU time 43.53 seconds
Started Feb 08 07:54:34 PM UTC 25
Finished Feb 08 07:55:20 PM UTC 25
Peak memory 263208 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo
/hw/dv/tools/sim.tcl +ntb_random_seed=2678013672 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default.vdb -cm_log /de
v/null -cm_name 23.alert_handler_smoke.2678013672
Directory /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/23.alert_handler_smoke/latest

Test location /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default/23.alert_handler_stress_all.497997553
Short name T115
Test name
Test status
Simulation time 4516784139 ps
CPU time 53.73 seconds
Started Feb 08 07:56:24 PM UTC 25
Finished Feb 08 07:57:19 PM UTC 25
Peak memory 269352 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=497997553 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_
regression/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_stress_all.497997553
Directory /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/23.alert_handler_stress_all/latest

Test location /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default/24.alert_handler_entropy.1591892906
Short name T561
Test name
Test status
Simulation time 219669564355 ps
CPU time 2287.83 seconds
Started Feb 08 07:58:21 PM UTC 25
Finished Feb 08 08:36:55 PM UTC 25
Peak memory 288804 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1591892906 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST
_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_entropy.1591892906
Directory /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/24.alert_handler_entropy/latest

Test location /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default/24.alert_handler_esc_alert_accum.993249618
Short name T475
Test name
Test status
Simulation time 398934221 ps
CPU time 39.93 seconds
Started Feb 08 07:58:04 PM UTC 25
Finished Feb 08 07:58:45 PM UTC 25
Peak memory 269284 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo
/hw/dv/tools/sim.tcl +ntb_random_seed=993249618 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_acc
um_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default.vdb -c
m_log /dev/null -cm_name 24.alert_handler_esc_alert_accum.993249618
Directory /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/24.alert_handler_esc_alert_accum/latest

Test location /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default/24.alert_handler_esc_intr_timeout.2309619838
Short name T474
Test name
Test status
Simulation time 544335170 ps
CPU time 36.87 seconds
Started Feb 08 07:57:53 PM UTC 25
Finished Feb 08 07:58:31 PM UTC 25
Peak memory 269288 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo
/hw/dv/tools/sim.tcl +ntb_random_seed=2309619838 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_tim
eout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 24.alert_handler_esc_intr_timeout.2309619838
Directory /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/24.alert_handler_esc_intr_timeout/latest

Test location /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default/24.alert_handler_lpg.341205642
Short name T372
Test name
Test status
Simulation time 16383969174 ps
CPU time 1878.46 seconds
Started Feb 08 07:58:46 PM UTC 25
Finished Feb 08 08:30:27 PM UTC 25
Peak memory 298024 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=341205642 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_
SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/cove
rage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_lpg.341205642
Directory /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/24.alert_handler_lpg/latest

Test location /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default/24.alert_handler_lpg_stub_clk.3278788607
Short name T533
Test name
Test status
Simulation time 13123330017 ps
CPU time 1433.52 seconds
Started Feb 08 07:59:59 PM UTC 25
Finished Feb 08 08:24:10 PM UTC 25
Peak memory 302108 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3278788607 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST
_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/alert_handler-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_lpg_stub_clk.3278788607
Directory /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/24.alert_handler_lpg_stub_clk/latest

Test location /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default/24.alert_handler_ping_timeout.579784950
Short name T360
Test name
Test status
Simulation time 95535157952 ps
CPU time 522.63 seconds
Started Feb 08 07:58:32 PM UTC 25
Finished Feb 08 08:07:21 PM UTC 25
Peak memory 263272 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=579784950 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_
SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/alert_handler-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_ping_timeout.579784950
Directory /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/24.alert_handler_ping_timeout/latest

Test location /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default/24.alert_handler_random_alerts.420617811
Short name T472
Test name
Test status
Simulation time 296319207 ps
CPU time 25.56 seconds
Started Feb 08 07:57:35 PM UTC 25
Finished Feb 08 07:58:03 PM UTC 25
Peak memory 269288 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo
/hw/dv/tools/sim.tcl +ntb_random_seed=420617811 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default.vdb -cm_
log /dev/null -cm_name 24.alert_handler_random_alerts.420617811
Directory /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/24.alert_handler_random_alerts/latest

Test location /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default/24.alert_handler_random_classes.538424492
Short name T289
Test name
Test status
Simulation time 3608616515 ps
CPU time 29.83 seconds
Started Feb 08 07:57:43 PM UTC 25
Finished Feb 08 07:58:14 PM UTC 25
Peak memory 263468 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo
/hw/dv/tools/sim.tcl +ntb_random_seed=538424492 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classe
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default.vdb -cm
_log /dev/null -cm_name 24.alert_handler_random_classes.538424492
Directory /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/24.alert_handler_random_classes/latest

Test location /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default/24.alert_handler_sig_int_fail.2587370901
Short name T473
Test name
Test status
Simulation time 22778618 ps
CPU time 3.81 seconds
Started Feb 08 07:58:15 PM UTC 25
Finished Feb 08 07:58:20 PM UTC 25
Peak memory 253168 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo
/hw/dv/tools/sim.tcl +ntb_random_seed=2587370901 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default.vdb -cm_
log /dev/null -cm_name 24.alert_handler_sig_int_fail.2587370901
Directory /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/24.alert_handler_sig_int_fail/latest

Test location /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default/24.alert_handler_smoke.3007208959
Short name T471
Test name
Test status
Simulation time 248798062 ps
CPU time 19.51 seconds
Started Feb 08 07:57:20 PM UTC 25
Finished Feb 08 07:57:41 PM UTC 25
Peak memory 269352 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo
/hw/dv/tools/sim.tcl +ntb_random_seed=3007208959 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default.vdb -cm_log /de
v/null -cm_name 24.alert_handler_smoke.3007208959
Directory /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/24.alert_handler_smoke/latest

Test location /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default/24.alert_handler_stress_all.3497127136
Short name T482
Test name
Test status
Simulation time 243423875 ps
CPU time 23.74 seconds
Started Feb 08 08:00:23 PM UTC 25
Finished Feb 08 08:00:48 PM UTC 25
Peak memory 267236 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3497127136 -assert nopostproc +UVM_TESTNAME=ale
rt_handler_base_test +UVM_TEST_SEQ=alert_handler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os
_regression/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_stress_all.3497127136
Directory /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/24.alert_handler_stress_all/latest

Test location /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default/25.alert_handler_entropy.2784649604
Short name T119
Test name
Test status
Simulation time 40408314211 ps
CPU time 3077.81 seconds
Started Feb 08 08:00:49 PM UTC 25
Finished Feb 08 08:52:42 PM UTC 25
Peak memory 304932 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2784649604 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST
_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_entropy.2784649604
Directory /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/25.alert_handler_entropy/latest

Test location /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default/25.alert_handler_esc_alert_accum.1552378036
Short name T490
Test name
Test status
Simulation time 17205645364 ps
CPU time 267.6 seconds
Started Feb 08 08:00:43 PM UTC 25
Finished Feb 08 08:05:15 PM UTC 25
Peak memory 269348 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo
/hw/dv/tools/sim.tcl +ntb_random_seed=1552378036 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_ac
cum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 25.alert_handler_esc_alert_accum.1552378036
Directory /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/25.alert_handler_esc_alert_accum/latest

Test location /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default/25.alert_handler_esc_intr_timeout.259753110
Short name T483
Test name
Test status
Simulation time 688064408 ps
CPU time 24.95 seconds
Started Feb 08 08:00:43 PM UTC 25
Finished Feb 08 08:01:10 PM UTC 25
Peak memory 269280 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo
/hw/dv/tools/sim.tcl +ntb_random_seed=259753110 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_time
out_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 25.alert_handler_esc_intr_timeout.259753110
Directory /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/25.alert_handler_esc_intr_timeout/latest

Test location /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default/25.alert_handler_lpg.3939437917
Short name T403
Test name
Test status
Simulation time 59726652293 ps
CPU time 1117.75 seconds
Started Feb 08 08:01:10 PM UTC 25
Finished Feb 08 08:20:01 PM UTC 25
Peak memory 302184 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3939437917 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST
_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_lpg.3939437917
Directory /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/25.alert_handler_lpg/latest

Test location /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default/25.alert_handler_lpg_stub_clk.2595313179
Short name T539
Test name
Test status
Simulation time 49374082858 ps
CPU time 1650.37 seconds
Started Feb 08 08:01:14 PM UTC 25
Finished Feb 08 08:29:04 PM UTC 25
Peak memory 302180 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2595313179 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST
_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/alert_handler-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_lpg_stub_clk.2595313179
Directory /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/25.alert_handler_lpg_stub_clk/latest

Test location /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default/25.alert_handler_ping_timeout.1488111920
Short name T504
Test name
Test status
Simulation time 18779859503 ps
CPU time 533.84 seconds
Started Feb 08 08:00:58 PM UTC 25
Finished Feb 08 08:09:59 PM UTC 25
Peak memory 263196 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1488111920 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST
_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/alert_handler-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_ping_timeout.1488111920
Directory /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/25.alert_handler_ping_timeout/latest

Test location /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default/25.alert_handler_random_alerts.941356575
Short name T480
Test name
Test status
Simulation time 89539976 ps
CPU time 17.96 seconds
Started Feb 08 08:00:23 PM UTC 25
Finished Feb 08 08:00:42 PM UTC 25
Peak memory 269352 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo
/hw/dv/tools/sim.tcl +ntb_random_seed=941356575 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default.vdb -cm_
log /dev/null -cm_name 25.alert_handler_random_alerts.941356575
Directory /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/25.alert_handler_random_alerts/latest

Test location /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default/25.alert_handler_random_classes.914354639
Short name T146
Test name
Test status
Simulation time 1518456810 ps
CPU time 59.11 seconds
Started Feb 08 08:00:35 PM UTC 25
Finished Feb 08 08:01:36 PM UTC 25
Peak memory 263136 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo
/hw/dv/tools/sim.tcl +ntb_random_seed=914354639 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classe
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default.vdb -cm
_log /dev/null -cm_name 25.alert_handler_random_classes.914354639
Directory /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/25.alert_handler_random_classes/latest

Test location /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default/25.alert_handler_sig_int_fail.3478856860
Short name T145
Test name
Test status
Simulation time 886823560 ps
CPU time 63.81 seconds
Started Feb 08 08:00:47 PM UTC 25
Finished Feb 08 08:01:53 PM UTC 25
Peak memory 263144 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo
/hw/dv/tools/sim.tcl +ntb_random_seed=3478856860 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default.vdb -cm_
log /dev/null -cm_name 25.alert_handler_sig_int_fail.3478856860
Directory /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/25.alert_handler_sig_int_fail/latest

Test location /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default/25.alert_handler_smoke.2310941699
Short name T478
Test name
Test status
Simulation time 179132007 ps
CPU time 10.33 seconds
Started Feb 08 08:00:23 PM UTC 25
Finished Feb 08 08:00:35 PM UTC 25
Peak memory 269552 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo
/hw/dv/tools/sim.tcl +ntb_random_seed=2310941699 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default.vdb -cm_log /de
v/null -cm_name 25.alert_handler_smoke.2310941699
Directory /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/25.alert_handler_smoke/latest

Test location /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default/25.alert_handler_stress_all.1351217594
Short name T312
Test name
Test status
Simulation time 44525325258 ps
CPU time 2842.55 seconds
Started Feb 08 08:01:36 PM UTC 25
Finished Feb 08 08:49:29 PM UTC 25
Peak memory 321252 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1351217594 -assert nopostproc +UVM_TESTNAME=ale
rt_handler_base_test +UVM_TEST_SEQ=alert_handler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os
_regression/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_stress_all.1351217594
Directory /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/25.alert_handler_stress_all/latest

Test location /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default/26.alert_handler_entropy.1573678382
Short name T526
Test name
Test status
Simulation time 19842841781 ps
CPU time 932.65 seconds
Started Feb 08 08:03:32 PM UTC 25
Finished Feb 08 08:19:16 PM UTC 25
Peak memory 281896 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1573678382 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST
_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_entropy.1573678382
Directory /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/26.alert_handler_entropy/latest

Test location /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default/26.alert_handler_esc_alert_accum.3482985863
Short name T486
Test name
Test status
Simulation time 602068503 ps
CPU time 10.04 seconds
Started Feb 08 08:03:17 PM UTC 25
Finished Feb 08 08:03:28 PM UTC 25
Peak memory 269552 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo
/hw/dv/tools/sim.tcl +ntb_random_seed=3482985863 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_ac
cum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 26.alert_handler_esc_alert_accum.3482985863
Directory /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/26.alert_handler_esc_alert_accum/latest

Test location /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default/26.alert_handler_esc_intr_timeout.375830180
Short name T485
Test name
Test status
Simulation time 307319808 ps
CPU time 19.08 seconds
Started Feb 08 08:02:56 PM UTC 25
Finished Feb 08 08:03:16 PM UTC 25
Peak memory 263208 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo
/hw/dv/tools/sim.tcl +ntb_random_seed=375830180 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_time
out_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 26.alert_handler_esc_intr_timeout.375830180
Directory /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/26.alert_handler_esc_intr_timeout/latest

Test location /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default/26.alert_handler_lpg.953650011
Short name T377
Test name
Test status
Simulation time 122818112379 ps
CPU time 1893.11 seconds
Started Feb 08 08:03:47 PM UTC 25
Finished Feb 08 08:35:41 PM UTC 25
Peak memory 285732 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=953650011 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_
SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/cove
rage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_lpg.953650011
Directory /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/26.alert_handler_lpg/latest

Test location /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default/26.alert_handler_lpg_stub_clk.266029140
Short name T518
Test name
Test status
Simulation time 9317574189 ps
CPU time 723.52 seconds
Started Feb 08 08:03:52 PM UTC 25
Finished Feb 08 08:16:03 PM UTC 25
Peak memory 285992 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=266029140 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_
SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/alert_handler-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_lpg_stub_clk.266029140
Directory /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/26.alert_handler_lpg_stub_clk/latest

Test location /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default/26.alert_handler_ping_timeout.770384121
Short name T348
Test name
Test status
Simulation time 7870973440 ps
CPU time 329.4 seconds
Started Feb 08 08:03:36 PM UTC 25
Finished Feb 08 08:09:10 PM UTC 25
Peak memory 263196 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=770384121 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_
SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/alert_handler-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_ping_timeout.770384121
Directory /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/26.alert_handler_ping_timeout/latest

Test location /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default/26.alert_handler_random_alerts.2472019102
Short name T487
Test name
Test status
Simulation time 910947597 ps
CPU time 60.91 seconds
Started Feb 08 08:02:29 PM UTC 25
Finished Feb 08 08:03:32 PM UTC 25
Peak memory 269284 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo
/hw/dv/tools/sim.tcl +ntb_random_seed=2472019102 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alert
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default.vdb -cm
_log /dev/null -cm_name 26.alert_handler_random_alerts.2472019102
Directory /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/26.alert_handler_random_alerts/latest

Test location /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default/26.alert_handler_random_classes.2377043003
Short name T488
Test name
Test status
Simulation time 788184808 ps
CPU time 66.86 seconds
Started Feb 08 08:02:38 PM UTC 25
Finished Feb 08 08:03:46 PM UTC 25
Peak memory 269280 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo
/hw/dv/tools/sim.tcl +ntb_random_seed=2377043003 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_class
es_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default.vdb -c
m_log /dev/null -cm_name 26.alert_handler_random_classes.2377043003
Directory /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/26.alert_handler_random_classes/latest

Test location /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default/26.alert_handler_smoke.3338572843
Short name T484
Test name
Test status
Simulation time 1282290557 ps
CPU time 32.52 seconds
Started Feb 08 08:01:54 PM UTC 25
Finished Feb 08 08:02:28 PM UTC 25
Peak memory 269280 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo
/hw/dv/tools/sim.tcl +ntb_random_seed=3338572843 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default.vdb -cm_log /de
v/null -cm_name 26.alert_handler_smoke.3338572843
Directory /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/26.alert_handler_smoke/latest

Test location /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default/26.alert_handler_stress_all.4259998356
Short name T540
Test name
Test status
Simulation time 48201671505 ps
CPU time 1524.79 seconds
Started Feb 08 08:04:17 PM UTC 25
Finished Feb 08 08:30:00 PM UTC 25
Peak memory 302116 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4259998356 -assert nopostproc +UVM_TESTNAME=ale
rt_handler_base_test +UVM_TEST_SEQ=alert_handler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os
_regression/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_stress_all.4259998356
Directory /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/26.alert_handler_stress_all/latest

Test location /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default/26.alert_handler_stress_all_with_rand_reset.3818001598
Short name T267
Test name
Test status
Simulation time 84684299349 ps
CPU time 5251.8 seconds
Started Feb 08 08:04:24 PM UTC 25
Finished Feb 08 09:32:51 PM UTC 25
Peak memory 315272 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=ale
rt_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=38180
01598 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_stress_al
l_with_rand_reset.3818001598
Directory /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/26.alert_handler_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default/27.alert_handler_entropy.3892183973
Short name T580
Test name
Test status
Simulation time 34371095425 ps
CPU time 2289.28 seconds
Started Feb 08 08:06:30 PM UTC 25
Finished Feb 08 08:45:06 PM UTC 25
Peak memory 298720 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3892183973 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST
_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_entropy.3892183973
Directory /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/27.alert_handler_entropy/latest

Test location /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default/27.alert_handler_esc_alert_accum.610999059
Short name T500
Test name
Test status
Simulation time 5033115367 ps
CPU time 157.46 seconds
Started Feb 08 08:06:12 PM UTC 25
Finished Feb 08 08:08:52 PM UTC 25
Peak memory 269612 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo
/hw/dv/tools/sim.tcl +ntb_random_seed=610999059 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_acc
um_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default.vdb -c
m_log /dev/null -cm_name 27.alert_handler_esc_alert_accum.610999059
Directory /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/27.alert_handler_esc_alert_accum/latest

Test location /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default/27.alert_handler_esc_intr_timeout.321090922
Short name T493
Test name
Test status
Simulation time 678638525 ps
CPU time 32.15 seconds
Started Feb 08 08:05:48 PM UTC 25
Finished Feb 08 08:06:22 PM UTC 25
Peak memory 269544 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo
/hw/dv/tools/sim.tcl +ntb_random_seed=321090922 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_time
out_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 27.alert_handler_esc_intr_timeout.321090922
Directory /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/27.alert_handler_esc_intr_timeout/latest

Test location /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default/27.alert_handler_ping_timeout.3142063293
Short name T351
Test name
Test status
Simulation time 10955684877 ps
CPU time 384.94 seconds
Started Feb 08 08:06:46 PM UTC 25
Finished Feb 08 08:13:16 PM UTC 25
Peak memory 263468 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3142063293 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST
_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/alert_handler-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_ping_timeout.3142063293
Directory /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/27.alert_handler_ping_timeout/latest

Test location /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default/27.alert_handler_random_alerts.1683474194
Short name T495
Test name
Test status
Simulation time 837986840 ps
CPU time 86.67 seconds
Started Feb 08 08:05:16 PM UTC 25
Finished Feb 08 08:06:45 PM UTC 25
Peak memory 269548 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo
/hw/dv/tools/sim.tcl +ntb_random_seed=1683474194 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alert
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default.vdb -cm
_log /dev/null -cm_name 27.alert_handler_random_alerts.1683474194
Directory /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/27.alert_handler_random_alerts/latest

Test location /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default/27.alert_handler_random_classes.3293687700
Short name T309
Test name
Test status
Simulation time 5133535794 ps
CPU time 113.94 seconds
Started Feb 08 08:05:30 PM UTC 25
Finished Feb 08 08:07:27 PM UTC 25
Peak memory 263200 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo
/hw/dv/tools/sim.tcl +ntb_random_seed=3293687700 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_class
es_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default.vdb -c
m_log /dev/null -cm_name 27.alert_handler_random_classes.3293687700
Directory /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/27.alert_handler_random_classes/latest

Test location /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default/27.alert_handler_sig_int_fail.2269952541
Short name T496
Test name
Test status
Simulation time 585892764 ps
CPU time 23.16 seconds
Started Feb 08 08:06:23 PM UTC 25
Finished Feb 08 08:06:48 PM UTC 25
Peak memory 263144 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo
/hw/dv/tools/sim.tcl +ntb_random_seed=2269952541 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default.vdb -cm_
log /dev/null -cm_name 27.alert_handler_sig_int_fail.2269952541
Directory /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/27.alert_handler_sig_int_fail/latest

Test location /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default/27.alert_handler_smoke.2616020337
Short name T491
Test name
Test status
Simulation time 1841920568 ps
CPU time 33.09 seconds
Started Feb 08 08:04:55 PM UTC 25
Finished Feb 08 08:05:29 PM UTC 25
Peak memory 269280 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo
/hw/dv/tools/sim.tcl +ntb_random_seed=2616020337 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default.vdb -cm_log /de
v/null -cm_name 27.alert_handler_smoke.2616020337
Directory /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/27.alert_handler_smoke/latest

Test location /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default/27.alert_handler_stress_all.1294225233
Short name T685
Test name
Test status
Simulation time 275336414906 ps
CPU time 4558.77 seconds
Started Feb 08 08:07:30 PM UTC 25
Finished Feb 08 09:24:17 PM UTC 25
Peak memory 321252 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1294225233 -assert nopostproc +UVM_TESTNAME=ale
rt_handler_base_test +UVM_TEST_SEQ=alert_handler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os
_regression/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_stress_all.1294225233
Directory /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/27.alert_handler_stress_all/latest

Test location /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default/28.alert_handler_entropy.3663682019
Short name T587
Test name
Test status
Simulation time 165304792996 ps
CPU time 2276.9 seconds
Started Feb 08 08:08:53 PM UTC 25
Finished Feb 08 08:47:15 PM UTC 25
Peak memory 285728 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3663682019 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST
_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_entropy.3663682019
Directory /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/28.alert_handler_entropy/latest

Test location /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default/28.alert_handler_esc_alert_accum.120663723
Short name T510
Test name
Test status
Simulation time 5617813562 ps
CPU time 232.05 seconds
Started Feb 08 08:08:42 PM UTC 25
Finished Feb 08 08:12:40 PM UTC 25
Peak memory 269420 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo
/hw/dv/tools/sim.tcl +ntb_random_seed=120663723 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_acc
um_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default.vdb -c
m_log /dev/null -cm_name 28.alert_handler_esc_alert_accum.120663723
Directory /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/28.alert_handler_esc_alert_accum/latest

Test location /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default/28.alert_handler_esc_intr_timeout.2513770616
Short name T502
Test name
Test status
Simulation time 2296388952 ps
CPU time 49.87 seconds
Started Feb 08 08:08:33 PM UTC 25
Finished Feb 08 08:09:25 PM UTC 25
Peak memory 269420 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo
/hw/dv/tools/sim.tcl +ntb_random_seed=2513770616 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_tim
eout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 28.alert_handler_esc_intr_timeout.2513770616
Directory /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/28.alert_handler_esc_intr_timeout/latest

Test location /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default/28.alert_handler_lpg.3581725476
Short name T593
Test name
Test status
Simulation time 136268832841 ps
CPU time 2370.56 seconds
Started Feb 08 08:09:13 PM UTC 25
Finished Feb 08 08:49:10 PM UTC 25
Peak memory 298712 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3581725476 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST
_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_lpg.3581725476
Directory /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/28.alert_handler_lpg/latest

Test location /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default/28.alert_handler_lpg_stub_clk.2927997423
Short name T592
Test name
Test status
Simulation time 432318129567 ps
CPU time 2332.01 seconds
Started Feb 08 08:09:14 PM UTC 25
Finished Feb 08 08:48:33 PM UTC 25
Peak memory 300064 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2927997423 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST
_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/alert_handler-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_lpg_stub_clk.2927997423
Directory /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/28.alert_handler_lpg_stub_clk/latest

Test location /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default/28.alert_handler_ping_timeout.388437507
Short name T357
Test name
Test status
Simulation time 14728786934 ps
CPU time 534.72 seconds
Started Feb 08 08:09:11 PM UTC 25
Finished Feb 08 08:18:12 PM UTC 25
Peak memory 263460 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=388437507 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_
SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/alert_handler-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_ping_timeout.388437507
Directory /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/28.alert_handler_ping_timeout/latest

Test location /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default/28.alert_handler_random_alerts.1616843644
Short name T501
Test name
Test status
Simulation time 2991325853 ps
CPU time 51.91 seconds
Started Feb 08 08:08:19 PM UTC 25
Finished Feb 08 08:09:13 PM UTC 25
Peak memory 269420 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo
/hw/dv/tools/sim.tcl +ntb_random_seed=1616843644 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alert
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default.vdb -cm
_log /dev/null -cm_name 28.alert_handler_random_alerts.1616843644
Directory /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/28.alert_handler_random_alerts/latest

Test location /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default/28.alert_handler_random_classes.1462698175
Short name T499
Test name
Test status
Simulation time 97257680 ps
CPU time 18.1 seconds
Started Feb 08 08:08:21 PM UTC 25
Finished Feb 08 08:08:41 PM UTC 25
Peak memory 269356 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo
/hw/dv/tools/sim.tcl +ntb_random_seed=1462698175 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_class
es_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default.vdb -c
m_log /dev/null -cm_name 28.alert_handler_random_classes.1462698175
Directory /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/28.alert_handler_random_classes/latest

Test location /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default/28.alert_handler_smoke.2294950734
Short name T497
Test name
Test status
Simulation time 11531398470 ps
CPU time 44.46 seconds
Started Feb 08 08:07:32 PM UTC 25
Finished Feb 08 08:08:18 PM UTC 25
Peak memory 269416 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo
/hw/dv/tools/sim.tcl +ntb_random_seed=2294950734 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default.vdb -cm_log /de
v/null -cm_name 28.alert_handler_smoke.2294950734
Directory /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/28.alert_handler_smoke/latest

Test location /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default/28.alert_handler_stress_all.885363438
Short name T573
Test name
Test status
Simulation time 33163975574 ps
CPU time 1957.01 seconds
Started Feb 08 08:09:17 PM UTC 25
Finished Feb 08 08:42:15 PM UTC 25
Peak memory 285736 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=885363438 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_
regression/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_stress_all.885363438
Directory /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/28.alert_handler_stress_all/latest

Test location /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default/29.alert_handler_entropy.1826631939
Short name T569
Test name
Test status
Simulation time 57450172409 ps
CPU time 1738.02 seconds
Started Feb 08 08:11:29 PM UTC 25
Finished Feb 08 08:40:46 PM UTC 25
Peak memory 285996 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1826631939 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST
_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_entropy.1826631939
Directory /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/29.alert_handler_entropy/latest

Test location /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default/29.alert_handler_esc_alert_accum.2382084441
Short name T511
Test name
Test status
Simulation time 2550857863 ps
CPU time 112.24 seconds
Started Feb 08 08:11:07 PM UTC 25
Finished Feb 08 08:13:02 PM UTC 25
Peak memory 269352 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo
/hw/dv/tools/sim.tcl +ntb_random_seed=2382084441 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_ac
cum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 29.alert_handler_esc_alert_accum.2382084441
Directory /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/29.alert_handler_esc_alert_accum/latest

Test location /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default/29.alert_handler_esc_intr_timeout.4102303677
Short name T509
Test name
Test status
Simulation time 692110187 ps
CPU time 59.52 seconds
Started Feb 08 08:10:53 PM UTC 25
Finished Feb 08 08:11:54 PM UTC 25
Peak memory 269548 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo
/hw/dv/tools/sim.tcl +ntb_random_seed=4102303677 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_tim
eout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 29.alert_handler_esc_intr_timeout.4102303677
Directory /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/29.alert_handler_esc_intr_timeout/latest

Test location /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default/29.alert_handler_lpg_stub_clk.4279160759
Short name T535
Test name
Test status
Simulation time 19797297826 ps
CPU time 736.75 seconds
Started Feb 08 08:11:57 PM UTC 25
Finished Feb 08 08:24:22 PM UTC 25
Peak memory 285724 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4279160759 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST
_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/alert_handler-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_lpg_stub_clk.4279160759
Directory /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/29.alert_handler_lpg_stub_clk/latest

Test location /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default/29.alert_handler_ping_timeout.3200207261
Short name T361
Test name
Test status
Simulation time 9372452170 ps
CPU time 436.65 seconds
Started Feb 08 08:11:30 PM UTC 25
Finished Feb 08 08:18:52 PM UTC 25
Peak memory 263468 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3200207261 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST
_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/alert_handler-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_ping_timeout.3200207261
Directory /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/29.alert_handler_ping_timeout/latest

Test location /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default/29.alert_handler_random_alerts.129490168
Short name T508
Test name
Test status
Simulation time 2081429485 ps
CPU time 97.75 seconds
Started Feb 08 08:10:00 PM UTC 25
Finished Feb 08 08:11:40 PM UTC 25
Peak memory 269356 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo
/hw/dv/tools/sim.tcl +ntb_random_seed=129490168 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default.vdb -cm_
log /dev/null -cm_name 29.alert_handler_random_alerts.129490168
Directory /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/29.alert_handler_random_alerts/latest

Test location /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default/29.alert_handler_random_classes.2998370442
Short name T505
Test name
Test status
Simulation time 1890657699 ps
CPU time 51.21 seconds
Started Feb 08 08:10:14 PM UTC 25
Finished Feb 08 08:11:06 PM UTC 25
Peak memory 269284 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo
/hw/dv/tools/sim.tcl +ntb_random_seed=2998370442 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_class
es_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default.vdb -c
m_log /dev/null -cm_name 29.alert_handler_random_classes.2998370442
Directory /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/29.alert_handler_random_classes/latest

Test location /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default/29.alert_handler_sig_int_fail.3503348658
Short name T506
Test name
Test status
Simulation time 588341776 ps
CPU time 17.31 seconds
Started Feb 08 08:11:09 PM UTC 25
Finished Feb 08 08:11:28 PM UTC 25
Peak memory 263144 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo
/hw/dv/tools/sim.tcl +ntb_random_seed=3503348658 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default.vdb -cm_
log /dev/null -cm_name 29.alert_handler_sig_int_fail.3503348658
Directory /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/29.alert_handler_sig_int_fail/latest

Test location /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default/29.alert_handler_smoke.1985919794
Short name T507
Test name
Test status
Simulation time 4830799958 ps
CPU time 109.33 seconds
Started Feb 08 08:09:37 PM UTC 25
Finished Feb 08 08:11:29 PM UTC 25
Peak memory 269608 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo
/hw/dv/tools/sim.tcl +ntb_random_seed=1985919794 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default.vdb -cm_log /de
v/null -cm_name 29.alert_handler_smoke.1985919794
Directory /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/29.alert_handler_smoke/latest

Test location /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default/29.alert_handler_stress_all.3046282426
Short name T524
Test name
Test status
Simulation time 18025210317 ps
CPU time 381.64 seconds
Started Feb 08 08:11:57 PM UTC 25
Finished Feb 08 08:18:24 PM UTC 25
Peak memory 269424 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3046282426 -assert nopostproc +UVM_TESTNAME=ale
rt_handler_base_test +UVM_TEST_SEQ=alert_handler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os
_regression/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_stress_all.3046282426
Directory /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/29.alert_handler_stress_all/latest

Test location /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default/3.alert_handler_alert_accum_saturation.1900127902
Short name T75
Test name
Test status
Simulation time 52562962 ps
CPU time 3.76 seconds
Started Feb 08 07:05:57 PM UTC 25
Finished Feb 08 07:06:02 PM UTC 25
Peak memory 263408 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
paces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1900127902 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_al
ert_accum_saturation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/cover
age/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_alert_accum_saturation.1900127902
Directory /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/3.alert_handler_alert_accum_saturation/latest

Test location /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default/3.alert_handler_entropy.3283976325
Short name T265
Test name
Test status
Simulation time 44530411276 ps
CPU time 1321.09 seconds
Started Feb 08 07:05:35 PM UTC 25
Finished Feb 08 07:27:51 PM UTC 25
Peak memory 302180 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3283976325 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST
_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_entropy.3283976325
Directory /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/3.alert_handler_entropy/latest

Test location /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default/3.alert_handler_entropy_stress.934751699
Short name T19
Test name
Test status
Simulation time 477897626 ps
CPU time 32.03 seconds
Started Feb 08 07:05:53 PM UTC 25
Finished Feb 08 07:06:27 PM UTC 25
Peak memory 263404 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
paces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=934751699 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ent
ropy_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 3.alert_handler_entropy_stress.934751699
Directory /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/3.alert_handler_entropy_stress/latest

Test location /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default/3.alert_handler_esc_alert_accum.3907451058
Short name T337
Test name
Test status
Simulation time 5480324565 ps
CPU time 131.28 seconds
Started Feb 08 07:05:29 PM UTC 25
Finished Feb 08 07:07:43 PM UTC 25
Peak memory 269420 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo
/hw/dv/tools/sim.tcl +ntb_random_seed=3907451058 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_ac
cum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 3.alert_handler_esc_alert_accum.3907451058
Directory /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/3.alert_handler_esc_alert_accum/latest

Test location /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default/3.alert_handler_esc_intr_timeout.2407471528
Short name T86
Test name
Test status
Simulation time 9115686701 ps
CPU time 78.59 seconds
Started Feb 08 07:05:27 PM UTC 25
Finished Feb 08 07:06:47 PM UTC 25
Peak memory 263208 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo
/hw/dv/tools/sim.tcl +ntb_random_seed=2407471528 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_tim
eout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 3.alert_handler_esc_intr_timeout.2407471528
Directory /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/3.alert_handler_esc_intr_timeout/latest

Test location /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default/3.alert_handler_lpg.3996753809
Short name T78
Test name
Test status
Simulation time 8932783179 ps
CPU time 1056.15 seconds
Started Feb 08 07:05:38 PM UTC 25
Finished Feb 08 07:23:26 PM UTC 25
Peak memory 285728 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3996753809 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST
_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_lpg.3996753809
Directory /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/3.alert_handler_lpg/latest

Test location /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default/3.alert_handler_lpg_stub_clk.2667804557
Short name T295
Test name
Test status
Simulation time 34009642553 ps
CPU time 1777.39 seconds
Started Feb 08 07:05:47 PM UTC 25
Finished Feb 08 07:35:46 PM UTC 25
Peak memory 302112 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2667804557 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST
_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/alert_handler-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_lpg_stub_clk.2667804557
Directory /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/3.alert_handler_lpg_stub_clk/latest

Test location /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default/3.alert_handler_ping_timeout.3898913561
Short name T17
Test name
Test status
Simulation time 4383035209 ps
CPU time 270.63 seconds
Started Feb 08 07:05:36 PM UTC 25
Finished Feb 08 07:10:11 PM UTC 25
Peak memory 263204 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3898913561 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST
_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/alert_handler-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_ping_timeout.3898913561
Directory /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/3.alert_handler_ping_timeout/latest

Test location /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default/3.alert_handler_random_alerts.2220150817
Short name T52
Test name
Test status
Simulation time 315950874 ps
CPU time 35.78 seconds
Started Feb 08 07:05:24 PM UTC 25
Finished Feb 08 07:06:01 PM UTC 25
Peak memory 269280 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo
/hw/dv/tools/sim.tcl +ntb_random_seed=2220150817 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alert
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default.vdb -cm
_log /dev/null -cm_name 3.alert_handler_random_alerts.2220150817
Directory /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/3.alert_handler_random_alerts/latest

Test location /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default/3.alert_handler_sec_cm.988071568
Short name T49
Test name
Test status
Simulation time 1236948659 ps
CPU time 34.57 seconds
Started Feb 08 07:06:03 PM UTC 25
Finished Feb 08 07:06:39 PM UTC 25
Peak memory 298988 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=988071568 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=al
ert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverag
e/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_sec_cm.988071568
Directory /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/3.alert_handler_sec_cm/latest

Test location /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default/3.alert_handler_smoke.1667152131
Short name T28
Test name
Test status
Simulation time 158903536 ps
CPU time 10.55 seconds
Started Feb 08 07:05:23 PM UTC 25
Finished Feb 08 07:05:35 PM UTC 25
Peak memory 265184 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo
/hw/dv/tools/sim.tcl +ntb_random_seed=1667152131 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default.vdb -cm_log /de
v/null -cm_name 3.alert_handler_smoke.1667152131
Directory /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/3.alert_handler_smoke/latest

Test location /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default/3.alert_handler_stress_all.3810596268
Short name T31
Test name
Test status
Simulation time 4119203089 ps
CPU time 183.99 seconds
Started Feb 08 07:05:56 PM UTC 25
Finished Feb 08 07:09:03 PM UTC 25
Peak memory 265252 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3810596268 -assert nopostproc +UVM_TESTNAME=ale
rt_handler_base_test +UVM_TEST_SEQ=alert_handler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os
_regression/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_stress_all.3810596268
Directory /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/3.alert_handler_stress_all/latest

Test location /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default/30.alert_handler_entropy.2316508800
Short name T245
Test name
Test status
Simulation time 10418580031 ps
CPU time 731.62 seconds
Started Feb 08 08:14:35 PM UTC 25
Finished Feb 08 08:26:56 PM UTC 25
Peak memory 285928 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2316508800 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST
_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_entropy.2316508800
Directory /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/30.alert_handler_entropy/latest

Test location /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default/30.alert_handler_esc_alert_accum.3046337005
Short name T523
Test name
Test status
Simulation time 8467245052 ps
CPU time 259.12 seconds
Started Feb 08 08:13:56 PM UTC 25
Finished Feb 08 08:18:19 PM UTC 25
Peak memory 269424 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo
/hw/dv/tools/sim.tcl +ntb_random_seed=3046337005 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_ac
cum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 30.alert_handler_esc_alert_accum.3046337005
Directory /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/30.alert_handler_esc_alert_accum/latest

Test location /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default/30.alert_handler_esc_intr_timeout.2678953768
Short name T515
Test name
Test status
Simulation time 750448418 ps
CPU time 48.24 seconds
Started Feb 08 08:13:54 PM UTC 25
Finished Feb 08 08:14:44 PM UTC 25
Peak memory 269548 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo
/hw/dv/tools/sim.tcl +ntb_random_seed=2678953768 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_tim
eout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 30.alert_handler_esc_intr_timeout.2678953768
Directory /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/30.alert_handler_esc_intr_timeout/latest

Test location /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default/30.alert_handler_lpg.268245240
Short name T567
Test name
Test status
Simulation time 57131720875 ps
CPU time 1495.28 seconds
Started Feb 08 08:14:57 PM UTC 25
Finished Feb 08 08:40:10 PM UTC 25
Peak memory 295972 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=268245240 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_
SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/cove
rage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_lpg.268245240
Directory /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/30.alert_handler_lpg/latest

Test location /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default/30.alert_handler_lpg_stub_clk.1468059016
Short name T548
Test name
Test status
Simulation time 68899474311 ps
CPU time 1049.37 seconds
Started Feb 08 08:15:12 PM UTC 25
Finished Feb 08 08:32:53 PM UTC 25
Peak memory 279656 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1468059016 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST
_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/alert_handler-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_lpg_stub_clk.1468059016
Directory /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/30.alert_handler_lpg_stub_clk/latest

Test location /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default/30.alert_handler_random_alerts.3036141706
Short name T514
Test name
Test status
Simulation time 724068710 ps
CPU time 36.55 seconds
Started Feb 08 08:13:17 PM UTC 25
Finished Feb 08 08:13:55 PM UTC 25
Peak memory 263468 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo
/hw/dv/tools/sim.tcl +ntb_random_seed=3036141706 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alert
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default.vdb -cm
_log /dev/null -cm_name 30.alert_handler_random_alerts.3036141706
Directory /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/30.alert_handler_random_alerts/latest

Test location /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default/30.alert_handler_random_classes.2085949067
Short name T517
Test name
Test status
Simulation time 2504821377 ps
CPU time 104.59 seconds
Started Feb 08 08:13:50 PM UTC 25
Finished Feb 08 08:15:37 PM UTC 25
Peak memory 269344 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo
/hw/dv/tools/sim.tcl +ntb_random_seed=2085949067 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_class
es_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default.vdb -c
m_log /dev/null -cm_name 30.alert_handler_random_classes.2085949067
Directory /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/30.alert_handler_random_classes/latest

Test location /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default/30.alert_handler_sig_int_fail.954894652
Short name T516
Test name
Test status
Simulation time 2602290747 ps
CPU time 65.36 seconds
Started Feb 08 08:14:05 PM UTC 25
Finished Feb 08 08:15:12 PM UTC 25
Peak memory 263204 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo
/hw/dv/tools/sim.tcl +ntb_random_seed=954894652 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default.vdb -cm_l
og /dev/null -cm_name 30.alert_handler_sig_int_fail.954894652
Directory /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/30.alert_handler_sig_int_fail/latest

Test location /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default/30.alert_handler_smoke.2594256674
Short name T512
Test name
Test status
Simulation time 689054763 ps
CPU time 45.35 seconds
Started Feb 08 08:13:03 PM UTC 25
Finished Feb 08 08:13:50 PM UTC 25
Peak memory 263464 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo
/hw/dv/tools/sim.tcl +ntb_random_seed=2594256674 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default.vdb -cm_log /de
v/null -cm_name 30.alert_handler_smoke.2594256674
Directory /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/30.alert_handler_smoke/latest

Test location /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default/30.alert_handler_stress_all.3944219776
Short name T152
Test name
Test status
Simulation time 2087240790 ps
CPU time 69.53 seconds
Started Feb 08 08:15:38 PM UTC 25
Finished Feb 08 08:16:49 PM UTC 25
Peak memory 269288 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3944219776 -assert nopostproc +UVM_TESTNAME=ale
rt_handler_base_test +UVM_TEST_SEQ=alert_handler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os
_regression/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_stress_all.3944219776
Directory /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/30.alert_handler_stress_all/latest

Test location /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default/31.alert_handler_entropy.518982121
Short name T615
Test name
Test status
Simulation time 118953504481 ps
CPU time 2393.82 seconds
Started Feb 08 08:18:10 PM UTC 25
Finished Feb 08 08:58:31 PM UTC 25
Peak memory 288480 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=518982121 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_
SEQ=alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/
coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_entropy.518982121
Directory /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/31.alert_handler_entropy/latest

Test location /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default/31.alert_handler_esc_alert_accum.2766151330
Short name T528
Test name
Test status
Simulation time 1239280683 ps
CPU time 108.7 seconds
Started Feb 08 08:17:41 PM UTC 25
Finished Feb 08 08:19:32 PM UTC 25
Peak memory 269360 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo
/hw/dv/tools/sim.tcl +ntb_random_seed=2766151330 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_ac
cum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 31.alert_handler_esc_alert_accum.2766151330
Directory /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/31.alert_handler_esc_alert_accum/latest

Test location /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default/31.alert_handler_esc_intr_timeout.2305909487
Short name T521
Test name
Test status
Simulation time 572284966 ps
CPU time 29.08 seconds
Started Feb 08 08:17:39 PM UTC 25
Finished Feb 08 08:18:09 PM UTC 25
Peak memory 263140 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo
/hw/dv/tools/sim.tcl +ntb_random_seed=2305909487 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_tim
eout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 31.alert_handler_esc_intr_timeout.2305909487
Directory /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/31.alert_handler_esc_intr_timeout/latest

Test location /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default/31.alert_handler_lpg_stub_clk.397813447
Short name T642
Test name
Test status
Simulation time 37171210389 ps
CPU time 3023.21 seconds
Started Feb 08 08:18:20 PM UTC 25
Finished Feb 08 09:09:18 PM UTC 25
Peak memory 304892 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=397813447 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_
SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/alert_handler-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_lpg_stub_clk.397813447
Directory /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/31.alert_handler_lpg_stub_clk/latest

Test location /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default/31.alert_handler_ping_timeout.1751647961
Short name T536
Test name
Test status
Simulation time 17392035003 ps
CPU time 551.87 seconds
Started Feb 08 08:18:13 PM UTC 25
Finished Feb 08 08:27:32 PM UTC 25
Peak memory 263204 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1751647961 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST
_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/alert_handler-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_ping_timeout.1751647961
Directory /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/31.alert_handler_ping_timeout/latest

Test location /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default/31.alert_handler_random_alerts.3712764622
Short name T520
Test name
Test status
Simulation time 192849140 ps
CPU time 30.67 seconds
Started Feb 08 08:17:06 PM UTC 25
Finished Feb 08 08:17:38 PM UTC 25
Peak memory 269192 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo
/hw/dv/tools/sim.tcl +ntb_random_seed=3712764622 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alert
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default.vdb -cm
_log /dev/null -cm_name 31.alert_handler_random_alerts.3712764622
Directory /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/31.alert_handler_random_alerts/latest

Test location /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default/31.alert_handler_random_classes.1424345231
Short name T116
Test name
Test status
Simulation time 6740155955 ps
CPU time 50.19 seconds
Started Feb 08 08:17:06 PM UTC 25
Finished Feb 08 08:17:58 PM UTC 25
Peak memory 269200 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo
/hw/dv/tools/sim.tcl +ntb_random_seed=1424345231 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_class
es_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default.vdb -c
m_log /dev/null -cm_name 31.alert_handler_random_classes.1424345231
Directory /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/31.alert_handler_random_classes/latest

Test location /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default/31.alert_handler_sig_int_fail.683920674
Short name T525
Test name
Test status
Simulation time 177660028 ps
CPU time 27.08 seconds
Started Feb 08 08:17:59 PM UTC 25
Finished Feb 08 08:18:27 PM UTC 25
Peak memory 263140 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo
/hw/dv/tools/sim.tcl +ntb_random_seed=683920674 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default.vdb -cm_l
og /dev/null -cm_name 31.alert_handler_sig_int_fail.683920674
Directory /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/31.alert_handler_sig_int_fail/latest

Test location /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default/31.alert_handler_smoke.2077385364
Short name T522
Test name
Test status
Simulation time 3364628713 ps
CPU time 80.88 seconds
Started Feb 08 08:16:50 PM UTC 25
Finished Feb 08 08:18:13 PM UTC 25
Peak memory 269416 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo
/hw/dv/tools/sim.tcl +ntb_random_seed=2077385364 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default.vdb -cm_log /de
v/null -cm_name 31.alert_handler_smoke.2077385364
Directory /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/31.alert_handler_smoke/latest

Test location /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default/31.alert_handler_stress_all_with_rand_reset.4218522146
Short name T216
Test name
Test status
Simulation time 87864896653 ps
CPU time 1752.34 seconds
Started Feb 08 08:18:28 PM UTC 25
Finished Feb 08 08:48:01 PM UTC 25
Peak memory 296096 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=ale
rt_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=42185
22146 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_stress_al
l_with_rand_reset.4218522146
Directory /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/31.alert_handler_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default/32.alert_handler_entropy.2283982846
Short name T117
Test name
Test status
Simulation time 16200810521 ps
CPU time 1056.14 seconds
Started Feb 08 08:20:04 PM UTC 25
Finished Feb 08 08:37:54 PM UTC 25
Peak memory 296036 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2283982846 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST
_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_entropy.2283982846
Directory /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/32.alert_handler_entropy/latest

Test location /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default/32.alert_handler_esc_alert_accum.1499568949
Short name T532
Test name
Test status
Simulation time 1947399825 ps
CPU time 164.19 seconds
Started Feb 08 08:19:42 PM UTC 25
Finished Feb 08 08:22:29 PM UTC 25
Peak memory 269360 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo
/hw/dv/tools/sim.tcl +ntb_random_seed=1499568949 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_ac
cum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 32.alert_handler_esc_alert_accum.1499568949
Directory /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/32.alert_handler_esc_alert_accum/latest

Test location /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default/32.alert_handler_esc_intr_timeout.4025450466
Short name T530
Test name
Test status
Simulation time 661630679 ps
CPU time 34.67 seconds
Started Feb 08 08:19:33 PM UTC 25
Finished Feb 08 08:20:09 PM UTC 25
Peak memory 263212 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo
/hw/dv/tools/sim.tcl +ntb_random_seed=4025450466 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_tim
eout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 32.alert_handler_esc_intr_timeout.4025450466
Directory /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/32.alert_handler_esc_intr_timeout/latest

Test location /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default/32.alert_handler_lpg.4094495150
Short name T376
Test name
Test status
Simulation time 31917325574 ps
CPU time 1284.9 seconds
Started Feb 08 08:20:22 PM UTC 25
Finished Feb 08 08:42:03 PM UTC 25
Peak memory 285728 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4094495150 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST
_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_lpg.4094495150
Directory /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/32.alert_handler_lpg/latest

Test location /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default/32.alert_handler_lpg_stub_clk.1558737760
Short name T292
Test name
Test status
Simulation time 55561318249 ps
CPU time 3461.66 seconds
Started Feb 08 08:20:33 PM UTC 25
Finished Feb 08 09:18:53 PM UTC 25
Peak memory 304856 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1558737760 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST
_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/alert_handler-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_lpg_stub_clk.1558737760
Directory /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/32.alert_handler_lpg_stub_clk/latest

Test location /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default/32.alert_handler_ping_timeout.551510450
Short name T242
Test name
Test status
Simulation time 7516261556 ps
CPU time 336.52 seconds
Started Feb 08 08:20:10 PM UTC 25
Finished Feb 08 08:25:51 PM UTC 25
Peak memory 263460 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=551510450 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_
SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/alert_handler-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_ping_timeout.551510450
Directory /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/32.alert_handler_ping_timeout/latest

Test location /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default/32.alert_handler_random_alerts.2408299541
Short name T531
Test name
Test status
Simulation time 3004265888 ps
CPU time 73.22 seconds
Started Feb 08 08:19:18 PM UTC 25
Finished Feb 08 08:20:33 PM UTC 25
Peak memory 269420 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo
/hw/dv/tools/sim.tcl +ntb_random_seed=2408299541 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alert
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default.vdb -cm
_log /dev/null -cm_name 32.alert_handler_random_alerts.2408299541
Directory /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/32.alert_handler_random_alerts/latest

Test location /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default/32.alert_handler_random_classes.893022555
Short name T142
Test name
Test status
Simulation time 1023820130 ps
CPU time 56.56 seconds
Started Feb 08 08:19:23 PM UTC 25
Finished Feb 08 08:20:21 PM UTC 25
Peak memory 263136 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo
/hw/dv/tools/sim.tcl +ntb_random_seed=893022555 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classe
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default.vdb -cm
_log /dev/null -cm_name 32.alert_handler_random_classes.893022555
Directory /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/32.alert_handler_random_classes/latest

Test location /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default/32.alert_handler_sig_int_fail.1044200289
Short name T127
Test name
Test status
Simulation time 352708636 ps
CPU time 34.11 seconds
Started Feb 08 08:20:00 PM UTC 25
Finished Feb 08 08:20:35 PM UTC 25
Peak memory 263408 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo
/hw/dv/tools/sim.tcl +ntb_random_seed=1044200289 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default.vdb -cm_
log /dev/null -cm_name 32.alert_handler_sig_int_fail.1044200289
Directory /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/32.alert_handler_sig_int_fail/latest

Test location /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default/32.alert_handler_smoke.2213550982
Short name T529
Test name
Test status
Simulation time 320627844 ps
CPU time 46.41 seconds
Started Feb 08 08:18:53 PM UTC 25
Finished Feb 08 08:19:41 PM UTC 25
Peak memory 269280 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo
/hw/dv/tools/sim.tcl +ntb_random_seed=2213550982 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default.vdb -cm_log /de
v/null -cm_name 32.alert_handler_smoke.2213550982
Directory /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/32.alert_handler_smoke/latest

Test location /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default/32.alert_handler_stress_all_with_rand_reset.2639259847
Short name T223
Test name
Test status
Simulation time 264717042507 ps
CPU time 8556.78 seconds
Started Feb 08 08:22:30 PM UTC 25
Finished Feb 08 10:46:45 PM UTC 25
Peak memory 403372 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=ale
rt_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=26392
59847 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_stress_al
l_with_rand_reset.2639259847
Directory /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/32.alert_handler_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default/33.alert_handler_entropy.664561236
Short name T629
Test name
Test status
Simulation time 204080516295 ps
CPU time 2413.66 seconds
Started Feb 08 08:25:03 PM UTC 25
Finished Feb 08 09:05:44 PM UTC 25
Peak memory 304892 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=664561236 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_
SEQ=alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/
coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_entropy.664561236
Directory /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/33.alert_handler_entropy/latest

Test location /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default/33.alert_handler_esc_alert_accum.2405512904
Short name T303
Test name
Test status
Simulation time 8889517953 ps
CPU time 361.22 seconds
Started Feb 08 08:24:46 PM UTC 25
Finished Feb 08 08:30:52 PM UTC 25
Peak memory 269352 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo
/hw/dv/tools/sim.tcl +ntb_random_seed=2405512904 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_ac
cum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 33.alert_handler_esc_alert_accum.2405512904
Directory /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/33.alert_handler_esc_alert_accum/latest

Test location /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default/33.alert_handler_esc_intr_timeout.1809873458
Short name T240
Test name
Test status
Simulation time 2446891856 ps
CPU time 59.33 seconds
Started Feb 08 08:24:24 PM UTC 25
Finished Feb 08 08:25:26 PM UTC 25
Peak memory 269348 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo
/hw/dv/tools/sim.tcl +ntb_random_seed=1809873458 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_tim
eout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 33.alert_handler_esc_intr_timeout.1809873458
Directory /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/33.alert_handler_esc_intr_timeout/latest

Test location /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default/33.alert_handler_lpg.3467997050
Short name T387
Test name
Test status
Simulation time 40289685368 ps
CPU time 2426.38 seconds
Started Feb 08 08:25:26 PM UTC 25
Finished Feb 08 09:06:19 PM UTC 25
Peak memory 298748 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3467997050 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST
_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_lpg.3467997050
Directory /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/33.alert_handler_lpg/latest

Test location /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default/33.alert_handler_lpg_stub_clk.1578037992
Short name T575
Test name
Test status
Simulation time 19974546293 ps
CPU time 997.41 seconds
Started Feb 08 08:25:46 PM UTC 25
Finished Feb 08 08:42:35 PM UTC 25
Peak memory 285728 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1578037992 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST
_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/alert_handler-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_lpg_stub_clk.1578037992
Directory /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/33.alert_handler_lpg_stub_clk/latest

Test location /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default/33.alert_handler_ping_timeout.3693754478
Short name T359
Test name
Test status
Simulation time 11949196417 ps
CPU time 276.45 seconds
Started Feb 08 08:25:17 PM UTC 25
Finished Feb 08 08:29:58 PM UTC 25
Peak memory 263196 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3693754478 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST
_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/alert_handler-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_ping_timeout.3693754478
Directory /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/33.alert_handler_ping_timeout/latest

Test location /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default/33.alert_handler_random_alerts.1074274611
Short name T239
Test name
Test status
Simulation time 3265176928 ps
CPU time 63.04 seconds
Started Feb 08 08:24:12 PM UTC 25
Finished Feb 08 08:25:17 PM UTC 25
Peak memory 269348 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo
/hw/dv/tools/sim.tcl +ntb_random_seed=1074274611 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alert
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default.vdb -cm
_log /dev/null -cm_name 33.alert_handler_random_alerts.1074274611
Directory /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/33.alert_handler_random_alerts/latest

Test location /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default/33.alert_handler_random_classes.728086911
Short name T241
Test name
Test status
Simulation time 2249722438 ps
CPU time 83.92 seconds
Started Feb 08 08:24:19 PM UTC 25
Finished Feb 08 08:25:45 PM UTC 25
Peak memory 263200 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo
/hw/dv/tools/sim.tcl +ntb_random_seed=728086911 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classe
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default.vdb -cm
_log /dev/null -cm_name 33.alert_handler_random_classes.728086911
Directory /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/33.alert_handler_random_classes/latest

Test location /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default/33.alert_handler_sig_int_fail.377601094
Short name T243
Test name
Test status
Simulation time 7823865485 ps
CPU time 59.71 seconds
Started Feb 08 08:24:55 PM UTC 25
Finished Feb 08 08:25:56 PM UTC 25
Peak memory 269348 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo
/hw/dv/tools/sim.tcl +ntb_random_seed=377601094 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default.vdb -cm_l
og /dev/null -cm_name 33.alert_handler_sig_int_fail.377601094
Directory /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/33.alert_handler_sig_int_fail/latest

Test location /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default/33.alert_handler_smoke.3090316765
Short name T534
Test name
Test status
Simulation time 291814485 ps
CPU time 9.87 seconds
Started Feb 08 08:24:07 PM UTC 25
Finished Feb 08 08:24:18 PM UTC 25
Peak memory 265184 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo
/hw/dv/tools/sim.tcl +ntb_random_seed=3090316765 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default.vdb -cm_log /de
v/null -cm_name 33.alert_handler_smoke.3090316765
Directory /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/33.alert_handler_smoke/latest

Test location /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default/33.alert_handler_stress_all.2271307834
Short name T110
Test name
Test status
Simulation time 47805865261 ps
CPU time 3282.89 seconds
Started Feb 08 08:25:52 PM UTC 25
Finished Feb 08 09:21:10 PM UTC 25
Peak memory 315136 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2271307834 -assert nopostproc +UVM_TESTNAME=ale
rt_handler_base_test +UVM_TEST_SEQ=alert_handler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os
_regression/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_stress_all.2271307834
Directory /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/33.alert_handler_stress_all/latest

Test location /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default/34.alert_handler_entropy.1194629960
Short name T601
Test name
Test status
Simulation time 25607760024 ps
CPU time 1410.33 seconds
Started Feb 08 08:27:39 PM UTC 25
Finished Feb 08 08:51:26 PM UTC 25
Peak memory 302112 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1194629960 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST
_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_entropy.1194629960
Directory /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/34.alert_handler_entropy/latest

Test location /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default/34.alert_handler_esc_alert_accum.3634380898
Short name T542
Test name
Test status
Simulation time 7054100769 ps
CPU time 208.52 seconds
Started Feb 08 08:27:33 PM UTC 25
Finished Feb 08 08:31:05 PM UTC 25
Peak memory 269424 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo
/hw/dv/tools/sim.tcl +ntb_random_seed=3634380898 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_ac
cum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 34.alert_handler_esc_alert_accum.3634380898
Directory /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/34.alert_handler_esc_alert_accum/latest

Test location /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default/34.alert_handler_esc_intr_timeout.83739142
Short name T118
Test name
Test status
Simulation time 2049279872 ps
CPU time 55.26 seconds
Started Feb 08 08:27:03 PM UTC 25
Finished Feb 08 08:28:00 PM UTC 25
Peak memory 263140 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo
/hw/dv/tools/sim.tcl +ntb_random_seed=83739142 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeo
ut_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default.vdb -c
m_log /dev/null -cm_name 34.alert_handler_esc_intr_timeout.83739142
Directory /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/34.alert_handler_esc_intr_timeout/latest

Test location /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default/34.alert_handler_lpg.1303580034
Short name T662
Test name
Test status
Simulation time 852241761125 ps
CPU time 2698.41 seconds
Started Feb 08 08:28:51 PM UTC 25
Finished Feb 08 09:14:17 PM UTC 25
Peak memory 305000 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1303580034 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST
_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_lpg.1303580034
Directory /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/34.alert_handler_lpg/latest

Test location /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default/34.alert_handler_lpg_stub_clk.1355588598
Short name T602
Test name
Test status
Simulation time 13252515747 ps
CPU time 1326.89 seconds
Started Feb 08 08:29:07 PM UTC 25
Finished Feb 08 08:51:29 PM UTC 25
Peak memory 298012 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1355588598 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST
_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/alert_handler-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_lpg_stub_clk.1355588598
Directory /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/34.alert_handler_lpg_stub_clk/latest

Test location /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default/34.alert_handler_ping_timeout.4087546133
Short name T554
Test name
Test status
Simulation time 30576459003 ps
CPU time 389.55 seconds
Started Feb 08 08:28:01 PM UTC 25
Finished Feb 08 08:34:36 PM UTC 25
Peak memory 263396 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4087546133 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST
_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/alert_handler-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_ping_timeout.4087546133
Directory /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/34.alert_handler_ping_timeout/latest

Test location /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default/34.alert_handler_random_alerts.464353695
Short name T246
Test name
Test status
Simulation time 557840809 ps
CPU time 22.09 seconds
Started Feb 08 08:26:39 PM UTC 25
Finished Feb 08 08:27:02 PM UTC 25
Peak memory 263136 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo
/hw/dv/tools/sim.tcl +ntb_random_seed=464353695 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default.vdb -cm_
log /dev/null -cm_name 34.alert_handler_random_alerts.464353695
Directory /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/34.alert_handler_random_alerts/latest

Test location /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default/34.alert_handler_random_classes.2129877504
Short name T537
Test name
Test status
Simulation time 382319687 ps
CPU time 34.64 seconds
Started Feb 08 08:26:58 PM UTC 25
Finished Feb 08 08:27:34 PM UTC 25
Peak memory 263140 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo
/hw/dv/tools/sim.tcl +ntb_random_seed=2129877504 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_class
es_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default.vdb -c
m_log /dev/null -cm_name 34.alert_handler_random_classes.2129877504
Directory /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/34.alert_handler_random_classes/latest

Test location /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default/34.alert_handler_smoke.4277589441
Short name T244
Test name
Test status
Simulation time 1334270754 ps
CPU time 39.35 seconds
Started Feb 08 08:25:57 PM UTC 25
Finished Feb 08 08:26:37 PM UTC 25
Peak memory 269544 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo
/hw/dv/tools/sim.tcl +ntb_random_seed=4277589441 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default.vdb -cm_log /de
v/null -cm_name 34.alert_handler_smoke.4277589441
Directory /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/34.alert_handler_smoke/latest

Test location /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default/34.alert_handler_stress_all.214903071
Short name T541
Test name
Test status
Simulation time 1003871850 ps
CPU time 40.19 seconds
Started Feb 08 08:29:59 PM UTC 25
Finished Feb 08 08:30:41 PM UTC 25
Peak memory 269424 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=214903071 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_
regression/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_stress_all.214903071
Directory /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/34.alert_handler_stress_all/latest

Test location /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default/35.alert_handler_entropy.116410791
Short name T108
Test name
Test status
Simulation time 114807116606 ps
CPU time 2490.15 seconds
Started Feb 08 08:31:15 PM UTC 25
Finished Feb 08 09:13:14 PM UTC 25
Peak memory 304868 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=116410791 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_
SEQ=alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/
coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_entropy.116410791
Directory /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/35.alert_handler_entropy/latest

Test location /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default/35.alert_handler_esc_alert_accum.1407629273
Short name T549
Test name
Test status
Simulation time 4701011659 ps
CPU time 138.11 seconds
Started Feb 08 08:31:09 PM UTC 25
Finished Feb 08 08:33:30 PM UTC 25
Peak memory 265584 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo
/hw/dv/tools/sim.tcl +ntb_random_seed=1407629273 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_ac
cum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 35.alert_handler_esc_alert_accum.1407629273
Directory /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/35.alert_handler_esc_alert_accum/latest

Test location /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default/35.alert_handler_esc_intr_timeout.3193476942
Short name T544
Test name
Test status
Simulation time 111188477 ps
CPU time 11.98 seconds
Started Feb 08 08:31:06 PM UTC 25
Finished Feb 08 08:31:20 PM UTC 25
Peak memory 263140 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo
/hw/dv/tools/sim.tcl +ntb_random_seed=3193476942 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_tim
eout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 35.alert_handler_esc_intr_timeout.3193476942
Directory /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/35.alert_handler_esc_intr_timeout/latest

Test location /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default/35.alert_handler_lpg.4103032382
Short name T683
Test name
Test status
Simulation time 39897123063 ps
CPU time 2906.51 seconds
Started Feb 08 08:31:55 PM UTC 25
Finished Feb 08 09:20:54 PM UTC 25
Peak memory 305128 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4103032382 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST
_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_lpg.4103032382
Directory /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/35.alert_handler_lpg/latest

Test location /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default/35.alert_handler_lpg_stub_clk.2060903587
Short name T599
Test name
Test status
Simulation time 9697532340 ps
CPU time 1113.33 seconds
Started Feb 08 08:32:04 PM UTC 25
Finished Feb 08 08:50:51 PM UTC 25
Peak memory 285756 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2060903587 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST
_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/alert_handler-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_lpg_stub_clk.2060903587
Directory /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/35.alert_handler_lpg_stub_clk/latest

Test location /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default/35.alert_handler_ping_timeout.387638795
Short name T558
Test name
Test status
Simulation time 24578798401 ps
CPU time 238.19 seconds
Started Feb 08 08:31:21 PM UTC 25
Finished Feb 08 08:35:22 PM UTC 25
Peak memory 263196 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=387638795 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_
SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/alert_handler-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_ping_timeout.387638795
Directory /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/35.alert_handler_ping_timeout/latest

Test location /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default/35.alert_handler_random_alerts.370935520
Short name T547
Test name
Test status
Simulation time 2679114712 ps
CPU time 97.03 seconds
Started Feb 08 08:30:42 PM UTC 25
Finished Feb 08 08:32:21 PM UTC 25
Peak memory 269344 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo
/hw/dv/tools/sim.tcl +ntb_random_seed=370935520 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default.vdb -cm_
log /dev/null -cm_name 35.alert_handler_random_alerts.370935520
Directory /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/35.alert_handler_random_alerts/latest

Test location /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default/35.alert_handler_random_classes.2327606206
Short name T546
Test name
Test status
Simulation time 2901608245 ps
CPU time 68.02 seconds
Started Feb 08 08:30:53 PM UTC 25
Finished Feb 08 08:32:03 PM UTC 25
Peak memory 269420 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo
/hw/dv/tools/sim.tcl +ntb_random_seed=2327606206 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_class
es_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default.vdb -c
m_log /dev/null -cm_name 35.alert_handler_random_classes.2327606206
Directory /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/35.alert_handler_random_classes/latest

Test location /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default/35.alert_handler_sig_int_fail.1689773561
Short name T545
Test name
Test status
Simulation time 245325250 ps
CPU time 36.99 seconds
Started Feb 08 08:31:15 PM UTC 25
Finished Feb 08 08:31:54 PM UTC 25
Peak memory 263144 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo
/hw/dv/tools/sim.tcl +ntb_random_seed=1689773561 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default.vdb -cm_
log /dev/null -cm_name 35.alert_handler_sig_int_fail.1689773561
Directory /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/35.alert_handler_sig_int_fail/latest

Test location /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default/35.alert_handler_smoke.432873353
Short name T543
Test name
Test status
Simulation time 1173064054 ps
CPU time 43.19 seconds
Started Feb 08 08:30:30 PM UTC 25
Finished Feb 08 08:31:14 PM UTC 25
Peak memory 269280 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo
/hw/dv/tools/sim.tcl +ntb_random_seed=432873353 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev
/null -cm_name 35.alert_handler_smoke.432873353
Directory /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/35.alert_handler_smoke/latest

Test location /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default/35.alert_handler_stress_all.2763086688
Short name T688
Test name
Test status
Simulation time 89740468839 ps
CPU time 3144.03 seconds
Started Feb 08 08:32:22 PM UTC 25
Finished Feb 08 09:25:21 PM UTC 25
Peak memory 304868 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2763086688 -assert nopostproc +UVM_TESTNAME=ale
rt_handler_base_test +UVM_TEST_SEQ=alert_handler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os
_regression/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_stress_all.2763086688
Directory /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/35.alert_handler_stress_all/latest

Test location /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default/36.alert_handler_entropy.3125180446
Short name T120
Test name
Test status
Simulation time 93930432826 ps
CPU time 1103.66 seconds
Started Feb 08 08:35:04 PM UTC 25
Finished Feb 08 08:53:40 PM UTC 25
Peak memory 296068 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3125180446 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST
_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_entropy.3125180446
Directory /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/36.alert_handler_entropy/latest

Test location /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default/36.alert_handler_esc_alert_accum.2481534459
Short name T559
Test name
Test status
Simulation time 755762392 ps
CPU time 60.97 seconds
Started Feb 08 08:34:36 PM UTC 25
Finished Feb 08 08:35:39 PM UTC 25
Peak memory 269356 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo
/hw/dv/tools/sim.tcl +ntb_random_seed=2481534459 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_ac
cum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 36.alert_handler_esc_alert_accum.2481534459
Directory /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/36.alert_handler_esc_alert_accum/latest

Test location /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default/36.alert_handler_esc_intr_timeout.1923927132
Short name T555
Test name
Test status
Simulation time 3775620258 ps
CPU time 38.11 seconds
Started Feb 08 08:34:22 PM UTC 25
Finished Feb 08 08:35:01 PM UTC 25
Peak memory 263468 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo
/hw/dv/tools/sim.tcl +ntb_random_seed=1923927132 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_tim
eout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 36.alert_handler_esc_intr_timeout.1923927132
Directory /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/36.alert_handler_esc_intr_timeout/latest

Test location /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default/36.alert_handler_lpg_stub_clk.2882534010
Short name T611
Test name
Test status
Simulation time 23328474721 ps
CPU time 1310.13 seconds
Started Feb 08 08:35:23 PM UTC 25
Finished Feb 08 08:57:28 PM UTC 25
Peak memory 285828 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2882534010 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST
_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/alert_handler-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_lpg_stub_clk.2882534010
Directory /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/36.alert_handler_lpg_stub_clk/latest

Test location /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default/36.alert_handler_ping_timeout.1960758426
Short name T585
Test name
Test status
Simulation time 69943602291 ps
CPU time 691.05 seconds
Started Feb 08 08:35:04 PM UTC 25
Finished Feb 08 08:46:43 PM UTC 25
Peak memory 263196 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1960758426 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST
_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/alert_handler-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_ping_timeout.1960758426
Directory /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/36.alert_handler_ping_timeout/latest

Test location /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default/36.alert_handler_random_alerts.2156343957
Short name T553
Test name
Test status
Simulation time 1996206649 ps
CPU time 44.85 seconds
Started Feb 08 08:33:48 PM UTC 25
Finished Feb 08 08:34:35 PM UTC 25
Peak memory 269548 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo
/hw/dv/tools/sim.tcl +ntb_random_seed=2156343957 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alert
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default.vdb -cm
_log /dev/null -cm_name 36.alert_handler_random_alerts.2156343957
Directory /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/36.alert_handler_random_alerts/latest

Test location /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default/36.alert_handler_random_classes.3173603886
Short name T552
Test name
Test status
Simulation time 444294236 ps
CPU time 22.42 seconds
Started Feb 08 08:33:57 PM UTC 25
Finished Feb 08 08:34:21 PM UTC 25
Peak memory 269356 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo
/hw/dv/tools/sim.tcl +ntb_random_seed=3173603886 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_class
es_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default.vdb -c
m_log /dev/null -cm_name 36.alert_handler_random_classes.3173603886
Directory /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/36.alert_handler_random_classes/latest

Test location /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default/36.alert_handler_sig_int_fail.1211296431
Short name T557
Test name
Test status
Simulation time 339460830 ps
CPU time 34.25 seconds
Started Feb 08 08:34:37 PM UTC 25
Finished Feb 08 08:35:13 PM UTC 25
Peak memory 263144 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo
/hw/dv/tools/sim.tcl +ntb_random_seed=1211296431 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default.vdb -cm_
log /dev/null -cm_name 36.alert_handler_sig_int_fail.1211296431
Directory /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/36.alert_handler_sig_int_fail/latest

Test location /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default/36.alert_handler_smoke.816210707
Short name T551
Test name
Test status
Simulation time 233510659 ps
CPU time 23.6 seconds
Started Feb 08 08:33:31 PM UTC 25
Finished Feb 08 08:33:56 PM UTC 25
Peak memory 269544 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo
/hw/dv/tools/sim.tcl +ntb_random_seed=816210707 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev
/null -cm_name 36.alert_handler_smoke.816210707
Directory /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/36.alert_handler_smoke/latest

Test location /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default/36.alert_handler_stress_all.3410570144
Short name T617
Test name
Test status
Simulation time 107171557434 ps
CPU time 1449.83 seconds
Started Feb 08 08:35:35 PM UTC 25
Finished Feb 08 09:00:01 PM UTC 25
Peak memory 302216 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3410570144 -assert nopostproc +UVM_TESTNAME=ale
rt_handler_base_test +UVM_TEST_SEQ=alert_handler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os
_regression/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_stress_all.3410570144
Directory /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/36.alert_handler_stress_all/latest

Test location /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default/36.alert_handler_stress_all_with_rand_reset.1319090769
Short name T72
Test name
Test status
Simulation time 41624874343 ps
CPU time 1339.74 seconds
Started Feb 08 08:35:39 PM UTC 25
Finished Feb 08 08:58:15 PM UTC 25
Peak memory 302244 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=ale
rt_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=13190
90769 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_stress_al
l_with_rand_reset.1319090769
Directory /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/36.alert_handler_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default/37.alert_handler_entropy.4219446390
Short name T654
Test name
Test status
Simulation time 29736361936 ps
CPU time 2065.21 seconds
Started Feb 08 08:37:41 PM UTC 25
Finished Feb 08 09:12:29 PM UTC 25
Peak memory 285892 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4219446390 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST
_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_entropy.4219446390
Directory /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/37.alert_handler_entropy/latest

Test location /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default/37.alert_handler_esc_alert_accum.1196748690
Short name T566
Test name
Test status
Simulation time 2756331727 ps
CPU time 138.58 seconds
Started Feb 08 08:37:13 PM UTC 25
Finished Feb 08 08:39:34 PM UTC 25
Peak memory 269424 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo
/hw/dv/tools/sim.tcl +ntb_random_seed=1196748690 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_ac
cum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 37.alert_handler_esc_alert_accum.1196748690
Directory /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/37.alert_handler_esc_alert_accum/latest

Test location /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default/37.alert_handler_esc_intr_timeout.1474048216
Short name T565
Test name
Test status
Simulation time 1173218954 ps
CPU time 93.46 seconds
Started Feb 08 08:37:13 PM UTC 25
Finished Feb 08 08:38:49 PM UTC 25
Peak memory 263212 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo
/hw/dv/tools/sim.tcl +ntb_random_seed=1474048216 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_tim
eout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 37.alert_handler_esc_intr_timeout.1474048216
Directory /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/37.alert_handler_esc_intr_timeout/latest

Test location /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default/37.alert_handler_lpg.2320298590
Short name T635
Test name
Test status
Simulation time 164583218128 ps
CPU time 1778.75 seconds
Started Feb 08 08:37:58 PM UTC 25
Finished Feb 08 09:07:56 PM UTC 25
Peak memory 286060 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2320298590 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST
_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_lpg.2320298590
Directory /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/37.alert_handler_lpg/latest

Test location /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default/37.alert_handler_lpg_stub_clk.116947244
Short name T625
Test name
Test status
Simulation time 365503563784 ps
CPU time 1466.79 seconds
Started Feb 08 08:38:20 PM UTC 25
Finished Feb 08 09:03:04 PM UTC 25
Peak memory 279852 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=116947244 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_
SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/alert_handler-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_lpg_stub_clk.116947244
Directory /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/37.alert_handler_lpg_stub_clk/latest

Test location /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default/37.alert_handler_ping_timeout.3593887671
Short name T584
Test name
Test status
Simulation time 8892013290 ps
CPU time 513.64 seconds
Started Feb 08 08:37:58 PM UTC 25
Finished Feb 08 08:46:38 PM UTC 25
Peak memory 263204 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3593887671 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST
_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/alert_handler-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_ping_timeout.3593887671
Directory /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/37.alert_handler_ping_timeout/latest

Test location /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default/37.alert_handler_random_alerts.1725452568
Short name T562
Test name
Test status
Simulation time 2075127417 ps
CPU time 72.67 seconds
Started Feb 08 08:35:58 PM UTC 25
Finished Feb 08 08:37:12 PM UTC 25
Peak memory 263404 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo
/hw/dv/tools/sim.tcl +ntb_random_seed=1725452568 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alert
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default.vdb -cm
_log /dev/null -cm_name 37.alert_handler_random_alerts.1725452568
Directory /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/37.alert_handler_random_alerts/latest

Test location /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default/37.alert_handler_random_classes.1616967597
Short name T143
Test name
Test status
Simulation time 6655849556 ps
CPU time 79.99 seconds
Started Feb 08 08:36:57 PM UTC 25
Finished Feb 08 08:38:19 PM UTC 25
Peak memory 263276 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo
/hw/dv/tools/sim.tcl +ntb_random_seed=1616967597 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_class
es_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default.vdb -c
m_log /dev/null -cm_name 37.alert_handler_random_classes.1616967597
Directory /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/37.alert_handler_random_classes/latest

Test location /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default/37.alert_handler_sig_int_fail.1944085286
Short name T563
Test name
Test status
Simulation time 126967927 ps
CPU time 15.91 seconds
Started Feb 08 08:37:23 PM UTC 25
Finished Feb 08 08:37:40 PM UTC 25
Peak memory 263144 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo
/hw/dv/tools/sim.tcl +ntb_random_seed=1944085286 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default.vdb -cm_
log /dev/null -cm_name 37.alert_handler_sig_int_fail.1944085286
Directory /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/37.alert_handler_sig_int_fail/latest

Test location /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default/37.alert_handler_smoke.1400344724
Short name T560
Test name
Test status
Simulation time 60058196 ps
CPU time 11.75 seconds
Started Feb 08 08:35:44 PM UTC 25
Finished Feb 08 08:35:57 PM UTC 25
Peak memory 269544 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo
/hw/dv/tools/sim.tcl +ntb_random_seed=1400344724 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default.vdb -cm_log /de
v/null -cm_name 37.alert_handler_smoke.1400344724
Directory /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/37.alert_handler_smoke/latest

Test location /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default/37.alert_handler_stress_all.2828387535
Short name T705
Test name
Test status
Simulation time 148953866501 ps
CPU time 4413.52 seconds
Started Feb 08 08:38:36 PM UTC 25
Finished Feb 08 09:52:57 PM UTC 25
Peak memory 319280 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2828387535 -assert nopostproc +UVM_TESTNAME=ale
rt_handler_base_test +UVM_TEST_SEQ=alert_handler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os
_regression/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_stress_all.2828387535
Directory /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/37.alert_handler_stress_all/latest

Test location /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default/38.alert_handler_entropy.12362003
Short name T665
Test name
Test status
Simulation time 110697377261 ps
CPU time 1978.53 seconds
Started Feb 08 08:41:47 PM UTC 25
Finished Feb 08 09:15:08 PM UTC 25
Peak memory 302184 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=12362003 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_S
EQ=alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_entropy.12362003
Directory /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/38.alert_handler_entropy/latest

Test location /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default/38.alert_handler_esc_alert_accum.4044534973
Short name T576
Test name
Test status
Simulation time 1878864175 ps
CPU time 126.32 seconds
Started Feb 08 08:40:49 PM UTC 25
Finished Feb 08 08:42:57 PM UTC 25
Peak memory 269284 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo
/hw/dv/tools/sim.tcl +ntb_random_seed=4044534973 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_ac
cum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 38.alert_handler_esc_alert_accum.4044534973
Directory /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/38.alert_handler_esc_alert_accum/latest

Test location /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default/38.alert_handler_esc_intr_timeout.2220111701
Short name T572
Test name
Test status
Simulation time 622180640 ps
CPU time 63.27 seconds
Started Feb 08 08:40:47 PM UTC 25
Finished Feb 08 08:41:52 PM UTC 25
Peak memory 269284 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo
/hw/dv/tools/sim.tcl +ntb_random_seed=2220111701 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_tim
eout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 38.alert_handler_esc_intr_timeout.2220111701
Directory /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/38.alert_handler_esc_intr_timeout/latest

Test location /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default/38.alert_handler_lpg.2940192800
Short name T637
Test name
Test status
Simulation time 69327963575 ps
CPU time 1552.58 seconds
Started Feb 08 08:42:06 PM UTC 25
Finished Feb 08 09:08:17 PM UTC 25
Peak memory 285800 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2940192800 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST
_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_lpg.2940192800
Directory /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/38.alert_handler_lpg/latest

Test location /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default/38.alert_handler_lpg_stub_clk.707680231
Short name T670
Test name
Test status
Simulation time 76519494728 ps
CPU time 1985.55 seconds
Started Feb 08 08:42:17 PM UTC 25
Finished Feb 08 09:15:46 PM UTC 25
Peak memory 302440 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=707680231 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_
SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/alert_handler-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_lpg_stub_clk.707680231
Directory /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/38.alert_handler_lpg_stub_clk/latest

Test location /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default/38.alert_handler_ping_timeout.2149913683
Short name T353
Test name
Test status
Simulation time 22073483300 ps
CPU time 170.34 seconds
Started Feb 08 08:41:53 PM UTC 25
Finished Feb 08 08:44:46 PM UTC 25
Peak memory 263196 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2149913683 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST
_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/alert_handler-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_ping_timeout.2149913683
Directory /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/38.alert_handler_ping_timeout/latest

Test location /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default/38.alert_handler_random_alerts.1879977738
Short name T570
Test name
Test status
Simulation time 724526627 ps
CPU time 71.28 seconds
Started Feb 08 08:40:13 PM UTC 25
Finished Feb 08 08:41:26 PM UTC 25
Peak memory 269356 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo
/hw/dv/tools/sim.tcl +ntb_random_seed=1879977738 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alert
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default.vdb -cm
_log /dev/null -cm_name 38.alert_handler_random_alerts.1879977738
Directory /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/38.alert_handler_random_alerts/latest

Test location /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default/38.alert_handler_random_classes.1580418644
Short name T571
Test name
Test status
Simulation time 811905365 ps
CPU time 76.9 seconds
Started Feb 08 08:40:27 PM UTC 25
Finished Feb 08 08:41:46 PM UTC 25
Peak memory 263404 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo
/hw/dv/tools/sim.tcl +ntb_random_seed=1580418644 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_class
es_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default.vdb -c
m_log /dev/null -cm_name 38.alert_handler_random_classes.1580418644
Directory /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/38.alert_handler_random_classes/latest

Test location /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default/38.alert_handler_sig_int_fail.3632518892
Short name T574
Test name
Test status
Simulation time 660182007 ps
CPU time 52.82 seconds
Started Feb 08 08:41:27 PM UTC 25
Finished Feb 08 08:42:22 PM UTC 25
Peak memory 263408 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo
/hw/dv/tools/sim.tcl +ntb_random_seed=3632518892 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default.vdb -cm_
log /dev/null -cm_name 38.alert_handler_sig_int_fail.3632518892
Directory /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/38.alert_handler_sig_int_fail/latest

Test location /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default/38.alert_handler_smoke.2365514855
Short name T568
Test name
Test status
Simulation time 2044985747 ps
CPU time 48.73 seconds
Started Feb 08 08:39:35 PM UTC 25
Finished Feb 08 08:40:26 PM UTC 25
Peak memory 269544 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo
/hw/dv/tools/sim.tcl +ntb_random_seed=2365514855 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default.vdb -cm_log /de
v/null -cm_name 38.alert_handler_smoke.2365514855
Directory /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/38.alert_handler_smoke/latest

Test location /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default/38.alert_handler_stress_all.298816255
Short name T326
Test name
Test status
Simulation time 66290889300 ps
CPU time 4046.17 seconds
Started Feb 08 08:42:22 PM UTC 25
Finished Feb 08 09:50:33 PM UTC 25
Peak memory 315112 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=298816255 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_
regression/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_stress_all.298816255
Directory /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/38.alert_handler_stress_all/latest

Test location /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default/39.alert_handler_entropy.3779040759
Short name T645
Test name
Test status
Simulation time 17655644784 ps
CPU time 1459.97 seconds
Started Feb 08 08:45:08 PM UTC 25
Finished Feb 08 09:09:46 PM UTC 25
Peak memory 301988 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3779040759 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST
_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_entropy.3779040759
Directory /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/39.alert_handler_entropy/latest

Test location /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default/39.alert_handler_esc_alert_accum.4000201852
Short name T583
Test name
Test status
Simulation time 583655356 ps
CPU time 72.01 seconds
Started Feb 08 08:44:21 PM UTC 25
Finished Feb 08 08:45:35 PM UTC 25
Peak memory 269360 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo
/hw/dv/tools/sim.tcl +ntb_random_seed=4000201852 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_ac
cum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 39.alert_handler_esc_alert_accum.4000201852
Directory /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/39.alert_handler_esc_alert_accum/latest

Test location /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default/39.alert_handler_esc_intr_timeout.2914760292
Short name T582
Test name
Test status
Simulation time 3051306351 ps
CPU time 65.46 seconds
Started Feb 08 08:44:18 PM UTC 25
Finished Feb 08 08:45:25 PM UTC 25
Peak memory 269348 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo
/hw/dv/tools/sim.tcl +ntb_random_seed=2914760292 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_tim
eout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 39.alert_handler_esc_intr_timeout.2914760292
Directory /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/39.alert_handler_esc_intr_timeout/latest

Test location /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default/39.alert_handler_lpg.1089705929
Short name T674
Test name
Test status
Simulation time 69404064333 ps
CPU time 1852.14 seconds
Started Feb 08 08:45:27 PM UTC 25
Finished Feb 08 09:16:41 PM UTC 25
Peak memory 302376 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1089705929 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST
_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_lpg.1089705929
Directory /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/39.alert_handler_lpg/latest

Test location /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default/39.alert_handler_lpg_stub_clk.3529209599
Short name T684
Test name
Test status
Simulation time 395873933948 ps
CPU time 2162.19 seconds
Started Feb 08 08:45:36 PM UTC 25
Finished Feb 08 09:22:02 PM UTC 25
Peak memory 298712 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3529209599 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST
_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/alert_handler-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_lpg_stub_clk.3529209599
Directory /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/39.alert_handler_lpg_stub_clk/latest

Test location /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default/39.alert_handler_ping_timeout.437490878
Short name T608
Test name
Test status
Simulation time 10510766762 ps
CPU time 515.63 seconds
Started Feb 08 08:45:08 PM UTC 25
Finished Feb 08 08:53:51 PM UTC 25
Peak memory 263116 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=437490878 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_
SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/alert_handler-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_ping_timeout.437490878
Directory /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/39.alert_handler_ping_timeout/latest

Test location /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default/39.alert_handler_random_alerts.3730845426
Short name T579
Test name
Test status
Simulation time 2713427538 ps
CPU time 66.34 seconds
Started Feb 08 08:43:12 PM UTC 25
Finished Feb 08 08:44:20 PM UTC 25
Peak memory 269612 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo
/hw/dv/tools/sim.tcl +ntb_random_seed=3730845426 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alert
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default.vdb -cm
_log /dev/null -cm_name 39.alert_handler_random_alerts.3730845426
Directory /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/39.alert_handler_random_alerts/latest

Test location /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default/39.alert_handler_random_classes.3623505915
Short name T578
Test name
Test status
Simulation time 1127784308 ps
CPU time 53.54 seconds
Started Feb 08 08:43:22 PM UTC 25
Finished Feb 08 08:44:17 PM UTC 25
Peak memory 263404 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo
/hw/dv/tools/sim.tcl +ntb_random_seed=3623505915 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_class
es_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default.vdb -c
m_log /dev/null -cm_name 39.alert_handler_random_classes.3623505915
Directory /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/39.alert_handler_random_classes/latest

Test location /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default/39.alert_handler_sig_int_fail.714609130
Short name T581
Test name
Test status
Simulation time 636070219 ps
CPU time 18.91 seconds
Started Feb 08 08:44:47 PM UTC 25
Finished Feb 08 08:45:07 PM UTC 25
Peak memory 267236 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo
/hw/dv/tools/sim.tcl +ntb_random_seed=714609130 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default.vdb -cm_l
og /dev/null -cm_name 39.alert_handler_sig_int_fail.714609130
Directory /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/39.alert_handler_sig_int_fail/latest

Test location /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default/39.alert_handler_smoke.4011085181
Short name T577
Test name
Test status
Simulation time 460058760 ps
CPU time 20.6 seconds
Started Feb 08 08:42:59 PM UTC 25
Finished Feb 08 08:43:21 PM UTC 25
Peak memory 269280 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo
/hw/dv/tools/sim.tcl +ntb_random_seed=4011085181 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default.vdb -cm_log /de
v/null -cm_name 39.alert_handler_smoke.4011085181
Directory /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/39.alert_handler_smoke/latest

Test location /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default/4.alert_handler_alert_accum_saturation.2513674841
Short name T55
Test name
Test status
Simulation time 122713449 ps
CPU time 6.59 seconds
Started Feb 08 07:06:32 PM UTC 25
Finished Feb 08 07:06:40 PM UTC 25
Peak memory 263600 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
paces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2513674841 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_al
ert_accum_saturation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/cover
age/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_alert_accum_saturation.2513674841
Directory /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/4.alert_handler_alert_accum_saturation/latest

Test location /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default/4.alert_handler_entropy_stress.3184497169
Short name T20
Test name
Test status
Simulation time 1062520140 ps
CPU time 62.14 seconds
Started Feb 08 07:06:23 PM UTC 25
Finished Feb 08 07:07:27 PM UTC 25
Peak memory 263212 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
paces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3184497169 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_en
tropy_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 4.alert_handler_entropy_stress.3184497169
Directory /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/4.alert_handler_entropy_stress/latest

Test location /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default/4.alert_handler_esc_alert_accum.106726677
Short name T144
Test name
Test status
Simulation time 270105811 ps
CPU time 36.22 seconds
Started Feb 08 07:06:08 PM UTC 25
Finished Feb 08 07:06:46 PM UTC 25
Peak memory 269280 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo
/hw/dv/tools/sim.tcl +ntb_random_seed=106726677 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_acc
um_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default.vdb -c
m_log /dev/null -cm_name 4.alert_handler_esc_alert_accum.106726677
Directory /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/4.alert_handler_esc_alert_accum/latest

Test location /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default/4.alert_handler_esc_intr_timeout.2021157258
Short name T151
Test name
Test status
Simulation time 159089052 ps
CPU time 6.74 seconds
Started Feb 08 07:06:05 PM UTC 25
Finished Feb 08 07:06:13 PM UTC 25
Peak memory 252972 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo
/hw/dv/tools/sim.tcl +ntb_random_seed=2021157258 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_tim
eout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 4.alert_handler_esc_intr_timeout.2021157258
Directory /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/4.alert_handler_esc_intr_timeout/latest

Test location /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default/4.alert_handler_lpg.1533687571
Short name T331
Test name
Test status
Simulation time 33663023465 ps
CPU time 759.79 seconds
Started Feb 08 07:06:18 PM UTC 25
Finished Feb 08 07:19:07 PM UTC 25
Peak memory 285724 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1533687571 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST
_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_lpg.1533687571
Directory /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/4.alert_handler_lpg/latest

Test location /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default/4.alert_handler_lpg_stub_clk.1745318342
Short name T371
Test name
Test status
Simulation time 28326338387 ps
CPU time 2148.31 seconds
Started Feb 08 07:06:22 PM UTC 25
Finished Feb 08 07:42:35 PM UTC 25
Peak memory 301096 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1745318342 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST
_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/alert_handler-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_lpg_stub_clk.1745318342
Directory /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/4.alert_handler_lpg_stub_clk/latest

Test location /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default/4.alert_handler_ping_timeout.3164331953
Short name T131
Test name
Test status
Simulation time 9235408113 ps
CPU time 345.12 seconds
Started Feb 08 07:06:15 PM UTC 25
Finished Feb 08 07:12:04 PM UTC 25
Peak memory 263464 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3164331953 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST
_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/alert_handler-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_ping_timeout.3164331953
Directory /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/4.alert_handler_ping_timeout/latest

Test location /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default/4.alert_handler_random_alerts.2038508069
Short name T85
Test name
Test status
Simulation time 573579737 ps
CPU time 37.11 seconds
Started Feb 08 07:06:03 PM UTC 25
Finished Feb 08 07:06:41 PM UTC 25
Peak memory 268896 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo
/hw/dv/tools/sim.tcl +ntb_random_seed=2038508069 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alert
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default.vdb -cm
_log /dev/null -cm_name 4.alert_handler_random_alerts.2038508069
Directory /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/4.alert_handler_random_alerts/latest

Test location /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default/4.alert_handler_random_classes.1456683511
Short name T56
Test name
Test status
Simulation time 648572291 ps
CPU time 33.89 seconds
Started Feb 08 07:06:05 PM UTC 25
Finished Feb 08 07:06:40 PM UTC 25
Peak memory 263208 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo
/hw/dv/tools/sim.tcl +ntb_random_seed=1456683511 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_class
es_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default.vdb -c
m_log /dev/null -cm_name 4.alert_handler_random_classes.1456683511
Directory /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/4.alert_handler_random_classes/latest

Test location /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default/4.alert_handler_sec_cm.3062798982
Short name T50
Test name
Test status
Simulation time 959944677 ps
CPU time 37.26 seconds
Started Feb 08 07:06:40 PM UTC 25
Finished Feb 08 07:07:19 PM UTC 25
Peak memory 297384 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3062798982 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=a
lert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/covera
ge/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_sec_cm.3062798982
Directory /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/4.alert_handler_sec_cm/latest

Test location /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default/4.alert_handler_sig_int_fail.2783897491
Short name T57
Test name
Test status
Simulation time 541714661 ps
CPU time 38.67 seconds
Started Feb 08 07:06:13 PM UTC 25
Finished Feb 08 07:06:54 PM UTC 25
Peak memory 263468 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo
/hw/dv/tools/sim.tcl +ntb_random_seed=2783897491 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default.vdb -cm_
log /dev/null -cm_name 4.alert_handler_sig_int_fail.2783897491
Directory /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/4.alert_handler_sig_int_fail/latest

Test location /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default/4.alert_handler_smoke.3885365479
Short name T40
Test name
Test status
Simulation time 120855798 ps
CPU time 16.73 seconds
Started Feb 08 07:06:03 PM UTC 25
Finished Feb 08 07:06:21 PM UTC 25
Peak memory 263136 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo
/hw/dv/tools/sim.tcl +ntb_random_seed=3885365479 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default.vdb -cm_log /de
v/null -cm_name 4.alert_handler_smoke.3885365479
Directory /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/4.alert_handler_smoke/latest

Test location /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default/4.alert_handler_stress_all.374380463
Short name T153
Test name
Test status
Simulation time 330279522149 ps
CPU time 1518.85 seconds
Started Feb 08 07:06:27 PM UTC 25
Finished Feb 08 07:32:03 PM UTC 25
Peak memory 312652 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=374380463 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_
regression/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_stress_all.374380463
Directory /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/4.alert_handler_stress_all/latest

Test location /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default/4.alert_handler_stress_all_with_rand_reset.1574196013
Short name T325
Test name
Test status
Simulation time 467684103836 ps
CPU time 8071.53 seconds
Started Feb 08 07:06:35 PM UTC 25
Finished Feb 08 09:22:36 PM UTC 25
Peak memory 370556 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=ale
rt_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=15741
96013 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_stress_all
_with_rand_reset.1574196013
Directory /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/4.alert_handler_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default/40.alert_handler_entropy.574073689
Short name T632
Test name
Test status
Simulation time 32942297754 ps
CPU time 1113.02 seconds
Started Feb 08 08:47:41 PM UTC 25
Finished Feb 08 09:06:28 PM UTC 25
Peak memory 302140 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=574073689 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_
SEQ=alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/
coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_entropy.574073689
Directory /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/40.alert_handler_entropy/latest

Test location /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default/40.alert_handler_esc_alert_accum.3523815680
Short name T594
Test name
Test status
Simulation time 4217493945 ps
CPU time 117.27 seconds
Started Feb 08 08:47:28 PM UTC 25
Finished Feb 08 08:49:28 PM UTC 25
Peak memory 269348 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo
/hw/dv/tools/sim.tcl +ntb_random_seed=3523815680 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_ac
cum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 40.alert_handler_esc_alert_accum.3523815680
Directory /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/40.alert_handler_esc_alert_accum/latest

Test location /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default/40.alert_handler_esc_intr_timeout.2337551344
Short name T589
Test name
Test status
Simulation time 244213154 ps
CPU time 13.63 seconds
Started Feb 08 08:47:20 PM UTC 25
Finished Feb 08 08:47:35 PM UTC 25
Peak memory 269284 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo
/hw/dv/tools/sim.tcl +ntb_random_seed=2337551344 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_tim
eout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 40.alert_handler_esc_intr_timeout.2337551344
Directory /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/40.alert_handler_esc_intr_timeout/latest

Test location /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default/40.alert_handler_lpg_stub_clk.1468981752
Short name T673
Test name
Test status
Simulation time 25631115497 ps
CPU time 1679.46 seconds
Started Feb 08 08:48:02 PM UTC 25
Finished Feb 08 09:16:20 PM UTC 25
Peak memory 285992 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1468981752 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST
_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/alert_handler-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_lpg_stub_clk.1468981752
Directory /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/40.alert_handler_lpg_stub_clk/latest

Test location /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default/40.alert_handler_ping_timeout.4176979638
Short name T595
Test name
Test status
Simulation time 2916232220 ps
CPU time 128.7 seconds
Started Feb 08 08:47:54 PM UTC 25
Finished Feb 08 08:50:05 PM UTC 25
Peak memory 263464 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4176979638 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST
_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/alert_handler-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_ping_timeout.4176979638
Directory /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/40.alert_handler_ping_timeout/latest

Test location /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default/40.alert_handler_random_alerts.1464323613
Short name T590
Test name
Test status
Simulation time 408799043 ps
CPU time 32.19 seconds
Started Feb 08 08:47:07 PM UTC 25
Finished Feb 08 08:47:40 PM UTC 25
Peak memory 263140 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo
/hw/dv/tools/sim.tcl +ntb_random_seed=1464323613 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alert
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default.vdb -cm
_log /dev/null -cm_name 40.alert_handler_random_alerts.1464323613
Directory /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/40.alert_handler_random_alerts/latest

Test location /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default/40.alert_handler_random_classes.2238824837
Short name T588
Test name
Test status
Simulation time 680508051 ps
CPU time 8.23 seconds
Started Feb 08 08:47:18 PM UTC 25
Finished Feb 08 08:47:27 PM UTC 25
Peak memory 263212 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo
/hw/dv/tools/sim.tcl +ntb_random_seed=2238824837 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_class
es_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default.vdb -c
m_log /dev/null -cm_name 40.alert_handler_random_classes.2238824837
Directory /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/40.alert_handler_random_classes/latest

Test location /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default/40.alert_handler_sig_int_fail.2071355480
Short name T328
Test name
Test status
Simulation time 195956124 ps
CPU time 17.58 seconds
Started Feb 08 08:47:35 PM UTC 25
Finished Feb 08 08:47:54 PM UTC 25
Peak memory 263472 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo
/hw/dv/tools/sim.tcl +ntb_random_seed=2071355480 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default.vdb -cm_
log /dev/null -cm_name 40.alert_handler_sig_int_fail.2071355480
Directory /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/40.alert_handler_sig_int_fail/latest

Test location /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default/40.alert_handler_smoke.3551444251
Short name T586
Test name
Test status
Simulation time 605766861 ps
CPU time 21.25 seconds
Started Feb 08 08:46:44 PM UTC 25
Finished Feb 08 08:47:06 PM UTC 25
Peak memory 269544 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo
/hw/dv/tools/sim.tcl +ntb_random_seed=3551444251 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default.vdb -cm_log /de
v/null -cm_name 40.alert_handler_smoke.3551444251
Directory /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/40.alert_handler_smoke/latest

Test location /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default/40.alert_handler_stress_all_with_rand_reset.948817221
Short name T704
Test name
Test status
Simulation time 68759879459 ps
CPU time 3761.83 seconds
Started Feb 08 08:49:13 PM UTC 25
Finished Feb 08 09:52:36 PM UTC 25
Peak memory 337836 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=ale
rt_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=94881
7221 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_stress_all
_with_rand_reset.948817221
Directory /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/40.alert_handler_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default/41.alert_handler_entropy.103260769
Short name T691
Test name
Test status
Simulation time 170931676284 ps
CPU time 2278.3 seconds
Started Feb 08 08:50:47 PM UTC 25
Finished Feb 08 09:29:10 PM UTC 25
Peak memory 300840 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=103260769 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_
SEQ=alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/
coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_entropy.103260769
Directory /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/41.alert_handler_entropy/latest

Test location /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default/41.alert_handler_esc_alert_accum.3886473999
Short name T598
Test name
Test status
Simulation time 964649393 ps
CPU time 29.82 seconds
Started Feb 08 08:50:16 PM UTC 25
Finished Feb 08 08:50:47 PM UTC 25
Peak memory 263144 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo
/hw/dv/tools/sim.tcl +ntb_random_seed=3886473999 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_ac
cum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 41.alert_handler_esc_alert_accum.3886473999
Directory /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/41.alert_handler_esc_alert_accum/latest

Test location /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default/41.alert_handler_esc_intr_timeout.1199290159
Short name T597
Test name
Test status
Simulation time 700268385 ps
CPU time 32.71 seconds
Started Feb 08 08:50:12 PM UTC 25
Finished Feb 08 08:50:46 PM UTC 25
Peak memory 263140 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo
/hw/dv/tools/sim.tcl +ntb_random_seed=1199290159 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_tim
eout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 41.alert_handler_esc_intr_timeout.1199290159
Directory /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/41.alert_handler_esc_intr_timeout/latest

Test location /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default/41.alert_handler_lpg.4200314924
Short name T675
Test name
Test status
Simulation time 22680456279 ps
CPU time 1558.22 seconds
Started Feb 08 08:50:52 PM UTC 25
Finished Feb 08 09:17:08 PM UTC 25
Peak memory 285996 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4200314924 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST
_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_lpg.4200314924
Directory /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/41.alert_handler_lpg/latest

Test location /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default/41.alert_handler_lpg_stub_clk.2634263267
Short name T681
Test name
Test status
Simulation time 49159517565 ps
CPU time 1675.65 seconds
Started Feb 08 08:51:18 PM UTC 25
Finished Feb 08 09:19:32 PM UTC 25
Peak memory 285796 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2634263267 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST
_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/alert_handler-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_lpg_stub_clk.2634263267
Directory /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/41.alert_handler_lpg_stub_clk/latest

Test location /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default/41.alert_handler_ping_timeout.562228437
Short name T622
Test name
Test status
Simulation time 11783506482 ps
CPU time 645.67 seconds
Started Feb 08 08:50:48 PM UTC 25
Finished Feb 08 09:01:42 PM UTC 25
Peak memory 263460 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=562228437 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_
SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/alert_handler-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_ping_timeout.562228437
Directory /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/41.alert_handler_ping_timeout/latest

Test location /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default/41.alert_handler_random_alerts.3886931760
Short name T596
Test name
Test status
Simulation time 833518069 ps
CPU time 41.46 seconds
Started Feb 08 08:49:32 PM UTC 25
Finished Feb 08 08:50:16 PM UTC 25
Peak memory 269356 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo
/hw/dv/tools/sim.tcl +ntb_random_seed=3886931760 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alert
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default.vdb -cm
_log /dev/null -cm_name 41.alert_handler_random_alerts.3886931760
Directory /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/41.alert_handler_random_alerts/latest

Test location /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default/41.alert_handler_random_classes.1088753076
Short name T600
Test name
Test status
Simulation time 7888538275 ps
CPU time 67.86 seconds
Started Feb 08 08:50:07 PM UTC 25
Finished Feb 08 08:51:16 PM UTC 25
Peak memory 269420 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo
/hw/dv/tools/sim.tcl +ntb_random_seed=1088753076 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_class
es_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default.vdb -c
m_log /dev/null -cm_name 41.alert_handler_random_classes.1088753076
Directory /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/41.alert_handler_random_classes/latest

Test location /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default/41.alert_handler_sig_int_fail.2072305407
Short name T291
Test name
Test status
Simulation time 3596896044 ps
CPU time 54.96 seconds
Started Feb 08 08:50:37 PM UTC 25
Finished Feb 08 08:51:34 PM UTC 25
Peak memory 263208 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo
/hw/dv/tools/sim.tcl +ntb_random_seed=2072305407 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default.vdb -cm_
log /dev/null -cm_name 41.alert_handler_sig_int_fail.2072305407
Directory /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/41.alert_handler_sig_int_fail/latest

Test location /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default/41.alert_handler_stress_all.119724449
Short name T604
Test name
Test status
Simulation time 1344820020 ps
CPU time 50.39 seconds
Started Feb 08 08:51:29 PM UTC 25
Finished Feb 08 08:52:21 PM UTC 25
Peak memory 263216 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=119724449 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_
regression/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_stress_all.119724449
Directory /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/41.alert_handler_stress_all/latest

Test location /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default/42.alert_handler_entropy.3538862252
Short name T648
Test name
Test status
Simulation time 8298635988 ps
CPU time 1045.26 seconds
Started Feb 08 08:53:15 PM UTC 25
Finished Feb 08 09:10:53 PM UTC 25
Peak memory 285992 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3538862252 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST
_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_entropy.3538862252
Directory /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/42.alert_handler_entropy/latest

Test location /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default/42.alert_handler_esc_alert_accum.3383303995
Short name T612
Test name
Test status
Simulation time 3353131285 ps
CPU time 279.68 seconds
Started Feb 08 08:52:44 PM UTC 25
Finished Feb 08 08:57:28 PM UTC 25
Peak memory 269352 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo
/hw/dv/tools/sim.tcl +ntb_random_seed=3383303995 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_ac
cum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 42.alert_handler_esc_alert_accum.3383303995
Directory /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/42.alert_handler_esc_alert_accum/latest

Test location /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default/42.alert_handler_esc_intr_timeout.1821580516
Short name T605
Test name
Test status
Simulation time 1227165472 ps
CPU time 25.23 seconds
Started Feb 08 08:52:23 PM UTC 25
Finished Feb 08 08:52:50 PM UTC 25
Peak memory 263408 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo
/hw/dv/tools/sim.tcl +ntb_random_seed=1821580516 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_tim
eout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 42.alert_handler_esc_intr_timeout.1821580516
Directory /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/42.alert_handler_esc_intr_timeout/latest

Test location /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default/42.alert_handler_lpg.209550157
Short name T676
Test name
Test status
Simulation time 42606326828 ps
CPU time 1414.14 seconds
Started Feb 08 08:53:32 PM UTC 25
Finished Feb 08 09:17:22 PM UTC 25
Peak memory 302188 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=209550157 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_
SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/cove
rage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_lpg.209550157
Directory /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/42.alert_handler_lpg/latest

Test location /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default/42.alert_handler_lpg_stub_clk.2670427022
Short name T633
Test name
Test status
Simulation time 14744685219 ps
CPU time 825.82 seconds
Started Feb 08 08:53:42 PM UTC 25
Finished Feb 08 09:07:38 PM UTC 25
Peak memory 285724 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2670427022 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST
_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/alert_handler-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_lpg_stub_clk.2670427022
Directory /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/42.alert_handler_lpg_stub_clk/latest

Test location /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default/42.alert_handler_ping_timeout.1600654766
Short name T613
Test name
Test status
Simulation time 12915488888 ps
CPU time 264.29 seconds
Started Feb 08 08:53:22 PM UTC 25
Finished Feb 08 08:57:50 PM UTC 25
Peak memory 263340 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1600654766 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST
_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/alert_handler-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_ping_timeout.1600654766
Directory /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/42.alert_handler_ping_timeout/latest

Test location /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default/42.alert_handler_random_alerts.4039523446
Short name T606
Test name
Test status
Simulation time 4092949643 ps
CPU time 98.9 seconds
Started Feb 08 08:51:40 PM UTC 25
Finished Feb 08 08:53:22 PM UTC 25
Peak memory 269420 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo
/hw/dv/tools/sim.tcl +ntb_random_seed=4039523446 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alert
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default.vdb -cm
_log /dev/null -cm_name 42.alert_handler_random_alerts.4039523446
Directory /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/42.alert_handler_random_alerts/latest

Test location /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default/42.alert_handler_random_classes.3771652092
Short name T607
Test name
Test status
Simulation time 2789268046 ps
CPU time 67.55 seconds
Started Feb 08 08:52:22 PM UTC 25
Finished Feb 08 08:53:31 PM UTC 25
Peak memory 263204 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo
/hw/dv/tools/sim.tcl +ntb_random_seed=3771652092 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_class
es_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default.vdb -c
m_log /dev/null -cm_name 42.alert_handler_random_classes.3771652092
Directory /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/42.alert_handler_random_classes/latest

Test location /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default/42.alert_handler_sig_int_fail.900509962
Short name T320
Test name
Test status
Simulation time 252109250 ps
CPU time 21.73 seconds
Started Feb 08 08:52:51 PM UTC 25
Finished Feb 08 08:53:14 PM UTC 25
Peak memory 263140 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo
/hw/dv/tools/sim.tcl +ntb_random_seed=900509962 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default.vdb -cm_l
og /dev/null -cm_name 42.alert_handler_sig_int_fail.900509962
Directory /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/42.alert_handler_sig_int_fail/latest

Test location /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default/42.alert_handler_smoke.4150544137
Short name T603
Test name
Test status
Simulation time 53887770 ps
CPU time 4.03 seconds
Started Feb 08 08:51:34 PM UTC 25
Finished Feb 08 08:51:40 PM UTC 25
Peak memory 265512 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo
/hw/dv/tools/sim.tcl +ntb_random_seed=4150544137 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default.vdb -cm_log /de
v/null -cm_name 42.alert_handler_smoke.4150544137
Directory /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/42.alert_handler_smoke/latest

Test location /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default/42.alert_handler_stress_all.428926118
Short name T655
Test name
Test status
Simulation time 27292734934 ps
CPU time 1110.16 seconds
Started Feb 08 08:53:51 PM UTC 25
Finished Feb 08 09:12:35 PM UTC 25
Peak memory 279856 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=428926118 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_
regression/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_stress_all.428926118
Directory /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/42.alert_handler_stress_all/latest

Test location /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default/43.alert_handler_entropy.1356501065
Short name T689
Test name
Test status
Simulation time 49293778335 ps
CPU time 1667.7 seconds
Started Feb 08 08:57:52 PM UTC 25
Finished Feb 08 09:25:58 PM UTC 25
Peak memory 286056 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1356501065 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST
_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_entropy.1356501065
Directory /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/43.alert_handler_entropy/latest

Test location /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default/43.alert_handler_esc_alert_accum.176930383
Short name T618
Test name
Test status
Simulation time 1413360177 ps
CPU time 167.28 seconds
Started Feb 08 08:57:30 PM UTC 25
Finished Feb 08 09:00:20 PM UTC 25
Peak memory 265188 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo
/hw/dv/tools/sim.tcl +ntb_random_seed=176930383 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_acc
um_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default.vdb -c
m_log /dev/null -cm_name 43.alert_handler_esc_alert_accum.176930383
Directory /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/43.alert_handler_esc_alert_accum/latest

Test location /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default/43.alert_handler_esc_intr_timeout.2119376299
Short name T614
Test name
Test status
Simulation time 589459704 ps
CPU time 44.1 seconds
Started Feb 08 08:57:30 PM UTC 25
Finished Feb 08 08:58:16 PM UTC 25
Peak memory 263212 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo
/hw/dv/tools/sim.tcl +ntb_random_seed=2119376299 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_tim
eout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 43.alert_handler_esc_intr_timeout.2119376299
Directory /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/43.alert_handler_esc_intr_timeout/latest

Test location /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default/43.alert_handler_lpg.1872285559
Short name T382
Test name
Test status
Simulation time 34244075337 ps
CPU time 2875.94 seconds
Started Feb 08 08:58:17 PM UTC 25
Finished Feb 08 09:46:47 PM UTC 25
Peak memory 302676 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1872285559 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST
_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_lpg.1872285559
Directory /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/43.alert_handler_lpg/latest

Test location /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default/43.alert_handler_lpg_stub_clk.2667464794
Short name T695
Test name
Test status
Simulation time 32151839051 ps
CPU time 2160.67 seconds
Started Feb 08 08:58:17 PM UTC 25
Finished Feb 08 09:34:43 PM UTC 25
Peak memory 298480 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2667464794 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST
_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/alert_handler-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_lpg_stub_clk.2667464794
Directory /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/43.alert_handler_lpg_stub_clk/latest

Test location /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default/43.alert_handler_ping_timeout.105835979
Short name T626
Test name
Test status
Simulation time 6406531233 ps
CPU time 418.11 seconds
Started Feb 08 08:58:12 PM UTC 25
Finished Feb 08 09:05:16 PM UTC 25
Peak memory 263204 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=105835979 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_
SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/alert_handler-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_ping_timeout.105835979
Directory /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/43.alert_handler_ping_timeout/latest

Test location /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default/43.alert_handler_random_alerts.1861455928
Short name T610
Test name
Test status
Simulation time 480655801 ps
CPU time 36.89 seconds
Started Feb 08 08:56:24 PM UTC 25
Finished Feb 08 08:57:02 PM UTC 25
Peak memory 269284 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo
/hw/dv/tools/sim.tcl +ntb_random_seed=1861455928 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alert
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default.vdb -cm
_log /dev/null -cm_name 43.alert_handler_random_alerts.1861455928
Directory /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/43.alert_handler_random_alerts/latest

Test location /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default/43.alert_handler_random_classes.754712128
Short name T616
Test name
Test status
Simulation time 1246200951 ps
CPU time 114.62 seconds
Started Feb 08 08:57:03 PM UTC 25
Finished Feb 08 08:59:00 PM UTC 25
Peak memory 263140 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo
/hw/dv/tools/sim.tcl +ntb_random_seed=754712128 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classe
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default.vdb -cm
_log /dev/null -cm_name 43.alert_handler_random_classes.754712128
Directory /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/43.alert_handler_random_classes/latest

Test location /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default/43.alert_handler_sig_int_fail.1020708606
Short name T323
Test name
Test status
Simulation time 1742283766 ps
CPU time 34.45 seconds
Started Feb 08 08:57:35 PM UTC 25
Finished Feb 08 08:58:10 PM UTC 25
Peak memory 263144 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo
/hw/dv/tools/sim.tcl +ntb_random_seed=1020708606 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default.vdb -cm_
log /dev/null -cm_name 43.alert_handler_sig_int_fail.1020708606
Directory /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/43.alert_handler_sig_int_fail/latest

Test location /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default/43.alert_handler_smoke.3965761959
Short name T609
Test name
Test status
Simulation time 5226991128 ps
CPU time 48.77 seconds
Started Feb 08 08:55:32 PM UTC 25
Finished Feb 08 08:56:23 PM UTC 25
Peak memory 269608 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo
/hw/dv/tools/sim.tcl +ntb_random_seed=3965761959 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default.vdb -cm_log /de
v/null -cm_name 43.alert_handler_smoke.3965761959
Directory /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/43.alert_handler_smoke/latest

Test location /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default/43.alert_handler_stress_all.2367670721
Short name T327
Test name
Test status
Simulation time 5519575444 ps
CPU time 717.94 seconds
Started Feb 08 08:58:32 PM UTC 25
Finished Feb 08 09:10:40 PM UTC 25
Peak memory 279588 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2367670721 -assert nopostproc +UVM_TESTNAME=ale
rt_handler_base_test +UVM_TEST_SEQ=alert_handler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os
_regression/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_stress_all.2367670721
Directory /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/43.alert_handler_stress_all/latest

Test location /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default/43.alert_handler_stress_all_with_rand_reset.647084234
Short name T221
Test name
Test status
Simulation time 257862779375 ps
CPU time 5470.52 seconds
Started Feb 08 08:59:01 PM UTC 25
Finished Feb 08 10:31:11 PM UTC 25
Peak memory 380844 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=ale
rt_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=64708
4234 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_stress_all
_with_rand_reset.647084234
Directory /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/43.alert_handler_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default/44.alert_handler_entropy.1440769648
Short name T661
Test name
Test status
Simulation time 7385297236 ps
CPU time 730.78 seconds
Started Feb 08 09:01:50 PM UTC 25
Finished Feb 08 09:14:10 PM UTC 25
Peak memory 285796 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1440769648 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST
_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_entropy.1440769648
Directory /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/44.alert_handler_entropy/latest

Test location /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default/44.alert_handler_esc_alert_accum.4177708319
Short name T634
Test name
Test status
Simulation time 5551789235 ps
CPU time 385 seconds
Started Feb 08 09:01:15 PM UTC 25
Finished Feb 08 09:07:46 PM UTC 25
Peak memory 269424 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo
/hw/dv/tools/sim.tcl +ntb_random_seed=4177708319 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_ac
cum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 44.alert_handler_esc_alert_accum.4177708319
Directory /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/44.alert_handler_esc_alert_accum/latest

Test location /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default/44.alert_handler_esc_intr_timeout.2526396423
Short name T624
Test name
Test status
Simulation time 5985395503 ps
CPU time 94.86 seconds
Started Feb 08 09:01:10 PM UTC 25
Finished Feb 08 09:02:47 PM UTC 25
Peak memory 263276 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo
/hw/dv/tools/sim.tcl +ntb_random_seed=2526396423 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_tim
eout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 44.alert_handler_esc_intr_timeout.2526396423
Directory /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/44.alert_handler_esc_intr_timeout/latest

Test location /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default/44.alert_handler_lpg.3372625446
Short name T679
Test name
Test status
Simulation time 10091140571 ps
CPU time 934.97 seconds
Started Feb 08 09:03:06 PM UTC 25
Finished Feb 08 09:18:52 PM UTC 25
Peak memory 285996 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3372625446 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST
_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_lpg.3372625446
Directory /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/44.alert_handler_lpg/latest

Test location /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default/44.alert_handler_lpg_stub_clk.1359605621
Short name T677
Test name
Test status
Simulation time 8803640820 ps
CPU time 840.26 seconds
Started Feb 08 09:03:16 PM UTC 25
Finished Feb 08 09:17:26 PM UTC 25
Peak memory 285724 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1359605621 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST
_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/alert_handler-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_lpg_stub_clk.1359605621
Directory /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/44.alert_handler_lpg_stub_clk/latest

Test location /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default/44.alert_handler_ping_timeout.146132207
Short name T652
Test name
Test status
Simulation time 20404654397 ps
CPU time 513.62 seconds
Started Feb 08 09:02:48 PM UTC 25
Finished Feb 08 09:11:28 PM UTC 25
Peak memory 269348 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=146132207 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_
SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/alert_handler-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_ping_timeout.146132207
Directory /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/44.alert_handler_ping_timeout/latest

Test location /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default/44.alert_handler_random_alerts.4252587223
Short name T619
Test name
Test status
Simulation time 346029812 ps
CPU time 19.17 seconds
Started Feb 08 09:00:22 PM UTC 25
Finished Feb 08 09:00:42 PM UTC 25
Peak memory 263468 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo
/hw/dv/tools/sim.tcl +ntb_random_seed=4252587223 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alert
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default.vdb -cm
_log /dev/null -cm_name 44.alert_handler_random_alerts.4252587223
Directory /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/44.alert_handler_random_alerts/latest

Test location /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default/44.alert_handler_random_classes.2873174621
Short name T621
Test name
Test status
Simulation time 835896193 ps
CPU time 29.87 seconds
Started Feb 08 09:00:43 PM UTC 25
Finished Feb 08 09:01:14 PM UTC 25
Peak memory 263404 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo
/hw/dv/tools/sim.tcl +ntb_random_seed=2873174621 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_class
es_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default.vdb -c
m_log /dev/null -cm_name 44.alert_handler_random_classes.2873174621
Directory /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/44.alert_handler_random_classes/latest

Test location /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default/44.alert_handler_sig_int_fail.2164698240
Short name T623
Test name
Test status
Simulation time 62447420 ps
CPU time 5.03 seconds
Started Feb 08 09:01:43 PM UTC 25
Finished Feb 08 09:01:49 PM UTC 25
Peak memory 252904 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo
/hw/dv/tools/sim.tcl +ntb_random_seed=2164698240 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default.vdb -cm_
log /dev/null -cm_name 44.alert_handler_sig_int_fail.2164698240
Directory /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/44.alert_handler_sig_int_fail/latest

Test location /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default/44.alert_handler_smoke.4272721902
Short name T620
Test name
Test status
Simulation time 562556373 ps
CPU time 51.19 seconds
Started Feb 08 09:00:04 PM UTC 25
Finished Feb 08 09:01:09 PM UTC 25
Peak memory 269280 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo
/hw/dv/tools/sim.tcl +ntb_random_seed=4272721902 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default.vdb -cm_log /de
v/null -cm_name 44.alert_handler_smoke.4272721902
Directory /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/44.alert_handler_smoke/latest

Test location /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default/44.alert_handler_stress_all_with_rand_reset.68474161
Short name T269
Test name
Test status
Simulation time 561224943379 ps
CPU time 3213.84 seconds
Started Feb 08 09:05:01 PM UTC 25
Finished Feb 08 09:59:11 PM UTC 25
Peak memory 315316 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=ale
rt_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=68474
161 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_stress_all_
with_rand_reset.68474161
Directory /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/44.alert_handler_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default/45.alert_handler_entropy.2328050760
Short name T698
Test name
Test status
Simulation time 271679093115 ps
CPU time 2052.09 seconds
Started Feb 08 09:06:03 PM UTC 25
Finished Feb 08 09:40:38 PM UTC 25
Peak memory 298716 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2328050760 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST
_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_entropy.2328050760
Directory /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/45.alert_handler_entropy/latest

Test location /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default/45.alert_handler_esc_alert_accum.3293138759
Short name T315
Test name
Test status
Simulation time 1876627325 ps
CPU time 113.46 seconds
Started Feb 08 09:05:47 PM UTC 25
Finished Feb 08 09:07:42 PM UTC 25
Peak memory 269612 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo
/hw/dv/tools/sim.tcl +ntb_random_seed=3293138759 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_ac
cum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 45.alert_handler_esc_alert_accum.3293138759
Directory /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/45.alert_handler_esc_alert_accum/latest

Test location /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default/45.alert_handler_esc_intr_timeout.671900055
Short name T630
Test name
Test status
Simulation time 742232923 ps
CPU time 16.02 seconds
Started Feb 08 09:05:44 PM UTC 25
Finished Feb 08 09:06:01 PM UTC 25
Peak memory 263140 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo
/hw/dv/tools/sim.tcl +ntb_random_seed=671900055 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_time
out_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 45.alert_handler_esc_intr_timeout.671900055
Directory /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/45.alert_handler_esc_intr_timeout/latest

Test location /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default/45.alert_handler_lpg.3814912803
Short name T686
Test name
Test status
Simulation time 41183352798 ps
CPU time 1056.62 seconds
Started Feb 08 09:06:30 PM UTC 25
Finished Feb 08 09:24:20 PM UTC 25
Peak memory 285804 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3814912803 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST
_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_lpg.3814912803
Directory /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/45.alert_handler_lpg/latest

Test location /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default/45.alert_handler_lpg_stub_clk.2992071178
Short name T692
Test name
Test status
Simulation time 79497481159 ps
CPU time 1352.81 seconds
Started Feb 08 09:07:04 PM UTC 25
Finished Feb 08 09:29:52 PM UTC 25
Peak memory 285864 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2992071178 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST
_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/alert_handler-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_lpg_stub_clk.2992071178
Directory /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/45.alert_handler_lpg_stub_clk/latest

Test location /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default/45.alert_handler_ping_timeout.1856345035
Short name T643
Test name
Test status
Simulation time 10873184054 ps
CPU time 179.5 seconds
Started Feb 08 09:06:21 PM UTC 25
Finished Feb 08 09:09:23 PM UTC 25
Peak memory 263276 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1856345035 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST
_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/alert_handler-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_ping_timeout.1856345035
Directory /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/45.alert_handler_ping_timeout/latest

Test location /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default/45.alert_handler_random_alerts.1813320382
Short name T631
Test name
Test status
Simulation time 413231557 ps
CPU time 44.2 seconds
Started Feb 08 09:05:17 PM UTC 25
Finished Feb 08 09:06:02 PM UTC 25
Peak memory 263404 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo
/hw/dv/tools/sim.tcl +ntb_random_seed=1813320382 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alert
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default.vdb -cm
_log /dev/null -cm_name 45.alert_handler_random_alerts.1813320382
Directory /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/45.alert_handler_random_alerts/latest

Test location /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default/45.alert_handler_random_classes.3856837618
Short name T628
Test name
Test status
Simulation time 345391313 ps
CPU time 14 seconds
Started Feb 08 09:05:28 PM UTC 25
Finished Feb 08 09:05:43 PM UTC 25
Peak memory 263136 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo
/hw/dv/tools/sim.tcl +ntb_random_seed=3856837618 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_class
es_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default.vdb -c
m_log /dev/null -cm_name 45.alert_handler_random_classes.3856837618
Directory /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/45.alert_handler_random_classes/latest

Test location /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default/45.alert_handler_sig_int_fail.2328613867
Short name T299
Test name
Test status
Simulation time 669927741 ps
CPU time 59.38 seconds
Started Feb 08 09:06:02 PM UTC 25
Finished Feb 08 09:07:03 PM UTC 25
Peak memory 269288 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo
/hw/dv/tools/sim.tcl +ntb_random_seed=2328613867 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default.vdb -cm_
log /dev/null -cm_name 45.alert_handler_sig_int_fail.2328613867
Directory /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/45.alert_handler_sig_int_fail/latest

Test location /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default/45.alert_handler_smoke.3762267072
Short name T627
Test name
Test status
Simulation time 156332118 ps
CPU time 9.19 seconds
Started Feb 08 09:05:17 PM UTC 25
Finished Feb 08 09:05:27 PM UTC 25
Peak memory 267300 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo
/hw/dv/tools/sim.tcl +ntb_random_seed=3762267072 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default.vdb -cm_log /de
v/null -cm_name 45.alert_handler_smoke.3762267072
Directory /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/45.alert_handler_smoke/latest

Test location /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default/45.alert_handler_stress_all.3779981799
Short name T693
Test name
Test status
Simulation time 12414743050 ps
CPU time 1356.95 seconds
Started Feb 08 09:07:23 PM UTC 25
Finished Feb 08 09:30:16 PM UTC 25
Peak memory 298352 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3779981799 -assert nopostproc +UVM_TESTNAME=ale
rt_handler_base_test +UVM_TEST_SEQ=alert_handler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os
_regression/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_stress_all.3779981799
Directory /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/45.alert_handler_stress_all/latest

Test location /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default/46.alert_handler_entropy.3110577530
Short name T694
Test name
Test status
Simulation time 28654226846 ps
CPU time 1318.94 seconds
Started Feb 08 09:08:22 PM UTC 25
Finished Feb 08 09:30:36 PM UTC 25
Peak memory 302136 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3110577530 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST
_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_entropy.3110577530
Directory /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/46.alert_handler_entropy/latest

Test location /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default/46.alert_handler_esc_alert_accum.3108444558
Short name T644
Test name
Test status
Simulation time 739901116 ps
CPU time 80.65 seconds
Started Feb 08 09:08:11 PM UTC 25
Finished Feb 08 09:09:34 PM UTC 25
Peak memory 269280 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo
/hw/dv/tools/sim.tcl +ntb_random_seed=3108444558 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_ac
cum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 46.alert_handler_esc_alert_accum.3108444558
Directory /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/46.alert_handler_esc_alert_accum/latest

Test location /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default/46.alert_handler_esc_intr_timeout.1217875999
Short name T636
Test name
Test status
Simulation time 340580253 ps
CPU time 10.37 seconds
Started Feb 08 09:07:58 PM UTC 25
Finished Feb 08 09:08:10 PM UTC 25
Peak memory 263404 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo
/hw/dv/tools/sim.tcl +ntb_random_seed=1217875999 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_tim
eout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 46.alert_handler_esc_intr_timeout.1217875999
Directory /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/46.alert_handler_esc_intr_timeout/latest

Test location /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default/46.alert_handler_lpg.1591741368
Short name T687
Test name
Test status
Simulation time 39342652125 ps
CPU time 954.26 seconds
Started Feb 08 09:08:35 PM UTC 25
Finished Feb 08 09:24:41 PM UTC 25
Peak memory 285996 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1591741368 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST
_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_lpg.1591741368
Directory /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/46.alert_handler_lpg/latest

Test location /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default/46.alert_handler_lpg_stub_clk.2060006761
Short name T708
Test name
Test status
Simulation time 45921117751 ps
CPU time 2786.63 seconds
Started Feb 08 09:08:46 PM UTC 25
Finished Feb 08 09:55:42 PM UTC 25
Peak memory 304860 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2060006761 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST
_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/alert_handler-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_lpg_stub_clk.2060006761
Directory /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/46.alert_handler_lpg_stub_clk/latest

Test location /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default/46.alert_handler_ping_timeout.976384918
Short name T671
Test name
Test status
Simulation time 12244796577 ps
CPU time 432.52 seconds
Started Feb 08 09:08:28 PM UTC 25
Finished Feb 08 09:15:47 PM UTC 25
Peak memory 263204 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=976384918 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_
SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/alert_handler-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_ping_timeout.976384918
Directory /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/46.alert_handler_ping_timeout/latest

Test location /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default/46.alert_handler_random_alerts.382530163
Short name T640
Test name
Test status
Simulation time 3400659952 ps
CPU time 49.2 seconds
Started Feb 08 09:07:43 PM UTC 25
Finished Feb 08 09:08:34 PM UTC 25
Peak memory 269344 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo
/hw/dv/tools/sim.tcl +ntb_random_seed=382530163 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default.vdb -cm_
log /dev/null -cm_name 46.alert_handler_random_alerts.382530163
Directory /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/46.alert_handler_random_alerts/latest

Test location /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default/46.alert_handler_random_classes.1882273242
Short name T639
Test name
Test status
Simulation time 422879058 ps
CPU time 39.47 seconds
Started Feb 08 09:07:47 PM UTC 25
Finished Feb 08 09:08:28 PM UTC 25
Peak memory 263404 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo
/hw/dv/tools/sim.tcl +ntb_random_seed=1882273242 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_class
es_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default.vdb -c
m_log /dev/null -cm_name 46.alert_handler_random_classes.1882273242
Directory /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/46.alert_handler_random_classes/latest

Test location /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default/46.alert_handler_sig_int_fail.3392444455
Short name T641
Test name
Test status
Simulation time 145807852 ps
CPU time 25.35 seconds
Started Feb 08 09:08:18 PM UTC 25
Finished Feb 08 09:08:45 PM UTC 25
Peak memory 263216 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo
/hw/dv/tools/sim.tcl +ntb_random_seed=3392444455 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default.vdb -cm_
log /dev/null -cm_name 46.alert_handler_sig_int_fail.3392444455
Directory /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/46.alert_handler_sig_int_fail/latest

Test location /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default/46.alert_handler_smoke.2946006524
Short name T638
Test name
Test status
Simulation time 496678617 ps
CPU time 39.12 seconds
Started Feb 08 09:07:40 PM UTC 25
Finished Feb 08 09:08:21 PM UTC 25
Peak memory 269352 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo
/hw/dv/tools/sim.tcl +ntb_random_seed=2946006524 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default.vdb -cm_log /de
v/null -cm_name 46.alert_handler_smoke.2946006524
Directory /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/46.alert_handler_smoke/latest

Test location /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default/46.alert_handler_stress_all.2897448491
Short name T653
Test name
Test status
Simulation time 5435703492 ps
CPU time 160.46 seconds
Started Feb 08 09:09:22 PM UTC 25
Finished Feb 08 09:12:05 PM UTC 25
Peak memory 269680 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2897448491 -assert nopostproc +UVM_TESTNAME=ale
rt_handler_base_test +UVM_TEST_SEQ=alert_handler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os
_regression/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_stress_all.2897448491
Directory /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/46.alert_handler_stress_all/latest

Test location /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default/46.alert_handler_stress_all_with_rand_reset.804049865
Short name T706
Test name
Test status
Simulation time 43963230657 ps
CPU time 2630.88 seconds
Started Feb 08 09:09:24 PM UTC 25
Finished Feb 08 09:53:44 PM UTC 25
Peak memory 321644 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=ale
rt_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=80404
9865 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_stress_all
_with_rand_reset.804049865
Directory /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/46.alert_handler_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default/47.alert_handler_entropy.3927118633
Short name T699
Test name
Test status
Simulation time 30171350420 ps
CPU time 1872.56 seconds
Started Feb 08 09:11:01 PM UTC 25
Finished Feb 08 09:42:35 PM UTC 25
Peak memory 288476 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3927118633 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST
_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_entropy.3927118633
Directory /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/47.alert_handler_entropy/latest

Test location /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default/47.alert_handler_esc_alert_accum.376151306
Short name T660
Test name
Test status
Simulation time 8892841648 ps
CPU time 194.66 seconds
Started Feb 08 09:10:41 PM UTC 25
Finished Feb 08 09:13:59 PM UTC 25
Peak memory 269348 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo
/hw/dv/tools/sim.tcl +ntb_random_seed=376151306 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_acc
um_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default.vdb -c
m_log /dev/null -cm_name 47.alert_handler_esc_alert_accum.376151306
Directory /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/47.alert_handler_esc_alert_accum/latest

Test location /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default/47.alert_handler_esc_intr_timeout.1904174385
Short name T651
Test name
Test status
Simulation time 244306356 ps
CPU time 35.71 seconds
Started Feb 08 09:10:38 PM UTC 25
Finished Feb 08 09:11:15 PM UTC 25
Peak memory 269552 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo
/hw/dv/tools/sim.tcl +ntb_random_seed=1904174385 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_tim
eout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 47.alert_handler_esc_intr_timeout.1904174385
Directory /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/47.alert_handler_esc_intr_timeout/latest

Test location /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default/47.alert_handler_lpg.2760097544
Short name T700
Test name
Test status
Simulation time 34198995371 ps
CPU time 1907.47 seconds
Started Feb 08 09:11:14 PM UTC 25
Finished Feb 08 09:43:23 PM UTC 25
Peak memory 287204 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2760097544 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST
_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_lpg.2760097544
Directory /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/47.alert_handler_lpg/latest

Test location /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default/47.alert_handler_ping_timeout.1390651861
Short name T659
Test name
Test status
Simulation time 16935410131 ps
CPU time 159.95 seconds
Started Feb 08 09:11:14 PM UTC 25
Finished Feb 08 09:13:57 PM UTC 25
Peak memory 269344 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1390651861 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST
_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/alert_handler-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_ping_timeout.1390651861
Directory /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/47.alert_handler_ping_timeout/latest

Test location /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default/47.alert_handler_random_alerts.1232261882
Short name T649
Test name
Test status
Simulation time 992422347 ps
CPU time 82.23 seconds
Started Feb 08 09:09:49 PM UTC 25
Finished Feb 08 09:11:13 PM UTC 25
Peak memory 269420 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo
/hw/dv/tools/sim.tcl +ntb_random_seed=1232261882 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alert
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default.vdb -cm
_log /dev/null -cm_name 47.alert_handler_random_alerts.1232261882
Directory /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/47.alert_handler_random_alerts/latest

Test location /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default/47.alert_handler_random_classes.2744413594
Short name T647
Test name
Test status
Simulation time 1597777162 ps
CPU time 20.55 seconds
Started Feb 08 09:10:15 PM UTC 25
Finished Feb 08 09:10:37 PM UTC 25
Peak memory 263404 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo
/hw/dv/tools/sim.tcl +ntb_random_seed=2744413594 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_class
es_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default.vdb -c
m_log /dev/null -cm_name 47.alert_handler_random_classes.2744413594
Directory /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/47.alert_handler_random_classes/latest

Test location /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default/47.alert_handler_sig_int_fail.2705574984
Short name T650
Test name
Test status
Simulation time 444557913 ps
CPU time 16.97 seconds
Started Feb 08 09:10:55 PM UTC 25
Finished Feb 08 09:11:14 PM UTC 25
Peak memory 269288 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo
/hw/dv/tools/sim.tcl +ntb_random_seed=2705574984 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default.vdb -cm_
log /dev/null -cm_name 47.alert_handler_sig_int_fail.2705574984
Directory /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/47.alert_handler_sig_int_fail/latest

Test location /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default/47.alert_handler_smoke.1379879788
Short name T646
Test name
Test status
Simulation time 373106507 ps
CPU time 37.45 seconds
Started Feb 08 09:09:35 PM UTC 25
Finished Feb 08 09:10:14 PM UTC 25
Peak memory 269544 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo
/hw/dv/tools/sim.tcl +ntb_random_seed=1379879788 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default.vdb -cm_log /de
v/null -cm_name 47.alert_handler_smoke.1379879788
Directory /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/47.alert_handler_smoke/latest

Test location /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default/47.alert_handler_stress_all.3773828328
Short name T316
Test name
Test status
Simulation time 52848339664 ps
CPU time 1765.42 seconds
Started Feb 08 09:11:29 PM UTC 25
Finished Feb 08 09:41:15 PM UTC 25
Peak memory 302192 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3773828328 -assert nopostproc +UVM_TESTNAME=ale
rt_handler_base_test +UVM_TEST_SEQ=alert_handler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os
_regression/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_stress_all.3773828328
Directory /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/47.alert_handler_stress_all/latest

Test location /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default/47.alert_handler_stress_all_with_rand_reset.2751011878
Short name T268
Test name
Test status
Simulation time 23432215691 ps
CPU time 1529.16 seconds
Started Feb 08 09:12:06 PM UTC 25
Finished Feb 08 09:37:52 PM UTC 25
Peak memory 298412 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=ale
rt_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=27510
11878 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_stress_al
l_with_rand_reset.2751011878
Directory /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/47.alert_handler_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default/48.alert_handler_entropy.1518773235
Short name T702
Test name
Test status
Simulation time 148453690434 ps
CPU time 2049.14 seconds
Started Feb 08 09:13:45 PM UTC 25
Finished Feb 08 09:48:16 PM UTC 25
Peak memory 288476 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1518773235 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST
_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_entropy.1518773235
Directory /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/48.alert_handler_entropy/latest

Test location /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default/48.alert_handler_esc_alert_accum.3600358537
Short name T664
Test name
Test status
Simulation time 1275636222 ps
CPU time 120.23 seconds
Started Feb 08 09:13:05 PM UTC 25
Finished Feb 08 09:15:07 PM UTC 25
Peak memory 269552 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo
/hw/dv/tools/sim.tcl +ntb_random_seed=3600358537 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_ac
cum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 48.alert_handler_esc_alert_accum.3600358537
Directory /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/48.alert_handler_esc_alert_accum/latest

Test location /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default/48.alert_handler_esc_intr_timeout.3656620470
Short name T663
Test name
Test status
Simulation time 3901343499 ps
CPU time 104.61 seconds
Started Feb 08 09:12:56 PM UTC 25
Finished Feb 08 09:14:43 PM UTC 25
Peak memory 269348 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo
/hw/dv/tools/sim.tcl +ntb_random_seed=3656620470 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_tim
eout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 48.alert_handler_esc_intr_timeout.3656620470
Directory /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/48.alert_handler_esc_intr_timeout/latest

Test location /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default/48.alert_handler_lpg.3898473286
Short name T381
Test name
Test status
Simulation time 14816734899 ps
CPU time 1373.97 seconds
Started Feb 08 09:13:57 PM UTC 25
Finished Feb 08 09:37:07 PM UTC 25
Peak memory 302108 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3898473286 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST
_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_lpg.3898473286
Directory /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/48.alert_handler_lpg/latest

Test location /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default/48.alert_handler_lpg_stub_clk.3186352262
Short name T709
Test name
Test status
Simulation time 247572331753 ps
CPU time 2806.59 seconds
Started Feb 08 09:14:00 PM UTC 25
Finished Feb 08 10:01:17 PM UTC 25
Peak memory 304860 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3186352262 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST
_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/alert_handler-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_lpg_stub_clk.3186352262
Directory /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/48.alert_handler_lpg_stub_clk/latest

Test location /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default/48.alert_handler_ping_timeout.3161204093
Short name T682
Test name
Test status
Simulation time 8202006650 ps
CPU time 353.41 seconds
Started Feb 08 09:13:51 PM UTC 25
Finished Feb 08 09:19:49 PM UTC 25
Peak memory 263460 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3161204093 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST
_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/alert_handler-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_ping_timeout.3161204093
Directory /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/48.alert_handler_ping_timeout/latest

Test location /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default/48.alert_handler_random_alerts.1346360797
Short name T656
Test name
Test status
Simulation time 94552419 ps
CPU time 16.84 seconds
Started Feb 08 09:12:36 PM UTC 25
Finished Feb 08 09:12:54 PM UTC 25
Peak memory 269548 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo
/hw/dv/tools/sim.tcl +ntb_random_seed=1346360797 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alert
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default.vdb -cm
_log /dev/null -cm_name 48.alert_handler_random_alerts.1346360797
Directory /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/48.alert_handler_random_alerts/latest

Test location /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default/48.alert_handler_random_classes.1184869715
Short name T658
Test name
Test status
Simulation time 1631932647 ps
CPU time 47.02 seconds
Started Feb 08 09:12:55 PM UTC 25
Finished Feb 08 09:13:44 PM UTC 25
Peak memory 269280 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo
/hw/dv/tools/sim.tcl +ntb_random_seed=1184869715 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_class
es_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default.vdb -c
m_log /dev/null -cm_name 48.alert_handler_random_classes.1184869715
Directory /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/48.alert_handler_random_classes/latest

Test location /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default/48.alert_handler_sig_int_fail.165901243
Short name T329
Test name
Test status
Simulation time 366034308 ps
CPU time 31.94 seconds
Started Feb 08 09:13:17 PM UTC 25
Finished Feb 08 09:13:50 PM UTC 25
Peak memory 263140 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo
/hw/dv/tools/sim.tcl +ntb_random_seed=165901243 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default.vdb -cm_l
og /dev/null -cm_name 48.alert_handler_sig_int_fail.165901243
Directory /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/48.alert_handler_sig_int_fail/latest

Test location /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default/48.alert_handler_smoke.2748140
Short name T657
Test name
Test status
Simulation time 462379497 ps
CPU time 22.15 seconds
Started Feb 08 09:12:32 PM UTC 25
Finished Feb 08 09:12:55 PM UTC 25
Peak memory 269548 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo
/hw/dv/tools/sim.tcl +ntb_random_seed=2748140 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/n
ull -cm_name 48.alert_handler_smoke.2748140
Directory /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/48.alert_handler_smoke/latest

Test location /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default/48.alert_handler_stress_all.2009343306
Short name T707
Test name
Test status
Simulation time 36149248754 ps
CPU time 2390.01 seconds
Started Feb 08 09:14:12 PM UTC 25
Finished Feb 08 09:54:29 PM UTC 25
Peak memory 300848 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2009343306 -assert nopostproc +UVM_TESTNAME=ale
rt_handler_base_test +UVM_TEST_SEQ=alert_handler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os
_regression/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_stress_all.2009343306
Directory /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/48.alert_handler_stress_all/latest

Test location /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default/48.alert_handler_stress_all_with_rand_reset.3886836634
Short name T224
Test name
Test status
Simulation time 92731567605 ps
CPU time 6472.43 seconds
Started Feb 08 09:14:20 PM UTC 25
Finished Feb 08 11:03:26 PM UTC 25
Peak memory 386916 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=ale
rt_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=38868
36634 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_stress_al
l_with_rand_reset.3886836634
Directory /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/48.alert_handler_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default/49.alert_handler_entropy.3118722598
Short name T711
Test name
Test status
Simulation time 195790879232 ps
CPU time 3197.94 seconds
Started Feb 08 09:15:27 PM UTC 25
Finished Feb 08 10:09:21 PM UTC 25
Peak memory 304696 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3118722598 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST
_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_entropy.3118722598
Directory /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/49.alert_handler_entropy/latest

Test location /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default/49.alert_handler_esc_alert_accum.4022703122
Short name T680
Test name
Test status
Simulation time 9178923623 ps
CPU time 237.47 seconds
Started Feb 08 09:15:20 PM UTC 25
Finished Feb 08 09:19:21 PM UTC 25
Peak memory 269348 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo
/hw/dv/tools/sim.tcl +ntb_random_seed=4022703122 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_ac
cum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 49.alert_handler_esc_alert_accum.4022703122
Directory /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/49.alert_handler_esc_alert_accum/latest

Test location /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default/49.alert_handler_esc_intr_timeout.2003101696
Short name T669
Test name
Test status
Simulation time 371222773 ps
CPU time 12.53 seconds
Started Feb 08 09:15:13 PM UTC 25
Finished Feb 08 09:15:26 PM UTC 25
Peak memory 269284 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo
/hw/dv/tools/sim.tcl +ntb_random_seed=2003101696 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_tim
eout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 49.alert_handler_esc_intr_timeout.2003101696
Directory /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/49.alert_handler_esc_intr_timeout/latest

Test location /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default/49.alert_handler_lpg.1326477705
Short name T703
Test name
Test status
Simulation time 108237940959 ps
CPU time 1999.21 seconds
Started Feb 08 09:15:50 PM UTC 25
Finished Feb 08 09:49:32 PM UTC 25
Peak memory 302112 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1326477705 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST
_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_lpg.1326477705
Directory /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/49.alert_handler_lpg/latest

Test location /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default/49.alert_handler_lpg_stub_clk.3752530284
Short name T710
Test name
Test status
Simulation time 36106863760 ps
CPU time 3172.39 seconds
Started Feb 08 09:15:50 PM UTC 25
Finished Feb 08 10:09:19 PM UTC 25
Peak memory 304964 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3752530284 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST
_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/alert_handler-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_lpg_stub_clk.3752530284
Directory /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/49.alert_handler_lpg_stub_clk/latest

Test location /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default/49.alert_handler_ping_timeout.1411437065
Short name T690
Test name
Test status
Simulation time 25791724674 ps
CPU time 740.59 seconds
Started Feb 08 09:15:50 PM UTC 25
Finished Feb 08 09:28:20 PM UTC 25
Peak memory 263468 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1411437065 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST
_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/alert_handler-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_ping_timeout.1411437065
Directory /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/49.alert_handler_ping_timeout/latest

Test location /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default/49.alert_handler_random_alerts.1721488479
Short name T668
Test name
Test status
Simulation time 425177916 ps
CPU time 16.57 seconds
Started Feb 08 09:15:08 PM UTC 25
Finished Feb 08 09:15:26 PM UTC 25
Peak memory 263140 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo
/hw/dv/tools/sim.tcl +ntb_random_seed=1721488479 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alert
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default.vdb -cm
_log /dev/null -cm_name 49.alert_handler_random_alerts.1721488479
Directory /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/49.alert_handler_random_alerts/latest

Test location /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default/49.alert_handler_random_classes.2061930302
Short name T667
Test name
Test status
Simulation time 98662712 ps
CPU time 7.1 seconds
Started Feb 08 09:15:10 PM UTC 25
Finished Feb 08 09:15:19 PM UTC 25
Peak memory 263136 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo
/hw/dv/tools/sim.tcl +ntb_random_seed=2061930302 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_class
es_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default.vdb -c
m_log /dev/null -cm_name 49.alert_handler_random_classes.2061930302
Directory /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/49.alert_handler_random_classes/latest

Test location /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default/49.alert_handler_sig_int_fail.2321070666
Short name T672
Test name
Test status
Simulation time 467525186 ps
CPU time 20.58 seconds
Started Feb 08 09:15:27 PM UTC 25
Finished Feb 08 09:15:49 PM UTC 25
Peak memory 269012 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo
/hw/dv/tools/sim.tcl +ntb_random_seed=2321070666 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default.vdb -cm_
log /dev/null -cm_name 49.alert_handler_sig_int_fail.2321070666
Directory /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/49.alert_handler_sig_int_fail/latest

Test location /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default/49.alert_handler_smoke.438132134
Short name T666
Test name
Test status
Simulation time 480131425 ps
CPU time 26.67 seconds
Started Feb 08 09:14:44 PM UTC 25
Finished Feb 08 09:15:12 PM UTC 25
Peak memory 269352 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo
/hw/dv/tools/sim.tcl +ntb_random_seed=438132134 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev
/null -cm_name 49.alert_handler_smoke.438132134
Directory /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/49.alert_handler_smoke/latest

Test location /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default/49.alert_handler_stress_all.1684043446
Short name T678
Test name
Test status
Simulation time 14009376673 ps
CPU time 142.38 seconds
Started Feb 08 09:16:22 PM UTC 25
Finished Feb 08 09:18:47 PM UTC 25
Peak memory 269352 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1684043446 -assert nopostproc +UVM_TESTNAME=ale
rt_handler_base_test +UVM_TEST_SEQ=alert_handler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os
_regression/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_stress_all.1684043446
Directory /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/49.alert_handler_stress_all/latest

Test location /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default/5.alert_handler_alert_accum_saturation.3445712975
Short name T251
Test name
Test status
Simulation time 34087262 ps
CPU time 5.07 seconds
Started Feb 08 07:07:25 PM UTC 25
Finished Feb 08 07:07:31 PM UTC 25
Peak memory 263408 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
paces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3445712975 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_al
ert_accum_saturation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/cover
age/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_alert_accum_saturation.3445712975
Directory /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/5.alert_handler_alert_accum_saturation/latest

Test location /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default/5.alert_handler_entropy_stress.1809928790
Short name T21
Test name
Test status
Simulation time 325504798 ps
CPU time 14.85 seconds
Started Feb 08 07:07:20 PM UTC 25
Finished Feb 08 07:07:37 PM UTC 25
Peak memory 263404 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
paces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1809928790 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_en
tropy_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 5.alert_handler_entropy_stress.1809928790
Directory /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/5.alert_handler_entropy_stress/latest

Test location /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default/5.alert_handler_esc_alert_accum.3144612797
Short name T249
Test name
Test status
Simulation time 448412498 ps
CPU time 35.28 seconds
Started Feb 08 07:06:48 PM UTC 25
Finished Feb 08 07:07:25 PM UTC 25
Peak memory 269548 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo
/hw/dv/tools/sim.tcl +ntb_random_seed=3144612797 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_ac
cum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 5.alert_handler_esc_alert_accum.3144612797
Directory /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/5.alert_handler_esc_alert_accum/latest

Test location /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default/5.alert_handler_lpg.2511769572
Short name T305
Test name
Test status
Simulation time 7649090719 ps
CPU time 695.72 seconds
Started Feb 08 07:07:14 PM UTC 25
Finished Feb 08 07:18:59 PM UTC 25
Peak memory 285724 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2511769572 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST
_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_lpg.2511769572
Directory /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/5.alert_handler_lpg/latest

Test location /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default/5.alert_handler_lpg_stub_clk.2623949966
Short name T374
Test name
Test status
Simulation time 13820717597 ps
CPU time 1424.02 seconds
Started Feb 08 07:07:19 PM UTC 25
Finished Feb 08 07:31:20 PM UTC 25
Peak memory 300136 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2623949966 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST
_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/alert_handler-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_lpg_stub_clk.2623949966
Directory /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/5.alert_handler_lpg_stub_clk/latest

Test location /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default/5.alert_handler_random_alerts.2808757798
Short name T45
Test name
Test status
Simulation time 284206899 ps
CPU time 37.28 seconds
Started Feb 08 07:06:41 PM UTC 25
Finished Feb 08 07:07:20 PM UTC 25
Peak memory 263436 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo
/hw/dv/tools/sim.tcl +ntb_random_seed=2808757798 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alert
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default.vdb -cm
_log /dev/null -cm_name 5.alert_handler_random_alerts.2808757798
Directory /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/5.alert_handler_random_alerts/latest

Test location /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default/5.alert_handler_random_classes.106311590
Short name T92
Test name
Test status
Simulation time 336668977 ps
CPU time 39.59 seconds
Started Feb 08 07:06:42 PM UTC 25
Finished Feb 08 07:07:23 PM UTC 25
Peak memory 269280 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo
/hw/dv/tools/sim.tcl +ntb_random_seed=106311590 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classe
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default.vdb -cm
_log /dev/null -cm_name 5.alert_handler_random_classes.106311590
Directory /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/5.alert_handler_random_classes/latest

Test location /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default/5.alert_handler_sig_int_fail.2610035007
Short name T88
Test name
Test status
Simulation time 3709101939 ps
CPU time 74.4 seconds
Started Feb 08 07:06:55 PM UTC 25
Finished Feb 08 07:08:11 PM UTC 25
Peak memory 263276 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo
/hw/dv/tools/sim.tcl +ntb_random_seed=2610035007 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default.vdb -cm_
log /dev/null -cm_name 5.alert_handler_sig_int_fail.2610035007
Directory /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/5.alert_handler_sig_int_fail/latest

Test location /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default/5.alert_handler_smoke.1003685243
Short name T405
Test name
Test status
Simulation time 1159630314 ps
CPU time 66.24 seconds
Started Feb 08 07:06:41 PM UTC 25
Finished Feb 08 07:07:49 PM UTC 25
Peak memory 269240 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo
/hw/dv/tools/sim.tcl +ntb_random_seed=1003685243 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default.vdb -cm_log /de
v/null -cm_name 5.alert_handler_smoke.1003685243
Directory /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/5.alert_handler_smoke/latest

Test location /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default/5.alert_handler_stress_all.357685554
Short name T310
Test name
Test status
Simulation time 49407877166 ps
CPU time 3563.85 seconds
Started Feb 08 07:07:22 PM UTC 25
Finished Feb 08 08:07:27 PM UTC 25
Peak memory 304944 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=357685554 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_
regression/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_stress_all.357685554
Directory /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/5.alert_handler_stress_all/latest

Test location /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default/5.alert_handler_stress_all_with_rand_reset.1474483419
Short name T71
Test name
Test status
Simulation time 296822547708 ps
CPU time 4605.07 seconds
Started Feb 08 07:07:25 PM UTC 25
Finished Feb 08 08:25:00 PM UTC 25
Peak memory 337764 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=ale
rt_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=14744
83419 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_stress_all
_with_rand_reset.1474483419
Directory /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/5.alert_handler_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default/6.alert_handler_alert_accum_saturation.718736081
Short name T148
Test name
Test status
Simulation time 72858144 ps
CPU time 4.37 seconds
Started Feb 08 07:08:06 PM UTC 25
Finished Feb 08 07:08:12 PM UTC 25
Peak memory 263360 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
paces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=718736081 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ale
rt_accum_saturation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/covera
ge/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_alert_accum_saturation.718736081
Directory /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/6.alert_handler_alert_accum_saturation/latest

Test location /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default/6.alert_handler_entropy_stress.3794624379
Short name T22
Test name
Test status
Simulation time 201079895 ps
CPU time 17.55 seconds
Started Feb 08 07:07:47 PM UTC 25
Finished Feb 08 07:08:06 PM UTC 25
Peak memory 263140 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
paces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3794624379 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_en
tropy_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 6.alert_handler_entropy_stress.3794624379
Directory /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/6.alert_handler_entropy_stress/latest

Test location /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default/6.alert_handler_esc_intr_timeout.3191178337
Short name T94
Test name
Test status
Simulation time 1399657550 ps
CPU time 32.72 seconds
Started Feb 08 07:07:32 PM UTC 25
Finished Feb 08 07:08:06 PM UTC 25
Peak memory 269356 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo
/hw/dv/tools/sim.tcl +ntb_random_seed=3191178337 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_tim
eout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 6.alert_handler_esc_intr_timeout.3191178337
Directory /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/6.alert_handler_esc_intr_timeout/latest

Test location /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default/6.alert_handler_lpg.2938780243
Short name T217
Test name
Test status
Simulation time 11225472905 ps
CPU time 1220.11 seconds
Started Feb 08 07:07:45 PM UTC 25
Finished Feb 08 07:28:20 PM UTC 25
Peak memory 285992 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2938780243 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST
_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_lpg.2938780243
Directory /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/6.alert_handler_lpg/latest

Test location /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default/6.alert_handler_lpg_stub_clk.1770640934
Short name T369
Test name
Test status
Simulation time 31944494064 ps
CPU time 800.54 seconds
Started Feb 08 07:07:46 PM UTC 25
Finished Feb 08 07:21:16 PM UTC 25
Peak memory 285728 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1770640934 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST
_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/alert_handler-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_lpg_stub_clk.1770640934
Directory /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/6.alert_handler_lpg_stub_clk/latest

Test location /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default/6.alert_handler_random_alerts.1142918203
Short name T404
Test name
Test status
Simulation time 129005499 ps
CPU time 14.2 seconds
Started Feb 08 07:07:28 PM UTC 25
Finished Feb 08 07:07:43 PM UTC 25
Peak memory 269612 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo
/hw/dv/tools/sim.tcl +ntb_random_seed=1142918203 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alert
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default.vdb -cm
_log /dev/null -cm_name 6.alert_handler_random_alerts.1142918203
Directory /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/6.alert_handler_random_alerts/latest

Test location /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default/6.alert_handler_random_classes.259960480
Short name T248
Test name
Test status
Simulation time 458376920 ps
CPU time 32.9 seconds
Started Feb 08 07:07:32 PM UTC 25
Finished Feb 08 07:08:06 PM UTC 25
Peak memory 269544 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo
/hw/dv/tools/sim.tcl +ntb_random_seed=259960480 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classe
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default.vdb -cm
_log /dev/null -cm_name 6.alert_handler_random_classes.259960480
Directory /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/6.alert_handler_random_classes/latest

Test location /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default/6.alert_handler_sig_int_fail.1188787043
Short name T89
Test name
Test status
Simulation time 1164477288 ps
CPU time 35.01 seconds
Started Feb 08 07:07:34 PM UTC 25
Finished Feb 08 07:08:11 PM UTC 25
Peak memory 263140 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo
/hw/dv/tools/sim.tcl +ntb_random_seed=1188787043 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default.vdb -cm_
log /dev/null -cm_name 6.alert_handler_sig_int_fail.1188787043
Directory /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/6.alert_handler_sig_int_fail/latest

Test location /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default/6.alert_handler_smoke.3525253102
Short name T87
Test name
Test status
Simulation time 320538975 ps
CPU time 18.22 seconds
Started Feb 08 07:07:26 PM UTC 25
Finished Feb 08 07:07:45 PM UTC 25
Peak memory 263136 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo
/hw/dv/tools/sim.tcl +ntb_random_seed=3525253102 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default.vdb -cm_log /de
v/null -cm_name 6.alert_handler_smoke.3525253102
Directory /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/6.alert_handler_smoke/latest

Test location /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default/6.alert_handler_stress_all_with_rand_reset.2990985461
Short name T214
Test name
Test status
Simulation time 92384569306 ps
CPU time 5185.3 seconds
Started Feb 08 07:08:07 PM UTC 25
Finished Feb 08 08:35:31 PM UTC 25
Peak memory 338024 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=ale
rt_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=29909
85461 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_stress_all
_with_rand_reset.2990985461
Directory /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/6.alert_handler_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default/7.alert_handler_alert_accum_saturation.2430677792
Short name T252
Test name
Test status
Simulation time 37110088 ps
CPU time 3.35 seconds
Started Feb 08 07:09:00 PM UTC 25
Finished Feb 08 07:09:05 PM UTC 25
Peak memory 263408 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
paces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2430677792 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_al
ert_accum_saturation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/cover
age/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_alert_accum_saturation.2430677792
Directory /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/7.alert_handler_alert_accum_saturation/latest

Test location /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default/7.alert_handler_entropy_stress.173962189
Short name T23
Test name
Test status
Simulation time 1350579001 ps
CPU time 22.72 seconds
Started Feb 08 07:08:49 PM UTC 25
Finished Feb 08 07:09:13 PM UTC 25
Peak memory 263468 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
paces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=173962189 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ent
ropy_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 7.alert_handler_entropy_stress.173962189
Directory /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/7.alert_handler_entropy_stress/latest

Test location /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default/7.alert_handler_esc_alert_accum.205048016
Short name T150
Test name
Test status
Simulation time 458295381 ps
CPU time 47.35 seconds
Started Feb 08 07:08:13 PM UTC 25
Finished Feb 08 07:09:02 PM UTC 25
Peak memory 269288 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo
/hw/dv/tools/sim.tcl +ntb_random_seed=205048016 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_acc
um_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default.vdb -c
m_log /dev/null -cm_name 7.alert_handler_esc_alert_accum.205048016
Directory /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/7.alert_handler_esc_alert_accum/latest

Test location /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default/7.alert_handler_esc_intr_timeout.542095746
Short name T95
Test name
Test status
Simulation time 99161289 ps
CPU time 10.83 seconds
Started Feb 08 07:08:13 PM UTC 25
Finished Feb 08 07:08:25 PM UTC 25
Peak memory 263216 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo
/hw/dv/tools/sim.tcl +ntb_random_seed=542095746 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_time
out_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 7.alert_handler_esc_intr_timeout.542095746
Directory /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/7.alert_handler_esc_intr_timeout/latest

Test location /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default/7.alert_handler_lpg_stub_clk.1916857995
Short name T434
Test name
Test status
Simulation time 15657101443 ps
CPU time 1409.82 seconds
Started Feb 08 07:08:45 PM UTC 25
Finished Feb 08 07:32:31 PM UTC 25
Peak memory 302140 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1916857995 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST
_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/alert_handler-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_lpg_stub_clk.1916857995
Directory /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/7.alert_handler_lpg_stub_clk/latest

Test location /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default/7.alert_handler_random_alerts.2509412167
Short name T58
Test name
Test status
Simulation time 520945504 ps
CPU time 63.98 seconds
Started Feb 08 07:08:07 PM UTC 25
Finished Feb 08 07:09:13 PM UTC 25
Peak memory 263404 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo
/hw/dv/tools/sim.tcl +ntb_random_seed=2509412167 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alert
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default.vdb -cm
_log /dev/null -cm_name 7.alert_handler_random_alerts.2509412167
Directory /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/7.alert_handler_random_alerts/latest

Test location /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default/7.alert_handler_random_classes.1462344007
Short name T90
Test name
Test status
Simulation time 543356991 ps
CPU time 39.45 seconds
Started Feb 08 07:08:11 PM UTC 25
Finished Feb 08 07:08:52 PM UTC 25
Peak memory 263400 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo
/hw/dv/tools/sim.tcl +ntb_random_seed=1462344007 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_class
es_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default.vdb -c
m_log /dev/null -cm_name 7.alert_handler_random_classes.1462344007
Directory /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/7.alert_handler_random_classes/latest

Test location /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default/7.alert_handler_sig_int_fail.3010077320
Short name T149
Test name
Test status
Simulation time 172045327 ps
CPU time 29.8 seconds
Started Feb 08 07:08:13 PM UTC 25
Finished Feb 08 07:08:44 PM UTC 25
Peak memory 263212 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo
/hw/dv/tools/sim.tcl +ntb_random_seed=3010077320 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default.vdb -cm_
log /dev/null -cm_name 7.alert_handler_sig_int_fail.3010077320
Directory /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/7.alert_handler_sig_int_fail/latest

Test location /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default/7.alert_handler_smoke.1233197031
Short name T41
Test name
Test status
Simulation time 335789256 ps
CPU time 11.88 seconds
Started Feb 08 07:08:07 PM UTC 25
Finished Feb 08 07:08:20 PM UTC 25
Peak memory 265104 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo
/hw/dv/tools/sim.tcl +ntb_random_seed=1233197031 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default.vdb -cm_log /de
v/null -cm_name 7.alert_handler_smoke.1233197031
Directory /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/7.alert_handler_smoke/latest

Test location /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default/7.alert_handler_stress_all.469642095
Short name T126
Test name
Test status
Simulation time 60032541963 ps
CPU time 3894.4 seconds
Started Feb 08 07:08:53 PM UTC 25
Finished Feb 08 08:14:32 PM UTC 25
Peak memory 304944 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=469642095 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_
regression/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_stress_all.469642095
Directory /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/7.alert_handler_stress_all/latest

Test location /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default/8.alert_handler_alert_accum_saturation.2516923370
Short name T253
Test name
Test status
Simulation time 35713487 ps
CPU time 5.25 seconds
Started Feb 08 07:10:23 PM UTC 25
Finished Feb 08 07:10:30 PM UTC 25
Peak memory 263600 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
paces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2516923370 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_al
ert_accum_saturation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/cover
age/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_alert_accum_saturation.2516923370
Directory /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/8.alert_handler_alert_accum_saturation/latest

Test location /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default/8.alert_handler_entropy.4274221543
Short name T123
Test name
Test status
Simulation time 157736254182 ps
CPU time 2416.44 seconds
Started Feb 08 07:09:24 PM UTC 25
Finished Feb 08 07:50:07 PM UTC 25
Peak memory 296232 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4274221543 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST
_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_entropy.4274221543
Directory /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/8.alert_handler_entropy/latest

Test location /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default/8.alert_handler_entropy_stress.3427072465
Short name T154
Test name
Test status
Simulation time 1913485019 ps
CPU time 31.03 seconds
Started Feb 08 07:10:12 PM UTC 25
Finished Feb 08 07:10:44 PM UTC 25
Peak memory 263404 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
paces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3427072465 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_en
tropy_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 8.alert_handler_entropy_stress.3427072465
Directory /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/8.alert_handler_entropy_stress/latest

Test location /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default/8.alert_handler_esc_alert_accum.3178744807
Short name T132
Test name
Test status
Simulation time 1916822512 ps
CPU time 175.24 seconds
Started Feb 08 07:09:14 PM UTC 25
Finished Feb 08 07:12:12 PM UTC 25
Peak memory 269356 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo
/hw/dv/tools/sim.tcl +ntb_random_seed=3178744807 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_ac
cum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 8.alert_handler_esc_alert_accum.3178744807
Directory /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/8.alert_handler_esc_alert_accum/latest

Test location /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default/8.alert_handler_esc_intr_timeout.2350580200
Short name T96
Test name
Test status
Simulation time 367338521 ps
CPU time 14.44 seconds
Started Feb 08 07:09:14 PM UTC 25
Finished Feb 08 07:09:29 PM UTC 25
Peak memory 263340 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo
/hw/dv/tools/sim.tcl +ntb_random_seed=2350580200 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_tim
eout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 8.alert_handler_esc_intr_timeout.2350580200
Directory /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/8.alert_handler_esc_intr_timeout/latest

Test location /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default/8.alert_handler_lpg_stub_clk.4099294709
Short name T464
Test name
Test status
Simulation time 141221324132 ps
CPU time 2643.53 seconds
Started Feb 08 07:09:49 PM UTC 25
Finished Feb 08 07:54:22 PM UTC 25
Peak memory 287532 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4099294709 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST
_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/alert_handler-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_lpg_stub_clk.4099294709
Directory /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/8.alert_handler_lpg_stub_clk/latest

Test location /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default/8.alert_handler_ping_timeout.230174025
Short name T343
Test name
Test status
Simulation time 14419117861 ps
CPU time 346.74 seconds
Started Feb 08 07:09:30 PM UTC 25
Finished Feb 08 07:15:22 PM UTC 25
Peak memory 263200 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=230174025 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_
SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/alert_handler-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_ping_timeout.230174025
Directory /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/8.alert_handler_ping_timeout/latest

Test location /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default/8.alert_handler_random_alerts.2632958169
Short name T406
Test name
Test status
Simulation time 420250181 ps
CPU time 16.88 seconds
Started Feb 08 07:09:05 PM UTC 25
Finished Feb 08 07:09:24 PM UTC 25
Peak memory 263400 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo
/hw/dv/tools/sim.tcl +ntb_random_seed=2632958169 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alert
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default.vdb -cm
_log /dev/null -cm_name 8.alert_handler_random_alerts.2632958169
Directory /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/8.alert_handler_random_alerts/latest

Test location /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default/8.alert_handler_random_classes.3003715223
Short name T91
Test name
Test status
Simulation time 308128926 ps
CPU time 36.74 seconds
Started Feb 08 07:09:09 PM UTC 25
Finished Feb 08 07:09:48 PM UTC 25
Peak memory 263136 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo
/hw/dv/tools/sim.tcl +ntb_random_seed=3003715223 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_class
es_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default.vdb -c
m_log /dev/null -cm_name 8.alert_handler_random_classes.3003715223
Directory /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/8.alert_handler_random_classes/latest

Test location /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default/8.alert_handler_sig_int_fail.1578117583
Short name T97
Test name
Test status
Simulation time 670454476 ps
CPU time 61.57 seconds
Started Feb 08 07:09:17 PM UTC 25
Finished Feb 08 07:10:21 PM UTC 25
Peak memory 263140 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo
/hw/dv/tools/sim.tcl +ntb_random_seed=1578117583 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default.vdb -cm_
log /dev/null -cm_name 8.alert_handler_sig_int_fail.1578117583
Directory /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/8.alert_handler_sig_int_fail/latest

Test location /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default/8.alert_handler_smoke.1481899202
Short name T34
Test name
Test status
Simulation time 3443646746 ps
CPU time 80.82 seconds
Started Feb 08 07:09:04 PM UTC 25
Finished Feb 08 07:10:27 PM UTC 25
Peak memory 269344 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo
/hw/dv/tools/sim.tcl +ntb_random_seed=1481899202 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default.vdb -cm_log /de
v/null -cm_name 8.alert_handler_smoke.1481899202
Directory /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/8.alert_handler_smoke/latest

Test location /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default/8.alert_handler_stress_all.1210471181
Short name T135
Test name
Test status
Simulation time 22696515790 ps
CPU time 150.83 seconds
Started Feb 08 07:10:22 PM UTC 25
Finished Feb 08 07:12:56 PM UTC 25
Peak memory 269344 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1210471181 -assert nopostproc +UVM_TESTNAME=ale
rt_handler_base_test +UVM_TEST_SEQ=alert_handler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os
_regression/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_stress_all.1210471181
Directory /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/8.alert_handler_stress_all/latest

Test location /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default/9.alert_handler_alert_accum_saturation.726458710
Short name T133
Test name
Test status
Simulation time 122161823 ps
CPU time 5.03 seconds
Started Feb 08 07:12:16 PM UTC 25
Finished Feb 08 07:12:23 PM UTC 25
Peak memory 263360 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
paces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=726458710 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ale
rt_accum_saturation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/covera
ge/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_alert_accum_saturation.726458710
Directory /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/9.alert_handler_alert_accum_saturation/latest

Test location /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default/9.alert_handler_entropy.3183571586
Short name T61
Test name
Test status
Simulation time 36211400178 ps
CPU time 852.35 seconds
Started Feb 08 07:11:44 PM UTC 25
Finished Feb 08 07:26:06 PM UTC 25
Peak memory 285720 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3183571586 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST
_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_entropy.3183571586
Directory /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/9.alert_handler_entropy/latest

Test location /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default/9.alert_handler_entropy_stress.1281012056
Short name T134
Test name
Test status
Simulation time 293809801 ps
CPU time 17.71 seconds
Started Feb 08 07:12:05 PM UTC 25
Finished Feb 08 07:12:24 PM UTC 25
Peak memory 263404 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
paces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1281012056 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_en
tropy_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 9.alert_handler_entropy_stress.1281012056
Directory /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/9.alert_handler_entropy_stress/latest

Test location /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default/9.alert_handler_esc_alert_accum.1679388366
Short name T410
Test name
Test status
Simulation time 1123829374 ps
CPU time 139.93 seconds
Started Feb 08 07:11:25 PM UTC 25
Finished Feb 08 07:13:48 PM UTC 25
Peak memory 269548 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo
/hw/dv/tools/sim.tcl +ntb_random_seed=1679388366 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_ac
cum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 9.alert_handler_esc_alert_accum.1679388366
Directory /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/9.alert_handler_esc_alert_accum/latest

Test location /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default/9.alert_handler_esc_intr_timeout.865821023
Short name T98
Test name
Test status
Simulation time 285485110 ps
CPU time 26.32 seconds
Started Feb 08 07:11:19 PM UTC 25
Finished Feb 08 07:11:47 PM UTC 25
Peak memory 269292 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo
/hw/dv/tools/sim.tcl +ntb_random_seed=865821023 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_time
out_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 9.alert_handler_esc_intr_timeout.865821023
Directory /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/9.alert_handler_esc_intr_timeout/latest

Test location /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default/9.alert_handler_lpg.1194841111
Short name T111
Test name
Test status
Simulation time 38416213813 ps
CPU time 1908.67 seconds
Started Feb 08 07:11:48 PM UTC 25
Finished Feb 08 07:43:59 PM UTC 25
Peak memory 302112 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1194841111 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST
_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/cov
erage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_lpg.1194841111
Directory /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/9.alert_handler_lpg/latest

Test location /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default/9.alert_handler_lpg_stub_clk.1320576074
Short name T39
Test name
Test status
Simulation time 7890920341 ps
CPU time 1062.32 seconds
Started Feb 08 07:11:51 PM UTC 25
Finished Feb 08 07:29:47 PM UTC 25
Peak memory 285728 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1320576074 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST
_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/alert_handler-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_lpg_stub_clk.1320576074
Directory /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/9.alert_handler_lpg_stub_clk/latest

Test location /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default/9.alert_handler_ping_timeout.3538465781
Short name T341
Test name
Test status
Simulation time 4112011519 ps
CPU time 105.06 seconds
Started Feb 08 07:11:45 PM UTC 25
Finished Feb 08 07:13:32 PM UTC 25
Peak memory 263200 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq
ueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3538465781 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST
_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/alert_handler-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_ping_timeout.3538465781
Directory /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/9.alert_handler_ping_timeout/latest

Test location /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default/9.alert_handler_random_alerts.1216938506
Short name T129
Test name
Test status
Simulation time 2177889251 ps
CPU time 57.41 seconds
Started Feb 08 07:10:45 PM UTC 25
Finished Feb 08 07:11:45 PM UTC 25
Peak memory 269344 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo
/hw/dv/tools/sim.tcl +ntb_random_seed=1216938506 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alert
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default.vdb -cm
_log /dev/null -cm_name 9.alert_handler_random_alerts.1216938506
Directory /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/9.alert_handler_random_alerts/latest

Test location /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default/9.alert_handler_random_classes.3392533151
Short name T35
Test name
Test status
Simulation time 2160600741 ps
CPU time 34.51 seconds
Started Feb 08 07:10:58 PM UTC 25
Finished Feb 08 07:11:34 PM UTC 25
Peak memory 269344 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo
/hw/dv/tools/sim.tcl +ntb_random_seed=3392533151 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_class
es_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default.vdb -c
m_log /dev/null -cm_name 9.alert_handler_random_classes.3392533151
Directory /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/9.alert_handler_random_classes/latest

Test location /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default/9.alert_handler_sig_int_fail.691736525
Short name T99
Test name
Test status
Simulation time 1444028661 ps
CPU time 46.99 seconds
Started Feb 08 07:11:35 PM UTC 25
Finished Feb 08 07:12:24 PM UTC 25
Peak memory 263136 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo
/hw/dv/tools/sim.tcl +ntb_random_seed=691736525 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default.vdb -cm_l
og /dev/null -cm_name 9.alert_handler_sig_int_fail.691736525
Directory /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/9.alert_handler_sig_int_fail/latest

Test location /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default/9.alert_handler_smoke.23623458
Short name T407
Test name
Test status
Simulation time 1015827917 ps
CPU time 24.57 seconds
Started Feb 08 07:10:31 PM UTC 25
Finished Feb 08 07:10:58 PM UTC 25
Peak memory 267500 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo
/hw/dv/tools/sim.tcl +ntb_random_seed=23623458 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/
null -cm_name 9.alert_handler_smoke.23623458
Directory /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/9.alert_handler_smoke/latest

Test location /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default/9.alert_handler_stress_all.748235384
Short name T101
Test name
Test status
Simulation time 11555360106 ps
CPU time 251.99 seconds
Started Feb 08 07:12:13 PM UTC 25
Finished Feb 08 07:16:29 PM UTC 25
Peak memory 269424 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=748235384 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_
regression/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_stress_all.748235384
Directory /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/9.alert_handler_stress_all/latest

Test location /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default/9.alert_handler_stress_all_with_rand_reset.4018564874
Short name T701
Test name
Test status
Simulation time 137266238939 ps
CPU time 9178.96 seconds
Started Feb 08 07:12:24 PM UTC 25
Finished Feb 08 09:47:08 PM UTC 25
Peak memory 370528 kb
Host ot-runner-1.us-west1-b.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=ale
rt_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=40185
64874 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_stress_all
_with_rand_reset.4018564874
Directory /workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/9.alert_handler_stress_all_with_rand_reset/latest
0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%