CLKMGR Simulation Results

Sunday April 21 2024 19:02:51 UTC

GitHub Revision: 4fd94db59a

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 89274329416853274976097168471417145417282051311181377329444669936981619711436

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke clkmgr_smoke 1.350s 197.188us 50 50 100.00
V1 csr_hw_reset clkmgr_csr_hw_reset 1.080s 119.101us 5 5 100.00
V1 csr_rw clkmgr_csr_rw 1.230s 182.276us 20 20 100.00
V1 csr_bit_bash clkmgr_csr_bit_bash 5.330s 506.150us 5 5 100.00
V1 csr_aliasing clkmgr_csr_aliasing 1.810s 109.469us 5 5 100.00
V1 csr_mem_rw_with_rand_reset clkmgr_csr_mem_rw_with_rand_reset 1.820s 67.263us 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr clkmgr_csr_rw 1.230s 182.276us 20 20 100.00
clkmgr_csr_aliasing 1.810s 109.469us 5 5 100.00
V1 TOTAL 105 105 100.00
V2 peri_enables clkmgr_peri 1.120s 146.466us 50 50 100.00
V2 trans_enables clkmgr_trans 2.370s 562.270us 50 50 100.00
V2 extclk clkmgr_extclk 2.070s 455.767us 50 50 100.00
V2 clk_status clkmgr_clk_status 1.080s 182.944us 50 50 100.00
V2 jitter clkmgr_smoke 1.350s 197.188us 50 50 100.00
V2 frequency clkmgr_frequency 18.520s 2.358ms 50 50 100.00
V2 frequency_timeout clkmgr_frequency_timeout 16.390s 2.298ms 50 50 100.00
V2 frequency_overflow clkmgr_frequency 18.520s 2.358ms 50 50 100.00
V2 stress_all clkmgr_stress_all 1.284m 11.052ms 50 50 100.00
V2 intr_test clkmgr_intr_test 0.810s 74.888us 50 50 100.00
V2 alert_test clkmgr_alert_test 1.350s 240.964us 50 50 100.00
V2 tl_d_oob_addr_access clkmgr_tl_errors 6.290s 1.406ms 20 20 100.00
V2 tl_d_illegal_access clkmgr_tl_errors 6.290s 1.406ms 20 20 100.00
V2 tl_d_outstanding_access clkmgr_csr_hw_reset 1.080s 119.101us 5 5 100.00
clkmgr_csr_rw 1.230s 182.276us 20 20 100.00
clkmgr_csr_aliasing 1.810s 109.469us 5 5 100.00
clkmgr_same_csr_outstanding 2.290s 328.866us 20 20 100.00
V2 tl_d_partial_access clkmgr_csr_hw_reset 1.080s 119.101us 5 5 100.00
clkmgr_csr_rw 1.230s 182.276us 20 20 100.00
clkmgr_csr_aliasing 1.810s 109.469us 5 5 100.00
clkmgr_same_csr_outstanding 2.290s 328.866us 20 20 100.00
V2 TOTAL 490 490 100.00
V2S tl_intg_err clkmgr_sec_cm 4.810s 1.068ms 5 5 100.00
clkmgr_tl_intg_err 3.580s 505.863us 20 20 100.00
V2S shadow_reg_update_error clkmgr_shadow_reg_errors 2.980s 528.721us 20 20 100.00
V2S shadow_reg_read_clear_staged_value clkmgr_shadow_reg_errors 2.980s 528.721us 20 20 100.00
V2S shadow_reg_storage_error clkmgr_shadow_reg_errors 2.980s 528.721us 20 20 100.00
V2S shadowed_reset_glitch clkmgr_shadow_reg_errors 2.980s 528.721us 20 20 100.00
V2S shadow_reg_update_error_with_csr_rw clkmgr_shadow_reg_errors_with_csr_rw 4.160s 686.984us 20 20 100.00
V2S sec_cm_bus_integrity clkmgr_tl_intg_err 3.580s 505.863us 20 20 100.00
V2S sec_cm_meas_clk_bkgn_chk clkmgr_frequency 18.520s 2.358ms 50 50 100.00
V2S sec_cm_timeout_clk_bkgn_chk clkmgr_frequency_timeout 16.390s 2.298ms 50 50 100.00
V2S sec_cm_meas_config_shadow clkmgr_shadow_reg_errors 2.980s 528.721us 20 20 100.00
V2S sec_cm_idle_intersig_mubi clkmgr_idle_intersig_mubi 2.350s 521.063us 50 50 100.00
V2S sec_cm_lc_ctrl_intersig_mubi clkmgr_lc_ctrl_intersig_mubi 1.620s 267.290us 50 50 100.00
V2S sec_cm_lc_ctrl_clk_handshake_intersig_mubi clkmgr_lc_clk_byp_req_intersig_mubi 1.460s 274.852us 50 50 100.00
V2S sec_cm_clk_handshake_intersig_mubi clkmgr_clk_handshake_intersig_mubi 1.450s 244.527us 50 50 100.00
V2S sec_cm_div_intersig_mubi clkmgr_div_intersig_mubi 1.820s 349.036us 50 50 100.00
V2S sec_cm_jitter_config_mubi clkmgr_csr_rw 1.230s 182.276us 20 20 100.00
V2S sec_cm_idle_ctr_redun clkmgr_sec_cm 4.810s 1.068ms 5 5 100.00
V2S sec_cm_meas_config_regwen clkmgr_csr_rw 1.230s 182.276us 20 20 100.00
V2S sec_cm_clk_ctrl_config_regwen clkmgr_csr_rw 1.230s 182.276us 20 20 100.00
V2S prim_count_check clkmgr_sec_cm 4.810s 1.068ms 5 5 100.00
V2S TOTAL 315 315 100.00
V3 regwen clkmgr_regwen 7.040s 1.323ms 50 50 100.00
V3 stress_all_with_rand_reset clkmgr_stress_all_with_rand_reset 31.772m 515.586ms 50 50 100.00
V3 TOTAL 100 100 100.00
TOTAL 1010 1010 100.00

Testplan Progress

Items Total Written Passing Progress
V1 6 6 6 100.00
V2 11 11 11 100.00
V2S 9 9 9 100.00
V3 2 2 2 100.00

Coverage Results

Coverage Dashboard

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP
98.52 99.15 95.84 100.00 100.00 98.81 97.01 98.80

Past Results