Line Coverage for Module :
prim_pulse_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 31 | 3 | 3 | 100.00 |
CONT_ASSIGN | 49 | 0 | 0 | |
CONT_ASSIGN | 52 | 0 | 0 | |
ALWAYS | 55 | 0 | 0 | |
ALWAYS | 89 | 3 | 3 | 100.00 |
CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
31 |
1 |
1 |
32 |
1 |
1 |
34 |
1 |
1 |
49 |
|
unreachable |
52 |
|
unreachable |
55 |
|
unreachable |
56 |
|
unreachable |
58 |
|
unreachable |
89 |
1 |
1 |
90 |
1 |
1 |
92 |
1 |
1 |
97 |
1 |
1 |
Cond Coverage for Module :
prim_pulse_sync
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 34
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T5,T6,T7 |
0 | 1 | Covered | T1,T2,T4 |
1 | 0 | Covered | T1,T2,T4 |
1 | 1 | Covered | T1,T2,T4 |
LINE 97
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T5,T6,T7 |
0 | 1 | Covered | T1,T2,T4 |
1 | 0 | Covered | T1,T2,T4 |
1 | 1 | Covered | T1,T2,T4 |
Branch Coverage for Module :
prim_pulse_sync
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
31 |
2 |
2 |
100.00 |
IF |
89 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 31 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T5,T6,T7 |
0 |
Covered |
T5,T6,T7 |
LineNo. Expression
-1-: 89 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T5,T6,T7 |
0 |
Covered |
T5,T6,T7 |
Assert Coverage for Module :
prim_pulse_sync
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
556222 |
0 |
0 |
T1 |
477160 |
254 |
0 |
0 |
T2 |
3313723 |
1880 |
0 |
0 |
T3 |
1371469 |
598 |
0 |
0 |
T4 |
101892 |
40 |
0 |
0 |
T11 |
0 |
6096 |
0 |
0 |
T12 |
0 |
5476 |
0 |
0 |
T13 |
0 |
280 |
0 |
0 |
T14 |
0 |
500 |
0 |
0 |
T15 |
0 |
670 |
0 |
0 |
T16 |
0 |
276 |
0 |
0 |
T18 |
38204 |
0 |
0 |
0 |
T19 |
9904 |
0 |
0 |
0 |
T20 |
21173 |
0 |
0 |
0 |
T21 |
20450 |
0 |
0 |
0 |
T22 |
10489 |
0 |
0 |
0 |
T23 |
10397 |
0 |
0 |
0 |
T33 |
0 |
378 |
0 |
0 |
T58 |
14158 |
2 |
0 |
0 |
T59 |
9652 |
1 |
0 |
0 |
T62 |
18432 |
1 |
0 |
0 |
T63 |
6812 |
1 |
0 |
0 |
T64 |
11232 |
1 |
0 |
0 |
T117 |
9954 |
1 |
0 |
0 |
T118 |
10424 |
1 |
0 |
0 |
T119 |
12654 |
1 |
0 |
0 |
T120 |
8022 |
1 |
0 |
0 |
T121 |
11156 |
1 |
0 |
0 |
T122 |
5009 |
0 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
555406 |
0 |
0 |
T1 |
119121 |
254 |
0 |
0 |
T2 |
1172552 |
1880 |
0 |
0 |
T3 |
733849 |
598 |
0 |
0 |
T4 |
25477 |
40 |
0 |
0 |
T11 |
0 |
5853 |
0 |
0 |
T12 |
0 |
5476 |
0 |
0 |
T13 |
0 |
280 |
0 |
0 |
T14 |
0 |
500 |
0 |
0 |
T15 |
0 |
670 |
0 |
0 |
T16 |
0 |
276 |
0 |
0 |
T18 |
10859 |
0 |
0 |
0 |
T19 |
5774 |
0 |
0 |
0 |
T20 |
6865 |
0 |
0 |
0 |
T21 |
6580 |
0 |
0 |
0 |
T22 |
6110 |
0 |
0 |
0 |
T23 |
3370 |
0 |
0 |
0 |
T33 |
0 |
378 |
0 |
0 |
T58 |
6516 |
2 |
0 |
0 |
T59 |
17802 |
1 |
0 |
0 |
T62 |
7948 |
1 |
0 |
0 |
T63 |
2898 |
1 |
0 |
0 |
T64 |
20548 |
1 |
0 |
0 |
T117 |
14188 |
1 |
0 |
0 |
T118 |
9866 |
1 |
0 |
0 |
T119 |
22782 |
1 |
0 |
0 |
T120 |
7163 |
1 |
0 |
0 |
T121 |
4608 |
1 |
0 |
0 |
T122 |
2058 |
0 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_en_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 31 | 3 | 3 | 100.00 |
CONT_ASSIGN | 49 | 0 | 0 | |
CONT_ASSIGN | 52 | 0 | 0 | |
ALWAYS | 55 | 0 | 0 | |
ALWAYS | 89 | 3 | 3 | 100.00 |
CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
31 |
1 |
1 |
32 |
1 |
1 |
34 |
1 |
1 |
49 |
|
unreachable |
52 |
|
unreachable |
55 |
|
unreachable |
56 |
|
unreachable |
58 |
|
unreachable |
89 |
1 |
1 |
90 |
1 |
1 |
92 |
1 |
1 |
97 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_en_cdc.u_src_to_dst_req
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 34
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T5,T6,T7 |
0 | 1 | Covered | T1,T2,T4 |
1 | 0 | Covered | T1,T2,T4 |
1 | 1 | Covered | T1,T2,T4 |
LINE 97
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T5,T6,T7 |
0 | 1 | Covered | T1,T2,T4 |
1 | 0 | Covered | T1,T2,T4 |
1 | 1 | Covered | T1,T2,T4 |
Branch Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_en_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
31 |
2 |
2 |
100.00 |
IF |
89 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 31 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T5,T6,T7 |
0 |
Covered |
T5,T6,T7 |
LineNo. Expression
-1-: 89 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T5,T6,T7 |
0 |
Covered |
T5,T6,T7 |
Assert Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_en_cdc.u_src_to_dst_req
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
223910640 |
14511 |
0 |
0 |
T1 |
118070 |
20 |
0 |
0 |
T2 |
768287 |
136 |
0 |
0 |
T3 |
284364 |
50 |
0 |
0 |
T4 |
28697 |
8 |
0 |
0 |
T11 |
0 |
259 |
0 |
0 |
T12 |
0 |
254 |
0 |
0 |
T13 |
0 |
20 |
0 |
0 |
T14 |
0 |
40 |
0 |
0 |
T15 |
0 |
38 |
0 |
0 |
T18 |
9219 |
0 |
0 |
0 |
T19 |
1995 |
0 |
0 |
0 |
T20 |
5283 |
0 |
0 |
0 |
T21 |
4775 |
0 |
0 |
0 |
T22 |
2084 |
0 |
0 |
0 |
T23 |
2589 |
0 |
0 |
0 |
T33 |
0 |
14 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
73828701 |
14511 |
0 |
0 |
T1 |
29517 |
20 |
0 |
0 |
T2 |
389922 |
136 |
0 |
0 |
T3 |
293261 |
50 |
0 |
0 |
T4 |
7472 |
8 |
0 |
0 |
T11 |
0 |
259 |
0 |
0 |
T12 |
0 |
254 |
0 |
0 |
T13 |
0 |
20 |
0 |
0 |
T14 |
0 |
40 |
0 |
0 |
T15 |
0 |
38 |
0 |
0 |
T18 |
1536 |
0 |
0 |
0 |
T19 |
2058 |
0 |
0 |
0 |
T20 |
1375 |
0 |
0 |
0 |
T21 |
1243 |
0 |
0 |
0 |
T22 |
2170 |
0 |
0 |
0 |
T23 |
673 |
0 |
0 |
0 |
T33 |
0 |
14 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 31 | 3 | 3 | 100.00 |
CONT_ASSIGN | 49 | 0 | 0 | |
CONT_ASSIGN | 52 | 0 | 0 | |
ALWAYS | 55 | 0 | 0 | |
ALWAYS | 89 | 3 | 3 | 100.00 |
CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
31 |
1 |
1 |
32 |
1 |
1 |
34 |
1 |
1 |
49 |
|
unreachable |
52 |
|
unreachable |
55 |
|
unreachable |
56 |
|
unreachable |
58 |
|
unreachable |
89 |
1 |
1 |
90 |
1 |
1 |
92 |
1 |
1 |
97 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_cdc.u_src_to_dst_req
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 34
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T5,T6,T7 |
0 | 1 | Covered | T1,T2,T4 |
1 | 0 | Covered | T1,T2,T4 |
1 | 1 | Covered | T1,T2,T4 |
LINE 97
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T5,T6,T7 |
0 | 1 | Covered | T1,T2,T4 |
1 | 0 | Covered | T1,T2,T4 |
1 | 1 | Covered | T1,T2,T4 |
Branch Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
31 |
2 |
2 |
100.00 |
IF |
89 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 31 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T5,T6,T7 |
0 |
Covered |
T5,T6,T7 |
LineNo. Expression
-1-: 89 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T5,T6,T7 |
0 |
Covered |
T5,T6,T7 |
Assert Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_cdc.u_src_to_dst_req
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
223910640 |
20222 |
0 |
0 |
T1 |
118070 |
20 |
0 |
0 |
T2 |
768287 |
136 |
0 |
0 |
T3 |
284364 |
50 |
0 |
0 |
T4 |
28697 |
16 |
0 |
0 |
T11 |
0 |
265 |
0 |
0 |
T12 |
0 |
259 |
0 |
0 |
T13 |
0 |
20 |
0 |
0 |
T14 |
0 |
40 |
0 |
0 |
T15 |
0 |
38 |
0 |
0 |
T18 |
9219 |
0 |
0 |
0 |
T19 |
1995 |
0 |
0 |
0 |
T20 |
5283 |
0 |
0 |
0 |
T21 |
4775 |
0 |
0 |
0 |
T22 |
2084 |
0 |
0 |
0 |
T23 |
2589 |
0 |
0 |
0 |
T33 |
0 |
14 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
73828701 |
20239 |
0 |
0 |
T1 |
29517 |
20 |
0 |
0 |
T2 |
389922 |
136 |
0 |
0 |
T3 |
293261 |
50 |
0 |
0 |
T4 |
7472 |
16 |
0 |
0 |
T11 |
0 |
265 |
0 |
0 |
T12 |
0 |
259 |
0 |
0 |
T13 |
0 |
20 |
0 |
0 |
T14 |
0 |
40 |
0 |
0 |
T15 |
0 |
38 |
0 |
0 |
T18 |
1536 |
0 |
0 |
0 |
T19 |
2058 |
0 |
0 |
0 |
T20 |
1375 |
0 |
0 |
0 |
T21 |
1243 |
0 |
0 |
0 |
T22 |
2170 |
0 |
0 |
0 |
T23 |
673 |
0 |
0 |
0 |
T33 |
0 |
14 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 31 | 3 | 3 | 100.00 |
CONT_ASSIGN | 49 | 0 | 0 | |
CONT_ASSIGN | 52 | 0 | 0 | |
ALWAYS | 55 | 0 | 0 | |
ALWAYS | 89 | 3 | 3 | 100.00 |
CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
31 |
1 |
1 |
32 |
1 |
1 |
34 |
1 |
1 |
49 |
|
unreachable |
52 |
|
unreachable |
55 |
|
unreachable |
56 |
|
unreachable |
58 |
|
unreachable |
89 |
1 |
1 |
90 |
1 |
1 |
92 |
1 |
1 |
97 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 34
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T5,T6,T7 |
0 | 1 | Covered | T1,T2,T4 |
1 | 0 | Covered | T1,T2,T4 |
1 | 1 | Covered | T1,T2,T4 |
LINE 97
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T5,T6,T7 |
0 | 1 | Covered | T1,T2,T4 |
1 | 0 | Covered | T1,T2,T4 |
1 | 1 | Covered | T1,T2,T4 |
Branch Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
31 |
2 |
2 |
100.00 |
IF |
89 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 31 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T5,T6,T7 |
0 |
Covered |
T5,T6,T7 |
LineNo. Expression
-1-: 89 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T5,T6,T7 |
0 |
Covered |
T5,T6,T7 |
Assert Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
73828701 |
20218 |
0 |
0 |
T1 |
29517 |
20 |
0 |
0 |
T2 |
389922 |
136 |
0 |
0 |
T3 |
293261 |
50 |
0 |
0 |
T4 |
7472 |
16 |
0 |
0 |
T11 |
0 |
265 |
0 |
0 |
T12 |
0 |
259 |
0 |
0 |
T13 |
0 |
20 |
0 |
0 |
T14 |
0 |
40 |
0 |
0 |
T15 |
0 |
38 |
0 |
0 |
T18 |
1536 |
0 |
0 |
0 |
T19 |
2058 |
0 |
0 |
0 |
T20 |
1375 |
0 |
0 |
0 |
T21 |
1243 |
0 |
0 |
0 |
T22 |
2170 |
0 |
0 |
0 |
T23 |
673 |
0 |
0 |
0 |
T33 |
0 |
14 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
223910640 |
20229 |
0 |
0 |
T1 |
118070 |
20 |
0 |
0 |
T2 |
768287 |
136 |
0 |
0 |
T3 |
284364 |
50 |
0 |
0 |
T4 |
28697 |
16 |
0 |
0 |
T11 |
0 |
265 |
0 |
0 |
T12 |
0 |
259 |
0 |
0 |
T13 |
0 |
20 |
0 |
0 |
T14 |
0 |
40 |
0 |
0 |
T15 |
0 |
38 |
0 |
0 |
T18 |
9219 |
0 |
0 |
0 |
T19 |
1995 |
0 |
0 |
0 |
T20 |
5283 |
0 |
0 |
0 |
T21 |
4775 |
0 |
0 |
0 |
T22 |
2084 |
0 |
0 |
0 |
T23 |
2589 |
0 |
0 |
0 |
T33 |
0 |
14 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_en_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 31 | 3 | 3 | 100.00 |
CONT_ASSIGN | 49 | 0 | 0 | |
CONT_ASSIGN | 52 | 0 | 0 | |
ALWAYS | 55 | 0 | 0 | |
ALWAYS | 89 | 3 | 3 | 100.00 |
CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
31 |
1 |
1 |
32 |
1 |
1 |
34 |
1 |
1 |
49 |
|
unreachable |
52 |
|
unreachable |
55 |
|
unreachable |
56 |
|
unreachable |
58 |
|
unreachable |
89 |
1 |
1 |
90 |
1 |
1 |
92 |
1 |
1 |
97 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_en_cdc.u_src_to_dst_req
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 34
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T5,T6,T7 |
0 | 1 | Covered | T1,T2,T4 |
1 | 0 | Covered | T1,T2,T4 |
1 | 1 | Covered | T1,T2,T4 |
LINE 97
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T5,T6,T7 |
0 | 1 | Covered | T1,T2,T4 |
1 | 0 | Covered | T1,T2,T4 |
1 | 1 | Covered | T1,T2,T4 |
Branch Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_en_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
31 |
2 |
2 |
100.00 |
IF |
89 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 31 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T5,T6,T7 |
0 |
Covered |
T5,T6,T7 |
LineNo. Expression
-1-: 89 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T5,T6,T7 |
0 |
Covered |
T5,T6,T7 |
Assert Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_en_cdc.u_src_to_dst_req
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
111190200 |
14511 |
0 |
0 |
T1 |
59023 |
20 |
0 |
0 |
T2 |
383768 |
136 |
0 |
0 |
T3 |
142179 |
50 |
0 |
0 |
T4 |
10237 |
8 |
0 |
0 |
T11 |
0 |
259 |
0 |
0 |
T12 |
0 |
254 |
0 |
0 |
T13 |
0 |
20 |
0 |
0 |
T14 |
0 |
40 |
0 |
0 |
T15 |
0 |
38 |
0 |
0 |
T18 |
5099 |
0 |
0 |
0 |
T19 |
1078 |
0 |
0 |
0 |
T20 |
2575 |
0 |
0 |
0 |
T21 |
2702 |
0 |
0 |
0 |
T22 |
1162 |
0 |
0 |
0 |
T23 |
1268 |
0 |
0 |
0 |
T33 |
0 |
14 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
73828701 |
14511 |
0 |
0 |
T1 |
29517 |
20 |
0 |
0 |
T2 |
389922 |
136 |
0 |
0 |
T3 |
293261 |
50 |
0 |
0 |
T4 |
7472 |
8 |
0 |
0 |
T11 |
0 |
259 |
0 |
0 |
T12 |
0 |
254 |
0 |
0 |
T13 |
0 |
20 |
0 |
0 |
T14 |
0 |
40 |
0 |
0 |
T15 |
0 |
38 |
0 |
0 |
T18 |
1536 |
0 |
0 |
0 |
T19 |
2058 |
0 |
0 |
0 |
T20 |
1375 |
0 |
0 |
0 |
T21 |
1243 |
0 |
0 |
0 |
T22 |
2170 |
0 |
0 |
0 |
T23 |
673 |
0 |
0 |
0 |
T33 |
0 |
14 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 31 | 3 | 3 | 100.00 |
CONT_ASSIGN | 49 | 0 | 0 | |
CONT_ASSIGN | 52 | 0 | 0 | |
ALWAYS | 55 | 0 | 0 | |
ALWAYS | 89 | 3 | 3 | 100.00 |
CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
31 |
1 |
1 |
32 |
1 |
1 |
34 |
1 |
1 |
49 |
|
unreachable |
52 |
|
unreachable |
55 |
|
unreachable |
56 |
|
unreachable |
58 |
|
unreachable |
89 |
1 |
1 |
90 |
1 |
1 |
92 |
1 |
1 |
97 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_cdc.u_src_to_dst_req
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 34
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T5,T6,T7 |
0 | 1 | Covered | T1,T2,T4 |
1 | 0 | Covered | T1,T2,T4 |
1 | 1 | Covered | T1,T2,T4 |
LINE 97
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T5,T6,T7 |
0 | 1 | Covered | T1,T2,T4 |
1 | 0 | Covered | T1,T2,T4 |
1 | 1 | Covered | T1,T2,T4 |
Branch Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
31 |
2 |
2 |
100.00 |
IF |
89 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 31 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T5,T6,T7 |
0 |
Covered |
T5,T6,T7 |
LineNo. Expression
-1-: 89 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T5,T6,T7 |
0 |
Covered |
T5,T6,T7 |
Assert Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_cdc.u_src_to_dst_req
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
111190200 |
20258 |
0 |
0 |
T1 |
59023 |
20 |
0 |
0 |
T2 |
383768 |
136 |
0 |
0 |
T3 |
142179 |
50 |
0 |
0 |
T4 |
10237 |
16 |
0 |
0 |
T11 |
0 |
265 |
0 |
0 |
T12 |
0 |
259 |
0 |
0 |
T13 |
0 |
20 |
0 |
0 |
T14 |
0 |
40 |
0 |
0 |
T15 |
0 |
38 |
0 |
0 |
T18 |
5099 |
0 |
0 |
0 |
T19 |
1078 |
0 |
0 |
0 |
T20 |
2575 |
0 |
0 |
0 |
T21 |
2702 |
0 |
0 |
0 |
T22 |
1162 |
0 |
0 |
0 |
T23 |
1268 |
0 |
0 |
0 |
T33 |
0 |
14 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
73828701 |
20279 |
0 |
0 |
T1 |
29517 |
20 |
0 |
0 |
T2 |
389922 |
136 |
0 |
0 |
T3 |
293261 |
50 |
0 |
0 |
T4 |
7472 |
16 |
0 |
0 |
T11 |
0 |
265 |
0 |
0 |
T12 |
0 |
259 |
0 |
0 |
T13 |
0 |
20 |
0 |
0 |
T14 |
0 |
40 |
0 |
0 |
T15 |
0 |
38 |
0 |
0 |
T18 |
1536 |
0 |
0 |
0 |
T19 |
2058 |
0 |
0 |
0 |
T20 |
1375 |
0 |
0 |
0 |
T21 |
1243 |
0 |
0 |
0 |
T22 |
2170 |
0 |
0 |
0 |
T23 |
673 |
0 |
0 |
0 |
T33 |
0 |
14 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 31 | 3 | 3 | 100.00 |
CONT_ASSIGN | 49 | 0 | 0 | |
CONT_ASSIGN | 52 | 0 | 0 | |
ALWAYS | 55 | 0 | 0 | |
ALWAYS | 89 | 3 | 3 | 100.00 |
CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
31 |
1 |
1 |
32 |
1 |
1 |
34 |
1 |
1 |
49 |
|
unreachable |
52 |
|
unreachable |
55 |
|
unreachable |
56 |
|
unreachable |
58 |
|
unreachable |
89 |
1 |
1 |
90 |
1 |
1 |
92 |
1 |
1 |
97 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 34
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T5,T6,T7 |
0 | 1 | Covered | T1,T2,T4 |
1 | 0 | Covered | T1,T2,T4 |
1 | 1 | Covered | T1,T2,T4 |
LINE 97
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T5,T6,T7 |
0 | 1 | Covered | T1,T2,T4 |
1 | 0 | Covered | T1,T2,T4 |
1 | 1 | Covered | T1,T2,T4 |
Branch Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
31 |
2 |
2 |
100.00 |
IF |
89 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 31 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T5,T6,T7 |
0 |
Covered |
T5,T6,T7 |
LineNo. Expression
-1-: 89 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T5,T6,T7 |
0 |
Covered |
T5,T6,T7 |
Assert Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
73828701 |
20250 |
0 |
0 |
T1 |
29517 |
20 |
0 |
0 |
T2 |
389922 |
136 |
0 |
0 |
T3 |
293261 |
50 |
0 |
0 |
T4 |
7472 |
16 |
0 |
0 |
T11 |
0 |
265 |
0 |
0 |
T12 |
0 |
259 |
0 |
0 |
T13 |
0 |
20 |
0 |
0 |
T14 |
0 |
40 |
0 |
0 |
T15 |
0 |
38 |
0 |
0 |
T18 |
1536 |
0 |
0 |
0 |
T19 |
2058 |
0 |
0 |
0 |
T20 |
1375 |
0 |
0 |
0 |
T21 |
1243 |
0 |
0 |
0 |
T22 |
2170 |
0 |
0 |
0 |
T23 |
673 |
0 |
0 |
0 |
T33 |
0 |
14 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
111190200 |
20261 |
0 |
0 |
T1 |
59023 |
20 |
0 |
0 |
T2 |
383768 |
136 |
0 |
0 |
T3 |
142179 |
50 |
0 |
0 |
T4 |
10237 |
16 |
0 |
0 |
T11 |
0 |
265 |
0 |
0 |
T12 |
0 |
259 |
0 |
0 |
T13 |
0 |
20 |
0 |
0 |
T14 |
0 |
40 |
0 |
0 |
T15 |
0 |
38 |
0 |
0 |
T18 |
5099 |
0 |
0 |
0 |
T19 |
1078 |
0 |
0 |
0 |
T20 |
2575 |
0 |
0 |
0 |
T21 |
2702 |
0 |
0 |
0 |
T22 |
1162 |
0 |
0 |
0 |
T23 |
1268 |
0 |
0 |
0 |
T33 |
0 |
14 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_en_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 31 | 3 | 3 | 100.00 |
CONT_ASSIGN | 49 | 0 | 0 | |
CONT_ASSIGN | 52 | 0 | 0 | |
ALWAYS | 55 | 0 | 0 | |
ALWAYS | 89 | 3 | 3 | 100.00 |
CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
31 |
1 |
1 |
32 |
1 |
1 |
34 |
1 |
1 |
49 |
|
unreachable |
52 |
|
unreachable |
55 |
|
unreachable |
56 |
|
unreachable |
58 |
|
unreachable |
89 |
1 |
1 |
90 |
1 |
1 |
92 |
1 |
1 |
97 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_en_cdc.u_src_to_dst_req
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 34
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T5,T6,T7 |
0 | 1 | Covered | T1,T2,T4 |
1 | 0 | Covered | T1,T2,T4 |
1 | 1 | Covered | T1,T2,T4 |
LINE 97
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T5,T6,T7 |
0 | 1 | Covered | T1,T2,T4 |
1 | 0 | Covered | T1,T2,T4 |
1 | 1 | Covered | T1,T2,T4 |
Branch Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_en_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
31 |
2 |
2 |
100.00 |
IF |
89 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 31 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T5,T6,T7 |
0 |
Covered |
T5,T6,T7 |
LineNo. Expression
-1-: 89 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T5,T6,T7 |
0 |
Covered |
T5,T6,T7 |
Assert Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_en_cdc.u_src_to_dst_req
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
55594684 |
14511 |
0 |
0 |
T1 |
29511 |
20 |
0 |
0 |
T2 |
191885 |
136 |
0 |
0 |
T3 |
71085 |
50 |
0 |
0 |
T4 |
5118 |
8 |
0 |
0 |
T11 |
0 |
259 |
0 |
0 |
T12 |
0 |
254 |
0 |
0 |
T13 |
0 |
20 |
0 |
0 |
T14 |
0 |
40 |
0 |
0 |
T15 |
0 |
38 |
0 |
0 |
T18 |
2548 |
0 |
0 |
0 |
T19 |
538 |
0 |
0 |
0 |
T20 |
1287 |
0 |
0 |
0 |
T21 |
1351 |
0 |
0 |
0 |
T22 |
579 |
0 |
0 |
0 |
T23 |
634 |
0 |
0 |
0 |
T33 |
0 |
14 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
73828701 |
14511 |
0 |
0 |
T1 |
29517 |
20 |
0 |
0 |
T2 |
389922 |
136 |
0 |
0 |
T3 |
293261 |
50 |
0 |
0 |
T4 |
7472 |
8 |
0 |
0 |
T11 |
0 |
259 |
0 |
0 |
T12 |
0 |
254 |
0 |
0 |
T13 |
0 |
20 |
0 |
0 |
T14 |
0 |
40 |
0 |
0 |
T15 |
0 |
38 |
0 |
0 |
T18 |
1536 |
0 |
0 |
0 |
T19 |
2058 |
0 |
0 |
0 |
T20 |
1375 |
0 |
0 |
0 |
T21 |
1243 |
0 |
0 |
0 |
T22 |
2170 |
0 |
0 |
0 |
T23 |
673 |
0 |
0 |
0 |
T33 |
0 |
14 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 31 | 3 | 3 | 100.00 |
CONT_ASSIGN | 49 | 0 | 0 | |
CONT_ASSIGN | 52 | 0 | 0 | |
ALWAYS | 55 | 0 | 0 | |
ALWAYS | 89 | 3 | 3 | 100.00 |
CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
31 |
1 |
1 |
32 |
1 |
1 |
34 |
1 |
1 |
49 |
|
unreachable |
52 |
|
unreachable |
55 |
|
unreachable |
56 |
|
unreachable |
58 |
|
unreachable |
89 |
1 |
1 |
90 |
1 |
1 |
92 |
1 |
1 |
97 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_cdc.u_src_to_dst_req
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 34
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T5,T6,T7 |
0 | 1 | Covered | T1,T2,T4 |
1 | 0 | Covered | T1,T2,T4 |
1 | 1 | Covered | T1,T2,T4 |
LINE 97
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T5,T6,T7 |
0 | 1 | Covered | T1,T2,T4 |
1 | 0 | Covered | T1,T2,T4 |
1 | 1 | Covered | T1,T2,T4 |
Branch Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
31 |
2 |
2 |
100.00 |
IF |
89 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 31 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T5,T6,T7 |
0 |
Covered |
T5,T6,T7 |
LineNo. Expression
-1-: 89 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T5,T6,T7 |
0 |
Covered |
T5,T6,T7 |
Assert Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_cdc.u_src_to_dst_req
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
55594684 |
20079 |
0 |
0 |
T1 |
29511 |
20 |
0 |
0 |
T2 |
191885 |
136 |
0 |
0 |
T3 |
71085 |
50 |
0 |
0 |
T4 |
5118 |
16 |
0 |
0 |
T11 |
0 |
265 |
0 |
0 |
T12 |
0 |
259 |
0 |
0 |
T13 |
0 |
20 |
0 |
0 |
T14 |
0 |
40 |
0 |
0 |
T15 |
0 |
38 |
0 |
0 |
T18 |
2548 |
0 |
0 |
0 |
T19 |
538 |
0 |
0 |
0 |
T20 |
1287 |
0 |
0 |
0 |
T21 |
1351 |
0 |
0 |
0 |
T22 |
579 |
0 |
0 |
0 |
T23 |
634 |
0 |
0 |
0 |
T33 |
0 |
14 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
73828701 |
20106 |
0 |
0 |
T1 |
29517 |
20 |
0 |
0 |
T2 |
389922 |
136 |
0 |
0 |
T3 |
293261 |
50 |
0 |
0 |
T4 |
7472 |
16 |
0 |
0 |
T11 |
0 |
265 |
0 |
0 |
T12 |
0 |
259 |
0 |
0 |
T13 |
0 |
20 |
0 |
0 |
T14 |
0 |
40 |
0 |
0 |
T15 |
0 |
38 |
0 |
0 |
T18 |
1536 |
0 |
0 |
0 |
T19 |
2058 |
0 |
0 |
0 |
T20 |
1375 |
0 |
0 |
0 |
T21 |
1243 |
0 |
0 |
0 |
T22 |
2170 |
0 |
0 |
0 |
T23 |
673 |
0 |
0 |
0 |
T33 |
0 |
14 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 31 | 3 | 3 | 100.00 |
CONT_ASSIGN | 49 | 0 | 0 | |
CONT_ASSIGN | 52 | 0 | 0 | |
ALWAYS | 55 | 0 | 0 | |
ALWAYS | 89 | 3 | 3 | 100.00 |
CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
31 |
1 |
1 |
32 |
1 |
1 |
34 |
1 |
1 |
49 |
|
unreachable |
52 |
|
unreachable |
55 |
|
unreachable |
56 |
|
unreachable |
58 |
|
unreachable |
89 |
1 |
1 |
90 |
1 |
1 |
92 |
1 |
1 |
97 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 34
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T5,T6,T7 |
0 | 1 | Covered | T1,T2,T4 |
1 | 0 | Covered | T1,T2,T4 |
1 | 1 | Covered | T1,T2,T4 |
LINE 97
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T5,T6,T7 |
0 | 1 | Covered | T1,T2,T4 |
1 | 0 | Covered | T1,T2,T4 |
1 | 1 | Covered | T1,T2,T4 |
Branch Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
31 |
2 |
2 |
100.00 |
IF |
89 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 31 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T5,T6,T7 |
0 |
Covered |
T5,T6,T7 |
LineNo. Expression
-1-: 89 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T5,T6,T7 |
0 |
Covered |
T5,T6,T7 |
Assert Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
73828701 |
20077 |
0 |
0 |
T1 |
29517 |
20 |
0 |
0 |
T2 |
389922 |
136 |
0 |
0 |
T3 |
293261 |
50 |
0 |
0 |
T4 |
7472 |
16 |
0 |
0 |
T11 |
0 |
265 |
0 |
0 |
T12 |
0 |
259 |
0 |
0 |
T13 |
0 |
20 |
0 |
0 |
T14 |
0 |
40 |
0 |
0 |
T15 |
0 |
38 |
0 |
0 |
T18 |
1536 |
0 |
0 |
0 |
T19 |
2058 |
0 |
0 |
0 |
T20 |
1375 |
0 |
0 |
0 |
T21 |
1243 |
0 |
0 |
0 |
T22 |
2170 |
0 |
0 |
0 |
T23 |
673 |
0 |
0 |
0 |
T33 |
0 |
14 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
55594684 |
20082 |
0 |
0 |
T1 |
29511 |
20 |
0 |
0 |
T2 |
191885 |
136 |
0 |
0 |
T3 |
71085 |
50 |
0 |
0 |
T4 |
5118 |
16 |
0 |
0 |
T11 |
0 |
265 |
0 |
0 |
T12 |
0 |
259 |
0 |
0 |
T13 |
0 |
20 |
0 |
0 |
T14 |
0 |
40 |
0 |
0 |
T15 |
0 |
38 |
0 |
0 |
T18 |
2548 |
0 |
0 |
0 |
T19 |
538 |
0 |
0 |
0 |
T20 |
1287 |
0 |
0 |
0 |
T21 |
1351 |
0 |
0 |
0 |
T22 |
579 |
0 |
0 |
0 |
T23 |
634 |
0 |
0 |
0 |
T33 |
0 |
14 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_en_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 31 | 3 | 3 | 100.00 |
CONT_ASSIGN | 49 | 0 | 0 | |
CONT_ASSIGN | 52 | 0 | 0 | |
ALWAYS | 55 | 0 | 0 | |
ALWAYS | 89 | 3 | 3 | 100.00 |
CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
31 |
1 |
1 |
32 |
1 |
1 |
34 |
1 |
1 |
49 |
|
unreachable |
52 |
|
unreachable |
55 |
|
unreachable |
56 |
|
unreachable |
58 |
|
unreachable |
89 |
1 |
1 |
90 |
1 |
1 |
92 |
1 |
1 |
97 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_en_cdc.u_src_to_dst_req
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 34
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T5,T6,T7 |
0 | 1 | Covered | T1,T2,T4 |
1 | 0 | Covered | T1,T2,T4 |
1 | 1 | Covered | T1,T2,T4 |
LINE 97
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T5,T6,T7 |
0 | 1 | Covered | T1,T2,T4 |
1 | 0 | Covered | T1,T2,T4 |
1 | 1 | Covered | T1,T2,T4 |
Branch Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_en_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
31 |
2 |
2 |
100.00 |
IF |
89 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 31 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T5,T6,T7 |
0 |
Covered |
T5,T6,T7 |
LineNo. Expression
-1-: 89 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T5,T6,T7 |
0 |
Covered |
T5,T6,T7 |
Assert Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_en_cdc.u_src_to_dst_req
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
239150230 |
14511 |
0 |
0 |
T1 |
122993 |
20 |
0 |
0 |
T2 |
812325 |
136 |
0 |
0 |
T3 |
296222 |
50 |
0 |
0 |
T4 |
29894 |
8 |
0 |
0 |
T11 |
0 |
259 |
0 |
0 |
T12 |
0 |
254 |
0 |
0 |
T13 |
0 |
20 |
0 |
0 |
T14 |
0 |
40 |
0 |
0 |
T15 |
0 |
38 |
0 |
0 |
T18 |
9604 |
0 |
0 |
0 |
T19 |
2079 |
0 |
0 |
0 |
T20 |
5503 |
0 |
0 |
0 |
T21 |
4975 |
0 |
0 |
0 |
T22 |
2170 |
0 |
0 |
0 |
T23 |
2697 |
0 |
0 |
0 |
T33 |
0 |
14 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
73828701 |
14511 |
0 |
0 |
T1 |
29517 |
20 |
0 |
0 |
T2 |
389922 |
136 |
0 |
0 |
T3 |
293261 |
50 |
0 |
0 |
T4 |
7472 |
8 |
0 |
0 |
T11 |
0 |
259 |
0 |
0 |
T12 |
0 |
254 |
0 |
0 |
T13 |
0 |
20 |
0 |
0 |
T14 |
0 |
40 |
0 |
0 |
T15 |
0 |
38 |
0 |
0 |
T18 |
1536 |
0 |
0 |
0 |
T19 |
2058 |
0 |
0 |
0 |
T20 |
1375 |
0 |
0 |
0 |
T21 |
1243 |
0 |
0 |
0 |
T22 |
2170 |
0 |
0 |
0 |
T23 |
673 |
0 |
0 |
0 |
T33 |
0 |
14 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 31 | 3 | 3 | 100.00 |
CONT_ASSIGN | 49 | 0 | 0 | |
CONT_ASSIGN | 52 | 0 | 0 | |
ALWAYS | 55 | 0 | 0 | |
ALWAYS | 89 | 3 | 3 | 100.00 |
CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
31 |
1 |
1 |
32 |
1 |
1 |
34 |
1 |
1 |
49 |
|
unreachable |
52 |
|
unreachable |
55 |
|
unreachable |
56 |
|
unreachable |
58 |
|
unreachable |
89 |
1 |
1 |
90 |
1 |
1 |
92 |
1 |
1 |
97 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_cdc.u_src_to_dst_req
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 34
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T5,T6,T7 |
0 | 1 | Covered | T1,T2,T4 |
1 | 0 | Covered | T1,T2,T4 |
1 | 1 | Covered | T1,T2,T4 |
LINE 97
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T5,T6,T7 |
0 | 1 | Covered | T1,T2,T4 |
1 | 0 | Covered | T1,T2,T4 |
1 | 1 | Covered | T1,T2,T4 |
Branch Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
31 |
2 |
2 |
100.00 |
IF |
89 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 31 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T5,T6,T7 |
0 |
Covered |
T5,T6,T7 |
LineNo. Expression
-1-: 89 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T5,T6,T7 |
0 |
Covered |
T5,T6,T7 |
Assert Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_cdc.u_src_to_dst_req
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
239150230 |
20042 |
0 |
0 |
T1 |
122993 |
20 |
0 |
0 |
T2 |
812325 |
136 |
0 |
0 |
T3 |
296222 |
50 |
0 |
0 |
T4 |
29894 |
16 |
0 |
0 |
T11 |
0 |
265 |
0 |
0 |
T12 |
0 |
259 |
0 |
0 |
T13 |
0 |
20 |
0 |
0 |
T14 |
0 |
40 |
0 |
0 |
T15 |
0 |
38 |
0 |
0 |
T18 |
9604 |
0 |
0 |
0 |
T19 |
2079 |
0 |
0 |
0 |
T20 |
5503 |
0 |
0 |
0 |
T21 |
4975 |
0 |
0 |
0 |
T22 |
2170 |
0 |
0 |
0 |
T23 |
2697 |
0 |
0 |
0 |
T33 |
0 |
14 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
73828701 |
20059 |
0 |
0 |
T1 |
29517 |
20 |
0 |
0 |
T2 |
389922 |
136 |
0 |
0 |
T3 |
293261 |
50 |
0 |
0 |
T4 |
7472 |
16 |
0 |
0 |
T11 |
0 |
265 |
0 |
0 |
T12 |
0 |
259 |
0 |
0 |
T13 |
0 |
20 |
0 |
0 |
T14 |
0 |
40 |
0 |
0 |
T15 |
0 |
38 |
0 |
0 |
T18 |
1536 |
0 |
0 |
0 |
T19 |
2058 |
0 |
0 |
0 |
T20 |
1375 |
0 |
0 |
0 |
T21 |
1243 |
0 |
0 |
0 |
T22 |
2170 |
0 |
0 |
0 |
T23 |
673 |
0 |
0 |
0 |
T33 |
0 |
14 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 31 | 3 | 3 | 100.00 |
CONT_ASSIGN | 49 | 0 | 0 | |
CONT_ASSIGN | 52 | 0 | 0 | |
ALWAYS | 55 | 0 | 0 | |
ALWAYS | 89 | 3 | 3 | 100.00 |
CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
31 |
1 |
1 |
32 |
1 |
1 |
34 |
1 |
1 |
49 |
|
unreachable |
52 |
|
unreachable |
55 |
|
unreachable |
56 |
|
unreachable |
58 |
|
unreachable |
89 |
1 |
1 |
90 |
1 |
1 |
92 |
1 |
1 |
97 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 34
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T5,T6,T7 |
0 | 1 | Covered | T1,T2,T4 |
1 | 0 | Covered | T1,T2,T4 |
1 | 1 | Covered | T1,T2,T4 |
LINE 97
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T5,T6,T7 |
0 | 1 | Covered | T1,T2,T4 |
1 | 0 | Covered | T1,T2,T4 |
1 | 1 | Covered | T1,T2,T4 |
Branch Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
31 |
2 |
2 |
100.00 |
IF |
89 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 31 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T5,T6,T7 |
0 |
Covered |
T5,T6,T7 |
LineNo. Expression
-1-: 89 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T5,T6,T7 |
0 |
Covered |
T5,T6,T7 |
Assert Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
73828701 |
20034 |
0 |
0 |
T1 |
29517 |
20 |
0 |
0 |
T2 |
389922 |
136 |
0 |
0 |
T3 |
293261 |
50 |
0 |
0 |
T4 |
7472 |
16 |
0 |
0 |
T11 |
0 |
265 |
0 |
0 |
T12 |
0 |
259 |
0 |
0 |
T13 |
0 |
20 |
0 |
0 |
T14 |
0 |
40 |
0 |
0 |
T15 |
0 |
38 |
0 |
0 |
T18 |
1536 |
0 |
0 |
0 |
T19 |
2058 |
0 |
0 |
0 |
T20 |
1375 |
0 |
0 |
0 |
T21 |
1243 |
0 |
0 |
0 |
T22 |
2170 |
0 |
0 |
0 |
T23 |
673 |
0 |
0 |
0 |
T33 |
0 |
14 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
239150230 |
20048 |
0 |
0 |
T1 |
122993 |
20 |
0 |
0 |
T2 |
812325 |
136 |
0 |
0 |
T3 |
296222 |
50 |
0 |
0 |
T4 |
29894 |
16 |
0 |
0 |
T11 |
0 |
265 |
0 |
0 |
T12 |
0 |
259 |
0 |
0 |
T13 |
0 |
20 |
0 |
0 |
T14 |
0 |
40 |
0 |
0 |
T15 |
0 |
38 |
0 |
0 |
T18 |
9604 |
0 |
0 |
0 |
T19 |
2079 |
0 |
0 |
0 |
T20 |
5503 |
0 |
0 |
0 |
T21 |
4975 |
0 |
0 |
0 |
T22 |
2170 |
0 |
0 |
0 |
T23 |
2697 |
0 |
0 |
0 |
T33 |
0 |
14 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_en_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 31 | 3 | 3 | 100.00 |
CONT_ASSIGN | 49 | 0 | 0 | |
CONT_ASSIGN | 52 | 0 | 0 | |
ALWAYS | 55 | 0 | 0 | |
ALWAYS | 89 | 3 | 3 | 100.00 |
CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
31 |
1 |
1 |
32 |
1 |
1 |
34 |
1 |
1 |
49 |
|
unreachable |
52 |
|
unreachable |
55 |
|
unreachable |
56 |
|
unreachable |
58 |
|
unreachable |
89 |
1 |
1 |
90 |
1 |
1 |
92 |
1 |
1 |
97 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_en_cdc.u_src_to_dst_req
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 34
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T5,T6,T7 |
0 | 1 | Covered | T1,T2,T4 |
1 | 0 | Covered | T1,T2,T4 |
1 | 1 | Covered | T1,T2,T4 |
LINE 97
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T5,T6,T7 |
0 | 1 | Covered | T1,T2,T4 |
1 | 0 | Covered | T1,T2,T4 |
1 | 1 | Covered | T1,T2,T4 |
Branch Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_en_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
31 |
2 |
2 |
100.00 |
IF |
89 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 31 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T5,T6,T7 |
0 |
Covered |
T5,T6,T7 |
LineNo. Expression
-1-: 89 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T5,T6,T7 |
0 |
Covered |
T5,T6,T7 |
Assert Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_en_cdc.u_src_to_dst_req
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
114657872 |
14057 |
0 |
0 |
T1 |
59037 |
20 |
0 |
0 |
T2 |
384162 |
136 |
0 |
0 |
T3 |
142189 |
50 |
0 |
0 |
T4 |
14349 |
4 |
0 |
0 |
T11 |
0 |
259 |
0 |
0 |
T12 |
0 |
254 |
0 |
0 |
T13 |
0 |
20 |
0 |
0 |
T14 |
0 |
40 |
0 |
0 |
T15 |
0 |
38 |
0 |
0 |
T18 |
4609 |
0 |
0 |
0 |
T19 |
997 |
0 |
0 |
0 |
T20 |
2641 |
0 |
0 |
0 |
T21 |
2388 |
0 |
0 |
0 |
T22 |
1042 |
0 |
0 |
0 |
T23 |
1295 |
0 |
0 |
0 |
T33 |
0 |
14 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
73828701 |
14511 |
0 |
0 |
T1 |
29517 |
20 |
0 |
0 |
T2 |
389922 |
136 |
0 |
0 |
T3 |
293261 |
50 |
0 |
0 |
T4 |
7472 |
8 |
0 |
0 |
T11 |
0 |
259 |
0 |
0 |
T12 |
0 |
254 |
0 |
0 |
T13 |
0 |
20 |
0 |
0 |
T14 |
0 |
40 |
0 |
0 |
T15 |
0 |
38 |
0 |
0 |
T18 |
1536 |
0 |
0 |
0 |
T19 |
2058 |
0 |
0 |
0 |
T20 |
1375 |
0 |
0 |
0 |
T21 |
1243 |
0 |
0 |
0 |
T22 |
2170 |
0 |
0 |
0 |
T23 |
673 |
0 |
0 |
0 |
T33 |
0 |
14 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 31 | 3 | 3 | 100.00 |
CONT_ASSIGN | 49 | 0 | 0 | |
CONT_ASSIGN | 52 | 0 | 0 | |
ALWAYS | 55 | 0 | 0 | |
ALWAYS | 89 | 3 | 3 | 100.00 |
CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
31 |
1 |
1 |
32 |
1 |
1 |
34 |
1 |
1 |
49 |
|
unreachable |
52 |
|
unreachable |
55 |
|
unreachable |
56 |
|
unreachable |
58 |
|
unreachable |
89 |
1 |
1 |
90 |
1 |
1 |
92 |
1 |
1 |
97 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_cdc.u_src_to_dst_req
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 34
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T5,T6,T7 |
0 | 1 | Covered | T1,T2,T4 |
1 | 0 | Covered | T1,T2,T4 |
1 | 1 | Covered | T1,T2,T4 |
LINE 97
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T5,T6,T7 |
0 | 1 | Covered | T1,T2,T4 |
1 | 0 | Covered | T1,T2,T4 |
1 | 1 | Covered | T1,T2,T4 |
Branch Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_cdc.u_src_to_dst_req
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
31 |
2 |
2 |
100.00 |
IF |
89 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 31 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T5,T6,T7 |
0 |
Covered |
T5,T6,T7 |
LineNo. Expression
-1-: 89 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T5,T6,T7 |
0 |
Covered |
T5,T6,T7 |
Assert Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_cdc.u_src_to_dst_req
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
114657872 |
19962 |
0 |
0 |
T1 |
59037 |
20 |
0 |
0 |
T2 |
384162 |
136 |
0 |
0 |
T3 |
142189 |
50 |
0 |
0 |
T4 |
14349 |
16 |
0 |
0 |
T11 |
0 |
265 |
0 |
0 |
T12 |
0 |
259 |
0 |
0 |
T13 |
0 |
20 |
0 |
0 |
T14 |
0 |
40 |
0 |
0 |
T15 |
0 |
38 |
0 |
0 |
T18 |
4609 |
0 |
0 |
0 |
T19 |
997 |
0 |
0 |
0 |
T20 |
2641 |
0 |
0 |
0 |
T21 |
2388 |
0 |
0 |
0 |
T22 |
1042 |
0 |
0 |
0 |
T23 |
1295 |
0 |
0 |
0 |
T33 |
0 |
14 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
73828701 |
20194 |
0 |
0 |
T1 |
29517 |
20 |
0 |
0 |
T2 |
389922 |
136 |
0 |
0 |
T3 |
293261 |
50 |
0 |
0 |
T4 |
7472 |
16 |
0 |
0 |
T11 |
0 |
265 |
0 |
0 |
T12 |
0 |
259 |
0 |
0 |
T13 |
0 |
20 |
0 |
0 |
T14 |
0 |
40 |
0 |
0 |
T15 |
0 |
38 |
0 |
0 |
T18 |
1536 |
0 |
0 |
0 |
T19 |
2058 |
0 |
0 |
0 |
T20 |
1375 |
0 |
0 |
0 |
T21 |
1243 |
0 |
0 |
0 |
T22 |
2170 |
0 |
0 |
0 |
T23 |
673 |
0 |
0 |
0 |
T33 |
0 |
14 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 31 | 3 | 3 | 100.00 |
CONT_ASSIGN | 49 | 0 | 0 | |
CONT_ASSIGN | 52 | 0 | 0 | |
ALWAYS | 55 | 0 | 0 | |
ALWAYS | 89 | 3 | 3 | 100.00 |
CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
31 |
1 |
1 |
32 |
1 |
1 |
34 |
1 |
1 |
49 |
|
unreachable |
52 |
|
unreachable |
55 |
|
unreachable |
56 |
|
unreachable |
58 |
|
unreachable |
89 |
1 |
1 |
90 |
1 |
1 |
92 |
1 |
1 |
97 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 34
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T5,T6,T7 |
0 | 1 | Covered | T1,T2,T4 |
1 | 0 | Covered | T1,T2,T4 |
1 | 1 | Covered | T1,T2,T4 |
LINE 97
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T5,T6,T7 |
0 | 1 | Covered | T1,T2,T4 |
1 | 0 | Covered | T1,T2,T4 |
1 | 1 | Covered | T1,T2,T4 |
Branch Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
31 |
2 |
2 |
100.00 |
IF |
89 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 31 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T5,T6,T7 |
0 |
Covered |
T5,T6,T7 |
LineNo. Expression
-1-: 89 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T5,T6,T7 |
0 |
Covered |
T5,T6,T7 |
Assert Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
73828701 |
19794 |
0 |
0 |
T1 |
29517 |
20 |
0 |
0 |
T2 |
389922 |
136 |
0 |
0 |
T3 |
293261 |
50 |
0 |
0 |
T4 |
7472 |
15 |
0 |
0 |
T11 |
0 |
265 |
0 |
0 |
T12 |
0 |
259 |
0 |
0 |
T13 |
0 |
20 |
0 |
0 |
T14 |
0 |
40 |
0 |
0 |
T15 |
0 |
38 |
0 |
0 |
T18 |
1536 |
0 |
0 |
0 |
T19 |
2058 |
0 |
0 |
0 |
T20 |
1375 |
0 |
0 |
0 |
T21 |
1243 |
0 |
0 |
0 |
T22 |
2170 |
0 |
0 |
0 |
T23 |
673 |
0 |
0 |
0 |
T33 |
0 |
14 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
114657872 |
19999 |
0 |
0 |
T1 |
59037 |
20 |
0 |
0 |
T2 |
384162 |
136 |
0 |
0 |
T3 |
142189 |
50 |
0 |
0 |
T4 |
14349 |
16 |
0 |
0 |
T11 |
0 |
265 |
0 |
0 |
T12 |
0 |
259 |
0 |
0 |
T13 |
0 |
20 |
0 |
0 |
T14 |
0 |
40 |
0 |
0 |
T15 |
0 |
38 |
0 |
0 |
T18 |
4609 |
0 |
0 |
0 |
T19 |
997 |
0 |
0 |
0 |
T20 |
2641 |
0 |
0 |
0 |
T21 |
2388 |
0 |
0 |
0 |
T22 |
1042 |
0 |
0 |
0 |
T23 |
1295 |
0 |
0 |
0 |
T33 |
0 |
14 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_hi_err_update_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 31 | 3 | 3 | 100.00 |
CONT_ASSIGN | 49 | 0 | 0 | |
CONT_ASSIGN | 52 | 0 | 0 | |
ALWAYS | 55 | 0 | 0 | |
ALWAYS | 89 | 3 | 3 | 100.00 |
CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
31 |
1 |
1 |
32 |
1 |
1 |
34 |
1 |
1 |
49 |
|
unreachable |
52 |
|
unreachable |
55 |
|
unreachable |
56 |
|
unreachable |
58 |
|
unreachable |
89 |
1 |
1 |
90 |
1 |
1 |
92 |
1 |
1 |
97 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_hi_err_update_sync
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 34
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T5,T6,T7 |
0 | 1 | Covered | T56,T57,T59 |
1 | 0 | Covered | T56,T57,T59 |
1 | 1 | Covered | T123,T124,T125 |
LINE 97
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T5,T6,T7 |
0 | 1 | Covered | T56,T57,T59 |
1 | 0 | Covered | T123,T124,T125 |
1 | 1 | Covered | T56,T57,T59 |
Branch Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_hi_err_update_sync
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
31 |
2 |
2 |
100.00 |
IF |
89 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 31 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T5,T6,T7 |
0 |
Covered |
T5,T6,T7 |
LineNo. Expression
-1-: 89 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T5,T6,T7 |
0 |
Covered |
T5,T6,T7 |
Assert Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_hi_err_update_sync
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
73828701 |
27 |
0 |
0 |
T56 |
8314 |
1 |
0 |
0 |
T57 |
8585 |
2 |
0 |
0 |
T59 |
4826 |
1 |
0 |
0 |
T60 |
4771 |
1 |
0 |
0 |
T119 |
6327 |
1 |
0 |
0 |
T120 |
8022 |
2 |
0 |
0 |
T122 |
5009 |
1 |
0 |
0 |
T126 |
10644 |
2 |
0 |
0 |
T127 |
3814 |
1 |
0 |
0 |
T128 |
4524 |
1 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
223910640 |
27 |
0 |
0 |
T56 |
13760 |
1 |
0 |
0 |
T57 |
8324 |
2 |
0 |
0 |
T59 |
19306 |
1 |
0 |
0 |
T60 |
26946 |
1 |
0 |
0 |
T119 |
24295 |
1 |
0 |
0 |
T120 |
16043 |
2 |
0 |
0 |
T122 |
4809 |
1 |
0 |
0 |
T126 |
20853 |
2 |
0 |
0 |
T127 |
33283 |
1 |
0 |
0 |
T128 |
17372 |
1 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_lo_err_update_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 31 | 3 | 3 | 100.00 |
CONT_ASSIGN | 49 | 0 | 0 | |
CONT_ASSIGN | 52 | 0 | 0 | |
ALWAYS | 55 | 0 | 0 | |
ALWAYS | 89 | 3 | 3 | 100.00 |
CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
31 |
1 |
1 |
32 |
1 |
1 |
34 |
1 |
1 |
49 |
|
unreachable |
52 |
|
unreachable |
55 |
|
unreachable |
56 |
|
unreachable |
58 |
|
unreachable |
89 |
1 |
1 |
90 |
1 |
1 |
92 |
1 |
1 |
97 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_lo_err_update_sync
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 34
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T5,T6,T7 |
0 | 1 | Covered | T56,T57,T61 |
1 | 0 | Covered | T56,T57,T61 |
1 | 1 | Covered | T57,T61,T59 |
LINE 97
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T5,T6,T7 |
0 | 1 | Covered | T56,T57,T61 |
1 | 0 | Covered | T57,T61,T59 |
1 | 1 | Covered | T56,T57,T61 |
Branch Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_lo_err_update_sync
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
31 |
2 |
2 |
100.00 |
IF |
89 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 31 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T5,T6,T7 |
0 |
Covered |
T5,T6,T7 |
LineNo. Expression
-1-: 89 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T5,T6,T7 |
0 |
Covered |
T5,T6,T7 |
Assert Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_lo_err_update_sync
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
73828701 |
30 |
0 |
0 |
T56 |
8314 |
1 |
0 |
0 |
T57 |
8585 |
2 |
0 |
0 |
T59 |
4826 |
4 |
0 |
0 |
T60 |
4771 |
1 |
0 |
0 |
T61 |
9336 |
3 |
0 |
0 |
T65 |
16822 |
1 |
0 |
0 |
T120 |
8022 |
2 |
0 |
0 |
T122 |
5009 |
2 |
0 |
0 |
T126 |
10644 |
1 |
0 |
0 |
T127 |
3814 |
1 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
223910640 |
30 |
0 |
0 |
T56 |
13760 |
1 |
0 |
0 |
T57 |
8324 |
2 |
0 |
0 |
T59 |
19306 |
4 |
0 |
0 |
T60 |
26946 |
1 |
0 |
0 |
T61 |
8962 |
3 |
0 |
0 |
T65 |
16822 |
1 |
0 |
0 |
T120 |
16043 |
2 |
0 |
0 |
T122 |
4809 |
2 |
0 |
0 |
T126 |
20853 |
1 |
0 |
0 |
T127 |
33283 |
1 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_hi_err_update_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 31 | 3 | 3 | 100.00 |
CONT_ASSIGN | 49 | 0 | 0 | |
CONT_ASSIGN | 52 | 0 | 0 | |
ALWAYS | 55 | 0 | 0 | |
ALWAYS | 89 | 3 | 3 | 100.00 |
CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
31 |
1 |
1 |
32 |
1 |
1 |
34 |
1 |
1 |
49 |
|
unreachable |
52 |
|
unreachable |
55 |
|
unreachable |
56 |
|
unreachable |
58 |
|
unreachable |
89 |
1 |
1 |
90 |
1 |
1 |
92 |
1 |
1 |
97 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_hi_err_update_sync
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 34
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T5,T6,T7 |
0 | 1 | Covered | T58,T62,T63 |
1 | 0 | Covered | T58,T62,T63 |
1 | 1 | Covered | T58,T129,T124 |
LINE 97
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T5,T6,T7 |
0 | 1 | Covered | T58,T62,T63 |
1 | 0 | Covered | T58,T129,T124 |
1 | 1 | Covered | T58,T62,T63 |
Branch Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_hi_err_update_sync
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
31 |
2 |
2 |
100.00 |
IF |
89 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 31 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T5,T6,T7 |
0 |
Covered |
T5,T6,T7 |
LineNo. Expression
-1-: 89 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T5,T6,T7 |
0 |
Covered |
T5,T6,T7 |
Assert Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_hi_err_update_sync
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
73828701 |
31 |
0 |
0 |
T58 |
7079 |
2 |
0 |
0 |
T59 |
4826 |
1 |
0 |
0 |
T62 |
9216 |
1 |
0 |
0 |
T63 |
6812 |
1 |
0 |
0 |
T64 |
5616 |
1 |
0 |
0 |
T117 |
4977 |
1 |
0 |
0 |
T118 |
10424 |
1 |
0 |
0 |
T119 |
6327 |
1 |
0 |
0 |
T120 |
8022 |
1 |
0 |
0 |
T121 |
5578 |
1 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
111190200 |
31 |
0 |
0 |
T58 |
3258 |
2 |
0 |
0 |
T59 |
8901 |
1 |
0 |
0 |
T62 |
3974 |
1 |
0 |
0 |
T63 |
2898 |
1 |
0 |
0 |
T64 |
10274 |
1 |
0 |
0 |
T117 |
7094 |
1 |
0 |
0 |
T118 |
9866 |
1 |
0 |
0 |
T119 |
11391 |
1 |
0 |
0 |
T120 |
7163 |
1 |
0 |
0 |
T121 |
2304 |
1 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_lo_err_update_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 31 | 3 | 3 | 100.00 |
CONT_ASSIGN | 49 | 0 | 0 | |
CONT_ASSIGN | 52 | 0 | 0 | |
ALWAYS | 55 | 0 | 0 | |
ALWAYS | 89 | 3 | 3 | 100.00 |
CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
31 |
1 |
1 |
32 |
1 |
1 |
34 |
1 |
1 |
49 |
|
unreachable |
52 |
|
unreachable |
55 |
|
unreachable |
56 |
|
unreachable |
58 |
|
unreachable |
89 |
1 |
1 |
90 |
1 |
1 |
92 |
1 |
1 |
97 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_lo_err_update_sync
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 34
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T5,T6,T7 |
0 | 1 | Covered | T58,T62,T64 |
1 | 0 | Covered | T58,T62,T64 |
1 | 1 | Covered | T58,T59,T122 |
LINE 97
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T5,T6,T7 |
0 | 1 | Covered | T58,T62,T64 |
1 | 0 | Covered | T58,T59,T122 |
1 | 1 | Covered | T58,T62,T64 |
Branch Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_lo_err_update_sync
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
31 |
2 |
2 |
100.00 |
IF |
89 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 31 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T5,T6,T7 |
0 |
Covered |
T5,T6,T7 |
LineNo. Expression
-1-: 89 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T5,T6,T7 |
0 |
Covered |
T5,T6,T7 |
Assert Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_lo_err_update_sync
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
73828701 |
31 |
0 |
0 |
T58 |
7079 |
2 |
0 |
0 |
T59 |
4826 |
3 |
0 |
0 |
T62 |
9216 |
2 |
0 |
0 |
T64 |
5616 |
1 |
0 |
0 |
T117 |
4977 |
1 |
0 |
0 |
T119 |
6327 |
1 |
0 |
0 |
T121 |
5578 |
1 |
0 |
0 |
T122 |
5009 |
2 |
0 |
0 |
T130 |
10873 |
1 |
0 |
0 |
T131 |
8584 |
1 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
111190200 |
31 |
0 |
0 |
T58 |
3258 |
2 |
0 |
0 |
T59 |
8901 |
3 |
0 |
0 |
T62 |
3974 |
2 |
0 |
0 |
T64 |
10274 |
1 |
0 |
0 |
T117 |
7094 |
1 |
0 |
0 |
T119 |
11391 |
1 |
0 |
0 |
T121 |
2304 |
1 |
0 |
0 |
T122 |
2058 |
2 |
0 |
0 |
T130 |
21910 |
1 |
0 |
0 |
T131 |
3990 |
1 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_hi_err_update_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 31 | 3 | 3 | 100.00 |
CONT_ASSIGN | 49 | 0 | 0 | |
CONT_ASSIGN | 52 | 0 | 0 | |
ALWAYS | 55 | 0 | 0 | |
ALWAYS | 89 | 3 | 3 | 100.00 |
CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
31 |
1 |
1 |
32 |
1 |
1 |
34 |
1 |
1 |
49 |
|
unreachable |
52 |
|
unreachable |
55 |
|
unreachable |
56 |
|
unreachable |
58 |
|
unreachable |
89 |
1 |
1 |
90 |
1 |
1 |
92 |
1 |
1 |
97 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_hi_err_update_sync
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 34
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T5,T6,T7 |
0 | 1 | Covered | T58,T65,T63 |
1 | 0 | Covered | T58,T65,T63 |
1 | 1 | Covered | T63,T132,T133 |
LINE 97
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T5,T6,T7 |
0 | 1 | Covered | T58,T65,T63 |
1 | 0 | Covered | T63,T132,T133 |
1 | 1 | Covered | T58,T65,T63 |
Branch Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_hi_err_update_sync
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
31 |
2 |
2 |
100.00 |
IF |
89 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 31 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T5,T6,T7 |
0 |
Covered |
T5,T6,T7 |
LineNo. Expression
-1-: 89 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T5,T6,T7 |
0 |
Covered |
T5,T6,T7 |
Assert Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_hi_err_update_sync
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
73828701 |
31 |
0 |
0 |
T58 |
7079 |
2 |
0 |
0 |
T63 |
6812 |
2 |
0 |
0 |
T64 |
5616 |
1 |
0 |
0 |
T65 |
16822 |
1 |
0 |
0 |
T66 |
15216 |
1 |
0 |
0 |
T119 |
6327 |
1 |
0 |
0 |
T120 |
8022 |
2 |
0 |
0 |
T122 |
5009 |
1 |
0 |
0 |
T126 |
10644 |
1 |
0 |
0 |
T134 |
7565 |
1 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
55594684 |
31 |
0 |
0 |
T58 |
1629 |
2 |
0 |
0 |
T63 |
1450 |
2 |
0 |
0 |
T64 |
5137 |
1 |
0 |
0 |
T65 |
3763 |
1 |
0 |
0 |
T66 |
3413 |
1 |
0 |
0 |
T119 |
5696 |
1 |
0 |
0 |
T120 |
3583 |
2 |
0 |
0 |
T122 |
1028 |
1 |
0 |
0 |
T126 |
4901 |
1 |
0 |
0 |
T134 |
3408 |
1 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_lo_err_update_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 31 | 3 | 3 | 100.00 |
CONT_ASSIGN | 49 | 0 | 0 | |
CONT_ASSIGN | 52 | 0 | 0 | |
ALWAYS | 55 | 0 | 0 | |
ALWAYS | 89 | 3 | 3 | 100.00 |
CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
31 |
1 |
1 |
32 |
1 |
1 |
34 |
1 |
1 |
49 |
|
unreachable |
52 |
|
unreachable |
55 |
|
unreachable |
56 |
|
unreachable |
58 |
|
unreachable |
89 |
1 |
1 |
90 |
1 |
1 |
92 |
1 |
1 |
97 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_lo_err_update_sync
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 34
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T5,T6,T7 |
0 | 1 | Covered | T57,T58,T65 |
1 | 0 | Covered | T57,T58,T65 |
1 | 1 | Covered | T58,T123 |
LINE 97
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T5,T6,T7 |
0 | 1 | Covered | T57,T58,T65 |
1 | 0 | Covered | T58,T123 |
1 | 1 | Covered | T57,T58,T65 |
Branch Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_lo_err_update_sync
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
31 |
2 |
2 |
100.00 |
IF |
89 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 31 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T5,T6,T7 |
0 |
Covered |
T5,T6,T7 |
LineNo. Expression
-1-: 89 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T5,T6,T7 |
0 |
Covered |
T5,T6,T7 |
Assert Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_lo_err_update_sync
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
73828701 |
31 |
0 |
0 |
T57 |
8585 |
1 |
0 |
0 |
T58 |
7079 |
3 |
0 |
0 |
T60 |
4771 |
1 |
0 |
0 |
T63 |
6812 |
1 |
0 |
0 |
T64 |
5616 |
1 |
0 |
0 |
T65 |
16822 |
1 |
0 |
0 |
T66 |
15216 |
1 |
0 |
0 |
T122 |
5009 |
1 |
0 |
0 |
T128 |
4524 |
1 |
0 |
0 |
T134 |
7565 |
1 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
55594684 |
31 |
0 |
0 |
T57 |
1731 |
1 |
0 |
0 |
T58 |
1629 |
3 |
0 |
0 |
T60 |
6479 |
1 |
0 |
0 |
T63 |
1450 |
1 |
0 |
0 |
T64 |
5137 |
1 |
0 |
0 |
T65 |
3763 |
1 |
0 |
0 |
T66 |
3413 |
1 |
0 |
0 |
T122 |
1028 |
1 |
0 |
0 |
T128 |
4106 |
1 |
0 |
0 |
T134 |
3408 |
1 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_hi_err_update_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 31 | 3 | 3 | 100.00 |
CONT_ASSIGN | 49 | 0 | 0 | |
CONT_ASSIGN | 52 | 0 | 0 | |
ALWAYS | 55 | 0 | 0 | |
ALWAYS | 89 | 3 | 3 | 100.00 |
CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
31 |
1 |
1 |
32 |
1 |
1 |
34 |
1 |
1 |
49 |
|
unreachable |
52 |
|
unreachable |
55 |
|
unreachable |
56 |
|
unreachable |
58 |
|
unreachable |
89 |
1 |
1 |
90 |
1 |
1 |
92 |
1 |
1 |
97 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_hi_err_update_sync
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 34
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T5,T6,T7 |
0 | 1 | Covered | T57,T59,T60 |
1 | 0 | Covered | T57,T59,T60 |
1 | 1 | Covered | T118,T135 |
LINE 97
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T5,T6,T7 |
0 | 1 | Covered | T57,T59,T60 |
1 | 0 | Covered | T118,T135 |
1 | 1 | Covered | T57,T59,T60 |
Branch Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_hi_err_update_sync
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
31 |
2 |
2 |
100.00 |
IF |
89 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 31 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T5,T6,T7 |
0 |
Covered |
T5,T6,T7 |
LineNo. Expression
-1-: 89 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T5,T6,T7 |
0 |
Covered |
T5,T6,T7 |
Assert Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_hi_err_update_sync
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
73828701 |
31 |
0 |
0 |
T57 |
8585 |
2 |
0 |
0 |
T59 |
4826 |
2 |
0 |
0 |
T60 |
4771 |
1 |
0 |
0 |
T118 |
10424 |
2 |
0 |
0 |
T120 |
8022 |
1 |
0 |
0 |
T121 |
5578 |
1 |
0 |
0 |
T126 |
10644 |
2 |
0 |
0 |
T127 |
3814 |
1 |
0 |
0 |
T134 |
7565 |
1 |
0 |
0 |
T136 |
6524 |
2 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
239150230 |
31 |
0 |
0 |
T57 |
8672 |
2 |
0 |
0 |
T59 |
20112 |
2 |
0 |
0 |
T60 |
28071 |
1 |
0 |
0 |
T118 |
21717 |
2 |
0 |
0 |
T120 |
16713 |
1 |
0 |
0 |
T121 |
5578 |
1 |
0 |
0 |
T126 |
21723 |
2 |
0 |
0 |
T127 |
34672 |
1 |
0 |
0 |
T134 |
15130 |
1 |
0 |
0 |
T136 |
6524 |
2 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_lo_err_update_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 31 | 3 | 3 | 100.00 |
CONT_ASSIGN | 49 | 0 | 0 | |
CONT_ASSIGN | 52 | 0 | 0 | |
ALWAYS | 55 | 0 | 0 | |
ALWAYS | 89 | 3 | 3 | 100.00 |
CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
31 |
1 |
1 |
32 |
1 |
1 |
34 |
1 |
1 |
49 |
|
unreachable |
52 |
|
unreachable |
55 |
|
unreachable |
56 |
|
unreachable |
58 |
|
unreachable |
89 |
1 |
1 |
90 |
1 |
1 |
92 |
1 |
1 |
97 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_lo_err_update_sync
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 34
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T5,T6,T7 |
0 | 1 | Covered | T56,T57,T61 |
1 | 0 | Covered | T56,T57,T61 |
1 | 1 | Covered | T128 |
LINE 97
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T5,T6,T7 |
0 | 1 | Covered | T56,T57,T61 |
1 | 0 | Covered | T128 |
1 | 1 | Covered | T56,T57,T61 |
Branch Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_lo_err_update_sync
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
31 |
2 |
2 |
100.00 |
IF |
89 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 31 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T5,T6,T7 |
0 |
Covered |
T5,T6,T7 |
LineNo. Expression
-1-: 89 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T5,T6,T7 |
0 |
Covered |
T5,T6,T7 |
Assert Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_lo_err_update_sync
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
73828701 |
33 |
0 |
0 |
T56 |
8314 |
1 |
0 |
0 |
T57 |
8585 |
2 |
0 |
0 |
T59 |
4826 |
3 |
0 |
0 |
T60 |
4771 |
1 |
0 |
0 |
T61 |
9336 |
1 |
0 |
0 |
T63 |
6812 |
1 |
0 |
0 |
T66 |
15216 |
2 |
0 |
0 |
T118 |
10424 |
2 |
0 |
0 |
T126 |
10644 |
1 |
0 |
0 |
T128 |
4524 |
2 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
239150230 |
33 |
0 |
0 |
T56 |
14335 |
1 |
0 |
0 |
T57 |
8672 |
2 |
0 |
0 |
T59 |
20112 |
3 |
0 |
0 |
T60 |
28071 |
1 |
0 |
0 |
T61 |
9336 |
1 |
0 |
0 |
T63 |
7097 |
1 |
0 |
0 |
T66 |
15851 |
2 |
0 |
0 |
T118 |
21717 |
2 |
0 |
0 |
T126 |
21723 |
1 |
0 |
0 |
T128 |
18096 |
2 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_hi_err_update_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 31 | 3 | 3 | 100.00 |
CONT_ASSIGN | 49 | 0 | 0 | |
CONT_ASSIGN | 52 | 0 | 0 | |
ALWAYS | 55 | 0 | 0 | |
ALWAYS | 89 | 3 | 3 | 100.00 |
CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
31 |
1 |
1 |
32 |
1 |
1 |
34 |
1 |
1 |
49 |
|
unreachable |
52 |
|
unreachable |
55 |
|
unreachable |
56 |
|
unreachable |
58 |
|
unreachable |
89 |
1 |
1 |
90 |
1 |
1 |
92 |
1 |
1 |
97 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_hi_err_update_sync
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 34
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T5,T6,T7 |
0 | 1 | Covered | T57,T62,T63 |
1 | 0 | Covered | T57,T62,T63 |
1 | 1 | Covered | T127,T118,T137 |
LINE 97
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T5,T6,T7 |
0 | 1 | Covered | T57,T62,T63 |
1 | 0 | Covered | T127,T118,T137 |
1 | 1 | Covered | T57,T62,T63 |
Branch Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_hi_err_update_sync
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
31 |
2 |
2 |
100.00 |
IF |
89 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 31 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T5,T6,T7 |
0 |
Covered |
T5,T6,T7 |
LineNo. Expression
-1-: 89 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T5,T6,T7 |
0 |
Covered |
T5,T6,T7 |
Assert Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_hi_err_update_sync
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
73828701 |
33 |
0 |
0 |
T57 |
8585 |
2 |
0 |
0 |
T59 |
4826 |
3 |
0 |
0 |
T60 |
4771 |
1 |
0 |
0 |
T62 |
9216 |
1 |
0 |
0 |
T63 |
6812 |
1 |
0 |
0 |
T64 |
5616 |
2 |
0 |
0 |
T66 |
15216 |
1 |
0 |
0 |
T118 |
10424 |
2 |
0 |
0 |
T127 |
3814 |
3 |
0 |
0 |
T134 |
7565 |
1 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
114657872 |
33 |
0 |
0 |
T57 |
4162 |
2 |
0 |
0 |
T59 |
9653 |
3 |
0 |
0 |
T60 |
13474 |
1 |
0 |
0 |
T62 |
4608 |
1 |
0 |
0 |
T63 |
3407 |
1 |
0 |
0 |
T64 |
10784 |
2 |
0 |
0 |
T66 |
7608 |
1 |
0 |
0 |
T118 |
10424 |
2 |
0 |
0 |
T127 |
16642 |
3 |
0 |
0 |
T134 |
7262 |
1 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_lo_err_update_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 31 | 3 | 3 | 100.00 |
CONT_ASSIGN | 49 | 0 | 0 | |
CONT_ASSIGN | 52 | 0 | 0 | |
ALWAYS | 55 | 0 | 0 | |
ALWAYS | 89 | 3 | 3 | 100.00 |
CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
31 |
1 |
1 |
32 |
1 |
1 |
34 |
1 |
1 |
49 |
|
unreachable |
52 |
|
unreachable |
55 |
|
unreachable |
56 |
|
unreachable |
58 |
|
unreachable |
89 |
1 |
1 |
90 |
1 |
1 |
92 |
1 |
1 |
97 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_lo_err_update_sync
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 34
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T5,T6,T7 |
0 | 1 | Covered | T57,T62,T65 |
1 | 0 | Covered | T57,T62,T65 |
1 | 1 | Covered | T66,T118,T137 |
LINE 97
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T5,T6,T7 |
0 | 1 | Covered | T57,T62,T65 |
1 | 0 | Covered | T66,T118,T137 |
1 | 1 | Covered | T57,T62,T65 |
Branch Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_lo_err_update_sync
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
31 |
2 |
2 |
100.00 |
IF |
89 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 31 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T5,T6,T7 |
0 |
Covered |
T5,T6,T7 |
LineNo. Expression
-1-: 89 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T5,T6,T7 |
0 |
Covered |
T5,T6,T7 |
Assert Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_lo_err_update_sync
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
73828701 |
35 |
0 |
0 |
T57 |
8585 |
3 |
0 |
0 |
T59 |
4826 |
3 |
0 |
0 |
T60 |
4771 |
1 |
0 |
0 |
T62 |
9216 |
1 |
0 |
0 |
T63 |
6812 |
2 |
0 |
0 |
T64 |
5616 |
1 |
0 |
0 |
T65 |
16822 |
1 |
0 |
0 |
T66 |
15216 |
2 |
0 |
0 |
T122 |
5009 |
1 |
0 |
0 |
T134 |
7565 |
1 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
114657872 |
35 |
0 |
0 |
T57 |
4162 |
3 |
0 |
0 |
T59 |
9653 |
3 |
0 |
0 |
T60 |
13474 |
1 |
0 |
0 |
T62 |
4608 |
1 |
0 |
0 |
T63 |
3407 |
2 |
0 |
0 |
T64 |
10784 |
1 |
0 |
0 |
T65 |
8411 |
1 |
0 |
0 |
T66 |
7608 |
2 |
0 |
0 |
T122 |
2405 |
1 |
0 |
0 |
T134 |
7262 |
1 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_io_meas.u_meas.u_sync_ref
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 31 | 3 | 3 | 100.00 |
CONT_ASSIGN | 49 | 0 | 0 | |
CONT_ASSIGN | 52 | 0 | 0 | |
ALWAYS | 55 | 0 | 0 | |
ALWAYS | 89 | 3 | 3 | 100.00 |
CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
31 |
1 |
1 |
32 |
1 |
1 |
34 |
1 |
1 |
49 |
|
unreachable |
52 |
|
unreachable |
55 |
|
unreachable |
56 |
|
unreachable |
58 |
|
unreachable |
89 |
1 |
1 |
90 |
1 |
1 |
92 |
1 |
1 |
97 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_io_meas.u_meas.u_sync_ref
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 34
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T5,T6,T7 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 97
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T5,T6,T7 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
Branch Coverage for Instance : tb.dut.u_io_meas.u_meas.u_sync_ref
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
31 |
2 |
2 |
100.00 |
IF |
89 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 31 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T5,T6,T7 |
0 |
Covered |
T5,T6,T7 |
LineNo. Expression
-1-: 89 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T5,T6,T7 |
0 |
Covered |
T5,T6,T7 |
Assert Coverage for Instance : tb.dut.u_io_meas.u_meas.u_sync_ref
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
221350909 |
53056 |
0 |
0 |
T1 |
118070 |
49 |
0 |
0 |
T2 |
768287 |
362 |
0 |
0 |
T3 |
284364 |
112 |
0 |
0 |
T4 |
28697 |
0 |
0 |
0 |
T11 |
0 |
1312 |
0 |
0 |
T12 |
0 |
1167 |
0 |
0 |
T13 |
0 |
55 |
0 |
0 |
T14 |
0 |
95 |
0 |
0 |
T15 |
0 |
133 |
0 |
0 |
T16 |
0 |
69 |
0 |
0 |
T18 |
9219 |
0 |
0 |
0 |
T19 |
1995 |
0 |
0 |
0 |
T20 |
5283 |
0 |
0 |
0 |
T21 |
4775 |
0 |
0 |
0 |
T22 |
2084 |
0 |
0 |
0 |
T23 |
2589 |
0 |
0 |
0 |
T33 |
0 |
78 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
7118742 |
52800 |
0 |
0 |
T1 |
266 |
49 |
0 |
0 |
T2 |
2229 |
362 |
0 |
0 |
T3 |
1287 |
112 |
0 |
0 |
T4 |
74 |
0 |
0 |
0 |
T11 |
0 |
1310 |
0 |
0 |
T12 |
0 |
1167 |
0 |
0 |
T13 |
0 |
55 |
0 |
0 |
T14 |
0 |
95 |
0 |
0 |
T15 |
0 |
133 |
0 |
0 |
T16 |
0 |
69 |
0 |
0 |
T18 |
672 |
0 |
0 |
0 |
T19 |
145 |
0 |
0 |
0 |
T20 |
385 |
0 |
0 |
0 |
T21 |
348 |
0 |
0 |
0 |
T22 |
152 |
0 |
0 |
0 |
T23 |
189 |
0 |
0 |
0 |
T33 |
0 |
78 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_io_div2_meas.u_meas.u_sync_ref
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 31 | 3 | 3 | 100.00 |
CONT_ASSIGN | 49 | 0 | 0 | |
CONT_ASSIGN | 52 | 0 | 0 | |
ALWAYS | 55 | 0 | 0 | |
ALWAYS | 89 | 3 | 3 | 100.00 |
CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
31 |
1 |
1 |
32 |
1 |
1 |
34 |
1 |
1 |
49 |
|
unreachable |
52 |
|
unreachable |
55 |
|
unreachable |
56 |
|
unreachable |
58 |
|
unreachable |
89 |
1 |
1 |
90 |
1 |
1 |
92 |
1 |
1 |
97 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_io_div2_meas.u_meas.u_sync_ref
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 34
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T5,T6,T7 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 97
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T5,T6,T7 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
Branch Coverage for Instance : tb.dut.u_io_div2_meas.u_meas.u_sync_ref
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
31 |
2 |
2 |
100.00 |
IF |
89 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 31 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T5,T6,T7 |
0 |
Covered |
T5,T6,T7 |
LineNo. Expression
-1-: 89 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T5,T6,T7 |
0 |
Covered |
T5,T6,T7 |
Assert Coverage for Instance : tb.dut.u_io_div2_meas.u_meas.u_sync_ref
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
109955818 |
52801 |
0 |
0 |
T1 |
59023 |
49 |
0 |
0 |
T2 |
383768 |
362 |
0 |
0 |
T3 |
142179 |
112 |
0 |
0 |
T4 |
10237 |
0 |
0 |
0 |
T11 |
0 |
1296 |
0 |
0 |
T12 |
0 |
1164 |
0 |
0 |
T13 |
0 |
55 |
0 |
0 |
T14 |
0 |
95 |
0 |
0 |
T15 |
0 |
133 |
0 |
0 |
T16 |
0 |
69 |
0 |
0 |
T18 |
5099 |
0 |
0 |
0 |
T19 |
1078 |
0 |
0 |
0 |
T20 |
2575 |
0 |
0 |
0 |
T21 |
2702 |
0 |
0 |
0 |
T22 |
1162 |
0 |
0 |
0 |
T23 |
1268 |
0 |
0 |
0 |
T33 |
0 |
78 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
7118742 |
52545 |
0 |
0 |
T1 |
266 |
49 |
0 |
0 |
T2 |
2229 |
362 |
0 |
0 |
T3 |
1287 |
112 |
0 |
0 |
T4 |
74 |
0 |
0 |
0 |
T11 |
0 |
1294 |
0 |
0 |
T12 |
0 |
1164 |
0 |
0 |
T13 |
0 |
55 |
0 |
0 |
T14 |
0 |
95 |
0 |
0 |
T15 |
0 |
133 |
0 |
0 |
T16 |
0 |
69 |
0 |
0 |
T18 |
672 |
0 |
0 |
0 |
T19 |
145 |
0 |
0 |
0 |
T20 |
385 |
0 |
0 |
0 |
T21 |
348 |
0 |
0 |
0 |
T22 |
152 |
0 |
0 |
0 |
T23 |
189 |
0 |
0 |
0 |
T33 |
0 |
78 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_io_div4_meas.u_meas.u_sync_ref
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 31 | 3 | 3 | 100.00 |
CONT_ASSIGN | 49 | 0 | 0 | |
CONT_ASSIGN | 52 | 0 | 0 | |
ALWAYS | 55 | 0 | 0 | |
ALWAYS | 89 | 3 | 3 | 100.00 |
CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
31 |
1 |
1 |
32 |
1 |
1 |
34 |
1 |
1 |
49 |
|
unreachable |
52 |
|
unreachable |
55 |
|
unreachable |
56 |
|
unreachable |
58 |
|
unreachable |
89 |
1 |
1 |
90 |
1 |
1 |
92 |
1 |
1 |
97 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_io_div4_meas.u_meas.u_sync_ref
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 34
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T5,T6,T7 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 97
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T5,T6,T7 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
Branch Coverage for Instance : tb.dut.u_io_div4_meas.u_meas.u_sync_ref
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
31 |
2 |
2 |
100.00 |
IF |
89 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 31 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T5,T6,T7 |
0 |
Covered |
T5,T6,T7 |
LineNo. Expression
-1-: 89 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T5,T6,T7 |
0 |
Covered |
T5,T6,T7 |
Assert Coverage for Instance : tb.dut.u_io_div4_meas.u_meas.u_sync_ref
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
54977509 |
52221 |
0 |
0 |
T1 |
29511 |
49 |
0 |
0 |
T2 |
191885 |
362 |
0 |
0 |
T3 |
71085 |
112 |
0 |
0 |
T4 |
5118 |
0 |
0 |
0 |
T11 |
0 |
1235 |
0 |
0 |
T12 |
0 |
1151 |
0 |
0 |
T13 |
0 |
55 |
0 |
0 |
T14 |
0 |
95 |
0 |
0 |
T15 |
0 |
133 |
0 |
0 |
T16 |
0 |
69 |
0 |
0 |
T18 |
2548 |
0 |
0 |
0 |
T19 |
538 |
0 |
0 |
0 |
T20 |
1287 |
0 |
0 |
0 |
T21 |
1351 |
0 |
0 |
0 |
T22 |
579 |
0 |
0 |
0 |
T23 |
634 |
0 |
0 |
0 |
T33 |
0 |
78 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
7118742 |
51966 |
0 |
0 |
T1 |
266 |
49 |
0 |
0 |
T2 |
2229 |
362 |
0 |
0 |
T3 |
1287 |
112 |
0 |
0 |
T4 |
74 |
0 |
0 |
0 |
T11 |
0 |
1234 |
0 |
0 |
T12 |
0 |
1151 |
0 |
0 |
T13 |
0 |
55 |
0 |
0 |
T14 |
0 |
95 |
0 |
0 |
T15 |
0 |
133 |
0 |
0 |
T16 |
0 |
69 |
0 |
0 |
T18 |
672 |
0 |
0 |
0 |
T19 |
145 |
0 |
0 |
0 |
T20 |
385 |
0 |
0 |
0 |
T21 |
348 |
0 |
0 |
0 |
T22 |
152 |
0 |
0 |
0 |
T23 |
189 |
0 |
0 |
0 |
T33 |
0 |
78 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_main_meas.u_meas.u_sync_ref
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 31 | 3 | 3 | 100.00 |
CONT_ASSIGN | 49 | 0 | 0 | |
CONT_ASSIGN | 52 | 0 | 0 | |
ALWAYS | 55 | 0 | 0 | |
ALWAYS | 89 | 3 | 3 | 100.00 |
CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
31 |
1 |
1 |
32 |
1 |
1 |
34 |
1 |
1 |
49 |
|
unreachable |
52 |
|
unreachable |
55 |
|
unreachable |
56 |
|
unreachable |
58 |
|
unreachable |
89 |
1 |
1 |
90 |
1 |
1 |
92 |
1 |
1 |
97 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_main_meas.u_meas.u_sync_ref
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 34
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T5,T6,T7 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 97
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T5,T6,T7 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
Branch Coverage for Instance : tb.dut.u_main_meas.u_meas.u_sync_ref
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
31 |
2 |
2 |
100.00 |
IF |
89 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 31 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T5,T6,T7 |
0 |
Covered |
T5,T6,T7 |
LineNo. Expression
-1-: 89 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T5,T6,T7 |
0 |
Covered |
T5,T6,T7 |
Assert Coverage for Instance : tb.dut.u_main_meas.u_meas.u_sync_ref
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
236483738 |
63077 |
0 |
0 |
T1 |
122993 |
47 |
0 |
0 |
T2 |
812325 |
386 |
0 |
0 |
T3 |
296222 |
112 |
0 |
0 |
T4 |
29894 |
0 |
0 |
0 |
T11 |
0 |
1464 |
0 |
0 |
T12 |
0 |
1222 |
0 |
0 |
T13 |
0 |
55 |
0 |
0 |
T14 |
0 |
95 |
0 |
0 |
T15 |
0 |
157 |
0 |
0 |
T16 |
0 |
69 |
0 |
0 |
T18 |
9604 |
0 |
0 |
0 |
T19 |
2079 |
0 |
0 |
0 |
T20 |
5503 |
0 |
0 |
0 |
T21 |
4975 |
0 |
0 |
0 |
T22 |
2170 |
0 |
0 |
0 |
T23 |
2697 |
0 |
0 |
0 |
T33 |
0 |
102 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
7093438 |
62511 |
0 |
0 |
T1 |
266 |
47 |
0 |
0 |
T2 |
2253 |
386 |
0 |
0 |
T3 |
1287 |
112 |
0 |
0 |
T4 |
74 |
0 |
0 |
0 |
T11 |
0 |
1226 |
0 |
0 |
T12 |
0 |
1222 |
0 |
0 |
T13 |
0 |
55 |
0 |
0 |
T14 |
0 |
95 |
0 |
0 |
T15 |
0 |
157 |
0 |
0 |
T16 |
0 |
69 |
0 |
0 |
T18 |
672 |
0 |
0 |
0 |
T19 |
145 |
0 |
0 |
0 |
T20 |
385 |
0 |
0 |
0 |
T21 |
348 |
0 |
0 |
0 |
T22 |
152 |
0 |
0 |
0 |
T23 |
189 |
0 |
0 |
0 |
T33 |
0 |
102 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_usb_meas.u_meas.u_sync_ref
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 31 | 3 | 3 | 100.00 |
CONT_ASSIGN | 49 | 0 | 0 | |
CONT_ASSIGN | 52 | 0 | 0 | |
ALWAYS | 55 | 0 | 0 | |
ALWAYS | 89 | 3 | 3 | 100.00 |
CONT_ASSIGN | 97 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
31 |
1 |
1 |
32 |
1 |
1 |
34 |
1 |
1 |
49 |
|
unreachable |
52 |
|
unreachable |
55 |
|
unreachable |
56 |
|
unreachable |
58 |
|
unreachable |
89 |
1 |
1 |
90 |
1 |
1 |
92 |
1 |
1 |
97 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_usb_meas.u_meas.u_sync_ref
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 34
EXPRESSION (src_level ^ src_pulse_i)
----1---- -----2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T5,T6,T7 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 97
EXPRESSION (dst_level_q ^ dst_level)
-----1----- ----2----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T5,T6,T7 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
Branch Coverage for Instance : tb.dut.u_usb_meas.u_meas.u_sync_ref
| Line No. | Total | Covered | Percent |
Branches |
|
4 |
4 |
100.00 |
IF |
31 |
2 |
2 |
100.00 |
IF |
89 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 31 if ((!rst_src_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T5,T6,T7 |
0 |
Covered |
T5,T6,T7 |
LineNo. Expression
-1-: 89 if ((!rst_dst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T5,T6,T7 |
0 |
Covered |
T5,T6,T7 |
Assert Coverage for Instance : tb.dut.u_usb_meas.u_meas.u_sync_ref
Assertion Details
DstPulseCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
113377980 |
61717 |
0 |
0 |
T1 |
59037 |
42 |
0 |
0 |
T2 |
384162 |
362 |
0 |
0 |
T3 |
142189 |
112 |
0 |
0 |
T4 |
14349 |
0 |
0 |
0 |
T11 |
0 |
1388 |
0 |
0 |
T12 |
0 |
1183 |
0 |
0 |
T13 |
0 |
48 |
0 |
0 |
T14 |
0 |
95 |
0 |
0 |
T15 |
0 |
121 |
0 |
0 |
T16 |
0 |
69 |
0 |
0 |
T18 |
4609 |
0 |
0 |
0 |
T19 |
997 |
0 |
0 |
0 |
T20 |
2641 |
0 |
0 |
0 |
T21 |
2388 |
0 |
0 |
0 |
T22 |
1042 |
0 |
0 |
0 |
T23 |
1295 |
0 |
0 |
0 |
T33 |
0 |
102 |
0 |
0 |
SrcPulseCheck_M
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
7178462 |
61220 |
0 |
0 |
T1 |
266 |
42 |
0 |
0 |
T2 |
2229 |
362 |
0 |
0 |
T3 |
1287 |
112 |
0 |
0 |
T4 |
74 |
0 |
0 |
0 |
T11 |
0 |
1388 |
0 |
0 |
T12 |
0 |
1183 |
0 |
0 |
T13 |
0 |
48 |
0 |
0 |
T14 |
0 |
95 |
0 |
0 |
T15 |
0 |
121 |
0 |
0 |
T16 |
0 |
69 |
0 |
0 |
T18 |
672 |
0 |
0 |
0 |
T19 |
145 |
0 |
0 |
0 |
T20 |
385 |
0 |
0 |
0 |
T21 |
348 |
0 |
0 |
0 |
T22 |
152 |
0 |
0 |
0 |
T23 |
189 |
0 |
0 |
0 |
T33 |
0 |
102 |
0 |
0 |