Module Definition
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Module Instance : tb.dut.u_reg.u_io_meas_ctrl_en_cdc.u_arb

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
73.61 90.00 76.19 78.26 50.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
83.59 94.90 76.09 88.37 75.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
96.43 100.00 85.71 100.00 100.00 u_io_meas_ctrl_en_cdc


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_wr_req.u_dst_update_sync 93.75 100.00 75.00 100.00 100.00



Module Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_en_cdc.u_arb

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
73.61 90.00 76.19 78.26 50.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
83.59 94.90 76.09 88.37 75.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
96.43 100.00 85.71 100.00 100.00 u_io_div2_meas_ctrl_en_cdc


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_wr_req.u_dst_update_sync 93.75 100.00 75.00 100.00 100.00



Module Instance : tb.dut.u_reg.u_main_meas_ctrl_en_cdc.u_arb

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
73.61 90.00 76.19 78.26 50.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
83.59 94.90 76.09 88.37 75.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
96.43 100.00 85.71 100.00 100.00 u_main_meas_ctrl_en_cdc


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_wr_req.u_dst_update_sync 93.75 100.00 75.00 100.00 100.00



Module Instance : tb.dut.u_reg.u_usb_meas_ctrl_en_cdc.u_arb

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
73.61 90.00 76.19 78.26 50.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
83.59 94.90 76.09 88.37 75.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
96.43 100.00 85.71 100.00 100.00 u_usb_meas_ctrl_en_cdc


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_wr_req.u_dst_update_sync 93.75 100.00 75.00 100.00 100.00



Module Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_en_cdc.u_arb

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
79.17 94.00 85.71 86.96 50.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
87.44 96.94 84.78 93.02 75.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
96.43 100.00 85.71 100.00 100.00 u_io_div4_meas_ctrl_en_cdc


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_wr_req.u_dst_update_sync 93.75 100.00 75.00 100.00 100.00



Module Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_cdc.u_arb

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
83.33 100.00 66.67


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
97.73 100.00 90.91 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
97.92 100.00 91.67 100.00 100.00 u_io_meas_ctrl_shadowed_cdc


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_passthru.u_dst_to_src_ack 100.00 100.00 100.00 100.00 100.00



Module Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_cdc.u_arb

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
83.33 100.00 66.67


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
97.73 100.00 90.91 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
97.92 100.00 91.67 100.00 100.00 u_io_div2_meas_ctrl_shadowed_cdc


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_passthru.u_dst_to_src_ack 100.00 100.00 100.00 100.00 100.00



Module Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_cdc.u_arb

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
83.33 100.00 66.67


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
97.73 100.00 90.91 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
97.92 100.00 91.67 100.00 100.00 u_io_div4_meas_ctrl_shadowed_cdc


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_passthru.u_dst_to_src_ack 100.00 100.00 100.00 100.00 100.00



Module Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_cdc.u_arb

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
83.33 100.00 66.67


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
97.73 100.00 90.91 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
97.92 100.00 91.67 100.00 100.00 u_main_meas_ctrl_shadowed_cdc


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_passthru.u_dst_to_src_ack 100.00 100.00 100.00 100.00 100.00



Module Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_cdc.u_arb

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
83.33 100.00 66.67


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
97.73 100.00 90.91 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
97.92 100.00 91.67 100.00 100.00 u_usb_meas_ctrl_shadowed_cdc


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_passthru.u_dst_to_src_ack 100.00 100.00 100.00 100.00 100.00

Line Coverage for Module : prim_reg_cdc_arb ( parameter DataWidth=4,ResetVal=9,DstWrReq=1 )
Line Coverage for Module self-instances :
SCORELINE
73.61 90.00
tb.dut.u_reg.u_io_meas_ctrl_en_cdc.u_arb

SCORELINE
73.61 90.00
tb.dut.u_reg.u_io_div2_meas_ctrl_en_cdc.u_arb

SCORELINE
79.17 94.00
tb.dut.u_reg.u_io_div4_meas_ctrl_en_cdc.u_arb

SCORELINE
73.61 90.00
tb.dut.u_reg.u_main_meas_ctrl_en_cdc.u_arb

SCORELINE
73.61 90.00
tb.dut.u_reg.u_usb_meas_ctrl_en_cdc.u_arb

Line No.TotalCoveredPercent
TOTAL504794.00
CONT_ASSIGN10011100.00
ALWAYS11133100.00
ALWAYS12166100.00
CONT_ASSIGN13511100.00
ALWAYS13966100.00
ALWAYS15510990.00
CONT_ASSIGN18311100.00
ALWAYS187191789.47
CONT_ASSIGN22811100.00
CONT_ASSIGN24311100.00
CONT_ASSIGN24411100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc_arb.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
100 1 1
111 1 1
112 1 1
114 1 1
121 1 1
122 1 1
123 1 1
128 1 1
129 1 1
132 1 1
MISSING_ELSE
135 1 1
139 1 1
140 1 1
141 1 1
142 1 1
143 1 1
144 1 1
MISSING_ELSE
155 1 1
156 1 1
157 1 1
158 1 1
159 1 1
160 1 1
161 1 1
162 0 1
163 1 1
164 1 1
MISSING_ELSE
183 1 1
187 1 1
188 1 1
192 1 1
193 1 1
195 1 1
197 1 1
199 1 1
200 1 1
202 1 1
203 1 1
204 1 1
205 0 1
206 0 1
207 1 1
210 1 1
211 1 1
MISSING_ELSE
216 1 1
217 1 1
218 1 1
MISSING_ELSE
228 1 1
243 1 1
244 1 1


Line Coverage for Module : prim_reg_cdc_arb ( parameter DataWidth=20,ResetVal,DstWrReq=0 + DataWidth=18,ResetVal=118010,DstWrReq=0 + DataWidth=16,ResetVal=28290,DstWrReq=0 )
Line Coverage for Module self-instances :
SCORELINE
83.33 100.00
tb.dut.u_reg.u_io_meas_ctrl_shadowed_cdc.u_arb

SCORELINE
83.33 100.00
tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_cdc.u_arb

SCORELINE
83.33 100.00
tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_cdc.u_arb

SCORELINE
83.33 100.00
tb.dut.u_reg.u_main_meas_ctrl_shadowed_cdc.u_arb

SCORELINE
83.33 100.00
tb.dut.u_reg.u_usb_meas_ctrl_shadowed_cdc.u_arb

Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN10000
CONT_ASSIGN28311100.00
CONT_ASSIGN28411100.00
CONT_ASSIGN29900
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc_arb.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
100 unreachable
283 1 1
284 1 1
299 unreachable


Cond Coverage for Module : prim_reg_cdc_arb ( parameter DataWidth=4,ResetVal=9,DstWrReq=1 )
Cond Coverage for Module self-instances :
SCORECOND
73.61 76.19
tb.dut.u_reg.u_io_meas_ctrl_en_cdc.u_arb

SCORECOND
73.61 76.19
tb.dut.u_reg.u_io_div2_meas_ctrl_en_cdc.u_arb

SCORECOND
79.17 85.71
tb.dut.u_reg.u_io_div4_meas_ctrl_en_cdc.u_arb

SCORECOND
73.61 76.19
tb.dut.u_reg.u_main_meas_ctrl_en_cdc.u_arb

SCORECOND
73.61 76.19
tb.dut.u_reg.u_usb_meas_ctrl_en_cdc.u_arb

TotalCoveredPercent
Conditions433683.72
Logical433683.72
Non-Logical00
Event00

 LINE       100
 EXPRESSION (dst_update_i & (dst_qs_o != dst_ds_i))
             ------1-----   -----------2----------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T4
11CoveredT1,T2,T4

 LINE       100
 SUB-EXPRESSION (dst_qs_o != dst_ds_i)
                -----------1----------
-1-StatusTests
0CoveredT5,T6,T7
1CoveredT1,T2,T4

 LINE       123
 EXPRESSION (gen_wr_req.dst_req_q && gen_wr_req.dst_lat_d)
             ----------1---------    ----------2---------
-1--2-StatusTests
01CoveredT1,T2,T4
10Not Covered
11CoveredT8,T9,T10

 LINE       129
 EXPRESSION (dst_req_i && ((!gen_wr_req.dst_req_q)) && gen_wr_req.busy)
             ----1----    ------------2------------    -------3-------
-1--2--3-StatusTests
011CoveredT1,T2,T4
101Not Covered
110CoveredT1,T2,T4
111CoveredT8,T9,T10

 LINE       135
 EXPRESSION (gen_wr_req.dst_req_q | dst_req_i)
             ----------1---------   ----2----
-1--2-StatusTests
00CoveredT5,T6,T7
01CoveredT1,T2,T4
10CoveredT8,T9,T10

 LINE       157
 EXPRESSION (gen_wr_req.dst_update_req && gen_wr_req.dst_update_ack)
             ------------1------------    ------------2------------
-1--2-StatusTests
01Not Covered
10CoveredT1,T2,T4
11CoveredT1,T2,T4

 LINE       159
 EXPRESSION (gen_wr_req.dst_req && gen_wr_req.dst_lat_d)
             ---------1--------    ----------2---------
-1--2-StatusTests
01Not Covered
10Not Covered
11CoveredT1,T2,T4

 LINE       161
 EXPRESSION (((!gen_wr_req.dst_req)) && gen_wr_req.dst_lat_d)
             -----------1-----------    ----------2---------
-1--2-StatusTests
01Not Covered
10CoveredT5,T6,T7
11Not Covered

 LINE       183
 EXPRESSION (((~gen_wr_req.busy)) & gen_wr_req.dst_req)
             ----------1---------   ---------2--------
-1--2-StatusTests
01CoveredT8,T9,T10
10CoveredT5,T6,T7
11CoveredT1,T2,T4

 LINE       207
 EXPRESSION (dst_qs_o != dst_qs_i)
            -----------1----------
-1-StatusTests
0CoveredT1,T2,T4
1CoveredT1,T2,T3

 LINE       228
 EXPRESSION (gen_wr_req.dst_hold_req | gen_wr_req.dst_lat_d | gen_wr_req.dst_lat_q)
             -----------1-----------   ----------2---------   ----------3---------
-1--2--3-StatusTests
000CoveredT5,T6,T7
001CoveredT1,T2,T3
010CoveredT1,T2,T4
100CoveredT1,T2,T4

 LINE       243
 EXPRESSION (gen_wr_req.src_req & (gen_wr_req.id_q == SelSwReq))
             ---------1--------   --------------2--------------
-1--2-StatusTests
01CoveredT5,T6,T7
10CoveredT1,T2,T3
11CoveredT1,T2,T4

 LINE       243
 SUB-EXPRESSION (gen_wr_req.id_q == SelSwReq)
                --------------1--------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT5,T6,T7

 LINE       244
 EXPRESSION (gen_wr_req.src_req & (gen_wr_req.id_q == SelHwReq))
             ---------1--------   --------------2--------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T4
11CoveredT1,T2,T3

 LINE       244
 SUB-EXPRESSION (gen_wr_req.id_q == SelHwReq)
                --------------1--------------
-1-StatusTests
0CoveredT5,T6,T7
1CoveredT1,T2,T3

Cond Coverage for Module : prim_reg_cdc_arb ( parameter DataWidth=20,ResetVal,DstWrReq=0 + DataWidth=18,ResetVal=118010,DstWrReq=0 + DataWidth=16,ResetVal=28290,DstWrReq=0 )
Cond Coverage for Module self-instances :
SCORECOND
83.33 66.67
tb.dut.u_reg.u_io_meas_ctrl_shadowed_cdc.u_arb

SCORECOND
83.33 66.67
tb.dut.u_reg.u_main_meas_ctrl_shadowed_cdc.u_arb

SCORECOND
83.33 66.67
tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_cdc.u_arb

SCORECOND
83.33 66.67
tb.dut.u_reg.u_usb_meas_ctrl_shadowed_cdc.u_arb

SCORECOND
83.33 66.67
tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_cdc.u_arb

TotalCoveredPercent
Conditions3266.67
Logical3266.67
Non-Logical00
Event00

 LINE       100
 EXPRESSION (dst_update_i & (dst_qs_o != dst_ds_i))
             ------1-----   -----------2----------
-1--2-StatusTests
01CoveredT5,T6,T7
10Unreachable
11Unreachable

 LINE       100
 SUB-EXPRESSION (dst_qs_o != dst_ds_i)
                -----------1----------
-1-StatusTests
0Not Covered
1CoveredT5,T6,T7

Branch Coverage for Module : prim_reg_cdc_arb
Line No.TotalCoveredPercent
Branches 23 20 86.96
IF 111 2 2 100.00
IF 121 4 4 100.00
IF 139 4 4 100.00
IF 155 6 5 83.33
CASE 197 7 5 71.43

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc_arb.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 111 if ((!rst_dst_ni))

Branches:
-1-StatusTests
1 Covered T5,T6,T7
0 Covered T5,T6,T7


LineNo. Expression -1-: 121 if ((!rst_dst_ni)) -2-: 123 if ((gen_wr_req.dst_req_q && gen_wr_req.dst_lat_d)) -3-: 129 if (((dst_req_i && (!gen_wr_req.dst_req_q)) && gen_wr_req.busy))

Branches:
-1--2--3-StatusTests
1 - - Covered T5,T6,T7
0 1 - Covered T8,T9,T10
0 0 1 Covered T8,T9,T10
0 0 0 Covered T5,T6,T7


LineNo. Expression -1-: 139 if ((!rst_dst_ni)) -2-: 141 if (gen_wr_req.dst_lat_d) -3-: 143 if (gen_wr_req.dst_lat_q)

Branches:
-1--2--3-StatusTests
1 - - Covered T5,T6,T7
0 1 - Covered T1,T2,T4
0 0 1 Covered T1,T2,T3
0 0 0 Covered T5,T6,T7


LineNo. Expression -1-: 155 if ((!rst_dst_ni)) -2-: 157 if ((gen_wr_req.dst_update_req && gen_wr_req.dst_update_ack)) -3-: 159 if ((gen_wr_req.dst_req && gen_wr_req.dst_lat_d)) -4-: 161 if (((!gen_wr_req.dst_req) && gen_wr_req.dst_lat_d)) -5-: 163 if (gen_wr_req.dst_lat_q)

Branches:
-1--2--3--4--5-StatusTests
1 - - - - Covered T5,T6,T7
0 1 - - - Covered T1,T2,T4
0 0 1 - - Covered T1,T2,T4
0 0 0 1 - Not Covered
0 0 0 0 1 Covered T1,T2,T3
0 0 0 0 0 Covered T5,T6,T7


LineNo. Expression -1-: 197 case (gen_wr_req.state_q) -2-: 200 if (gen_wr_req.dst_req) -3-: 204 if (dst_update) -4-: 207 if ((dst_qs_o != dst_qs_i)) -5-: 217 if (gen_wr_req.dst_update_ack)

Branches:
-1--2--3--4--5-StatusTests
StIdle 1 - - - Covered T1,T2,T4
StIdle 0 1 - - Not Covered
StIdle 0 0 1 - Covered T1,T2,T3
StIdle 0 0 0 - Covered T1,T2,T4
StWait - - - 1 Covered T1,T2,T4
StWait - - - 0 Covered T1,T2,T4
default - - - - Not Covered


Assert Coverage for Module : prim_reg_cdc_arb
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 1 50.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 1 50.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
gen_wr_req.DstUpdateReqCheck_A 744503626 0 0 4895
gen_wr_req.HwIdSelCheck_A 744503626 3200 0 0


gen_wr_req.DstUpdateReqCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 744503626 0 0 4895

gen_wr_req.HwIdSelCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 744503626 3200 0 0
T1 388634 15 0 0
T2 2540427 85 0 0
T3 936039 30 0 0
T4 88295 0 0 0
T11 0 30 0 0
T12 0 20 0 0
T13 0 10 0 0
T14 0 20 0 0
T15 0 5 0 0
T16 0 10 0 0
T17 0 5 0 0
T18 31079 0 0 0
T19 6687 0 0 0
T20 17289 0 0 0
T21 16191 0 0 0
T22 7037 0 0 0
T23 8483 0 0 0

Line Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_en_cdc.u_arb
Line No.TotalCoveredPercent
TOTAL504590.00
CONT_ASSIGN10011100.00
ALWAYS11133100.00
ALWAYS1216466.67
CONT_ASSIGN13511100.00
ALWAYS13966100.00
ALWAYS15510990.00
CONT_ASSIGN18311100.00
ALWAYS187191789.47
CONT_ASSIGN22811100.00
CONT_ASSIGN24311100.00
CONT_ASSIGN24411100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc_arb.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
100 1 1
111 1 1
112 1 1
114 1 1
121 1 1
122 1 1
123 1 1
128 0 1
129 1 1
132 0 1
MISSING_ELSE
135 1 1
139 1 1
140 1 1
141 1 1
142 1 1
143 1 1
144 1 1
MISSING_ELSE
155 1 1
156 1 1
157 1 1
158 1 1
159 1 1
160 1 1
161 1 1
162 0 1
163 1 1
164 1 1
MISSING_ELSE
183 1 1
187 1 1
188 1 1
192 1 1
193 1 1
195 1 1
197 1 1
199 1 1
200 1 1
202 1 1
203 1 1
204 1 1
205 0 1
206 0 1
207 1 1
210 1 1
211 1 1
MISSING_ELSE
216 1 1
217 1 1
218 1 1
MISSING_ELSE
228 1 1
243 1 1
244 1 1


Cond Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_en_cdc.u_arb
TotalCoveredPercent
Conditions423276.19
Logical423276.19
Non-Logical00
Event00

 LINE       100
 EXPRESSION (dst_update_i & (dst_qs_o != dst_ds_i))
             ------1-----   -----------2----------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T4
11CoveredT1,T2,T4

 LINE       100
 SUB-EXPRESSION (dst_qs_o != dst_ds_i)
                -----------1----------
-1-StatusTests
0CoveredT5,T6,T7
1CoveredT1,T2,T4

 LINE       123
 EXPRESSION (gen_wr_req.dst_req_q && gen_wr_req.dst_lat_d)
             ----------1---------    ----------2---------
-1--2-StatusTests
01CoveredT1,T2,T4
10Not Covered
11Not Covered

 LINE       129
 EXPRESSION (dst_req_i && ((!gen_wr_req.dst_req_q)) && gen_wr_req.busy)
             ----1----    ------------2------------    -------3-------
-1--2--3-StatusTests
011CoveredT1,T2,T4
101Not Covered
110CoveredT1,T2,T4
111Not Covered

 LINE       135
 EXPRESSION (gen_wr_req.dst_req_q | dst_req_i)
             ----------1---------   ----2----
-1--2-StatusTests
00CoveredT5,T6,T7
01CoveredT1,T2,T4
10Not Covered

 LINE       157
 EXPRESSION (gen_wr_req.dst_update_req && gen_wr_req.dst_update_ack)
             ------------1------------    ------------2------------
-1--2-StatusTests
01Not Covered
10CoveredT1,T2,T4
11CoveredT1,T2,T4

 LINE       159
 EXPRESSION (gen_wr_req.dst_req && gen_wr_req.dst_lat_d)
             ---------1--------    ----------2---------
-1--2-StatusTests
01Not Covered
10Not Covered
11CoveredT1,T2,T4

 LINE       161
 EXPRESSION (((!gen_wr_req.dst_req)) && gen_wr_req.dst_lat_d)
             -----------1-----------    ----------2---------
-1--2-StatusTestsExclude Annotation
01Excluded VC_COV_UNR
10CoveredT5,T6,T7
11Not Covered

 LINE       183
 EXPRESSION (((~gen_wr_req.busy)) & gen_wr_req.dst_req)
             ----------1---------   ---------2--------
-1--2-StatusTests
01Not Covered
10CoveredT5,T6,T7
11CoveredT1,T2,T4

 LINE       207
 EXPRESSION (dst_qs_o != dst_qs_i)
            -----------1----------
-1-StatusTests
0CoveredT1,T2,T4
1CoveredT1,T2,T3

 LINE       228
 EXPRESSION (gen_wr_req.dst_hold_req | gen_wr_req.dst_lat_d | gen_wr_req.dst_lat_q)
             -----------1-----------   ----------2---------   ----------3---------
-1--2--3-StatusTests
000CoveredT5,T6,T7
001CoveredT1,T2,T3
010CoveredT1,T2,T4
100CoveredT1,T2,T4

 LINE       243
 EXPRESSION (gen_wr_req.src_req & (gen_wr_req.id_q == SelSwReq))
             ---------1--------   --------------2--------------
-1--2-StatusTests
01CoveredT5,T6,T7
10CoveredT1,T2,T3
11CoveredT1,T2,T4

 LINE       243
 SUB-EXPRESSION (gen_wr_req.id_q == SelSwReq)
                --------------1--------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT5,T6,T7

 LINE       244
 EXPRESSION (gen_wr_req.src_req & (gen_wr_req.id_q == SelHwReq))
             ---------1--------   --------------2--------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T4
11CoveredT1,T2,T3

 LINE       244
 SUB-EXPRESSION (gen_wr_req.id_q == SelHwReq)
                --------------1--------------
-1-StatusTests
0CoveredT5,T6,T7
1CoveredT1,T2,T3

Branch Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_en_cdc.u_arb
Line No.TotalCoveredPercent
Branches 23 18 78.26
IF 111 2 2 100.00
IF 121 4 2 50.00
IF 139 4 4 100.00
IF 155 6 5 83.33
CASE 197 7 5 71.43

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc_arb.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 111 if ((!rst_dst_ni))

Branches:
-1-StatusTests
1 Covered T5,T6,T7
0 Covered T5,T6,T7


LineNo. Expression -1-: 121 if ((!rst_dst_ni)) -2-: 123 if ((gen_wr_req.dst_req_q && gen_wr_req.dst_lat_d)) -3-: 129 if (((dst_req_i && (!gen_wr_req.dst_req_q)) && gen_wr_req.busy))

Branches:
-1--2--3-StatusTests
1 - - Covered T5,T6,T7
0 1 - Not Covered
0 0 1 Not Covered
0 0 0 Covered T5,T6,T7


LineNo. Expression -1-: 139 if ((!rst_dst_ni)) -2-: 141 if (gen_wr_req.dst_lat_d) -3-: 143 if (gen_wr_req.dst_lat_q)

Branches:
-1--2--3-StatusTests
1 - - Covered T5,T6,T7
0 1 - Covered T1,T2,T4
0 0 1 Covered T1,T2,T3
0 0 0 Covered T5,T6,T7


LineNo. Expression -1-: 155 if ((!rst_dst_ni)) -2-: 157 if ((gen_wr_req.dst_update_req && gen_wr_req.dst_update_ack)) -3-: 159 if ((gen_wr_req.dst_req && gen_wr_req.dst_lat_d)) -4-: 161 if (((!gen_wr_req.dst_req) && gen_wr_req.dst_lat_d)) -5-: 163 if (gen_wr_req.dst_lat_q)

Branches:
-1--2--3--4--5-StatusTests
1 - - - - Covered T5,T6,T7
0 1 - - - Covered T1,T2,T4
0 0 1 - - Covered T1,T2,T4
0 0 0 1 - Not Covered
0 0 0 0 1 Covered T1,T2,T3
0 0 0 0 0 Covered T5,T6,T7


LineNo. Expression -1-: 197 case (gen_wr_req.state_q) -2-: 200 if (gen_wr_req.dst_req) -3-: 204 if (dst_update) -4-: 207 if ((dst_qs_o != dst_qs_i)) -5-: 217 if (gen_wr_req.dst_update_ack)

Branches:
-1--2--3--4--5-StatusTests
StIdle 1 - - - Covered T1,T2,T4
StIdle 0 1 - - Not Covered
StIdle 0 0 1 - Covered T1,T2,T3
StIdle 0 0 0 - Covered T1,T2,T4
StWait - - - 1 Covered T1,T2,T4
StWait - - - 0 Covered T1,T2,T4
default - - - - Not Covered


Assert Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_en_cdc.u_arb
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 1 50.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 1 50.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
gen_wr_req.DstUpdateReqCheck_A 223910640 0 0 979
gen_wr_req.HwIdSelCheck_A 223910640 640 0 0


gen_wr_req.DstUpdateReqCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 223910640 0 0 979

gen_wr_req.HwIdSelCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 223910640 640 0 0
T1 118070 3 0 0
T2 768287 17 0 0
T3 284364 6 0 0
T4 28697 0 0 0
T11 0 6 0 0
T12 0 4 0 0
T13 0 2 0 0
T14 0 4 0 0
T15 0 1 0 0
T16 0 2 0 0
T17 0 1 0 0
T18 9219 0 0 0
T19 1995 0 0 0
T20 5283 0 0 0
T21 4775 0 0 0
T22 2084 0 0 0
T23 2589 0 0 0

Line Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_en_cdc.u_arb
Line No.TotalCoveredPercent
TOTAL504590.00
CONT_ASSIGN10011100.00
ALWAYS11133100.00
ALWAYS1216466.67
CONT_ASSIGN13511100.00
ALWAYS13966100.00
ALWAYS15510990.00
CONT_ASSIGN18311100.00
ALWAYS187191789.47
CONT_ASSIGN22811100.00
CONT_ASSIGN24311100.00
CONT_ASSIGN24411100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc_arb.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
100 1 1
111 1 1
112 1 1
114 1 1
121 1 1
122 1 1
123 1 1
128 0 1
129 1 1
132 0 1
MISSING_ELSE
135 1 1
139 1 1
140 1 1
141 1 1
142 1 1
143 1 1
144 1 1
MISSING_ELSE
155 1 1
156 1 1
157 1 1
158 1 1
159 1 1
160 1 1
161 1 1
162 0 1
163 1 1
164 1 1
MISSING_ELSE
183 1 1
187 1 1
188 1 1
192 1 1
193 1 1
195 1 1
197 1 1
199 1 1
200 1 1
202 1 1
203 1 1
204 1 1
205 0 1
206 0 1
207 1 1
210 1 1
211 1 1
MISSING_ELSE
216 1 1
217 1 1
218 1 1
MISSING_ELSE
228 1 1
243 1 1
244 1 1


Cond Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_en_cdc.u_arb
TotalCoveredPercent
Conditions423276.19
Logical423276.19
Non-Logical00
Event00

 LINE       100
 EXPRESSION (dst_update_i & (dst_qs_o != dst_ds_i))
             ------1-----   -----------2----------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT1,T2,T4

 LINE       100
 SUB-EXPRESSION (dst_qs_o != dst_ds_i)
                -----------1----------
-1-StatusTests
0CoveredT5,T6,T7
1CoveredT1,T2,T4

 LINE       123
 EXPRESSION (gen_wr_req.dst_req_q && gen_wr_req.dst_lat_d)
             ----------1---------    ----------2---------
-1--2-StatusTests
01CoveredT1,T2,T4
10Not Covered
11Not Covered

 LINE       129
 EXPRESSION (dst_req_i && ((!gen_wr_req.dst_req_q)) && gen_wr_req.busy)
             ----1----    ------------2------------    -------3-------
-1--2--3-StatusTests
011CoveredT1,T2,T4
101Not Covered
110CoveredT1,T2,T4
111Not Covered

 LINE       135
 EXPRESSION (gen_wr_req.dst_req_q | dst_req_i)
             ----------1---------   ----2----
-1--2-StatusTests
00CoveredT5,T6,T7
01CoveredT1,T2,T4
10Not Covered

 LINE       157
 EXPRESSION (gen_wr_req.dst_update_req && gen_wr_req.dst_update_ack)
             ------------1------------    ------------2------------
-1--2-StatusTests
01Not Covered
10CoveredT1,T2,T4
11CoveredT1,T2,T4

 LINE       159
 EXPRESSION (gen_wr_req.dst_req && gen_wr_req.dst_lat_d)
             ---------1--------    ----------2---------
-1--2-StatusTests
01Not Covered
10Not Covered
11CoveredT1,T2,T4

 LINE       161
 EXPRESSION (((!gen_wr_req.dst_req)) && gen_wr_req.dst_lat_d)
             -----------1-----------    ----------2---------
-1--2-StatusTestsExclude Annotation
01Excluded VC_COV_UNR
10CoveredT5,T6,T7
11Not Covered

 LINE       183
 EXPRESSION (((~gen_wr_req.busy)) & gen_wr_req.dst_req)
             ----------1---------   ---------2--------
-1--2-StatusTests
01Not Covered
10CoveredT5,T6,T7
11CoveredT1,T2,T4

 LINE       207
 EXPRESSION (dst_qs_o != dst_qs_i)
            -----------1----------
-1-StatusTests
0CoveredT1,T2,T4
1CoveredT1,T2,T3

 LINE       228
 EXPRESSION (gen_wr_req.dst_hold_req | gen_wr_req.dst_lat_d | gen_wr_req.dst_lat_q)
             -----------1-----------   ----------2---------   ----------3---------
-1--2--3-StatusTests
000CoveredT5,T6,T7
001CoveredT1,T2,T3
010CoveredT1,T2,T4
100CoveredT1,T2,T4

 LINE       243
 EXPRESSION (gen_wr_req.src_req & (gen_wr_req.id_q == SelSwReq))
             ---------1--------   --------------2--------------
-1--2-StatusTests
01CoveredT5,T6,T7
10CoveredT1,T2,T3
11CoveredT1,T2,T4

 LINE       243
 SUB-EXPRESSION (gen_wr_req.id_q == SelSwReq)
                --------------1--------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT5,T6,T7

 LINE       244
 EXPRESSION (gen_wr_req.src_req & (gen_wr_req.id_q == SelHwReq))
             ---------1--------   --------------2--------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T4
11CoveredT1,T2,T3

 LINE       244
 SUB-EXPRESSION (gen_wr_req.id_q == SelHwReq)
                --------------1--------------
-1-StatusTests
0CoveredT5,T6,T7
1CoveredT1,T2,T3

Branch Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_en_cdc.u_arb
Line No.TotalCoveredPercent
Branches 23 18 78.26
IF 111 2 2 100.00
IF 121 4 2 50.00
IF 139 4 4 100.00
IF 155 6 5 83.33
CASE 197 7 5 71.43

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc_arb.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 111 if ((!rst_dst_ni))

Branches:
-1-StatusTests
1 Covered T5,T6,T7
0 Covered T5,T6,T7


LineNo. Expression -1-: 121 if ((!rst_dst_ni)) -2-: 123 if ((gen_wr_req.dst_req_q && gen_wr_req.dst_lat_d)) -3-: 129 if (((dst_req_i && (!gen_wr_req.dst_req_q)) && gen_wr_req.busy))

Branches:
-1--2--3-StatusTests
1 - - Covered T5,T6,T7
0 1 - Not Covered
0 0 1 Not Covered
0 0 0 Covered T5,T6,T7


LineNo. Expression -1-: 139 if ((!rst_dst_ni)) -2-: 141 if (gen_wr_req.dst_lat_d) -3-: 143 if (gen_wr_req.dst_lat_q)

Branches:
-1--2--3-StatusTests
1 - - Covered T5,T6,T7
0 1 - Covered T1,T2,T4
0 0 1 Covered T1,T2,T3
0 0 0 Covered T5,T6,T7


LineNo. Expression -1-: 155 if ((!rst_dst_ni)) -2-: 157 if ((gen_wr_req.dst_update_req && gen_wr_req.dst_update_ack)) -3-: 159 if ((gen_wr_req.dst_req && gen_wr_req.dst_lat_d)) -4-: 161 if (((!gen_wr_req.dst_req) && gen_wr_req.dst_lat_d)) -5-: 163 if (gen_wr_req.dst_lat_q)

Branches:
-1--2--3--4--5-StatusTests
1 - - - - Covered T5,T6,T7
0 1 - - - Covered T1,T2,T4
0 0 1 - - Covered T1,T2,T4
0 0 0 1 - Not Covered
0 0 0 0 1 Covered T1,T2,T3
0 0 0 0 0 Covered T5,T6,T7


LineNo. Expression -1-: 197 case (gen_wr_req.state_q) -2-: 200 if (gen_wr_req.dst_req) -3-: 204 if (dst_update) -4-: 207 if ((dst_qs_o != dst_qs_i)) -5-: 217 if (gen_wr_req.dst_update_ack)

Branches:
-1--2--3--4--5-StatusTests
StIdle 1 - - - Covered T1,T2,T4
StIdle 0 1 - - Not Covered
StIdle 0 0 1 - Covered T1,T2,T3
StIdle 0 0 0 - Covered T1,T2,T4
StWait - - - 1 Covered T1,T2,T4
StWait - - - 0 Covered T1,T2,T4
default - - - - Not Covered


Assert Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_en_cdc.u_arb
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 1 50.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 1 50.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
gen_wr_req.DstUpdateReqCheck_A 111190200 0 0 979
gen_wr_req.HwIdSelCheck_A 111190200 640 0 0


gen_wr_req.DstUpdateReqCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 111190200 0 0 979

gen_wr_req.HwIdSelCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 111190200 640 0 0
T1 59023 3 0 0
T2 383768 17 0 0
T3 142179 6 0 0
T4 10237 0 0 0
T11 0 6 0 0
T12 0 4 0 0
T13 0 2 0 0
T14 0 4 0 0
T15 0 1 0 0
T16 0 2 0 0
T17 0 1 0 0
T18 5099 0 0 0
T19 1078 0 0 0
T20 2575 0 0 0
T21 2702 0 0 0
T22 1162 0 0 0
T23 1268 0 0 0

Line Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_en_cdc.u_arb
Line No.TotalCoveredPercent
TOTAL504590.00
CONT_ASSIGN10011100.00
ALWAYS11133100.00
ALWAYS1216466.67
CONT_ASSIGN13511100.00
ALWAYS13966100.00
ALWAYS15510990.00
CONT_ASSIGN18311100.00
ALWAYS187191789.47
CONT_ASSIGN22811100.00
CONT_ASSIGN24311100.00
CONT_ASSIGN24411100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc_arb.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
100 1 1
111 1 1
112 1 1
114 1 1
121 1 1
122 1 1
123 1 1
128 0 1
129 1 1
132 0 1
MISSING_ELSE
135 1 1
139 1 1
140 1 1
141 1 1
142 1 1
143 1 1
144 1 1
MISSING_ELSE
155 1 1
156 1 1
157 1 1
158 1 1
159 1 1
160 1 1
161 1 1
162 0 1
163 1 1
164 1 1
MISSING_ELSE
183 1 1
187 1 1
188 1 1
192 1 1
193 1 1
195 1 1
197 1 1
199 1 1
200 1 1
202 1 1
203 1 1
204 1 1
205 0 1
206 0 1
207 1 1
210 1 1
211 1 1
MISSING_ELSE
216 1 1
217 1 1
218 1 1
MISSING_ELSE
228 1 1
243 1 1
244 1 1


Cond Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_en_cdc.u_arb
TotalCoveredPercent
Conditions423276.19
Logical423276.19
Non-Logical00
Event00

 LINE       100
 EXPRESSION (dst_update_i & (dst_qs_o != dst_ds_i))
             ------1-----   -----------2----------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT1,T2,T4

 LINE       100
 SUB-EXPRESSION (dst_qs_o != dst_ds_i)
                -----------1----------
-1-StatusTests
0CoveredT5,T6,T7
1CoveredT1,T2,T4

 LINE       123
 EXPRESSION (gen_wr_req.dst_req_q && gen_wr_req.dst_lat_d)
             ----------1---------    ----------2---------
-1--2-StatusTests
01CoveredT1,T2,T4
10Not Covered
11Not Covered

 LINE       129
 EXPRESSION (dst_req_i && ((!gen_wr_req.dst_req_q)) && gen_wr_req.busy)
             ----1----    ------------2------------    -------3-------
-1--2--3-StatusTests
011CoveredT1,T2,T4
101Not Covered
110CoveredT1,T2,T4
111Not Covered

 LINE       135
 EXPRESSION (gen_wr_req.dst_req_q | dst_req_i)
             ----------1---------   ----2----
-1--2-StatusTests
00CoveredT5,T6,T7
01CoveredT1,T2,T4
10Not Covered

 LINE       157
 EXPRESSION (gen_wr_req.dst_update_req && gen_wr_req.dst_update_ack)
             ------------1------------    ------------2------------
-1--2-StatusTests
01Not Covered
10CoveredT1,T2,T4
11CoveredT1,T2,T4

 LINE       159
 EXPRESSION (gen_wr_req.dst_req && gen_wr_req.dst_lat_d)
             ---------1--------    ----------2---------
-1--2-StatusTests
01Not Covered
10Not Covered
11CoveredT1,T2,T4

 LINE       161
 EXPRESSION (((!gen_wr_req.dst_req)) && gen_wr_req.dst_lat_d)
             -----------1-----------    ----------2---------
-1--2-StatusTestsExclude Annotation
01Excluded VC_COV_UNR
10CoveredT5,T6,T7
11Not Covered

 LINE       183
 EXPRESSION (((~gen_wr_req.busy)) & gen_wr_req.dst_req)
             ----------1---------   ---------2--------
-1--2-StatusTests
01Not Covered
10CoveredT5,T6,T7
11CoveredT1,T2,T4

 LINE       207
 EXPRESSION (dst_qs_o != dst_qs_i)
            -----------1----------
-1-StatusTests
0CoveredT1,T2,T4
1CoveredT1,T2,T3

 LINE       228
 EXPRESSION (gen_wr_req.dst_hold_req | gen_wr_req.dst_lat_d | gen_wr_req.dst_lat_q)
             -----------1-----------   ----------2---------   ----------3---------
-1--2--3-StatusTests
000CoveredT5,T6,T7
001CoveredT1,T2,T3
010CoveredT1,T2,T4
100CoveredT1,T2,T4

 LINE       243
 EXPRESSION (gen_wr_req.src_req & (gen_wr_req.id_q == SelSwReq))
             ---------1--------   --------------2--------------
-1--2-StatusTests
01CoveredT5,T6,T7
10CoveredT1,T2,T3
11CoveredT1,T2,T4

 LINE       243
 SUB-EXPRESSION (gen_wr_req.id_q == SelSwReq)
                --------------1--------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT5,T6,T7

 LINE       244
 EXPRESSION (gen_wr_req.src_req & (gen_wr_req.id_q == SelHwReq))
             ---------1--------   --------------2--------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T4
11CoveredT1,T2,T3

 LINE       244
 SUB-EXPRESSION (gen_wr_req.id_q == SelHwReq)
                --------------1--------------
-1-StatusTests
0CoveredT5,T6,T7
1CoveredT1,T2,T3

Branch Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_en_cdc.u_arb
Line No.TotalCoveredPercent
Branches 23 18 78.26
IF 111 2 2 100.00
IF 121 4 2 50.00
IF 139 4 4 100.00
IF 155 6 5 83.33
CASE 197 7 5 71.43

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc_arb.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 111 if ((!rst_dst_ni))

Branches:
-1-StatusTests
1 Covered T5,T6,T7
0 Covered T5,T6,T7


LineNo. Expression -1-: 121 if ((!rst_dst_ni)) -2-: 123 if ((gen_wr_req.dst_req_q && gen_wr_req.dst_lat_d)) -3-: 129 if (((dst_req_i && (!gen_wr_req.dst_req_q)) && gen_wr_req.busy))

Branches:
-1--2--3-StatusTests
1 - - Covered T5,T6,T7
0 1 - Not Covered
0 0 1 Not Covered
0 0 0 Covered T5,T6,T7


LineNo. Expression -1-: 139 if ((!rst_dst_ni)) -2-: 141 if (gen_wr_req.dst_lat_d) -3-: 143 if (gen_wr_req.dst_lat_q)

Branches:
-1--2--3-StatusTests
1 - - Covered T5,T6,T7
0 1 - Covered T1,T2,T4
0 0 1 Covered T1,T2,T3
0 0 0 Covered T5,T6,T7


LineNo. Expression -1-: 155 if ((!rst_dst_ni)) -2-: 157 if ((gen_wr_req.dst_update_req && gen_wr_req.dst_update_ack)) -3-: 159 if ((gen_wr_req.dst_req && gen_wr_req.dst_lat_d)) -4-: 161 if (((!gen_wr_req.dst_req) && gen_wr_req.dst_lat_d)) -5-: 163 if (gen_wr_req.dst_lat_q)

Branches:
-1--2--3--4--5-StatusTests
1 - - - - Covered T5,T6,T7
0 1 - - - Covered T1,T2,T4
0 0 1 - - Covered T1,T2,T4
0 0 0 1 - Not Covered
0 0 0 0 1 Covered T1,T2,T3
0 0 0 0 0 Covered T5,T6,T7


LineNo. Expression -1-: 197 case (gen_wr_req.state_q) -2-: 200 if (gen_wr_req.dst_req) -3-: 204 if (dst_update) -4-: 207 if ((dst_qs_o != dst_qs_i)) -5-: 217 if (gen_wr_req.dst_update_ack)

Branches:
-1--2--3--4--5-StatusTests
StIdle 1 - - - Covered T1,T2,T4
StIdle 0 1 - - Not Covered
StIdle 0 0 1 - Covered T1,T2,T3
StIdle 0 0 0 - Covered T1,T2,T4
StWait - - - 1 Covered T1,T2,T4
StWait - - - 0 Covered T1,T2,T4
default - - - - Not Covered


Assert Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_en_cdc.u_arb
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 1 50.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 1 50.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
gen_wr_req.DstUpdateReqCheck_A 239150230 0 0 979
gen_wr_req.HwIdSelCheck_A 239150230 640 0 0


gen_wr_req.DstUpdateReqCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 239150230 0 0 979

gen_wr_req.HwIdSelCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 239150230 640 0 0
T1 122993 3 0 0
T2 812325 17 0 0
T3 296222 6 0 0
T4 29894 0 0 0
T11 0 6 0 0
T12 0 4 0 0
T13 0 2 0 0
T14 0 4 0 0
T15 0 1 0 0
T16 0 2 0 0
T17 0 1 0 0
T18 9604 0 0 0
T19 2079 0 0 0
T20 5503 0 0 0
T21 4975 0 0 0
T22 2170 0 0 0
T23 2697 0 0 0

Line Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_en_cdc.u_arb
Line No.TotalCoveredPercent
TOTAL504590.00
CONT_ASSIGN10011100.00
ALWAYS11133100.00
ALWAYS1216466.67
CONT_ASSIGN13511100.00
ALWAYS13966100.00
ALWAYS15510990.00
CONT_ASSIGN18311100.00
ALWAYS187191789.47
CONT_ASSIGN22811100.00
CONT_ASSIGN24311100.00
CONT_ASSIGN24411100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc_arb.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
100 1 1
111 1 1
112 1 1
114 1 1
121 1 1
122 1 1
123 1 1
128 0 1
129 1 1
132 0 1
MISSING_ELSE
135 1 1
139 1 1
140 1 1
141 1 1
142 1 1
143 1 1
144 1 1
MISSING_ELSE
155 1 1
156 1 1
157 1 1
158 1 1
159 1 1
160 1 1
161 1 1
162 0 1
163 1 1
164 1 1
MISSING_ELSE
183 1 1
187 1 1
188 1 1
192 1 1
193 1 1
195 1 1
197 1 1
199 1 1
200 1 1
202 1 1
203 1 1
204 1 1
205 0 1
206 0 1
207 1 1
210 1 1
211 1 1
MISSING_ELSE
216 1 1
217 1 1
218 1 1
MISSING_ELSE
228 1 1
243 1 1
244 1 1


Cond Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_en_cdc.u_arb
TotalCoveredPercent
Conditions423276.19
Logical423276.19
Non-Logical00
Event00

 LINE       100
 EXPRESSION (dst_update_i & (dst_qs_o != dst_ds_i))
             ------1-----   -----------2----------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T4
11CoveredT1,T2,T4

 LINE       100
 SUB-EXPRESSION (dst_qs_o != dst_ds_i)
                -----------1----------
-1-StatusTests
0CoveredT5,T6,T7
1CoveredT1,T2,T4

 LINE       123
 EXPRESSION (gen_wr_req.dst_req_q && gen_wr_req.dst_lat_d)
             ----------1---------    ----------2---------
-1--2-StatusTests
01CoveredT1,T2,T4
10Not Covered
11Not Covered

 LINE       129
 EXPRESSION (dst_req_i && ((!gen_wr_req.dst_req_q)) && gen_wr_req.busy)
             ----1----    ------------2------------    -------3-------
-1--2--3-StatusTests
011CoveredT1,T2,T4
101Not Covered
110CoveredT1,T2,T4
111Not Covered

 LINE       135
 EXPRESSION (gen_wr_req.dst_req_q | dst_req_i)
             ----------1---------   ----2----
-1--2-StatusTests
00CoveredT5,T6,T7
01CoveredT1,T2,T4
10Not Covered

 LINE       157
 EXPRESSION (gen_wr_req.dst_update_req && gen_wr_req.dst_update_ack)
             ------------1------------    ------------2------------
-1--2-StatusTests
01Not Covered
10CoveredT1,T2,T4
11CoveredT1,T2,T4

 LINE       159
 EXPRESSION (gen_wr_req.dst_req && gen_wr_req.dst_lat_d)
             ---------1--------    ----------2---------
-1--2-StatusTests
01Not Covered
10Not Covered
11CoveredT1,T2,T4

 LINE       161
 EXPRESSION (((!gen_wr_req.dst_req)) && gen_wr_req.dst_lat_d)
             -----------1-----------    ----------2---------
-1--2-StatusTestsExclude Annotation
01Excluded VC_COV_UNR
10CoveredT5,T6,T7
11Not Covered

 LINE       183
 EXPRESSION (((~gen_wr_req.busy)) & gen_wr_req.dst_req)
             ----------1---------   ---------2--------
-1--2-StatusTests
01Not Covered
10CoveredT5,T6,T7
11CoveredT1,T2,T4

 LINE       207
 EXPRESSION (dst_qs_o != dst_qs_i)
            -----------1----------
-1-StatusTests
0CoveredT1,T2,T4
1CoveredT1,T2,T3

 LINE       228
 EXPRESSION (gen_wr_req.dst_hold_req | gen_wr_req.dst_lat_d | gen_wr_req.dst_lat_q)
             -----------1-----------   ----------2---------   ----------3---------
-1--2--3-StatusTests
000CoveredT5,T6,T7
001CoveredT1,T2,T3
010CoveredT1,T2,T4
100CoveredT1,T2,T4

 LINE       243
 EXPRESSION (gen_wr_req.src_req & (gen_wr_req.id_q == SelSwReq))
             ---------1--------   --------------2--------------
-1--2-StatusTests
01CoveredT5,T6,T7
10CoveredT1,T2,T3
11CoveredT1,T2,T4

 LINE       243
 SUB-EXPRESSION (gen_wr_req.id_q == SelSwReq)
                --------------1--------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT5,T6,T7

 LINE       244
 EXPRESSION (gen_wr_req.src_req & (gen_wr_req.id_q == SelHwReq))
             ---------1--------   --------------2--------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T4
11CoveredT1,T2,T3

 LINE       244
 SUB-EXPRESSION (gen_wr_req.id_q == SelHwReq)
                --------------1--------------
-1-StatusTests
0CoveredT5,T6,T7
1CoveredT1,T2,T3

Branch Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_en_cdc.u_arb
Line No.TotalCoveredPercent
Branches 23 18 78.26
IF 111 2 2 100.00
IF 121 4 2 50.00
IF 139 4 4 100.00
IF 155 6 5 83.33
CASE 197 7 5 71.43

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc_arb.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 111 if ((!rst_dst_ni))

Branches:
-1-StatusTests
1 Covered T5,T6,T7
0 Covered T5,T6,T7


LineNo. Expression -1-: 121 if ((!rst_dst_ni)) -2-: 123 if ((gen_wr_req.dst_req_q && gen_wr_req.dst_lat_d)) -3-: 129 if (((dst_req_i && (!gen_wr_req.dst_req_q)) && gen_wr_req.busy))

Branches:
-1--2--3-StatusTests
1 - - Covered T5,T6,T7
0 1 - Not Covered
0 0 1 Not Covered
0 0 0 Covered T5,T6,T7


LineNo. Expression -1-: 139 if ((!rst_dst_ni)) -2-: 141 if (gen_wr_req.dst_lat_d) -3-: 143 if (gen_wr_req.dst_lat_q)

Branches:
-1--2--3-StatusTests
1 - - Covered T5,T6,T7
0 1 - Covered T1,T2,T4
0 0 1 Covered T1,T2,T3
0 0 0 Covered T5,T6,T7


LineNo. Expression -1-: 155 if ((!rst_dst_ni)) -2-: 157 if ((gen_wr_req.dst_update_req && gen_wr_req.dst_update_ack)) -3-: 159 if ((gen_wr_req.dst_req && gen_wr_req.dst_lat_d)) -4-: 161 if (((!gen_wr_req.dst_req) && gen_wr_req.dst_lat_d)) -5-: 163 if (gen_wr_req.dst_lat_q)

Branches:
-1--2--3--4--5-StatusTests
1 - - - - Covered T5,T6,T7
0 1 - - - Covered T1,T2,T4
0 0 1 - - Covered T1,T2,T4
0 0 0 1 - Not Covered
0 0 0 0 1 Covered T1,T2,T3
0 0 0 0 0 Covered T5,T6,T7


LineNo. Expression -1-: 197 case (gen_wr_req.state_q) -2-: 200 if (gen_wr_req.dst_req) -3-: 204 if (dst_update) -4-: 207 if ((dst_qs_o != dst_qs_i)) -5-: 217 if (gen_wr_req.dst_update_ack)

Branches:
-1--2--3--4--5-StatusTests
StIdle 1 - - - Covered T1,T2,T4
StIdle 0 1 - - Not Covered
StIdle 0 0 1 - Covered T1,T2,T3
StIdle 0 0 0 - Covered T1,T2,T4
StWait - - - 1 Covered T1,T2,T4
StWait - - - 0 Covered T1,T2,T4
default - - - - Not Covered


Assert Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_en_cdc.u_arb
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 1 50.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 1 50.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
gen_wr_req.DstUpdateReqCheck_A 114657872 0 0 979
gen_wr_req.HwIdSelCheck_A 114657872 640 0 0


gen_wr_req.DstUpdateReqCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 114657872 0 0 979

gen_wr_req.HwIdSelCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 114657872 640 0 0
T1 59037 3 0 0
T2 384162 17 0 0
T3 142189 6 0 0
T4 14349 0 0 0
T11 0 6 0 0
T12 0 4 0 0
T13 0 2 0 0
T14 0 4 0 0
T15 0 1 0 0
T16 0 2 0 0
T17 0 1 0 0
T18 4609 0 0 0
T19 997 0 0 0
T20 2641 0 0 0
T21 2388 0 0 0
T22 1042 0 0 0
T23 1295 0 0 0

Line Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_en_cdc.u_arb
Line No.TotalCoveredPercent
TOTAL504794.00
CONT_ASSIGN10011100.00
ALWAYS11133100.00
ALWAYS12166100.00
CONT_ASSIGN13511100.00
ALWAYS13966100.00
ALWAYS15510990.00
CONT_ASSIGN18311100.00
ALWAYS187191789.47
CONT_ASSIGN22811100.00
CONT_ASSIGN24311100.00
CONT_ASSIGN24411100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc_arb.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
100 1 1
111 1 1
112 1 1
114 1 1
121 1 1
122 1 1
123 1 1
128 1 1
129 1 1
132 1 1
MISSING_ELSE
135 1 1
139 1 1
140 1 1
141 1 1
142 1 1
143 1 1
144 1 1
MISSING_ELSE
155 1 1
156 1 1
157 1 1
158 1 1
159 1 1
160 1 1
161 1 1
162 0 1
163 1 1
164 1 1
MISSING_ELSE
183 1 1
187 1 1
188 1 1
192 1 1
193 1 1
195 1 1
197 1 1
199 1 1
200 1 1
202 1 1
203 1 1
204 1 1
205 0 1
206 0 1
207 1 1
210 1 1
211 1 1
MISSING_ELSE
216 1 1
217 1 1
218 1 1
MISSING_ELSE
228 1 1
243 1 1
244 1 1


Cond Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_en_cdc.u_arb
TotalCoveredPercent
Conditions423685.71
Logical423685.71
Non-Logical00
Event00

 LINE       100
 EXPRESSION (dst_update_i & (dst_qs_o != dst_ds_i))
             ------1-----   -----------2----------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T4
11CoveredT1,T2,T4

 LINE       100
 SUB-EXPRESSION (dst_qs_o != dst_ds_i)
                -----------1----------
-1-StatusTests
0CoveredT5,T6,T7
1CoveredT1,T2,T4

 LINE       123
 EXPRESSION (gen_wr_req.dst_req_q && gen_wr_req.dst_lat_d)
             ----------1---------    ----------2---------
-1--2-StatusTests
01CoveredT1,T2,T4
10Not Covered
11CoveredT8,T9,T10

 LINE       129
 EXPRESSION (dst_req_i && ((!gen_wr_req.dst_req_q)) && gen_wr_req.busy)
             ----1----    ------------2------------    -------3-------
-1--2--3-StatusTests
011CoveredT1,T2,T4
101Not Covered
110CoveredT1,T2,T4
111CoveredT8,T9,T10

 LINE       135
 EXPRESSION (gen_wr_req.dst_req_q | dst_req_i)
             ----------1---------   ----2----
-1--2-StatusTests
00CoveredT5,T6,T7
01CoveredT1,T2,T4
10CoveredT8,T9,T10

 LINE       157
 EXPRESSION (gen_wr_req.dst_update_req && gen_wr_req.dst_update_ack)
             ------------1------------    ------------2------------
-1--2-StatusTests
01Not Covered
10CoveredT1,T2,T4
11CoveredT1,T2,T4

 LINE       159
 EXPRESSION (gen_wr_req.dst_req && gen_wr_req.dst_lat_d)
             ---------1--------    ----------2---------
-1--2-StatusTests
01Not Covered
10Not Covered
11CoveredT1,T2,T4

 LINE       161
 EXPRESSION (((!gen_wr_req.dst_req)) && gen_wr_req.dst_lat_d)
             -----------1-----------    ----------2---------
-1--2-StatusTestsExclude Annotation
01Excluded VC_COV_UNR
10CoveredT5,T6,T7
11Not Covered

 LINE       183
 EXPRESSION (((~gen_wr_req.busy)) & gen_wr_req.dst_req)
             ----------1---------   ---------2--------
-1--2-StatusTests
01CoveredT8,T9,T10
10CoveredT5,T6,T7
11CoveredT1,T2,T4

 LINE       207
 EXPRESSION (dst_qs_o != dst_qs_i)
            -----------1----------
-1-StatusTests
0CoveredT1,T2,T4
1CoveredT1,T2,T3

 LINE       228
 EXPRESSION (gen_wr_req.dst_hold_req | gen_wr_req.dst_lat_d | gen_wr_req.dst_lat_q)
             -----------1-----------   ----------2---------   ----------3---------
-1--2--3-StatusTests
000CoveredT5,T6,T7
001CoveredT1,T2,T3
010CoveredT1,T2,T4
100CoveredT1,T2,T4

 LINE       243
 EXPRESSION (gen_wr_req.src_req & (gen_wr_req.id_q == SelSwReq))
             ---------1--------   --------------2--------------
-1--2-StatusTests
01CoveredT5,T6,T7
10CoveredT1,T2,T3
11CoveredT1,T2,T4

 LINE       243
 SUB-EXPRESSION (gen_wr_req.id_q == SelSwReq)
                --------------1--------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT5,T6,T7

 LINE       244
 EXPRESSION (gen_wr_req.src_req & (gen_wr_req.id_q == SelHwReq))
             ---------1--------   --------------2--------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T4
11CoveredT1,T2,T3

 LINE       244
 SUB-EXPRESSION (gen_wr_req.id_q == SelHwReq)
                --------------1--------------
-1-StatusTests
0CoveredT5,T6,T7
1CoveredT1,T2,T3

Branch Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_en_cdc.u_arb
Line No.TotalCoveredPercent
Branches 23 20 86.96
IF 111 2 2 100.00
IF 121 4 4 100.00
IF 139 4 4 100.00
IF 155 6 5 83.33
CASE 197 7 5 71.43

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc_arb.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 111 if ((!rst_dst_ni))

Branches:
-1-StatusTests
1 Covered T5,T6,T7
0 Covered T5,T6,T7


LineNo. Expression -1-: 121 if ((!rst_dst_ni)) -2-: 123 if ((gen_wr_req.dst_req_q && gen_wr_req.dst_lat_d)) -3-: 129 if (((dst_req_i && (!gen_wr_req.dst_req_q)) && gen_wr_req.busy))

Branches:
-1--2--3-StatusTests
1 - - Covered T5,T6,T7
0 1 - Covered T8,T9,T10
0 0 1 Covered T8,T9,T10
0 0 0 Covered T5,T6,T7


LineNo. Expression -1-: 139 if ((!rst_dst_ni)) -2-: 141 if (gen_wr_req.dst_lat_d) -3-: 143 if (gen_wr_req.dst_lat_q)

Branches:
-1--2--3-StatusTests
1 - - Covered T5,T6,T7
0 1 - Covered T1,T2,T4
0 0 1 Covered T1,T2,T3
0 0 0 Covered T5,T6,T7


LineNo. Expression -1-: 155 if ((!rst_dst_ni)) -2-: 157 if ((gen_wr_req.dst_update_req && gen_wr_req.dst_update_ack)) -3-: 159 if ((gen_wr_req.dst_req && gen_wr_req.dst_lat_d)) -4-: 161 if (((!gen_wr_req.dst_req) && gen_wr_req.dst_lat_d)) -5-: 163 if (gen_wr_req.dst_lat_q)

Branches:
-1--2--3--4--5-StatusTests
1 - - - - Covered T5,T6,T7
0 1 - - - Covered T1,T2,T4
0 0 1 - - Covered T1,T2,T4
0 0 0 1 - Not Covered
0 0 0 0 1 Covered T1,T2,T3
0 0 0 0 0 Covered T5,T6,T7


LineNo. Expression -1-: 197 case (gen_wr_req.state_q) -2-: 200 if (gen_wr_req.dst_req) -3-: 204 if (dst_update) -4-: 207 if ((dst_qs_o != dst_qs_i)) -5-: 217 if (gen_wr_req.dst_update_ack)

Branches:
-1--2--3--4--5-StatusTests
StIdle 1 - - - Covered T1,T2,T4
StIdle 0 1 - - Not Covered
StIdle 0 0 1 - Covered T1,T2,T3
StIdle 0 0 0 - Covered T1,T2,T4
StWait - - - 1 Covered T1,T2,T4
StWait - - - 0 Covered T1,T2,T4
default - - - - Not Covered


Assert Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_en_cdc.u_arb
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 1 50.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 1 50.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
gen_wr_req.DstUpdateReqCheck_A 55594684 0 0 979
gen_wr_req.HwIdSelCheck_A 55594684 640 0 0


gen_wr_req.DstUpdateReqCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 55594684 0 0 979

gen_wr_req.HwIdSelCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 55594684 640 0 0
T1 29511 3 0 0
T2 191885 17 0 0
T3 71085 6 0 0
T4 5118 0 0 0
T11 0 6 0 0
T12 0 4 0 0
T13 0 2 0 0
T14 0 4 0 0
T15 0 1 0 0
T16 0 2 0 0
T17 0 1 0 0
T18 2548 0 0 0
T19 538 0 0 0
T20 1287 0 0 0
T21 1351 0 0 0
T22 579 0 0 0
T23 634 0 0 0

Line Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_cdc.u_arb
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN10000
CONT_ASSIGN28311100.00
CONT_ASSIGN28411100.00
CONT_ASSIGN29900
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc_arb.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
100 unreachable
283 1 1
284 1 1
299 unreachable


Cond Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_cdc.u_arb
TotalCoveredPercent
Conditions3266.67
Logical3266.67
Non-Logical00
Event00

 LINE       100
 EXPRESSION (dst_update_i & (dst_qs_o != dst_ds_i))
             ------1-----   -----------2----------
-1--2-StatusTests
01CoveredT5,T6,T7
10Unreachable
11Unreachable

 LINE       100
 SUB-EXPRESSION (dst_qs_o != dst_ds_i)
                -----------1----------
-1-StatusTests
0Not Covered
1CoveredT5,T6,T7
Line Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_cdc.u_arb
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN10000
CONT_ASSIGN28311100.00
CONT_ASSIGN28411100.00
CONT_ASSIGN29900
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc_arb.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
100 unreachable
283 1 1
284 1 1
299 unreachable


Cond Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_cdc.u_arb
TotalCoveredPercent
Conditions3266.67
Logical3266.67
Non-Logical00
Event00

 LINE       100
 EXPRESSION (dst_update_i & (dst_qs_o != dst_ds_i))
             ------1-----   -----------2----------
-1--2-StatusTests
01CoveredT5,T6,T7
10Unreachable
11Unreachable

 LINE       100
 SUB-EXPRESSION (dst_qs_o != dst_ds_i)
                -----------1----------
-1-StatusTests
0Not Covered
1CoveredT5,T6,T7
Line Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_cdc.u_arb
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN10000
CONT_ASSIGN28311100.00
CONT_ASSIGN28411100.00
CONT_ASSIGN29900
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc_arb.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
100 unreachable
283 1 1
284 1 1
299 unreachable


Cond Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_cdc.u_arb
TotalCoveredPercent
Conditions3266.67
Logical3266.67
Non-Logical00
Event00

 LINE       100
 EXPRESSION (dst_update_i & (dst_qs_o != dst_ds_i))
             ------1-----   -----------2----------
-1--2-StatusTests
01CoveredT5,T6,T7
10Unreachable
11Unreachable

 LINE       100
 SUB-EXPRESSION (dst_qs_o != dst_ds_i)
                -----------1----------
-1-StatusTests
0Not Covered
1CoveredT5,T6,T7
Line Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_cdc.u_arb
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN10000
CONT_ASSIGN28311100.00
CONT_ASSIGN28411100.00
CONT_ASSIGN29900
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc_arb.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
100 unreachable
283 1 1
284 1 1
299 unreachable


Cond Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_cdc.u_arb
TotalCoveredPercent
Conditions3266.67
Logical3266.67
Non-Logical00
Event00

 LINE       100
 EXPRESSION (dst_update_i & (dst_qs_o != dst_ds_i))
             ------1-----   -----------2----------
-1--2-StatusTests
01CoveredT5,T6,T7
10Unreachable
11Unreachable

 LINE       100
 SUB-EXPRESSION (dst_qs_o != dst_ds_i)
                -----------1----------
-1-StatusTests
0Not Covered
1CoveredT5,T6,T7
Line Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_cdc.u_arb
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN10000
CONT_ASSIGN28311100.00
CONT_ASSIGN28411100.00
CONT_ASSIGN29900
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc_arb.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
100 unreachable
283 1 1
284 1 1
299 unreachable


Cond Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_cdc.u_arb
TotalCoveredPercent
Conditions3266.67
Logical3266.67
Non-Logical00
Event00

 LINE       100
 EXPRESSION (dst_update_i & (dst_qs_o != dst_ds_i))
             ------1-----   -----------2----------
-1--2-StatusTests
01CoveredT5,T6,T7
10Unreachable
11Unreachable

 LINE       100
 SUB-EXPRESSION (dst_qs_o != dst_ds_i)
                -----------1----------
-1-StatusTests
0Not Covered
1CoveredT5,T6,T7
0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%