Line Coverage for Module :
prim_reg_cdc
| Line No. | Total | Covered | Percent |
TOTAL | | 22 | 22 | 100.00 |
CONT_ASSIGN | 65 | 1 | 1 | 100.00 |
ALWAYS | 71 | 6 | 6 | 100.00 |
CONT_ASSIGN | 85 | 1 | 1 | 100.00 |
CONT_ASSIGN | 109 | 1 | 1 | 100.00 |
ALWAYS | 115 | 9 | 9 | 100.00 |
CONT_ASSIGN | 150 | 1 | 1 | 100.00 |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 156 | 1 | 1 | 100.00 |
CONT_ASSIGN | 200 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
65 |
1 |
1 |
71 |
1 |
1 |
72 |
1 |
1 |
73 |
1 |
1 |
74 |
1 |
1 |
75 |
1 |
1 |
76 |
1 |
1 |
|
|
|
MISSING_ELSE |
85 |
1 |
1 |
109 |
1 |
1 |
115 |
1 |
1 |
116 |
1 |
1 |
117 |
1 |
1 |
118 |
1 |
1 |
123 |
1 |
1 |
124 |
1 |
1 |
125 |
1 |
1 |
134 |
1 |
1 |
135 |
1 |
1 |
|
|
|
MISSING_ELSE |
150 |
1 |
1 |
155 |
1 |
1 |
156 |
1 |
1 |
200 |
1 |
1 |
Cond Coverage for Module :
prim_reg_cdc
| Total | Covered | Percent |
Conditions | 15 | 13 | 86.67 |
Logical | 15 | 13 | 86.67 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 65
EXPRESSION (src_we_i | src_re_i)
----1--- ----2---
-1- | -2- | Status | Tests |
0 | 0 | Covered | T5,T6,T7 |
0 | 1 | Covered | T4,T11,T12 |
1 | 0 | Covered | T1,T2,T4 |
LINE 109
EXPRESSION (src_busy_q & ((!src_ack)))
-----1---- ------2-----
-1- | -2- | Status | Tests |
0 | 1 | Covered | T5,T6,T7 |
1 | 0 | Covered | T1,T2,T4 |
1 | 1 | Covered | T1,T2,T4 |
LINE 125
EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
-----------1----------- ------------2------------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T5,T6,T7 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T4 |
LINE 125
SUB-EXPRESSION (src_busy_q && src_ack)
-----1---- ---2---
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T1,T2,T4 |
1 | 1 | Covered | T1,T2,T4 |
LINE 125
SUB-EXPRESSION (src_update && ((!busy)))
-----1---- ----2----
-1- | -2- | Status | Tests |
0 | 1 | Covered | T5,T6,T7 |
1 | 0 | Not Covered | |
1 | 1 | Covered | T1,T2,T3 |
Branch Coverage for Module :
prim_reg_cdc
| Line No. | Total | Covered | Percent |
Branches |
|
8 |
8 |
100.00 |
IF |
71 |
4 |
4 |
100.00 |
IF |
115 |
4 |
4 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 71 if ((!rst_src_ni))
-2-: 73 if (src_req)
-3-: 75 if (src_ack)
Branches:
-1- | -2- | -3- | Status | Tests |
1 |
- |
- |
Covered |
T5,T6,T7 |
0 |
1 |
- |
Covered |
T1,T2,T4 |
0 |
0 |
1 |
Covered |
T1,T2,T4 |
0 |
0 |
0 |
Covered |
T5,T6,T7 |
LineNo. Expression
-1-: 115 if ((!rst_src_ni))
-2-: 118 if (src_req)
-3-: 125 if (((src_busy_q && src_ack) || (src_update && (!busy))))
Branches:
-1- | -2- | -3- | Status | Tests |
1 |
- |
- |
Covered |
T5,T6,T7 |
0 |
1 |
- |
Covered |
T1,T2,T4 |
0 |
0 |
1 |
Covered |
T1,T2,T4 |
0 |
0 |
0 |
Covered |
T5,T6,T7 |
Assert Coverage for Module :
prim_reg_cdc
Assertion Details
BusySrcReqChk_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
738287010 |
832548 |
0 |
0 |
T1 |
295170 |
682 |
0 |
0 |
T2 |
3899220 |
7123 |
0 |
0 |
T3 |
2932610 |
4018 |
0 |
0 |
T4 |
74720 |
411 |
0 |
0 |
T11 |
0 |
9181 |
0 |
0 |
T12 |
0 |
8978 |
0 |
0 |
T13 |
0 |
724 |
0 |
0 |
T14 |
0 |
3307 |
0 |
0 |
T15 |
0 |
1900 |
0 |
0 |
T18 |
15360 |
0 |
0 |
0 |
T19 |
20580 |
0 |
0 |
0 |
T20 |
13750 |
0 |
0 |
0 |
T21 |
12430 |
0 |
0 |
0 |
T22 |
21700 |
0 |
0 |
0 |
T23 |
6730 |
0 |
0 |
0 |
T33 |
0 |
814 |
0 |
0 |
DstReqKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1489007252 |
1467051966 |
0 |
0 |
T5 |
28008 |
26992 |
0 |
0 |
T6 |
27934 |
26626 |
0 |
0 |
T7 |
37040 |
35610 |
0 |
0 |
T24 |
26872 |
26016 |
0 |
0 |
T25 |
27518 |
26160 |
0 |
0 |
T26 |
15438 |
14970 |
0 |
0 |
T27 |
35928 |
34936 |
0 |
0 |
T28 |
9318 |
8834 |
0 |
0 |
T29 |
22368 |
21008 |
0 |
0 |
T30 |
13482 |
12666 |
0 |
0 |
SrcAckBusyChk_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
738287010 |
172469 |
0 |
0 |
T1 |
295170 |
200 |
0 |
0 |
T2 |
3899220 |
1360 |
0 |
0 |
T3 |
2932610 |
500 |
0 |
0 |
T4 |
74720 |
116 |
0 |
0 |
T11 |
0 |
2620 |
0 |
0 |
T12 |
0 |
2565 |
0 |
0 |
T13 |
0 |
200 |
0 |
0 |
T14 |
0 |
400 |
0 |
0 |
T15 |
0 |
380 |
0 |
0 |
T18 |
15360 |
0 |
0 |
0 |
T19 |
20580 |
0 |
0 |
0 |
T20 |
13750 |
0 |
0 |
0 |
T21 |
12430 |
0 |
0 |
0 |
T22 |
21700 |
0 |
0 |
0 |
T23 |
6730 |
0 |
0 |
0 |
T33 |
0 |
140 |
0 |
0 |
SrcBusyKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
738287010 |
716647400 |
0 |
0 |
T5 |
10980 |
10530 |
0 |
0 |
T6 |
11530 |
10950 |
0 |
0 |
T7 |
10370 |
9940 |
0 |
0 |
T24 |
11530 |
11120 |
0 |
0 |
T25 |
10500 |
9930 |
0 |
0 |
T26 |
23710 |
22880 |
0 |
0 |
T27 |
13540 |
13140 |
0 |
0 |
T28 |
14370 |
13560 |
0 |
0 |
T29 |
24230 |
22550 |
0 |
0 |
T30 |
21380 |
19850 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_en_cdc
| Line No. | Total | Covered | Percent |
TOTAL | | 22 | 22 | 100.00 |
CONT_ASSIGN | 65 | 1 | 1 | 100.00 |
ALWAYS | 71 | 6 | 6 | 100.00 |
CONT_ASSIGN | 85 | 1 | 1 | 100.00 |
CONT_ASSIGN | 109 | 1 | 1 | 100.00 |
ALWAYS | 115 | 9 | 9 | 100.00 |
CONT_ASSIGN | 150 | 1 | 1 | 100.00 |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 156 | 1 | 1 | 100.00 |
CONT_ASSIGN | 200 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
65 |
1 |
1 |
71 |
1 |
1 |
72 |
1 |
1 |
73 |
1 |
1 |
74 |
1 |
1 |
75 |
1 |
1 |
76 |
1 |
1 |
|
|
|
MISSING_ELSE |
85 |
1 |
1 |
109 |
1 |
1 |
115 |
1 |
1 |
116 |
1 |
1 |
117 |
1 |
1 |
118 |
1 |
1 |
123 |
1 |
1 |
124 |
1 |
1 |
125 |
1 |
1 |
134 |
1 |
1 |
135 |
1 |
1 |
|
|
|
MISSING_ELSE |
150 |
1 |
1 |
155 |
1 |
1 |
156 |
1 |
1 |
200 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_en_cdc
| Total | Covered | Percent |
Conditions | 14 | 12 | 85.71 |
Logical | 14 | 12 | 85.71 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 65
EXPRESSION (src_we_i | src_re_i)
----1--- ----2---
-1- | -2- | Status | Tests |
0 | 0 | Covered | T5,T6,T7 |
0 | 1 | Unreachable | |
1 | 0 | Covered | T1,T2,T4 |
LINE 109
EXPRESSION (src_busy_q & ((!src_ack)))
-----1---- ------2-----
-1- | -2- | Status | Tests |
0 | 1 | Covered | T5,T6,T7 |
1 | 0 | Covered | T1,T2,T4 |
1 | 1 | Covered | T1,T2,T4 |
LINE 125
EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
-----------1----------- ------------2------------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T5,T6,T7 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T4 |
LINE 125
SUB-EXPRESSION (src_busy_q && src_ack)
-----1---- ---2---
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T1,T2,T4 |
1 | 1 | Covered | T1,T2,T4 |
LINE 125
SUB-EXPRESSION (src_update && ((!busy)))
-----1---- ----2----
-1- | -2- | Status | Tests |
0 | 1 | Covered | T5,T6,T7 |
1 | 0 | Not Covered | |
1 | 1 | Covered | T1,T2,T3 |
Branch Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_en_cdc
| Line No. | Total | Covered | Percent |
Branches |
|
8 |
8 |
100.00 |
IF |
71 |
4 |
4 |
100.00 |
IF |
115 |
4 |
4 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 71 if ((!rst_src_ni))
-2-: 73 if (src_req)
-3-: 75 if (src_ack)
Branches:
-1- | -2- | -3- | Status | Tests |
1 |
- |
- |
Covered |
T5,T6,T7 |
0 |
1 |
- |
Covered |
T1,T2,T4 |
0 |
0 |
1 |
Covered |
T1,T2,T4 |
0 |
0 |
0 |
Covered |
T5,T6,T7 |
LineNo. Expression
-1-: 115 if ((!rst_src_ni))
-2-: 118 if (src_req)
-3-: 125 if (((src_busy_q && src_ack) || (src_update && (!busy))))
Branches:
-1- | -2- | -3- | Status | Tests |
1 |
- |
- |
Covered |
T5,T6,T7 |
0 |
1 |
- |
Covered |
T1,T2,T4 |
0 |
0 |
1 |
Covered |
T1,T2,T4 |
0 |
0 |
0 |
Covered |
T5,T6,T7 |
Assert Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_en_cdc
Assertion Details
BusySrcReqChk_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
73828701 |
48367 |
0 |
0 |
T1 |
29517 |
49 |
0 |
0 |
T2 |
389922 |
479 |
0 |
0 |
T3 |
293261 |
253 |
0 |
0 |
T4 |
7472 |
20 |
0 |
0 |
T11 |
0 |
676 |
0 |
0 |
T12 |
0 |
664 |
0 |
0 |
T13 |
0 |
54 |
0 |
0 |
T14 |
0 |
238 |
0 |
0 |
T15 |
0 |
132 |
0 |
0 |
T18 |
1536 |
0 |
0 |
0 |
T19 |
2058 |
0 |
0 |
0 |
T20 |
1375 |
0 |
0 |
0 |
T21 |
1243 |
0 |
0 |
0 |
T22 |
2170 |
0 |
0 |
0 |
T23 |
673 |
0 |
0 |
0 |
T33 |
0 |
56 |
0 |
0 |
DstReqKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
223910640 |
220146104 |
0 |
0 |
T5 |
4221 |
4045 |
0 |
0 |
T6 |
4261 |
4044 |
0 |
0 |
T7 |
5786 |
5541 |
0 |
0 |
T24 |
4100 |
3952 |
0 |
0 |
T25 |
4204 |
3973 |
0 |
0 |
T26 |
2276 |
2196 |
0 |
0 |
T27 |
5420 |
5257 |
0 |
0 |
T28 |
1421 |
1342 |
0 |
0 |
T29 |
3323 |
3092 |
0 |
0 |
T30 |
2072 |
1924 |
0 |
0 |
SrcAckBusyChk_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
73828701 |
14511 |
0 |
0 |
T1 |
29517 |
20 |
0 |
0 |
T2 |
389922 |
136 |
0 |
0 |
T3 |
293261 |
50 |
0 |
0 |
T4 |
7472 |
8 |
0 |
0 |
T11 |
0 |
259 |
0 |
0 |
T12 |
0 |
254 |
0 |
0 |
T13 |
0 |
20 |
0 |
0 |
T14 |
0 |
40 |
0 |
0 |
T15 |
0 |
38 |
0 |
0 |
T18 |
1536 |
0 |
0 |
0 |
T19 |
2058 |
0 |
0 |
0 |
T20 |
1375 |
0 |
0 |
0 |
T21 |
1243 |
0 |
0 |
0 |
T22 |
2170 |
0 |
0 |
0 |
T23 |
673 |
0 |
0 |
0 |
T33 |
0 |
14 |
0 |
0 |
SrcBusyKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
73828701 |
71664740 |
0 |
0 |
T5 |
1098 |
1053 |
0 |
0 |
T6 |
1153 |
1095 |
0 |
0 |
T7 |
1037 |
994 |
0 |
0 |
T24 |
1153 |
1112 |
0 |
0 |
T25 |
1050 |
993 |
0 |
0 |
T26 |
2371 |
2288 |
0 |
0 |
T27 |
1354 |
1314 |
0 |
0 |
T28 |
1437 |
1356 |
0 |
0 |
T29 |
2423 |
2255 |
0 |
0 |
T30 |
2138 |
1985 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_en_cdc
| Line No. | Total | Covered | Percent |
TOTAL | | 22 | 22 | 100.00 |
CONT_ASSIGN | 65 | 1 | 1 | 100.00 |
ALWAYS | 71 | 6 | 6 | 100.00 |
CONT_ASSIGN | 85 | 1 | 1 | 100.00 |
CONT_ASSIGN | 109 | 1 | 1 | 100.00 |
ALWAYS | 115 | 9 | 9 | 100.00 |
CONT_ASSIGN | 150 | 1 | 1 | 100.00 |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 156 | 1 | 1 | 100.00 |
CONT_ASSIGN | 200 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
65 |
1 |
1 |
71 |
1 |
1 |
72 |
1 |
1 |
73 |
1 |
1 |
74 |
1 |
1 |
75 |
1 |
1 |
76 |
1 |
1 |
|
|
|
MISSING_ELSE |
85 |
1 |
1 |
109 |
1 |
1 |
115 |
1 |
1 |
116 |
1 |
1 |
117 |
1 |
1 |
118 |
1 |
1 |
123 |
1 |
1 |
124 |
1 |
1 |
125 |
1 |
1 |
134 |
1 |
1 |
135 |
1 |
1 |
|
|
|
MISSING_ELSE |
150 |
1 |
1 |
155 |
1 |
1 |
156 |
1 |
1 |
200 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_en_cdc
| Total | Covered | Percent |
Conditions | 14 | 12 | 85.71 |
Logical | 14 | 12 | 85.71 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 65
EXPRESSION (src_we_i | src_re_i)
----1--- ----2---
-1- | -2- | Status | Tests |
0 | 0 | Covered | T5,T6,T7 |
0 | 1 | Unreachable | |
1 | 0 | Covered | T1,T2,T4 |
LINE 109
EXPRESSION (src_busy_q & ((!src_ack)))
-----1---- ------2-----
-1- | -2- | Status | Tests |
0 | 1 | Covered | T5,T6,T7 |
1 | 0 | Covered | T1,T2,T4 |
1 | 1 | Covered | T1,T2,T4 |
LINE 125
EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
-----------1----------- ------------2------------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T5,T6,T7 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T4 |
LINE 125
SUB-EXPRESSION (src_busy_q && src_ack)
-----1---- ---2---
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T1,T2,T4 |
1 | 1 | Covered | T1,T2,T4 |
LINE 125
SUB-EXPRESSION (src_update && ((!busy)))
-----1---- ----2----
-1- | -2- | Status | Tests |
0 | 1 | Covered | T5,T6,T7 |
1 | 0 | Not Covered | |
1 | 1 | Covered | T1,T2,T3 |
Branch Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_en_cdc
| Line No. | Total | Covered | Percent |
Branches |
|
8 |
8 |
100.00 |
IF |
71 |
4 |
4 |
100.00 |
IF |
115 |
4 |
4 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 71 if ((!rst_src_ni))
-2-: 73 if (src_req)
-3-: 75 if (src_ack)
Branches:
-1- | -2- | -3- | Status | Tests |
1 |
- |
- |
Covered |
T5,T6,T7 |
0 |
1 |
- |
Covered |
T1,T2,T4 |
0 |
0 |
1 |
Covered |
T1,T2,T4 |
0 |
0 |
0 |
Covered |
T5,T6,T7 |
LineNo. Expression
-1-: 115 if ((!rst_src_ni))
-2-: 118 if (src_req)
-3-: 125 if (((src_busy_q && src_ack) || (src_update && (!busy))))
Branches:
-1- | -2- | -3- | Status | Tests |
1 |
- |
- |
Covered |
T5,T6,T7 |
0 |
1 |
- |
Covered |
T1,T2,T4 |
0 |
0 |
1 |
Covered |
T1,T2,T4 |
0 |
0 |
0 |
Covered |
T5,T6,T7 |
Assert Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_en_cdc
Assertion Details
BusySrcReqChk_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
73828701 |
68743 |
0 |
0 |
T1 |
29517 |
69 |
0 |
0 |
T2 |
389922 |
687 |
0 |
0 |
T3 |
293261 |
408 |
0 |
0 |
T4 |
7472 |
28 |
0 |
0 |
T11 |
0 |
940 |
0 |
0 |
T12 |
0 |
909 |
0 |
0 |
T13 |
0 |
74 |
0 |
0 |
T14 |
0 |
348 |
0 |
0 |
T15 |
0 |
190 |
0 |
0 |
T18 |
1536 |
0 |
0 |
0 |
T19 |
2058 |
0 |
0 |
0 |
T20 |
1375 |
0 |
0 |
0 |
T21 |
1243 |
0 |
0 |
0 |
T22 |
2170 |
0 |
0 |
0 |
T23 |
673 |
0 |
0 |
0 |
T33 |
0 |
84 |
0 |
0 |
DstReqKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
111190200 |
110253825 |
0 |
0 |
T5 |
2185 |
2144 |
0 |
0 |
T6 |
2091 |
2022 |
0 |
0 |
T7 |
2833 |
2771 |
0 |
0 |
T24 |
2010 |
1976 |
0 |
0 |
T25 |
2049 |
1987 |
0 |
0 |
T26 |
1290 |
1269 |
0 |
0 |
T27 |
2793 |
2738 |
0 |
0 |
T28 |
698 |
671 |
0 |
0 |
T29 |
1827 |
1765 |
0 |
0 |
T30 |
983 |
962 |
0 |
0 |
SrcAckBusyChk_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
73828701 |
14511 |
0 |
0 |
T1 |
29517 |
20 |
0 |
0 |
T2 |
389922 |
136 |
0 |
0 |
T3 |
293261 |
50 |
0 |
0 |
T4 |
7472 |
8 |
0 |
0 |
T11 |
0 |
259 |
0 |
0 |
T12 |
0 |
254 |
0 |
0 |
T13 |
0 |
20 |
0 |
0 |
T14 |
0 |
40 |
0 |
0 |
T15 |
0 |
38 |
0 |
0 |
T18 |
1536 |
0 |
0 |
0 |
T19 |
2058 |
0 |
0 |
0 |
T20 |
1375 |
0 |
0 |
0 |
T21 |
1243 |
0 |
0 |
0 |
T22 |
2170 |
0 |
0 |
0 |
T23 |
673 |
0 |
0 |
0 |
T33 |
0 |
14 |
0 |
0 |
SrcBusyKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
73828701 |
71664740 |
0 |
0 |
T5 |
1098 |
1053 |
0 |
0 |
T6 |
1153 |
1095 |
0 |
0 |
T7 |
1037 |
994 |
0 |
0 |
T24 |
1153 |
1112 |
0 |
0 |
T25 |
1050 |
993 |
0 |
0 |
T26 |
2371 |
2288 |
0 |
0 |
T27 |
1354 |
1314 |
0 |
0 |
T28 |
1437 |
1356 |
0 |
0 |
T29 |
2423 |
2255 |
0 |
0 |
T30 |
2138 |
1985 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_en_cdc
| Line No. | Total | Covered | Percent |
TOTAL | | 22 | 22 | 100.00 |
CONT_ASSIGN | 65 | 1 | 1 | 100.00 |
ALWAYS | 71 | 6 | 6 | 100.00 |
CONT_ASSIGN | 85 | 1 | 1 | 100.00 |
CONT_ASSIGN | 109 | 1 | 1 | 100.00 |
ALWAYS | 115 | 9 | 9 | 100.00 |
CONT_ASSIGN | 150 | 1 | 1 | 100.00 |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 156 | 1 | 1 | 100.00 |
CONT_ASSIGN | 200 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
65 |
1 |
1 |
71 |
1 |
1 |
72 |
1 |
1 |
73 |
1 |
1 |
74 |
1 |
1 |
75 |
1 |
1 |
76 |
1 |
1 |
|
|
|
MISSING_ELSE |
85 |
1 |
1 |
109 |
1 |
1 |
115 |
1 |
1 |
116 |
1 |
1 |
117 |
1 |
1 |
118 |
1 |
1 |
123 |
1 |
1 |
124 |
1 |
1 |
125 |
1 |
1 |
134 |
1 |
1 |
135 |
1 |
1 |
|
|
|
MISSING_ELSE |
150 |
1 |
1 |
155 |
1 |
1 |
156 |
1 |
1 |
200 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_en_cdc
| Total | Covered | Percent |
Conditions | 14 | 12 | 85.71 |
Logical | 14 | 12 | 85.71 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 65
EXPRESSION (src_we_i | src_re_i)
----1--- ----2---
-1- | -2- | Status | Tests |
0 | 0 | Covered | T5,T6,T7 |
0 | 1 | Unreachable | |
1 | 0 | Covered | T1,T2,T4 |
LINE 109
EXPRESSION (src_busy_q & ((!src_ack)))
-----1---- ------2-----
-1- | -2- | Status | Tests |
0 | 1 | Covered | T5,T6,T7 |
1 | 0 | Covered | T1,T2,T4 |
1 | 1 | Covered | T1,T2,T4 |
LINE 125
EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
-----------1----------- ------------2------------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T5,T6,T7 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T4 |
LINE 125
SUB-EXPRESSION (src_busy_q && src_ack)
-----1---- ---2---
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T1,T2,T4 |
1 | 1 | Covered | T1,T2,T4 |
LINE 125
SUB-EXPRESSION (src_update && ((!busy)))
-----1---- ----2----
-1- | -2- | Status | Tests |
0 | 1 | Covered | T5,T6,T7 |
1 | 0 | Not Covered | |
1 | 1 | Covered | T1,T2,T3 |
Branch Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_en_cdc
| Line No. | Total | Covered | Percent |
Branches |
|
8 |
8 |
100.00 |
IF |
71 |
4 |
4 |
100.00 |
IF |
115 |
4 |
4 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 71 if ((!rst_src_ni))
-2-: 73 if (src_req)
-3-: 75 if (src_ack)
Branches:
-1- | -2- | -3- | Status | Tests |
1 |
- |
- |
Covered |
T5,T6,T7 |
0 |
1 |
- |
Covered |
T1,T2,T4 |
0 |
0 |
1 |
Covered |
T1,T2,T4 |
0 |
0 |
0 |
Covered |
T5,T6,T7 |
LineNo. Expression
-1-: 115 if ((!rst_src_ni))
-2-: 118 if (src_req)
-3-: 125 if (((src_busy_q && src_ack) || (src_update && (!busy))))
Branches:
-1- | -2- | -3- | Status | Tests |
1 |
- |
- |
Covered |
T5,T6,T7 |
0 |
1 |
- |
Covered |
T1,T2,T4 |
0 |
0 |
1 |
Covered |
T1,T2,T4 |
0 |
0 |
0 |
Covered |
T5,T6,T7 |
Assert Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_en_cdc
Assertion Details
BusySrcReqChk_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
73828701 |
107660 |
0 |
0 |
T1 |
29517 |
100 |
0 |
0 |
T2 |
389922 |
1095 |
0 |
0 |
T3 |
293261 |
701 |
0 |
0 |
T4 |
7472 |
38 |
0 |
0 |
T11 |
0 |
1343 |
0 |
0 |
T12 |
0 |
1312 |
0 |
0 |
T13 |
0 |
107 |
0 |
0 |
T14 |
0 |
559 |
0 |
0 |
T15 |
0 |
305 |
0 |
0 |
T18 |
1536 |
0 |
0 |
0 |
T19 |
2058 |
0 |
0 |
0 |
T20 |
1375 |
0 |
0 |
0 |
T21 |
1243 |
0 |
0 |
0 |
T22 |
2170 |
0 |
0 |
0 |
T23 |
673 |
0 |
0 |
0 |
T33 |
0 |
131 |
0 |
0 |
DstReqKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
55594684 |
55126596 |
0 |
0 |
T5 |
1092 |
1071 |
0 |
0 |
T6 |
1045 |
1011 |
0 |
0 |
T7 |
1416 |
1385 |
0 |
0 |
T24 |
1005 |
988 |
0 |
0 |
T25 |
1024 |
993 |
0 |
0 |
T26 |
644 |
633 |
0 |
0 |
T27 |
1395 |
1367 |
0 |
0 |
T28 |
349 |
335 |
0 |
0 |
T29 |
911 |
880 |
0 |
0 |
T30 |
491 |
481 |
0 |
0 |
SrcAckBusyChk_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
73828701 |
14511 |
0 |
0 |
T1 |
29517 |
20 |
0 |
0 |
T2 |
389922 |
136 |
0 |
0 |
T3 |
293261 |
50 |
0 |
0 |
T4 |
7472 |
8 |
0 |
0 |
T11 |
0 |
259 |
0 |
0 |
T12 |
0 |
254 |
0 |
0 |
T13 |
0 |
20 |
0 |
0 |
T14 |
0 |
40 |
0 |
0 |
T15 |
0 |
38 |
0 |
0 |
T18 |
1536 |
0 |
0 |
0 |
T19 |
2058 |
0 |
0 |
0 |
T20 |
1375 |
0 |
0 |
0 |
T21 |
1243 |
0 |
0 |
0 |
T22 |
2170 |
0 |
0 |
0 |
T23 |
673 |
0 |
0 |
0 |
T33 |
0 |
14 |
0 |
0 |
SrcBusyKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
73828701 |
71664740 |
0 |
0 |
T5 |
1098 |
1053 |
0 |
0 |
T6 |
1153 |
1095 |
0 |
0 |
T7 |
1037 |
994 |
0 |
0 |
T24 |
1153 |
1112 |
0 |
0 |
T25 |
1050 |
993 |
0 |
0 |
T26 |
2371 |
2288 |
0 |
0 |
T27 |
1354 |
1314 |
0 |
0 |
T28 |
1437 |
1356 |
0 |
0 |
T29 |
2423 |
2255 |
0 |
0 |
T30 |
2138 |
1985 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_en_cdc
| Line No. | Total | Covered | Percent |
TOTAL | | 22 | 22 | 100.00 |
CONT_ASSIGN | 65 | 1 | 1 | 100.00 |
ALWAYS | 71 | 6 | 6 | 100.00 |
CONT_ASSIGN | 85 | 1 | 1 | 100.00 |
CONT_ASSIGN | 109 | 1 | 1 | 100.00 |
ALWAYS | 115 | 9 | 9 | 100.00 |
CONT_ASSIGN | 150 | 1 | 1 | 100.00 |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 156 | 1 | 1 | 100.00 |
CONT_ASSIGN | 200 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
65 |
1 |
1 |
71 |
1 |
1 |
72 |
1 |
1 |
73 |
1 |
1 |
74 |
1 |
1 |
75 |
1 |
1 |
76 |
1 |
1 |
|
|
|
MISSING_ELSE |
85 |
1 |
1 |
109 |
1 |
1 |
115 |
1 |
1 |
116 |
1 |
1 |
117 |
1 |
1 |
118 |
1 |
1 |
123 |
1 |
1 |
124 |
1 |
1 |
125 |
1 |
1 |
134 |
1 |
1 |
135 |
1 |
1 |
|
|
|
MISSING_ELSE |
150 |
1 |
1 |
155 |
1 |
1 |
156 |
1 |
1 |
200 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_en_cdc
| Total | Covered | Percent |
Conditions | 14 | 12 | 85.71 |
Logical | 14 | 12 | 85.71 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 65
EXPRESSION (src_we_i | src_re_i)
----1--- ----2---
-1- | -2- | Status | Tests |
0 | 0 | Covered | T5,T6,T7 |
0 | 1 | Unreachable | |
1 | 0 | Covered | T1,T2,T4 |
LINE 109
EXPRESSION (src_busy_q & ((!src_ack)))
-----1---- ------2-----
-1- | -2- | Status | Tests |
0 | 1 | Covered | T5,T6,T7 |
1 | 0 | Covered | T1,T2,T4 |
1 | 1 | Covered | T1,T2,T4 |
LINE 125
EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
-----------1----------- ------------2------------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T5,T6,T7 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T4 |
LINE 125
SUB-EXPRESSION (src_busy_q && src_ack)
-----1---- ---2---
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T1,T2,T4 |
1 | 1 | Covered | T1,T2,T4 |
LINE 125
SUB-EXPRESSION (src_update && ((!busy)))
-----1---- ----2----
-1- | -2- | Status | Tests |
0 | 1 | Covered | T5,T6,T7 |
1 | 0 | Not Covered | |
1 | 1 | Covered | T1,T2,T3 |
Branch Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_en_cdc
| Line No. | Total | Covered | Percent |
Branches |
|
8 |
8 |
100.00 |
IF |
71 |
4 |
4 |
100.00 |
IF |
115 |
4 |
4 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 71 if ((!rst_src_ni))
-2-: 73 if (src_req)
-3-: 75 if (src_ack)
Branches:
-1- | -2- | -3- | Status | Tests |
1 |
- |
- |
Covered |
T5,T6,T7 |
0 |
1 |
- |
Covered |
T1,T2,T4 |
0 |
0 |
1 |
Covered |
T1,T2,T4 |
0 |
0 |
0 |
Covered |
T5,T6,T7 |
LineNo. Expression
-1-: 115 if ((!rst_src_ni))
-2-: 118 if (src_req)
-3-: 125 if (((src_busy_q && src_ack) || (src_update && (!busy))))
Branches:
-1- | -2- | -3- | Status | Tests |
1 |
- |
- |
Covered |
T5,T6,T7 |
0 |
1 |
- |
Covered |
T1,T2,T4 |
0 |
0 |
1 |
Covered |
T1,T2,T4 |
0 |
0 |
0 |
Covered |
T5,T6,T7 |
Assert Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_en_cdc
Assertion Details
BusySrcReqChk_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
73828701 |
47433 |
0 |
0 |
T1 |
29517 |
49 |
0 |
0 |
T2 |
389922 |
477 |
0 |
0 |
T3 |
293261 |
244 |
0 |
0 |
T4 |
7472 |
19 |
0 |
0 |
T11 |
0 |
651 |
0 |
0 |
T12 |
0 |
637 |
0 |
0 |
T13 |
0 |
53 |
0 |
0 |
T14 |
0 |
195 |
0 |
0 |
T15 |
0 |
130 |
0 |
0 |
T18 |
1536 |
0 |
0 |
0 |
T19 |
2058 |
0 |
0 |
0 |
T20 |
1375 |
0 |
0 |
0 |
T21 |
1243 |
0 |
0 |
0 |
T22 |
2170 |
0 |
0 |
0 |
T23 |
673 |
0 |
0 |
0 |
T33 |
0 |
56 |
0 |
0 |
DstReqKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
239150230 |
235222780 |
0 |
0 |
T5 |
4396 |
4213 |
0 |
0 |
T6 |
4439 |
4213 |
0 |
0 |
T7 |
5698 |
5443 |
0 |
0 |
T24 |
4271 |
4116 |
0 |
0 |
T25 |
4380 |
4140 |
0 |
0 |
T26 |
2371 |
2288 |
0 |
0 |
T27 |
5646 |
5477 |
0 |
0 |
T28 |
1481 |
1398 |
0 |
0 |
T29 |
3462 |
3221 |
0 |
0 |
T30 |
2159 |
2004 |
0 |
0 |
SrcAckBusyChk_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
73828701 |
14511 |
0 |
0 |
T1 |
29517 |
20 |
0 |
0 |
T2 |
389922 |
136 |
0 |
0 |
T3 |
293261 |
50 |
0 |
0 |
T4 |
7472 |
8 |
0 |
0 |
T11 |
0 |
259 |
0 |
0 |
T12 |
0 |
254 |
0 |
0 |
T13 |
0 |
20 |
0 |
0 |
T14 |
0 |
40 |
0 |
0 |
T15 |
0 |
38 |
0 |
0 |
T18 |
1536 |
0 |
0 |
0 |
T19 |
2058 |
0 |
0 |
0 |
T20 |
1375 |
0 |
0 |
0 |
T21 |
1243 |
0 |
0 |
0 |
T22 |
2170 |
0 |
0 |
0 |
T23 |
673 |
0 |
0 |
0 |
T33 |
0 |
14 |
0 |
0 |
SrcBusyKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
73828701 |
71664740 |
0 |
0 |
T5 |
1098 |
1053 |
0 |
0 |
T6 |
1153 |
1095 |
0 |
0 |
T7 |
1037 |
994 |
0 |
0 |
T24 |
1153 |
1112 |
0 |
0 |
T25 |
1050 |
993 |
0 |
0 |
T26 |
2371 |
2288 |
0 |
0 |
T27 |
1354 |
1314 |
0 |
0 |
T28 |
1437 |
1356 |
0 |
0 |
T29 |
2423 |
2255 |
0 |
0 |
T30 |
2138 |
1985 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_en_cdc
| Line No. | Total | Covered | Percent |
TOTAL | | 22 | 22 | 100.00 |
CONT_ASSIGN | 65 | 1 | 1 | 100.00 |
ALWAYS | 71 | 6 | 6 | 100.00 |
CONT_ASSIGN | 85 | 1 | 1 | 100.00 |
CONT_ASSIGN | 109 | 1 | 1 | 100.00 |
ALWAYS | 115 | 9 | 9 | 100.00 |
CONT_ASSIGN | 150 | 1 | 1 | 100.00 |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 156 | 1 | 1 | 100.00 |
CONT_ASSIGN | 200 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
65 |
1 |
1 |
71 |
1 |
1 |
72 |
1 |
1 |
73 |
1 |
1 |
74 |
1 |
1 |
75 |
1 |
1 |
76 |
1 |
1 |
|
|
|
MISSING_ELSE |
85 |
1 |
1 |
109 |
1 |
1 |
115 |
1 |
1 |
116 |
1 |
1 |
117 |
1 |
1 |
118 |
1 |
1 |
123 |
1 |
1 |
124 |
1 |
1 |
125 |
1 |
1 |
134 |
1 |
1 |
135 |
1 |
1 |
|
|
|
MISSING_ELSE |
150 |
1 |
1 |
155 |
1 |
1 |
156 |
1 |
1 |
200 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_en_cdc
| Total | Covered | Percent |
Conditions | 14 | 12 | 85.71 |
Logical | 14 | 12 | 85.71 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 65
EXPRESSION (src_we_i | src_re_i)
----1--- ----2---
-1- | -2- | Status | Tests |
0 | 0 | Covered | T5,T6,T7 |
0 | 1 | Unreachable | |
1 | 0 | Covered | T1,T2,T4 |
LINE 109
EXPRESSION (src_busy_q & ((!src_ack)))
-----1---- ------2-----
-1- | -2- | Status | Tests |
0 | 1 | Covered | T5,T6,T7 |
1 | 0 | Covered | T1,T2,T4 |
1 | 1 | Covered | T1,T2,T4 |
LINE 125
EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
-----------1----------- ------------2------------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T5,T6,T7 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T4 |
LINE 125
SUB-EXPRESSION (src_busy_q && src_ack)
-----1---- ---2---
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T1,T2,T4 |
1 | 1 | Covered | T1,T2,T4 |
LINE 125
SUB-EXPRESSION (src_update && ((!busy)))
-----1---- ----2----
-1- | -2- | Status | Tests |
0 | 1 | Covered | T5,T6,T7 |
1 | 0 | Not Covered | |
1 | 1 | Covered | T1,T2,T3 |
Branch Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_en_cdc
| Line No. | Total | Covered | Percent |
Branches |
|
8 |
8 |
100.00 |
IF |
71 |
4 |
4 |
100.00 |
IF |
115 |
4 |
4 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 71 if ((!rst_src_ni))
-2-: 73 if (src_req)
-3-: 75 if (src_ack)
Branches:
-1- | -2- | -3- | Status | Tests |
1 |
- |
- |
Covered |
T5,T6,T7 |
0 |
1 |
- |
Covered |
T1,T2,T4 |
0 |
0 |
1 |
Covered |
T1,T2,T4 |
0 |
0 |
0 |
Covered |
T5,T6,T7 |
LineNo. Expression
-1-: 115 if ((!rst_src_ni))
-2-: 118 if (src_req)
-3-: 125 if (((src_busy_q && src_ack) || (src_update && (!busy))))
Branches:
-1- | -2- | -3- | Status | Tests |
1 |
- |
- |
Covered |
T5,T6,T7 |
0 |
1 |
- |
Covered |
T1,T2,T4 |
0 |
0 |
1 |
Covered |
T1,T2,T4 |
0 |
0 |
0 |
Covered |
T5,T6,T7 |
Assert Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_en_cdc
Assertion Details
BusySrcReqChk_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
73828701 |
66536 |
0 |
0 |
T1 |
29517 |
69 |
0 |
0 |
T2 |
389922 |
823 |
0 |
0 |
T3 |
293261 |
398 |
0 |
0 |
T4 |
7472 |
18 |
0 |
0 |
T11 |
0 |
932 |
0 |
0 |
T12 |
0 |
913 |
0 |
0 |
T13 |
0 |
76 |
0 |
0 |
T14 |
0 |
314 |
0 |
0 |
T15 |
0 |
188 |
0 |
0 |
T18 |
1536 |
0 |
0 |
0 |
T19 |
2058 |
0 |
0 |
0 |
T20 |
1375 |
0 |
0 |
0 |
T21 |
1243 |
0 |
0 |
0 |
T22 |
2170 |
0 |
0 |
0 |
T23 |
673 |
0 |
0 |
0 |
T33 |
0 |
80 |
0 |
0 |
DstReqKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
114657872 |
112776678 |
0 |
0 |
T5 |
2110 |
2023 |
0 |
0 |
T6 |
2131 |
2023 |
0 |
0 |
T7 |
2787 |
2665 |
0 |
0 |
T24 |
2050 |
1976 |
0 |
0 |
T25 |
2102 |
1987 |
0 |
0 |
T26 |
1138 |
1099 |
0 |
0 |
T27 |
2710 |
2629 |
0 |
0 |
T28 |
710 |
671 |
0 |
0 |
T29 |
1661 |
1546 |
0 |
0 |
T30 |
1036 |
962 |
0 |
0 |
SrcAckBusyChk_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
73828701 |
13999 |
0 |
0 |
T1 |
29517 |
20 |
0 |
0 |
T2 |
389922 |
136 |
0 |
0 |
T3 |
293261 |
50 |
0 |
0 |
T4 |
7472 |
4 |
0 |
0 |
T11 |
0 |
259 |
0 |
0 |
T12 |
0 |
254 |
0 |
0 |
T13 |
0 |
20 |
0 |
0 |
T14 |
0 |
40 |
0 |
0 |
T15 |
0 |
38 |
0 |
0 |
T18 |
1536 |
0 |
0 |
0 |
T19 |
2058 |
0 |
0 |
0 |
T20 |
1375 |
0 |
0 |
0 |
T21 |
1243 |
0 |
0 |
0 |
T22 |
2170 |
0 |
0 |
0 |
T23 |
673 |
0 |
0 |
0 |
T33 |
0 |
14 |
0 |
0 |
SrcBusyKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
73828701 |
71664740 |
0 |
0 |
T5 |
1098 |
1053 |
0 |
0 |
T6 |
1153 |
1095 |
0 |
0 |
T7 |
1037 |
994 |
0 |
0 |
T24 |
1153 |
1112 |
0 |
0 |
T25 |
1050 |
993 |
0 |
0 |
T26 |
2371 |
2288 |
0 |
0 |
T27 |
1354 |
1314 |
0 |
0 |
T28 |
1437 |
1356 |
0 |
0 |
T29 |
2423 |
2255 |
0 |
0 |
T30 |
2138 |
1985 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_cdc
| Line No. | Total | Covered | Percent |
TOTAL | | 22 | 22 | 100.00 |
CONT_ASSIGN | 65 | 1 | 1 | 100.00 |
ALWAYS | 71 | 6 | 6 | 100.00 |
CONT_ASSIGN | 85 | 1 | 1 | 100.00 |
CONT_ASSIGN | 109 | 1 | 1 | 100.00 |
ALWAYS | 115 | 9 | 9 | 100.00 |
CONT_ASSIGN | 150 | 1 | 1 | 100.00 |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 156 | 1 | 1 | 100.00 |
CONT_ASSIGN | 200 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
65 |
1 |
1 |
71 |
1 |
1 |
72 |
1 |
1 |
73 |
1 |
1 |
74 |
1 |
1 |
75 |
1 |
1 |
76 |
1 |
1 |
|
|
|
MISSING_ELSE |
85 |
1 |
1 |
109 |
1 |
1 |
115 |
1 |
1 |
116 |
1 |
1 |
117 |
1 |
1 |
118 |
1 |
1 |
123 |
1 |
1 |
124 |
1 |
1 |
125 |
1 |
1 |
134 |
1 |
1 |
135 |
1 |
1 |
|
|
|
MISSING_ELSE |
150 |
1 |
1 |
155 |
1 |
1 |
156 |
1 |
1 |
200 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_cdc
| Total | Covered | Percent |
Conditions | 12 | 11 | 91.67 |
Logical | 12 | 11 | 91.67 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 65
EXPRESSION (src_we_i | src_re_i)
----1--- ----2---
-1- | -2- | Status | Tests |
0 | 0 | Covered | T5,T6,T7 |
0 | 1 | Covered | T4,T11,T12 |
1 | 0 | Covered | T1,T2,T4 |
LINE 109
EXPRESSION (src_busy_q & ((!src_ack)))
-----1---- ------2-----
-1- | -2- | Status | Tests |
0 | 1 | Covered | T5,T6,T7 |
1 | 0 | Covered | T1,T2,T4 |
1 | 1 | Covered | T1,T2,T4 |
LINE 125
EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
-----------1----------- ------------2------------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T5,T6,T7 |
0 | 1 | Unreachable | |
1 | 0 | Covered | T1,T2,T4 |
LINE 125
SUB-EXPRESSION (src_busy_q && src_ack)
-----1---- ---2---
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T1,T2,T4 |
1 | 1 | Covered | T1,T2,T4 |
LINE 125
SUB-EXPRESSION (src_update && ((!busy)))
-----1---- ----2----
-1- | -2- | Status | Tests |
0 | 1 | Covered | T5,T6,T7 |
1 | 0 | Unreachable | |
1 | 1 | Unreachable | |
Branch Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_cdc
| Line No. | Total | Covered | Percent |
Branches |
|
8 |
8 |
100.00 |
IF |
71 |
4 |
4 |
100.00 |
IF |
115 |
4 |
4 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 71 if ((!rst_src_ni))
-2-: 73 if (src_req)
-3-: 75 if (src_ack)
Branches:
-1- | -2- | -3- | Status | Tests |
1 |
- |
- |
Covered |
T5,T6,T7 |
0 |
1 |
- |
Covered |
T1,T2,T4 |
0 |
0 |
1 |
Covered |
T1,T2,T4 |
0 |
0 |
0 |
Covered |
T5,T6,T7 |
LineNo. Expression
-1-: 115 if ((!rst_src_ni))
-2-: 118 if (src_req)
-3-: 125 if (((src_busy_q && src_ack) || (src_update && (!busy))))
Branches:
-1- | -2- | -3- | Status | Tests |
1 |
- |
- |
Covered |
T5,T6,T7 |
0 |
1 |
- |
Covered |
T1,T2,T4 |
0 |
0 |
1 |
Covered |
T1,T2,T4 |
0 |
0 |
0 |
Covered |
T5,T6,T7 |
Assert Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_cdc
Assertion Details
BusySrcReqChk_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
73828701 |
70041 |
0 |
0 |
T1 |
29517 |
51 |
0 |
0 |
T2 |
389922 |
480 |
0 |
0 |
T3 |
293261 |
251 |
0 |
0 |
T4 |
7472 |
42 |
0 |
0 |
T11 |
0 |
697 |
0 |
0 |
T12 |
0 |
673 |
0 |
0 |
T13 |
0 |
54 |
0 |
0 |
T14 |
0 |
236 |
0 |
0 |
T15 |
0 |
133 |
0 |
0 |
T18 |
1536 |
0 |
0 |
0 |
T19 |
2058 |
0 |
0 |
0 |
T20 |
1375 |
0 |
0 |
0 |
T21 |
1243 |
0 |
0 |
0 |
T22 |
2170 |
0 |
0 |
0 |
T23 |
673 |
0 |
0 |
0 |
T33 |
0 |
59 |
0 |
0 |
DstReqKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
223910640 |
220146104 |
0 |
0 |
T5 |
4221 |
4045 |
0 |
0 |
T6 |
4261 |
4044 |
0 |
0 |
T7 |
5786 |
5541 |
0 |
0 |
T24 |
4100 |
3952 |
0 |
0 |
T25 |
4204 |
3973 |
0 |
0 |
T26 |
2276 |
2196 |
0 |
0 |
T27 |
5420 |
5257 |
0 |
0 |
T28 |
1421 |
1342 |
0 |
0 |
T29 |
3323 |
3092 |
0 |
0 |
T30 |
2072 |
1924 |
0 |
0 |
SrcAckBusyChk_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
73828701 |
20220 |
0 |
0 |
T1 |
29517 |
20 |
0 |
0 |
T2 |
389922 |
136 |
0 |
0 |
T3 |
293261 |
50 |
0 |
0 |
T4 |
7472 |
16 |
0 |
0 |
T11 |
0 |
265 |
0 |
0 |
T12 |
0 |
259 |
0 |
0 |
T13 |
0 |
20 |
0 |
0 |
T14 |
0 |
40 |
0 |
0 |
T15 |
0 |
38 |
0 |
0 |
T18 |
1536 |
0 |
0 |
0 |
T19 |
2058 |
0 |
0 |
0 |
T20 |
1375 |
0 |
0 |
0 |
T21 |
1243 |
0 |
0 |
0 |
T22 |
2170 |
0 |
0 |
0 |
T23 |
673 |
0 |
0 |
0 |
T33 |
0 |
14 |
0 |
0 |
SrcBusyKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
73828701 |
71664740 |
0 |
0 |
T5 |
1098 |
1053 |
0 |
0 |
T6 |
1153 |
1095 |
0 |
0 |
T7 |
1037 |
994 |
0 |
0 |
T24 |
1153 |
1112 |
0 |
0 |
T25 |
1050 |
993 |
0 |
0 |
T26 |
2371 |
2288 |
0 |
0 |
T27 |
1354 |
1314 |
0 |
0 |
T28 |
1437 |
1356 |
0 |
0 |
T29 |
2423 |
2255 |
0 |
0 |
T30 |
2138 |
1985 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_cdc
| Line No. | Total | Covered | Percent |
TOTAL | | 22 | 22 | 100.00 |
CONT_ASSIGN | 65 | 1 | 1 | 100.00 |
ALWAYS | 71 | 6 | 6 | 100.00 |
CONT_ASSIGN | 85 | 1 | 1 | 100.00 |
CONT_ASSIGN | 109 | 1 | 1 | 100.00 |
ALWAYS | 115 | 9 | 9 | 100.00 |
CONT_ASSIGN | 150 | 1 | 1 | 100.00 |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 156 | 1 | 1 | 100.00 |
CONT_ASSIGN | 200 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
65 |
1 |
1 |
71 |
1 |
1 |
72 |
1 |
1 |
73 |
1 |
1 |
74 |
1 |
1 |
75 |
1 |
1 |
76 |
1 |
1 |
|
|
|
MISSING_ELSE |
85 |
1 |
1 |
109 |
1 |
1 |
115 |
1 |
1 |
116 |
1 |
1 |
117 |
1 |
1 |
118 |
1 |
1 |
123 |
1 |
1 |
124 |
1 |
1 |
125 |
1 |
1 |
134 |
1 |
1 |
135 |
1 |
1 |
|
|
|
MISSING_ELSE |
150 |
1 |
1 |
155 |
1 |
1 |
156 |
1 |
1 |
200 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_cdc
| Total | Covered | Percent |
Conditions | 12 | 11 | 91.67 |
Logical | 12 | 11 | 91.67 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 65
EXPRESSION (src_we_i | src_re_i)
----1--- ----2---
-1- | -2- | Status | Tests |
0 | 0 | Covered | T5,T6,T7 |
0 | 1 | Covered | T4,T11,T12 |
1 | 0 | Covered | T1,T2,T4 |
LINE 109
EXPRESSION (src_busy_q & ((!src_ack)))
-----1---- ------2-----
-1- | -2- | Status | Tests |
0 | 1 | Covered | T5,T6,T7 |
1 | 0 | Covered | T1,T2,T4 |
1 | 1 | Covered | T1,T2,T4 |
LINE 125
EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
-----------1----------- ------------2------------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T5,T6,T7 |
0 | 1 | Unreachable | |
1 | 0 | Covered | T1,T2,T4 |
LINE 125
SUB-EXPRESSION (src_busy_q && src_ack)
-----1---- ---2---
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T1,T2,T4 |
1 | 1 | Covered | T1,T2,T4 |
LINE 125
SUB-EXPRESSION (src_update && ((!busy)))
-----1---- ----2----
-1- | -2- | Status | Tests |
0 | 1 | Covered | T5,T6,T7 |
1 | 0 | Unreachable | |
1 | 1 | Unreachable | |
Branch Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_cdc
| Line No. | Total | Covered | Percent |
Branches |
|
8 |
8 |
100.00 |
IF |
71 |
4 |
4 |
100.00 |
IF |
115 |
4 |
4 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 71 if ((!rst_src_ni))
-2-: 73 if (src_req)
-3-: 75 if (src_ack)
Branches:
-1- | -2- | -3- | Status | Tests |
1 |
- |
- |
Covered |
T5,T6,T7 |
0 |
1 |
- |
Covered |
T1,T2,T4 |
0 |
0 |
1 |
Covered |
T1,T2,T4 |
0 |
0 |
0 |
Covered |
T5,T6,T7 |
LineNo. Expression
-1-: 115 if ((!rst_src_ni))
-2-: 118 if (src_req)
-3-: 125 if (((src_busy_q && src_ack) || (src_update && (!busy))))
Branches:
-1- | -2- | -3- | Status | Tests |
1 |
- |
- |
Covered |
T5,T6,T7 |
0 |
1 |
- |
Covered |
T1,T2,T4 |
0 |
0 |
1 |
Covered |
T1,T2,T4 |
0 |
0 |
0 |
Covered |
T5,T6,T7 |
Assert Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_cdc
Assertion Details
BusySrcReqChk_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
73828701 |
100140 |
0 |
0 |
T1 |
29517 |
71 |
0 |
0 |
T2 |
389922 |
688 |
0 |
0 |
T3 |
293261 |
408 |
0 |
0 |
T4 |
7472 |
58 |
0 |
0 |
T11 |
0 |
953 |
0 |
0 |
T12 |
0 |
938 |
0 |
0 |
T13 |
0 |
73 |
0 |
0 |
T14 |
0 |
332 |
0 |
0 |
T15 |
0 |
190 |
0 |
0 |
T18 |
1536 |
0 |
0 |
0 |
T19 |
2058 |
0 |
0 |
0 |
T20 |
1375 |
0 |
0 |
0 |
T21 |
1243 |
0 |
0 |
0 |
T22 |
2170 |
0 |
0 |
0 |
T23 |
673 |
0 |
0 |
0 |
T33 |
0 |
80 |
0 |
0 |
DstReqKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
111190200 |
110253825 |
0 |
0 |
T5 |
2185 |
2144 |
0 |
0 |
T6 |
2091 |
2022 |
0 |
0 |
T7 |
2833 |
2771 |
0 |
0 |
T24 |
2010 |
1976 |
0 |
0 |
T25 |
2049 |
1987 |
0 |
0 |
T26 |
1290 |
1269 |
0 |
0 |
T27 |
2793 |
2738 |
0 |
0 |
T28 |
698 |
671 |
0 |
0 |
T29 |
1827 |
1765 |
0 |
0 |
T30 |
983 |
962 |
0 |
0 |
SrcAckBusyChk_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
73828701 |
20253 |
0 |
0 |
T1 |
29517 |
20 |
0 |
0 |
T2 |
389922 |
136 |
0 |
0 |
T3 |
293261 |
50 |
0 |
0 |
T4 |
7472 |
16 |
0 |
0 |
T11 |
0 |
265 |
0 |
0 |
T12 |
0 |
259 |
0 |
0 |
T13 |
0 |
20 |
0 |
0 |
T14 |
0 |
40 |
0 |
0 |
T15 |
0 |
38 |
0 |
0 |
T18 |
1536 |
0 |
0 |
0 |
T19 |
2058 |
0 |
0 |
0 |
T20 |
1375 |
0 |
0 |
0 |
T21 |
1243 |
0 |
0 |
0 |
T22 |
2170 |
0 |
0 |
0 |
T23 |
673 |
0 |
0 |
0 |
T33 |
0 |
14 |
0 |
0 |
SrcBusyKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
73828701 |
71664740 |
0 |
0 |
T5 |
1098 |
1053 |
0 |
0 |
T6 |
1153 |
1095 |
0 |
0 |
T7 |
1037 |
994 |
0 |
0 |
T24 |
1153 |
1112 |
0 |
0 |
T25 |
1050 |
993 |
0 |
0 |
T26 |
2371 |
2288 |
0 |
0 |
T27 |
1354 |
1314 |
0 |
0 |
T28 |
1437 |
1356 |
0 |
0 |
T29 |
2423 |
2255 |
0 |
0 |
T30 |
2138 |
1985 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_cdc
| Line No. | Total | Covered | Percent |
TOTAL | | 22 | 22 | 100.00 |
CONT_ASSIGN | 65 | 1 | 1 | 100.00 |
ALWAYS | 71 | 6 | 6 | 100.00 |
CONT_ASSIGN | 85 | 1 | 1 | 100.00 |
CONT_ASSIGN | 109 | 1 | 1 | 100.00 |
ALWAYS | 115 | 9 | 9 | 100.00 |
CONT_ASSIGN | 150 | 1 | 1 | 100.00 |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 156 | 1 | 1 | 100.00 |
CONT_ASSIGN | 200 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
65 |
1 |
1 |
71 |
1 |
1 |
72 |
1 |
1 |
73 |
1 |
1 |
74 |
1 |
1 |
75 |
1 |
1 |
76 |
1 |
1 |
|
|
|
MISSING_ELSE |
85 |
1 |
1 |
109 |
1 |
1 |
115 |
1 |
1 |
116 |
1 |
1 |
117 |
1 |
1 |
118 |
1 |
1 |
123 |
1 |
1 |
124 |
1 |
1 |
125 |
1 |
1 |
134 |
1 |
1 |
135 |
1 |
1 |
|
|
|
MISSING_ELSE |
150 |
1 |
1 |
155 |
1 |
1 |
156 |
1 |
1 |
200 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_cdc
| Total | Covered | Percent |
Conditions | 12 | 11 | 91.67 |
Logical | 12 | 11 | 91.67 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 65
EXPRESSION (src_we_i | src_re_i)
----1--- ----2---
-1- | -2- | Status | Tests |
0 | 0 | Covered | T5,T6,T7 |
0 | 1 | Covered | T4,T11,T12 |
1 | 0 | Covered | T1,T2,T4 |
LINE 109
EXPRESSION (src_busy_q & ((!src_ack)))
-----1---- ------2-----
-1- | -2- | Status | Tests |
0 | 1 | Covered | T5,T6,T7 |
1 | 0 | Covered | T1,T2,T4 |
1 | 1 | Covered | T1,T2,T4 |
LINE 125
EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
-----------1----------- ------------2------------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T5,T6,T7 |
0 | 1 | Unreachable | |
1 | 0 | Covered | T1,T2,T4 |
LINE 125
SUB-EXPRESSION (src_busy_q && src_ack)
-----1---- ---2---
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T1,T2,T4 |
1 | 1 | Covered | T1,T2,T4 |
LINE 125
SUB-EXPRESSION (src_update && ((!busy)))
-----1---- ----2----
-1- | -2- | Status | Tests |
0 | 1 | Covered | T5,T6,T7 |
1 | 0 | Unreachable | |
1 | 1 | Unreachable | |
Branch Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_cdc
| Line No. | Total | Covered | Percent |
Branches |
|
8 |
8 |
100.00 |
IF |
71 |
4 |
4 |
100.00 |
IF |
115 |
4 |
4 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 71 if ((!rst_src_ni))
-2-: 73 if (src_req)
-3-: 75 if (src_ack)
Branches:
-1- | -2- | -3- | Status | Tests |
1 |
- |
- |
Covered |
T5,T6,T7 |
0 |
1 |
- |
Covered |
T1,T2,T4 |
0 |
0 |
1 |
Covered |
T1,T2,T4 |
0 |
0 |
0 |
Covered |
T5,T6,T7 |
LineNo. Expression
-1-: 115 if ((!rst_src_ni))
-2-: 118 if (src_req)
-3-: 125 if (((src_busy_q && src_ack) || (src_update && (!busy))))
Branches:
-1- | -2- | -3- | Status | Tests |
1 |
- |
- |
Covered |
T5,T6,T7 |
0 |
1 |
- |
Covered |
T1,T2,T4 |
0 |
0 |
1 |
Covered |
T1,T2,T4 |
0 |
0 |
0 |
Covered |
T5,T6,T7 |
Assert Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_cdc
Assertion Details
BusySrcReqChk_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
73828701 |
157176 |
0 |
0 |
T1 |
29517 |
102 |
0 |
0 |
T2 |
389922 |
1097 |
0 |
0 |
T3 |
293261 |
699 |
0 |
0 |
T4 |
7472 |
87 |
0 |
0 |
T11 |
0 |
1375 |
0 |
0 |
T12 |
0 |
1338 |
0 |
0 |
T13 |
0 |
108 |
0 |
0 |
T14 |
0 |
581 |
0 |
0 |
T15 |
0 |
311 |
0 |
0 |
T18 |
1536 |
0 |
0 |
0 |
T19 |
2058 |
0 |
0 |
0 |
T20 |
1375 |
0 |
0 |
0 |
T21 |
1243 |
0 |
0 |
0 |
T22 |
2170 |
0 |
0 |
0 |
T23 |
673 |
0 |
0 |
0 |
T33 |
0 |
132 |
0 |
0 |
DstReqKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
55594684 |
55126596 |
0 |
0 |
T5 |
1092 |
1071 |
0 |
0 |
T6 |
1045 |
1011 |
0 |
0 |
T7 |
1416 |
1385 |
0 |
0 |
T24 |
1005 |
988 |
0 |
0 |
T25 |
1024 |
993 |
0 |
0 |
T26 |
644 |
633 |
0 |
0 |
T27 |
1395 |
1367 |
0 |
0 |
T28 |
349 |
335 |
0 |
0 |
T29 |
911 |
880 |
0 |
0 |
T30 |
491 |
481 |
0 |
0 |
SrcAckBusyChk_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
73828701 |
20078 |
0 |
0 |
T1 |
29517 |
20 |
0 |
0 |
T2 |
389922 |
136 |
0 |
0 |
T3 |
293261 |
50 |
0 |
0 |
T4 |
7472 |
16 |
0 |
0 |
T11 |
0 |
265 |
0 |
0 |
T12 |
0 |
259 |
0 |
0 |
T13 |
0 |
20 |
0 |
0 |
T14 |
0 |
40 |
0 |
0 |
T15 |
0 |
38 |
0 |
0 |
T18 |
1536 |
0 |
0 |
0 |
T19 |
2058 |
0 |
0 |
0 |
T20 |
1375 |
0 |
0 |
0 |
T21 |
1243 |
0 |
0 |
0 |
T22 |
2170 |
0 |
0 |
0 |
T23 |
673 |
0 |
0 |
0 |
T33 |
0 |
14 |
0 |
0 |
SrcBusyKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
73828701 |
71664740 |
0 |
0 |
T5 |
1098 |
1053 |
0 |
0 |
T6 |
1153 |
1095 |
0 |
0 |
T7 |
1037 |
994 |
0 |
0 |
T24 |
1153 |
1112 |
0 |
0 |
T25 |
1050 |
993 |
0 |
0 |
T26 |
2371 |
2288 |
0 |
0 |
T27 |
1354 |
1314 |
0 |
0 |
T28 |
1437 |
1356 |
0 |
0 |
T29 |
2423 |
2255 |
0 |
0 |
T30 |
2138 |
1985 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_cdc
| Line No. | Total | Covered | Percent |
TOTAL | | 22 | 22 | 100.00 |
CONT_ASSIGN | 65 | 1 | 1 | 100.00 |
ALWAYS | 71 | 6 | 6 | 100.00 |
CONT_ASSIGN | 85 | 1 | 1 | 100.00 |
CONT_ASSIGN | 109 | 1 | 1 | 100.00 |
ALWAYS | 115 | 9 | 9 | 100.00 |
CONT_ASSIGN | 150 | 1 | 1 | 100.00 |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 156 | 1 | 1 | 100.00 |
CONT_ASSIGN | 200 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
65 |
1 |
1 |
71 |
1 |
1 |
72 |
1 |
1 |
73 |
1 |
1 |
74 |
1 |
1 |
75 |
1 |
1 |
76 |
1 |
1 |
|
|
|
MISSING_ELSE |
85 |
1 |
1 |
109 |
1 |
1 |
115 |
1 |
1 |
116 |
1 |
1 |
117 |
1 |
1 |
118 |
1 |
1 |
123 |
1 |
1 |
124 |
1 |
1 |
125 |
1 |
1 |
134 |
1 |
1 |
135 |
1 |
1 |
|
|
|
MISSING_ELSE |
150 |
1 |
1 |
155 |
1 |
1 |
156 |
1 |
1 |
200 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_cdc
| Total | Covered | Percent |
Conditions | 12 | 11 | 91.67 |
Logical | 12 | 11 | 91.67 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 65
EXPRESSION (src_we_i | src_re_i)
----1--- ----2---
-1- | -2- | Status | Tests |
0 | 0 | Covered | T5,T6,T7 |
0 | 1 | Covered | T4,T11,T12 |
1 | 0 | Covered | T1,T2,T4 |
LINE 109
EXPRESSION (src_busy_q & ((!src_ack)))
-----1---- ------2-----
-1- | -2- | Status | Tests |
0 | 1 | Covered | T5,T6,T7 |
1 | 0 | Covered | T1,T2,T4 |
1 | 1 | Covered | T1,T2,T4 |
LINE 125
EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
-----------1----------- ------------2------------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T5,T6,T7 |
0 | 1 | Unreachable | |
1 | 0 | Covered | T1,T2,T4 |
LINE 125
SUB-EXPRESSION (src_busy_q && src_ack)
-----1---- ---2---
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T1,T2,T4 |
1 | 1 | Covered | T1,T2,T4 |
LINE 125
SUB-EXPRESSION (src_update && ((!busy)))
-----1---- ----2----
-1- | -2- | Status | Tests |
0 | 1 | Covered | T5,T6,T7 |
1 | 0 | Unreachable | |
1 | 1 | Unreachable | |
Branch Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_cdc
| Line No. | Total | Covered | Percent |
Branches |
|
8 |
8 |
100.00 |
IF |
71 |
4 |
4 |
100.00 |
IF |
115 |
4 |
4 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 71 if ((!rst_src_ni))
-2-: 73 if (src_req)
-3-: 75 if (src_ack)
Branches:
-1- | -2- | -3- | Status | Tests |
1 |
- |
- |
Covered |
T5,T6,T7 |
0 |
1 |
- |
Covered |
T1,T2,T4 |
0 |
0 |
1 |
Covered |
T1,T2,T4 |
0 |
0 |
0 |
Covered |
T5,T6,T7 |
LineNo. Expression
-1-: 115 if ((!rst_src_ni))
-2-: 118 if (src_req)
-3-: 125 if (((src_busy_q && src_ack) || (src_update && (!busy))))
Branches:
-1- | -2- | -3- | Status | Tests |
1 |
- |
- |
Covered |
T5,T6,T7 |
0 |
1 |
- |
Covered |
T1,T2,T4 |
0 |
0 |
1 |
Covered |
T1,T2,T4 |
0 |
0 |
0 |
Covered |
T5,T6,T7 |
Assert Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_cdc
Assertion Details
BusySrcReqChk_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
73828701 |
68110 |
0 |
0 |
T1 |
29517 |
51 |
0 |
0 |
T2 |
389922 |
473 |
0 |
0 |
T3 |
293261 |
246 |
0 |
0 |
T4 |
7472 |
42 |
0 |
0 |
T11 |
0 |
665 |
0 |
0 |
T12 |
0 |
653 |
0 |
0 |
T13 |
0 |
52 |
0 |
0 |
T14 |
0 |
191 |
0 |
0 |
T15 |
0 |
131 |
0 |
0 |
T18 |
1536 |
0 |
0 |
0 |
T19 |
2058 |
0 |
0 |
0 |
T20 |
1375 |
0 |
0 |
0 |
T21 |
1243 |
0 |
0 |
0 |
T22 |
2170 |
0 |
0 |
0 |
T23 |
673 |
0 |
0 |
0 |
T33 |
0 |
55 |
0 |
0 |
DstReqKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
239150230 |
235222780 |
0 |
0 |
T5 |
4396 |
4213 |
0 |
0 |
T6 |
4439 |
4213 |
0 |
0 |
T7 |
5698 |
5443 |
0 |
0 |
T24 |
4271 |
4116 |
0 |
0 |
T25 |
4380 |
4140 |
0 |
0 |
T26 |
2371 |
2288 |
0 |
0 |
T27 |
5646 |
5477 |
0 |
0 |
T28 |
1481 |
1398 |
0 |
0 |
T29 |
3462 |
3221 |
0 |
0 |
T30 |
2159 |
2004 |
0 |
0 |
SrcAckBusyChk_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
73828701 |
20038 |
0 |
0 |
T1 |
29517 |
20 |
0 |
0 |
T2 |
389922 |
136 |
0 |
0 |
T3 |
293261 |
50 |
0 |
0 |
T4 |
7472 |
16 |
0 |
0 |
T11 |
0 |
265 |
0 |
0 |
T12 |
0 |
259 |
0 |
0 |
T13 |
0 |
20 |
0 |
0 |
T14 |
0 |
40 |
0 |
0 |
T15 |
0 |
38 |
0 |
0 |
T18 |
1536 |
0 |
0 |
0 |
T19 |
2058 |
0 |
0 |
0 |
T20 |
1375 |
0 |
0 |
0 |
T21 |
1243 |
0 |
0 |
0 |
T22 |
2170 |
0 |
0 |
0 |
T23 |
673 |
0 |
0 |
0 |
T33 |
0 |
14 |
0 |
0 |
SrcBusyKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
73828701 |
71664740 |
0 |
0 |
T5 |
1098 |
1053 |
0 |
0 |
T6 |
1153 |
1095 |
0 |
0 |
T7 |
1037 |
994 |
0 |
0 |
T24 |
1153 |
1112 |
0 |
0 |
T25 |
1050 |
993 |
0 |
0 |
T26 |
2371 |
2288 |
0 |
0 |
T27 |
1354 |
1314 |
0 |
0 |
T28 |
1437 |
1356 |
0 |
0 |
T29 |
2423 |
2255 |
0 |
0 |
T30 |
2138 |
1985 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_cdc
| Line No. | Total | Covered | Percent |
TOTAL | | 22 | 22 | 100.00 |
CONT_ASSIGN | 65 | 1 | 1 | 100.00 |
ALWAYS | 71 | 6 | 6 | 100.00 |
CONT_ASSIGN | 85 | 1 | 1 | 100.00 |
CONT_ASSIGN | 109 | 1 | 1 | 100.00 |
ALWAYS | 115 | 9 | 9 | 100.00 |
CONT_ASSIGN | 150 | 1 | 1 | 100.00 |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 156 | 1 | 1 | 100.00 |
CONT_ASSIGN | 200 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
65 |
1 |
1 |
71 |
1 |
1 |
72 |
1 |
1 |
73 |
1 |
1 |
74 |
1 |
1 |
75 |
1 |
1 |
76 |
1 |
1 |
|
|
|
MISSING_ELSE |
85 |
1 |
1 |
109 |
1 |
1 |
115 |
1 |
1 |
116 |
1 |
1 |
117 |
1 |
1 |
118 |
1 |
1 |
123 |
1 |
1 |
124 |
1 |
1 |
125 |
1 |
1 |
134 |
1 |
1 |
135 |
1 |
1 |
|
|
|
MISSING_ELSE |
150 |
1 |
1 |
155 |
1 |
1 |
156 |
1 |
1 |
200 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_cdc
| Total | Covered | Percent |
Conditions | 12 | 11 | 91.67 |
Logical | 12 | 11 | 91.67 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 65
EXPRESSION (src_we_i | src_re_i)
----1--- ----2---
-1- | -2- | Status | Tests |
0 | 0 | Covered | T5,T6,T7 |
0 | 1 | Covered | T4,T11,T12 |
1 | 0 | Covered | T1,T2,T4 |
LINE 109
EXPRESSION (src_busy_q & ((!src_ack)))
-----1---- ------2-----
-1- | -2- | Status | Tests |
0 | 1 | Covered | T5,T6,T7 |
1 | 0 | Covered | T1,T2,T4 |
1 | 1 | Covered | T1,T2,T4 |
LINE 125
EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
-----------1----------- ------------2------------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T5,T6,T7 |
0 | 1 | Unreachable | |
1 | 0 | Covered | T1,T2,T4 |
LINE 125
SUB-EXPRESSION (src_busy_q && src_ack)
-----1---- ---2---
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T1,T2,T4 |
1 | 1 | Covered | T1,T2,T4 |
LINE 125
SUB-EXPRESSION (src_update && ((!busy)))
-----1---- ----2----
-1- | -2- | Status | Tests |
0 | 1 | Covered | T5,T6,T7 |
1 | 0 | Unreachable | |
1 | 1 | Unreachable | |
Branch Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_cdc
| Line No. | Total | Covered | Percent |
Branches |
|
8 |
8 |
100.00 |
IF |
71 |
4 |
4 |
100.00 |
IF |
115 |
4 |
4 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 71 if ((!rst_src_ni))
-2-: 73 if (src_req)
-3-: 75 if (src_ack)
Branches:
-1- | -2- | -3- | Status | Tests |
1 |
- |
- |
Covered |
T5,T6,T7 |
0 |
1 |
- |
Covered |
T1,T2,T4 |
0 |
0 |
1 |
Covered |
T1,T2,T4 |
0 |
0 |
0 |
Covered |
T5,T6,T7 |
LineNo. Expression
-1-: 115 if ((!rst_src_ni))
-2-: 118 if (src_req)
-3-: 125 if (((src_busy_q && src_ack) || (src_update && (!busy))))
Branches:
-1- | -2- | -3- | Status | Tests |
1 |
- |
- |
Covered |
T5,T6,T7 |
0 |
1 |
- |
Covered |
T1,T2,T4 |
0 |
0 |
1 |
Covered |
T1,T2,T4 |
0 |
0 |
0 |
Covered |
T5,T6,T7 |
Assert Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_cdc
Assertion Details
BusySrcReqChk_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
73828701 |
98342 |
0 |
0 |
T1 |
29517 |
71 |
0 |
0 |
T2 |
389922 |
824 |
0 |
0 |
T3 |
293261 |
410 |
0 |
0 |
T4 |
7472 |
59 |
0 |
0 |
T11 |
0 |
949 |
0 |
0 |
T12 |
0 |
941 |
0 |
0 |
T13 |
0 |
73 |
0 |
0 |
T14 |
0 |
313 |
0 |
0 |
T15 |
0 |
190 |
0 |
0 |
T18 |
1536 |
0 |
0 |
0 |
T19 |
2058 |
0 |
0 |
0 |
T20 |
1375 |
0 |
0 |
0 |
T21 |
1243 |
0 |
0 |
0 |
T22 |
2170 |
0 |
0 |
0 |
T23 |
673 |
0 |
0 |
0 |
T33 |
0 |
81 |
0 |
0 |
DstReqKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
114657872 |
112776678 |
0 |
0 |
T5 |
2110 |
2023 |
0 |
0 |
T6 |
2131 |
2023 |
0 |
0 |
T7 |
2787 |
2665 |
0 |
0 |
T24 |
2050 |
1976 |
0 |
0 |
T25 |
2102 |
1987 |
0 |
0 |
T26 |
1138 |
1099 |
0 |
0 |
T27 |
2710 |
2629 |
0 |
0 |
T28 |
710 |
671 |
0 |
0 |
T29 |
1661 |
1546 |
0 |
0 |
T30 |
1036 |
962 |
0 |
0 |
SrcAckBusyChk_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
73828701 |
19837 |
0 |
0 |
T1 |
29517 |
20 |
0 |
0 |
T2 |
389922 |
136 |
0 |
0 |
T3 |
293261 |
50 |
0 |
0 |
T4 |
7472 |
16 |
0 |
0 |
T11 |
0 |
265 |
0 |
0 |
T12 |
0 |
259 |
0 |
0 |
T13 |
0 |
20 |
0 |
0 |
T14 |
0 |
40 |
0 |
0 |
T15 |
0 |
38 |
0 |
0 |
T18 |
1536 |
0 |
0 |
0 |
T19 |
2058 |
0 |
0 |
0 |
T20 |
1375 |
0 |
0 |
0 |
T21 |
1243 |
0 |
0 |
0 |
T22 |
2170 |
0 |
0 |
0 |
T23 |
673 |
0 |
0 |
0 |
T33 |
0 |
14 |
0 |
0 |
SrcBusyKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
73828701 |
71664740 |
0 |
0 |
T5 |
1098 |
1053 |
0 |
0 |
T6 |
1153 |
1095 |
0 |
0 |
T7 |
1037 |
994 |
0 |
0 |
T24 |
1153 |
1112 |
0 |
0 |
T25 |
1050 |
993 |
0 |
0 |
T26 |
2371 |
2288 |
0 |
0 |
T27 |
1354 |
1314 |
0 |
0 |
T28 |
1437 |
1356 |
0 |
0 |
T29 |
2423 |
2255 |
0 |
0 |
T30 |
2138 |
1985 |
0 |
0 |