Unified Coverage Report :: Module :: clkmgr_trans

Module : clkmgr_trans

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
0.00	0.00	0.00			0.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_opentitan_top_earlgrey_clkmgr_0.1/rtl/clkmgr_trans.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_clk_main_aes_trans	0.00	0.00	0.00			0.00
tb.dut.u_clk_main_hmac_trans	0.00	0.00	0.00			0.00
tb.dut.u_clk_main_kmac_trans	0.00	0.00	0.00			0.00
tb.dut.u_clk_main_otbn_trans	0.00	0.00	0.00			0.00

---

Module Instance : tb.dut.u_clk_main_aes_trans

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
0.00	0.00	0.00			0.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
0.00	0.00	0.00	0.00		0.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
21.89	0.00	0.00	87.58		0.00		dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_cg	0.00	0.00	0.00			0.00
u_en_sync	0.00	0.00				0.00
u_err_sync	0.00	0.00				0.00
u_hint_sync	0.00	0.00				0.00
u_idle_cnt	0.00			0.00
u_idle_sync	0.00	0.00	0.00			0.00
u_prim_buf_en	0.00	0.00
u_prim_mubi4_sender	0.00	0.00				0.00
u_scanmode_sync	0.00	0.00

---

Module Instance : tb.dut.u_clk_main_hmac_trans

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
0.00	0.00	0.00			0.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
0.00	0.00	0.00	0.00		0.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
21.89	0.00	0.00	87.58		0.00		dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_cg	0.00	0.00	0.00			0.00
u_en_sync	0.00	0.00				0.00
u_err_sync	0.00	0.00				0.00
u_hint_sync	0.00	0.00				0.00
u_idle_cnt	0.00			0.00
u_idle_sync	0.00	0.00	0.00			0.00
u_prim_buf_en	0.00	0.00
u_prim_mubi4_sender	0.00	0.00				0.00
u_scanmode_sync	0.00	0.00

---

Module Instance : tb.dut.u_clk_main_kmac_trans

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
0.00	0.00	0.00			0.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
0.00	0.00	0.00	0.00		0.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
21.89	0.00	0.00	87.58		0.00		dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_cg	0.00	0.00	0.00			0.00
u_en_sync	0.00	0.00				0.00
u_err_sync	0.00	0.00				0.00
u_hint_sync	0.00	0.00				0.00
u_idle_cnt	0.00			0.00
u_idle_sync	0.00	0.00	0.00			0.00
u_prim_buf_en	0.00	0.00
u_prim_mubi4_sender	0.00	0.00				0.00
u_scanmode_sync	0.00	0.00

---

Module Instance : tb.dut.u_clk_main_otbn_trans

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
0.00	0.00	0.00			0.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
0.00	0.00	0.00	0.00		0.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
21.89	0.00	0.00	87.58		0.00		dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_cg	0.00	0.00	0.00			0.00
u_en_sync	0.00	0.00				0.00
u_err_sync	0.00	0.00				0.00
u_hint_sync	0.00	0.00				0.00
u_idle_cnt	0.00			0.00
u_idle_sync	0.00	0.00	0.00			0.00
u_prim_buf_en	0.00	0.00
u_prim_mubi4_sender	0.00	0.00				0.00
u_scanmode_sync	0.00	0.00

Line Coverage for Module : clkmgr_trans

	Line No.	Total	Covered	Percent
TOTAL		9	0	0.00
CONT_ASSIGN	45	1	0	0.00
CONT_ASSIGN	46	1	0	0.00
ALWAYS	140	4	0	0.00
ALWAYS	158	3	0	0.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_opentitan_top_earlgrey_clkmgr_0.1/rtl/clkmgr_trans.sv' or '../src/lowrisc_opentitan_top_earlgrey_clkmgr_0.1/rtl/clkmgr_trans.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
45	0	1
46	0	1
140	0	1
141	0	1
142	0	1
143	0	1
			==> MISSING_ELSE
158	0	1
159	0	1
161	0	1

---

Cond Coverage for Module : clkmgr_trans

	Total	Covered	Percent
Conditions	10	0	0.00
Logical	10	0	0.00
Non-Logical	0	0
Event	0	0

 LINE       45
 EXPRESSION (idle_cnt == 4'(TransIdleCnt))
            ---------------1--------------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       46
 EXPRESSION (sw_hint_synced | ((~idle_valid)))
             -------1------   -------2-------

-1-	-2-	Status	Tests
0	0	Not Covered
0	1	Not Covered
1	0	Not Covered

 LINE       106
 EXPRESSION (local_en & en_i)
             ----1---   --2-

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

 LINE       125
 EXPRESSION (combined_en_d ? MuBi4False : MuBi4True)
             ------1------

-1-	Status	Tests
0	Not Covered
1	Not Covered

---

Branch Coverage for Module : clkmgr_trans

	Line No.	Total	Covered	Percent
Branches		7	0	0.00
TERNARY	125	2	0	0.00
IF	140	3	0	0.00
IF	158	2	0	0.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_opentitan_top_earlgrey_clkmgr_0.1/rtl/clkmgr_trans.sv' or '../src/lowrisc_opentitan_top_earlgrey_clkmgr_0.1/rtl/clkmgr_trans.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	125	(combined_en_d) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered

	LineNo.	Expression
-1-:	140	if ((!rst_ni))
-2-:	142	if (cnt_err)

Branches:

-1-	-2-	Status	Tests
1	-	Not Covered
0	1	Not Covered
0	0	Not Covered

	LineNo.	Expression
-1-:	158	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered

Line Coverage for Instance : tb.dut.u_clk_main_aes_trans

	Line No.	Total	Covered	Percent
TOTAL		9	0	0.00
CONT_ASSIGN	45	1	0	0.00
CONT_ASSIGN	46	1	0	0.00
ALWAYS	140	4	0	0.00
ALWAYS	158	3	0	0.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_opentitan_top_earlgrey_clkmgr_0.1/rtl/clkmgr_trans.sv' or '../src/lowrisc_opentitan_top_earlgrey_clkmgr_0.1/rtl/clkmgr_trans.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
45	0	1
46	0	1
140	0	1
141	0	1
142	0	1
143	0	1
			==> MISSING_ELSE
158	0	1
159	0	1
161	0	1

---

Cond Coverage for Instance : tb.dut.u_clk_main_aes_trans

	Total	Covered	Percent
Conditions	10	0	0.00
Logical	10	0	0.00
Non-Logical	0	0
Event	0	0

 LINE       45
 EXPRESSION (idle_cnt == 4'(TransIdleCnt))
            ---------------1--------------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       46
 EXPRESSION (sw_hint_synced | ((~idle_valid)))
             -------1------   -------2-------

-1-	-2-	Status	Tests
0	0	Not Covered
0	1	Not Covered
1	0	Not Covered

 LINE       106
 EXPRESSION (local_en & en_i)
             ----1---   --2-

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

 LINE       125
 EXPRESSION (combined_en_d ? MuBi4False : MuBi4True)
             ------1------

-1-	Status	Tests
0	Not Covered
1	Not Covered

---

Branch Coverage for Instance : tb.dut.u_clk_main_aes_trans

	Line No.	Total	Covered	Percent
Branches		7	0	0.00
TERNARY	125	2	0	0.00
IF	140	3	0	0.00
IF	158	2	0	0.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_opentitan_top_earlgrey_clkmgr_0.1/rtl/clkmgr_trans.sv' or '../src/lowrisc_opentitan_top_earlgrey_clkmgr_0.1/rtl/clkmgr_trans.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	125	(combined_en_d) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered

	LineNo.	Expression
-1-:	140	if ((!rst_ni))
-2-:	142	if (cnt_err)

Branches:

-1-	-2-	Status	Tests
1	-	Not Covered
0	1	Not Covered
0	0	Not Covered

	LineNo.	Expression
-1-:	158	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered

Line Coverage for Instance : tb.dut.u_clk_main_hmac_trans

	Line No.	Total	Covered	Percent
TOTAL		9	0	0.00
CONT_ASSIGN	45	1	0	0.00
CONT_ASSIGN	46	1	0	0.00
ALWAYS	140	4	0	0.00
ALWAYS	158	3	0	0.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_opentitan_top_earlgrey_clkmgr_0.1/rtl/clkmgr_trans.sv' or '../src/lowrisc_opentitan_top_earlgrey_clkmgr_0.1/rtl/clkmgr_trans.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
45	0	1
46	0	1
140	0	1
141	0	1
142	0	1
143	0	1
			==> MISSING_ELSE
158	0	1
159	0	1
161	0	1

---

Cond Coverage for Instance : tb.dut.u_clk_main_hmac_trans

	Total	Covered	Percent
Conditions	10	0	0.00
Logical	10	0	0.00
Non-Logical	0	0
Event	0	0

 LINE       45
 EXPRESSION (idle_cnt == 4'(TransIdleCnt))
            ---------------1--------------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       46
 EXPRESSION (sw_hint_synced | ((~idle_valid)))
             -------1------   -------2-------

-1-	-2-	Status	Tests
0	0	Not Covered
0	1	Not Covered
1	0	Not Covered

 LINE       106
 EXPRESSION (local_en & en_i)
             ----1---   --2-

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

 LINE       125
 EXPRESSION (combined_en_d ? MuBi4False : MuBi4True)
             ------1------

-1-	Status	Tests
0	Not Covered
1	Not Covered

---

Branch Coverage for Instance : tb.dut.u_clk_main_hmac_trans

	Line No.	Total	Covered	Percent
Branches		7	0	0.00
TERNARY	125	2	0	0.00
IF	140	3	0	0.00
IF	158	2	0	0.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_opentitan_top_earlgrey_clkmgr_0.1/rtl/clkmgr_trans.sv' or '../src/lowrisc_opentitan_top_earlgrey_clkmgr_0.1/rtl/clkmgr_trans.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	125	(combined_en_d) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered

	LineNo.	Expression
-1-:	140	if ((!rst_ni))
-2-:	142	if (cnt_err)

Branches:

-1-	-2-	Status	Tests
1	-	Not Covered
0	1	Not Covered
0	0	Not Covered

	LineNo.	Expression
-1-:	158	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered

Line Coverage for Instance : tb.dut.u_clk_main_kmac_trans

	Line No.	Total	Covered	Percent
TOTAL		9	0	0.00
CONT_ASSIGN	45	1	0	0.00
CONT_ASSIGN	46	1	0	0.00
ALWAYS	140	4	0	0.00
ALWAYS	158	3	0	0.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_opentitan_top_earlgrey_clkmgr_0.1/rtl/clkmgr_trans.sv' or '../src/lowrisc_opentitan_top_earlgrey_clkmgr_0.1/rtl/clkmgr_trans.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
45	0	1
46	0	1
140	0	1
141	0	1
142	0	1
143	0	1
			==> MISSING_ELSE
158	0	1
159	0	1
161	0	1

---

Cond Coverage for Instance : tb.dut.u_clk_main_kmac_trans

	Total	Covered	Percent
Conditions	10	0	0.00
Logical	10	0	0.00
Non-Logical	0	0
Event	0	0

 LINE       45
 EXPRESSION (idle_cnt == 4'(TransIdleCnt))
            ---------------1--------------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       46
 EXPRESSION (sw_hint_synced | ((~idle_valid)))
             -------1------   -------2-------

-1-	-2-	Status	Tests
0	0	Not Covered
0	1	Not Covered
1	0	Not Covered

 LINE       106
 EXPRESSION (local_en & en_i)
             ----1---   --2-

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

 LINE       125
 EXPRESSION (combined_en_d ? MuBi4False : MuBi4True)
             ------1------

-1-	Status	Tests
0	Not Covered
1	Not Covered

---

Branch Coverage for Instance : tb.dut.u_clk_main_kmac_trans

	Line No.	Total	Covered	Percent
Branches		7	0	0.00
TERNARY	125	2	0	0.00
IF	140	3	0	0.00
IF	158	2	0	0.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_opentitan_top_earlgrey_clkmgr_0.1/rtl/clkmgr_trans.sv' or '../src/lowrisc_opentitan_top_earlgrey_clkmgr_0.1/rtl/clkmgr_trans.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	125	(combined_en_d) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered

	LineNo.	Expression
-1-:	140	if ((!rst_ni))
-2-:	142	if (cnt_err)

Branches:

-1-	-2-	Status	Tests
1	-	Not Covered
0	1	Not Covered
0	0	Not Covered

	LineNo.	Expression
-1-:	158	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered

Line Coverage for Instance : tb.dut.u_clk_main_otbn_trans

	Line No.	Total	Covered	Percent
TOTAL		9	0	0.00
CONT_ASSIGN	45	1	0	0.00
CONT_ASSIGN	46	1	0	0.00
ALWAYS	140	4	0	0.00
ALWAYS	158	3	0	0.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_opentitan_top_earlgrey_clkmgr_0.1/rtl/clkmgr_trans.sv' or '../src/lowrisc_opentitan_top_earlgrey_clkmgr_0.1/rtl/clkmgr_trans.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
45	0	1
46	0	1
140	0	1
141	0	1
142	0	1
143	0	1
			==> MISSING_ELSE
158	0	1
159	0	1
161	0	1

---

Cond Coverage for Instance : tb.dut.u_clk_main_otbn_trans

	Total	Covered	Percent
Conditions	10	0	0.00
Logical	10	0	0.00
Non-Logical	0	0
Event	0	0

 LINE       45
 EXPRESSION (idle_cnt == 4'(TransIdleCnt))
            ---------------1--------------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       46
 EXPRESSION (sw_hint_synced | ((~idle_valid)))
             -------1------   -------2-------

-1-	-2-	Status	Tests
0	0	Not Covered
0	1	Not Covered
1	0	Not Covered

 LINE       106
 EXPRESSION (local_en & en_i)
             ----1---   --2-

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

 LINE       125
 EXPRESSION (combined_en_d ? MuBi4False : MuBi4True)
             ------1------

-1-	Status	Tests
0	Not Covered
1	Not Covered

---

Branch Coverage for Instance : tb.dut.u_clk_main_otbn_trans

	Line No.	Total	Covered	Percent
Branches		7	0	0.00
TERNARY	125	2	0	0.00
IF	140	3	0	0.00
IF	158	2	0	0.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_opentitan_top_earlgrey_clkmgr_0.1/rtl/clkmgr_trans.sv' or '../src/lowrisc_opentitan_top_earlgrey_clkmgr_0.1/rtl/clkmgr_trans.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	125	(combined_en_d) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered

	LineNo.	Expression
-1-:	140	if ((!rst_ni))
-2-:	142	if (cnt_err)

Branches:

-1-	-2-	Status	Tests
1	-	Not Covered
0	1	Not Covered
0	0	Not Covered

	LineNo.	Expression
-1-:	158	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered