Unified Coverage Report :: Module :: clkmgr

Module : clkmgr

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
21.89	0.00	0.00	87.58		0.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_opentitan_top_earlgrey_clkmgr_0.1/rtl/clkmgr.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut	21.89	0.00	0.00	87.58		0.00

---

Module Instance : tb.dut

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
21.89	0.00	0.00	87.58		0.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
53.17	41.92	57.65	81.32	0.00	48.71	89.43

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							tb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
clkmgr_cg_io_div2_infra	0.00	0.00	0.00
clkmgr_cg_io_div2_peri	0.00	0.00	0.00
clkmgr_cg_io_div4_infra	0.00	0.00	0.00
clkmgr_cg_io_div4_peri	0.00	0.00	0.00
clkmgr_cg_io_div4_secure	0.00	0.00	0.00
clkmgr_cg_io_div4_timers	0.00	0.00	0.00
clkmgr_cg_io_infra	0.00	0.00	0.00
clkmgr_cg_io_peri	0.00	0.00	0.00
clkmgr_cg_main_aes	0.00	0.00	0.00
clkmgr_cg_main_hmac	0.00	0.00	0.00
clkmgr_cg_main_infra	0.00	0.00	0.00
clkmgr_cg_main_kmac	0.00	0.00	0.00
clkmgr_cg_main_otbn	0.00	0.00	0.00
clkmgr_cg_main_secure	0.00	0.00	0.00
clkmgr_cg_usb_infra	0.00	0.00	0.00
clkmgr_cg_usb_peri	0.00	0.00	0.00
clkmgr_csr_assert	100.00						100.00
clkmgr_div2_sva_if	0.00	0.00	0.00
clkmgr_div4_sva_if	0.00	0.00	0.00
clkmgr_extclk_sva_if	0.00	0.00	0.00
clkmgr_io_div2_peri_sva_if	0.00	0.00	0.00
clkmgr_io_div4_peri_sva_if	0.00	0.00	0.00
clkmgr_io_peri_sva_if	0.00	0.00	0.00
clkmgr_sec_cm_checker_assert	0.00	0.00	0.00
clkmgr_usb_peri_sva_if	0.00	0.00	0.00
gen_alert_tx[0].u_prim_alert_sender	100.00			100.00
gen_alert_tx[1].u_prim_alert_sender	100.00			100.00
tlul_assert_device	32.63	0.00				0.00	97.90
u_calib_rdy_sync	0.00	0.00				0.00
u_clk_aon_buf	0.00	0.00
u_clk_aon_peri_buf	0.00	0.00
u_clk_aon_powerup_buf	0.00	0.00
u_clk_aon_secure_buf	0.00	0.00
u_clk_aon_timers_buf	0.00	0.00
u_clk_io_buf	0.00	0.00
u_clk_io_div2_peri_cg	0.00	0.00	0.00			0.00
u_clk_io_div2_peri_scanmode_sync	0.00	0.00
u_clk_io_div2_peri_sw_en_sync	0.00	0.00				0.00
u_clk_io_div2_powerup_buf	0.00	0.00
u_clk_io_div4_peri_cg	0.00	0.00	0.00			0.00
u_clk_io_div4_peri_scanmode_sync	0.00	0.00
u_clk_io_div4_peri_sw_en_sync	0.00	0.00				0.00
u_clk_io_div4_powerup_buf	0.00	0.00
u_clk_io_peri_cg	0.00	0.00	0.00			0.00
u_clk_io_peri_scanmode_sync	0.00	0.00
u_clk_io_peri_sw_en_sync	0.00	0.00				0.00
u_clk_io_powerup_buf	0.00	0.00
u_clk_main_aes_trans	0.00	0.00	0.00	0.00		0.00
u_clk_main_buf	0.00	0.00
u_clk_main_hmac_trans	0.00	0.00	0.00	0.00		0.00
u_clk_main_kmac_trans	0.00	0.00	0.00	0.00		0.00
u_clk_main_otbn_trans	0.00	0.00	0.00	0.00		0.00
u_clk_main_powerup_buf	0.00	0.00
u_clk_usb_buf	0.00	0.00
u_clk_usb_peri_cg	0.00	0.00	0.00			0.00
u_clk_usb_peri_scanmode_sync	0.00	0.00
u_clk_usb_peri_sw_en_sync	0.00	0.00				0.00
u_clk_usb_powerup_buf	0.00	0.00
u_clkmgr_byp	0.00	0.00	0.00			0.00
u_io_div2_div_scanmode_sync	0.00	0.00
u_io_div2_meas	0.00	0.00	0.00		0.00	0.00
u_io_div2_root_ctrl	0.00	0.00	0.00			0.00
u_io_div4_div_scanmode_sync	0.00	0.00
u_io_div4_meas	0.00	0.00	0.00		0.00	0.00
u_io_div4_root_ctrl	0.00	0.00	0.00			0.00
u_io_meas	0.00	0.00	0.00		0.00	0.00
u_io_root_ctrl	0.00	0.00	0.00			0.00
u_io_status	0.00	0.00				0.00
u_io_step_down_req_sync	0.00	0.00	0.00			0.00
u_main_meas	0.00	0.00	0.00		0.00	0.00
u_main_root_ctrl	0.00	0.00	0.00			0.00
u_main_status	0.00	0.00				0.00
u_no_scan_io_div2_div	0.00	0.00	0.00			0.00
u_no_scan_io_div4_div	0.00	0.00	0.00			0.00
u_prim_mubi4_sender_clk_io_div2_infra	0.00	0.00				0.00
u_prim_mubi4_sender_clk_io_div2_peri	0.00	0.00				0.00
u_prim_mubi4_sender_clk_io_div4_infra	0.00	0.00				0.00
u_prim_mubi4_sender_clk_io_div4_peri	0.00	0.00				0.00
u_prim_mubi4_sender_clk_io_div4_secure	0.00	0.00				0.00
u_prim_mubi4_sender_clk_io_div4_timers	0.00	0.00				0.00
u_prim_mubi4_sender_clk_io_infra	0.00	0.00				0.00
u_prim_mubi4_sender_clk_io_peri	0.00	0.00				0.00
u_prim_mubi4_sender_clk_main_infra	0.00	0.00				0.00
u_prim_mubi4_sender_clk_main_secure	0.00	0.00				0.00
u_prim_mubi4_sender_clk_usb_infra	0.00	0.00				0.00
u_prim_mubi4_sender_clk_usb_peri	0.00	0.00				0.00
u_reg	81.08	79.70	78.72	89.50		85.62	71.83
u_usb_meas	0.00	0.00	0.00		0.00	0.00
u_usb_root_ctrl	0.00	0.00	0.00			0.00
u_usb_status	0.00	0.00				0.00

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : clkmgr

	Line No.	Total	Covered	Percent
TOTAL		34	0	0.00
CONT_ASSIGN	260	1	0	0.00
CONT_ASSIGN	266	1	0	0.00
CONT_ASSIGN	279	1	0	0.00
CONT_ASSIGN	309	1	0	0.00
CONT_ASSIGN	310	1	0	0.00
CONT_ASSIGN	408	1	0	0.00
CONT_ASSIGN	413	1	0	0.00
CONT_ASSIGN	414	1	0	0.00
CONT_ASSIGN	415	1	0	0.00
CONT_ASSIGN	418	1	0	0.00
CONT_ASSIGN	437	1	0	0.00
CONT_ASSIGN	462	1	0	0.00
CONT_ASSIGN	474	1	0	0.00
CONT_ASSIGN	486	1	0	0.00
CONT_ASSIGN	511	1	0	0.00
ALWAYS	552	5	0	0.00
CONT_ASSIGN	699	1	0	0.00
CONT_ASSIGN	710	1	0	0.00
CONT_ASSIGN	721	1	0	0.00
CONT_ASSIGN	732	1	0	0.00
CONT_ASSIGN	743	1	0	0.00
CONT_ASSIGN	754	1	0	0.00
CONT_ASSIGN	765	1	0	0.00
CONT_ASSIGN	776	1	0	0.00
CONT_ASSIGN	819	1	0	0.00
CONT_ASSIGN	861	1	0	0.00
CONT_ASSIGN	903	1	0	0.00
CONT_ASSIGN	945	1	0	0.00
CONT_ASSIGN	1062	1	0	0.00
CONT_ASSIGN	1071	1	0	0.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_opentitan_top_earlgrey_clkmgr_0.1/rtl/clkmgr.sv' or '../src/lowrisc_opentitan_top_earlgrey_clkmgr_0.1/rtl/clkmgr.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
260	0	1
266	0	1
279	0	1
309	0	1
310	0	1
408	0	1
413	0	1
414	0	1
415	0	1
418	0	1
437	0	1
462	0	1
474	0	1
486	0	1
511	0	1
552	0	1
553	0	1
555	0	1
556	0	1
557	0	1
			==> MISSING_ELSE
699	0	1
710	0	1
721	0	1
732	0	1
743	0	1
754	0	1
765	0	1
776	0	1
819	0	1
861	0	1
903	0	1
945	0	1
1062	0	1
1071	0	1

---

Cond Coverage for Module : clkmgr

	Total	Covered	Percent
Conditions	148	0	0.00
Logical	148	0	0.00
Non-Logical	0	0
Event	0	0

 LINE       37
 EXPRESSION (scanmode_i == MuBi4True)
            ------------1------------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       46
 EXPRESSION (scanmode_i == MuBi4True)
            ------------1------------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       55
 EXPRESSION (scanmode_i == MuBi4True)
            ------------1------------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       64
 EXPRESSION (scanmode_i == MuBi4True)
            ------------1------------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       74
 EXPRESSION (idle_i[HintMainAes] == MuBi4True)
            -----------------1----------------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       74
 EXPRESSION (scanmode_i == MuBi4True)
            ------------1------------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       84
 EXPRESSION (idle_i[HintMainHmac] == MuBi4True)
            -----------------1-----------------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       84
 EXPRESSION (scanmode_i == MuBi4True)
            ------------1------------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       94
 EXPRESSION (idle_i[HintMainKmac] == MuBi4True)
            -----------------1-----------------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       94
 EXPRESSION (scanmode_i == MuBi4True)
            ------------1------------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       104
 EXPRESSION (idle_i[HintMainOtbn] == MuBi4True)
            -----------------1-----------------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       104
 EXPRESSION (scanmode_i == MuBi4True)
            ------------1------------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       128
 EXPRESSION (div_step_down_req_i == MuBi4True)
            -----------------1----------------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       128
 EXPRESSION (scanmode_i == MuBi4True)
            ------------1------------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       139
 EXPRESSION (div_step_down_req_i == MuBi4True)
            -----------------1----------------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       139
 EXPRESSION (scanmode_i == MuBi4True)
            ------------1------------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       148
 EXPRESSION (cg_en_o.aon_peri == MuBi4True)
            ---------------1---------------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       152
 EXPRESSION (cg_en_o.aon_powerup == MuBi4True)
            -----------------1----------------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       156
 EXPRESSION (cg_en_o.aon_secure == MuBi4True)
            ----------------1----------------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       160
 EXPRESSION (cg_en_o.aon_timers == MuBi4True)
            ----------------1----------------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       164
 EXPRESSION (cg_en_o.io_div2_powerup == MuBi4True)
            -------------------1------------------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       168
 EXPRESSION (cg_en_o.io_div4_powerup == MuBi4True)
            -------------------1------------------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       172
 EXPRESSION (cg_en_o.io_powerup == MuBi4True)
            ----------------1----------------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       176
 EXPRESSION (cg_en_o.main_powerup == MuBi4True)
            -----------------1-----------------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       180
 EXPRESSION (cg_en_o.usb_powerup == MuBi4True)
            -----------------1----------------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       185
 EXPRESSION (cg_en_o.io_div2_infra == MuBi4True)
            ------------------1-----------------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       194
 EXPRESSION (cg_en_o.io_div4_infra == MuBi4True)
            ------------------1-----------------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       203
 EXPRESSION (cg_en_o.io_div4_secure == MuBi4True)
            ------------------1------------------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       212
 EXPRESSION (cg_en_o.io_div4_timers == MuBi4True)
            ------------------1------------------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       221
 EXPRESSION (cg_en_o.io_infra == MuBi4True)
            ---------------1---------------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       230
 EXPRESSION (cg_en_o.main_infra == MuBi4True)
            ----------------1----------------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       239
 EXPRESSION (cg_en_o.main_secure == MuBi4True)
            -----------------1----------------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       248
 EXPRESSION (cg_en_o.usb_infra == MuBi4True)
            ----------------1---------------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       258
 EXPRESSION (cg_en_o.io_div4_peri == MuBi4True)
            -----------------1-----------------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       260
 SUB-EXPRESSION (reg2hw.alert_test.fatal_fault.q & reg2hw.alert_test.fatal_fault.qe)
                 ---------------1---------------   ----------------2---------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

 LINE       260
 SUB-EXPRESSION (reg2hw.alert_test.recov_fault.q & reg2hw.alert_test.recov_fault.qe)
                 ---------------1---------------   ----------------2---------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

 LINE       266
 EXPRESSION 
 Number  Term
      1  hw2reg.recov_err_code.io_measure_err.de | 
      2  hw2reg.recov_err_code.io_timeout_err.de | 
      3  hw2reg.recov_err_code.io_div2_measure_err.de | 
      4  hw2reg.recov_err_code.io_div2_timeout_err.de | 
      5  hw2reg.recov_err_code.io_div4_measure_err.de | 
      6  hw2reg.recov_err_code.io_div4_timeout_err.de | 
      7  hw2reg.recov_err_code.main_measure_err.de | 
      8  hw2reg.recov_err_code.main_timeout_err.de | 
      9  hw2reg.recov_err_code.usb_measure_err.de | 
     10  hw2reg.recov_err_code.usb_timeout_err.de | 
     11  hw2reg.recov_err_code.shadow_update_err.de)

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	Status	Tests
0	0	0	0	0	0	0	0	0	0	0	Not Covered
0	0	0	0	0	0	0	0	0	0	1	Not Covered
0	0	0	0	0	0	0	0	0	1	0	Not Covered
0	0	0	0	0	0	0	0	1	0	0	Not Covered
0	0	0	0	0	0	0	1	0	0	0	Not Covered
0	0	0	0	0	0	1	0	0	0	0	Not Covered
0	0	0	0	0	1	0	0	0	0	0	Not Covered
0	0	0	0	1	0	0	0	0	0	0	Not Covered
0	0	0	1	0	0	0	0	0	0	0	Not Covered
0	0	1	0	0	0	0	0	0	0	0	Not Covered
0	1	0	0	0	0	0	0	0	0	0	Not Covered
1	0	0	0	0	0	0	0	0	0	0	Not Covered

 LINE       267
 EXPRESSION (cg_en_o.io_div2_peri == MuBi4True)
            -----------------1-----------------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       276
 EXPRESSION (cg_en_o.io_peri == MuBi4True)
            ---------------1--------------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       285
 EXPRESSION (cg_en_o.usb_peri == MuBi4True)
            ---------------1---------------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       295
 EXPRESSION (clkmgr.u_clk_main_aes_trans.sw_hint_synced || ((!clkmgr.u_clk_main_aes_trans.idle_valid)))
             ---------------------1--------------------    ---------------------2---------------------

-1-	-2-	Status	Tests
0	0	Not Covered
0	1	Not Covered
1	0	Not Covered

 LINE       295
 EXPRESSION (cg_en_o.main_aes == MuBi4True)
            ---------------1---------------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       304
 EXPRESSION (clkmgr.u_clk_main_hmac_trans.sw_hint_synced || ((!clkmgr.u_clk_main_hmac_trans.idle_valid)))
             ---------------------1---------------------    ----------------------2---------------------

-1-	-2-	Status	Tests
0	0	Not Covered
0	1	Not Covered
1	0	Not Covered

 LINE       304
 EXPRESSION (cg_en_o.main_hmac == MuBi4True)
            ----------------1---------------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       313
 EXPRESSION (clkmgr.u_clk_main_kmac_trans.sw_hint_synced || ((!clkmgr.u_clk_main_kmac_trans.idle_valid)))
             ---------------------1---------------------    ----------------------2---------------------

-1-	-2-	Status	Tests
0	0	Not Covered
0	1	Not Covered
1	0	Not Covered

 LINE       313
 EXPRESSION (cg_en_o.main_kmac == MuBi4True)
            ----------------1---------------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       322
 EXPRESSION (clkmgr.u_clk_main_otbn_trans.sw_hint_synced || ((!clkmgr.u_clk_main_otbn_trans.idle_valid)))
             ---------------------1---------------------    ----------------------2---------------------

-1-	-2-	Status	Tests
0	0	Not Covered
0	1	Not Covered
1	0	Not Covered

 LINE       322
 EXPRESSION (cg_en_o.main_otbn == MuBi4True)
            ----------------1---------------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       704
 EXPRESSION (clk_io_div4_en ? MuBi4False : MuBi4True)
             -------1------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       715
 EXPRESSION (clk_main_en ? MuBi4False : MuBi4True)
             -----1-----

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       726
 EXPRESSION (clk_usb_en ? MuBi4False : MuBi4True)
             -----1----

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       737
 EXPRESSION (clk_io_en ? MuBi4False : MuBi4True)
             ----1----

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       748
 EXPRESSION (clk_io_div2_en ? MuBi4False : MuBi4True)
             -------1------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       759
 EXPRESSION (clk_io_div4_en ? MuBi4False : MuBi4True)
             -------1------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       770
 EXPRESSION (clk_main_en ? MuBi4False : MuBi4True)
             -----1-----

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       781
 EXPRESSION (clk_io_div4_en ? MuBi4False : MuBi4True)
             -------1------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       819
 EXPRESSION (clk_io_div4_peri_sw_en & clk_io_div4_en)
             -----------1----------   -------2------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

 LINE       832
 EXPRESSION (clk_io_div4_peri_combined_en ? MuBi4False : MuBi4True)
             --------------1-------------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       861
 EXPRESSION (clk_io_div2_peri_sw_en & clk_io_div2_en)
             -----------1----------   -------2------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

 LINE       874
 EXPRESSION (clk_io_div2_peri_combined_en ? MuBi4False : MuBi4True)
             --------------1-------------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       903
 EXPRESSION (clk_io_peri_sw_en & clk_io_en)
             --------1--------   ----2----

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

 LINE       916
 EXPRESSION (clk_io_peri_combined_en ? MuBi4False : MuBi4True)
             -----------1-----------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       945
 EXPRESSION (clk_usb_peri_sw_en & clk_usb_en)
             ---------1--------   -----2----

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

 LINE       958
 EXPRESSION (clk_usb_peri_combined_en ? MuBi4False : MuBi4True)
             ------------1-----------

-1-	Status	Tests
0	Not Covered
1	Not Covered

---

Toggle Coverage for Module : clkmgr

	Total	Covered	Percent
Totals	106	93	87.74
Total Bits	660	578	87.58
Total Bits 0->1	330	289	87.58
Total Bits 1->0	330	289	87.58

Ports	106	93	87.74
Port Bits	660	578	87.58
Port Bits 0->1	330	289	87.58
Port Bits 1->0	330	289	87.58

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T1,T4,T5	Yes	T1,T2,T3	INPUT
rst_shadowed_ni	Yes	Yes	T1,T4,T5	Yes	T1,T2,T3	INPUT
clk_main_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_main_ni	Yes	Yes	T1,T4,T5	Yes	T1,T2,T3	INPUT
clk_io_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_io_ni	Yes	Yes	T1,T4,T5	Yes	T1,T2,T3	INPUT
clk_usb_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_usb_ni	Yes	Yes	T1,T4,T5	Yes	T1,T2,T3	INPUT
clk_aon_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_aon_ni	Yes	Yes	T1,T4,T5	Yes	T1,T2,T3	INPUT
rst_io_div2_ni	Yes	Yes	T1,T4,T5	Yes	T1,T2,T3	INPUT
rst_io_div4_ni	Yes	Yes	T1,T4,T5	Yes	T1,T2,T3	INPUT
rst_root_ni	Yes	Yes	T1,T4,T5	Yes	T1,T2,T3	INPUT
rst_root_main_ni	Yes	Yes	T1,T4,T5	Yes	T1,T2,T3	INPUT
rst_root_io_ni	Yes	Yes	T1,T4,T5	Yes	T1,T2,T3	INPUT
rst_root_io_div2_ni	Yes	Yes	T1,T4,T5	Yes	T1,T2,T3	INPUT
rst_root_io_div4_ni	Yes	Yes	T1,T4,T5	Yes	T1,T2,T3	INPUT
rst_root_usb_ni	Yes	Yes	T1,T4,T5	Yes	T1,T2,T3	INPUT
tl_i.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T6	Yes	T1,T2,T6	INPUT
tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T6	Yes	T1,T2,T6	INPUT
tl_i.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T6	Yes	T1,T2,T6	INPUT
tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_data[31:0]	Yes	Yes	T1,T2,T6	Yes	T1,T2,T6	INPUT
tl_i.a_mask[3:0]	Yes	Yes	T1,T2,T6	Yes	T1,T2,T6	INPUT
tl_i.a_address[31:0]	Yes	Yes	T1,T2,T6	Yes	T1,T2,T6	INPUT
tl_i.a_source[7:0]	Yes	Yes	T1,T2,T6	Yes	T1,T2,T6	INPUT
tl_i.a_size[1:0]	Yes	Yes	T1,T2,T6	Yes	T1,T2,T6	INPUT
tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_opcode[2:0]	Yes	Yes	T1,T2,T6	Yes	T1,T2,T6	INPUT
tl_i.a_valid	Yes	Yes	T1,T2,T6	Yes	T1,T2,T6	INPUT
tl_o.a_ready	Yes	Yes	T1,T2,T6	Yes	T1,T2,T6	OUTPUT
tl_o.d_error	Yes	Yes	T1,T4,T7	Yes	T1,T4,T8	OUTPUT
tl_o.d_user.data_intg[6:0]	Yes	Yes	T1,T2,T6	Yes	T1,T2,T6	OUTPUT
tl_o.d_user.rsp_intg[5:0]	Yes	Yes	T1,*T2,*T6	Yes	T1,T2,T6	OUTPUT
tl_o.d_user.rsp_intg[6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_data[31:0]	Yes	Yes	T1,T2,T6	Yes	T1,T2,T6	OUTPUT
tl_o.d_sink	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_source[7:0]	Yes	Yes	T1,T2,T6	Yes	T1,T2,T6	OUTPUT
tl_o.d_size[1:0]	Yes	Yes	T1,T6,T9	Yes	T1,T6,T9	OUTPUT
tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_opcode[0]	Yes	Yes	*T1,*T2,*T6	Yes	T1,T2,T6	OUTPUT
tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_valid	Yes	Yes	T1,T2,T6	Yes	T1,T2,T6	OUTPUT
alert_rx_i[0].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T1,T2,T6	Yes	T1,T2,T6	INPUT
alert_rx_i[0].ping_n	Unreachable	Unreachable		Unreachable		INPUT
alert_rx_i[0].ping_p	Unreachable	Unreachable		Unreachable		INPUT
alert_rx_i[1].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[1].ack_p	Yes	Yes	T1,T2,T9	Yes	T1,T2,T9	INPUT
alert_rx_i[1].ping_n	Unreachable	Unreachable		Unreachable		INPUT
alert_rx_i[1].ping_p	Unreachable	Unreachable		Unreachable		INPUT
alert_tx_o[0].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T1,T2,T6	Yes	T1,T2,T6	OUTPUT
alert_tx_o[1].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[1].alert_p	Yes	Yes	T1,T2,T9	Yes	T1,T2,T9	OUTPUT
pwr_i.usb_ip_clk_en	No	No		No		INPUT
pwr_i.io_ip_clk_en	No	No		No		INPUT
pwr_i.main_ip_clk_en	No	No		No		INPUT
pwr_o.usb_status	Yes	Yes	T1,T4,T5	Yes	T1,T2,T3	OUTPUT
pwr_o.io_status	Yes	Yes	T1,T4,T5	Yes	T1,T2,T3	OUTPUT
pwr_o.main_status	Yes	Yes	T1,T4,T5	Yes	T1,T2,T3	OUTPUT
scanmode_i[3:0]	Yes	Yes	T4,T10,T11	Yes	T1,T2,T3	INPUT
lc_hw_debug_en_i[3:0]	No	No		No		INPUT
lc_clk_byp_req_i[3:0]	No	No		No		INPUT
lc_clk_byp_ack_o[3:0]	No	No		No		OUTPUT
io_clk_byp_req_o[3:0]	No	No		No		OUTPUT
io_clk_byp_ack_i[3:0]	No	No		No		INPUT
all_clk_byp_req_o[3:0]	No	No		No		OUTPUT
all_clk_byp_ack_i[3:0]	No	No		No		INPUT
hi_speed_sel_o[3:0]	Yes	Yes	T1,T4,T5	Yes	T1,T2,T3	OUTPUT
calib_rdy_i[3:0]	No	No		No		INPUT
jitter_en_o[0]	Yes	Yes	*T2,*T12,*T13	Yes	T13,T14,T15	OUTPUT
jitter_en_o[2:1]	No	No		No		OUTPUT
jitter_en_o[3]	Yes	Yes	T2,T12,T13	Yes	T13,T14,T15	OUTPUT
div_step_down_req_i[3:0]	No	No		No		INPUT
cg_en_o.usb_peri[3:0]	Yes	Yes	T1,T2,T6	Yes	T1,T2,T3	OUTPUT
cg_en_o.io_peri[3:0]	Yes	Yes	T1,T2,T6	Yes	T1,T2,T3	OUTPUT
cg_en_o.io_div2_peri[3:0]	Yes	Yes	T1,T2,T6	Yes	T1,T2,T3	OUTPUT
cg_en_o.io_div4_peri[3:0]	Yes	Yes	T1,T2,T6	Yes	T1,T2,T3	OUTPUT
cg_en_o.io_div4_timers[3:0]	Yes	Yes	T1,T4,T5	Yes	T1,T2,T3	OUTPUT
cg_en_o.main_secure[3:0]	Yes	Yes	T1,T4,T5	Yes	T1,T2,T3	OUTPUT
cg_en_o.io_div4_secure[3:0]	Yes	Yes	T1,T4,T5	Yes	T1,T2,T3	OUTPUT
cg_en_o.io_div2_infra[3:0]	Yes	Yes	T1,T4,T5	Yes	T1,T2,T3	OUTPUT
cg_en_o.io_infra[3:0]	Yes	Yes	T1,T4,T5	Yes	T1,T2,T3	OUTPUT
cg_en_o.usb_infra[3:0]	Yes	Yes	T1,T4,T5	Yes	T1,T2,T3	OUTPUT
cg_en_o.main_infra[3:0]	Yes	Yes	T1,T4,T5	Yes	T1,T2,T3	OUTPUT
cg_en_o.io_div4_infra[3:0]	Yes	Yes	T1,T4,T5	Yes	T1,T2,T3	OUTPUT
cg_en_o.main_otbn[3:0]	Yes	Yes	T1,T4,T5	Yes	T1,T2,T3	OUTPUT
cg_en_o.main_kmac[3:0]	Yes	Yes	T1,T4,T5	Yes	T1,T2,T3	OUTPUT
cg_en_o.main_hmac[3:0]	Yes	Yes	T1,T4,T5	Yes	T1,T2,T3	OUTPUT
cg_en_o.main_aes[3:0]	Yes	Yes	T1,T4,T5	Yes	T1,T2,T3	OUTPUT
cg_en_o.aon_timers[3:0]	Unreachable	Unreachable		Unreachable		OUTPUT
cg_en_o.aon_peri[3:0]	Unreachable	Unreachable		Unreachable		OUTPUT
cg_en_o.aon_secure[3:0]	Unreachable	Unreachable		Unreachable		OUTPUT
cg_en_o.io_div2_powerup[3:0]	Unreachable	Unreachable		Unreachable		OUTPUT
cg_en_o.usb_powerup[3:0]	Unreachable	Unreachable		Unreachable		OUTPUT
cg_en_o.io_powerup[3:0]	Unreachable	Unreachable		Unreachable		OUTPUT
cg_en_o.main_powerup[3:0]	Unreachable	Unreachable		Unreachable		OUTPUT
cg_en_o.aon_powerup[3:0]	Unreachable	Unreachable		Unreachable		OUTPUT
cg_en_o.io_div4_powerup[3:0]	Unreachable	Unreachable		Unreachable		OUTPUT
clocks_o.clk_usb_peri	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
clocks_o.clk_io_peri	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
clocks_o.clk_io_div2_peri	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
clocks_o.clk_io_div4_peri	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
clocks_o.clk_io_div4_timers	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
clocks_o.clk_main_secure	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
clocks_o.clk_io_div4_secure	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
clocks_o.clk_io_div2_infra	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
clocks_o.clk_io_infra	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
clocks_o.clk_usb_infra	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
clocks_o.clk_main_infra	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
clocks_o.clk_io_div4_infra	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
clocks_o.clk_main_otbn	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
clocks_o.clk_main_kmac	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
clocks_o.clk_main_hmac	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
clocks_o.clk_main_aes	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
clocks_o.clk_aon_timers	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
clocks_o.clk_aon_peri	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
clocks_o.clk_aon_secure	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
clocks_o.clk_io_div2_powerup	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
clocks_o.clk_usb_powerup	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
clocks_o.clk_io_powerup	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
clocks_o.clk_main_powerup	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
clocks_o.clk_aon_powerup	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
clocks_o.clk_io_div4_powerup	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT

*Tests covering at least one bit in the range

---

Branch Coverage for Module : clkmgr

	Line No.	Total	Covered	Percent
Branches		26	0	0.00
TERNARY	704	2	0	0.00
TERNARY	715	2	0	0.00
TERNARY	726	2	0	0.00
TERNARY	737	2	0	0.00
TERNARY	748	2	0	0.00
TERNARY	759	2	0	0.00
TERNARY	770	2	0	0.00
TERNARY	781	2	0	0.00
TERNARY	832	2	0	0.00
TERNARY	874	2	0	0.00
TERNARY	916	2	0	0.00
TERNARY	958	2	0	0.00
IF	555	2	0	0.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_opentitan_top_earlgrey_clkmgr_0.1/rtl/clkmgr.sv' or '../src/lowrisc_opentitan_top_earlgrey_clkmgr_0.1/rtl/clkmgr.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	704	(clk_io_div4_en) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered

	LineNo.	Expression
-1-:	715	(clk_main_en) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered

	LineNo.	Expression
-1-:	726	(clk_usb_en) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered

	LineNo.	Expression
-1-:	737	(clk_io_en) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered

	LineNo.	Expression
-1-:	748	(clk_io_div2_en) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered

	LineNo.	Expression
-1-:	759	(clk_io_div4_en) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered

	LineNo.	Expression
-1-:	770	(clk_main_en) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered

	LineNo.	Expression
-1-:	781	(clk_io_div4_en) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered

	LineNo.	Expression
-1-:	832	(clk_io_div4_peri_combined_en) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered

	LineNo.	Expression
-1-:	874	(clk_io_div2_peri_combined_en) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered

	LineNo.	Expression
-1-:	916	(clk_io_peri_combined_en) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered

	LineNo.	Expression
-1-:	958	(clk_usb_peri_combined_en) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered

	LineNo.	Expression
-1-:	555	if (prim_mubi_pkg::mubi4_test_false_strict(calib_rdy[BaseIdx]))

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered