Unified Coverage Report :: Module :: clkmgr_csr_assert_fpv

Module : clkmgr_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_clkmgr_csr_assert_0/clkmgr_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_csr_assert	100.00						100.00

---

Module Instance : tb.dut.clkmgr_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
21.89	0.00	0.00	87.58		0.00		dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : clkmgr_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	7	7	100.00	7	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	7	7	100.00	7	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	937428	11310	0	0
clk_enables_rd_A	937428	3668	0	0
clk_hints_rd_A	937428	3752	0	0
extclk_ctrl_rd_A	937428	551	0	0
extclk_ctrl_regwen_rd_A	937428	2202	0	0
jitter_enable_rd_A	937428	2033	0	0
jitter_regwen_rd_A	937428	2166	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	937428	11310	0	0
T1	12904	7	0	0
T2	2275	0	0	0
T3	994	0	0	0
T4	1663	24	0	0
T5	8150	0	0	0
T6	1488	0	0	0
T7	2106	96	0	0
T8	8499	674	0	0
T9	1566	0	0	0
T16	13169	0	0	0
T17	0	3	0	0
T18	0	36	0	0
T19	0	439	0	0
T20	0	2	0	0
T28	0	7	0	0
T29	0	3	0	0

clk_enables_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	937428	3668	0	0
T1	12904	65	0	0
T2	2275	0	0	0
T3	994	0	0	0
T4	1663	0	0	0
T5	8150	0	0	0
T6	1488	0	0	0
T7	2106	0	0	0
T8	8499	0	0	0
T9	1566	0	0	0
T16	13169	0	0	0
T20	0	158	0	0
T28	0	158	0	0
T29	0	22	0	0
T32	0	28	0	0
T34	0	225	0	0
T52	0	34	0	0
T71	0	11	0	0
T74	0	11	0	0
T75	0	404	0	0

clk_hints_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	937428	3752	0	0
T1	12904	105	0	0
T2	2275	0	0	0
T3	994	0	0	0
T4	1663	0	0	0
T5	8150	0	0	0
T6	1488	0	0	0
T7	2106	0	0	0
T8	8499	0	0	0
T9	1566	0	0	0
T16	13169	0	0	0
T20	0	185	0	0
T28	0	204	0	0
T29	0	69	0	0
T32	0	23	0	0
T34	0	216	0	0
T52	0	27	0	0
T71	0	9	0	0
T74	0	10	0	0
T75	0	472	0	0

extclk_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	937428	551	0	0
T10	0	7	0	0
T12	2525	0	0	0
T14	0	11	0	0
T18	1841	0	0	0
T23	0	14	0	0
T24	9474	0	0	0
T25	1867	0	0	0
T26	8465	0	0	0
T27	10246	0	0	0
T28	16590	6	0	0
T29	5834	0	0	0
T31	0	13	0	0
T32	6983	47	0	0
T34	0	8	0	0
T52	0	22	0	0
T58	840	0	0	0
T71	0	17	0	0
T76	0	2	0	0

extclk_ctrl_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	937428	2202	0	0
T1	12904	65	0	0
T2	2275	0	0	0
T3	994	0	0	0
T4	1663	0	0	0
T5	8150	0	0	0
T6	1488	0	0	0
T7	2106	0	0	0
T8	8499	0	0	0
T9	1566	0	0	0
T16	13169	0	0	0
T20	0	71	0	0
T28	0	92	0	0
T29	0	3	0	0
T32	0	26	0	0
T34	0	96	0	0
T52	0	36	0	0
T71	0	31	0	0
T74	0	4	0	0
T75	0	484	0	0

jitter_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	937428	2033	0	0
T1	12904	34	0	0
T2	2275	0	0	0
T3	994	0	0	0
T4	1663	0	0	0
T5	8150	0	0	0
T6	1488	0	0	0
T7	2106	0	0	0
T8	8499	0	0	0
T9	1566	0	0	0
T16	13169	0	0	0
T20	0	72	0	0
T28	0	87	0	0
T29	0	13	0	0
T32	0	20	0	0
T34	0	107	0	0
T52	0	20	0	0
T71	0	31	0	0
T74	0	9	0	0
T75	0	414	0	0

jitter_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	937428	2166	0	0
T1	12904	24	0	0
T2	2275	0	0	0
T3	994	0	0	0
T4	1663	0	0	0
T5	8150	0	0	0
T6	1488	0	0	0
T7	2106	0	0	0
T8	8499	0	0	0
T9	1566	0	0	0
T16	13169	0	0	0
T20	0	63	0	0
T28	0	70	0	0
T29	0	39	0	0
T32	0	31	0	0
T34	0	80	0	0
T52	0	24	0	0
T71	0	4	0	0
T74	0	5	0	0
T75	0	473	0	0