eb776817a5| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | smoke | flash_ctrl_smoke | 3.612m | 254.623us | 50 | 50 | 100.00 |
| V1 | smoke_hw | flash_ctrl_smoke_hw | 26.690s | 52.285us | 5 | 5 | 100.00 |
| V1 | csr_hw_reset | flash_ctrl_csr_hw_reset | 46.000s | 173.250us | 5 | 5 | 100.00 |
| V1 | csr_rw | flash_ctrl_csr_rw | 17.930s | 60.678us | 20 | 20 | 100.00 |
| V1 | csr_bit_bash | flash_ctrl_csr_bit_bash | 1.422m | 10.467ms | 5 | 5 | 100.00 |
| V1 | csr_aliasing | flash_ctrl_csr_aliasing | 1.098m | 1.657ms | 5 | 5 | 100.00 |
| V1 | csr_mem_rw_with_rand_reset | flash_ctrl_csr_mem_rw_with_rand_reset | 19.500s | 93.010us | 20 | 20 | 100.00 |
| V1 | regwen_csr_and_corresponding_lockable_csr | flash_ctrl_csr_rw | 17.930s | 60.678us | 20 | 20 | 100.00 |
| flash_ctrl_csr_aliasing | 1.098m | 1.657ms | 5 | 5 | 100.00 | ||
| V1 | mem_walk | flash_ctrl_mem_walk | 13.400s | 14.152us | 5 | 5 | 100.00 |
| V1 | mem_partial_access | flash_ctrl_mem_partial_access | 13.800s | 156.775us | 5 | 5 | 100.00 |
| V1 | TOTAL | 120 | 120 | 100.00 | |||
| V2 | sw_op | flash_ctrl_sw_op | 27.260s | 52.191us | 5 | 5 | 100.00 |
| V2 | host_read_direct | flash_ctrl_host_dir_rd | 1.649m | 101.038us | 5 | 5 | 100.00 |
| V2 | rma_hw_if | flash_ctrl_hw_rma | 40.049m | 168.116ms | 3 | 3 | 100.00 |
| flash_ctrl_hw_rma_reset | 23.598m | 540.423ms | 20 | 20 | 100.00 | ||
| flash_ctrl_lcmgr_intg | 13.870s | 48.078us | 20 | 20 | 100.00 | ||
| V2 | host_controller_arb | flash_ctrl_host_ctrl_arb | 35.839m | 332.826ms | 5 | 5 | 100.00 |
| V2 | erase_suspend | flash_ctrl_erase_suspend | 9.539m | 16.017ms | 5 | 5 | 100.00 |
| V2 | program_reset | flash_ctrl_prog_reset | 4.477m | 29.805ms | 30 | 30 | 100.00 |
| V2 | full_memory_access | flash_ctrl_full_mem_access | 1.073h | 48.915ms | 5 | 5 | 100.00 |
| V2 | rd_buff_eviction | flash_ctrl_rd_buff_evict | 2.492m | 735.041us | 5 | 5 | 100.00 |
| V2 | rd_buff_eviction_w_ecc | flash_ctrl_rw_evict | 32.970s | 116.918us | 28 | 40 | 70.00 |
| flash_ctrl_rw_evict_all_en | 33.160s | 41.575us | 34 | 40 | 85.00 | ||
| flash_ctrl_re_evict | 39.100s | 626.300us | 20 | 20 | 100.00 | ||
| V2 | host_arb | flash_ctrl_phy_arb | 9.967m | 2.056ms | 20 | 20 | 100.00 |
| V2 | host_interleave | flash_ctrl_phy_arb | 9.967m | 2.056ms | 20 | 20 | 100.00 |
| V2 | memory_protection | flash_ctrl_mp_regions | 18.731m | 62.748ms | 20 | 20 | 100.00 |
| V2 | fetch_code | flash_ctrl_fetch_code | 28.130s | 1.638ms | 10 | 10 | 100.00 |
| V2 | all_partitions | flash_ctrl_rand_ops | 25.943m | 1.986ms | 20 | 20 | 100.00 |
| V2 | error_mp | flash_ctrl_error_mp | 46.761m | 27.800ms | 10 | 10 | 100.00 |
| V2 | error_prog_win | flash_ctrl_error_prog_win | 18.022m | 851.322us | 10 | 10 | 100.00 |
| V2 | error_prog_type | flash_ctrl_error_prog_type | 54.405m | 1.473ms | 5 | 5 | 100.00 |
| V2 | error_read_seed | flash_ctrl_hw_read_seed_err | 14.050s | 15.193us | 20 | 20 | 100.00 |
| V2 | read_write_overflow | flash_ctrl_oversize_error | 3.801m | 5.537ms | 4 | 5 | 80.00 |
| V2 | flash_ctrl_disable | flash_ctrl_disable | 23.020s | 11.332us | 50 | 50 | 100.00 |
| V2 | flash_ctrl_connect | flash_ctrl_connect | 16.950s | 24.712us | 80 | 80 | 100.00 |
| V2 | stress_all | flash_ctrl_stress_all | 24.088m | 4.033ms | 5 | 5 | 100.00 |
| V2 | secret_partition | flash_ctrl_hw_sec_otp | 4.344m | 3.109ms | 50 | 50 | 100.00 |
| flash_ctrl_otp_reset | 2.274m | 142.127us | 80 | 80 | 100.00 | ||
| V2 | isolation_partition | flash_ctrl_hw_rma | 40.049m | 168.116ms | 3 | 3 | 100.00 |
| V2 | interrupts | flash_ctrl_intr_rd | 4.552m | 1.540ms | 38 | 40 | 95.00 |
| flash_ctrl_intr_wr | 1.455m | 10.614ms | 9 | 10 | 90.00 | ||
| flash_ctrl_intr_rd_slow_flash | 8.525m | 83.194ms | 40 | 40 | 100.00 | ||
| flash_ctrl_intr_wr_slow_flash | 5.109m | 495.958ms | 10 | 10 | 100.00 | ||
| V2 | invalid_op | flash_ctrl_invalid_op | 1.733m | 8.887ms | 20 | 20 | 100.00 |
| V2 | mid_op_rst | flash_ctrl_mid_op_rst | 1.244m | 2.675ms | 5 | 5 | 100.00 |
| V2 | double_bit_err | flash_ctrl_read_word_sweep_derr | 22.670s | 20.362us | 2 | 5 | 40.00 |
| flash_ctrl_ro_derr | 2.977m | 1.170ms | 10 | 10 | 100.00 | ||
| flash_ctrl_rw_derr | 14.145m | 5.204ms | 6 | 10 | 60.00 | ||
| flash_ctrl_derr_detect | 1.818m | 1.222ms | 5 | 5 | 100.00 | ||
| flash_ctrl_integrity | 12.332m | 13.802ms | 2 | 5 | 40.00 | ||
| V2 | single_bit_err | flash_ctrl_read_word_sweep_serr | 22.660s | 24.068us | 1 | 5 | 20.00 |
| flash_ctrl_ro_serr | 2.936m | 645.720us | 10 | 10 | 100.00 | ||
| flash_ctrl_rw_serr | 12.807m | 3.948ms | 8 | 10 | 80.00 | ||
| V2 | singlebit_err_counter | flash_ctrl_serr_counter | 1.286m | 853.622us | 5 | 5 | 100.00 |
| V2 | singlebit_err_address | flash_ctrl_serr_address | 2.128m | 1.254ms | 5 | 5 | 100.00 |
| V2 | scramble | flash_ctrl_wo | 4.274m | 5.916ms | 17 | 20 | 85.00 |
| flash_ctrl_write_word_sweep | 15.080s | 39.119us | 1 | 1 | 100.00 | ||
| flash_ctrl_read_word_sweep | 13.290s | 130.893us | 1 | 1 | 100.00 | ||
| flash_ctrl_ro | 2.588m | 2.312ms | 20 | 20 | 100.00 | ||
| flash_ctrl_rw | 13.486m | 33.022ms | 19 | 20 | 95.00 | ||
| V2 | filesystem_support | flash_ctrl_fs_sup | 43.800s | 5.349ms | 4 | 5 | 80.00 |
| V2 | rma_write_process_error | flash_ctrl_rma_err | 16.924m | 265.308ms | 3 | 3 | 100.00 |
| flash_ctrl_hw_prog_rma_wipe_err | 5.493m | 10.012ms | 20 | 20 | 100.00 | ||
| V2 | alert_test | flash_ctrl_alert_test | 14.760s | 148.054us | 50 | 50 | 100.00 |
| V2 | intr_test | flash_ctrl_intr_test | 14.190s | 136.533us | 50 | 50 | 100.00 |
| V2 | tl_d_oob_addr_access | flash_ctrl_tl_errors | 20.300s | 148.049us | 20 | 20 | 100.00 |
| V2 | tl_d_illegal_access | flash_ctrl_tl_errors | 20.300s | 148.049us | 20 | 20 | 100.00 |
| V2 | tl_d_outstanding_access | flash_ctrl_csr_hw_reset | 46.000s | 173.250us | 5 | 5 | 100.00 |
| flash_ctrl_csr_rw | 17.930s | 60.678us | 20 | 20 | 100.00 | ||
| flash_ctrl_csr_aliasing | 1.098m | 1.657ms | 5 | 5 | 100.00 | ||
| flash_ctrl_same_csr_outstanding | 36.110s | 170.257us | 20 | 20 | 100.00 | ||
| V2 | tl_d_partial_access | flash_ctrl_csr_hw_reset | 46.000s | 173.250us | 5 | 5 | 100.00 |
| flash_ctrl_csr_rw | 17.930s | 60.678us | 20 | 20 | 100.00 | ||
| flash_ctrl_csr_aliasing | 1.098m | 1.657ms | 5 | 5 | 100.00 | ||
| flash_ctrl_same_csr_outstanding | 36.110s | 170.257us | 20 | 20 | 100.00 | ||
| V2 | TOTAL | 970 | 1013 | 95.76 | |||
| V2S | shadow_reg_update_error | flash_ctrl_shadow_reg_errors | 15.870s | 47.283us | 20 | 20 | 100.00 |
| V2S | shadow_reg_read_clear_staged_value | flash_ctrl_shadow_reg_errors | 15.870s | 47.283us | 20 | 20 | 100.00 |
| V2S | shadow_reg_storage_error | flash_ctrl_shadow_reg_errors | 15.870s | 47.283us | 20 | 20 | 100.00 |
| V2S | shadowed_reset_glitch | flash_ctrl_shadow_reg_errors | 15.870s | 47.283us | 20 | 20 | 100.00 |
| V2S | shadow_reg_update_error_with_csr_rw | flash_ctrl_shadow_reg_errors_with_csr_rw | 15.940s | 24.610us | 20 | 20 | 100.00 |
| V2S | tl_intg_err | flash_ctrl_sec_cm | 1.382h | 1.542ms | 5 | 5 | 100.00 |
| flash_ctrl_tl_intg_err | 15.314m | 3.280ms | 20 | 20 | 100.00 | ||
| V2S | sec_cm_reg_bus_integrity | flash_ctrl_tl_intg_err | 15.314m | 3.280ms | 20 | 20 | 100.00 |
| V2S | sec_cm_host_bus_integrity | flash_ctrl_tl_intg_err | 15.314m | 3.280ms | 20 | 20 | 100.00 |
| V2S | sec_cm_mem_bus_integrity | flash_ctrl_rd_intg | 32.920s | 134.180us | 3 | 3 | 100.00 |
| flash_ctrl_wr_intg | 15.640s | 174.534us | 3 | 3 | 100.00 | ||
| V2S | sec_cm_scramble_key_sideload | flash_ctrl_smoke | 3.612m | 254.623us | 50 | 50 | 100.00 |
| V2S | sec_cm_lc_ctrl_intersig_mubi | flash_ctrl_otp_reset | 2.274m | 142.127us | 80 | 80 | 100.00 |
| flash_ctrl_disable | 23.020s | 11.332us | 50 | 50 | 100.00 | ||
| flash_ctrl_sec_info_access | 1.490m | 17.983ms | 50 | 50 | 100.00 | ||
| flash_ctrl_connect | 16.950s | 24.712us | 80 | 80 | 100.00 | ||
| V2S | sec_cm_ctrl_config_regwen | flash_ctrl_config_regwen | 13.970s | 33.393us | 4 | 5 | 80.00 |
| V2S | sec_cm_data_regions_config_regwen | flash_ctrl_csr_rw | 17.930s | 60.678us | 20 | 20 | 100.00 |
| V2S | sec_cm_data_regions_config_shadow | flash_ctrl_shadow_reg_errors | 15.870s | 47.283us | 20 | 20 | 100.00 |
| V2S | sec_cm_info_regions_config_regwen | flash_ctrl_csr_rw | 17.930s | 60.678us | 20 | 20 | 100.00 |
| V2S | sec_cm_info_regions_config_shadow | flash_ctrl_shadow_reg_errors | 15.870s | 47.283us | 20 | 20 | 100.00 |
| V2S | sec_cm_bank_config_regwen | flash_ctrl_csr_rw | 17.930s | 60.678us | 20 | 20 | 100.00 |
| V2S | sec_cm_bank_config_shadow | flash_ctrl_shadow_reg_errors | 15.870s | 47.283us | 20 | 20 | 100.00 |
| V2S | sec_cm_mem_ctrl_global_esc | flash_ctrl_disable | 23.020s | 11.332us | 50 | 50 | 100.00 |
| V2S | sec_cm_mem_ctrl_local_esc | flash_ctrl_rd_intg | 32.920s | 134.180us | 3 | 3 | 100.00 |
| flash_ctrl_access_after_disable | 13.690s | 29.722us | 3 | 3 | 100.00 | ||
| V2S | sec_cm_mem_disable_config_mubi | flash_ctrl_disable | 23.020s | 11.332us | 50 | 50 | 100.00 |
| V2S | sec_cm_exec_config_redun | flash_ctrl_fetch_code | 28.130s | 1.638ms | 10 | 10 | 100.00 |
| V2S | sec_cm_mem_scramble | flash_ctrl_rw | 13.486m | 33.022ms | 19 | 20 | 95.00 |
| V2S | sec_cm_mem_integrity | flash_ctrl_rw_serr | 12.807m | 3.948ms | 8 | 10 | 80.00 |
| flash_ctrl_rw_derr | 14.145m | 5.204ms | 6 | 10 | 60.00 | ||
| flash_ctrl_integrity | 12.332m | 13.802ms | 2 | 5 | 40.00 | ||
| V2S | sec_cm_rma_entry_mem_sec_wipe | flash_ctrl_hw_rma | 40.049m | 168.116ms | 3 | 3 | 100.00 |
| V2S | sec_cm_ctrl_fsm_sparse | flash_ctrl_sec_cm | 1.382h | 1.542ms | 5 | 5 | 100.00 |
| V2S | sec_cm_phy_fsm_sparse | flash_ctrl_sec_cm | 1.382h | 1.542ms | 5 | 5 | 100.00 |
| V2S | sec_cm_phy_prog_fsm_sparse | flash_ctrl_sec_cm | 1.382h | 1.542ms | 5 | 5 | 100.00 |
| V2S | sec_cm_ctr_redun | flash_ctrl_sec_cm | 1.382h | 1.542ms | 5 | 5 | 100.00 |
| V2S | sec_cm_phy_arbiter_ctrl_redun | flash_ctrl_phy_arb_redun | 24.030s | 835.142us | 5 | 5 | 100.00 |
| V2S | sec_cm_phy_host_grant_ctrl_consistency | flash_ctrl_phy_host_grant_err | 14.270s | 14.396us | 5 | 5 | 100.00 |
| V2S | sec_cm_phy_ack_ctrl_consistency | flash_ctrl_phy_ack_consistency | 14.440s | 15.576us | 5 | 5 | 100.00 |
| V2S | sec_cm_fifo_ctr_redun | flash_ctrl_sec_cm | 1.382h | 1.542ms | 5 | 5 | 100.00 |
| V2S | sec_cm_mem_tl_lc_gate_fsm_sparse | flash_ctrl_sec_cm | 1.382h | 1.542ms | 5 | 5 | 100.00 |
| V2S | sec_cm_prog_tl_lc_gate_fsm_sparse | flash_ctrl_sec_cm | 1.382h | 1.542ms | 5 | 5 | 100.00 |
| V2S | TOTAL | 143 | 144 | 99.31 | |||
| V3 | asymmetric_read_path | flash_ctrl_rd_ooo | 45.320s | 71.549us | 1 | 1 | 100.00 |
| V3 | stress_all_with_rand_reset | flash_ctrl_stress_all_with_rand_reset | 0 | 0 | -- | ||
| V3 | TOTAL | 1 | 1 | 100.00 | |||
| TOTAL | 1234 | 1278 | 96.56 |
| Items | Total | Written | Passing | Progress |
|---|---|---|---|---|
| V1 | 9 | 9 | 9 | 100.00 |
| V2 | 55 | 55 | 42 | 76.36 |
| V2S | 12 | 12 | 11 | 91.67 |
| V3 | 2 | 1 | 1 | 50.00 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
|---|---|---|---|---|---|---|---|
| 96.48 | 95.75 | 94.26 | 98.85 | 92.52 | 98.07 | 98.00 | 97.90 |
UVM_FATAL (flash_ctrl_base_vseq.sv:81) [flash_ctrl_rw_evict_vseq] Check failed (!address_was_written(addr)) Overwriting address * has 16 failures:
0.flash_ctrl_rw_evict.108803125470127899531666172924714606177651688397609765285163017585518766491374
Line 294, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/0.flash_ctrl_rw_evict/latest/run.log
UVM_FATAL @ 63082.8 ns: (flash_ctrl_base_vseq.sv:81) [uvm_test_top.env.virtual_sequencer.flash_ctrl_rw_evict_vseq] Check failed (!address_was_written(addr)) Overwriting address 0x00004d38
UVM_INFO @ 63082.8 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
5.flash_ctrl_rw_evict.102868010725662182551157607269273852339320866627921242679221092946851008934158
Line 297, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/5.flash_ctrl_rw_evict/latest/run.log
UVM_FATAL @ 11758.6 ns: (flash_ctrl_base_vseq.sv:81) [uvm_test_top.env.virtual_sequencer.flash_ctrl_rw_evict_vseq] Check failed (!address_was_written(addr)) Overwriting address 0x00003bc8
UVM_INFO @ 11758.6 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 9 more failures.
16.flash_ctrl_rw_evict_all_en.57127798989507939171289864286397875388630933089235815473962678424186728504741
Line 293, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/16.flash_ctrl_rw_evict_all_en/latest/run.log
UVM_FATAL @ 14009.8 ns: (flash_ctrl_base_vseq.sv:81) [uvm_test_top.env.virtual_sequencer.flash_ctrl_rw_evict_vseq] Check failed (!address_was_written(addr)) Overwriting address 0x000302d0
UVM_INFO @ 14009.8 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
18.flash_ctrl_rw_evict_all_en.20005888130821977404297312580422941884852145243138855967335442931146580409180
Line 295, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/18.flash_ctrl_rw_evict_all_en/latest/run.log
UVM_FATAL @ 34706.8 ns: (flash_ctrl_base_vseq.sv:81) [uvm_test_top.env.virtual_sequencer.flash_ctrl_rw_evict_vseq] Check failed (!address_was_written(addr)) Overwriting address 0x0000d200
UVM_INFO @ 34706.8 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 3 more failures.
UVM_ERROR (flash_ctrl_otf_scoreboard.sv:547) [lm_wdata_comp_bank0] Check failed rcv.mem_wdata == exp.req.prog_full_data (* [*] vs * [*]) has 6 failures:
Test flash_ctrl_integrity has 2 failures.
0.flash_ctrl_integrity.71973324903268395901797248871057535236010057705990482855222207563356932819285
Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/0.flash_ctrl_integrity/latest/run.log
UVM_ERROR @ 1781749.2 ns: (flash_ctrl_otf_scoreboard.sv:547) [lm_wdata_comp_bank0] Check failed rcv.mem_wdata == exp.req.prog_full_data (37821680329774703065601 [0x8025141101458203a01] vs 24211369258054463491 [0x15000101018263003])
UVM_INFO @ 1781749.2 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
1.flash_ctrl_integrity.80715135845661440369015671971988705571820308962305151820170828146800443261355
Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/1.flash_ctrl_integrity/latest/run.log
UVM_ERROR @ 10111780.2 ns: (flash_ctrl_otf_scoreboard.sv:547) [lm_wdata_comp_bank0] Check failed rcv.mem_wdata == exp.req.prog_full_data (1772355624502803472476 [0x60146012248b36a05c] vs 21850519992901657919552 [0x4a084e144870a338040])
UVM_INFO @ 10111780.2 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test flash_ctrl_rw_serr has 1 failures.
2.flash_ctrl_rw_serr.45037375608200284190298227628361366907546401783557571797140297878832123390436
Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/2.flash_ctrl_rw_serr/latest/run.log
UVM_ERROR @ 1229712.1 ns: (flash_ctrl_otf_scoreboard.sv:547) [lm_wdata_comp_bank0] Check failed rcv.mem_wdata == exp.req.prog_full_data (666479843498537273345 [0x2421440e8018404801] vs 814053796088213686273 [0x2c21440e8018404801])
UVM_INFO @ 1229712.1 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test flash_ctrl_rw_derr has 3 failures.
4.flash_ctrl_rw_derr.72776978108951927188887107859971808742317489119225194025664874972058302294587
Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/4.flash_ctrl_rw_derr/latest/run.log
UVM_ERROR @ 3382182.4 ns: (flash_ctrl_otf_scoreboard.sv:547) [lm_wdata_comp_bank0] Check failed rcv.mem_wdata == exp.req.prog_full_data (22098782844290323448352 [0x4adfa38188335340220] vs 19737599602855500841504 [0x42dfa38188335340220])
UVM_INFO @ 3382182.4 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
6.flash_ctrl_rw_derr.76211910419662089457482404474785853688634199570578029432009458726084116162151
Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/6.flash_ctrl_rw_derr/latest/run.log
UVM_ERROR @ 9765218.9 ns: (flash_ctrl_otf_scoreboard.sv:547) [lm_wdata_comp_bank0] Check failed rcv.mem_wdata == exp.req.prog_full_data (29007805178886737631794 [0x624842a404240801a32] vs 10118339247408156777010 [0x224842a404240801a32])
UVM_INFO @ 9765218.9 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 1 more failures.
Job flash_ctrl-sim-vcs_run_default killed due to: Exit reason: Job failed: the job consumes more ram than allocated, try to request more ram for the job. has 6 failures:
Test flash_ctrl_wo has 3 failures.
2.flash_ctrl_wo.41801135197188299085351174894190939185490824992389694383131641216187789092245
Log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/2.flash_ctrl_wo/latest/run.log
Job ID: smart:df7d5eb5-30a9-42f8-bbbe-ec2cb7137388
13.flash_ctrl_wo.31993873350766932082143320742463590443110373194326924726259750092483467967688
Log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/13.flash_ctrl_wo/latest/run.log
Job ID: smart:b8b4c63b-d016-4aed-bfdf-8f84cf65236b
... and 1 more failures.
Test flash_ctrl_oversize_error has 1 failures.
4.flash_ctrl_oversize_error.6805326053924384286231959287247132834234689450892341910907124484050074617331
Log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/4.flash_ctrl_oversize_error/latest/run.log
Job ID: smart:57f0ee81-0ce2-46d6-9aed-65f3ce6b00b9
Test flash_ctrl_intr_wr has 1 failures.
5.flash_ctrl_intr_wr.27236083968527744101541072825475685582329308323668844067193501027138971521994
Log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/5.flash_ctrl_intr_wr/latest/run.log
Job ID: smart:16ae6217-b03d-41a0-9018-46b299bbb607
Test flash_ctrl_rw has 1 failures.
12.flash_ctrl_rw.18467213948124493288743810112702189988882931840335062912352097326958265751744
Log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/12.flash_ctrl_rw/latest/run.log
Job ID: smart:150e1194-ff82-49d8-88f7-93c7c43872f4
UVM_ERROR (flash_ctrl_otf_scoreboard.sv:289) m_otf_scb [process_read] unexpected double bit error * has 4 failures:
0.flash_ctrl_read_word_sweep_derr.108035469183206673578346857949535836642728866413173248682914002355532685228351
Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/0.flash_ctrl_read_word_sweep_derr/latest/run.log
UVM_ERROR @ 5507.6 ns: (flash_ctrl_otf_scoreboard.sv:289) uvm_test_top.env.m_otf_scb [process_read] unexpected double bit error 0x000001c8
UVM_INFO @ 5507.6 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
1.flash_ctrl_read_word_sweep_derr.97010166585886683636287917987916142315614391335107191685050828558078841990488
Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/1.flash_ctrl_read_word_sweep_derr/latest/run.log
UVM_ERROR @ 21184.0 ns: (flash_ctrl_otf_scoreboard.sv:289) uvm_test_top.env.m_otf_scb [process_read] unexpected double bit error 0x00017dd0
UVM_INFO @ 21184.0 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 1 more failures.
3.flash_ctrl_integrity.111972624795140185939676914622835653606302300488887354864146344890957434065718
Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/3.flash_ctrl_integrity/latest/run.log
UVM_ERROR @ 2363624.0 ns: (flash_ctrl_otf_scoreboard.sv:289) uvm_test_top.env.m_otf_scb [process_read] unexpected double bit error 0x00003000
UVM_INFO @ 2363624.0 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_scoreboard.sv:241) [scoreboard] Check failed expected_alert[alert_name].expected == * (* [*] vs * [*]) alert fatal_err triggered unexpectedly has 3 failures:
Test flash_ctrl_read_word_sweep_serr has 2 failures.
1.flash_ctrl_read_word_sweep_serr.53146262444163919297102795962905702890756250894580464360906861152901913826137
Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/1.flash_ctrl_read_word_sweep_serr/latest/run.log
UVM_ERROR @ 5074.1 ns: (cip_base_scoreboard.sv:241) [uvm_test_top.env.scoreboard] Check failed expected_alert[alert_name].expected == 1 (0 [0x0] vs 1 [0x1]) alert fatal_err triggered unexpectedly
UVM_INFO @ 5074.1 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
4.flash_ctrl_read_word_sweep_serr.45419612979781228305249422212646093944150622851318446977791238152396188257422
Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/4.flash_ctrl_read_word_sweep_serr/latest/run.log
UVM_ERROR @ 91568.6 ns: (cip_base_scoreboard.sv:241) [uvm_test_top.env.scoreboard] Check failed expected_alert[alert_name].expected == 1 (0 [0x0] vs 1 [0x1]) alert fatal_err triggered unexpectedly
UVM_INFO @ 91568.6 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test flash_ctrl_fs_sup has 1 failures.
4.flash_ctrl_fs_sup.103505349971751206107245613459318963160190917460825717917193132513390581913730
Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/4.flash_ctrl_fs_sup/latest/run.log
UVM_ERROR @ 291874.6 ns: (cip_base_scoreboard.sv:241) [uvm_test_top.env.scoreboard] Check failed expected_alert[alert_name].expected == 1 (0 [0x0] vs 1 [0x1]) alert fatal_err triggered unexpectedly
UVM_INFO @ 291874.6 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (flash_ctrl_otf_scoreboard.sv:547) [lm_wdata_comp_bank1] Check failed rcv.mem_wdata == exp.req.prog_full_data (* [*] vs * [*]) has 2 failures:
Test flash_ctrl_rw_derr has 1 failures.
1.flash_ctrl_rw_derr.99133192617047609937800703698363171979421937044186307948423158568233257875678
Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/1.flash_ctrl_rw_derr/latest/run.log
UVM_ERROR @ 4186007.3 ns: (flash_ctrl_otf_scoreboard.sv:547) [lm_wdata_comp_bank1] Check failed rcv.mem_wdata == exp.req.prog_full_data (4804391451465170952 [0x42aca09202814008] vs 192705433037783048 [0x2aca09202814008])
UVM_INFO @ 4186007.3 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test flash_ctrl_rw_serr has 1 failures.
8.flash_ctrl_rw_serr.99738291677663209099430112845877129981974663892329729599125714676356231796726
Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/8.flash_ctrl_rw_serr/latest/run.log
UVM_ERROR @ 12439216.8 ns: (flash_ctrl_otf_scoreboard.sv:547) [lm_wdata_comp_bank1] Check failed rcv.mem_wdata == exp.req.prog_full_data (29750022606295775969356 [0x64cc080420d0482004c] vs 29750022606295775971404 [0x64cc080420d0482084c])
UVM_INFO @ 12439216.8 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_scoreboard.sv:241) [scoreboard] Check failed expected_alert[alert_name].expected == * (* [*] vs * [*]) alert recov_err triggered unexpectedly has 2 failures:
2.flash_ctrl_read_word_sweep_serr.115656483694986430184326706413584382157870178596327430158587248851078600718053
Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/2.flash_ctrl_read_word_sweep_serr/latest/run.log
UVM_ERROR @ 19147.3 ns: (cip_base_scoreboard.sv:241) [uvm_test_top.env.scoreboard] Check failed expected_alert[alert_name].expected == 1 (0 [0x0] vs 1 [0x1]) alert recov_err triggered unexpectedly
UVM_INFO @ 19147.3 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
3.flash_ctrl_read_word_sweep_serr.98440557544631798875592031077046990687983067286755338104709025767457962695158
Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/3.flash_ctrl_read_word_sweep_serr/latest/run.log
UVM_ERROR @ 4832.3 ns: (cip_base_scoreboard.sv:241) [uvm_test_top.env.scoreboard] Check failed expected_alert[alert_name].expected == 1 (0 [0x0] vs 1 [0x1]) alert recov_err triggered unexpectedly
UVM_INFO @ 4832.3 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: flash_ctrl_core_reg_block.op_status.err reset value: * has 2 failures:
Test flash_ctrl_rw_evict has 1 failures.
4.flash_ctrl_rw_evict.5539693599834083154656095346719578575134389633390762325138733235820587161083
Line 289, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/4.flash_ctrl_rw_evict/latest/run.log
UVM_ERROR @ 46877.8 ns: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: flash_ctrl_core_reg_block.op_status.err reset value: 0x0
UVM_INFO @ 46877.8 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test flash_ctrl_rw_evict_all_en has 1 failures.
12.flash_ctrl_rw_evict_all_en.58001590564092077530103327129608627896851777732054218390994490662215813222458
Line 294, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/12.flash_ctrl_rw_evict_all_en/latest/run.log
UVM_ERROR @ 13822.4 ns: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: flash_ctrl_core_reg_block.op_status.err reset value: 0x0
UVM_INFO @ 13822.4 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (flash_ctrl_otf_scoreboard.sv:375) [rdata_comp_bank1] *: obs:exp *bc0e3b_ae3bbb4f:ffffffff_ae3bbb4f mismatch!! has 1 failures:
0.flash_ctrl_intr_rd.53239109960693381494465304206438798355018539610027350731956213184454142171211
Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/0.flash_ctrl_intr_rd/latest/run.log
UVM_ERROR @ 7146347.5 ns: (flash_ctrl_otf_scoreboard.sv:375) [rdata_comp_bank1] 3: obs:exp 64bc0e3b_ae3bbb4f:ffffffff_ae3bbb4f mismatch!!
UVM_INFO @ 7146347.5 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Error-[CNST-CIF] Constraints inconsistency failure has 1 failures:
1.flash_ctrl_config_regwen.28713282712866706682779892842598693878147215401998102839725686182305880644974
Line 328, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/1.flash_ctrl_config_regwen/latest/run.log
Error-[CNST-CIF] Constraints inconsistency failure
../src/lowrisc_dv_flash_ctrl_env_0.1/seq_lib/flash_ctrl_config_regwen_vseq.sv, 46
Constraints are inconsistent and cannot be solved.
Please check the inconsistent constraints being printed above and rewrite
them.
UVM_ERROR (flash_ctrl_otf_scoreboard.sv:375) [rdata_comp_bank1] *: obs:exp f0d180f5_0e1345f9:ffffffff_0e1345f* mismatch!! has 1 failures:
38.flash_ctrl_intr_rd.88585169180956193994322392227823945885118211714807610797903985373159185870616
Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/38.flash_ctrl_intr_rd/latest/run.log
UVM_ERROR @ 1611767.3 ns: (flash_ctrl_otf_scoreboard.sv:375) [rdata_comp_bank1] 6: obs:exp f0d180f5_0e1345f9:ffffffff_0e1345f9 mismatch!!
UVM_INFO @ 1611767.3 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---