FLASH_CTRL Simulation Results

Tuesday August 06 2024 23:02:29 UTC

GitHub Revision: 5fd4ecc0fc

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 56304622830272859824235340993951659280265419461975949533183046575604373639200

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	flash_ctrl_smoke	3.667m	58.020us	50	50	100.00
V1	smoke_hw	flash_ctrl_smoke_hw	26.990s	100.193us	5	5	100.00
V1	csr_hw_reset	flash_ctrl_csr_hw_reset	46.380s	192.427us	5	5	100.00
V1	csr_rw	flash_ctrl_csr_rw	17.900s	207.133us	20	20	100.00
V1	csr_bit_bash	flash_ctrl_csr_bit_bash	1.004m	2.526ms	5	5	100.00
V1	csr_aliasing	flash_ctrl_csr_aliasing	52.930s	1.101ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	flash_ctrl_csr_mem_rw_with_rand_reset	20.190s	42.840us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	flash_ctrl_csr_rw	17.900s	207.133us	20	20	100.00
		flash_ctrl_csr_aliasing	52.930s	1.101ms	5	5	100.00
V1	mem_walk	flash_ctrl_mem_walk	13.610s	40.694us	5	5	100.00
V1	mem_partial_access	flash_ctrl_mem_partial_access	13.910s	27.413us	5	5	100.00
V1		TOTAL			120	120	100.00
V2	sw_op	flash_ctrl_sw_op	26.720s	26.933us	5	5	100.00
V2	host_read_direct	flash_ctrl_host_dir_rd	1.508m	93.370us	5	5	100.00
V2	rma_hw_if	flash_ctrl_hw_rma	34.130m	334.810ms	3	3	100.00
		flash_ctrl_hw_rma_reset	17.800m	630.446ms	20	20	100.00
		flash_ctrl_lcmgr_intg	13.800s	70.381us	19	20	95.00
V2	host_controller_arb	flash_ctrl_host_ctrl_arb	43.213m	576.968ms	5	5	100.00
V2	erase_suspend	flash_ctrl_erase_suspend	8.712m	27.940ms	5	5	100.00
V2	program_reset	flash_ctrl_prog_reset	3.588m	5.216ms	30	30	100.00
V2	full_memory_access	flash_ctrl_full_mem_access	1.177h	325.739ms	5	5	100.00
V2	rd_buff_eviction	flash_ctrl_rd_buff_evict	1.997m	1.284ms	5	5	100.00
V2	rd_buff_eviction_w_ecc	flash_ctrl_rw_evict	32.360s	61.512us	39	40	97.50
		flash_ctrl_rw_evict_all_en	32.440s	290.657us	40	40	100.00
		flash_ctrl_re_evict	36.460s	275.474us	20	20	100.00
V2	host_arb	flash_ctrl_phy_arb	8.590m	4.211ms	20	20	100.00
V2	host_interleave	flash_ctrl_phy_arb	8.590m	4.211ms	20	20	100.00
V2	memory_protection	flash_ctrl_mp_regions	18.261m	27.310ms	20	20	100.00
V2	fetch_code	flash_ctrl_fetch_code	29.490s	2.008ms	10	10	100.00
V2	all_partitions	flash_ctrl_rand_ops	23.989m	843.212us	20	20	100.00
V2	error_mp	flash_ctrl_error_mp	45.048m	44.902ms	10	10	100.00
V2	error_prog_win	flash_ctrl_error_prog_win	16.728m	4.192ms	10	10	100.00
V2	error_prog_type	flash_ctrl_error_prog_type	47.070m	1.987ms	5	5	100.00
V2	error_read_seed	flash_ctrl_hw_read_seed_err	13.780s	121.605us	20	20	100.00
V2	read_write_overflow	flash_ctrl_oversize_error	4.294m	8.198ms	5	5	100.00
V2	flash_ctrl_disable	flash_ctrl_disable	22.680s	29.352us	50	50	100.00
V2	flash_ctrl_connect	flash_ctrl_connect	16.630s	14.169us	80	80	100.00
V2	stress_all	flash_ctrl_stress_all	22.175m	1.238ms	5	5	100.00
V2	secret_partition	flash_ctrl_hw_sec_otp	4.119m	10.964ms	50	50	100.00
		flash_ctrl_otp_reset	2.261m	68.444us	80	80	100.00
V2	isolation_partition	flash_ctrl_hw_rma	34.130m	334.810ms	3	3	100.00
V2	interrupts	flash_ctrl_intr_rd	4.009m	8.081ms	39	40	97.50
		flash_ctrl_intr_wr	1.422m	5.282ms	10	10	100.00
		flash_ctrl_intr_rd_slow_flash	7.960m	12.803ms	40	40	100.00
		flash_ctrl_intr_wr_slow_flash	3.544m	71.520ms	10	10	100.00
V2	invalid_op	flash_ctrl_invalid_op	1.583m	4.422ms	20	20	100.00
V2	mid_op_rst	flash_ctrl_mid_op_rst	1.255m	3.385ms	5	5	100.00
V2	double_bit_err	flash_ctrl_read_word_sweep_derr	23.370s	18.885us	5	5	100.00
		flash_ctrl_ro_derr	2.746m	2.611ms	10	10	100.00
		flash_ctrl_rw_derr	4.674m	4.397ms	10	10	100.00
		flash_ctrl_derr_detect	3.646m	5.381ms	5	5	100.00
		flash_ctrl_integrity	11.734m	4.793ms	5	5	100.00
V2	single_bit_err	flash_ctrl_read_word_sweep_serr	22.990s	77.191us	5	5	100.00
		flash_ctrl_ro_serr	2.364m	1.330ms	10	10	100.00
		flash_ctrl_rw_serr	4.101m	3.874ms	10	10	100.00
V2	singlebit_err_counter	flash_ctrl_serr_counter	1.227m	1.751ms	5	5	100.00
V2	singlebit_err_address	flash_ctrl_serr_address	1.444m	1.632ms	5	5	100.00
V2	scramble	flash_ctrl_wo	3.881m	35.292ms	20	20	100.00
		flash_ctrl_write_word_sweep	15.040s	145.896us	1	1	100.00
		flash_ctrl_read_word_sweep	14.160s	172.495us	1	1	100.00
		flash_ctrl_ro	2.181m	2.434ms	20	20	100.00
		flash_ctrl_rw	11.132m	21.972ms	20	20	100.00
V2	filesystem_support	flash_ctrl_fs_sup	44.160s	5.863ms	4	5	80.00
V2	rma_write_process_error	flash_ctrl_rma_err	17.436m	197.316ms	3	3	100.00
		flash_ctrl_hw_prog_rma_wipe_err	5.543m	10.012ms	20	20	100.00
V2	alert_test	flash_ctrl_alert_test	14.970s	248.855us	50	50	100.00
V2	intr_test	flash_ctrl_intr_test	13.960s	58.332us	50	50	100.00
V2	tl_d_oob_addr_access	flash_ctrl_tl_errors	21.000s	447.875us	20	20	100.00
V2	tl_d_illegal_access	flash_ctrl_tl_errors	21.000s	447.875us	20	20	100.00
V2	tl_d_outstanding_access	flash_ctrl_csr_hw_reset	46.380s	192.427us	5	5	100.00
		flash_ctrl_csr_rw	17.900s	207.133us	20	20	100.00
		flash_ctrl_csr_aliasing	52.930s	1.101ms	5	5	100.00
		flash_ctrl_same_csr_outstanding	35.600s	197.688us	20	20	100.00
V2	tl_d_partial_access	flash_ctrl_csr_hw_reset	46.380s	192.427us	5	5	100.00
		flash_ctrl_csr_rw	17.900s	207.133us	20	20	100.00
		flash_ctrl_csr_aliasing	52.930s	1.101ms	5	5	100.00
		flash_ctrl_same_csr_outstanding	35.600s	197.688us	20	20	100.00
V2		TOTAL			1009	1013	99.61
V2S	shadow_reg_update_error	flash_ctrl_shadow_reg_errors	16.580s	43.080us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	flash_ctrl_shadow_reg_errors	16.580s	43.080us	20	20	100.00
V2S	shadow_reg_storage_error	flash_ctrl_shadow_reg_errors	16.580s	43.080us	20	20	100.00
V2S	shadowed_reset_glitch	flash_ctrl_shadow_reg_errors	16.580s	43.080us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	flash_ctrl_shadow_reg_errors_with_csr_rw	16.790s	12.216us	20	20	100.00
V2S	tl_intg_err	flash_ctrl_sec_cm	1.390h	4.322ms	5	5	100.00
		flash_ctrl_tl_intg_err	15.364m	1.598ms	20	20	100.00
V2S	sec_cm_reg_bus_integrity	flash_ctrl_tl_intg_err	15.364m	1.598ms	20	20	100.00
V2S	sec_cm_host_bus_integrity	flash_ctrl_tl_intg_err	15.364m	1.598ms	20	20	100.00
V2S	sec_cm_mem_bus_integrity	flash_ctrl_rd_intg	31.660s	132.406us	3	3	100.00
		flash_ctrl_wr_intg	15.510s	482.677us	3	3	100.00
V2S	sec_cm_scramble_key_sideload	flash_ctrl_smoke	3.667m	58.020us	50	50	100.00
V2S	sec_cm_lc_ctrl_intersig_mubi	flash_ctrl_otp_reset	2.261m	68.444us	80	80	100.00
		flash_ctrl_disable	22.680s	29.352us	50	50	100.00
		flash_ctrl_sec_info_access	1.506m	10.580ms	50	50	100.00
		flash_ctrl_connect	16.630s	14.169us	80	80	100.00
V2S	sec_cm_ctrl_config_regwen	flash_ctrl_config_regwen	14.010s	22.251us	5	5	100.00
V2S	sec_cm_data_regions_config_regwen	flash_ctrl_csr_rw	17.900s	207.133us	20	20	100.00
V2S	sec_cm_data_regions_config_shadow	flash_ctrl_shadow_reg_errors	16.580s	43.080us	20	20	100.00
V2S	sec_cm_info_regions_config_regwen	flash_ctrl_csr_rw	17.900s	207.133us	20	20	100.00
V2S	sec_cm_info_regions_config_shadow	flash_ctrl_shadow_reg_errors	16.580s	43.080us	20	20	100.00
V2S	sec_cm_bank_config_regwen	flash_ctrl_csr_rw	17.900s	207.133us	20	20	100.00
V2S	sec_cm_bank_config_shadow	flash_ctrl_shadow_reg_errors	16.580s	43.080us	20	20	100.00
V2S	sec_cm_mem_ctrl_global_esc	flash_ctrl_disable	22.680s	29.352us	50	50	100.00
V2S	sec_cm_mem_ctrl_local_esc	flash_ctrl_rd_intg	31.660s	132.406us	3	3	100.00
		flash_ctrl_access_after_disable	13.870s	23.334us	3	3	100.00
V2S	sec_cm_mem_addr_infection	flash_ctrl_host_addr_infection	31.050s	94.106us	3	3	100.00
V2S	sec_cm_mem_disable_config_mubi	flash_ctrl_disable	22.680s	29.352us	50	50	100.00
V2S	sec_cm_exec_config_redun	flash_ctrl_fetch_code	29.490s	2.008ms	10	10	100.00
V2S	sec_cm_mem_scramble	flash_ctrl_rw	11.132m	21.972ms	20	20	100.00
V2S	sec_cm_mem_integrity	flash_ctrl_rw_serr	4.101m	3.874ms	10	10	100.00
		flash_ctrl_rw_derr	4.674m	4.397ms	10	10	100.00
		flash_ctrl_integrity	11.734m	4.793ms	5	5	100.00
V2S	sec_cm_rma_entry_mem_sec_wipe	flash_ctrl_hw_rma	34.130m	334.810ms	3	3	100.00
V2S	sec_cm_ctrl_fsm_sparse	flash_ctrl_sec_cm	1.390h	4.322ms	5	5	100.00
V2S	sec_cm_phy_fsm_sparse	flash_ctrl_sec_cm	1.390h	4.322ms	5	5	100.00
V2S	sec_cm_phy_prog_fsm_sparse	flash_ctrl_sec_cm	1.390h	4.322ms	5	5	100.00
V2S	sec_cm_ctr_redun	flash_ctrl_sec_cm	1.390h	4.322ms	5	5	100.00
V2S	sec_cm_phy_arbiter_ctrl_redun	flash_ctrl_phy_arb_redun	20.870s	868.268us	5	5	100.00
V2S	sec_cm_phy_host_grant_ctrl_consistency	flash_ctrl_phy_host_grant_err	13.970s	14.937us	4	5	80.00
V2S	sec_cm_phy_ack_ctrl_consistency	flash_ctrl_phy_ack_consistency	17.320s	195.164us	5	5	100.00
V2S	sec_cm_fifo_ctr_redun	flash_ctrl_sec_cm	1.390h	4.322ms	5	5	100.00
V2S	sec_cm_mem_tl_lc_gate_fsm_sparse	flash_ctrl_sec_cm	1.390h	4.322ms	5	5	100.00
V2S	sec_cm_prog_tl_lc_gate_fsm_sparse	flash_ctrl_sec_cm	1.390h	4.322ms	5	5	100.00
V2S		TOTAL			146	147	99.32
V3	asymmetric_read_path	flash_ctrl_rd_ooo	45.520s	55.166us	1	1	100.00
V3	stress_all_with_rand_reset	flash_ctrl_stress_all_with_rand_reset			0	0	--
V3		TOTAL			1	1	100.00
		TOTAL			1276	1281	99.61

Testplan Progress

Items	Total	Written	Passing	Progress
V1	9	9	9	100.00
V2	55	55	51	92.73
V2S	13	13	12	92.31
V3	2	1	1	50.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
96.16	95.73	93.91	98.31	91.84	98.29	96.89	98.12

Failure Buckets

• UVM_ERROR (cip_base_scoreboard.sv:242) [scoreboard] Check failed expected_alert[alert_name].expected == * (* [*] vs * [*]) alert fatal_err triggered unexpectedly has 1 failures:

  • Test flash_ctrl_fs_sup has 1 failures.

    • 0.flash_ctrl_fs_sup.98703554727679219322047855250539558617345635777492051268768734175458165109440
      Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/0.flash_ctrl_fs_sup/latest/run.log

        UVM_ERROR @ 509554.5 ns: (cip_base_scoreboard.sv:242) [uvm_test_top.env.scoreboard] Check failed expected_alert[alert_name].expected == 1 (0 [0x0] vs 1 [0x1]) alert fatal_err triggered unexpectedly
        UVM_INFO @ 509554.5 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• Offending '(!$isunknown((alert_tx.alert_p ^ alert_tx.alert_n)))' has 1 failures:

  • Test flash_ctrl_phy_host_grant_err has 1 failures.

    • 2.flash_ctrl_phy_host_grant_err.111985238252694615202044018104138329322817799356225422335305484817913316872381
      Line 406, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/2.flash_ctrl_phy_host_grant_err/latest/run.log

            Offending '(!$isunknown((alert_tx.alert_p ^ alert_tx.alert_n)))'
        UVM_ERROR @ 7405.4 ns: (alert_esc_if.sv:189) [ASSERT FAILED] AlertKnown_A
        UVM_INFO @ 7405.4 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (csr_utils_pkg.sv:476) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: flash_ctrl_core_reg_block.std_fault_status.lcmgr_intg_err reset value: * has 1 failures:

  • Test flash_ctrl_lcmgr_intg has 1 failures.

    • 10.flash_ctrl_lcmgr_intg.74755748939431399917169094738698052801971524284605439715269439007523630084800
      Line 285, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/10.flash_ctrl_lcmgr_intg/latest/run.log

        UVM_ERROR @ 13241.6 ns: (csr_utils_pkg.sv:476) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: flash_ctrl_core_reg_block.std_fault_status.lcmgr_intg_err reset value: 0x0
        UVM_INFO @ 13241.6 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (csr_utils_pkg.sv:476) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: flash_ctrl_core_reg_block.op_status.err reset value: * has 1 failures:

  • Test flash_ctrl_rw_evict has 1 failures.

    • 16.flash_ctrl_rw_evict.109022390994703181020383760944242351761619919601597961495203786372365608711839
      Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/16.flash_ctrl_rw_evict/latest/run.log

        UVM_ERROR @ 14874.6 ns: (csr_utils_pkg.sv:476) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: flash_ctrl_core_reg_block.op_status.err reset value: 0x0
        UVM_INFO @ 14874.6 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (flash_ctrl_otf_scoreboard.sv:375) [rdata_comp_bank1] *: obs:exp *fd43229_ade72b06:ffffffff_ade72b* mismatch!! has 1 failures:

  • Test flash_ctrl_intr_rd has 1 failures.

    • 34.flash_ctrl_intr_rd.55797888238078531553132417615623249546382492569600537635827602966939304849108
      Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/34.flash_ctrl_intr_rd/latest/run.log

        UVM_ERROR @ 1176475.1 ns: (flash_ctrl_otf_scoreboard.sv:375) [rdata_comp_bank1]    6: obs:exp    7fd43229_ade72b06:ffffffff_ade72b06  mismatch!!
        UVM_INFO @ 1176475.1 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

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