3707c48f56| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | smoke | flash_ctrl_smoke | 3.654m | 121.662us | 50 | 50 | 100.00 |
| V1 | smoke_hw | flash_ctrl_smoke_hw | 26.940s | 27.309us | 5 | 5 | 100.00 |
| V1 | csr_hw_reset | flash_ctrl_csr_hw_reset | 45.320s | 25.495us | 5 | 5 | 100.00 |
| V1 | csr_rw | flash_ctrl_csr_rw | 17.430s | 361.608us | 20 | 20 | 100.00 |
| V1 | csr_bit_bash | flash_ctrl_csr_bit_bash | 1.226m | 5.699ms | 5 | 5 | 100.00 |
| V1 | csr_aliasing | flash_ctrl_csr_aliasing | 1.033m | 4.635ms | 5 | 5 | 100.00 |
| V1 | csr_mem_rw_with_rand_reset | flash_ctrl_csr_mem_rw_with_rand_reset | 19.840s | 858.373us | 20 | 20 | 100.00 |
| V1 | regwen_csr_and_corresponding_lockable_csr | flash_ctrl_csr_rw | 17.430s | 361.608us | 20 | 20 | 100.00 |
| flash_ctrl_csr_aliasing | 1.033m | 4.635ms | 5 | 5 | 100.00 | ||
| V1 | mem_walk | flash_ctrl_mem_walk | 13.390s | 30.898us | 5 | 5 | 100.00 |
| V1 | mem_partial_access | flash_ctrl_mem_partial_access | 14.180s | 59.419us | 5 | 5 | 100.00 |
| V1 | TOTAL | 120 | 120 | 100.00 | |||
| V2 | sw_op | flash_ctrl_sw_op | 27.450s | 41.553us | 5 | 5 | 100.00 |
| V2 | host_read_direct | flash_ctrl_host_dir_rd | 1.865m | 137.651us | 5 | 5 | 100.00 |
| V2 | rma_hw_if | flash_ctrl_hw_rma | 39.095m | 192.502ms | 3 | 3 | 100.00 |
| flash_ctrl_hw_rma_reset | 19.091m | 350.329ms | 20 | 20 | 100.00 | ||
| flash_ctrl_lcmgr_intg | 13.860s | 54.939us | 20 | 20 | 100.00 | ||
| V2 | host_controller_arb | flash_ctrl_host_ctrl_arb | 36.950m | 399.674ms | 5 | 5 | 100.00 |
| V2 | erase_suspend | flash_ctrl_erase_suspend | 9.168m | 3.486ms | 5 | 5 | 100.00 |
| V2 | program_reset | flash_ctrl_prog_reset | 3.271m | 9.525ms | 30 | 30 | 100.00 |
| V2 | full_memory_access | flash_ctrl_full_mem_access | 1.170h | 271.941ms | 5 | 5 | 100.00 |
| V2 | rd_buff_eviction | flash_ctrl_rd_buff_evict | 3.216m | 1.410ms | 5 | 5 | 100.00 |
| V2 | rd_buff_eviction_w_ecc | flash_ctrl_rw_evict | 32.580s | 29.947us | 26 | 40 | 65.00 |
| flash_ctrl_rw_evict_all_en | 32.210s | 166.958us | 28 | 40 | 70.00 | ||
| flash_ctrl_re_evict | 37.090s | 158.268us | 20 | 20 | 100.00 | ||
| V2 | host_arb | flash_ctrl_phy_arb | 7.467m | 5.686ms | 20 | 20 | 100.00 |
| V2 | host_interleave | flash_ctrl_phy_arb | 7.467m | 5.686ms | 20 | 20 | 100.00 |
| V2 | memory_protection | flash_ctrl_mp_regions | 21.849m | 67.819ms | 20 | 20 | 100.00 |
| V2 | fetch_code | flash_ctrl_fetch_code | 26.210s | 725.306us | 10 | 10 | 100.00 |
| V2 | all_partitions | flash_ctrl_rand_ops | 16.098m | 204.573us | 20 | 20 | 100.00 |
| V2 | error_mp | flash_ctrl_error_mp | 41.757m | 5.185ms | 10 | 10 | 100.00 |
| V2 | error_prog_win | flash_ctrl_error_prog_win | 16.561m | 2.053ms | 10 | 10 | 100.00 |
| V2 | error_prog_type | flash_ctrl_error_prog_type | 42.878m | 1.769ms | 5 | 5 | 100.00 |
| V2 | error_read_seed | flash_ctrl_hw_read_seed_err | 13.980s | 15.466us | 20 | 20 | 100.00 |
| V2 | read_write_overflow | flash_ctrl_oversize_error | 3.869m | 1.729ms | 5 | 5 | 100.00 |
| V2 | flash_ctrl_disable | flash_ctrl_disable | 23.160s | 20.784us | 50 | 50 | 100.00 |
| V2 | flash_ctrl_connect | flash_ctrl_connect | 16.490s | 62.814us | 80 | 80 | 100.00 |
| V2 | stress_all | flash_ctrl_stress_all | 26.475m | 940.450us | 5 | 5 | 100.00 |
| V2 | secret_partition | flash_ctrl_hw_sec_otp | 4.032m | 2.816ms | 50 | 50 | 100.00 |
| flash_ctrl_otp_reset | 2.268m | 181.276us | 80 | 80 | 100.00 | ||
| V2 | isolation_partition | flash_ctrl_hw_rma | 39.095m | 192.502ms | 3 | 3 | 100.00 |
| V2 | interrupts | flash_ctrl_intr_rd | 4.670m | 7.066ms | 39 | 40 | 97.50 |
| flash_ctrl_intr_wr | 1.298m | 4.607ms | 10 | 10 | 100.00 | ||
| flash_ctrl_intr_rd_slow_flash | 8.296m | 12.666ms | 40 | 40 | 100.00 | ||
| flash_ctrl_intr_wr_slow_flash | 4.965m | 97.908ms | 10 | 10 | 100.00 | ||
| V2 | invalid_op | flash_ctrl_invalid_op | 1.596m | 3.866ms | 20 | 20 | 100.00 |
| V2 | mid_op_rst | flash_ctrl_mid_op_rst | 1.262m | 3.307ms | 5 | 5 | 100.00 |
| V2 | double_bit_err | flash_ctrl_read_word_sweep_derr | 22.930s | 89.865us | 5 | 5 | 100.00 |
| flash_ctrl_ro_derr | 2.967m | 10.997ms | 10 | 10 | 100.00 | ||
| flash_ctrl_rw_derr | 4.590m | 7.707ms | 10 | 10 | 100.00 | ||
| flash_ctrl_derr_detect | 3.617m | 6.660ms | 5 | 5 | 100.00 | ||
| flash_ctrl_integrity | 13.304m | 16.761ms | 5 | 5 | 100.00 | ||
| V2 | single_bit_err | flash_ctrl_read_word_sweep_serr | 23.180s | 22.880us | 5 | 5 | 100.00 |
| flash_ctrl_ro_serr | 3.052m | 10.037ms | 10 | 10 | 100.00 | ||
| flash_ctrl_rw_serr | 4.632m | 2.211ms | 10 | 10 | 100.00 | ||
| V2 | singlebit_err_counter | flash_ctrl_serr_counter | 1.304m | 3.646ms | 5 | 5 | 100.00 |
| V2 | singlebit_err_address | flash_ctrl_serr_address | 1.752m | 6.871ms | 5 | 5 | 100.00 |
| V2 | scramble | flash_ctrl_wo | 4.130m | 5.528ms | 20 | 20 | 100.00 |
| flash_ctrl_write_word_sweep | 15.320s | 139.466us | 1 | 1 | 100.00 | ||
| flash_ctrl_read_word_sweep | 14.220s | 82.094us | 1 | 1 | 100.00 | ||
| flash_ctrl_ro | 2.608m | 3.578ms | 20 | 20 | 100.00 | ||
| flash_ctrl_rw | 10.571m | 7.690ms | 19 | 20 | 95.00 | ||
| V2 | filesystem_support | flash_ctrl_fs_sup | 43.850s | 334.391us | 5 | 5 | 100.00 |
| V2 | rma_write_process_error | flash_ctrl_rma_err | 19.545m | 68.238ms | 3 | 3 | 100.00 |
| flash_ctrl_hw_prog_rma_wipe_err | 5.335m | 10.013ms | 20 | 20 | 100.00 | ||
| V2 | alert_test | flash_ctrl_alert_test | 14.360s | 73.590us | 50 | 50 | 100.00 |
| V2 | intr_test | flash_ctrl_intr_test | 14.120s | 16.636us | 50 | 50 | 100.00 |
| V2 | tl_d_oob_addr_access | flash_ctrl_tl_errors | 21.830s | 139.166us | 20 | 20 | 100.00 |
| V2 | tl_d_illegal_access | flash_ctrl_tl_errors | 21.830s | 139.166us | 20 | 20 | 100.00 |
| V2 | tl_d_outstanding_access | flash_ctrl_csr_hw_reset | 45.320s | 25.495us | 5 | 5 | 100.00 |
| flash_ctrl_csr_rw | 17.430s | 361.608us | 20 | 20 | 100.00 | ||
| flash_ctrl_csr_aliasing | 1.033m | 4.635ms | 5 | 5 | 100.00 | ||
| flash_ctrl_same_csr_outstanding | 35.670s | 391.700us | 20 | 20 | 100.00 | ||
| V2 | tl_d_partial_access | flash_ctrl_csr_hw_reset | 45.320s | 25.495us | 5 | 5 | 100.00 |
| flash_ctrl_csr_rw | 17.430s | 361.608us | 20 | 20 | 100.00 | ||
| flash_ctrl_csr_aliasing | 1.033m | 4.635ms | 5 | 5 | 100.00 | ||
| flash_ctrl_same_csr_outstanding | 35.670s | 391.700us | 20 | 20 | 100.00 | ||
| V2 | TOTAL | 985 | 1013 | 97.24 | |||
| V2S | shadow_reg_update_error | flash_ctrl_shadow_reg_errors | 16.110s | 110.130us | 20 | 20 | 100.00 |
| V2S | shadow_reg_read_clear_staged_value | flash_ctrl_shadow_reg_errors | 16.110s | 110.130us | 20 | 20 | 100.00 |
| V2S | shadow_reg_storage_error | flash_ctrl_shadow_reg_errors | 16.110s | 110.130us | 20 | 20 | 100.00 |
| V2S | shadowed_reset_glitch | flash_ctrl_shadow_reg_errors | 16.110s | 110.130us | 20 | 20 | 100.00 |
| V2S | shadow_reg_update_error_with_csr_rw | flash_ctrl_shadow_reg_errors_with_csr_rw | 16.150s | 26.906us | 20 | 20 | 100.00 |
| V2S | tl_intg_err | flash_ctrl_sec_cm | 1.364h | 6.399ms | 5 | 5 | 100.00 |
| flash_ctrl_tl_intg_err | 15.312m | 2.280ms | 20 | 20 | 100.00 | ||
| V2S | sec_cm_reg_bus_integrity | flash_ctrl_tl_intg_err | 15.312m | 2.280ms | 20 | 20 | 100.00 |
| V2S | sec_cm_host_bus_integrity | flash_ctrl_tl_intg_err | 15.312m | 2.280ms | 20 | 20 | 100.00 |
| V2S | sec_cm_mem_bus_integrity | flash_ctrl_rd_intg | 31.860s | 495.913us | 3 | 3 | 100.00 |
| flash_ctrl_wr_intg | 15.340s | 123.115us | 3 | 3 | 100.00 | ||
| V2S | sec_cm_scramble_key_sideload | flash_ctrl_smoke | 3.654m | 121.662us | 50 | 50 | 100.00 |
| V2S | sec_cm_lc_ctrl_intersig_mubi | flash_ctrl_otp_reset | 2.268m | 181.276us | 80 | 80 | 100.00 |
| flash_ctrl_disable | 23.160s | 20.784us | 50 | 50 | 100.00 | ||
| flash_ctrl_sec_info_access | 1.628m | 26.135ms | 50 | 50 | 100.00 | ||
| flash_ctrl_connect | 16.490s | 62.814us | 80 | 80 | 100.00 | ||
| V2S | sec_cm_ctrl_config_regwen | flash_ctrl_config_regwen | 14.290s | 69.581us | 5 | 5 | 100.00 |
| V2S | sec_cm_data_regions_config_regwen | flash_ctrl_csr_rw | 17.430s | 361.608us | 20 | 20 | 100.00 |
| V2S | sec_cm_data_regions_config_shadow | flash_ctrl_shadow_reg_errors | 16.110s | 110.130us | 20 | 20 | 100.00 |
| V2S | sec_cm_info_regions_config_regwen | flash_ctrl_csr_rw | 17.430s | 361.608us | 20 | 20 | 100.00 |
| V2S | sec_cm_info_regions_config_shadow | flash_ctrl_shadow_reg_errors | 16.110s | 110.130us | 20 | 20 | 100.00 |
| V2S | sec_cm_bank_config_regwen | flash_ctrl_csr_rw | 17.430s | 361.608us | 20 | 20 | 100.00 |
| V2S | sec_cm_bank_config_shadow | flash_ctrl_shadow_reg_errors | 16.110s | 110.130us | 20 | 20 | 100.00 |
| V2S | sec_cm_mem_ctrl_global_esc | flash_ctrl_disable | 23.160s | 20.784us | 50 | 50 | 100.00 |
| V2S | sec_cm_mem_ctrl_local_esc | flash_ctrl_rd_intg | 31.860s | 495.913us | 3 | 3 | 100.00 |
| flash_ctrl_access_after_disable | 13.820s | 12.397us | 3 | 3 | 100.00 | ||
| V2S | sec_cm_mem_addr_infection | flash_ctrl_host_addr_infection | 30.630s | 63.449us | 3 | 3 | 100.00 |
| V2S | sec_cm_mem_disable_config_mubi | flash_ctrl_disable | 23.160s | 20.784us | 50 | 50 | 100.00 |
| V2S | sec_cm_exec_config_redun | flash_ctrl_fetch_code | 26.210s | 725.306us | 10 | 10 | 100.00 |
| V2S | sec_cm_mem_scramble | flash_ctrl_rw | 10.571m | 7.690ms | 19 | 20 | 95.00 |
| V2S | sec_cm_mem_integrity | flash_ctrl_rw_serr | 4.632m | 2.211ms | 10 | 10 | 100.00 |
| flash_ctrl_rw_derr | 4.590m | 7.707ms | 10 | 10 | 100.00 | ||
| flash_ctrl_integrity | 13.304m | 16.761ms | 5 | 5 | 100.00 | ||
| V2S | sec_cm_rma_entry_mem_sec_wipe | flash_ctrl_hw_rma | 39.095m | 192.502ms | 3 | 3 | 100.00 |
| V2S | sec_cm_ctrl_fsm_sparse | flash_ctrl_sec_cm | 1.364h | 6.399ms | 5 | 5 | 100.00 |
| V2S | sec_cm_phy_fsm_sparse | flash_ctrl_sec_cm | 1.364h | 6.399ms | 5 | 5 | 100.00 |
| V2S | sec_cm_phy_prog_fsm_sparse | flash_ctrl_sec_cm | 1.364h | 6.399ms | 5 | 5 | 100.00 |
| V2S | sec_cm_ctr_redun | flash_ctrl_sec_cm | 1.364h | 6.399ms | 5 | 5 | 100.00 |
| V2S | sec_cm_phy_arbiter_ctrl_redun | flash_ctrl_phy_arb_redun | 22.750s | 866.367us | 5 | 5 | 100.00 |
| V2S | sec_cm_phy_host_grant_ctrl_consistency | flash_ctrl_phy_host_grant_err | 14.940s | 14.758us | 5 | 5 | 100.00 |
| V2S | sec_cm_phy_ack_ctrl_consistency | flash_ctrl_phy_ack_consistency | 22.740s | 132.755us | 5 | 5 | 100.00 |
| V2S | sec_cm_fifo_ctr_redun | flash_ctrl_sec_cm | 1.364h | 6.399ms | 5 | 5 | 100.00 |
| V2S | sec_cm_mem_tl_lc_gate_fsm_sparse | flash_ctrl_sec_cm | 1.364h | 6.399ms | 5 | 5 | 100.00 |
| V2S | sec_cm_prog_tl_lc_gate_fsm_sparse | flash_ctrl_sec_cm | 1.364h | 6.399ms | 5 | 5 | 100.00 |
| V2S | TOTAL | 147 | 147 | 100.00 | |||
| V3 | asymmetric_read_path | flash_ctrl_rd_ooo | 45.260s | 107.640us | 1 | 1 | 100.00 |
| V3 | stress_all_with_rand_reset | flash_ctrl_stress_all_with_rand_reset | 0 | 0 | -- | ||
| V3 | TOTAL | 1 | 1 | 100.00 | |||
| TOTAL | 1253 | 1281 | 97.81 |
| Items | Total | Written | Passing | Progress |
|---|---|---|---|---|
| V1 | 9 | 9 | 9 | 100.00 |
| V2 | 55 | 55 | 51 | 92.73 |
| V2S | 13 | 13 | 13 | 100.00 |
| V3 | 2 | 1 | 1 | 50.00 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
|---|---|---|---|---|---|---|---|
| 96.24 | 95.70 | 93.92 | 98.31 | 92.52 | 98.14 | 96.89 | 98.18 |
UVM_ERROR (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: flash_ctrl_core_reg_block.op_status.err reset value: * has 5 failures:
0.flash_ctrl_rw_evict.13604376498585784252186371881802713482694678433766446856141206093177004596370
Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/0.flash_ctrl_rw_evict/latest/run.log
UVM_ERROR @ 21841.2 ns: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: flash_ctrl_core_reg_block.op_status.err reset value: 0x0
UVM_INFO @ 21841.2 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
12.flash_ctrl_rw_evict.22918792421269596482382473759215803568817326438511607656276327496755967809177
Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/12.flash_ctrl_rw_evict/latest/run.log
UVM_ERROR @ 19581.2 ns: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: flash_ctrl_core_reg_block.op_status.err reset value: 0x0
UVM_INFO @ 19581.2 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 1 more failures.
26.flash_ctrl_rw_evict_all_en.84971394624306022807356241878469163089277354777801870048490630763573571584698
Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/26.flash_ctrl_rw_evict_all_en/latest/run.log
UVM_ERROR @ 53678.7 ns: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: flash_ctrl_core_reg_block.op_status.err reset value: 0x0
UVM_INFO @ 53678.7 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
36.flash_ctrl_rw_evict_all_en.51629373869125516213283557077414180316997645361713350986320817486082188950914
Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/36.flash_ctrl_rw_evict_all_en/latest/run.log
UVM_ERROR @ 14903.8 ns: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: flash_ctrl_core_reg_block.op_status.err reset value: 0x0
UVM_INFO @ 14903.8 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_scoreboard.sv:484) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface flash_ctrl_eflash_reg_block, TL item: req: (cip_tl_seq_item@154788) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_source_is_overridden: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:
2.flash_ctrl_rw_evict.15303191582538148487026192492845473393106562248023788154239953160018195602145
Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/2.flash_ctrl_rw_evict/latest/run.log
UVM_ERROR @ 43304.4 ns: (cip_base_scoreboard.sv:484) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (1 [0x1] vs 0 [0x0]) On interface flash_ctrl_eflash_reg_block, TL item: req: (cip_tl_seq_item@154788) { a_addr: 'h619c8 a_data: 'h0 a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h29 a_opcode: 'h4 a_user: 'h25d2a d_param: 'h0 d_source: 'h29 d_data: 'hffffffff d_size: 'h2 d_opcode: 'h1 d_error: 'h1 d_sink: 'h0 d_user: 'heaa a_source_is_overridden: 'h0 a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
, unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
UVM_INFO @ 43304.4 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_scoreboard.sv:484) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface flash_ctrl_eflash_reg_block, TL item: req: (cip_tl_seq_item@155500) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_source_is_overridden: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:
2.flash_ctrl_rw_evict_all_en.36172882315793992514007873609849376314140240861994042620056825396505441851513
Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/2.flash_ctrl_rw_evict_all_en/latest/run.log
UVM_ERROR @ 33568.5 ns: (cip_base_scoreboard.sv:484) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (1 [0x1] vs 0 [0x0]) On interface flash_ctrl_eflash_reg_block, TL item: req: (cip_tl_seq_item@155500) { a_addr: 'he2070 a_data: 'h0 a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h4e a_opcode: 'h4 a_user: 'h26f2a d_param: 'h0 d_source: 'h4e d_data: 'hffffffff d_size: 'h2 d_opcode: 'h1 d_error: 'h1 d_sink: 'h0 d_user: 'heaa a_source_is_overridden: 'h0 a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
, unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
UVM_INFO @ 33568.5 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_scoreboard.sv:484) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface flash_ctrl_eflash_reg_block, TL item: req: (cip_tl_seq_item@155830) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_source_is_overridden: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:
6.flash_ctrl_rw_evict.65555380683809984196185674845513172302389724096115035090696166286253244324360
Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/6.flash_ctrl_rw_evict/latest/run.log
UVM_ERROR @ 11126.6 ns: (cip_base_scoreboard.sv:484) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (1 [0x1] vs 0 [0x0]) On interface flash_ctrl_eflash_reg_block, TL item: req: (cip_tl_seq_item@155830) { a_addr: 'h57b68 a_data: 'h0 a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h5 a_opcode: 'h4 a_user: 'h2562a d_param: 'h0 d_source: 'h5 d_data: 'hffffffff d_size: 'h2 d_opcode: 'h1 d_error: 'h1 d_sink: 'h0 d_user: 'heaa a_source_is_overridden: 'h0 a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
, unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
UVM_INFO @ 11126.6 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_scoreboard.sv:484) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface flash_ctrl_eflash_reg_block, TL item: req: (cip_tl_seq_item@152518) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_source_is_overridden: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:
7.flash_ctrl_rw_evict.46406653711161208683332990196002086580810792839973502837171510853931565865795
Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/7.flash_ctrl_rw_evict/latest/run.log
UVM_ERROR @ 12675.7 ns: (cip_base_scoreboard.sv:484) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (1 [0x1] vs 0 [0x0]) On interface flash_ctrl_eflash_reg_block, TL item: req: (cip_tl_seq_item@152518) { a_addr: 'h83748 a_data: 'h0 a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h87 a_opcode: 'h4 a_user: 'h26aaa d_param: 'h0 d_source: 'h87 d_data: 'hffffffff d_size: 'h2 d_opcode: 'h1 d_error: 'h1 d_sink: 'h0 d_user: 'heaa a_source_is_overridden: 'h0 a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
, unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
UVM_INFO @ 12675.7 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_scoreboard.sv:242) [scoreboard] Check failed expected_alert[alert_name].expected == * (* [*] vs * [*]) alert fatal_err triggered unexpectedly has 1 failures:
8.flash_ctrl_rw.93797050469341232250320454338370868091047224855464345719279194518790283194716
Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/8.flash_ctrl_rw/latest/run.log
UVM_ERROR @ 1093890.3 ns: (cip_base_scoreboard.sv:242) [uvm_test_top.env.scoreboard] Check failed expected_alert[alert_name].expected == 1 (0 [0x0] vs 1 [0x1]) alert fatal_err triggered unexpectedly
UVM_INFO @ 1093890.3 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_scoreboard.sv:484) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface flash_ctrl_eflash_reg_block, TL item: req: (cip_tl_seq_item@153014) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_source_is_overridden: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:
10.flash_ctrl_rw_evict.90896103326436079969946324007605795373572883862572252324136149146074316607815
Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/10.flash_ctrl_rw_evict/latest/run.log
UVM_ERROR @ 34435.8 ns: (cip_base_scoreboard.sv:484) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (1 [0x1] vs 0 [0x0]) On interface flash_ctrl_eflash_reg_block, TL item: req: (cip_tl_seq_item@153014) { a_addr: 'h46f30 a_data: 'h0 a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'hdd a_opcode: 'h4 a_user: 'h279aa d_param: 'h0 d_source: 'hdd d_data: 'hffffffff d_size: 'h2 d_opcode: 'h1 d_error: 'h1 d_sink: 'h0 d_user: 'heaa a_source_is_overridden: 'h0 a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
, unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
UVM_INFO @ 34435.8 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_scoreboard.sv:484) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface flash_ctrl_eflash_reg_block, TL item: req: (cip_tl_seq_item@157281) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_source_is_overridden: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:
11.flash_ctrl_rw_evict.34246874468490043066628292396739961268753111445395867535077217885417787914304
Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/11.flash_ctrl_rw_evict/latest/run.log
UVM_ERROR @ 11846.1 ns: (cip_base_scoreboard.sv:484) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (1 [0x1] vs 0 [0x0]) On interface flash_ctrl_eflash_reg_block, TL item: req: (cip_tl_seq_item@157281) { a_addr: 'hcab0 a_data: 'h0 a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'hbb a_opcode: 'h4 a_user: 'h25f2a d_param: 'h0 d_source: 'hbb d_data: 'hffffffff d_size: 'h2 d_opcode: 'h1 d_error: 'h1 d_sink: 'h0 d_user: 'heaa a_source_is_overridden: 'h0 a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
, unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
UVM_INFO @ 11846.1 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_scoreboard.sv:484) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface flash_ctrl_eflash_reg_block, TL item: req: (cip_tl_seq_item@155530) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_source_is_overridden: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:
13.flash_ctrl_rw_evict_all_en.43641400717236129852750169014486005160087866684528960681620470774487477322228
Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/13.flash_ctrl_rw_evict_all_en/latest/run.log
UVM_ERROR @ 10428.7 ns: (cip_base_scoreboard.sv:484) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (1 [0x1] vs 0 [0x0]) On interface flash_ctrl_eflash_reg_block, TL item: req: (cip_tl_seq_item@155530) { a_addr: 'hd6958 a_data: 'h0 a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h88 a_opcode: 'h4 a_user: 'h27a2a d_param: 'h0 d_source: 'h88 d_data: 'hffffffff d_size: 'h2 d_opcode: 'h1 d_error: 'h1 d_sink: 'h0 d_user: 'heaa a_source_is_overridden: 'h0 a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
, unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
UVM_INFO @ 10428.7 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_scoreboard.sv:484) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface flash_ctrl_eflash_reg_block, TL item: req: (cip_tl_seq_item@155547) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_source_is_overridden: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:
16.flash_ctrl_rw_evict_all_en.82736026299785756519673165286472102824094872205812439852450389924829295465379
Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/16.flash_ctrl_rw_evict_all_en/latest/run.log
UVM_ERROR @ 30621.0 ns: (cip_base_scoreboard.sv:484) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (1 [0x1] vs 0 [0x0]) On interface flash_ctrl_eflash_reg_block, TL item: req: (cip_tl_seq_item@155547) { a_addr: 'h68d58 a_data: 'h0 a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'hd7 a_opcode: 'h4 a_user: 'h24e2a d_param: 'h0 d_source: 'hd7 d_data: 'hffffffff d_size: 'h2 d_opcode: 'h1 d_error: 'h1 d_sink: 'h0 d_user: 'heaa a_source_is_overridden: 'h0 a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
, unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
UVM_INFO @ 30621.0 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_scoreboard.sv:484) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface flash_ctrl_eflash_reg_block, TL item: req: (cip_tl_seq_item@155309) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_source_is_overridden: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:
17.flash_ctrl_rw_evict.114329074895283716291793121024130407540900033626296463176328792422572504156309
Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/17.flash_ctrl_rw_evict/latest/run.log
UVM_ERROR @ 63771.7 ns: (cip_base_scoreboard.sv:484) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (1 [0x1] vs 0 [0x0]) On interface flash_ctrl_eflash_reg_block, TL item: req: (cip_tl_seq_item@155309) { a_addr: 'hf2ee8 a_data: 'h0 a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'he9 a_opcode: 'h4 a_user: 'h27daa d_param: 'h0 d_source: 'he9 d_data: 'hffffffff d_size: 'h2 d_opcode: 'h1 d_error: 'h1 d_sink: 'h0 d_user: 'heaa a_source_is_overridden: 'h0 a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
, unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
UVM_INFO @ 63771.7 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_scoreboard.sv:484) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface flash_ctrl_eflash_reg_block, TL item: req: (cip_tl_seq_item@153450) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_source_is_overridden: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:
20.flash_ctrl_rw_evict_all_en.3751662989507271987625330494247937821099643422670301189106486602874065645973
Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/20.flash_ctrl_rw_evict_all_en/latest/run.log
UVM_ERROR @ 37604.5 ns: (cip_base_scoreboard.sv:484) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (1 [0x1] vs 0 [0x0]) On interface flash_ctrl_eflash_reg_block, TL item: req: (cip_tl_seq_item@153450) { a_addr: 'h7bdc8 a_data: 'h0 a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'hbc a_opcode: 'h4 a_user: 'h26b2a d_param: 'h0 d_source: 'hbc d_data: 'hffffffff d_size: 'h2 d_opcode: 'h1 d_error: 'h1 d_sink: 'h0 d_user: 'heaa a_source_is_overridden: 'h0 a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
, unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
UVM_INFO @ 37604.5 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_scoreboard.sv:484) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface flash_ctrl_eflash_reg_block, TL item: req: (cip_tl_seq_item@158380) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_source_is_overridden: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:
21.flash_ctrl_rw_evict_all_en.104836812020039538905760958119914363064087955162002123837426723382651338639695
Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/21.flash_ctrl_rw_evict_all_en/latest/run.log
UVM_ERROR @ 24578.2 ns: (cip_base_scoreboard.sv:484) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (1 [0x1] vs 0 [0x0]) On interface flash_ctrl_eflash_reg_block, TL item: req: (cip_tl_seq_item@158380) { a_addr: 'h27cc8 a_data: 'h0 a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h74 a_opcode: 'h4 a_user: 'h2772a d_param: 'h0 d_source: 'h74 d_data: 'hffffffff d_size: 'h2 d_opcode: 'h1 d_error: 'h1 d_sink: 'h0 d_user: 'heaa a_source_is_overridden: 'h0 a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
, unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
UVM_INFO @ 24578.2 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_scoreboard.sv:484) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface flash_ctrl_eflash_reg_block, TL item: req: (cip_tl_seq_item@152026) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_source_is_overridden: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:
22.flash_ctrl_rw_evict_all_en.40990551711951177572903745864682221470916356134326747123428657054629923963926
Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/22.flash_ctrl_rw_evict_all_en/latest/run.log
UVM_ERROR @ 7873.5 ns: (cip_base_scoreboard.sv:484) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (1 [0x1] vs 0 [0x0]) On interface flash_ctrl_eflash_reg_block, TL item: req: (cip_tl_seq_item@152026) { a_addr: 'h1e668 a_data: 'h0 a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h11 a_opcode: 'h4 a_user: 'h27b2a d_param: 'h0 d_source: 'h11 d_data: 'hffffffff d_size: 'h2 d_opcode: 'h1 d_error: 'h1 d_sink: 'h0 d_user: 'heaa a_source_is_overridden: 'h0 a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
, unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
UVM_INFO @ 7873.5 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (flash_ctrl_otf_scoreboard.sv:375) [rdata_comp_bank1] *: obs:exp fe75993e_8b42a8cf:ffffffff_ffffffff mismatch!! has 1 failures:
25.flash_ctrl_intr_rd.73850124167577712450050134667582087148734732782918370768311742648463299663303
Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/25.flash_ctrl_intr_rd/latest/run.log
UVM_ERROR @ 3456255.9 ns: (flash_ctrl_otf_scoreboard.sv:375) [rdata_comp_bank1] 7: obs:exp fe75993e_8b42a8cf:ffffffff_ffffffff mismatch!!
UVM_INFO @ 3456255.9 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_scoreboard.sv:484) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface flash_ctrl_eflash_reg_block, TL item: req: (cip_tl_seq_item@151899) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_source_is_overridden: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:
25.flash_ctrl_rw_evict.114199401784567850440536368985564815322985983933253952420441893567540144585134
Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/25.flash_ctrl_rw_evict/latest/run.log
UVM_ERROR @ 7855.5 ns: (cip_base_scoreboard.sv:484) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (1 [0x1] vs 0 [0x0]) On interface flash_ctrl_eflash_reg_block, TL item: req: (cip_tl_seq_item@151899) { a_addr: 'h3ed50 a_data: 'h0 a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h4c a_opcode: 'h4 a_user: 'h24daa d_param: 'h0 d_source: 'h4c d_data: 'hffffffff d_size: 'h2 d_opcode: 'h1 d_error: 'h1 d_sink: 'h0 d_user: 'heaa a_source_is_overridden: 'h0 a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
, unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
UVM_INFO @ 7855.5 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_scoreboard.sv:484) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface flash_ctrl_eflash_reg_block, TL item: req: (cip_tl_seq_item@158252) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_source_is_overridden: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:
26.flash_ctrl_rw_evict.43016722229015974007985651733928594222499591879415706184471390454410456397852
Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/26.flash_ctrl_rw_evict/latest/run.log
UVM_ERROR @ 251456.9 ns: (cip_base_scoreboard.sv:484) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (1 [0x1] vs 0 [0x0]) On interface flash_ctrl_eflash_reg_block, TL item: req: (cip_tl_seq_item@158252) { a_addr: 'ha6038 a_data: 'h0 a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'hbf a_opcode: 'h4 a_user: 'h2782a d_param: 'h0 d_source: 'hbf d_data: 'hffffffff d_size: 'h2 d_opcode: 'h1 d_error: 'h1 d_sink: 'h0 d_user: 'heaa a_source_is_overridden: 'h0 a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
, unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
UVM_INFO @ 251456.9 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_scoreboard.sv:484) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface flash_ctrl_eflash_reg_block, TL item: req: (cip_tl_seq_item@156714) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_source_is_overridden: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:
29.flash_ctrl_rw_evict_all_en.71928121270699699745312938449804249709528835114276055213389921638313580637431
Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/29.flash_ctrl_rw_evict_all_en/latest/run.log
UVM_ERROR @ 11250.6 ns: (cip_base_scoreboard.sv:484) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (1 [0x1] vs 0 [0x0]) On interface flash_ctrl_eflash_reg_block, TL item: req: (cip_tl_seq_item@156714) { a_addr: 'ha7c08 a_data: 'h0 a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'hc6 a_opcode: 'h4 a_user: 'h2792a d_param: 'h0 d_source: 'hc6 d_data: 'hffffffff d_size: 'h2 d_opcode: 'h1 d_error: 'h1 d_sink: 'h0 d_user: 'heaa a_source_is_overridden: 'h0 a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
, unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
UVM_INFO @ 11250.6 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_scoreboard.sv:484) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface flash_ctrl_eflash_reg_block, TL item: req: (cip_tl_seq_item@154520) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_source_is_overridden: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:
30.flash_ctrl_rw_evict_all_en.68245757173577460322369042737661535947731960408165219251000305385123118899575
Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/30.flash_ctrl_rw_evict_all_en/latest/run.log
UVM_ERROR @ 37788.6 ns: (cip_base_scoreboard.sv:484) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (1 [0x1] vs 0 [0x0]) On interface flash_ctrl_eflash_reg_block, TL item: req: (cip_tl_seq_item@154520) { a_addr: 'hd2750 a_data: 'h0 a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h6a a_opcode: 'h4 a_user: 'h270aa d_param: 'h0 d_source: 'h6a d_data: 'hffffffff d_size: 'h2 d_opcode: 'h1 d_error: 'h1 d_sink: 'h0 d_user: 'heaa a_source_is_overridden: 'h0 a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
, unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
UVM_INFO @ 37788.6 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_scoreboard.sv:484) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface flash_ctrl_eflash_reg_block, TL item: req: (cip_tl_seq_item@155720) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_source_is_overridden: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:
32.flash_ctrl_rw_evict_all_en.83690304985930039458578205535545709031878931371741497123277392363809401956792
Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/32.flash_ctrl_rw_evict_all_en/latest/run.log
UVM_ERROR @ 42682.8 ns: (cip_base_scoreboard.sv:484) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (1 [0x1] vs 0 [0x0]) On interface flash_ctrl_eflash_reg_block, TL item: req: (cip_tl_seq_item@155720) { a_addr: 'h75d80 a_data: 'h0 a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h2a a_opcode: 'h4 a_user: 'h27e2a d_param: 'h0 d_source: 'h2a d_data: 'hffffffff d_size: 'h2 d_opcode: 'h1 d_error: 'h1 d_sink: 'h0 d_user: 'heaa a_source_is_overridden: 'h0 a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
, unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
UVM_INFO @ 42682.8 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_scoreboard.sv:484) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface flash_ctrl_eflash_reg_block, TL item: req: (cip_tl_seq_item@154878) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_source_is_overridden: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:
35.flash_ctrl_rw_evict.52011419346645738468808695430137594198392908498727631538218934148047214253000
Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/35.flash_ctrl_rw_evict/latest/run.log
UVM_ERROR @ 196986.5 ns: (cip_base_scoreboard.sv:484) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (1 [0x1] vs 0 [0x0]) On interface flash_ctrl_eflash_reg_block, TL item: req: (cip_tl_seq_item@154878) { a_addr: 'h48e28 a_data: 'h0 a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'hae a_opcode: 'h4 a_user: 'h267aa d_param: 'h0 d_source: 'hae d_data: 'hffffffff d_size: 'h2 d_opcode: 'h1 d_error: 'h1 d_sink: 'h0 d_user: 'heaa a_source_is_overridden: 'h0 a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
, unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
UVM_INFO @ 196986.5 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_scoreboard.sv:484) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface flash_ctrl_eflash_reg_block, TL item: req: (cip_tl_seq_item@153959) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_source_is_overridden: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:
37.flash_ctrl_rw_evict.85060192608001261996725088900902640206611740903166545332343611255843835169565
Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/37.flash_ctrl_rw_evict/latest/run.log
UVM_ERROR @ 37907.8 ns: (cip_base_scoreboard.sv:484) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (1 [0x1] vs 0 [0x0]) On interface flash_ctrl_eflash_reg_block, TL item: req: (cip_tl_seq_item@153959) { a_addr: 'h33e98 a_data: 'h0 a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h7f a_opcode: 'h4 a_user: 'h27c2a d_param: 'h0 d_source: 'h7f d_data: 'hffffffff d_size: 'h2 d_opcode: 'h1 d_error: 'h1 d_sink: 'h0 d_user: 'heaa a_source_is_overridden: 'h0 a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
, unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
UVM_INFO @ 37907.8 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_scoreboard.sv:484) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface flash_ctrl_eflash_reg_block, TL item: req: (cip_tl_seq_item@162905) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_source_is_overridden: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:
38.flash_ctrl_rw_evict.95489472703752590820627822048262524198145553868640954919041075389764574145482
Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/38.flash_ctrl_rw_evict/latest/run.log
UVM_ERROR @ 63276.0 ns: (cip_base_scoreboard.sv:484) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (1 [0x1] vs 0 [0x0]) On interface flash_ctrl_eflash_reg_block, TL item: req: (cip_tl_seq_item@162905) { a_addr: 'hf588 a_data: 'h0 a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'he a_opcode: 'h4 a_user: 'h253aa d_param: 'h0 d_source: 'he d_data: 'hffffffff d_size: 'h2 d_opcode: 'h1 d_error: 'h1 d_sink: 'h0 d_user: 'heaa a_source_is_overridden: 'h0 a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
, unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
UVM_INFO @ 63276.0 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_scoreboard.sv:484) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface flash_ctrl_eflash_reg_block, TL item: req: (cip_tl_seq_item@151280) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_source_is_overridden: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:
38.flash_ctrl_rw_evict_all_en.37458167700025106137948469179756064467806855291808886485619843567370502017449
Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/38.flash_ctrl_rw_evict_all_en/latest/run.log
UVM_ERROR @ 12757.1 ns: (cip_base_scoreboard.sv:484) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (1 [0x1] vs 0 [0x0]) On interface flash_ctrl_eflash_reg_block, TL item: req: (cip_tl_seq_item@151280) { a_addr: 'h44f88 a_data: 'h0 a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'hf1 a_opcode: 'h4 a_user: 'h274aa d_param: 'h0 d_source: 'hf1 d_data: 'hffffffff d_size: 'h2 d_opcode: 'h1 d_error: 'h1 d_sink: 'h0 d_user: 'heaa a_source_is_overridden: 'h0 a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
, unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
UVM_INFO @ 12757.1 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---