bbf435ceff| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | smoke | flash_ctrl_smoke | 3.305m | 51.434us | 50 | 50 | 100.00 |
| V1 | smoke_hw | flash_ctrl_smoke_hw | 26.790s | 58.957us | 5 | 5 | 100.00 |
| V1 | csr_hw_reset | flash_ctrl_csr_hw_reset | 45.580s | 27.299us | 5 | 5 | 100.00 |
| V1 | csr_rw | flash_ctrl_csr_rw | 17.980s | 212.114us | 20 | 20 | 100.00 |
| V1 | csr_bit_bash | flash_ctrl_csr_bit_bash | 1.575m | 24.794ms | 5 | 5 | 100.00 |
| V1 | csr_aliasing | flash_ctrl_csr_aliasing | 55.780s | 2.011ms | 5 | 5 | 100.00 |
| V1 | csr_mem_rw_with_rand_reset | flash_ctrl_csr_mem_rw_with_rand_reset | 20.770s | 165.946us | 20 | 20 | 100.00 |
| V1 | regwen_csr_and_corresponding_lockable_csr | flash_ctrl_csr_rw | 17.980s | 212.114us | 20 | 20 | 100.00 |
| flash_ctrl_csr_aliasing | 55.780s | 2.011ms | 5 | 5 | 100.00 | ||
| V1 | mem_walk | flash_ctrl_mem_walk | 13.510s | 34.851us | 5 | 5 | 100.00 |
| V1 | mem_partial_access | flash_ctrl_mem_partial_access | 13.850s | 32.108us | 5 | 5 | 100.00 |
| V1 | TOTAL | 120 | 120 | 100.00 | |||
| V2 | sw_op | flash_ctrl_sw_op | 26.830s | 26.113us | 5 | 5 | 100.00 |
| V2 | host_read_direct | flash_ctrl_host_dir_rd | 1.950m | 236.970us | 5 | 5 | 100.00 |
| V2 | rma_hw_if | flash_ctrl_hw_rma | 47.461m | 1.015s | 3 | 3 | 100.00 |
| flash_ctrl_hw_rma_reset | 16.794m | 210.190ms | 20 | 20 | 100.00 | ||
| flash_ctrl_lcmgr_intg | 14.360s | 46.410us | 19 | 20 | 95.00 | ||
| V2 | host_controller_arb | flash_ctrl_host_ctrl_arb | 52.440m | 273.361ms | 5 | 5 | 100.00 |
| V2 | erase_suspend | flash_ctrl_erase_suspend | 7.382m | 12.036ms | 5 | 5 | 100.00 |
| V2 | program_reset | flash_ctrl_prog_reset | 3.925m | 36.060ms | 30 | 30 | 100.00 |
| V2 | full_memory_access | flash_ctrl_full_mem_access | 1.219h | 195.646ms | 5 | 5 | 100.00 |
| V2 | rd_buff_eviction | flash_ctrl_rd_buff_evict | 2.355m | 2.927ms | 5 | 5 | 100.00 |
| V2 | rd_buff_eviction_w_ecc | flash_ctrl_rw_evict | 32.540s | 71.160us | 28 | 40 | 70.00 |
| flash_ctrl_rw_evict_all_en | 32.530s | 31.445us | 33 | 40 | 82.50 | ||
| flash_ctrl_re_evict | 37.130s | 217.573us | 20 | 20 | 100.00 | ||
| V2 | host_arb | flash_ctrl_phy_arb | 7.740m | 799.182us | 20 | 20 | 100.00 |
| V2 | host_interleave | flash_ctrl_phy_arb | 7.740m | 799.182us | 20 | 20 | 100.00 |
| V2 | memory_protection | flash_ctrl_mp_regions | 19.671m | 35.215ms | 20 | 20 | 100.00 |
| V2 | fetch_code | flash_ctrl_fetch_code | 28.370s | 1.167ms | 10 | 10 | 100.00 |
| V2 | all_partitions | flash_ctrl_rand_ops | 25.340m | 1.512ms | 20 | 20 | 100.00 |
| V2 | error_mp | flash_ctrl_error_mp | 45.685m | 11.254ms | 10 | 10 | 100.00 |
| V2 | error_prog_win | flash_ctrl_error_prog_win | 20.608m | 4.687ms | 10 | 10 | 100.00 |
| V2 | error_prog_type | flash_ctrl_error_prog_type | 45.987m | 7.969ms | 5 | 5 | 100.00 |
| V2 | error_read_seed | flash_ctrl_hw_read_seed_err | 14.180s | 26.714us | 20 | 20 | 100.00 |
| V2 | read_write_overflow | flash_ctrl_oversize_error | 4.085m | 2.707ms | 5 | 5 | 100.00 |
| V2 | flash_ctrl_disable | flash_ctrl_disable | 23.200s | 38.608us | 50 | 50 | 100.00 |
| V2 | flash_ctrl_connect | flash_ctrl_connect | 16.530s | 40.725us | 80 | 80 | 100.00 |
| V2 | stress_all | flash_ctrl_stress_all | 23.721m | 1.931ms | 5 | 5 | 100.00 |
| V2 | secret_partition | flash_ctrl_hw_sec_otp | 4.656m | 23.293ms | 50 | 50 | 100.00 |
| flash_ctrl_otp_reset | 2.268m | 331.539us | 80 | 80 | 100.00 | ||
| V2 | isolation_partition | flash_ctrl_hw_rma | 47.461m | 1.015s | 3 | 3 | 100.00 |
| V2 | interrupts | flash_ctrl_intr_rd | 5.101m | 2.182ms | 39 | 40 | 97.50 |
| flash_ctrl_intr_wr | 1.256m | 2.924ms | 10 | 10 | 100.00 | ||
| flash_ctrl_intr_rd_slow_flash | 9.089m | 87.733ms | 40 | 40 | 100.00 | ||
| flash_ctrl_intr_wr_slow_flash | 6.104m | 406.178ms | 10 | 10 | 100.00 | ||
| V2 | invalid_op | flash_ctrl_invalid_op | 1.528m | 2.258ms | 20 | 20 | 100.00 |
| V2 | mid_op_rst | flash_ctrl_mid_op_rst | 1.431m | 17.933ms | 5 | 5 | 100.00 |
| V2 | double_bit_err | flash_ctrl_read_word_sweep_derr | 23.500s | 18.702us | 5 | 5 | 100.00 |
| flash_ctrl_ro_derr | 3.279m | 2.604ms | 10 | 10 | 100.00 | ||
| flash_ctrl_rw_derr | 4.763m | 2.844ms | 9 | 10 | 90.00 | ||
| flash_ctrl_derr_detect | 3.423m | 5.406ms | 5 | 5 | 100.00 | ||
| flash_ctrl_integrity | 12.149m | 11.509ms | 5 | 5 | 100.00 | ||
| V2 | single_bit_err | flash_ctrl_read_word_sweep_serr | 22.940s | 41.688us | 5 | 5 | 100.00 |
| flash_ctrl_ro_serr | 2.954m | 3.039ms | 10 | 10 | 100.00 | ||
| flash_ctrl_rw_serr | 4.781m | 37.754ms | 10 | 10 | 100.00 | ||
| V2 | singlebit_err_counter | flash_ctrl_serr_counter | 1.831m | 8.272ms | 5 | 5 | 100.00 |
| V2 | singlebit_err_address | flash_ctrl_serr_address | 1.810m | 11.594ms | 5 | 5 | 100.00 |
| V2 | scramble | flash_ctrl_wo | 4.553m | 6.232ms | 20 | 20 | 100.00 |
| flash_ctrl_write_word_sweep | 15.450s | 77.268us | 1 | 1 | 100.00 | ||
| flash_ctrl_read_word_sweep | 15.260s | 59.208us | 1 | 1 | 100.00 | ||
| flash_ctrl_ro | 2.515m | 564.348us | 20 | 20 | 100.00 | ||
| flash_ctrl_rw | 11.411m | 19.257ms | 19 | 20 | 95.00 | ||
| V2 | filesystem_support | flash_ctrl_fs_sup | 43.840s | 1.712ms | 4 | 5 | 80.00 |
| V2 | rma_write_process_error | flash_ctrl_rma_err | 23.946m | 98.374ms | 3 | 3 | 100.00 |
| flash_ctrl_hw_prog_rma_wipe_err | 5.591m | 10.013ms | 20 | 20 | 100.00 | ||
| V2 | alert_test | flash_ctrl_alert_test | 14.570s | 311.495us | 50 | 50 | 100.00 |
| V2 | intr_test | flash_ctrl_intr_test | 13.990s | 24.421us | 50 | 50 | 100.00 |
| V2 | tl_d_oob_addr_access | flash_ctrl_tl_errors | 21.020s | 238.925us | 20 | 20 | 100.00 |
| V2 | tl_d_illegal_access | flash_ctrl_tl_errors | 21.020s | 238.925us | 20 | 20 | 100.00 |
| V2 | tl_d_outstanding_access | flash_ctrl_csr_hw_reset | 45.580s | 27.299us | 5 | 5 | 100.00 |
| flash_ctrl_csr_rw | 17.980s | 212.114us | 20 | 20 | 100.00 | ||
| flash_ctrl_csr_aliasing | 55.780s | 2.011ms | 5 | 5 | 100.00 | ||
| flash_ctrl_same_csr_outstanding | 35.870s | 434.846us | 20 | 20 | 100.00 | ||
| V2 | tl_d_partial_access | flash_ctrl_csr_hw_reset | 45.580s | 27.299us | 5 | 5 | 100.00 |
| flash_ctrl_csr_rw | 17.980s | 212.114us | 20 | 20 | 100.00 | ||
| flash_ctrl_csr_aliasing | 55.780s | 2.011ms | 5 | 5 | 100.00 | ||
| flash_ctrl_same_csr_outstanding | 35.870s | 434.846us | 20 | 20 | 100.00 | ||
| V2 | TOTAL | 989 | 1013 | 97.63 | |||
| V2S | shadow_reg_update_error | flash_ctrl_shadow_reg_errors | 16.210s | 92.356us | 20 | 20 | 100.00 |
| V2S | shadow_reg_read_clear_staged_value | flash_ctrl_shadow_reg_errors | 16.210s | 92.356us | 20 | 20 | 100.00 |
| V2S | shadow_reg_storage_error | flash_ctrl_shadow_reg_errors | 16.210s | 92.356us | 20 | 20 | 100.00 |
| V2S | shadowed_reset_glitch | flash_ctrl_shadow_reg_errors | 16.210s | 92.356us | 20 | 20 | 100.00 |
| V2S | shadow_reg_update_error_with_csr_rw | flash_ctrl_shadow_reg_errors_with_csr_rw | 16.220s | 23.711us | 20 | 20 | 100.00 |
| V2S | tl_intg_err | flash_ctrl_sec_cm | 1.395h | 7.611ms | 5 | 5 | 100.00 |
| flash_ctrl_tl_intg_err | 15.239m | 1.290ms | 20 | 20 | 100.00 | ||
| V2S | sec_cm_reg_bus_integrity | flash_ctrl_tl_intg_err | 15.239m | 1.290ms | 20 | 20 | 100.00 |
| V2S | sec_cm_host_bus_integrity | flash_ctrl_tl_intg_err | 15.239m | 1.290ms | 20 | 20 | 100.00 |
| V2S | sec_cm_mem_bus_integrity | flash_ctrl_rd_intg | 32.930s | 65.078us | 3 | 3 | 100.00 |
| flash_ctrl_wr_intg | 15.220s | 85.369us | 3 | 3 | 100.00 | ||
| V2S | sec_cm_scramble_key_sideload | flash_ctrl_smoke | 3.305m | 51.434us | 50 | 50 | 100.00 |
| V2S | sec_cm_lc_ctrl_intersig_mubi | flash_ctrl_otp_reset | 2.268m | 331.539us | 80 | 80 | 100.00 |
| flash_ctrl_disable | 23.200s | 38.608us | 50 | 50 | 100.00 | ||
| flash_ctrl_sec_info_access | 1.636m | 14.274ms | 50 | 50 | 100.00 | ||
| flash_ctrl_connect | 16.530s | 40.725us | 80 | 80 | 100.00 | ||
| V2S | sec_cm_ctrl_config_regwen | flash_ctrl_config_regwen | 14.380s | 39.862us | 5 | 5 | 100.00 |
| V2S | sec_cm_data_regions_config_regwen | flash_ctrl_csr_rw | 17.980s | 212.114us | 20 | 20 | 100.00 |
| V2S | sec_cm_data_regions_config_shadow | flash_ctrl_shadow_reg_errors | 16.210s | 92.356us | 20 | 20 | 100.00 |
| V2S | sec_cm_info_regions_config_regwen | flash_ctrl_csr_rw | 17.980s | 212.114us | 20 | 20 | 100.00 |
| V2S | sec_cm_info_regions_config_shadow | flash_ctrl_shadow_reg_errors | 16.210s | 92.356us | 20 | 20 | 100.00 |
| V2S | sec_cm_bank_config_regwen | flash_ctrl_csr_rw | 17.980s | 212.114us | 20 | 20 | 100.00 |
| V2S | sec_cm_bank_config_shadow | flash_ctrl_shadow_reg_errors | 16.210s | 92.356us | 20 | 20 | 100.00 |
| V2S | sec_cm_mem_ctrl_global_esc | flash_ctrl_disable | 23.200s | 38.608us | 50 | 50 | 100.00 |
| V2S | sec_cm_mem_ctrl_local_esc | flash_ctrl_rd_intg | 32.930s | 65.078us | 3 | 3 | 100.00 |
| flash_ctrl_access_after_disable | 13.940s | 13.424us | 3 | 3 | 100.00 | ||
| V2S | sec_cm_mem_addr_infection | flash_ctrl_host_addr_infection | 30.810s | 35.464us | 3 | 3 | 100.00 |
| V2S | sec_cm_mem_disable_config_mubi | flash_ctrl_disable | 23.200s | 38.608us | 50 | 50 | 100.00 |
| V2S | sec_cm_exec_config_redun | flash_ctrl_fetch_code | 28.370s | 1.167ms | 10 | 10 | 100.00 |
| V2S | sec_cm_mem_scramble | flash_ctrl_rw | 11.411m | 19.257ms | 19 | 20 | 95.00 |
| V2S | sec_cm_mem_integrity | flash_ctrl_rw_serr | 4.781m | 37.754ms | 10 | 10 | 100.00 |
| flash_ctrl_rw_derr | 4.763m | 2.844ms | 9 | 10 | 90.00 | ||
| flash_ctrl_integrity | 12.149m | 11.509ms | 5 | 5 | 100.00 | ||
| V2S | sec_cm_rma_entry_mem_sec_wipe | flash_ctrl_hw_rma | 47.461m | 1.015s | 3 | 3 | 100.00 |
| V2S | sec_cm_ctrl_fsm_sparse | flash_ctrl_sec_cm | 1.395h | 7.611ms | 5 | 5 | 100.00 |
| V2S | sec_cm_phy_fsm_sparse | flash_ctrl_sec_cm | 1.395h | 7.611ms | 5 | 5 | 100.00 |
| V2S | sec_cm_phy_prog_fsm_sparse | flash_ctrl_sec_cm | 1.395h | 7.611ms | 5 | 5 | 100.00 |
| V2S | sec_cm_ctr_redun | flash_ctrl_sec_cm | 1.395h | 7.611ms | 5 | 5 | 100.00 |
| V2S | sec_cm_phy_arbiter_ctrl_redun | flash_ctrl_phy_arb_redun | 19.940s | 935.140us | 5 | 5 | 100.00 |
| V2S | sec_cm_phy_host_grant_ctrl_consistency | flash_ctrl_phy_host_grant_err | 14.530s | 43.854us | 5 | 5 | 100.00 |
| V2S | sec_cm_phy_ack_ctrl_consistency | flash_ctrl_phy_ack_consistency | 14.210s | 15.961us | 4 | 5 | 80.00 |
| V2S | sec_cm_fifo_ctr_redun | flash_ctrl_sec_cm | 1.395h | 7.611ms | 5 | 5 | 100.00 |
| V2S | sec_cm_mem_tl_lc_gate_fsm_sparse | flash_ctrl_sec_cm | 1.395h | 7.611ms | 5 | 5 | 100.00 |
| V2S | sec_cm_prog_tl_lc_gate_fsm_sparse | flash_ctrl_sec_cm | 1.395h | 7.611ms | 5 | 5 | 100.00 |
| V2S | TOTAL | 146 | 147 | 99.32 | |||
| V3 | asymmetric_read_path | flash_ctrl_rd_ooo | 44.810s | 154.148us | 1 | 1 | 100.00 |
| V3 | stress_all_with_rand_reset | flash_ctrl_stress_all_with_rand_reset | 0 | 0 | -- | ||
| V3 | TOTAL | 1 | 1 | 100.00 | |||
| TOTAL | 1256 | 1281 | 98.05 |
| Items | Total | Written | Passing | Progress |
|---|---|---|---|---|
| V1 | 9 | 9 | 9 | 100.00 |
| V2 | 55 | 55 | 48 | 87.27 |
| V2S | 13 | 13 | 12 | 92.31 |
| V3 | 2 | 1 | 1 | 50.00 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
|---|---|---|---|---|---|---|---|
| 96.27 | 95.73 | 93.96 | 98.31 | 92.52 | 98.25 | 96.89 | 98.21 |
UVM_ERROR (cip_base_scoreboard.sv:242) [scoreboard] Check failed expected_alert[alert_name].expected == * (* [*] vs * [*]) alert fatal_err triggered unexpectedly has 2 failures:
Test flash_ctrl_fs_sup has 1 failures.
2.flash_ctrl_fs_sup.13921966170093372430907909919725201141282809979936683647070487516443582074349
Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/2.flash_ctrl_fs_sup/latest/run.log
UVM_ERROR @ 784431.6 ns: (cip_base_scoreboard.sv:242) [uvm_test_top.env.scoreboard] Check failed expected_alert[alert_name].expected == 1 (0 [0x0] vs 1 [0x1]) alert fatal_err triggered unexpectedly
UVM_INFO @ 784431.6 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test flash_ctrl_rw has 1 failures.
16.flash_ctrl_rw.9911426492787835746098315947434743911141685463821361151973105702690489137041
Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/16.flash_ctrl_rw/latest/run.log
UVM_ERROR @ 3131341.0 ns: (cip_base_scoreboard.sv:242) [uvm_test_top.env.scoreboard] Check failed expected_alert[alert_name].expected == 1 (0 [0x0] vs 1 [0x1]) alert fatal_err triggered unexpectedly
UVM_INFO @ 3131341.0 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_scoreboard.sv:484) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface flash_ctrl_eflash_reg_block, TL item: req: (cip_tl_seq_item@154647) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_source_is_overridden: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:
1.flash_ctrl_rw_evict.35697993008479996853237345795673781531521483713192702365284851457659401791813
Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/1.flash_ctrl_rw_evict/latest/run.log
UVM_ERROR @ 42043.1 ns: (cip_base_scoreboard.sv:484) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (1 [0x1] vs 0 [0x0]) On interface flash_ctrl_eflash_reg_block, TL item: req: (cip_tl_seq_item@154647) { a_addr: 'h3ae60 a_data: 'h0 a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'hfb a_opcode: 'h4 a_user: 'h258aa d_param: 'h0 d_source: 'hfb d_data: 'hffffffff d_size: 'h2 d_opcode: 'h1 d_error: 'h1 d_sink: 'h0 d_user: 'heaa a_source_is_overridden: 'h0 a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
, unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
UVM_INFO @ 42043.1 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_tl_seq_item.sv:223) [req] d_user.data_intg act (*) != exp (*) has 1 failures:
2.flash_ctrl_phy_ack_consistency.79807403130308359817744001275330057742284320737534678458366887668654824933037
Line 284, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/2.flash_ctrl_phy_ack_consistency/latest/run.log
UVM_ERROR @ 19970.7 ns: (cip_tl_seq_item.sv:223) [req] d_user.data_intg act (0x2a) != exp (0x6f)
UVM_INFO @ 19970.7 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (flash_ctrl_otf_scoreboard.sv:289) m_otf_scb [process_read] unexpected double bit error * has 1 failures:
4.flash_ctrl_rw_derr.84900800277726631734695721399846081756632283333677890893340690169739381950747
Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/4.flash_ctrl_rw_derr/latest/run.log
UVM_ERROR @ 534631.2 ns: (flash_ctrl_otf_scoreboard.sv:289) uvm_test_top.env.m_otf_scb [process_read] unexpected double bit error 0x00003a00
UVM_INFO @ 534631.2 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (csr_utils_pkg.sv:476) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: flash_ctrl_core_reg_block.op_status.err reset value: * has 1 failures:
4.flash_ctrl_rw_evict.110341765895825757795371626248534185892501611649773347560439032050575357821690
Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/4.flash_ctrl_rw_evict/latest/run.log
UVM_ERROR @ 16945.2 ns: (csr_utils_pkg.sv:476) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: flash_ctrl_core_reg_block.op_status.err reset value: 0x0
UVM_INFO @ 16945.2 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_scoreboard.sv:484) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface flash_ctrl_eflash_reg_block, TL item: req: (cip_tl_seq_item@152084) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_source_is_overridden: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:
4.flash_ctrl_rw_evict_all_en.92791908022837126810782203449981319931681049710405538676207833403412805455402
Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/4.flash_ctrl_rw_evict_all_en/latest/run.log
UVM_ERROR @ 7794.7 ns: (cip_base_scoreboard.sv:484) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (1 [0x1] vs 0 [0x0]) On interface flash_ctrl_eflash_reg_block, TL item: req: (cip_tl_seq_item@152084) { a_addr: 'h51b68 a_data: 'h0 a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h9b a_opcode: 'h4 a_user: 'h2662a d_param: 'h0 d_source: 'h9b d_data: 'hffffffff d_size: 'h2 d_opcode: 'h1 d_error: 'h1 d_sink: 'h0 d_user: 'heaa a_source_is_overridden: 'h0 a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
, unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
UVM_INFO @ 7794.7 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (csr_utils_pkg.sv:476) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: flash_ctrl_core_reg_block.std_fault_status.lcmgr_intg_err reset value: * has 1 failures:
6.flash_ctrl_lcmgr_intg.14621971062600264653881615958757340708435423564855708013811125021437407247377
Line 285, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/6.flash_ctrl_lcmgr_intg/latest/run.log
UVM_ERROR @ 27499.0 ns: (csr_utils_pkg.sv:476) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: flash_ctrl_core_reg_block.std_fault_status.lcmgr_intg_err reset value: 0x0
UVM_INFO @ 27499.0 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_scoreboard.sv:484) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface flash_ctrl_eflash_reg_block, TL item: req: (cip_tl_seq_item@156812) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_source_is_overridden: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:
7.flash_ctrl_rw_evict.97826506361320380981902645144229303622493404060239000740897680963904792833826
Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/7.flash_ctrl_rw_evict/latest/run.log
UVM_ERROR @ 21807.3 ns: (cip_base_scoreboard.sv:484) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (1 [0x1] vs 0 [0x0]) On interface flash_ctrl_eflash_reg_block, TL item: req: (cip_tl_seq_item@156812) { a_addr: 'h9e6e0 a_data: 'h0 a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'he7 a_opcode: 'h4 a_user: 'h2492a d_param: 'h0 d_source: 'he7 d_data: 'hffffffff d_size: 'h2 d_opcode: 'h1 d_error: 'h1 d_sink: 'h0 d_user: 'heaa a_source_is_overridden: 'h0 a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
, unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
UVM_INFO @ 21807.3 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_scoreboard.sv:484) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface flash_ctrl_eflash_reg_block, TL item: req: (cip_tl_seq_item@153265) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_source_is_overridden: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:
7.flash_ctrl_rw_evict_all_en.5154773845487887100428310859516579964717788540557409207633374353642261720142
Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/7.flash_ctrl_rw_evict_all_en/latest/run.log
UVM_ERROR @ 34742.6 ns: (cip_base_scoreboard.sv:484) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (1 [0x1] vs 0 [0x0]) On interface flash_ctrl_eflash_reg_block, TL item: req: (cip_tl_seq_item@153265) { a_addr: 'h16020 a_data: 'h0 a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'hc1 a_opcode: 'h4 a_user: 'h2462a d_param: 'h0 d_source: 'hc1 d_data: 'hffffffff d_size: 'h2 d_opcode: 'h1 d_error: 'h1 d_sink: 'h0 d_user: 'heaa a_source_is_overridden: 'h0 a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
, unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
UVM_INFO @ 34742.6 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_scoreboard.sv:484) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface flash_ctrl_eflash_reg_block, TL item: req: (cip_tl_seq_item@161777) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_source_is_overridden: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:
10.flash_ctrl_rw_evict.68070392727110968690694699776319557766964501901393211413078838678949181787725
Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/10.flash_ctrl_rw_evict/latest/run.log
UVM_ERROR @ 60937.6 ns: (cip_base_scoreboard.sv:484) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (1 [0x1] vs 0 [0x0]) On interface flash_ctrl_eflash_reg_block, TL item: req: (cip_tl_seq_item@161777) { a_addr: 'h39708 a_data: 'h0 a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'he5 a_opcode: 'h4 a_user: 'h2402a d_param: 'h0 d_source: 'he5 d_data: 'hffffffff d_size: 'h2 d_opcode: 'h1 d_error: 'h1 d_sink: 'h0 d_user: 'heaa a_source_is_overridden: 'h0 a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
, unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
UVM_INFO @ 60937.6 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_scoreboard.sv:484) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface flash_ctrl_eflash_reg_block, TL item: req: (cip_tl_seq_item@155514) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_source_is_overridden: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:
14.flash_ctrl_rw_evict.60926943874255017557991935687849854337964444222186911890009298785381623835520
Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/14.flash_ctrl_rw_evict/latest/run.log
UVM_ERROR @ 11068.1 ns: (cip_base_scoreboard.sv:484) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (1 [0x1] vs 0 [0x0]) On interface flash_ctrl_eflash_reg_block, TL item: req: (cip_tl_seq_item@155514) { a_addr: 'h3ae0 a_data: 'h0 a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h95 a_opcode: 'h4 a_user: 'h2772a d_param: 'h0 d_source: 'h95 d_data: 'hffffffff d_size: 'h2 d_opcode: 'h1 d_error: 'h1 d_sink: 'h0 d_user: 'heaa a_source_is_overridden: 'h0 a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
, unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
UVM_INFO @ 11068.1 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_scoreboard.sv:484) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface flash_ctrl_eflash_reg_block, TL item: req: (cip_tl_seq_item@157150) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_source_is_overridden: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:
19.flash_ctrl_rw_evict.59303130916487420674825527449994013753094164724070021796793478274633877295950
Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/19.flash_ctrl_rw_evict/latest/run.log
UVM_ERROR @ 17987.5 ns: (cip_base_scoreboard.sv:484) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (1 [0x1] vs 0 [0x0]) On interface flash_ctrl_eflash_reg_block, TL item: req: (cip_tl_seq_item@157150) { a_addr: 'h54128 a_data: 'h0 a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'hd3 a_opcode: 'h4 a_user: 'h24eaa d_param: 'h0 d_source: 'hd3 d_data: 'hffffffff d_size: 'h2 d_opcode: 'h1 d_error: 'h1 d_sink: 'h0 d_user: 'heaa a_source_is_overridden: 'h0 a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
, unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
UVM_INFO @ 17987.5 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_scoreboard.sv:484) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface flash_ctrl_eflash_reg_block, TL item: req: (cip_tl_seq_item@159546) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_source_is_overridden: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:
20.flash_ctrl_rw_evict.87131035002921100620454668868160608727888016320175923041572421332307886162185
Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/20.flash_ctrl_rw_evict/latest/run.log
UVM_ERROR @ 18423.8 ns: (cip_base_scoreboard.sv:484) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (1 [0x1] vs 0 [0x0]) On interface flash_ctrl_eflash_reg_block, TL item: req: (cip_tl_seq_item@159546) { a_addr: 'hecb08 a_data: 'h0 a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'hde a_opcode: 'h4 a_user: 'h2692a d_param: 'h0 d_source: 'hde d_data: 'hffffffff d_size: 'h2 d_opcode: 'h1 d_error: 'h1 d_sink: 'h0 d_user: 'heaa a_source_is_overridden: 'h0 a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
, unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
UVM_INFO @ 18423.8 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_scoreboard.sv:484) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface flash_ctrl_eflash_reg_block, TL item: req: (cip_tl_seq_item@153777) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_source_is_overridden: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:
23.flash_ctrl_rw_evict.82832926767047482092014379390066774270646486377191555513026527222633178381146
Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/23.flash_ctrl_rw_evict/latest/run.log
UVM_ERROR @ 28056.5 ns: (cip_base_scoreboard.sv:484) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (1 [0x1] vs 0 [0x0]) On interface flash_ctrl_eflash_reg_block, TL item: req: (cip_tl_seq_item@153777) { a_addr: 'h63160 a_data: 'h0 a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h51 a_opcode: 'h4 a_user: 'h257aa d_param: 'h0 d_source: 'h51 d_data: 'hffffffff d_size: 'h2 d_opcode: 'h1 d_error: 'h1 d_sink: 'h0 d_user: 'heaa a_source_is_overridden: 'h0 a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
, unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
UVM_INFO @ 28056.5 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_scoreboard.sv:484) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface flash_ctrl_eflash_reg_block, TL item: req: (cip_tl_seq_item@153863) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_source_is_overridden: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:
23.flash_ctrl_rw_evict_all_en.13097039879701557414728393321507377623532643276802378160773357279808191638574
Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/23.flash_ctrl_rw_evict_all_en/latest/run.log
UVM_ERROR @ 49689.6 ns: (cip_base_scoreboard.sv:484) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (1 [0x1] vs 0 [0x0]) On interface flash_ctrl_eflash_reg_block, TL item: req: (cip_tl_seq_item@153863) { a_addr: 'hebb88 a_data: 'h0 a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h7f a_opcode: 'h4 a_user: 'h264aa d_param: 'h0 d_source: 'h7f d_data: 'hffffffff d_size: 'h2 d_opcode: 'h1 d_error: 'h1 d_sink: 'h0 d_user: 'heaa a_source_is_overridden: 'h0 a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
, unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
UVM_INFO @ 49689.6 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_scoreboard.sv:484) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface flash_ctrl_eflash_reg_block, TL item: req: (cip_tl_seq_item@155778) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_source_is_overridden: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:
24.flash_ctrl_rw_evict_all_en.108756520636052314096578568640283459635898386166650029337228300952848382727513
Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/24.flash_ctrl_rw_evict_all_en/latest/run.log
UVM_ERROR @ 21488.2 ns: (cip_base_scoreboard.sv:484) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (1 [0x1] vs 0 [0x0]) On interface flash_ctrl_eflash_reg_block, TL item: req: (cip_tl_seq_item@155778) { a_addr: 'h920a8 a_data: 'h0 a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'hcb a_opcode: 'h4 a_user: 'h2512a d_param: 'h0 d_source: 'hcb d_data: 'hffffffff d_size: 'h2 d_opcode: 'h1 d_error: 'h1 d_sink: 'h0 d_user: 'heaa a_source_is_overridden: 'h0 a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
, unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
UVM_INFO @ 21488.2 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_scoreboard.sv:484) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface flash_ctrl_eflash_reg_block, TL item: req: (cip_tl_seq_item@154159) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_source_is_overridden: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:
25.flash_ctrl_rw_evict.58129503992379478035976012968087835181470931594981480834878893883535722002480
Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/25.flash_ctrl_rw_evict/latest/run.log
UVM_ERROR @ 9683.6 ns: (cip_base_scoreboard.sv:484) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (1 [0x1] vs 0 [0x0]) On interface flash_ctrl_eflash_reg_block, TL item: req: (cip_tl_seq_item@154159) { a_addr: 'h2d000 a_data: 'h0 a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h55 a_opcode: 'h4 a_user: 'h247aa d_param: 'h0 d_source: 'h55 d_data: 'hffffffff d_size: 'h2 d_opcode: 'h1 d_error: 'h1 d_sink: 'h0 d_user: 'heaa a_source_is_overridden: 'h0 a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
, unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
UVM_INFO @ 9683.6 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_scoreboard.sv:484) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface flash_ctrl_eflash_reg_block, TL item: req: (cip_tl_seq_item@154105) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_source_is_overridden: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:
29.flash_ctrl_rw_evict.62243899474089519657737300681427126254260836018764748654717333184809559117378
Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/29.flash_ctrl_rw_evict/latest/run.log
UVM_ERROR @ 32211.1 ns: (cip_base_scoreboard.sv:484) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (1 [0x1] vs 0 [0x0]) On interface flash_ctrl_eflash_reg_block, TL item: req: (cip_tl_seq_item@154105) { a_addr: 'h46590 a_data: 'h0 a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h4a a_opcode: 'h4 a_user: 'h279aa d_param: 'h0 d_source: 'h4a d_data: 'hffffffff d_size: 'h2 d_opcode: 'h1 d_error: 'h1 d_sink: 'h0 d_user: 'heaa a_source_is_overridden: 'h0 a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
, unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
UVM_INFO @ 32211.1 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (flash_ctrl_otf_scoreboard.sv:375) [rdata_comp_bank1] *: obs:exp d7f89451_6fd87845:ffffffff_6fd* mismatch!! has 1 failures:
33.flash_ctrl_intr_rd.97683038353563440505195567588736597161749255236715654163766892972861178839309
Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/33.flash_ctrl_intr_rd/latest/run.log
UVM_ERROR @ 77223.0 ns: (flash_ctrl_otf_scoreboard.sv:375) [rdata_comp_bank1] 7: obs:exp d7f89451_6fd87845:ffffffff_6fd87845 mismatch!!
UVM_INFO @ 77223.0 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_scoreboard.sv:484) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface flash_ctrl_eflash_reg_block, TL item: req: (cip_tl_seq_item@153698) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_source_is_overridden: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:
33.flash_ctrl_rw_evict.49549900606828129078585503223055209164633622341350359975760552789727428610647
Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/33.flash_ctrl_rw_evict/latest/run.log
UVM_ERROR @ 76813.7 ns: (cip_base_scoreboard.sv:484) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (1 [0x1] vs 0 [0x0]) On interface flash_ctrl_eflash_reg_block, TL item: req: (cip_tl_seq_item@153698) { a_addr: 'h15368 a_data: 'h0 a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'hd7 a_opcode: 'h4 a_user: 'h26e2a d_param: 'h0 d_source: 'hd7 d_data: 'hffffffff d_size: 'h2 d_opcode: 'h1 d_error: 'h1 d_sink: 'h0 d_user: 'heaa a_source_is_overridden: 'h0 a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
, unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
UVM_INFO @ 76813.7 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_scoreboard.sv:484) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface flash_ctrl_eflash_reg_block, TL item: req: (cip_tl_seq_item@152724) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_source_is_overridden: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:
35.flash_ctrl_rw_evict_all_en.32756321590126853124428227060624232719014999146418549342228049356808024825888
Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/35.flash_ctrl_rw_evict_all_en/latest/run.log
UVM_ERROR @ 16327.6 ns: (cip_base_scoreboard.sv:484) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (1 [0x1] vs 0 [0x0]) On interface flash_ctrl_eflash_reg_block, TL item: req: (cip_tl_seq_item@152724) { a_addr: 'hb27d0 a_data: 'h0 a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h89 a_opcode: 'h4 a_user: 'h27f2a d_param: 'h0 d_source: 'h89 d_data: 'hffffffff d_size: 'h2 d_opcode: 'h1 d_error: 'h1 d_sink: 'h0 d_user: 'heaa a_source_is_overridden: 'h0 a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
, unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
UVM_INFO @ 16327.6 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_scoreboard.sv:484) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface flash_ctrl_eflash_reg_block, TL item: req: (cip_tl_seq_item@158963) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_source_is_overridden: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:
36.flash_ctrl_rw_evict.90384875028137108263165407246714679526032405429789321428580124177910991306099
Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/36.flash_ctrl_rw_evict/latest/run.log
UVM_ERROR @ 25876.1 ns: (cip_base_scoreboard.sv:484) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (1 [0x1] vs 0 [0x0]) On interface flash_ctrl_eflash_reg_block, TL item: req: (cip_tl_seq_item@158963) { a_addr: 'h622f0 a_data: 'h0 a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h5c a_opcode: 'h4 a_user: 'h242aa d_param: 'h0 d_source: 'h5c d_data: 'hffffffff d_size: 'h2 d_opcode: 'h1 d_error: 'h1 d_sink: 'h0 d_user: 'heaa a_source_is_overridden: 'h0 a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
, unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
UVM_INFO @ 25876.1 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_scoreboard.sv:484) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface flash_ctrl_eflash_reg_block, TL item: req: (cip_tl_seq_item@154952) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_source_is_overridden: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:
36.flash_ctrl_rw_evict_all_en.3377188739883885659876480267883927712280098129326442160288579066622860568460
Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/36.flash_ctrl_rw_evict_all_en/latest/run.log
UVM_ERROR @ 9779.1 ns: (cip_base_scoreboard.sv:484) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (1 [0x1] vs 0 [0x0]) On interface flash_ctrl_eflash_reg_block, TL item: req: (cip_tl_seq_item@154952) { a_addr: 'h4c3d8 a_data: 'h0 a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h93 a_opcode: 'h4 a_user: 'h251aa d_param: 'h0 d_source: 'h93 d_data: 'hffffffff d_size: 'h2 d_opcode: 'h1 d_error: 'h1 d_sink: 'h0 d_user: 'heaa a_source_is_overridden: 'h0 a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
, unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
UVM_INFO @ 9779.1 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_scoreboard.sv:484) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface flash_ctrl_eflash_reg_block, TL item: req: (cip_tl_seq_item@153598) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_source_is_overridden: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:
38.flash_ctrl_rw_evict_all_en.27881237849426648661706470843212155124555354949345979757750100903254052976863
Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/38.flash_ctrl_rw_evict_all_en/latest/run.log
UVM_ERROR @ 35279.5 ns: (cip_base_scoreboard.sv:484) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (1 [0x1] vs 0 [0x0]) On interface flash_ctrl_eflash_reg_block, TL item: req: (cip_tl_seq_item@153598) { a_addr: 'h3400 a_data: 'h0 a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h78 a_opcode: 'h4 a_user: 'h24caa d_param: 'h0 d_source: 'h78 d_data: 'hffffffff d_size: 'h2 d_opcode: 'h1 d_error: 'h1 d_sink: 'h0 d_user: 'heaa a_source_is_overridden: 'h0 a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
, unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
UVM_INFO @ 35279.5 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---