Unified Coverage Report :: Module :: prim_arbiter_fixed

Module : prim_arbiter_fixed

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb	96.88	87.50	100.00			100.00	100.00
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb	96.88	87.50	100.00			100.00	100.00
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb	96.88	87.50	100.00			100.00	100.00
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb	96.88	87.50	100.00			100.00	100.00

---

Module Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
76.67	90.00	40.00			100.00		u_host_arb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
76.67	90.00	40.00			100.00		u_host_arb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.67	90.00	100.00			100.00		u_host_arb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.67	90.00	100.00			100.00		u_host_arb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : prim_arbiter_fixed

	Line No.	Total	Covered	Percent
TOTAL		16	14	87.50
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
ALWAYS	105	6	6	100.00
CONT_ASSIGN	124	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	132	1	1	100.00

84                                  // forward path
85         2/2                      assign req_tree[Pa]      = req_i[offset];
           Tests:       T1 T2 T13  | T1 T2 T3 
86                                  assign idx_tree[Pa]      = offset;
87         0/2     ==>              assign data_tree[Pa]     = data_i[offset];
88                                  // backward (grant) path
89         2/2                      assign gnt_o[offset]     = gnt_tree[Pa];
           Tests:       T1 T2 T13  | T1 T2 T3 
90                      
91                                end else begin : gen_tie_off
92                                  // forward path
93                                  assign req_tree[Pa]  = '0;
94                                  assign idx_tree[Pa]  = '0;
95                                  assign data_tree[Pa] = '0;
96                                  logic unused_sigs;
97                                  assign unused_sigs = gnt_tree[Pa];
98                                end
99                              // this creates the node assignments
100                             end else begin : gen_nodes
101                               // forward path
102                               logic sel; // local helper variable
103                               always_comb begin : p_node
104                                 // this always gives priority to the left child
105        1/1                      sel = ~req_tree[C0];
           Tests:       T1 T2 T3 
106                                 // propagate requests
107        1/1                      req_tree[Pa]  = req_tree[C0] | req_tree[C1];
           Tests:       T1 T2 T3 
108                                 // data and index muxes
109        1/1                      idx_tree[Pa]  = (sel) ? idx_tree[C1]  : idx_tree[C0];
           Tests:       T1 T2 T3 
110        1/1                      data_tree[Pa] = (sel) ? data_tree[C1] : data_tree[C0];
           Tests:       T1 T2 T3 
111                                 // propagate the grants back to the input
112        1/1                      gnt_tree[C0] = gnt_tree[Pa] & ~sel;
           Tests:       T1 T2 T3 
113        1/1                      gnt_tree[C1] = gnt_tree[Pa] &  sel;
           Tests:       T1 T2 T3 
114                               end
115                             end
116                           end : gen_level
117                         end : gen_tree
118                     
119                         // the results can be found at the tree root
120                         if (EnDataPort) begin : gen_data_port
121                           assign data_o      = data_tree[0];
122                         end else begin : gen_no_dataport
123                           logic [DW-1:0] unused_data;
124        1/1                assign unused_data = data_tree[0];
           Tests:       T1 T2 T13 
125                           assign data_o = '1;
126                         end
127                     
128        1/1              assign idx_o       = idx_tree[0];
           Tests:       T1 T2 T13 
129        1/1              assign valid_o     = req_tree[0];
           Tests:       T1 T2 T3 
130                     
131                         // this propagates a grant back to the input
132        1/1              assign gnt_tree[0] = valid_o & ready_i;
           Tests:       T1 T2 T3 

---

Cond Coverage for Module : prim_arbiter_fixed

	Total	Covered	Percent
Conditions	16	16	100.00
Logical	16	16	100.00
Non-Logical	0	0
Event	0	0

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T13,T14

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T1,T13,T14
1	Covered	T1,T2,T3

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T1,T13,T14
1	Covered	T1,T2,T3

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Covered	T13,T14,T15
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T13,T14

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T13,T14
1	1	Covered	T1,T2,T3

 LINE       132
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T13,T14,T15
1	1	Covered	T1,T2,T3

---

Branch Coverage for Module : prim_arbiter_fixed

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00

109                    idx_tree[Pa]  = (sel) ? idx_tree[C1]  : idx_tree[C0];
                                             -1-  
                                             ==>  
                                             ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T13,T14

110                    data_tree[Pa] = (sel) ? data_tree[C1] : data_tree[C0];
                                             -1-  
                                             ==>  
                                             ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T13,T14

---

Assert Coverage for Module : prim_arbiter_fixed

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	13	13	100.00	13	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	13	13	100.00	13	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	1539457676	1536123268	0	0
CheckNGreaterZero_A	4168	4168	0	0
GntImpliesReady_A	1539457676	400726312	0	0
GntImpliesValid_A	1539457676	400726312	0	0
GrantKnown_A	1539457676	1536123268	0	0
IdxKnown_A	1539457676	1536123268	0	0
IndexIsCorrect_A	1539457676	400726312	0	0
NoReadyValidNoGrant_A	1539457676	168401136	0	0
Priority_A	1539457676	424851766	0	0
ReadyAndValidImplyGrant_A	1539457676	400726312	0	0
ReqAndReadyImplyGrant_A	1539457676	400726312	0	0
ReqImpliesValid_A	1539457676	424851766	0	0
ValidKnown_A	1539457676	1536123268	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1539457676	1536123268	0	0
T1	6544	6248	0	0
T2	7804	7504	0	0
T3	13528	13240	0	0
T7	16984	14376	0	0
T13	94840	94560	0	0
T14	24984	24592	0	0
T15	13660	13428	0	0
T18	11784	11448	0	0
T19	1943644	1871484	0	0
T20	281432	281124	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	4168	4168	0	0
T1	4	4	0	0
T2	4	4	0	0
T3	4	4	0	0
T7	4	4	0	0
T13	4	4	0	0
T14	4	4	0	0
T15	4	4	0	0
T18	4	4	0	0
T19	4	4	0	0
T20	4	4	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1539457676	400726312	0	0
T1	3272	84	0	0
T2	3902	1162	0	0
T3	13528	906	0	0
T7	16984	400	0	0
T13	94840	1406	0	0
T14	24984	7162	0	0
T15	13660	2628	0	0
T18	11784	902	0	0
T19	1943644	311172	0	0
T20	281432	136042	0	0
T48	0	74836	0	0
T49	0	19580	0	0
T52	0	21402	0	0
T65	3870	292	0	0
T66	7240	4366	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1539457676	400726312	0	0
T1	3272	84	0	0
T2	3902	1162	0	0
T3	13528	906	0	0
T7	16984	400	0	0
T13	94840	1406	0	0
T14	24984	7162	0	0
T15	13660	2628	0	0
T18	11784	902	0	0
T19	1943644	311172	0	0
T20	281432	136042	0	0
T48	0	74836	0	0
T49	0	19580	0	0
T52	0	21402	0	0
T65	3870	292	0	0
T66	7240	4366	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1539457676	1536123268	0	0
T1	6544	6248	0	0
T2	7804	7504	0	0
T3	13528	13240	0	0
T7	16984	14376	0	0
T13	94840	94560	0	0
T14	24984	24592	0	0
T15	13660	13428	0	0
T18	11784	11448	0	0
T19	1943644	1871484	0	0
T20	281432	281124	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1539457676	1536123268	0	0
T1	6544	6248	0	0
T2	7804	7504	0	0
T3	13528	13240	0	0
T7	16984	14376	0	0
T13	94840	94560	0	0
T14	24984	24592	0	0
T15	13660	13428	0	0
T18	11784	11448	0	0
T19	1943644	1871484	0	0
T20	281432	281124	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1539457676	400726312	0	0
T1	3272	84	0	0
T2	3902	1162	0	0
T3	13528	906	0	0
T7	16984	400	0	0
T13	94840	1406	0	0
T14	24984	7162	0	0
T15	13660	2628	0	0
T18	11784	902	0	0
T19	1943644	311172	0	0
T20	281432	136042	0	0
T48	0	74836	0	0
T49	0	19580	0	0
T52	0	21402	0	0
T65	3870	292	0	0
T66	7240	4366	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1539457676	168401136	0	0
T1	3272	286	0	0
T2	3902	316	0	0
T3	13528	406	0	0
T7	16984	1408	0	0
T13	94840	2294	0	0
T14	24984	822	0	0
T15	13660	1090	0	0
T18	11784	330	0	0
T19	1943644	89472	0	0
T20	281432	840	0	0
T32	0	3322	0	0
T41	0	58140	0	0
T48	0	4452	0	0
T49	0	88	0	0
T52	0	27670	0	0
T65	3870	400	0	0
T66	7240	0	0	0

Priority_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1539457676	424851766	0	0
T1	3272	84	0	0
T2	3902	1162	0	0
T3	13528	906	0	0
T7	16984	400	0	0
T13	94840	1410	0	0
T14	24984	7182	0	0
T15	13660	2840	0	0
T18	11784	902	0	0
T19	1943644	311172	0	0
T20	281432	136042	0	0
T48	0	74836	0	0
T49	0	19580	0	0
T52	0	33862	0	0
T65	3870	292	0	0
T66	7240	4366	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1539457676	400726312	0	0
T1	3272	84	0	0
T2	3902	1162	0	0
T3	13528	906	0	0
T7	16984	400	0	0
T13	94840	1406	0	0
T14	24984	7162	0	0
T15	13660	2628	0	0
T18	11784	902	0	0
T19	1943644	311172	0	0
T20	281432	136042	0	0
T48	0	74836	0	0
T49	0	19580	0	0
T52	0	21402	0	0
T65	3870	292	0	0
T66	7240	4366	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1539457676	400726312	0	0
T1	3272	84	0	0
T2	3902	1162	0	0
T3	13528	906	0	0
T7	16984	400	0	0
T13	94840	1406	0	0
T14	24984	7162	0	0
T15	13660	2628	0	0
T18	11784	902	0	0
T19	1943644	311172	0	0
T20	281432	136042	0	0
T48	0	74836	0	0
T49	0	19580	0	0
T52	0	21402	0	0
T65	3870	292	0	0
T66	7240	4366	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1539457676	424851766	0	0
T1	3272	84	0	0
T2	3902	1162	0	0
T3	13528	906	0	0
T7	16984	400	0	0
T13	94840	1410	0	0
T14	24984	7182	0	0
T15	13660	2840	0	0
T18	11784	902	0	0
T19	1943644	311172	0	0
T20	281432	136042	0	0
T48	0	74836	0	0
T49	0	19580	0	0
T52	0	33862	0	0
T65	3870	292	0	0
T66	7240	4366	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1539457676	1536123268	0	0
T1	6544	6248	0	0
T2	7804	7504	0	0
T3	13528	13240	0	0
T7	16984	14376	0	0
T13	94840	94560	0	0
T14	24984	24592	0	0
T15	13660	13428	0	0
T18	11784	11448	0	0
T19	1943644	1871484	0	0
T20	281432	281124	0	0

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
TOTAL		16	14	87.50
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
ALWAYS	105	6	6	100.00
CONT_ASSIGN	124	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	132	1	1	100.00

84                                  // forward path
85         2/2                      assign req_tree[Pa]      = req_i[offset];
           Tests:       T1 T2 T13  | T1 T2 T3 
86                                  assign idx_tree[Pa]      = offset;
87         0/2     ==>              assign data_tree[Pa]     = data_i[offset];
88                                  // backward (grant) path
89         2/2                      assign gnt_o[offset]     = gnt_tree[Pa];
           Tests:       T1 T2 T13  | T1 T2 T3 
90                      
91                                end else begin : gen_tie_off
92                                  // forward path
93                                  assign req_tree[Pa]  = '0;
94                                  assign idx_tree[Pa]  = '0;
95                                  assign data_tree[Pa] = '0;
96                                  logic unused_sigs;
97                                  assign unused_sigs = gnt_tree[Pa];
98                                end
99                              // this creates the node assignments
100                             end else begin : gen_nodes
101                               // forward path
102                               logic sel; // local helper variable
103                               always_comb begin : p_node
104                                 // this always gives priority to the left child
105        1/1                      sel = ~req_tree[C0];
           Tests:       T1 T2 T3 
106                                 // propagate requests
107        1/1                      req_tree[Pa]  = req_tree[C0] | req_tree[C1];
           Tests:       T1 T2 T3 
108                                 // data and index muxes
109        1/1                      idx_tree[Pa]  = (sel) ? idx_tree[C1]  : idx_tree[C0];
           Tests:       T1 T2 T3 
110        1/1                      data_tree[Pa] = (sel) ? data_tree[C1] : data_tree[C0];
           Tests:       T1 T2 T3 
111                                 // propagate the grants back to the input
112        1/1                      gnt_tree[C0] = gnt_tree[Pa] & ~sel;
           Tests:       T1 T2 T3 
113        1/1                      gnt_tree[C1] = gnt_tree[Pa] &  sel;
           Tests:       T1 T2 T3 
114                               end
115                             end
116                           end : gen_level
117                         end : gen_tree
118                     
119                         // the results can be found at the tree root
120                         if (EnDataPort) begin : gen_data_port
121                           assign data_o      = data_tree[0];
122                         end else begin : gen_no_dataport
123                           logic [DW-1:0] unused_data;
124        1/1                assign unused_data = data_tree[0];
           Tests:       T1 T2 T13 
125                           assign data_o = '1;
126                         end
127                     
128        1/1              assign idx_o       = idx_tree[0];
           Tests:       T1 T2 T13 
129        1/1              assign valid_o     = req_tree[0];
           Tests:       T1 T2 T3 
130                     
131                         // this propagates a grant back to the input
132        1/1              assign gnt_tree[0] = valid_o & ready_i;
           Tests:       T1 T2 T3 

---

Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Total	Covered	Percent
Conditions	16	16	100.00
Logical	16	16	100.00
Non-Logical	0	0
Event	0	0

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T13,T14

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T1,T13,T14
1	Covered	T1,T2,T3

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T1,T13,T14
1	Covered	T1,T2,T3

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Covered	T13,T14,T15
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T13,T14

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T13,T14
1	1	Covered	T1,T2,T3

 LINE       132
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T13,T14,T15
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00

109                    idx_tree[Pa]  = (sel) ? idx_tree[C1]  : idx_tree[C0];
                                             -1-  
                                             ==>  
                                             ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T13,T14

110                    data_tree[Pa] = (sel) ? data_tree[C1] : data_tree[C0];
                                             -1-  
                                             ==>  
                                             ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T13,T14

---

Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	13	13	100.00	13	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	13	13	100.00	13	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	384864419	384030817	0	0
CheckNGreaterZero_A	1042	1042	0	0
GntImpliesReady_A	384864419	102293044	0	0
GntImpliesValid_A	384864419	102293044	0	0
GrantKnown_A	384864419	384030817	0	0
IdxKnown_A	384864419	384030817	0	0
IndexIsCorrect_A	384864419	102293044	0	0
NoReadyValidNoGrant_A	384864419	43333530	0	0
Priority_A	384864419	108403792	0	0
ReadyAndValidImplyGrant_A	384864419	102293044	0	0
ReqAndReadyImplyGrant_A	384864419	102293044	0	0
ReqImpliesValid_A	384864419	108403792	0	0
ValidKnown_A	384864419	384030817	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	384864419	384030817	0	0
T1	1636	1562	0	0
T2	1951	1876	0	0
T3	3382	3310	0	0
T7	4246	3594	0	0
T13	23710	23640	0	0
T14	6246	6148	0	0
T15	3415	3357	0	0
T18	2946	2862	0	0
T19	485911	467871	0	0
T20	70358	70281	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1042	1042	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	384864419	102293044	0	0
T1	1636	42	0	0
T2	1951	581	0	0
T3	3382	441	0	0
T7	4246	200	0	0
T13	23710	280	0	0
T14	6246	2017	0	0
T15	3415	960	0	0
T18	2946	56	0	0
T19	485911	155586	0	0
T20	70358	68021	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	384864419	102293044	0	0
T1	1636	42	0	0
T2	1951	581	0	0
T3	3382	441	0	0
T7	4246	200	0	0
T13	23710	280	0	0
T14	6246	2017	0	0
T15	3415	960	0	0
T18	2946	56	0	0
T19	485911	155586	0	0
T20	70358	68021	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	384864419	384030817	0	0
T1	1636	1562	0	0
T2	1951	1876	0	0
T3	3382	3310	0	0
T7	4246	3594	0	0
T13	23710	23640	0	0
T14	6246	6148	0	0
T15	3415	3357	0	0
T18	2946	2862	0	0
T19	485911	467871	0	0
T20	70358	70281	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	384864419	384030817	0	0
T1	1636	1562	0	0
T2	1951	1876	0	0
T3	3382	3310	0	0
T7	4246	3594	0	0
T13	23710	23640	0	0
T14	6246	6148	0	0
T15	3415	3357	0	0
T18	2946	2862	0	0
T19	485911	467871	0	0
T20	70358	70281	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	384864419	102293044	0	0
T1	1636	42	0	0
T2	1951	581	0	0
T3	3382	441	0	0
T7	4246	200	0	0
T13	23710	280	0	0
T14	6246	2017	0	0
T15	3415	960	0	0
T18	2946	56	0	0
T19	485911	155586	0	0
T20	70358	68021	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	384864419	43333530	0	0
T1	1636	143	0	0
T2	1951	158	0	0
T3	3382	184	0	0
T7	4246	704	0	0
T13	23710	502	0	0
T14	6246	286	0	0
T15	3415	509	0	0
T18	2946	165	0	0
T19	485911	44736	0	0
T20	70358	420	0	0

Priority_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	384864419	108403792	0	0
T1	1636	42	0	0
T2	1951	581	0	0
T3	3382	441	0	0
T7	4246	200	0	0
T13	23710	281	0	0
T14	6246	2024	0	0
T15	3415	1066	0	0
T18	2946	56	0	0
T19	485911	155586	0	0
T20	70358	68021	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	384864419	102293044	0	0
T1	1636	42	0	0
T2	1951	581	0	0
T3	3382	441	0	0
T7	4246	200	0	0
T13	23710	280	0	0
T14	6246	2017	0	0
T15	3415	960	0	0
T18	2946	56	0	0
T19	485911	155586	0	0
T20	70358	68021	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	384864419	102293044	0	0
T1	1636	42	0	0
T2	1951	581	0	0
T3	3382	441	0	0
T7	4246	200	0	0
T13	23710	280	0	0
T14	6246	2017	0	0
T15	3415	960	0	0
T18	2946	56	0	0
T19	485911	155586	0	0
T20	70358	68021	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	384864419	108403792	0	0
T1	1636	42	0	0
T2	1951	581	0	0
T3	3382	441	0	0
T7	4246	200	0	0
T13	23710	281	0	0
T14	6246	2024	0	0
T15	3415	1066	0	0
T18	2946	56	0	0
T19	485911	155586	0	0
T20	70358	68021	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	384864419	384030817	0	0
T1	1636	1562	0	0
T2	1951	1876	0	0
T3	3382	3310	0	0
T7	4246	3594	0	0
T13	23710	23640	0	0
T14	6246	6148	0	0
T15	3415	3357	0	0
T18	2946	2862	0	0
T19	485911	467871	0	0
T20	70358	70281	0	0

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
TOTAL		16	14	87.50
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
ALWAYS	105	6	6	100.00
CONT_ASSIGN	124	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	132	1	1	100.00

84                                  // forward path
85         2/2                      assign req_tree[Pa]      = req_i[offset];
           Tests:       T1 T2 T13  | T1 T2 T3 
86                                  assign idx_tree[Pa]      = offset;
87         0/2     ==>              assign data_tree[Pa]     = data_i[offset];
88                                  // backward (grant) path
89         2/2                      assign gnt_o[offset]     = gnt_tree[Pa];
           Tests:       T1 T2 T13  | T1 T2 T3 
90                      
91                                end else begin : gen_tie_off
92                                  // forward path
93                                  assign req_tree[Pa]  = '0;
94                                  assign idx_tree[Pa]  = '0;
95                                  assign data_tree[Pa] = '0;
96                                  logic unused_sigs;
97                                  assign unused_sigs = gnt_tree[Pa];
98                                end
99                              // this creates the node assignments
100                             end else begin : gen_nodes
101                               // forward path
102                               logic sel; // local helper variable
103                               always_comb begin : p_node
104                                 // this always gives priority to the left child
105        1/1                      sel = ~req_tree[C0];
           Tests:       T1 T2 T3 
106                                 // propagate requests
107        1/1                      req_tree[Pa]  = req_tree[C0] | req_tree[C1];
           Tests:       T1 T2 T3 
108                                 // data and index muxes
109        1/1                      idx_tree[Pa]  = (sel) ? idx_tree[C1]  : idx_tree[C0];
           Tests:       T1 T2 T3 
110        1/1                      data_tree[Pa] = (sel) ? data_tree[C1] : data_tree[C0];
           Tests:       T1 T2 T3 
111                                 // propagate the grants back to the input
112        1/1                      gnt_tree[C0] = gnt_tree[Pa] & ~sel;
           Tests:       T1 T2 T3 
113        1/1                      gnt_tree[C1] = gnt_tree[Pa] &  sel;
           Tests:       T1 T2 T3 
114                               end
115                             end
116                           end : gen_level
117                         end : gen_tree
118                     
119                         // the results can be found at the tree root
120                         if (EnDataPort) begin : gen_data_port
121                           assign data_o      = data_tree[0];
122                         end else begin : gen_no_dataport
123                           logic [DW-1:0] unused_data;
124        1/1                assign unused_data = data_tree[0];
           Tests:       T1 T2 T13 
125                           assign data_o = '1;
126                         end
127                     
128        1/1              assign idx_o       = idx_tree[0];
           Tests:       T1 T2 T13 
129        1/1              assign valid_o     = req_tree[0];
           Tests:       T1 T2 T3 
130                     
131                         // this propagates a grant back to the input
132        1/1              assign gnt_tree[0] = valid_o & ready_i;
           Tests:       T1 T2 T3 

---

Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Total	Covered	Percent
Conditions	16	16	100.00
Logical	16	16	100.00
Non-Logical	0	0
Event	0	0

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T13,T14

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T1,T13,T14
1	Covered	T1,T2,T3

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T1,T13,T14
1	Covered	T1,T2,T3

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Covered	T13,T14,T15
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T13,T14

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T13,T14
1	1	Covered	T1,T2,T3

 LINE       132
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T13,T14,T15
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00

109                    idx_tree[Pa]  = (sel) ? idx_tree[C1]  : idx_tree[C0];
                                             -1-  
                                             ==>  
                                             ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T13,T14

110                    data_tree[Pa] = (sel) ? data_tree[C1] : data_tree[C0];
                                             -1-  
                                             ==>  
                                             ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T13,T14

---

Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	13	13	100.00	13	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	13	13	100.00	13	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	384864419	384030817	0	0
CheckNGreaterZero_A	1042	1042	0	0
GntImpliesReady_A	384864419	102293044	0	0
GntImpliesValid_A	384864419	102293044	0	0
GrantKnown_A	384864419	384030817	0	0
IdxKnown_A	384864419	384030817	0	0
IndexIsCorrect_A	384864419	102293044	0	0
NoReadyValidNoGrant_A	384864419	43333530	0	0
Priority_A	384864419	108403792	0	0
ReadyAndValidImplyGrant_A	384864419	102293044	0	0
ReqAndReadyImplyGrant_A	384864419	102293044	0	0
ReqImpliesValid_A	384864419	108403792	0	0
ValidKnown_A	384864419	384030817	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	384864419	384030817	0	0
T1	1636	1562	0	0
T2	1951	1876	0	0
T3	3382	3310	0	0
T7	4246	3594	0	0
T13	23710	23640	0	0
T14	6246	6148	0	0
T15	3415	3357	0	0
T18	2946	2862	0	0
T19	485911	467871	0	0
T20	70358	70281	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1042	1042	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	384864419	102293044	0	0
T1	1636	42	0	0
T2	1951	581	0	0
T3	3382	441	0	0
T7	4246	200	0	0
T13	23710	280	0	0
T14	6246	2017	0	0
T15	3415	960	0	0
T18	2946	56	0	0
T19	485911	155586	0	0
T20	70358	68021	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	384864419	102293044	0	0
T1	1636	42	0	0
T2	1951	581	0	0
T3	3382	441	0	0
T7	4246	200	0	0
T13	23710	280	0	0
T14	6246	2017	0	0
T15	3415	960	0	0
T18	2946	56	0	0
T19	485911	155586	0	0
T20	70358	68021	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	384864419	384030817	0	0
T1	1636	1562	0	0
T2	1951	1876	0	0
T3	3382	3310	0	0
T7	4246	3594	0	0
T13	23710	23640	0	0
T14	6246	6148	0	0
T15	3415	3357	0	0
T18	2946	2862	0	0
T19	485911	467871	0	0
T20	70358	70281	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	384864419	384030817	0	0
T1	1636	1562	0	0
T2	1951	1876	0	0
T3	3382	3310	0	0
T7	4246	3594	0	0
T13	23710	23640	0	0
T14	6246	6148	0	0
T15	3415	3357	0	0
T18	2946	2862	0	0
T19	485911	467871	0	0
T20	70358	70281	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	384864419	102293044	0	0
T1	1636	42	0	0
T2	1951	581	0	0
T3	3382	441	0	0
T7	4246	200	0	0
T13	23710	280	0	0
T14	6246	2017	0	0
T15	3415	960	0	0
T18	2946	56	0	0
T19	485911	155586	0	0
T20	70358	68021	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	384864419	43333530	0	0
T1	1636	143	0	0
T2	1951	158	0	0
T3	3382	184	0	0
T7	4246	704	0	0
T13	23710	502	0	0
T14	6246	286	0	0
T15	3415	509	0	0
T18	2946	165	0	0
T19	485911	44736	0	0
T20	70358	420	0	0

Priority_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	384864419	108403792	0	0
T1	1636	42	0	0
T2	1951	581	0	0
T3	3382	441	0	0
T7	4246	200	0	0
T13	23710	281	0	0
T14	6246	2024	0	0
T15	3415	1066	0	0
T18	2946	56	0	0
T19	485911	155586	0	0
T20	70358	68021	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	384864419	102293044	0	0
T1	1636	42	0	0
T2	1951	581	0	0
T3	3382	441	0	0
T7	4246	200	0	0
T13	23710	280	0	0
T14	6246	2017	0	0
T15	3415	960	0	0
T18	2946	56	0	0
T19	485911	155586	0	0
T20	70358	68021	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	384864419	102293044	0	0
T1	1636	42	0	0
T2	1951	581	0	0
T3	3382	441	0	0
T7	4246	200	0	0
T13	23710	280	0	0
T14	6246	2017	0	0
T15	3415	960	0	0
T18	2946	56	0	0
T19	485911	155586	0	0
T20	70358	68021	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	384864419	108403792	0	0
T1	1636	42	0	0
T2	1951	581	0	0
T3	3382	441	0	0
T7	4246	200	0	0
T13	23710	281	0	0
T14	6246	2024	0	0
T15	3415	1066	0	0
T18	2946	56	0	0
T19	485911	155586	0	0
T20	70358	68021	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	384864419	384030817	0	0
T1	1636	1562	0	0
T2	1951	1876	0	0
T3	3382	3310	0	0
T7	4246	3594	0	0
T13	23710	23640	0	0
T14	6246	6148	0	0
T15	3415	3357	0	0
T18	2946	2862	0	0
T19	485911	467871	0	0
T20	70358	70281	0	0

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
TOTAL		16	14	87.50
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
ALWAYS	105	6	6	100.00
CONT_ASSIGN	124	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	132	1	1	100.00

84                                  // forward path
85         2/2                      assign req_tree[Pa]      = req_i[offset];
           Tests:       T1 T2 T13  | T1 T2 T3 
86                                  assign idx_tree[Pa]      = offset;
87         0/2     ==>              assign data_tree[Pa]     = data_i[offset];
88                                  // backward (grant) path
89         2/2                      assign gnt_o[offset]     = gnt_tree[Pa];
           Tests:       T1 T2 T13  | T1 T2 T3 
90                      
91                                end else begin : gen_tie_off
92                                  // forward path
93                                  assign req_tree[Pa]  = '0;
94                                  assign idx_tree[Pa]  = '0;
95                                  assign data_tree[Pa] = '0;
96                                  logic unused_sigs;
97                                  assign unused_sigs = gnt_tree[Pa];
98                                end
99                              // this creates the node assignments
100                             end else begin : gen_nodes
101                               // forward path
102                               logic sel; // local helper variable
103                               always_comb begin : p_node
104                                 // this always gives priority to the left child
105        1/1                      sel = ~req_tree[C0];
           Tests:       T1 T2 T3 
106                                 // propagate requests
107        1/1                      req_tree[Pa]  = req_tree[C0] | req_tree[C1];
           Tests:       T1 T2 T3 
108                                 // data and index muxes
109        1/1                      idx_tree[Pa]  = (sel) ? idx_tree[C1]  : idx_tree[C0];
           Tests:       T1 T2 T3 
110        1/1                      data_tree[Pa] = (sel) ? data_tree[C1] : data_tree[C0];
           Tests:       T1 T2 T3 
111                                 // propagate the grants back to the input
112        1/1                      gnt_tree[C0] = gnt_tree[Pa] & ~sel;
           Tests:       T1 T2 T3 
113        1/1                      gnt_tree[C1] = gnt_tree[Pa] &  sel;
           Tests:       T1 T2 T3 
114                               end
115                             end
116                           end : gen_level
117                         end : gen_tree
118                     
119                         // the results can be found at the tree root
120                         if (EnDataPort) begin : gen_data_port
121                           assign data_o      = data_tree[0];
122                         end else begin : gen_no_dataport
123                           logic [DW-1:0] unused_data;
124        1/1                assign unused_data = data_tree[0];
           Tests:       T1 T2 T13 
125                           assign data_o = '1;
126                         end
127                     
128        1/1              assign idx_o       = idx_tree[0];
           Tests:       T1 T2 T13 
129        1/1              assign valid_o     = req_tree[0];
           Tests:       T1 T2 T3 
130                     
131                         // this propagates a grant back to the input
132        1/1              assign gnt_tree[0] = valid_o & ready_i;
           Tests:       T1 T2 T3 

---

Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Total	Covered	Percent
Conditions	16	16	100.00
Logical	16	16	100.00
Non-Logical	0	0
Event	0	0

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T3,T13,T14
1	0	Covered	T13,T14,T15

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T13,T14,T15
1	Covered	T1,T2,T3

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T13,T14,T15
1	Covered	T1,T2,T3

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Covered	T13,T14,T52
1	0	Covered	T3,T13,T14
1	1	Covered	T13,T14,T15

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T13,T14,T15
1	1	Covered	T3,T13,T14

 LINE       132
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T13,T14,T52
1	1	Covered	T3,T13,T14

---

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00

109                    idx_tree[Pa]  = (sel) ? idx_tree[C1]  : idx_tree[C0];
                                             -1-  
                                             ==>  
                                             ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T13,T14,T15

110                    data_tree[Pa] = (sel) ? data_tree[C1] : data_tree[C0];
                                             -1-  
                                             ==>  
                                             ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T13,T14,T15

---

Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	13	13	100.00	13	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	13	13	100.00	13	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	384864419	384030817	0	0
CheckNGreaterZero_A	1042	1042	0	0
GntImpliesReady_A	384864419	98070185	0	0
GntImpliesValid_A	384864419	98070185	0	0
GrantKnown_A	384864419	384030817	0	0
IdxKnown_A	384864419	384030817	0	0
IndexIsCorrect_A	384864419	98070185	0	0
NoReadyValidNoGrant_A	384864419	40867061	0	0
Priority_A	384864419	104022141	0	0
ReadyAndValidImplyGrant_A	384864419	98070185	0	0
ReqAndReadyImplyGrant_A	384864419	98070185	0	0
ReqImpliesValid_A	384864419	104022141	0	0
ValidKnown_A	384864419	384030817	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	384864419	384030817	0	0
T1	1636	1562	0	0
T2	1951	1876	0	0
T3	3382	3310	0	0
T7	4246	3594	0	0
T13	23710	23640	0	0
T14	6246	6148	0	0
T15	3415	3357	0	0
T18	2946	2862	0	0
T19	485911	467871	0	0
T20	70358	70281	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1042	1042	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	384864419	98070185	0	0
T3	3382	12	0	0
T7	4246	0	0	0
T13	23710	423	0	0
T14	6246	1564	0	0
T15	3415	354	0	0
T18	2946	395	0	0
T19	485911	0	0	0
T20	70358	0	0	0
T48	0	37418	0	0
T49	0	9790	0	0
T52	0	10701	0	0
T65	1935	146	0	0
T66	3620	2183	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	384864419	98070185	0	0
T3	3382	12	0	0
T7	4246	0	0	0
T13	23710	423	0	0
T14	6246	1564	0	0
T15	3415	354	0	0
T18	2946	395	0	0
T19	485911	0	0	0
T20	70358	0	0	0
T48	0	37418	0	0
T49	0	9790	0	0
T52	0	10701	0	0
T65	1935	146	0	0
T66	3620	2183	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	384864419	384030817	0	0
T1	1636	1562	0	0
T2	1951	1876	0	0
T3	3382	3310	0	0
T7	4246	3594	0	0
T13	23710	23640	0	0
T14	6246	6148	0	0
T15	3415	3357	0	0
T18	2946	2862	0	0
T19	485911	467871	0	0
T20	70358	70281	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	384864419	384030817	0	0
T1	1636	1562	0	0
T2	1951	1876	0	0
T3	3382	3310	0	0
T7	4246	3594	0	0
T13	23710	23640	0	0
T14	6246	6148	0	0
T15	3415	3357	0	0
T18	2946	2862	0	0
T19	485911	467871	0	0
T20	70358	70281	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	384864419	98070185	0	0
T3	3382	12	0	0
T7	4246	0	0	0
T13	23710	423	0	0
T14	6246	1564	0	0
T15	3415	354	0	0
T18	2946	395	0	0
T19	485911	0	0	0
T20	70358	0	0	0
T48	0	37418	0	0
T49	0	9790	0	0
T52	0	10701	0	0
T65	1935	146	0	0
T66	3620	2183	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	384864419	40867061	0	0
T3	3382	19	0	0
T7	4246	0	0	0
T13	23710	645	0	0
T14	6246	125	0	0
T15	3415	36	0	0
T18	2946	0	0	0
T19	485911	0	0	0
T20	70358	0	0	0
T32	0	1661	0	0
T41	0	29070	0	0
T48	0	2226	0	0
T49	0	44	0	0
T52	0	13835	0	0
T65	1935	200	0	0
T66	3620	0	0	0

Priority_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	384864419	104022141	0	0
T3	3382	12	0	0
T7	4246	0	0	0
T13	23710	424	0	0
T14	6246	1567	0	0
T15	3415	354	0	0
T18	2946	395	0	0
T19	485911	0	0	0
T20	70358	0	0	0
T48	0	37418	0	0
T49	0	9790	0	0
T52	0	16931	0	0
T65	1935	146	0	0
T66	3620	2183	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	384864419	98070185	0	0
T3	3382	12	0	0
T7	4246	0	0	0
T13	23710	423	0	0
T14	6246	1564	0	0
T15	3415	354	0	0
T18	2946	395	0	0
T19	485911	0	0	0
T20	70358	0	0	0
T48	0	37418	0	0
T49	0	9790	0	0
T52	0	10701	0	0
T65	1935	146	0	0
T66	3620	2183	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	384864419	98070185	0	0
T3	3382	12	0	0
T7	4246	0	0	0
T13	23710	423	0	0
T14	6246	1564	0	0
T15	3415	354	0	0
T18	2946	395	0	0
T19	485911	0	0	0
T20	70358	0	0	0
T48	0	37418	0	0
T49	0	9790	0	0
T52	0	10701	0	0
T65	1935	146	0	0
T66	3620	2183	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	384864419	104022141	0	0
T3	3382	12	0	0
T7	4246	0	0	0
T13	23710	424	0	0
T14	6246	1567	0	0
T15	3415	354	0	0
T18	2946	395	0	0
T19	485911	0	0	0
T20	70358	0	0	0
T48	0	37418	0	0
T49	0	9790	0	0
T52	0	16931	0	0
T65	1935	146	0	0
T66	3620	2183	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	384864419	384030817	0	0
T1	1636	1562	0	0
T2	1951	1876	0	0
T3	3382	3310	0	0
T7	4246	3594	0	0
T13	23710	23640	0	0
T14	6246	6148	0	0
T15	3415	3357	0	0
T18	2946	2862	0	0
T19	485911	467871	0	0
T20	70358	70281	0	0

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
TOTAL		16	14	87.50
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
ALWAYS	105	6	6	100.00
CONT_ASSIGN	124	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	132	1	1	100.00

84                                  // forward path
85         2/2                      assign req_tree[Pa]      = req_i[offset];
           Tests:       T1 T2 T13  | T1 T2 T3 
86                                  assign idx_tree[Pa]      = offset;
87         0/2     ==>              assign data_tree[Pa]     = data_i[offset];
88                                  // backward (grant) path
89         2/2                      assign gnt_o[offset]     = gnt_tree[Pa];
           Tests:       T1 T2 T13  | T1 T2 T3 
90                      
91                                end else begin : gen_tie_off
92                                  // forward path
93                                  assign req_tree[Pa]  = '0;
94                                  assign idx_tree[Pa]  = '0;
95                                  assign data_tree[Pa] = '0;
96                                  logic unused_sigs;
97                                  assign unused_sigs = gnt_tree[Pa];
98                                end
99                              // this creates the node assignments
100                             end else begin : gen_nodes
101                               // forward path
102                               logic sel; // local helper variable
103                               always_comb begin : p_node
104                                 // this always gives priority to the left child
105        1/1                      sel = ~req_tree[C0];
           Tests:       T1 T2 T3 
106                                 // propagate requests
107        1/1                      req_tree[Pa]  = req_tree[C0] | req_tree[C1];
           Tests:       T1 T2 T3 
108                                 // data and index muxes
109        1/1                      idx_tree[Pa]  = (sel) ? idx_tree[C1]  : idx_tree[C0];
           Tests:       T1 T2 T3 
110        1/1                      data_tree[Pa] = (sel) ? data_tree[C1] : data_tree[C0];
           Tests:       T1 T2 T3 
111                                 // propagate the grants back to the input
112        1/1                      gnt_tree[C0] = gnt_tree[Pa] & ~sel;
           Tests:       T1 T2 T3 
113        1/1                      gnt_tree[C1] = gnt_tree[Pa] &  sel;
           Tests:       T1 T2 T3 
114                               end
115                             end
116                           end : gen_level
117                         end : gen_tree
118                     
119                         // the results can be found at the tree root
120                         if (EnDataPort) begin : gen_data_port
121                           assign data_o      = data_tree[0];
122                         end else begin : gen_no_dataport
123                           logic [DW-1:0] unused_data;
124        1/1                assign unused_data = data_tree[0];
           Tests:       T1 T2 T13 
125                           assign data_o = '1;
126                         end
127                     
128        1/1              assign idx_o       = idx_tree[0];
           Tests:       T1 T2 T13 
129        1/1              assign valid_o     = req_tree[0];
           Tests:       T1 T2 T3 
130                     
131                         // this propagates a grant back to the input
132        1/1              assign gnt_tree[0] = valid_o & ready_i;
           Tests:       T1 T2 T3 

---

Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Total	Covered	Percent
Conditions	16	16	100.00
Logical	16	16	100.00
Non-Logical	0	0
Event	0	0

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T3,T13,T14
1	0	Covered	T13,T14,T15

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T13,T14,T15
1	Covered	T1,T2,T3

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T13,T14,T15
1	Covered	T1,T2,T3

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Covered	T13,T14,T52
1	0	Covered	T3,T13,T14
1	1	Covered	T13,T14,T15

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T13,T14,T15
1	1	Covered	T3,T13,T14

 LINE       132
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T13,T14,T52
1	1	Covered	T3,T13,T14

---

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00

109                    idx_tree[Pa]  = (sel) ? idx_tree[C1]  : idx_tree[C0];
                                             -1-  
                                             ==>  
                                             ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T13,T14,T15

110                    data_tree[Pa] = (sel) ? data_tree[C1] : data_tree[C0];
                                             -1-  
                                             ==>  
                                             ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T13,T14,T15

---

Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	13	13	100.00	13	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	13	13	100.00	13	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	384864419	384030817	0	0
CheckNGreaterZero_A	1042	1042	0	0
GntImpliesReady_A	384864419	98070039	0	0
GntImpliesValid_A	384864419	98070039	0	0
GrantKnown_A	384864419	384030817	0	0
IdxKnown_A	384864419	384030817	0	0
IndexIsCorrect_A	384864419	98070039	0	0
NoReadyValidNoGrant_A	384864419	40867015	0	0
Priority_A	384864419	104022041	0	0
ReadyAndValidImplyGrant_A	384864419	98070039	0	0
ReqAndReadyImplyGrant_A	384864419	98070039	0	0
ReqImpliesValid_A	384864419	104022041	0	0
ValidKnown_A	384864419	384030817	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	384864419	384030817	0	0
T1	1636	1562	0	0
T2	1951	1876	0	0
T3	3382	3310	0	0
T7	4246	3594	0	0
T13	23710	23640	0	0
T14	6246	6148	0	0
T15	3415	3357	0	0
T18	2946	2862	0	0
T19	485911	467871	0	0
T20	70358	70281	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1042	1042	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	384864419	98070039	0	0
T3	3382	12	0	0
T7	4246	0	0	0
T13	23710	423	0	0
T14	6246	1564	0	0
T15	3415	354	0	0
T18	2946	395	0	0
T19	485911	0	0	0
T20	70358	0	0	0
T48	0	37418	0	0
T49	0	9790	0	0
T52	0	10701	0	0
T65	1935	146	0	0
T66	3620	2183	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	384864419	98070039	0	0
T3	3382	12	0	0
T7	4246	0	0	0
T13	23710	423	0	0
T14	6246	1564	0	0
T15	3415	354	0	0
T18	2946	395	0	0
T19	485911	0	0	0
T20	70358	0	0	0
T48	0	37418	0	0
T49	0	9790	0	0
T52	0	10701	0	0
T65	1935	146	0	0
T66	3620	2183	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	384864419	384030817	0	0
T1	1636	1562	0	0
T2	1951	1876	0	0
T3	3382	3310	0	0
T7	4246	3594	0	0
T13	23710	23640	0	0
T14	6246	6148	0	0
T15	3415	3357	0	0
T18	2946	2862	0	0
T19	485911	467871	0	0
T20	70358	70281	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	384864419	384030817	0	0
T1	1636	1562	0	0
T2	1951	1876	0	0
T3	3382	3310	0	0
T7	4246	3594	0	0
T13	23710	23640	0	0
T14	6246	6148	0	0
T15	3415	3357	0	0
T18	2946	2862	0	0
T19	485911	467871	0	0
T20	70358	70281	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	384864419	98070039	0	0
T3	3382	12	0	0
T7	4246	0	0	0
T13	23710	423	0	0
T14	6246	1564	0	0
T15	3415	354	0	0
T18	2946	395	0	0
T19	485911	0	0	0
T20	70358	0	0	0
T48	0	37418	0	0
T49	0	9790	0	0
T52	0	10701	0	0
T65	1935	146	0	0
T66	3620	2183	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	384864419	40867015	0	0
T3	3382	19	0	0
T7	4246	0	0	0
T13	23710	645	0	0
T14	6246	125	0	0
T15	3415	36	0	0
T18	2946	0	0	0
T19	485911	0	0	0
T20	70358	0	0	0
T32	0	1661	0	0
T41	0	29070	0	0
T48	0	2226	0	0
T49	0	44	0	0
T52	0	13835	0	0
T65	1935	200	0	0
T66	3620	0	0	0

Priority_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	384864419	104022041	0	0
T3	3382	12	0	0
T7	4246	0	0	0
T13	23710	424	0	0
T14	6246	1567	0	0
T15	3415	354	0	0
T18	2946	395	0	0
T19	485911	0	0	0
T20	70358	0	0	0
T48	0	37418	0	0
T49	0	9790	0	0
T52	0	16931	0	0
T65	1935	146	0	0
T66	3620	2183	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	384864419	98070039	0	0
T3	3382	12	0	0
T7	4246	0	0	0
T13	23710	423	0	0
T14	6246	1564	0	0
T15	3415	354	0	0
T18	2946	395	0	0
T19	485911	0	0	0
T20	70358	0	0	0
T48	0	37418	0	0
T49	0	9790	0	0
T52	0	10701	0	0
T65	1935	146	0	0
T66	3620	2183	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	384864419	98070039	0	0
T3	3382	12	0	0
T7	4246	0	0	0
T13	23710	423	0	0
T14	6246	1564	0	0
T15	3415	354	0	0
T18	2946	395	0	0
T19	485911	0	0	0
T20	70358	0	0	0
T48	0	37418	0	0
T49	0	9790	0	0
T52	0	10701	0	0
T65	1935	146	0	0
T66	3620	2183	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	384864419	104022041	0	0
T3	3382	12	0	0
T7	4246	0	0	0
T13	23710	424	0	0
T14	6246	1567	0	0
T15	3415	354	0	0
T18	2946	395	0	0
T19	485911	0	0	0
T20	70358	0	0	0
T48	0	37418	0	0
T49	0	9790	0	0
T52	0	16931	0	0
T65	1935	146	0	0
T66	3620	2183	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	384864419	384030817	0	0
T1	1636	1562	0	0
T2	1951	1876	0	0
T3	3382	3310	0	0
T7	4246	3594	0	0
T13	23710	23640	0	0
T14	6246	6148	0	0
T15	3415	3357	0	0
T18	2946	2862	0	0
T19	485911	467871	0	0
T20	70358	70281	0	0