Module Definition
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Module Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
76.67 90.00 40.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
91.95 75.93 91.89 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
98.87 100.00 94.34 100.00 100.00 100.00 gen_flash_cores[0].u_core


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_input_bufs[0].gen_data_bufs[0].u_dat_buf 0.00 0.00
gen_input_bufs[0].gen_data_bufs[1].u_dat_buf 0.00 0.00
gen_input_bufs[0].gen_fixed_arbiter.u_arb 96.88 87.50 100.00 100.00 100.00
gen_input_bufs[0].u_req_buf 100.00 100.00
gen_input_bufs[1].gen_data_bufs[0].u_dat_buf 0.00 0.00
gen_input_bufs[1].gen_data_bufs[1].u_dat_buf 0.00 0.00
gen_input_bufs[1].gen_fixed_arbiter.u_arb 96.88 87.50 100.00 100.00 100.00
gen_input_bufs[1].u_req_buf 100.00 100.00



Module Instance : tb.dut.u_eflash.u_scramble.u_prim_arbiter_tree_op

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
80.00 100.00 40.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
94.47 100.00 84.11 100.00 93.75


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
95.40 100.00 86.21 100.00 u_scramble


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_input_bufs[0].gen_data_bufs[0].u_dat_buf 100.00 100.00
gen_input_bufs[0].gen_data_bufs[1].u_dat_buf 100.00 100.00
gen_input_bufs[0].gen_rr_arbiter.u_arb 95.01 100.00 86.27 100.00 93.75
gen_input_bufs[0].u_req_buf 100.00 100.00
gen_input_bufs[1].gen_data_bufs[0].u_dat_buf 100.00 100.00
gen_input_bufs[1].gen_data_bufs[1].u_dat_buf 100.00 100.00
gen_input_bufs[1].gen_rr_arbiter.u_arb 95.01 100.00 86.27 100.00 93.75
gen_input_bufs[1].u_req_buf 100.00 100.00



Module Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
96.67 90.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
93.98 75.93 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
96.74 100.00 85.85 100.00 97.83 100.00 gen_flash_cores[1].u_core


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_input_bufs[0].gen_data_bufs[0].u_dat_buf 0.00 0.00
gen_input_bufs[0].gen_data_bufs[1].u_dat_buf 0.00 0.00
gen_input_bufs[0].gen_fixed_arbiter.u_arb 96.88 87.50 100.00 100.00 100.00
gen_input_bufs[0].u_req_buf 100.00 100.00
gen_input_bufs[1].gen_data_bufs[0].u_dat_buf 0.00 0.00
gen_input_bufs[1].gen_data_bufs[1].u_dat_buf 0.00 0.00
gen_input_bufs[1].gen_fixed_arbiter.u_arb 96.88 87.50 100.00 100.00 100.00
gen_input_bufs[1].u_req_buf 100.00 100.00



Module Instance : tb.dut.u_eflash.u_scramble.u_prim_arbiter_tree_calc

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
98.67 100.00 97.80 100.00 96.88


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
95.40 100.00 86.21 100.00 u_scramble


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_input_bufs[0].gen_data_bufs[0].u_dat_buf 100.00 100.00
gen_input_bufs[0].gen_data_bufs[1].u_dat_buf 100.00 100.00
gen_input_bufs[0].gen_rr_arbiter.u_arb 99.42 100.00 97.67 100.00 100.00
gen_input_bufs[0].u_req_buf 100.00 100.00
gen_input_bufs[1].gen_data_bufs[0].u_dat_buf 100.00 100.00
gen_input_bufs[1].gen_data_bufs[1].u_dat_buf 100.00 100.00
gen_input_bufs[1].gen_rr_arbiter.u_arb 97.86 100.00 97.67 100.00 93.75
gen_input_bufs[1].u_req_buf 100.00 100.00

Line Coverage for Module : prim_arbiter_tree_dup ( parameter N=2,DW=16,EnDataPort=1,FixedArb=0,IdxW=1,ArbInstances=2 + N=2,DW=129,EnDataPort=1,FixedArb=0,IdxW=1,ArbInstances=2 )
Line Coverage for Module self-instances :
SCORELINE
100.00 100.00
tb.dut.u_eflash.u_scramble.u_prim_arbiter_tree_calc

SCORELINE
80.00 100.00
tb.dut.u_eflash.u_scramble.u_prim_arbiter_tree_op

Line No.TotalCoveredPercent
TOTAL1010100.00
CONT_ASSIGN12311100.00
CONT_ASSIGN12411100.00
CONT_ASSIGN12511100.00
CONT_ASSIGN12611100.00
CONT_ASSIGN13211100.00
CONT_ASSIGN13711100.00
ALWAYS13933100.00
CONT_ASSIGN14611100.00

122 // the last buffered position is sent out 123 1/1 assign gnt_o = arb_output_buf[ArbInstances-1].gnt; Tests: T1 T2 T3  124 1/1 assign idx_o = arb_output_buf[ArbInstances-1].idx; Tests: T1 T2 T3  125 1/1 assign valid_o = arb_output_buf[ArbInstances-1].valid; Tests: T1 T2 T3  126 1/1 assign data_o = arb_output_buf[ArbInstances-1].data; Tests: T1 T2 T3  127 128 // Check the last buffer index against all other instances 129 logic [ArbInstances-2:0] output_delta; 130 131 for (genvar i = 0; i < ArbInstances-1; i++) begin : gen_checks 132 1/1 assign output_delta[i] = arb_output_buf[ArbInstances-1] != arb_output_buf[i]; Tests: T1 T2 T3  133 end 134 135 logic err_d, err_q; 136 // There is an error if anything ever disagrees 137 1/1 assign err_d = |output_delta; Tests: T1 T2 T3  138 always_ff @(posedge clk_i or negedge rst_ni) begin 139 1/1 if (!rst_ni) begin Tests: T1 T2 T3  140 1/1 err_q <= '0; Tests: T1 T2 T3  141 end else begin 142 1/1 err_q <= err_d | err_q; Tests: T1 T2 T3  143 end 144 end 145 146 1/1 assign err_o = err_q; Tests: T1 T2 T3 

Line Coverage for Module : prim_arbiter_tree_dup ( parameter N=2,DW=2,EnDataPort=0,FixedArb=1,IdxW=1,ArbInstances=2 )
Line Coverage for Module self-instances :
SCORELINE
76.67 90.00
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb

SCORELINE
96.67 90.00
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb

Line No.TotalCoveredPercent
TOTAL10990.00
CONT_ASSIGN10000
CONT_ASSIGN10000
CONT_ASSIGN12311100.00
CONT_ASSIGN12411100.00
CONT_ASSIGN12511100.00
CONT_ASSIGN126100.00
CONT_ASSIGN13211100.00
CONT_ASSIGN13711100.00
ALWAYS13933100.00
CONT_ASSIGN14611100.00

99 logic unused_req_chk; 100 unreachable assign unused_req_chk = req_chk_i; 101 102 end else begin : gen_rr_arbiter 103 prim_arbiter_tree #( 104 .N(N), 105 .DW(DW), 106 .EnDataPort(EnDataPort) 107 ) u_arb ( 108 .clk_i, 109 .rst_ni, 110 .req_chk_i, 111 .req_i(req_buf), 112 .data_i(data_buf), 113 .gnt_o(arb_output_buf[i].gnt), 114 .idx_o(arb_output_buf[i].idx), 115 .valid_o(arb_output_buf[i].valid), 116 .data_o(arb_output_buf[i].data), 117 .ready_i 118 ); 119 end 120 end 121 122 // the last buffered position is sent out 123 1/1 assign gnt_o = arb_output_buf[ArbInstances-1].gnt; Tests: T1 T2 T3  124 1/1 assign idx_o = arb_output_buf[ArbInstances-1].idx; Tests: T1 T2 T13  125 1/1 assign valid_o = arb_output_buf[ArbInstances-1].valid; Tests: T1 T2 T3  126 0/1 ==> assign data_o = arb_output_buf[ArbInstances-1].data; 127 128 // Check the last buffer index against all other instances 129 logic [ArbInstances-2:0] output_delta; 130 131 for (genvar i = 0; i < ArbInstances-1; i++) begin : gen_checks 132 1/1 assign output_delta[i] = arb_output_buf[ArbInstances-1] != arb_output_buf[i]; Tests: T1 T2 T3  133 end 134 135 logic err_d, err_q; 136 // There is an error if anything ever disagrees 137 1/1 assign err_d = |output_delta; Tests: T1 T2 T3  138 always_ff @(posedge clk_i or negedge rst_ni) begin 139 1/1 if (!rst_ni) begin Tests: T1 T2 T3  140 1/1 err_q <= '0; Tests: T1 T2 T3  141 end else begin 142 1/1 err_q <= err_d | err_q; Tests: T1 T2 T3  143 end 144 end 145 146 1/1 assign err_o = err_q; Tests: T1 T2 T3 

Cond Coverage for Module : prim_arbiter_tree_dup
TotalCoveredPercent
Conditions55100.00
Logical55100.00
Non-Logical00
Event00

 LINE       132
 EXPRESSION (arb_output_buf[(ArbInstances - 1)] != arb_output_buf[0])
            ----------------------------1----------------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT76,T82,T83

 LINE       142
 EXPRESSION (err_d | err_q)
             --1--   --2--
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT76,T82,T83
10CoveredT76,T82,T83

Branch Coverage for Module : prim_arbiter_tree_dup
Line No.TotalCoveredPercent
Branches 2 2 100.00
IF 139 2 2 100.00


139 if (!rst_ni) begin -1- 140 err_q <= '0; ==> 141 end else begin 142 err_q <= err_d | err_q; ==>

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb
Line No.TotalCoveredPercent
TOTAL10990.00
CONT_ASSIGN10000
CONT_ASSIGN10000
CONT_ASSIGN12311100.00
CONT_ASSIGN12411100.00
CONT_ASSIGN12511100.00
CONT_ASSIGN126100.00
CONT_ASSIGN13211100.00
CONT_ASSIGN13711100.00
ALWAYS13933100.00
CONT_ASSIGN14611100.00

99 logic unused_req_chk; 100 unreachable assign unused_req_chk = req_chk_i; 101 102 end else begin : gen_rr_arbiter 103 prim_arbiter_tree #( 104 .N(N), 105 .DW(DW), 106 .EnDataPort(EnDataPort) 107 ) u_arb ( 108 .clk_i, 109 .rst_ni, 110 .req_chk_i, 111 .req_i(req_buf), 112 .data_i(data_buf), 113 .gnt_o(arb_output_buf[i].gnt), 114 .idx_o(arb_output_buf[i].idx), 115 .valid_o(arb_output_buf[i].valid), 116 .data_o(arb_output_buf[i].data), 117 .ready_i 118 ); 119 end 120 end 121 122 // the last buffered position is sent out 123 1/1 assign gnt_o = arb_output_buf[ArbInstances-1].gnt; Tests: T1 T2 T3  124 1/1 assign idx_o = arb_output_buf[ArbInstances-1].idx; Tests: T1 T2 T13  125 1/1 assign valid_o = arb_output_buf[ArbInstances-1].valid; Tests: T1 T2 T3  126 0/1 ==> assign data_o = arb_output_buf[ArbInstances-1].data; 127 128 // Check the last buffer index against all other instances 129 logic [ArbInstances-2:0] output_delta; 130 131 for (genvar i = 0; i < ArbInstances-1; i++) begin : gen_checks 132 1/1 assign output_delta[i] = arb_output_buf[ArbInstances-1] != arb_output_buf[i]; Tests: T1 T2 T3  133 end 134 135 logic err_d, err_q; 136 // There is an error if anything ever disagrees 137 1/1 assign err_d = |output_delta; Tests: T1 T2 T3  138 always_ff @(posedge clk_i or negedge rst_ni) begin 139 1/1 if (!rst_ni) begin Tests: T1 T2 T3  140 1/1 err_q <= '0; Tests: T1 T2 T3  141 end else begin 142 1/1 err_q <= err_d | err_q; Tests: T1 T2 T3  143 end 144 end 145 146 1/1 assign err_o = err_q; Tests: T1 T2 T3 

Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb
TotalCoveredPercent
Conditions5240.00
Logical5240.00
Non-Logical00
Event00

 LINE       132
 EXPRESSION (arb_output_buf[(ArbInstances - 1)] != arb_output_buf[0])
            ----------------------------1----------------------------
-1-StatusTests
0CoveredT1,T2,T3
1Not Covered

 LINE       142
 EXPRESSION (err_d | err_q)
             --1--   --2--
-1--2-StatusTests
00CoveredT1,T2,T3
01Not Covered
10Not Covered

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb
Line No.TotalCoveredPercent
Branches 2 2 100.00
IF 139 2 2 100.00


139 if (!rst_ni) begin -1- 140 err_q <= '0; ==> 141 end else begin 142 err_q <= err_d | err_q; ==>

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3

Line Coverage for Instance : tb.dut.u_eflash.u_scramble.u_prim_arbiter_tree_op
Line No.TotalCoveredPercent
TOTAL1010100.00
CONT_ASSIGN12311100.00
CONT_ASSIGN12411100.00
CONT_ASSIGN12511100.00
CONT_ASSIGN12611100.00
CONT_ASSIGN13211100.00
CONT_ASSIGN13711100.00
ALWAYS13933100.00
CONT_ASSIGN14611100.00

122 // the last buffered position is sent out 123 1/1 assign gnt_o = arb_output_buf[ArbInstances-1].gnt; Tests: T1 T2 T3  124 1/1 assign idx_o = arb_output_buf[ArbInstances-1].idx; Tests: T1 T2 T3  125 1/1 assign valid_o = arb_output_buf[ArbInstances-1].valid; Tests: T1 T2 T3  126 1/1 assign data_o = arb_output_buf[ArbInstances-1].data; Tests: T1 T2 T3  127 128 // Check the last buffer index against all other instances 129 logic [ArbInstances-2:0] output_delta; 130 131 for (genvar i = 0; i < ArbInstances-1; i++) begin : gen_checks 132 1/1 assign output_delta[i] = arb_output_buf[ArbInstances-1] != arb_output_buf[i]; Tests: T1 T2 T3  133 end 134 135 logic err_d, err_q; 136 // There is an error if anything ever disagrees 137 1/1 assign err_d = |output_delta; Tests: T1 T2 T3  138 always_ff @(posedge clk_i or negedge rst_ni) begin 139 1/1 if (!rst_ni) begin Tests: T1 T2 T3  140 1/1 err_q <= '0; Tests: T1 T2 T3  141 end else begin 142 1/1 err_q <= err_d | err_q; Tests: T1 T2 T3  143 end 144 end 145 146 1/1 assign err_o = err_q; Tests: T1 T2 T3 

Cond Coverage for Instance : tb.dut.u_eflash.u_scramble.u_prim_arbiter_tree_op
TotalCoveredPercent
Conditions5240.00
Logical5240.00
Non-Logical00
Event00

 LINE       132
 EXPRESSION (arb_output_buf[(ArbInstances - 1)] != arb_output_buf[0])
            ----------------------------1----------------------------
-1-StatusTests
0CoveredT1,T2,T3
1Not Covered

 LINE       142
 EXPRESSION (err_d | err_q)
             --1--   --2--
-1--2-StatusTests
00CoveredT1,T2,T3
01Not Covered
10Not Covered

Branch Coverage for Instance : tb.dut.u_eflash.u_scramble.u_prim_arbiter_tree_op
Line No.TotalCoveredPercent
Branches 2 2 100.00
IF 139 2 2 100.00


139 if (!rst_ni) begin -1- 140 err_q <= '0; ==> 141 end else begin 142 err_q <= err_d | err_q; ==>

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb
Line No.TotalCoveredPercent
TOTAL10990.00
CONT_ASSIGN10000
CONT_ASSIGN10000
CONT_ASSIGN12311100.00
CONT_ASSIGN12411100.00
CONT_ASSIGN12511100.00
CONT_ASSIGN126100.00
CONT_ASSIGN13211100.00
CONT_ASSIGN13711100.00
ALWAYS13933100.00
CONT_ASSIGN14611100.00

99 logic unused_req_chk; 100 unreachable assign unused_req_chk = req_chk_i; 101 102 end else begin : gen_rr_arbiter 103 prim_arbiter_tree #( 104 .N(N), 105 .DW(DW), 106 .EnDataPort(EnDataPort) 107 ) u_arb ( 108 .clk_i, 109 .rst_ni, 110 .req_chk_i, 111 .req_i(req_buf), 112 .data_i(data_buf), 113 .gnt_o(arb_output_buf[i].gnt), 114 .idx_o(arb_output_buf[i].idx), 115 .valid_o(arb_output_buf[i].valid), 116 .data_o(arb_output_buf[i].data), 117 .ready_i 118 ); 119 end 120 end 121 122 // the last buffered position is sent out 123 1/1 assign gnt_o = arb_output_buf[ArbInstances-1].gnt; Tests: T1 T2 T3  124 1/1 assign idx_o = arb_output_buf[ArbInstances-1].idx; Tests: T1 T2 T13  125 1/1 assign valid_o = arb_output_buf[ArbInstances-1].valid; Tests: T1 T2 T3  126 0/1 ==> assign data_o = arb_output_buf[ArbInstances-1].data; 127 128 // Check the last buffer index against all other instances 129 logic [ArbInstances-2:0] output_delta; 130 131 for (genvar i = 0; i < ArbInstances-1; i++) begin : gen_checks 132 1/1 assign output_delta[i] = arb_output_buf[ArbInstances-1] != arb_output_buf[i]; Tests: T1 T2 T3  133 end 134 135 logic err_d, err_q; 136 // There is an error if anything ever disagrees 137 1/1 assign err_d = |output_delta; Tests: T1 T2 T3  138 always_ff @(posedge clk_i or negedge rst_ni) begin 139 1/1 if (!rst_ni) begin Tests: T1 T2 T3  140 1/1 err_q <= '0; Tests: T1 T2 T3  141 end else begin 142 1/1 err_q <= err_d | err_q; Tests: T1 T2 T3  143 end 144 end 145 146 1/1 assign err_o = err_q; Tests: T1 T2 T3 

Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb
TotalCoveredPercent
Conditions55100.00
Logical55100.00
Non-Logical00
Event00

 LINE       132
 EXPRESSION (arb_output_buf[(ArbInstances - 1)] != arb_output_buf[0])
            ----------------------------1----------------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT76,T83,T84

 LINE       142
 EXPRESSION (err_d | err_q)
             --1--   --2--
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT76,T83,T84
10CoveredT76,T83,T84

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb
Line No.TotalCoveredPercent
Branches 2 2 100.00
IF 139 2 2 100.00


139 if (!rst_ni) begin -1- 140 err_q <= '0; ==> 141 end else begin 142 err_q <= err_d | err_q; ==>

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3

Line Coverage for Instance : tb.dut.u_eflash.u_scramble.u_prim_arbiter_tree_calc
Line No.TotalCoveredPercent
TOTAL1010100.00
CONT_ASSIGN12311100.00
CONT_ASSIGN12411100.00
CONT_ASSIGN12511100.00
CONT_ASSIGN12611100.00
CONT_ASSIGN13211100.00
CONT_ASSIGN13711100.00
ALWAYS13933100.00
CONT_ASSIGN14611100.00

122 // the last buffered position is sent out 123 1/1 assign gnt_o = arb_output_buf[ArbInstances-1].gnt; Tests: T1 T2 T3  124 1/1 assign idx_o = arb_output_buf[ArbInstances-1].idx; Tests: T1 T2 T3  125 1/1 assign valid_o = arb_output_buf[ArbInstances-1].valid; Tests: T1 T2 T3  126 1/1 assign data_o = arb_output_buf[ArbInstances-1].data; Tests: T1 T2 T3  127 128 // Check the last buffer index against all other instances 129 logic [ArbInstances-2:0] output_delta; 130 131 for (genvar i = 0; i < ArbInstances-1; i++) begin : gen_checks 132 1/1 assign output_delta[i] = arb_output_buf[ArbInstances-1] != arb_output_buf[i]; Tests: T1 T2 T3  133 end 134 135 logic err_d, err_q; 136 // There is an error if anything ever disagrees 137 1/1 assign err_d = |output_delta; Tests: T1 T2 T3  138 always_ff @(posedge clk_i or negedge rst_ni) begin 139 1/1 if (!rst_ni) begin Tests: T1 T2 T3  140 1/1 err_q <= '0; Tests: T1 T2 T3  141 end else begin 142 1/1 err_q <= err_d | err_q; Tests: T1 T2 T3  143 end 144 end 145 146 1/1 assign err_o = err_q; Tests: T1 T2 T3 

Cond Coverage for Instance : tb.dut.u_eflash.u_scramble.u_prim_arbiter_tree_calc
TotalCoveredPercent
Conditions55100.00
Logical55100.00
Non-Logical00
Event00

 LINE       132
 EXPRESSION (arb_output_buf[(ArbInstances - 1)] != arb_output_buf[0])
            ----------------------------1----------------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT82

 LINE       142
 EXPRESSION (err_d | err_q)
             --1--   --2--
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT82
10CoveredT82

Branch Coverage for Instance : tb.dut.u_eflash.u_scramble.u_prim_arbiter_tree_calc
Line No.TotalCoveredPercent
Branches 2 2 100.00
IF 139 2 2 100.00


139 if (!rst_ni) begin -1- 140 err_q <= '0; ==> 141 end else begin 142 err_q <= err_d | err_q; ==>

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%