Module Definition
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Module Instance : tb.dut.u_ctrl_arb.u_state_regs

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 100.00 100.00 u_ctrl_arb


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_state_flop 100.00 100.00 100.00



Module Instance : tb.dut.u_flash_hw_if.u_state_regs

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
96.96 100.00 93.75 92.11 98.94 100.00 u_flash_hw_if


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_state_flop 100.00 100.00 100.00



Module Instance : tb.dut.u_flash_hw_if.u_rma_state_regs

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
96.96 100.00 93.75 92.11 98.94 100.00 u_flash_hw_if


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_state_flop 100.00 100.00 100.00



Module Instance : tb.dut.u_prog_tl_gate.u_state_regs

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
78.37 100.00 88.89 57.14 95.83 50.00 u_prog_tl_gate


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_state_flop 100.00 100.00 100.00



Module Instance : tb.dut.u_tl_gate.u_state_regs

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
80.60 100.00 100.00 57.14 95.83 50.00 u_tl_gate


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_state_flop 100.00 100.00 100.00



Module Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_state_regs

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
98.87 100.00 94.34 100.00 100.00 100.00 gen_flash_cores[0].u_core


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_state_flop 100.00 100.00 100.00



Module Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.gen_prog_data.u_prog.u_state_regs

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.69 100.00 98.46 100.00 100.00 100.00 gen_prog_data.u_prog


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_state_flop 100.00 100.00 100.00



Module Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_state_regs

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
96.74 100.00 85.85 100.00 97.83 100.00 gen_flash_cores[1].u_core


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_state_flop 100.00 100.00 100.00



Module Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.gen_prog_data.u_prog.u_state_regs

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.38 100.00 96.92 100.00 100.00 100.00 gen_prog_data.u_prog


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_state_flop 100.00 100.00 100.00

Line Coverage for Module : prim_sparse_fsm_flop
Line No.TotalCoveredPercent
TOTAL66100.00
CONT_ASSIGN4011100.00
CONT_ASSIGN4311100.00
ROUTINE4744100.00

39 ); 40 1/1 assign state_o = StateEnumT'(state_raw); Tests: T1 T2 T3  41 42 `ifdef INC_ASSERT 43 1/1 assign unused_err_o = is_undefined_state(state_o); Tests: T1 T2 T3  44 45 function automatic logic is_undefined_state(StateEnumT sig); 46 // This is written with a vector in order to make it amenable to x-prop analysis. 47 1/1 logic is_defined = 1'b0; Tests: T1 T2 T3  48 1/1 for (int i = 0, StateEnumT t = t.first(); i < t.num(); i += 1, t = t.next()) begin Tests: T1 T2 T3  49 1/1 is_defined |= (sig === t); Tests: T1 T2 T3  50 end 51 1/1 return ~is_defined; Tests: T1 T2 T3 

Assert Coverage for Module : prim_sparse_fsm_flop
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 1 1 100.00 1 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 1 1 100.00 1 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
AssertConnected_A 9378 9378 0 0


AssertConnected_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 9378 9378 0 0
T1 9 9 0 0
T2 9 9 0 0
T3 9 9 0 0
T7 9 9 0 0
T13 9 9 0 0
T14 9 9 0 0
T15 9 9 0 0
T18 9 9 0 0
T19 9 9 0 0
T20 9 9 0 0

Line Coverage for Instance : tb.dut.u_ctrl_arb.u_state_regs
Line No.TotalCoveredPercent
TOTAL66100.00
CONT_ASSIGN4011100.00
CONT_ASSIGN4311100.00
ROUTINE4744100.00

39 ); 40 1/1 assign state_o = StateEnumT'(state_raw); Tests: T1 T2 T3  41 42 `ifdef INC_ASSERT 43 1/1 assign unused_err_o = is_undefined_state(state_o); Tests: T1 T2 T3  44 45 function automatic logic is_undefined_state(StateEnumT sig); 46 // This is written with a vector in order to make it amenable to x-prop analysis. 47 1/1 logic is_defined = 1'b0; Tests: T1 T2 T3  48 1/1 for (int i = 0, StateEnumT t = t.first(); i < t.num(); i += 1, t = t.next()) begin Tests: T1 T2 T3  49 1/1 is_defined |= (sig === t); Tests: T1 T2 T3  50 end 51 1/1 return ~is_defined; Tests: T1 T2 T3 

Assert Coverage for Instance : tb.dut.u_ctrl_arb.u_state_regs
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 1 1 100.00 1 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 1 1 100.00 1 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
AssertConnected_A 1042 1042 0 0


AssertConnected_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1042 1042 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T7 1 1 0 0
T13 1 1 0 0
T14 1 1 0 0
T15 1 1 0 0
T18 1 1 0 0
T19 1 1 0 0
T20 1 1 0 0

Line Coverage for Instance : tb.dut.u_flash_hw_if.u_state_regs
Line No.TotalCoveredPercent
TOTAL66100.00
CONT_ASSIGN4011100.00
CONT_ASSIGN4311100.00
ROUTINE4744100.00

39 ); 40 1/1 assign state_o = StateEnumT'(state_raw); Tests: T1 T2 T3  41 42 `ifdef INC_ASSERT 43 1/1 assign unused_err_o = is_undefined_state(state_o); Tests: T1 T2 T3  44 45 function automatic logic is_undefined_state(StateEnumT sig); 46 // This is written with a vector in order to make it amenable to x-prop analysis. 47 1/1 logic is_defined = 1'b0; Tests: T1 T2 T3  48 1/1 for (int i = 0, StateEnumT t = t.first(); i < t.num(); i += 1, t = t.next()) begin Tests: T1 T2 T3  49 1/1 is_defined |= (sig === t); Tests: T1 T2 T3  50 end 51 1/1 return ~is_defined; Tests: T1 T2 T3 

Assert Coverage for Instance : tb.dut.u_flash_hw_if.u_state_regs
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 1 1 100.00 1 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 1 1 100.00 1 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
AssertConnected_A 1042 1042 0 0


AssertConnected_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1042 1042 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T7 1 1 0 0
T13 1 1 0 0
T14 1 1 0 0
T15 1 1 0 0
T18 1 1 0 0
T19 1 1 0 0
T20 1 1 0 0

Line Coverage for Instance : tb.dut.u_flash_hw_if.u_rma_state_regs
Line No.TotalCoveredPercent
TOTAL66100.00
CONT_ASSIGN4011100.00
CONT_ASSIGN4311100.00
ROUTINE4744100.00

39 ); 40 1/1 assign state_o = StateEnumT'(state_raw); Tests: T1 T2 T3  41 42 `ifdef INC_ASSERT 43 1/1 assign unused_err_o = is_undefined_state(state_o); Tests: T1 T2 T3  44 45 function automatic logic is_undefined_state(StateEnumT sig); 46 // This is written with a vector in order to make it amenable to x-prop analysis. 47 1/1 logic is_defined = 1'b0; Tests: T1 T2 T3  48 1/1 for (int i = 0, StateEnumT t = t.first(); i < t.num(); i += 1, t = t.next()) begin Tests: T1 T2 T3  49 1/1 is_defined |= (sig === t); Tests: T1 T2 T3  50 end 51 1/1 return ~is_defined; Tests: T1 T2 T3 

Assert Coverage for Instance : tb.dut.u_flash_hw_if.u_rma_state_regs
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 1 1 100.00 1 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 1 1 100.00 1 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
AssertConnected_A 1042 1042 0 0


AssertConnected_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1042 1042 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T7 1 1 0 0
T13 1 1 0 0
T14 1 1 0 0
T15 1 1 0 0
T18 1 1 0 0
T19 1 1 0 0
T20 1 1 0 0

Line Coverage for Instance : tb.dut.u_prog_tl_gate.u_state_regs
Line No.TotalCoveredPercent
TOTAL66100.00
CONT_ASSIGN4011100.00
CONT_ASSIGN4311100.00
ROUTINE4744100.00

39 ); 40 1/1 assign state_o = StateEnumT'(state_raw); Tests: T1 T2 T3  41 42 `ifdef INC_ASSERT 43 1/1 assign unused_err_o = is_undefined_state(state_o); Tests: T1 T2 T3  44 45 function automatic logic is_undefined_state(StateEnumT sig); 46 // This is written with a vector in order to make it amenable to x-prop analysis. 47 1/1 logic is_defined = 1'b0; Tests: T1 T2 T3  48 1/1 for (int i = 0, StateEnumT t = t.first(); i < t.num(); i += 1, t = t.next()) begin Tests: T1 T2 T3  49 1/1 is_defined |= (sig === t); Tests: T1 T2 T3  50 end 51 1/1 return ~is_defined; Tests: T1 T2 T3 

Assert Coverage for Instance : tb.dut.u_prog_tl_gate.u_state_regs
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 1 1 100.00 1 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 1 1 100.00 1 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
AssertConnected_A 1042 1042 0 0


AssertConnected_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1042 1042 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T7 1 1 0 0
T13 1 1 0 0
T14 1 1 0 0
T15 1 1 0 0
T18 1 1 0 0
T19 1 1 0 0
T20 1 1 0 0

Line Coverage for Instance : tb.dut.u_tl_gate.u_state_regs
Line No.TotalCoveredPercent
TOTAL66100.00
CONT_ASSIGN4011100.00
CONT_ASSIGN4311100.00
ROUTINE4744100.00

39 ); 40 1/1 assign state_o = StateEnumT'(state_raw); Tests: T1 T2 T3  41 42 `ifdef INC_ASSERT 43 1/1 assign unused_err_o = is_undefined_state(state_o); Tests: T1 T2 T3  44 45 function automatic logic is_undefined_state(StateEnumT sig); 46 // This is written with a vector in order to make it amenable to x-prop analysis. 47 1/1 logic is_defined = 1'b0; Tests: T1 T2 T3  48 1/1 for (int i = 0, StateEnumT t = t.first(); i < t.num(); i += 1, t = t.next()) begin Tests: T1 T2 T3  49 1/1 is_defined |= (sig === t); Tests: T1 T2 T3  50 end 51 1/1 return ~is_defined; Tests: T1 T2 T3 

Assert Coverage for Instance : tb.dut.u_tl_gate.u_state_regs
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 1 1 100.00 1 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 1 1 100.00 1 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
AssertConnected_A 1042 1042 0 0


AssertConnected_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1042 1042 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T7 1 1 0 0
T13 1 1 0 0
T14 1 1 0 0
T15 1 1 0 0
T18 1 1 0 0
T19 1 1 0 0
T20 1 1 0 0

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_state_regs
Line No.TotalCoveredPercent
TOTAL66100.00
CONT_ASSIGN4011100.00
CONT_ASSIGN4311100.00
ROUTINE4744100.00

39 ); 40 1/1 assign state_o = StateEnumT'(state_raw); Tests: T1 T2 T3  41 42 `ifdef INC_ASSERT 43 1/1 assign unused_err_o = is_undefined_state(state_o); Tests: T1 T2 T3  44 45 function automatic logic is_undefined_state(StateEnumT sig); 46 // This is written with a vector in order to make it amenable to x-prop analysis. 47 1/1 logic is_defined = 1'b0; Tests: T1 T2 T3  48 1/1 for (int i = 0, StateEnumT t = t.first(); i < t.num(); i += 1, t = t.next()) begin Tests: T1 T2 T3  49 1/1 is_defined |= (sig === t); Tests: T1 T2 T3  50 end 51 1/1 return ~is_defined; Tests: T1 T2 T3 

Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_state_regs
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 1 1 100.00 1 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 1 1 100.00 1 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
AssertConnected_A 1042 1042 0 0


AssertConnected_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1042 1042 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T7 1 1 0 0
T13 1 1 0 0
T14 1 1 0 0
T15 1 1 0 0
T18 1 1 0 0
T19 1 1 0 0
T20 1 1 0 0

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.gen_prog_data.u_prog.u_state_regs
Line No.TotalCoveredPercent
TOTAL66100.00
CONT_ASSIGN4011100.00
CONT_ASSIGN4311100.00
ROUTINE4744100.00

39 ); 40 1/1 assign state_o = StateEnumT'(state_raw); Tests: T1 T2 T3  41 42 `ifdef INC_ASSERT 43 1/1 assign unused_err_o = is_undefined_state(state_o); Tests: T1 T2 T3  44 45 function automatic logic is_undefined_state(StateEnumT sig); 46 // This is written with a vector in order to make it amenable to x-prop analysis. 47 1/1 logic is_defined = 1'b0; Tests: T1 T2 T3  48 1/1 for (int i = 0, StateEnumT t = t.first(); i < t.num(); i += 1, t = t.next()) begin Tests: T1 T2 T3  49 1/1 is_defined |= (sig === t); Tests: T1 T2 T3  50 end 51 1/1 return ~is_defined; Tests: T1 T2 T3 

Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.gen_prog_data.u_prog.u_state_regs
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 1 1 100.00 1 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 1 1 100.00 1 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
AssertConnected_A 1042 1042 0 0


AssertConnected_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1042 1042 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T7 1 1 0 0
T13 1 1 0 0
T14 1 1 0 0
T15 1 1 0 0
T18 1 1 0 0
T19 1 1 0 0
T20 1 1 0 0

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_state_regs
Line No.TotalCoveredPercent
TOTAL66100.00
CONT_ASSIGN4011100.00
CONT_ASSIGN4311100.00
ROUTINE4744100.00

39 ); 40 1/1 assign state_o = StateEnumT'(state_raw); Tests: T1 T2 T3  41 42 `ifdef INC_ASSERT 43 1/1 assign unused_err_o = is_undefined_state(state_o); Tests: T1 T2 T3  44 45 function automatic logic is_undefined_state(StateEnumT sig); 46 // This is written with a vector in order to make it amenable to x-prop analysis. 47 1/1 logic is_defined = 1'b0; Tests: T1 T2 T3  48 1/1 for (int i = 0, StateEnumT t = t.first(); i < t.num(); i += 1, t = t.next()) begin Tests: T1 T2 T3  49 1/1 is_defined |= (sig === t); Tests: T1 T2 T3  50 end 51 1/1 return ~is_defined; Tests: T1 T2 T3 

Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_state_regs
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 1 1 100.00 1 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 1 1 100.00 1 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
AssertConnected_A 1042 1042 0 0


AssertConnected_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1042 1042 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T7 1 1 0 0
T13 1 1 0 0
T14 1 1 0 0
T15 1 1 0 0
T18 1 1 0 0
T19 1 1 0 0
T20 1 1 0 0

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.gen_prog_data.u_prog.u_state_regs
Line No.TotalCoveredPercent
TOTAL66100.00
CONT_ASSIGN4011100.00
CONT_ASSIGN4311100.00
ROUTINE4744100.00

39 ); 40 1/1 assign state_o = StateEnumT'(state_raw); Tests: T1 T2 T3  41 42 `ifdef INC_ASSERT 43 1/1 assign unused_err_o = is_undefined_state(state_o); Tests: T1 T2 T3  44 45 function automatic logic is_undefined_state(StateEnumT sig); 46 // This is written with a vector in order to make it amenable to x-prop analysis. 47 1/1 logic is_defined = 1'b0; Tests: T1 T2 T3  48 1/1 for (int i = 0, StateEnumT t = t.first(); i < t.num(); i += 1, t = t.next()) begin Tests: T1 T2 T3  49 1/1 is_defined |= (sig === t); Tests: T1 T2 T3  50 end 51 1/1 return ~is_defined; Tests: T1 T2 T3 

Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.gen_prog_data.u_prog.u_state_regs
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 1 1 100.00 1 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 1 1 100.00 1 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
AssertConnected_A 1042 1042 0 0


AssertConnected_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1042 1042 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T7 1 1 0 0
T13 1 1 0 0
T14 1 1 0 0
T15 1 1 0 0
T18 1 1 0 0
T19 1 1 0 0
T20 1 1 0 0

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