Unified Coverage Report :: Module :: flash_ctrl_lcmgr

Module : flash_ctrl_lcmgr

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.96	100.00	93.75		92.11	98.94	100.00

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/sim-vcs/../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_ctrl_lcmgr.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_flash_hw_if	96.96	100.00	93.75		92.11	98.94	100.00

---

Module Instance : tb.dut.u_flash_hw_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.96	100.00	93.75		92.11	98.94	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.49	99.27	94.44	95.83	92.11	97.30	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
94.85	97.12	94.40	98.44		100.00	84.29	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_addr_cnt	100.00			100.00
u_addr_sync_reqack	96.46	95.83	100.00			90.00	100.00
u_bus_intg	100.00	100.00
u_data_intg_chk	100.00	100.00		100.00
u_data_sync_reqack	98.23	97.92	100.00			95.00	100.00
u_page_cnt	78.79			78.79
u_prim_flop_err_sts	100.00	100.00				100.00
u_rma_state_regs	100.00	100.00				100.00	100.00
u_seed_cnt	100.00			100.00
u_state_regs	100.00	100.00				100.00	100.00
u_sync_flash_init	100.00	100.00				100.00
u_sync_rma_req	100.00	100.00				100.00	100.00
u_wipe_idx_cnt	100.00			100.00
u_word_cnt	100.00			100.00

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : flash_ctrl_lcmgr

	Line No.	Total	Covered	Percent
TOTAL		242	242	100.00
CONT_ASSIGN	149	1	1	100.00
ALWAYS	152	3	3	100.00
CONT_ASSIGN	170	1	1	100.00
CONT_ASSIGN	171	1	1	100.00
ALWAYS	174	7	7	100.00
CONT_ASSIGN	185	1	1	100.00
ALWAYS	227	5	5	100.00
CONT_ASSIGN	243	1	1	100.00
CONT_ASSIGN	247	1	1	100.00
ALWAYS	251	3	3	100.00
CONT_ASSIGN	261	1	1	100.00
CONT_ASSIGN	262	1	1	100.00
ALWAYS	264	6	6	100.00
CONT_ASSIGN	278	1	1	100.00
CONT_ASSIGN	279	1	1	100.00
CONT_ASSIGN	280	1	1	100.00
ALWAYS	359	9	9	100.00
CONT_ASSIGN	380	1	1	100.00
ALWAYS	386	85	85	100.00
CONT_ASSIGN	607	1	1	100.00
ALWAYS	613	3	3	100.00
ALWAYS	673	7	7	100.00
ALWAYS	688	10	10	100.00
ALWAYS	705	2	2	100.00
CONT_ASSIGN	714	1	1	100.00
CONT_ASSIGN	715	1	1	100.00
CONT_ASSIGN	737	1	1	100.00
CONT_ASSIGN	741	1	1	100.00
CONT_ASSIGN	742	1	1	100.00
CONT_ASSIGN	754	1	1	100.00
ALWAYS	761	66	66	100.00
CONT_ASSIGN	891	1	1	100.00
CONT_ASSIGN	892	1	1	100.00
CONT_ASSIGN	893	1	1	100.00
CONT_ASSIGN	894	0	0
CONT_ASSIGN	895	0	0
CONT_ASSIGN	896	1	1	100.00
CONT_ASSIGN	897	1	1	100.00
CONT_ASSIGN	898	1	1	100.00
CONT_ASSIGN	900	1	1	100.00
CONT_ASSIGN	902	1	1	100.00
CONT_ASSIGN	905	1	1	100.00
CONT_ASSIGN	906	1	1	100.00
CONT_ASSIGN	908	1	1	100.00
CONT_ASSIGN	909	1	1	100.00
CONT_ASSIGN	911	1	1	100.00
CONT_ASSIGN	914	1	1	100.00
CONT_ASSIGN	918	1	1	100.00
CONT_ASSIGN	921	1	1	100.00
ALWAYS	932	0	0
CONT_ASSIGN	939	1	1	100.00

Click here to see the source line report.

---

Cond Coverage for Module : flash_ctrl_lcmgr

	Total	Covered	Percent
Conditions	96	90	93.75
Logical	96	90	93.75
Non-Logical	0	0
Event	0	0

 LINE       170
 EXPRESSION (phase == PhaseSeed)
            ----------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       171
 EXPRESSION (phase == PhaseRma)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T7,T93,T117

 LINE       185
 EXPRESSION (seed_err_q | seed_err_d)
             -----1----   -----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T7,T178,T179
1	0	Not Covered

 LINE       231
 EXPRESSION (addr_cnt_err_q | addr_cnt_err_d)
             -------1------   -------2------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T16,T17,T53
1	0	Covered	T16,T17,T53

 LINE       232
 EXPRESSION (seed_cnt_err_q | seed_cnt_err_d)
             -------1------   -------2------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T16,T17,T53
1	0	Covered	T16,T17,T53

 LINE       247
 EXPRESSION (data_invalid_q | (rvalid_i & ((~data_intg_ok))))
             -------1------   ---------------2--------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T123,T180,T181
1	0	Covered	T123,T180,T181

 LINE       247
 SUB-EXPRESSION (rvalid_i & ((~data_intg_ok)))
                 ----1---   --------2--------

-1-	-2-	Status	Tests
0	1	Covered	T123,T180,T181
1	0	Covered	T1,T2,T3
1	1	Covered	T123,T180,T181

 LINE       266
 EXPRESSION (seed_phase && validate_q && rvalid_i)
             -----1----    -----2----    ----3---

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T1,T2,T3
1	1	1	Covered	T1,T2,T3

 LINE       270
 EXPRESSION (seed_phase && rvalid_i)
             -----1----    ----2---

-1-	-2-	Status	Tests
0	1	Covered	T93,T118,T158
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       363
 EXPRESSION (addr_key_req_d && addr_key_ack_q)
             -------1------    -------2------

-1-	-2-	Status	Tests
0	1	Covered	T182,T171,T183
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       368
 EXPRESSION (data_key_req_d && data_key_ack_q)
             -------1------    -------2------

-1-	-2-	Status	Tests
0	1	Covered	T119,T174,T184
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       457
 EXPRESSION (provision_en_i ? StReadSeeds : StWait)
             -------1------

-1-	Status	Tests
0	Covered	T185,T174,T186
1	Covered	T1,T2,T3

 LINE       473
 EXPRESSION (seed_cnt_q == flash_ctrl_pkg::NumSeeds)
            --------------------1-------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       516
 EXPRESSION ((rma_wipe_idx == MaxWipeEntry[(WipeIdxWidth - 1):0]) && rma_wipe_done)
             --------------------------1-------------------------    ------2------

-1-	-2-	Status	Tests
0	1	Covered	T93,T118,T122
1	0	Covered	T118,T122,T85
1	1	Covered	T118,T122,T85

 LINE       516
 SUB-EXPRESSION (rma_wipe_idx == MaxWipeEntry[(WipeIdxWidth - 1):0])
                --------------------------1-------------------------

-1-	Status	Tests
0	Covered	T7,T93,T117
1	Covered	T118,T122,T85

 LINE       678
 EXPRESSION (page_err_q | page_err_d)
             -----1----   -----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T16,T17,T53
1	0	Covered	T16,T17,T53

 LINE       679
 EXPRESSION (word_err_q | word_err_d)
             -----1----   -----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T16,T17,T53
1	0	Covered	T16,T17,T53

 LINE       680
 EXPRESSION (rma_idx_err_q | rma_idx_err_d)
             ------1------   ------2------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T16,T17,T53
1	0	Covered	T16,T17,T53

 LINE       693
 EXPRESSION (wvalid_o && wready_i)
             ----1---    ----2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T118,T187
1	1	Covered	T93,T118,T158

 LINE       697
 EXPRESSION (rvalid_i && rready_o)
             ----1---    ----2---

-1-	-2-	Status	Tests
0	1	Covered	T93,T118,T158
1	0	Unreachable
1	1	Covered	T93,T118,T158

 LINE       705
 EXPRESSION (prog_cnt_en && wvalid_o && wready_i)
             -----1-----    ----2---    ----3---

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Not Covered
1	1	0	Covered	T118,T187
1	1	1	Covered	T93,T118,T158

 LINE       835
 EXPRESSION ((beat_cnt == MaxBeatCnt[(BeatCntWidth - 1):0]) && wready_i)
             -----------------------1----------------------    ----2---

-1-	-2-	Status	Tests
0	1	Covered	T93,T118,T158
1	0	Covered	T118
1	1	Covered	T93,T118,T158

 LINE       835
 SUB-EXPRESSION (beat_cnt == MaxBeatCnt[(BeatCntWidth - 1):0])
                -----------------------1----------------------

-1-	Status	Tests
0	Covered	T93,T118,T158
1	Covered	T93,T118,T158

 LINE       856
 EXPRESSION ((beat_cnt == MaxBeatCnt[(BeatCntWidth - 1):0]) && done_i)
             -----------------------1----------------------    ---2--

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T93,T118,T158
1	1	Covered	T93,T118,T158

 LINE       856
 SUB-EXPRESSION (beat_cnt == MaxBeatCnt[(BeatCntWidth - 1):0])
                -----------------------1----------------------

-1-	Status	Tests
0	Covered	T93,T118,T158
1	Covered	T93,T118,T158

 LINE       862
 EXPRESSION (rvalid_i && rready_o)
             ----1---    ----2---

-1-	-2-	Status	Tests
0	1	Covered	T93,T118,T158
1	0	Unreachable
1	1	Covered	T93,T118,T158

 LINE       863
 EXPRESSION (prog_data[beat_cnt] != rdata_i[(flash_ctrl_pkg::BusWidth - 1):0])
            ---------------------------------1--------------------------------

-1-	Status	Tests
0	Covered	T118,T158,T122
1	Covered	T93,T85,T88

 LINE       892
 EXPRESSION (seed_phase ? start : rma_start)
             -----1----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       893
 EXPRESSION (seed_phase ? op : rma_op)
             -----1----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       896
 EXPRESSION (seed_phase ? part_sel : rma_part_sel)
             -----1----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       897
 EXPRESSION (seed_phase ? info_sel : rma_info_sel)
             -----1----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       898
 EXPRESSION (seed_phase ? num_words : rma_num_words)
             -----1----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       900
 EXPRESSION (seed_phase ? ({addr, {flash_ctrl_pkg::BusByteWidth {1'b0}}}) : ({rma_addr, {flash_ctrl_pkg::BusByteWidth {1'b0}}}))
             -----1----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       906
 EXPRESSION (seed_phase | rma_phase)
             -----1----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T7,T93,T117
1	0	Covered	T1,T2,T3

 LINE       914
 EXPRESSION (page_err_q | word_err_q | fsm_err | state_err | rma_idx_err_q | addr_cnt_err_q | seed_cnt_err_q)
             -----1----   -----2----   ---3---   ----4----   ------5------   -------6------   -------7------

-1-	-2-	-3-	-4-	-5-	-6-	-7-	Status	Tests
0	0	0	0	0	0	0	Covered	T1,T2,T3
0	0	0	0	0	0	1	Covered	T16,T17,T53
0	0	0	0	0	1	0	Covered	T16,T17,T53
0	0	0	0	1	0	0	Covered	T16,T17,T53
0	0	0	1	0	0	0	Covered	T85,T88,T177
0	0	1	0	0	0	0	Covered	T16,T17,T53
0	1	0	0	0	0	0	Covered	T16,T17,T53
1	0	0	0	0	0	0	Covered	T16,T17,T53

---

FSM Coverage for Module : flash_ctrl_lcmgr

Summary for FSM :: state_q

	Total	Covered	Percent
States	11	11	100.00	(Not included in score)
Transitions	25	23	92.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
StDisabled	545	Covered	T7,T8,T9
StEntropyReseed	499	Covered	T7,T93,T117
StIdle	432	Covered	T1,T2,T3
StInvalid	520	Covered	T85,T88,T177
StReadEval	478	Covered	T1,T2,T3
StReadSeeds	457	Covered	T1,T2,T3
StReqAddrKey	436	Covered	T1,T2,T3
StReqDataKey	446	Covered	T1,T2,T3
StRmaRsp	520	Covered	T118,T122,T87
StRmaWipe	434	Covered	T7,T93,T117
StWait	457	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests
StEntropyReseed->StDisabled	572	Covered	T7,T119,T174
StEntropyReseed->StRmaWipe	507	Covered	T7,T93,T117
StIdle->StDisabled	572	Covered	T16,T17,T53
StIdle->StReqAddrKey	436	Covered	T1,T2,T3
StIdle->StRmaWipe	434	Covered	T93,T158,T170
StInvalid->StDisabled	572	Not Covered
StReadEval->StDisabled	572	Covered	T174,T188,T189
StReadEval->StReadSeeds	485	Covered	T1,T2,T3
StReadSeeds->StDisabled	572	Covered	T123,T180,T181
StReadSeeds->StReadEval	478	Covered	T1,T2,T3
StReadSeeds->StWait	475	Covered	T1,T2,T3
StReqAddrKey->StDisabled	572	Covered	T182,T171,T183
StReqAddrKey->StReqDataKey	446	Covered	T1,T2,T3
StReqAddrKey->StRmaWipe	444	Covered	T171,T172,T173
StReqDataKey->StDisabled	572	Covered	T119,T184,T190
StReqDataKey->StReadSeeds	457	Covered	T1,T2,T3
StReqDataKey->StRmaWipe	454	Covered	T174,T175,T176
StReqDataKey->StWait	457	Covered	T185,T174,T186
StRmaRsp->StDisabled	572	Covered	T120
StRmaRsp->StInvalid	534	Not Covered
StRmaWipe->StDisabled	572	Covered	T117,T118,T158
StRmaWipe->StInvalid	520	Covered	T85,T88,T177
StRmaWipe->StRmaRsp	520	Covered	T118,T122,T87
StWait->StDisabled	572	Covered	T8,T9,T10
StWait->StEntropyReseed	499	Covered	T7,T93,T117

Summary for FSM :: rma_state_q

	Total	Covered	Percent
States	10	10	100.00	(Not included in score)
Transitions	13	12	92.31
Sequences	0	0

State, Transition and Sequence Details for FSM :: rma_state_q

---

states	Line No.	Covered	Tests
StRmaDisabled	785	Covered	T7,T8,T9
StRmaErase	796	Covered	T7,T93,T117
StRmaEraseWait	809	Covered	T93,T117,T118
StRmaIdle	800	Covered	T1,T2,T3
StRmaInvalid	872	Covered	T16,T17,T53
StRmaPageSel	787	Covered	T7,T93,T117
StRmaProgram	822	Covered	T93,T118,T158
StRmaProgramWait	836	Covered	T93,T118,T158
StRmaRdVerify	847	Covered	T93,T118,T158
StRmaWordSel	815	Covered	T93,T117,T118

transitions	Line No.	Covered	Tests
StRmaErase->StRmaEraseWait	809	Covered	T93,T117,T118
StRmaEraseWait->StRmaWordSel	815	Covered	T93,T117,T118
StRmaIdle->StRmaDisabled	785	Covered	T7,T8,T9
StRmaIdle->StRmaPageSel	787	Covered	T7,T93,T117
StRmaPageSel->StRmaDisabled	794	Not Covered
StRmaPageSel->StRmaErase	796	Covered	T7,T93,T117
StRmaPageSel->StRmaIdle	800	Covered	T93,T118,T122
StRmaProgram->StRmaProgramWait	836	Covered	T93,T118,T158
StRmaProgramWait->StRmaRdVerify	847	Covered	T93,T118,T158
StRmaRdVerify->StRmaWordSel	859	Covered	T93,T118,T158
StRmaWordSel->StRmaDisabled	820	Covered	T117,T119,T191
StRmaWordSel->StRmaPageSel	826	Covered	T93,T118,T122
StRmaWordSel->StRmaProgram	822	Covered	T93,T118,T158

---

Branch Coverage for Module : flash_ctrl_lcmgr

	Line No.	Total	Covered	Percent
Branches		94	93	98.94
TERNARY	892	2	2	100.00
TERNARY	893	2	2	100.00
TERNARY	896	2	2	100.00
TERNARY	897	2	2	100.00
TERNARY	898	2	2	100.00
TERNARY	900	2	2	100.00
IF	152	2	2	100.00
IF	174	2	2	100.00
IF	227	2	2	100.00
IF	251	2	2	100.00
IF	264	4	4	100.00
IF	359	5	5	100.00
CASE	427	27	26	96.30
IF	569	2	2	100.00
IF	613	2	2	100.00
IF	673	2	2	100.00
IF	688	7	7	100.00
IF	705	2	2	100.00
CASE	777	23	23	100.00

892          assign ctrl_o.start.q = seed_phase ? start : rma_start;
                                                -1-  
                                                ==>  
                                                ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

893          assign ctrl_o.op.q = seed_phase ? op : rma_op;
                                             -1-  
                                             ==>  
                                             ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

896          assign ctrl_o.partition_sel.q = seed_phase ? part_sel : rma_part_sel;
                                                        -1-  
                                                        ==>  
                                                        ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

897          assign ctrl_o.info_sel.q = seed_phase ? info_sel : rma_info_sel;
                                                   -1-  
                                                   ==>  
                                                   ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

898          assign ctrl_o.num = seed_phase ? num_words : rma_num_words;
                                            -1-  
                                            ==>  
                                            ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

900          assign addr_o = seed_phase ? {addr, {BusByteWidth{1'b0}}} :
                                        -1-  
                                        ==>  
                                        ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

152          `PRIM_FLOP_SPARSE_FSM(u_state_regs, state_d, state_q, lcmgr_state_e, StIdle)
             -1-                                                                            
             ==>                                                                            
             ==>                                                                            

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

174            if (!rst_ni) begin
               -1-  
175              rma_ack_q <= lc_ctrl_pkg::Off;
                 ==>
176              validate_q <= 1'b0;
177              seed_err_q <= '0;
178            end else begin
179              rma_ack_q <= rma_ack_d;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

227            if (!rst_ni) begin
               -1-  
228              addr_cnt_err_q <= '0;
                 ==>
229              seed_cnt_err_q <= '0;
230            end else begin
231              addr_cnt_err_q <= addr_cnt_err_q | addr_cnt_err_d;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

251            if (!rst_ni) begin
               -1-  
252              data_invalid_q <= '0;
                 ==>
253            end else begin
254              data_invalid_q <= data_invalid_d;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

264            if (!rst_ni) begin
               -1-  
265              seeds_q <= RndCnstAllSeeds;
                 ==>
266            end else if (seed_phase && validate_q && rvalid_i) begin
                        -2-  
267              // validate current value
268              seeds_q[seed_idx][rd_idx] <= seeds_q[seed_idx][rd_idx] &
                 ==>
269                                           rdata_i[BusWidth-1:0];
270            end else if (seed_phase && rvalid_i) begin
                        -3-  
271              seeds_q[seed_idx][rd_idx] <= rdata_i[BusWidth-1:0];
                 ==>
272            end
               MISSING_ELSE
               ==>

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

359            if (!rst_ni) begin
               -1-  
360              addr_key_o <= RndCnstAddrKey;
                 ==>
361              data_key_o <= RndCnstDataKey;
362            end else begin
363              if (addr_key_req_d && addr_key_ack_q) begin
                 -2-  
364                addr_key_o <= flash_key_t'(otp_key_rsp_i.key);
                   ==>
365                rand_addr_key_o <= flash_key_t'(otp_key_rsp_i.rand_key);
366              end
                 MISSING_ELSE
                 ==>
367        
368              if (data_key_req_d && data_key_ack_q) begin
                 -3-  
369                data_key_o <= flash_key_t'(otp_key_rsp_i.key);
                   ==>
370                rand_data_key_o <= flash_key_t'(otp_key_rsp_i.rand_key);
371              end
                 MISSING_ELSE
                 ==>

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	-	Covered	T1,T2,T3
0	-	1	Covered	T1,T2,T3
0	-	0	Covered	T1,T2,T3

427            unique case (state_q)
                      -1-  
428        
429              // If rma request is seen, directly transition to wipe.
430              // Since init has not been called, there are no guarantees
431              // to entropy behavior, thus do not reseed
432              StIdle: begin
433                if (lc_tx_test_true_strict(rma_req[RmaReqInit])) begin
                   -2-  
434                  state_d = StRmaWipe;
                     ==>
435                end else if (init_q) begin
                            -3-  
436                  state_d = StReqAddrKey;
                     ==>
437                end
                   MISSING_ELSE
                   ==>
438              end
439        
440              StReqAddrKey: begin
441                phase = PhaseSeed;
442                addr_key_req_d = 1'b1;
443                if (lc_tx_test_true_strict(rma_req[RmaReqKey])) begin
                   -4-  
444                  state_d = StRmaWipe;
                     ==>
445                end else if (addr_key_ack_q) begin
                            -5-  
446                  state_d = StReqDataKey;
                     ==>
447                end
                   MISSING_ELSE
                   ==>
448              end
449        
450              StReqDataKey: begin
451                phase = PhaseSeed;
452                data_key_req_d = 1'b1;
453                if (lc_tx_test_true_strict(rma_req[RmaReqKey])) begin
                   -6-  
454                  state_d = StRmaWipe;
                     ==>
455                end else if (data_key_ack_q) begin
                            -7-  
456                  // provision_en is only a "good" value after otp/lc initialization
457                  state_d = provision_en_i ? StReadSeeds : StWait;
                                              -8-  
                                              ==>  
                                              ==>  
458                end
                   MISSING_ELSE
                   ==>
459              end
460        
461              // read seeds
462              StReadSeeds: begin
463                // seeds can be updated in this state
464                phase = PhaseSeed;
465        
466                // kick off flash transaction
467                start = 1'b1;
468                addr = BusAddrW'(seed_page_addr);
469                info_sel = seed_info_sel;
470        
471                // we have checked all seeds, proceed
472                addr_cnt_en = rvalid_i;
473                if (seed_cnt_q == NumSeeds) begin
                   -9-  
474                  start = 1'b0;
                     ==>
475                  state_d = StWait;
476                end else if (done_i) begin
                            -10-  
477                  seed_err_d = |err_i;
                     ==>
478                  state_d = StReadEval;
479                end
                   MISSING_ELSE
                   ==>
480              end // case: StReadSeeds
481        
482              StReadEval: begin
483                phase = PhaseSeed;
484                addr_cnt_clr = 1'b1;
485                state_d = StReadSeeds;
486        
487                if (validate_q) begin
                   -11-  
488                  seed_cnt_en = 1'b1;
                     ==>
489                  validate_d = 1'b0;
490                end else begin
491                  validate_d = 1'b1;
                     ==>
492                end
493              end
494        
495              // Waiting for an rma entry command
496              StWait: begin
497                rd_buf_en_o = 1'b1;
498                if (lc_tx_test_true_strict(rma_req[RmaReqWait])) begin
                   -12-  
499                  state_d = StEntropyReseed;
                     ==>
500                end
                   MISSING_ELSE
                   ==>
501              end
502        
503              // Reseed entropy
504              StEntropyReseed: begin
505                edn_req_o = 1'b1;
506                if(edn_ack_i) begin
                   -13-  
507                  state_d = StRmaWipe;
                     ==>
508                end
                   MISSING_ELSE
                   ==>
509              end
510        
511              StRmaWipe: begin
512                phase = PhaseRma;
513                lfsr_en_o = 1'b1;
514                rma_wipe_req = 1'b1;
515        
516                if (rma_wipe_idx == MaxWipeEntry[WipeIdxWidth-1:0] && rma_wipe_done) begin
                   -14-  
517                  // first check for error status
518                  // If error status is set, go directly to invalid terminal state
519                  // If error status is good, go to second check
520                  state_d = lc_ctrl_pkg::lc_tx_test_false_loose(err_sts_q) ? StInvalid : StRmaRsp;
                     ==>
521                end else if (rma_wipe_done) begin
                            -15-  
522                  rma_wipe_idx_incr = 1;
                     ==>
523                end
                   MISSING_ELSE
                   ==>
524              end
525        
526              // response to rma request
527              // Second check for error status:
528              // If error status indicates error, jump to invalid terminal state
529              // Otherwise assign output to error status;
530              StRmaRsp: begin
531                phase = PhaseRma;
532                dis_access_o = lc_ctrl_pkg::On;
533                if (lc_ctrl_pkg::lc_tx_test_false_loose(err_sts_q)) begin
                   -16-  
534                  state_d = StInvalid;
                     ==>
535                end else begin
536                  rma_ack_d = err_sts_q;
                     ==>
537                end
538              end
539        
540              // Disabled state is functionally equivalent to invalid, just without the
541              // the explicit error-ing
542              StDisabled: begin
543                dis_access_o = lc_ctrl_pkg::On;
                   ==>
544                rma_ack_d = lc_ctrl_pkg::Off;
545                state_d = StDisabled;
546              end
547        
548              StInvalid: begin
549                dis_access_o = lc_ctrl_pkg::On;
                   ==>
550                state_err = 1'b1;
551                rma_ack_d = lc_ctrl_pkg::Off;
552                state_d = StInvalid;
553              end
554        
555              // Invalid catch-all state
556              default: begin
557                dis_access_o = lc_ctrl_pkg::On;
                   ==>

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	-15-	-16-	Status	Tests
StIdle	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T93,T158,T170
StIdle	0	1	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
StIdle	0	0	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
StReqAddrKey	-	-	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T171,T172,T173
StReqAddrKey	-	-	0	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
StReqAddrKey	-	-	0	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
StReqDataKey	-	-	-	-	1	-	-	-	-	-	-	-	-	-	-	Covered	T174,T175,T176
StReqDataKey	-	-	-	-	0	1	1	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
StReqDataKey	-	-	-	-	0	1	0	-	-	-	-	-	-	-	-	Covered	T185,T174,T186
StReqDataKey	-	-	-	-	0	0	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
StReadSeeds	-	-	-	-	-	-	-	1	-	-	-	-	-	-	-	Covered	T1,T2,T3
StReadSeeds	-	-	-	-	-	-	-	0	1	-	-	-	-	-	-	Covered	T1,T2,T3
StReadSeeds	-	-	-	-	-	-	-	0	0	-	-	-	-	-	-	Covered	T1,T2,T3
StReadEval	-	-	-	-	-	-	-	-	-	1	-	-	-	-	-	Covered	T1,T2,T3
StReadEval	-	-	-	-	-	-	-	-	-	0	-	-	-	-	-	Covered	T1,T2,T3
StWait	-	-	-	-	-	-	-	-	-	-	1	-	-	-	-	Covered	T7,T93,T117
StWait	-	-	-	-	-	-	-	-	-	-	0	-	-	-	-	Covered	T1,T2,T3
StEntropyReseed	-	-	-	-	-	-	-	-	-	-	-	1	-	-	-	Covered	T7,T93,T117
StEntropyReseed	-	-	-	-	-	-	-	-	-	-	-	0	-	-	-	Not Covered
StRmaWipe	-	-	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T118,T122,T85
StRmaWipe	-	-	-	-	-	-	-	-	-	-	-	-	0	1	-	Covered	T93,T118,T122
StRmaWipe	-	-	-	-	-	-	-	-	-	-	-	-	0	0	-	Covered	T7,T93,T117
StRmaRsp	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T12
StRmaRsp	-	-	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T118,T122,T87
StDisabled	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T7,T8,T9
StInvalid	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T85,T88,T177
default	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T12,T16,T17

569            if (prim_mubi_pkg::mubi4_test_true_loose(disable_i) &&
               -1-  
570                state_d != StInvalid &&
571                !rma_done) begin
572              state_d = StDisabled;
                 ==>
573            end
               MISSING_ELSE
               ==>

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T9
0	Covered	T1,T2,T3

613          `PRIM_FLOP_SPARSE_FSM(u_rma_state_regs, rma_state_d, rma_state_q, rma_state_e, StRmaIdle)
             -1-                                                                                         
             ==>                                                                                         
             ==>                                                                                         

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

673            if (!rst_ni) begin
               -1-  
674              page_err_q <= '0;
                 ==>
675              word_err_q <= '0;
676              rma_idx_err_q <= '0;
677            end else begin
678              page_err_q <= page_err_q | page_err_d;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

688            if (!rst_ni) begin
               -1-  
689              beat_cnt <= '0;
                 ==>
690            end else if (beat_cnt_clr) begin
                        -2-  
691              beat_cnt <= '0;
                 ==>
692            end else if (prog_cnt_en) begin
                        -3-  
693              if (wvalid_o && wready_i) begin
                 -4-  
694                beat_cnt <= beat_cnt + 1'b1;
                   ==>
695              end
                 MISSING_ELSE
                 ==>
696            end else if (rd_cnt_en) begin
                        -5-  
697              if (rvalid_i && rready_o) begin
                 -6-  
698                beat_cnt <= beat_cnt + 1'b1;
                   ==>
699              end
                 MISSING_ELSE
                 ==>
700            end
               MISSING_ELSE
               ==>

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	Status	Tests
1	-	-	-	-	-	Covered	T1,T2,T3
0	1	-	-	-	-	Covered	T93,T118,T158
0	0	1	1	-	-	Covered	T93,T118,T158
0	0	1	0	-	-	Covered	T118,T12,T187
0	0	0	-	1	1	Covered	T93,T118,T158
0	0	0	-	1	0	Covered	T93,T118,T158
0	0	0	-	0	-	Covered	T1,T2,T3

705            if (prog_cnt_en && wvalid_o && wready_i) begin
               -1-  
706              prog_data[beat_cnt] <= rand_i;
                 ==>
707            end
               MISSING_ELSE
               ==>

Branches:

-1-	Status	Tests
1	Covered	T93,T118,T158
0	Covered	T1,T2,T3

777            unique case (rma_state_q)
                      -1-  
778              // Transition to invalid state via disable only when any ongoing stateful
779              // operations are complete. This ensures we do not electrically disturb
780              // any ongoing operation.
781              // This of course cannot be guaranteed if the FSM state is directly disturbed,
782              // and that is considered an extremely invasive attack.
783              StRmaIdle: begin
784                if (prim_mubi_pkg::mubi4_test_true_loose(disable_i)) begin
                   -2-  
785                  rma_state_d = StRmaDisabled;
                     ==>
786                end else if (rma_wipe_req_int) begin
                            -3-  
787                  rma_state_d = StRmaPageSel;
                     ==>
788                  page_cnt_ld = 1'b1;
789                end
                   MISSING_ELSE
                   ==>
790              end
791        
792              StRmaPageSel: begin
793                if (prim_mubi_pkg::mubi4_test_true_loose(disable_i)) begin
                   -4-  
794                  rma_state_d = StRmaDisabled;
                     ==>
795                end else if (page_cnt < end_page) begin
                            -5-  
796                  rma_state_d = StRmaErase;
                     ==>
797                end else begin
798                  rma_wipe_done = 1'b1;
                     ==>
799                  page_cnt_clr = 1'b1;
800                  rma_state_d = StRmaIdle;
801                end
802              end
803        
804              StRmaErase: begin
805                rma_start = 1'b1;
806                rma_op = FlashOpErase;
807                if (done_i) begin
                   -6-  
808                  err_sts_set = |err_i;
                     ==>
809                  rma_state_d = StRmaEraseWait;
810                end
                   MISSING_ELSE
                   ==>
811              end
812        
813              StRmaEraseWait: begin
814                 word_cnt_ld = 1'b1;
                    ==>
815                 rma_state_d = StRmaWordSel;
816              end
817        
818              StRmaWordSel: begin
819                if (prim_mubi_pkg::mubi4_test_true_loose(disable_i)) begin
                   -7-  
820                  rma_state_d = StRmaDisabled;
                     ==>
821                end else if (word_cnt < BusWordsPerPage) begin
                            -8-  
822                  rma_state_d = StRmaProgram;
                     ==>
823                end else begin
824                  word_cnt_clr = 1'b1;
                     ==>
825                  page_cnt_incr = 1'b1;
826                  rma_state_d = StRmaPageSel;
827                end
828              end
829        
830              StRmaProgram: begin
831                rma_start = 1'b1;
832                rma_op = FlashOpProgram;
833                prog_cnt_en = 1'b1;
834        
835                if ((beat_cnt == MaxBeatCnt[BeatCntWidth-1:0]) && wready_i) begin
                   -9-  
836                  rma_state_d = StRmaProgramWait;
                     ==>
837                end
                   MISSING_ELSE
                   ==>
838              end
839        
840              StRmaProgramWait: begin
841                rma_start = 1'b1;
842                rma_op = FlashOpProgram;
843        
844                if (done_i) begin
                   -10-  
845                  beat_cnt_clr = 1'b1;
                     ==>
846                  err_sts_set = |err_i;
847                  rma_state_d = StRmaRdVerify;
848                end
                   MISSING_ELSE
                   ==>
849              end
850        
851              StRmaRdVerify: begin
852                rma_start = 1'b1;
853                rma_op = FlashOpRead;
854                rd_cnt_en = 1'b1;
855        
856                if ((beat_cnt == MaxBeatCnt[BeatCntWidth-1:0]) && done_i) begin
                   -11-  
857                  beat_cnt_clr = 1'b1;
                     ==>
858                  word_cnt_incr = 1'b1;
859                  rma_state_d = StRmaWordSel;
860                end
                   MISSING_ELSE
                   ==>
861        
862                if (rvalid_i && rready_o) begin
                   -12-  
863                  err_sts_set = prog_data[beat_cnt] != rdata_i[BusWidth-1:0];
                     ==>
864                end
                   MISSING_ELSE
                   ==>
865              end
866        
867              StRmaDisabled: begin
868                rma_state_d = StRmaDisabled;
                   ==>
869              end
870        
871              StRmaInvalid: begin
872                rma_state_d = StRmaInvalid;
                   ==>
873                err_sts_set = 1'b1;
874                fsm_err = 1'b1;
875              end
876        
877              default: begin
878                rma_state_d = StRmaInvalid;
                   ==>

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	Status	Tests
StRmaIdle	1	-	-	-	-	-	-	-	-	-	-	Covered	T7,T8,T9
StRmaIdle	0	1	-	-	-	-	-	-	-	-	-	Covered	T7,T93,T117
StRmaIdle	0	0	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
StRmaPageSel	-	-	1	-	-	-	-	-	-	-	-	Covered	T12
StRmaPageSel	-	-	0	1	-	-	-	-	-	-	-	Covered	T7,T93,T117
StRmaPageSel	-	-	0	0	-	-	-	-	-	-	-	Covered	T93,T118,T122
StRmaErase	-	-	-	-	1	-	-	-	-	-	-	Covered	T93,T117,T118
StRmaErase	-	-	-	-	0	-	-	-	-	-	-	Covered	T7,T93,T117
StRmaEraseWait	-	-	-	-	-	-	-	-	-	-	-	Covered	T93,T117,T118
StRmaWordSel	-	-	-	-	-	1	-	-	-	-	-	Covered	T117,T119,T12
StRmaWordSel	-	-	-	-	-	0	1	-	-	-	-	Covered	T93,T118,T158
StRmaWordSel	-	-	-	-	-	0	0	-	-	-	-	Covered	T93,T118,T122
StRmaProgram	-	-	-	-	-	-	-	1	-	-	-	Covered	T93,T118,T158
StRmaProgram	-	-	-	-	-	-	-	0	-	-	-	Covered	T93,T118,T158
StRmaProgramWait	-	-	-	-	-	-	-	-	1	-	-	Covered	T93,T118,T158
StRmaProgramWait	-	-	-	-	-	-	-	-	0	-	-	Covered	T118,T158,T122
StRmaRdVerify	-	-	-	-	-	-	-	-	-	1	-	Covered	T93,T118,T158
StRmaRdVerify	-	-	-	-	-	-	-	-	-	0	-	Covered	T93,T118,T158
StRmaRdVerify	-	-	-	-	-	-	-	-	-	-	1	Covered	T93,T118,T158
StRmaRdVerify	-	-	-	-	-	-	-	-	-	-	0	Covered	T93,T118,T158
StRmaDisabled	-	-	-	-	-	-	-	-	-	-	-	Covered	T7,T8,T9
StRmaInvalid	-	-	-	-	-	-	-	-	-	-	-	Covered	T12,T16,T17
default	-	-	-	-	-	-	-	-	-	-	-	Covered	T12,T16,T17

---

Assert Coverage for Module : flash_ctrl_lcmgr

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DisableChk_A	372733529	7754052	0	41
ProgRdVerify_A	372082196	2043553	0	0
u_rma_state_regs_A	384864519	384030917	0	0
u_state_regs_A	384864519	384030917	0	0

DisableChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	372733529	7754052	0	41
T7	4246	1	0	0
T8	0	135	0	1
T9	0	311	0	1
T10	0	559	0	0
T11	0	555	0	0
T15	3415	0	0	0
T22	0	320	0	1
T23	0	0	0	1
T32	911208	0	0	0
T48	98505	0	0	0
T49	82218	0	0	0
T52	56734	0	0	0
T65	1935	0	0	0
T66	3620	0	0	0
T71	248442	0	0	0
T86	0	0	0	1
T104	2132	0	0	0
T107	0	0	0	1
T108	0	0	0	1
T110	0	0	0	1
T117	0	10	0	0
T118	0	10	0	0
T123	0	3	0	0
T168	0	224	0	1
T192	0	0	0	1

ProgRdVerify_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	372082196	2043553	0	0
T31	199580	0	0	0
T87	0	131840	0	0
T103	49676	0	0	0
T118	401199	65920	0	0
T120	0	65920	0	0
T121	0	131840	0	0
T122	0	65920	0	0
T143	379744	0	0	0
T158	0	1	0	0
T170	0	4	0	0
T193	0	65920	0	0
T194	0	65920	0	0
T195	0	65920	0	0
T196	59072	0	0	0
T197	1355	0	0	0
T198	60575	0	0	0
T199	229353	0	0	0
T200	77106	0	0	0
T201	52405	0	0	0

u_rma_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	384864519	384030917	0	0
T1	1636	1562	0	0
T2	1951	1876	0	0
T3	3382	3310	0	0
T7	4246	3594	0	0
T13	23710	23640	0	0
T14	6246	6148	0	0
T15	3415	3357	0	0
T18	2946	2862	0	0
T19	485911	467871	0	0
T20	70358	70281	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	384864519	384030917	0	0
T1	1636	1562	0	0
T2	1951	1876	0	0
T3	3382	3310	0	0
T7	4246	3594	0	0
T13	23710	23640	0	0
T14	6246	6148	0	0
T15	3415	3357	0	0
T18	2946	2862	0	0
T19	485911	467871	0	0
T20	70358	70281	0	0