Module Definition
dashboard | hierarchy | modlist | groups | tests | asserts



Module Instance : tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.u_reg_top.u_reg_if.u_rsp_intg_gen

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
83.33 66.67 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
83.33 66.67 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
98.91 100.00 95.65 100.00 100.00 u_reg_if


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_reg_core.u_reg_if.u_rsp_intg_gen

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
90.00 80.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
96.43 92.86 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
97.96 100.00 91.84 100.00 100.00 u_reg_if


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_data_intg.u_tlul_data_integ_enc 100.00 100.00



Module Instance : tb.dut.u_to_prog_fifo.u_rsp_gen

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
91.67 83.33 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
91.67 83.33 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
83.96 100.00 65.52 85.71 84.62 u_to_prog_fifo


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_to_rd_fifo.u_rsp_gen

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
91.67 83.33 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
91.67 83.33 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
92.89 100.00 75.00 96.55 100.00 u_to_rd_fifo


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_reg_core.u_rsp_intg_gen

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.86 100.00 99.43 100.00 100.00 u_reg_core


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_rsp_intg.u_rsp_gen 100.00 100.00



Module Instance : tb.dut.u_reg_core.u_socket.gen_err_resp.err_resp.u_intg_gen

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
57.14 71.43 50.00 50.00 gen_err_resp.err_resp


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_data_intg.u_tlul_data_integ_enc 100.00 100.00
gen_rsp_intg.u_rsp_gen 100.00 100.00



Module Instance : tb.dut.u_prog_tl_gate.u_tlul_err_resp.u_intg_gen

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
96.67 100.00 90.00 100.00 u_tlul_err_resp


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_data_intg.u_tlul_data_integ_enc 100.00 100.00
gen_rsp_intg.u_rsp_gen 100.00 100.00



Module Instance : tb.dut.u_tl_gate.u_tlul_err_resp.u_intg_gen

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
84.44 100.00 70.00 83.33 u_tlul_err_resp


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_data_intg.u_tlul_data_integ_enc 100.00 100.00
gen_rsp_intg.u_rsp_gen 100.00 100.00



Module Instance : tb.dut.u_tl_adapter_eflash.u_rsp_gen

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
94.06 100.00 79.69 96.55 100.00 u_tl_adapter_eflash


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_rsp_intg.u_rsp_gen 100.00 100.00



Module Instance : tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.u_reg_top.u_rsp_intg_gen

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 100.00 u_reg_top


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_data_intg.u_tlul_data_integ_enc 100.00 100.00
gen_rsp_intg.u_rsp_gen 100.00 100.00

Line Coverage for Module : tlul_rsp_intg_gen ( parameter EnableRspIntgGen=1,EnableDataIntgGen=0 )
Line Coverage for Module self-instances :
SCORELINE
100.00 100.00
tb.dut.u_reg_core.u_rsp_intg_gen

SCORELINE
100.00 100.00
tb.dut.u_tl_adapter_eflash.u_rsp_gen

Line No.TotalCoveredPercent
TOTAL66100.00
CONT_ASSIGN2511100.00
CONT_ASSIGN4311100.00
ALWAYS4733100.00
CONT_ASSIGN5311100.00

24 25 1/1 assign rsp = extract_d2h_rsp_intg(tl_i); Tests: T1 T2 T3  26 27 prim_secded_inv_64_57_enc u_rsp_gen ( 28 .data_i(D2HRspMaxWidth'(rsp)), 29 .data_o({rsp_intg, unused_payload}) 30 ); 31 end else begin : gen_passthrough_rsp_intg 32 assign rsp_intg = tl_i.d_user.rsp_intg; 33 end 34 35 logic [DataIntgWidth-1:0] data_intg; 36 if (EnableDataIntgGen) begin : gen_data_intg 37 logic [DataMaxWidth-1:0] unused_data; 38 tlul_data_integ_enc u_tlul_data_integ_enc ( 39 .data_i(DataMaxWidth'(tl_i.d_data)), 40 .data_intg_o({data_intg, unused_data}) 41 ); 42 end else begin : gen_passthrough_data_intg 43 1/1 assign data_intg = tl_i.d_user.data_intg; Tests: T1 T2 T3  44 end 45 46 always_comb begin 47 1/1 tl_o = tl_i; Tests: T1 T2 T3  48 1/1 tl_o.d_user.rsp_intg = rsp_intg; Tests: T1 T2 T3  49 1/1 tl_o.d_user.data_intg = data_intg; Tests: T1 T2 T3  50 end 51 52 logic unused_tl; 53 1/1 assign unused_tl = ^tl_i; Tests: T1 T2 T3 

Line Coverage for Module : tlul_rsp_intg_gen ( parameter EnableRspIntgGen=0,EnableDataIntgGen=1 )
Line Coverage for Module self-instances :
SCORELINE
90.00 80.00
tb.dut.u_reg_core.u_reg_if.u_rsp_intg_gen

Line No.TotalCoveredPercent
TOTAL5480.00
CONT_ASSIGN32100.00
ALWAYS4733100.00
CONT_ASSIGN5311100.00

31 end else begin : gen_passthrough_rsp_intg 32 0/1 ==> assign rsp_intg = tl_i.d_user.rsp_intg; 33 end 34 35 logic [DataIntgWidth-1:0] data_intg; 36 if (EnableDataIntgGen) begin : gen_data_intg 37 logic [DataMaxWidth-1:0] unused_data; 38 tlul_data_integ_enc u_tlul_data_integ_enc ( 39 .data_i(DataMaxWidth'(tl_i.d_data)), 40 .data_intg_o({data_intg, unused_data}) 41 ); 42 end else begin : gen_passthrough_data_intg 43 assign data_intg = tl_i.d_user.data_intg; 44 end 45 46 always_comb begin 47 1/1 tl_o = tl_i; Tests: T1 T2 T3  48 1/1 tl_o.d_user.rsp_intg = rsp_intg; Tests: T1 T2 T3  49 1/1 tl_o.d_user.data_intg = data_intg; Tests: T1 T2 T3  50 end 51 52 logic unused_tl; 53 1/1 assign unused_tl = ^tl_i; Tests: T1 T2 T3 

Line Coverage for Module : tlul_rsp_intg_gen ( parameter EnableRspIntgGen=1,EnableDataIntgGen=1 )
Line Coverage for Module self-instances :
SCORELINE
100.00 100.00
tb.dut.u_reg_core.u_socket.gen_err_resp.err_resp.u_intg_gen

SCORELINE
100.00 100.00
tb.dut.u_prog_tl_gate.u_tlul_err_resp.u_intg_gen

SCORELINE
100.00 100.00
tb.dut.u_tl_gate.u_tlul_err_resp.u_intg_gen

SCORELINE
100.00 100.00
tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.u_reg_top.u_rsp_intg_gen

Line No.TotalCoveredPercent
TOTAL55100.00
CONT_ASSIGN2511100.00
ALWAYS4733100.00
CONT_ASSIGN5311100.00

24 25 1/1 assign rsp = extract_d2h_rsp_intg(tl_i); Tests: T1 T2 T3  26 27 prim_secded_inv_64_57_enc u_rsp_gen ( 28 .data_i(D2HRspMaxWidth'(rsp)), 29 .data_o({rsp_intg, unused_payload}) 30 ); 31 end else begin : gen_passthrough_rsp_intg 32 assign rsp_intg = tl_i.d_user.rsp_intg; 33 end 34 35 logic [DataIntgWidth-1:0] data_intg; 36 if (EnableDataIntgGen) begin : gen_data_intg 37 logic [DataMaxWidth-1:0] unused_data; 38 tlul_data_integ_enc u_tlul_data_integ_enc ( 39 .data_i(DataMaxWidth'(tl_i.d_data)), 40 .data_intg_o({data_intg, unused_data}) 41 ); 42 end else begin : gen_passthrough_data_intg 43 assign data_intg = tl_i.d_user.data_intg; 44 end 45 46 always_comb begin 47 1/1 tl_o = tl_i; Tests: T1 T2 T3  48 1/1 tl_o.d_user.rsp_intg = rsp_intg; Tests: T1 T2 T3  49 1/1 tl_o.d_user.data_intg = data_intg; Tests: T1 T2 T3  50 end 51 52 logic unused_tl; 53 1/1 assign unused_tl = ^tl_i; Tests: T1 T2 T3 

Line Coverage for Module : tlul_rsp_intg_gen ( parameter EnableRspIntgGen=0,EnableDataIntgGen=0 )
Line Coverage for Module self-instances :
SCORELINE
91.67 83.33
tb.dut.u_to_prog_fifo.u_rsp_gen

SCORELINE
91.67 83.33
tb.dut.u_to_rd_fifo.u_rsp_gen

SCORELINE
83.33 66.67
tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.u_reg_top.u_reg_if.u_rsp_intg_gen

Line No.TotalCoveredPercent
TOTAL6583.33
CONT_ASSIGN32100.00
CONT_ASSIGN4311100.00
ALWAYS4733100.00
CONT_ASSIGN5311100.00

31 end else begin : gen_passthrough_rsp_intg 32 0/1 ==> assign rsp_intg = tl_i.d_user.rsp_intg; 33 end 34 35 logic [DataIntgWidth-1:0] data_intg; 36 if (EnableDataIntgGen) begin : gen_data_intg 37 logic [DataMaxWidth-1:0] unused_data; 38 tlul_data_integ_enc u_tlul_data_integ_enc ( 39 .data_i(DataMaxWidth'(tl_i.d_data)), 40 .data_intg_o({data_intg, unused_data}) 41 ); 42 end else begin : gen_passthrough_data_intg 43 1/1 assign data_intg = tl_i.d_user.data_intg; Tests: T1 T2 T3  44 end 45 46 always_comb begin 47 1/1 tl_o = tl_i; Tests: T1 T2 T3  48 1/1 tl_o.d_user.rsp_intg = rsp_intg; Tests: T1 T2 T3  49 1/1 tl_o.d_user.data_intg = data_intg; Tests: T1 T2 T3  50 end 51 52 logic unused_tl; 53 1/1 assign unused_tl = ^tl_i; Tests: T1 T2 T3 

Assert Coverage for Module : tlul_rsp_intg_gen
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
DataWidthCheck_A 11495 11495 0 0
PayLoadWidthCheck 11495 11495 0 0


DataWidthCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 11495 11495 0 0
T1 10 10 0 0
T2 10 10 0 0
T3 10 10 0 0
T7 10 10 0 0
T13 10 10 0 0
T14 10 10 0 0
T15 10 10 0 0
T18 10 10 0 0
T19 10 10 0 0
T20 10 10 0 0

PayLoadWidthCheck
NameAttemptsReal SuccessesFailuresIncomplete
Total 11495 11495 0 0
T1 10 10 0 0
T2 10 10 0 0
T3 10 10 0 0
T7 10 10 0 0
T13 10 10 0 0
T14 10 10 0 0
T15 10 10 0 0
T18 10 10 0 0
T19 10 10 0 0
T20 10 10 0 0

Line Coverage for Instance : tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.u_reg_top.u_reg_if.u_rsp_intg_gen
Line No.TotalCoveredPercent
TOTAL6466.67
CONT_ASSIGN32100.00
CONT_ASSIGN43100.00
ALWAYS4733100.00
CONT_ASSIGN5311100.00

31 end else begin : gen_passthrough_rsp_intg 32 0/1 ==> assign rsp_intg = tl_i.d_user.rsp_intg; 33 end 34 35 logic [DataIntgWidth-1:0] data_intg; 36 if (EnableDataIntgGen) begin : gen_data_intg 37 logic [DataMaxWidth-1:0] unused_data; 38 tlul_data_integ_enc u_tlul_data_integ_enc ( 39 .data_i(DataMaxWidth'(tl_i.d_data)), 40 .data_intg_o({data_intg, unused_data}) 41 ); 42 end else begin : gen_passthrough_data_intg 43 0/1 ==> assign data_intg = tl_i.d_user.data_intg; 44 end 45 46 always_comb begin 47 1/1 tl_o = tl_i; Tests: T1 T2 T3  48 1/1 tl_o.d_user.rsp_intg = rsp_intg; Tests: T1 T2 T3  49 1/1 tl_o.d_user.data_intg = data_intg; Tests: T1 T2 T3  50 end 51 52 logic unused_tl; 53 1/1 assign unused_tl = ^tl_i; Tests: T1 T2 T3 

Assert Coverage for Instance : tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.u_reg_top.u_reg_if.u_rsp_intg_gen
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
DataWidthCheck_A 1257 1257 0 0
PayLoadWidthCheck 1257 1257 0 0


DataWidthCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1257 1257 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T7 1 1 0 0
T13 1 1 0 0
T14 1 1 0 0
T15 1 1 0 0
T18 1 1 0 0
T19 1 1 0 0
T20 1 1 0 0

PayLoadWidthCheck
NameAttemptsReal SuccessesFailuresIncomplete
Total 1257 1257 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T7 1 1 0 0
T13 1 1 0 0
T14 1 1 0 0
T15 1 1 0 0
T18 1 1 0 0
T19 1 1 0 0
T20 1 1 0 0

Line Coverage for Instance : tb.dut.u_reg_core.u_reg_if.u_rsp_intg_gen
Line No.TotalCoveredPercent
TOTAL5480.00
CONT_ASSIGN32100.00
ALWAYS4733100.00
CONT_ASSIGN5311100.00

31 end else begin : gen_passthrough_rsp_intg 32 0/1 ==> assign rsp_intg = tl_i.d_user.rsp_intg; 33 end 34 35 logic [DataIntgWidth-1:0] data_intg; 36 if (EnableDataIntgGen) begin : gen_data_intg 37 logic [DataMaxWidth-1:0] unused_data; 38 tlul_data_integ_enc u_tlul_data_integ_enc ( 39 .data_i(DataMaxWidth'(tl_i.d_data)), 40 .data_intg_o({data_intg, unused_data}) 41 ); 42 end else begin : gen_passthrough_data_intg 43 assign data_intg = tl_i.d_user.data_intg; 44 end 45 46 always_comb begin 47 1/1 tl_o = tl_i; Tests: T1 T2 T3  48 1/1 tl_o.d_user.rsp_intg = rsp_intg; Tests: T1 T2 T3  49 1/1 tl_o.d_user.data_intg = data_intg; Tests: T1 T2 T3  50 end 51 52 logic unused_tl; 53 1/1 assign unused_tl = ^tl_i; Tests: T1 T2 T3 

Assert Coverage for Instance : tb.dut.u_reg_core.u_reg_if.u_rsp_intg_gen
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
DataWidthCheck_A 1257 1257 0 0
PayLoadWidthCheck 1257 1257 0 0


DataWidthCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1257 1257 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T7 1 1 0 0
T13 1 1 0 0
T14 1 1 0 0
T15 1 1 0 0
T18 1 1 0 0
T19 1 1 0 0
T20 1 1 0 0

PayLoadWidthCheck
NameAttemptsReal SuccessesFailuresIncomplete
Total 1257 1257 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T7 1 1 0 0
T13 1 1 0 0
T14 1 1 0 0
T15 1 1 0 0
T18 1 1 0 0
T19 1 1 0 0
T20 1 1 0 0

Line Coverage for Instance : tb.dut.u_to_prog_fifo.u_rsp_gen
Line No.TotalCoveredPercent
TOTAL6583.33
CONT_ASSIGN32100.00
CONT_ASSIGN4311100.00
ALWAYS4733100.00
CONT_ASSIGN5311100.00

31 end else begin : gen_passthrough_rsp_intg 32 0/1 ==> assign rsp_intg = tl_i.d_user.rsp_intg; 33 end 34 35 logic [DataIntgWidth-1:0] data_intg; 36 if (EnableDataIntgGen) begin : gen_data_intg 37 logic [DataMaxWidth-1:0] unused_data; 38 tlul_data_integ_enc u_tlul_data_integ_enc ( 39 .data_i(DataMaxWidth'(tl_i.d_data)), 40 .data_intg_o({data_intg, unused_data}) 41 ); 42 end else begin : gen_passthrough_data_intg 43 1/1 assign data_intg = tl_i.d_user.data_intg; Tests: T1 T2 T3  44 end 45 46 always_comb begin 47 1/1 tl_o = tl_i; Tests: T1 T2 T3  48 1/1 tl_o.d_user.rsp_intg = rsp_intg; Tests: T1 T2 T3  49 1/1 tl_o.d_user.data_intg = data_intg; Tests: T1 T2 T3  50 end 51 52 logic unused_tl; 53 1/1 assign unused_tl = ^tl_i; Tests: T1 T2 T3 

Assert Coverage for Instance : tb.dut.u_to_prog_fifo.u_rsp_gen
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
DataWidthCheck_A 1042 1042 0 0
PayLoadWidthCheck 1042 1042 0 0


DataWidthCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1042 1042 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T7 1 1 0 0
T13 1 1 0 0
T14 1 1 0 0
T15 1 1 0 0
T18 1 1 0 0
T19 1 1 0 0
T20 1 1 0 0

PayLoadWidthCheck
NameAttemptsReal SuccessesFailuresIncomplete
Total 1042 1042 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T7 1 1 0 0
T13 1 1 0 0
T14 1 1 0 0
T15 1 1 0 0
T18 1 1 0 0
T19 1 1 0 0
T20 1 1 0 0

Line Coverage for Instance : tb.dut.u_to_rd_fifo.u_rsp_gen
Line No.TotalCoveredPercent
TOTAL6583.33
CONT_ASSIGN32100.00
CONT_ASSIGN4311100.00
ALWAYS4733100.00
CONT_ASSIGN5311100.00

31 end else begin : gen_passthrough_rsp_intg 32 0/1 ==> assign rsp_intg = tl_i.d_user.rsp_intg; 33 end 34 35 logic [DataIntgWidth-1:0] data_intg; 36 if (EnableDataIntgGen) begin : gen_data_intg 37 logic [DataMaxWidth-1:0] unused_data; 38 tlul_data_integ_enc u_tlul_data_integ_enc ( 39 .data_i(DataMaxWidth'(tl_i.d_data)), 40 .data_intg_o({data_intg, unused_data}) 41 ); 42 end else begin : gen_passthrough_data_intg 43 1/1 assign data_intg = tl_i.d_user.data_intg; Tests: T1 T2 T3  44 end 45 46 always_comb begin 47 1/1 tl_o = tl_i; Tests: T1 T2 T3  48 1/1 tl_o.d_user.rsp_intg = rsp_intg; Tests: T1 T2 T3  49 1/1 tl_o.d_user.data_intg = data_intg; Tests: T1 T2 T3  50 end 51 52 logic unused_tl; 53 1/1 assign unused_tl = ^tl_i; Tests: T1 T2 T3 

Assert Coverage for Instance : tb.dut.u_to_rd_fifo.u_rsp_gen
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
DataWidthCheck_A 1042 1042 0 0
PayLoadWidthCheck 1042 1042 0 0


DataWidthCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1042 1042 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T7 1 1 0 0
T13 1 1 0 0
T14 1 1 0 0
T15 1 1 0 0
T18 1 1 0 0
T19 1 1 0 0
T20 1 1 0 0

PayLoadWidthCheck
NameAttemptsReal SuccessesFailuresIncomplete
Total 1042 1042 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T7 1 1 0 0
T13 1 1 0 0
T14 1 1 0 0
T15 1 1 0 0
T18 1 1 0 0
T19 1 1 0 0
T20 1 1 0 0

Line Coverage for Instance : tb.dut.u_reg_core.u_rsp_intg_gen
Line No.TotalCoveredPercent
TOTAL66100.00
CONT_ASSIGN2511100.00
CONT_ASSIGN4311100.00
ALWAYS4733100.00
CONT_ASSIGN5311100.00

24 25 1/1 assign rsp = extract_d2h_rsp_intg(tl_i); Tests: T1 T2 T3  26 27 prim_secded_inv_64_57_enc u_rsp_gen ( 28 .data_i(D2HRspMaxWidth'(rsp)), 29 .data_o({rsp_intg, unused_payload}) 30 ); 31 end else begin : gen_passthrough_rsp_intg 32 assign rsp_intg = tl_i.d_user.rsp_intg; 33 end 34 35 logic [DataIntgWidth-1:0] data_intg; 36 if (EnableDataIntgGen) begin : gen_data_intg 37 logic [DataMaxWidth-1:0] unused_data; 38 tlul_data_integ_enc u_tlul_data_integ_enc ( 39 .data_i(DataMaxWidth'(tl_i.d_data)), 40 .data_intg_o({data_intg, unused_data}) 41 ); 42 end else begin : gen_passthrough_data_intg 43 1/1 assign data_intg = tl_i.d_user.data_intg; Tests: T1 T2 T3  44 end 45 46 always_comb begin 47 1/1 tl_o = tl_i; Tests: T1 T2 T3  48 1/1 tl_o.d_user.rsp_intg = rsp_intg; Tests: T1 T2 T3  49 1/1 tl_o.d_user.data_intg = data_intg; Tests: T1 T2 T3  50 end 51 52 logic unused_tl; 53 1/1 assign unused_tl = ^tl_i; Tests: T1 T2 T3 

Assert Coverage for Instance : tb.dut.u_reg_core.u_rsp_intg_gen
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
DataWidthCheck_A 1257 1257 0 0
PayLoadWidthCheck 1257 1257 0 0


DataWidthCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1257 1257 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T7 1 1 0 0
T13 1 1 0 0
T14 1 1 0 0
T15 1 1 0 0
T18 1 1 0 0
T19 1 1 0 0
T20 1 1 0 0

PayLoadWidthCheck
NameAttemptsReal SuccessesFailuresIncomplete
Total 1257 1257 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T7 1 1 0 0
T13 1 1 0 0
T14 1 1 0 0
T15 1 1 0 0
T18 1 1 0 0
T19 1 1 0 0
T20 1 1 0 0

Line Coverage for Instance : tb.dut.u_reg_core.u_socket.gen_err_resp.err_resp.u_intg_gen
Line No.TotalCoveredPercent
TOTAL55100.00
CONT_ASSIGN2511100.00
ALWAYS4733100.00
CONT_ASSIGN5311100.00

24 25 1/1 assign rsp = extract_d2h_rsp_intg(tl_i); Tests: T1 T2 T3  26 27 prim_secded_inv_64_57_enc u_rsp_gen ( 28 .data_i(D2HRspMaxWidth'(rsp)), 29 .data_o({rsp_intg, unused_payload}) 30 ); 31 end else begin : gen_passthrough_rsp_intg 32 assign rsp_intg = tl_i.d_user.rsp_intg; 33 end 34 35 logic [DataIntgWidth-1:0] data_intg; 36 if (EnableDataIntgGen) begin : gen_data_intg 37 logic [DataMaxWidth-1:0] unused_data; 38 tlul_data_integ_enc u_tlul_data_integ_enc ( 39 .data_i(DataMaxWidth'(tl_i.d_data)), 40 .data_intg_o({data_intg, unused_data}) 41 ); 42 end else begin : gen_passthrough_data_intg 43 assign data_intg = tl_i.d_user.data_intg; 44 end 45 46 always_comb begin 47 1/1 tl_o = tl_i; Tests: T1 T2 T3  48 1/1 tl_o.d_user.rsp_intg = rsp_intg; Tests: T1 T2 T3  49 1/1 tl_o.d_user.data_intg = data_intg; Tests: T1 T2 T3  50 end 51 52 logic unused_tl; 53 1/1 assign unused_tl = ^tl_i; Tests: T1 T2 T3 

Assert Coverage for Instance : tb.dut.u_reg_core.u_socket.gen_err_resp.err_resp.u_intg_gen
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
DataWidthCheck_A 1257 1257 0 0
PayLoadWidthCheck 1257 1257 0 0


DataWidthCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1257 1257 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T7 1 1 0 0
T13 1 1 0 0
T14 1 1 0 0
T15 1 1 0 0
T18 1 1 0 0
T19 1 1 0 0
T20 1 1 0 0

PayLoadWidthCheck
NameAttemptsReal SuccessesFailuresIncomplete
Total 1257 1257 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T7 1 1 0 0
T13 1 1 0 0
T14 1 1 0 0
T15 1 1 0 0
T18 1 1 0 0
T19 1 1 0 0
T20 1 1 0 0

Line Coverage for Instance : tb.dut.u_prog_tl_gate.u_tlul_err_resp.u_intg_gen
Line No.TotalCoveredPercent
TOTAL55100.00
CONT_ASSIGN2511100.00
ALWAYS4733100.00
CONT_ASSIGN5311100.00

24 25 1/1 assign rsp = extract_d2h_rsp_intg(tl_i); Tests: T1 T2 T3  26 27 prim_secded_inv_64_57_enc u_rsp_gen ( 28 .data_i(D2HRspMaxWidth'(rsp)), 29 .data_o({rsp_intg, unused_payload}) 30 ); 31 end else begin : gen_passthrough_rsp_intg 32 assign rsp_intg = tl_i.d_user.rsp_intg; 33 end 34 35 logic [DataIntgWidth-1:0] data_intg; 36 if (EnableDataIntgGen) begin : gen_data_intg 37 logic [DataMaxWidth-1:0] unused_data; 38 tlul_data_integ_enc u_tlul_data_integ_enc ( 39 .data_i(DataMaxWidth'(tl_i.d_data)), 40 .data_intg_o({data_intg, unused_data}) 41 ); 42 end else begin : gen_passthrough_data_intg 43 assign data_intg = tl_i.d_user.data_intg; 44 end 45 46 always_comb begin 47 1/1 tl_o = tl_i; Tests: T1 T2 T3  48 1/1 tl_o.d_user.rsp_intg = rsp_intg; Tests: T1 T2 T3  49 1/1 tl_o.d_user.data_intg = data_intg; Tests: T1 T2 T3  50 end 51 52 logic unused_tl; 53 1/1 assign unused_tl = ^tl_i; Tests: T1 T2 T3 

Assert Coverage for Instance : tb.dut.u_prog_tl_gate.u_tlul_err_resp.u_intg_gen
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
DataWidthCheck_A 1042 1042 0 0
PayLoadWidthCheck 1042 1042 0 0


DataWidthCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1042 1042 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T7 1 1 0 0
T13 1 1 0 0
T14 1 1 0 0
T15 1 1 0 0
T18 1 1 0 0
T19 1 1 0 0
T20 1 1 0 0

PayLoadWidthCheck
NameAttemptsReal SuccessesFailuresIncomplete
Total 1042 1042 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T7 1 1 0 0
T13 1 1 0 0
T14 1 1 0 0
T15 1 1 0 0
T18 1 1 0 0
T19 1 1 0 0
T20 1 1 0 0

Line Coverage for Instance : tb.dut.u_tl_gate.u_tlul_err_resp.u_intg_gen
Line No.TotalCoveredPercent
TOTAL55100.00
CONT_ASSIGN2511100.00
ALWAYS4733100.00
CONT_ASSIGN5311100.00

24 25 1/1 assign rsp = extract_d2h_rsp_intg(tl_i); Tests: T1 T2 T3  26 27 prim_secded_inv_64_57_enc u_rsp_gen ( 28 .data_i(D2HRspMaxWidth'(rsp)), 29 .data_o({rsp_intg, unused_payload}) 30 ); 31 end else begin : gen_passthrough_rsp_intg 32 assign rsp_intg = tl_i.d_user.rsp_intg; 33 end 34 35 logic [DataIntgWidth-1:0] data_intg; 36 if (EnableDataIntgGen) begin : gen_data_intg 37 logic [DataMaxWidth-1:0] unused_data; 38 tlul_data_integ_enc u_tlul_data_integ_enc ( 39 .data_i(DataMaxWidth'(tl_i.d_data)), 40 .data_intg_o({data_intg, unused_data}) 41 ); 42 end else begin : gen_passthrough_data_intg 43 assign data_intg = tl_i.d_user.data_intg; 44 end 45 46 always_comb begin 47 1/1 tl_o = tl_i; Tests: T1 T2 T3  48 1/1 tl_o.d_user.rsp_intg = rsp_intg; Tests: T1 T2 T3  49 1/1 tl_o.d_user.data_intg = data_intg; Tests: T1 T2 T3  50 end 51 52 logic unused_tl; 53 1/1 assign unused_tl = ^tl_i; Tests: T1 T2 T3 

Assert Coverage for Instance : tb.dut.u_tl_gate.u_tlul_err_resp.u_intg_gen
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
DataWidthCheck_A 1042 1042 0 0
PayLoadWidthCheck 1042 1042 0 0


DataWidthCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1042 1042 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T7 1 1 0 0
T13 1 1 0 0
T14 1 1 0 0
T15 1 1 0 0
T18 1 1 0 0
T19 1 1 0 0
T20 1 1 0 0

PayLoadWidthCheck
NameAttemptsReal SuccessesFailuresIncomplete
Total 1042 1042 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T7 1 1 0 0
T13 1 1 0 0
T14 1 1 0 0
T15 1 1 0 0
T18 1 1 0 0
T19 1 1 0 0
T20 1 1 0 0

Line Coverage for Instance : tb.dut.u_tl_adapter_eflash.u_rsp_gen
Line No.TotalCoveredPercent
TOTAL66100.00
CONT_ASSIGN2511100.00
CONT_ASSIGN4311100.00
ALWAYS4733100.00
CONT_ASSIGN5311100.00

24 25 1/1 assign rsp = extract_d2h_rsp_intg(tl_i); Tests: T1 T2 T3  26 27 prim_secded_inv_64_57_enc u_rsp_gen ( 28 .data_i(D2HRspMaxWidth'(rsp)), 29 .data_o({rsp_intg, unused_payload}) 30 ); 31 end else begin : gen_passthrough_rsp_intg 32 assign rsp_intg = tl_i.d_user.rsp_intg; 33 end 34 35 logic [DataIntgWidth-1:0] data_intg; 36 if (EnableDataIntgGen) begin : gen_data_intg 37 logic [DataMaxWidth-1:0] unused_data; 38 tlul_data_integ_enc u_tlul_data_integ_enc ( 39 .data_i(DataMaxWidth'(tl_i.d_data)), 40 .data_intg_o({data_intg, unused_data}) 41 ); 42 end else begin : gen_passthrough_data_intg 43 1/1 assign data_intg = tl_i.d_user.data_intg; Tests: T1 T2 T3  44 end 45 46 always_comb begin 47 1/1 tl_o = tl_i; Tests: T1 T2 T3  48 1/1 tl_o.d_user.rsp_intg = rsp_intg; Tests: T1 T2 T3  49 1/1 tl_o.d_user.data_intg = data_intg; Tests: T1 T2 T3  50 end 51 52 logic unused_tl; 53 1/1 assign unused_tl = ^tl_i; Tests: T1 T2 T3 

Assert Coverage for Instance : tb.dut.u_tl_adapter_eflash.u_rsp_gen
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
DataWidthCheck_A 1042 1042 0 0
PayLoadWidthCheck 1042 1042 0 0


DataWidthCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1042 1042 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T7 1 1 0 0
T13 1 1 0 0
T14 1 1 0 0
T15 1 1 0 0
T18 1 1 0 0
T19 1 1 0 0
T20 1 1 0 0

PayLoadWidthCheck
NameAttemptsReal SuccessesFailuresIncomplete
Total 1042 1042 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T7 1 1 0 0
T13 1 1 0 0
T14 1 1 0 0
T15 1 1 0 0
T18 1 1 0 0
T19 1 1 0 0
T20 1 1 0 0

Line Coverage for Instance : tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.u_reg_top.u_rsp_intg_gen
Line No.TotalCoveredPercent
TOTAL55100.00
CONT_ASSIGN2511100.00
ALWAYS4733100.00
CONT_ASSIGN5311100.00

24 25 1/1 assign rsp = extract_d2h_rsp_intg(tl_i); Tests: T1 T2 T3  26 27 prim_secded_inv_64_57_enc u_rsp_gen ( 28 .data_i(D2HRspMaxWidth'(rsp)), 29 .data_o({rsp_intg, unused_payload}) 30 ); 31 end else begin : gen_passthrough_rsp_intg 32 assign rsp_intg = tl_i.d_user.rsp_intg; 33 end 34 35 logic [DataIntgWidth-1:0] data_intg; 36 if (EnableDataIntgGen) begin : gen_data_intg 37 logic [DataMaxWidth-1:0] unused_data; 38 tlul_data_integ_enc u_tlul_data_integ_enc ( 39 .data_i(DataMaxWidth'(tl_i.d_data)), 40 .data_intg_o({data_intg, unused_data}) 41 ); 42 end else begin : gen_passthrough_data_intg 43 assign data_intg = tl_i.d_user.data_intg; 44 end 45 46 always_comb begin 47 1/1 tl_o = tl_i; Tests: T1 T2 T3  48 1/1 tl_o.d_user.rsp_intg = rsp_intg; Tests: T1 T2 T3  49 1/1 tl_o.d_user.data_intg = data_intg; Tests: T1 T2 T3  50 end 51 52 logic unused_tl; 53 1/1 assign unused_tl = ^tl_i; Tests: T1 T2 T3 

Assert Coverage for Instance : tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.u_reg_top.u_rsp_intg_gen
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
DataWidthCheck_A 1257 1257 0 0
PayLoadWidthCheck 1257 1257 0 0


DataWidthCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1257 1257 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T7 1 1 0 0
T13 1 1 0 0
T14 1 1 0 0
T15 1 1 0 0
T18 1 1 0 0
T19 1 1 0 0
T20 1 1 0 0

PayLoadWidthCheck
NameAttemptsReal SuccessesFailuresIncomplete
Total 1257 1257 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T7 1 1 0 0
T13 1 1 0 0
T14 1 1 0 0
T15 1 1 0 0
T18 1 1 0 0
T19 1 1 0 0
T20 1 1 0 0

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%